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11862430 | DETAILED DESCRIPTION Example embodiments provide a pattern formation method and a template manufacturing method for facilitating formation of a line-and-space pattern using a side wall transfer process. In general, according to one embodiment, a pattern formation method placing an imprint resist film on a substrate, then imprinting a pattern in the imprint resist film. The pattern has a first loop section in a first end portion and a second loop section in a second end portion corresponding to, for example, a side wall pattern doubling transfer process. The patterned imprint resist film is then selectively irradiated in a portion between the first loop section and the second loop section. The imprint resist film is then etched under conditions leaving the selectively irradiated portion of the imprint resist film and removing the unirradiated portion of the imprint resist. Certain example embodiments of the present disclosure will be described with reference to the accompanying drawings. In the drawings, the same or substantially similar aspects are denoted by same reference symbols. However, the drawings are schematic and depicted relationships between thicknesses and plane dimensions and the like generally differ from actual relationships. A template according to an embodiment will first be described with reference toFIGS.1A and1B.FIG.1Ais a plan view of a template1viewed from a Z direction.FIG.1Bis a cross-sectional view of the template1taken along AA′ ofFIG.1Aand viewed from an X direction. The template1has a substrate21that has a quadrilateral shape in a view from the Z direction. In a case of nanoimprint lithography using photo-curing, the template1comprises, for example, quartz or other transparent material. A mesa structure23projecting from a principal surface22of the substrate21is provided at a center of the principal surface22. The mesa structure23has a pattern surface24on an upward facing surface thereof. A recess structure (topographic) pattern incorporating a transfer pattern (the pattern to be transferred in the imprint lithography process) and an alignment mark is formed on the pattern surface24. The transfer pattern formed on the pattern surface24includes a fine line-and-space pattern at, several tens of nanometer (nm) half pitch (hp). Such a fine pattern is generally difficult to directly form by exposing the corresponding pattern in a photoresist using photolithography or the like in a single exposure step and thus more complicated methods are often adopted. A template manufacturing method according to the present disclosure will be described with reference toFIGS.2A to6D.FIGS.2A to4Bshow aspects of a pattern formation method according to an embodiment.FIGS.5A and5Bdepict an example of a mold template used in the embodiment.FIGS.2A,3A,4A, and5Aare plan views viewed from the Z direction.FIGS.2B,3B,4B, and5Bare cross-sectional views taken along AA′ ofFIGS.2A,3A,4A, and5A and viewed from the X direction.FIGS.6A to6Dshow aspects of the template manufacturing method according to the present disclosure. As depicted inFIG.2A, a hard mask film12is first formed on the substrate21. The substrate21comprises, for example, quartz. The hard mask film12comprises, for example, chromium. Next, a resist film13is formed on the hard mask film12. The resist film13may be formed, for example, by coating a resist material on the hard mask film12using a spin coating method and then baking the resist. Examples of the resist material include an ultraviolet curable resist. Next, a pattern is transferred into the resist. In the present embodiment, a mold template2(shown inFIGS.5A and5B), with a pattern having a raised loop structure that may be formed by a side wall transfer process or the like can be used. The mold template2comprises, for example, quartz (or other transparent material) in the case of the nanoimprint lithography using photo-curing. In this context, a side wall transfer process as used herein refers to a process of forming a resist pattern by lithography, subsequently forming another film on the resist pattern, performing etching to form a pattern on a side wall of the resist pattern, and then transferring the formed pattern into a hard mask film. Using the side wall transfer process makes it possible to form a fine line-and-space shape although a loop structure is initially present. The side wall transfer process may also be referred to in some instances as side wall pattern doubling process or the like. In this present example, an imprint process using the mold template2is performed to pattern the resist film13, and the pattern having a recessed loop structure as shown inFIGS.2A and2Bis thereby formed in the resist film2. As shown inFIG.2A, the formed pattern has a first loop section14at a first end portion and a second loop section15at a second end portion. The pattern has line parts that are present between the first loop section14and the second loop section15. The line parts couple the first loop section14to the second loop section15, and that extend in the X direction. Next, as shown inFIG.3B, radiation17is applied to the resist film13within a region16between the first loop section14and the second loop section15. The radiation17is, for example, an electron beam. The electron beam can be applied to the resist film13at an acceleration voltage of 0.7 kV and a total amount of irradiation is 2038.4 μC/cm2. It is noted that the region16is not necessarily limited to the region shown inFIGS.3A and3Band may be set to any desired location between the first loop section14and the second loop section15. Furthermore, the region16may include interconnections features, circuit element patterns, an alignment mark, and the like formed in the resist film13in regions outside the first loop section14and the second loop section15. Applying the radiation17to the resist film13provides a reduction in free volume of the resist film13, and an improvement in etch resistance of the resist film13as compared with a resist film13to which the radiation17is not applied. Next, the resist film13is etched. At this time, since the resist film13in the region16has improved etch resistance due to application of the radiation17, the resist film13in the region16can remain while the resist film13outside of the region16is removed, as shown inFIGS.4A and4B. In this way, a desired mask pattern28(seeFIG.6A) from which the first loop section14and the second loop section15are removed can be formed. It is, therefore, possible to form a line-and-space pattern without the loop shape in the end portions. FIG.6Ashows a state after the etching shown inFIGS.4A and4B. Next, as shown inFIG.6B, the hard mask film12is etched using the mask pattern28formed of the resist film13as a mask. The mask pattern28is thereby transferred into the hard mask film12. Next, as shown inFIG.6C, the substrate21is etched using the now-patterned hard mask film12as a mask. Next, as shown inFIG.6D, the hard mask film12is removed (stripped). The hard mask film12can be removed by wet etching or dry etching. In this way, the template1according to the present embodiment is manufactured. The template manufacturing method according to the present embodiment is capable of facilitating forming the desired mask pattern28from which the first loop section14and the second loop section15have been removed by applying the radiation17to the resist film13in the region16. In addition, the template manufacturing method according to the present embodiment is capable of achieving a reduction in the number of processes because there is no need to provide a mask for removing the first loop section14and the second loop section15. Additionally, the template manufacturing method according to the present embodiment is capable of achieving an improvement in yield because of the reduction in the number of processes such as forming and removing the mask for loop section removal or the like. While certain embodiments have been described, these embodiments have been presented by way of example only, and are not intended to limit the scope of the disclosure. Indeed, the novel embodiments described herein may be embodied in a variety of other forms; furthermore, various omissions, substitutions and changes in the form of the embodiments described herein may be made without departing from the spirit of the disclosure. The accompanying claims and their equivalents are intended to cover such forms or modifications as would fall within the scope and spirit of the disclosure. | 8,547 |
11862431 | DESCRIPTION OF THE EMBODIMENTS Hereinafter, a plasma control system of one embodiment according to the disclosure will be described with reference to the drawings. <System Configuration> As shown inFIG.1, a plasma control system200of the present embodiment includes at least a plasma treatment device100that processes a substrate using inductively coupled plasma and a control device X for controlling the plasma. First, the plasma treatment device100will be described. As shown inFIG.2, for example, the plasma treatment device100applies a treatment such as film formation by a plasma CVD method, etching, ashing, or sputtering on a substrate W. The substrate W is, for example, a substrate for a flat panel display (FPD) such as a liquid crystal display or an organic EL display, or a flexible substrate for a flexible display. Here, the plasma treatment device100is also called a plasma CVD device when film formation is performed by a plasma CVD method, a plasma etching device when etching is performed, a plasma ashing device when ashing is performed, and a plasma sputtering device when sputtering is performed. Specifically, the plasma treatment device100includes a vacuum container2which is vacuum-exhausted and a gas G is introduced, a long antenna3disposed in the vacuum container2, and a high-frequency power supply4that applies a high frequency to the antenna3in order to generate inductively coupled plasma P in the vacuum container2. Here, by applying a high frequency from the high-frequency power supply4to the antenna3, a high-frequency current IR flows through the antenna3, an inductive electric field is generated in the vacuum container2, and inductively coupled plasma P is generated. The vacuum container2is, for example, a metal container, and the inside thereof is vacuum-exhausted by a vacuum exhaust device5. In this example, the vacuum container2is electrically grounded. For example, a gas G is introduced into the vacuum container2via a flow rate adjusting container (not shown) and a gas introduction port21formed on the side wall of the vacuum container2. The gas G may be set according to the details of treatments performed on the substrate W. In addition, a substrate holder6for holding the substrate W is provided in the vacuum container2. As in this example, a bias voltage may be applied to the substrate holder6from a bias power supply7. The bias voltage is, for example, a negative DC voltage or a negative pulse voltage, but the disclosure is not limited thereto. With such a bias voltage, for example, the energy when positive ions in the plasma P enter the substrate W can be controlled, and the degree of crystallization of a film formed on the surface of the substrate W and the like can be controlled. A heater61for heating the substrate W may be provided in the substrate holder6. Here, the antenna3has a linear shape, and is disposed above the substrate W in the vacuum container2and along the surface of the substrate W (for example, substantially parallel to the surface of the substrate W). The vicinity of both ends of the antenna3penetrates the side walls of the vacuum container2facing each other. Each insulation member8is provided at a part that penetrates both ends of the antenna3to the outside of the vacuum container2. Both ends of the antenna3penetrate each insulation member8and the penetrating part is vacuum-sealed by, for example, packing91. The space between each insulation member8and the vacuum container2is also vacuum-sealed by, for example, packing92. Here, the material of the insulation member8is, for example, a ceramic such as alumina, quartz, or engineering plastic such as polyphenylene sulfide (PPS) or polyether ether ketone (PEEK). In addition, in the antenna3, the part positioned inside the vacuum container2is covered with a straight tubular insulation cover10. Both ends of the insulation cover10are supported by the insulation member8. Here, the material of the insulation cover10is, for example, quartz, alumina, fluororesin, silicon nitride, silicon carbide, or silicon. Here, the plurality of antennas3have a hollow structure having a flow path3S through which a liquid coolant CL flow therein. In the present embodiment, they are a metal pipe forming a straight tube. The material of the metal pipe is, for example, copper, aluminum, alloys thereof, or stainless steel. Here, the liquid coolant CL flows through the antenna3via a circulation flow path11provided outside the vacuum container2, and at the circulation flow path11, a temperature control mechanism111such as a heat exchanger for adjusting the temperature of the liquid coolant CL to be constant, and a circulation mechanism112such as a pump for circulating the liquid coolant CL through the circulation flow path11are provided. As the liquid coolant CL, in consideration of electrical insulation, water having high resistance is preferable, and for example, pure water or water close thereto is preferable. In addition, for example, a liquid coolant other than water such as a fluorine-based inactive liquid may be used. As shown inFIG.1andFIG.3, the plurality of above antennas3are provided. That is, the plasma treatment device100of the present embodiment includes an antenna group3xcomposed of a plurality of antennas connected to the high-frequency power supply4. The antenna group3xis formed by connecting a plurality of sets of at least two antennas3connected in series in parallel, and here, it is composed of a total of six antennas3obtained by connecting three sets of two antennas connected in series in parallel. In the following, for convenience of description, three sets of a first antenna3A and a second antenna3B, a third antenna3C and a fourth antenna3D, and a fifth antenna3E and a sixth antenna3F, which are connected in series, are connected in parallel. As shown inFIG.3, the plurality of antennas3connected in series are connected by a connecting conductor12to form one antenna structure. That is, the ends of the antennas3adjacent to each other extending to the outside of the vacuum container2are electrically connected by the connecting conductor12. More specifically, in the present embodiment, two antennas3are connected by the connecting conductor12, and the end of one antenna3and the end of the other antenna3are electrically connected. In the following, the connecting conductor12that connects the first antenna3A and the second antenna3B will be described, but the connecting conductor that connects the third antenna3C and the fourth antenna3D, and the connecting conductor that connects the fifth antenna3E and the sixth antenna3F have the same configuration. The ends of the first antenna3A and the second antenna3B connected by the connecting conductor12are the ends positioned on the same side wall side. Thereby, the high-frequency currents IR in opposite directions flow through the first antenna3A and the second antenna3B. Here, the connecting conductor12has a flow path therein, and has a configuration in which the liquid coolant CL flows through the flow path. Specifically, one end of the connecting conductor12communicates with the flow path of the first antenna3A, and the other end of the connecting conductor12communicates with the flow path of the second antenna3B. Thereby, in the antennas3A and3B adjacent to each other, the liquid coolant CL that has flowed through the first antenna3A flows through the second antenna3B via the flow path of the connecting conductor12. Thereby, the plurality of antennas3can be cooled with the common liquid coolant CL. In addition, since the plurality of antennas3can be cooled through one flow path, the configuration of the circulation flow path11can be simplified. One end (here, one end of the first antenna3A) of the antennas3A and3B that is not connected by the connecting conductor12becomes a feeding side end3a1, and the high-frequency power supply4is connected to the feeding side end3a1via a matching circuit41. In addition, a terminal part3b2, which is the other end (here, the other end of the second antenna3B), is grounded. With the above configuration, the high-frequency current IR can flow from the high-frequency power supply4to the antenna3via the matching circuit41. The frequency of the high frequency is, for example, generally, 13.56 MHz, but the disclosure is not limited thereto. <Configuration of Connecting Conductor12> Next, the connecting conductor12will be described in detail with reference toFIG.4toFIG.8. Here, inFIG.4andFIG.5, some sealing members and the like are omitted. As shown inFIG.4andFIG.5, the connecting conductor12includes a variable capacitor VC electrically connected to each of the antennas3A and3B, a first connecting part14that connects the variable capacitor VC and the other end3a2of the first antenna3A, and a second connecting part15that connects the variable capacitor VC and one end3b1of the second antenna3B. The first connecting part14electrically contacts the antenna3A by surrounding the other end3a2of the first antenna3A, and guides the liquid coolant CL to the variable capacitor VC from an opening3H formed at the other end3a2of the antenna3A. The second connecting part15electrically contacts the antenna3B by surrounding the one end3b1of the second antenna3B and guides the liquid coolant CL that has passed through the variable capacitor VC to the opening3H formed at the one end3b1of the antenna3B. The material of these connecting parts14and15is, for example, copper, aluminum, alloys thereof, or stainless steel. Each of the connecting parts14and15of the present embodiment is liquid-tightly mounted at the end of the antenna3via a sealing member Sa such as an O-ring on the side of the vacuum container2with respect to the opening3H, and is configured not to restrain the outside of the opening3H (refer toFIG.4). Thereby, it has a configuration that allows a light inclination of the antenna3with respect to the connecting parts14and15. The variable capacitor VC includes a first fixed electrode16electrically connected to the first antenna3A, a second fixed electrode17electrically connected to the second antenna3B, and a movable electrode18, which is a movable element that forms a first capacitor between it and the first fixed electrode16and forms a second capacitor between it and the second fixed electrode17. The variable capacitor VC of the present embodiment has a configuration in which the movable electrode18can rotate around a predetermined rotation axis C and the capacitance thereof can be changed. Here, the variable capacitor VC includes an insulating storage container19in which the first fixed electrode16, the second fixed electrode17and the movable electrode18are accommodated. The storage container19has an introduction port P1through which the liquid coolant CL is introduced from the first antenna3A and an introduction port P2through which a liquid coolant CL is introduced to the second antenna3B. The introduction port P1is formed on one side wall (the left side wall inFIG.4) of a storage container19, the introduction port P2is formed on the other side wall (the right side wall inFIG.4) of the storage container19, and the introduction port P1and the introduction port P2are provided at positions facing each other. Here, the storage container19of the present embodiment has a substantially rectangular parallelepiped shape having a hollow portion therein, but it may have other shapes. The first fixed electrode16and the second fixed electrode17are provided at different positions around the rotation axis C of the movable electrode18. In the present embodiment, the first fixed electrode16that is inserted into the storage container19from the introduction port P1of the storage container19is provided. In addition, the second fixed electrode17that is inserted into the storage container19from the introduction port P2of the storage container19is provided. Thereby, the first fixed electrode16and the second fixed electrode17are provided at positions that are symmetric with respect to the rotation axis C. As shown inFIG.5andFIG.6, the first fixed electrode16has a plurality of first fixed metal plates161provided to face each other. In addition, the second fixed electrode17has a plurality of second fixed metal plates171provided to face each other. The fixed metal plates161and171are provided at substantially equal intervals along the rotation axis C. Here, the plurality of first fixed metal plates161have the same shape as each other, and are supported by a first flange member162. The first flange member162is fixed to the left side wall on which the introduction port P1of the storage container19is formed. Here, a through-hole162H communicating with the introduction port P1is formed at the first flange member162. In addition, the plurality of second fixed metal plates171have the same shape as each other, and are supported by a second flange member172. The second flange member172is fixed to the right side wall on which the introduction port P2of the storage container19is formed. Here, a through-hole172H communicating with the introduction port P2is formed at the second flange member172. The plurality of first fixed metal plates161and the plurality of second fixed metal plates171that are fixed to the storage container19are provided at positions that are symmetric with respect to the rotation axis C. In addition, the first fixed metal plate161and the second fixed metal plate171have a flat plate shape, and as shown inFIG.7, have a shape whose width decreases toward the rotation axis C in a plan view. Here, in the fixed metal plates161and171, end sides161aand171awhose widths decrease are formed in the radial direction of the rotation axis C. Here, the angle formed by the end sides161aand171afacing each other is 90 degrees. In addition, tip sides161band171bof the fixed metal plates161and171on the side of the rotation axis C have an arc shape. As shown inFIG.4andFIG.5, the movable electrode18includes a rotating shaft181that is rotatable around the rotation axis C and supported on the side wall (inFIG.4, the front side wall) of the storage container19, a first movable metal plate182that is supported by the rotating shaft181and faces the first fixed electrode16, and a second movable metal plate183that is supported by the rotating shaft181and faces the second fixed electrode17. The rotating shaft181has a linear shape extending along the rotation axis C. The rotating shaft181has one end that is configured to extend from the front side wall of the storage container19to the outside. Here, it is rotatably supported by a sealing member Sb such as an O-ring on the front side wall of the storage container19. Here, two points are supported by two O-rings on the front side wall. In addition, the other end of the rotating shaft181is rotatably in contact with a positioning recess191provided on the inner surface of the storage container19. In addition, in the rotating shaft181, a part181xthat supports the first movable metal plate182and the second movable metal plate183is formed of a conductive material such as a metal, and a part181ythat extends from the storage container19to the outside is formed of an insulating material such as a resin. The plurality of first movable metal plates182are provided to correspond to the first fixed metal plates161. Here, the first movable metal plates182have the same shape. In addition, the plurality of second movable metal plates183are provided to correspond to the second fixed metal plates171. Here, the second movable metal plates183have the same shape. The movable metal plates182and183are provided at substantially equal intervals along the rotation axis C. In addition, in the present embodiment, the movable metal plates182and183are interposed between the fixed metal plates161and171. InFIG.4, the number of fixed metal plates161and171is six, the number of movable metal plates182and183is five, but the disclosure is not limited thereto. Here, the gap between the movable metal plates182and183and the fixed metal plates161and171is, for example, 1 mm. As shown inFIG.5, the first movable metal plate182and the second movable metal plate183are provided at positions that are symmetric with respect to the rotation axis C and have the same shape as each other. Specifically, as shown inFIG.7, the movable metal plates182and183have a fan shape that expands radially outward from the rotation axis C in a plan view. In the present embodiment, it has a fan shape having a central angle of 90 degrees. By rotating the movable electrode18in the variable capacitor VC configured in this manner, as shown inFIG.8, a facing area (a first facing area A1) between the first fixed metal plate161and the first movable metal plate182changes, and a facing area (a second facing area A2) between the second fixed metal plate171and the second movable metal plate183changes. In the present embodiment, the first facing area A1and the second facing area A2changes in the same manner. In addition, the tip sides161band171bof the fixed metal plates161and171on the side of the rotation axis C have an arc shape, and by rotating the movable electrode18, the first facing area A1and the second facing area A2change in proportion of the rotation angle θ of the movable electrode18. In the above configuration, when the liquid coolant CL flows from the introduction port P1of the storage container19, the inside of the storage container19is filled with the liquid coolant CL. In this case, the space between the first fixed metal plate161and the first movable metal plate182is filled with the liquid coolant CL, and the space between the second fixed metal plate171and the second movable metal plate183is filled with the liquid coolant CL. Thereby, the liquid coolant CL becomes a dielectric of the first capacitor and a dielectric of the second capacitor. In the present embodiment, the capacitance of the first capacitor and the capacitance of the second capacitor are the same. In addition, the first capacitor and the second capacitor configured in this manner are connected in series, and the capacitance of the variable capacitor VC is half the capacitance of the first capacitor (or the second capacitor). The connecting conductor12configured in this manner may be provided between the antenna3and the high-frequency power supply4. In this case, the first fixed electrode16is electrically connected to the high-frequency power supply4, and the second fixed electrode17is electrically connected to the antenna3. In addition, the connecting conductor12may be provided between the antenna3and the ground. In this case, the first fixed electrode16is electrically connected to the antenna3, and the second fixed electrode17is grounded. With this configuration, the variable capacitor VC is connected to the feeding side and the ground side of the plurality of antennas constituting the antenna group3x. Here, as shown inFIG.1andFIG.3, the variable capacitor VC is connected to the feeding side and the ground side of the antennas3A to3F, and in the following, as shown inFIG.1, the variable capacitors VC connected to nine points on the feeding side of the first antenna3A, between the first antenna3A and the second antenna3B, the ground side of the second antenna3B, the feeding side of the third antenna3C, between the third antenna3C and the fourth antenna3D, the ground side of the fourth antenna3D, the feeding side of the fifth antenna3E, between the fifth antenna3E and the sixth antenna3F, and the ground side of the sixth antenna3F are called a first variable capacitor VC1, a second variable capacitor VC2, a third variable capacitor VC3, a fourth variable capacitor VC4, a fifth variable capacitor VC5, a sixth variable capacitor VC6, a seventh variable capacitor VC7, an eighth variable capacitor VC8, and a ninth variable capacitor VC9, respectively. Therefore, as shown inFIG.1, the plasma control system200of the present embodiment further includes a current detection mechanism Sx that detects a current flowing through the feeding side and the ground side of the plurality of antennas3constituting the antenna group3x, and the above control device X has a configuration in which the reactance of the variable capacitor VC sequentially changes based on the current value detected by the current detection mechanism Sx. Here, inFIG.2andFIG.3, the description of the current detection mechanism Sx is omitted. The current detection mechanism Sx detects a current flowing through the feeding side and the ground side of the antennas3A to3F, and is composed of a plurality of current detection units S1to S9provided on the feeding side and the ground side of the antennas3A to3F. The current detection units S1to S9are, for example, a current monitor such as a current transformer, and the detected detection signal is converted from an alternating current to a direct current by a DC conversion circuit, converted from an analog signal to a digital signal by an AD converter, and output to the control device X. The control device X is physically a computer such as a PLC including a CPU, a memory, an input/output interface and the like, and when a plasma control program stored in the memory is executed, and the devices collaborate with each other, as shown inFIG.9, at least functions of a uniformity calculation unit X1and a reactance changing unit X2are exhibited. The uniformity calculation unit X1acquires the detection signal detected by the current detection units S1to S9, and calculates a uniformity index value indicating the uniformity of the current that flows through the plurality of antennas3A to3F based on the current value indicated by each detection signal. The uniformity index value is a value calculated using at least a part of the current value detected by the current detection units S1to S9as a parameter, and a smaller value indicates higher uniformity of the current flowing through the antennas3A to3F, and a higher value indicates lower uniformity of the current flowing through the antennas3A to3F. The uniformity calculation unit X1here is configured to calculate the uniformity index value using the maximum value and the minimum value of the current value detected by the current detection units S1to S9as parameters, and specifically, the following calculation formula is used. uniformity index valueIx=(maximum valueImax−minimum valueImin)/(maximum valueImax+minimum valueImin)×100(%) Here, the uniformity index value Ix is not limited to the value calculated by the above calculation formula, but it may be calculated using, for example, the average value or the standard deviation of the current value detected by the current detection units S1to S9. The reactance changing unit X2sequentially changes the reactances of the plurality of variable capacitors VC so that the uniformity index value Ix calculated by the uniformity calculation unit X1approaches a predetermined set value Is. Here, the reactance changing unit X2changes the capacitance by outputting a drive signal to the drive unit that rotates the movable electrode18of the variable capacitor VC, and is configured to change the capacitances of the first variable capacitor VC1to the ninth variable capacitor VC9in a predetermined order. Hereinafter, a case in which the capacitances of the first variable capacitor VC1to the ninth variable capacitor VC9are set to be changed in this order will be described with reference to the flowchart ofFIG.10. First, the reactance changing unit X2sets a counter using a counter circuit (T1). Specifically, the count number m is increased by increasing the count number m indicating the number of operations so far by 1. Subsequently, when the reactance changing unit X2changes the capacitance of the m-th variable capacitor VCm according to the count number m in T1, the initial rotation direction of the movable electrode18is set to either a forward rotation direction or a reverse rotation direction, and in other words, the initial change direction of the capacitance of the m-th variable capacitor VCm is set to either an increase direction or a decrease direction (T2). Specifically, first, the movable electrode18is rotated by a predetermined angle (for example, 3°), for example, in the forward rotation direction (for example, a direction in which the impedance increases). Thereby, when the uniformity index value Ix approaches the set value Is, the forward rotation direction is set as the initial rotation direction, and on the other hand, when the uniformity index value Ix is away from the set value Is, the reverse rotation direction is set as the initial rotation direction. Here, it is not always possible to perform rotation in the forward rotation direction first, and the initial rotation direction may be set by performing rotation in the reverse rotation direction. Next, the reactance changing unit X2compares the uniformity index value Ix with the set value Is and determines whether the uniformity index value Ix reaches the set value Is, and in other words, determines whether the uniformity index value Ix is smaller than the set value Is (T3). In T3, when the uniformity index value Ix is smaller than the set value Is, the control is terminated. On the other hand, in T3, when the uniformity index value Ix is equal to or larger than the set value Is, the reactance changing unit X2determines whether the movable electrode18is rotated and thus the uniformity index value Ix is larger than the value before the rotation (T4). In T4, when the uniformity index value Ix decreases, the reactance changing unit X2rotates the movable electrode18of the above m-th variable capacitor VCm in the initial rotation direction by a predetermined angle (for example, 3°), and the capacitance changes (T5), and the state returns to T3. On the other hand, in T4, when the uniformity index value Ix increases, the reactance changing unit X2rotates the movable electrode18of the m-th variable capacitor VCm in a direction (for example, a direction in which the impedance decreases) opposite to the initial rotation direction by the above predetermined angle (for example, 3°), and returns the capacitance of the m-th variable capacitor VCm to a state before the change (T6). Then, it is determined whether the count number m matches the maximum count number (9in the present embodiment) which is a total number of variable capacitors VC to be controlled (T7), and if they match, the count number m is reset to 0 (T8), the state returns to T1, and if they do not match, the state returns to T1while the count number m is maintained. Effects of the Present Embodiment According to the plasma control system200of the present embodiment configured in this manner, as shown inFIG.11, since the capacitances of the plurality of variable capacitors VC, that is, the reactances of the plurality of variable capacitors VC, sequentially change so that the uniformity index value Ix approaches the set value Is, the current flowing through the plurality of antennas3can be made as uniform as possible. As a result, it is possible to generate uniform plasma while it is possible to cope with an increase in size of a substrate using the plurality of antennas3. Here, the example shown inFIG.11is a variation of the uniformity index value Ix when the capacitance of the first variable capacitor VC1to the fourth variable capacitor VC4changes. In addition, since it is a control method in which the capacitances of the plurality of variable capacitors VC sequentially change, even if the number of antennas3increases or decreases, it is not necessary to greatly change the control method, and plasma can be made uniform in various device configurations according to a simple control method. In addition, since the current flowing through each of the feeding side and the ground side of the antennas3is detected, the current flowing through the antennas3can be made as equal as possible, and since the variable capacitor VC is provided on each of the feeding side and the ground side of the antennas3, the plasma density can be controlled more finely. In addition, since the antenna3can be cooled with the liquid coolant CL, the plasma P can be stably generated. In addition, since the dielectric of the first variable capacitor VC1is composed of the liquid coolant CL flowing through the antenna3, it is possible to minimize an unexpected variation in the capacitance while cooling the first variable capacitor VC1. Other Modified Embodiments Here, the disclosure is not limited to the above embodiment. For example, the antenna group of the above embodiment is composed of a total of six antennas obtained by connecting three sets of two antennas connected in series in parallel, but the number of antennas constituting the antenna group is not limited thereto, and the antenna group may include a plurality of antennas, and for example, it may include four antennas obtained by connecting two sets of two antennas connected in series in parallel. In addition, in the above embodiment, the movable electrode is rotated by a constant angle until the uniformity index value becomes smaller than the set value, but the rotation angle may be changed stepwise. Specifically, an aspect in which a threshold value different from the set value is set for the uniformity index value and the rotation angle is changed before and after the threshold value is reached, and an aspect in which the rotation angle is changed according to the current reactance of the variable capacitor VC, that is, the current angle of the movable electrode may be exemplified. As an example of the former aspect, an aspect in which, if the uniformity index value is larger than the set value, when the reactance changing unit compares the uniformity index value with the threshold value and the uniformity index value is larger than the threshold value, the movable electrode is rotated by a predetermined first angle (for example, 3°), and when the uniformity index value is smaller than the threshold value, the movable electrode is rotated by a predetermined second angle (for example, 1°) smaller than the first rotation angle may be exemplified. With such a configuration, the reactance change amount can be increased until the uniformity index value reaches the threshold value, the reactance change amount can be reduced until the uniformity index value reaches the threshold value and then reaches the set value, and thus the control time can be shortened. Here, a plurality of threshold values may be provided and the rotation angle may be changed in more stages. As an example of the latter aspect, an aspect in which, since the change in reactance when the movable electrode is rotated by the same angle is larger when it is on the low angle side than when it is on the high angle side, a boundary angle as a boundary between the low angle side and the high angle side is set may be exemplified. Here, when the uniformity index value is larger than the set value, the reactance changing unit compares the current angle of the movable electrode with the boundary angle, and if the current angle is larger than the boundary angle, the movable electrode is rotated by a predetermined first angle (for example, 3°), and if the current angle is smaller than the boundary angle, the movable electrode is rotated by a predetermined second angle (for example, 1°) smaller than the first angle. With such a configuration, the reactance change amount can be adjusted appropriately depending on whether the reactance of the variable capacitor can be changed slowly or the reactance varies greatly. Here, a plurality of boundary angles may be provided, and the rotation angle may be changed in more stages. In addition, as shown inFIG.12, the control device X may further include a function of a weighted value storage unit X3that stores a weighted value indicating the degree of influence on the uniformity index value, which is a value weighted in advance for each of the plurality of variable capacitors. For such a weighted value, for example, a plurality of variable capacitors are rotated one by one in the forward rotation direction and/or reverse rotation direction by a constant angle, the amount of change (amount of decrease) in the uniformity index value due to the rotation is confirmed, and the weighted value is set to be larger as the amount in change is larger. Here, the weighted value is not limited thereto and may be set by various methods. Here, when the uniformity index value is larger than the set value, the reactance changing unit X2refers to the weighted value of each reactance variable element stored in the weighted value storage unit X3, and changes the reactance in the order from the variable capacitor having a larger weighted value. With such a configuration, since the reactance of the variable capacitor, which has a high influence on the uniformity index value, can be changed, the efficiency of control can be improved. In addition, in the above embodiment, variable capacitors are provided on the feeding side and the ground side of the antennas, but it is not always necessary to provide all of these variable capacitors, and for example, one or two among the first variable capacitor, the fourth variable capacitor, and the seventh variable capacitor in the above embodiment may be omitted. In the variable capacitor of the above embodiment, the movable electrode rotates around the rotation axis, but the movable electrode may slide and move in one direction. Here, in a configuration in which the movable electrode slides, the movable electrode may slide in a direction orthogonal to the facing direction with respect to the fixed electrode and the facing area may change, or the movable electrode may slide in a direction facing the fixed electrode and the facing distance may change. In such a configuration, the drive unit may be a motor as in the above embodiment or a cylinder or the like. In place of the variable capacitor in the above embodiment, a reactance variable element of which the reactance changes when the movable element moves such as a variable impedance element or a variable resistive element may be used. In the above embodiment, the antenna has a linear shape, but it may have a curved or bent shape. In this case, the metal pipe may have a curved or bent shape, and the insulating pipe may have a curved or bent shape. In addition, it should be noted that the disclosure is not limited to the above embodiment, and various modifications can be made without departing from the spirit and scope of the disclosure. REFERENCE SIGNS LIST 200Plasma control system100Plasma treatment deviceW SubstrateP Inductively coupled plasmaIR High-frequency current2Vacuum container3xAntenna group3Antenna3a1One end3a2Other endVC Variable capacitor18Movable electrode (movable element)CL Liquid coolant (dielectric of liquid)Sx Current detection mechanismX Control deviceX1Uniformity calculation unitX2Reactance changing unit | 35,100 |
11862432 | DESCRIPTION OF EMBODIMENTS Hereinafter, for illustrating the invention in more detail, embodiments for carrying out the invention will be described with reference to the accompanying drawings. Embodiment 1 FIG.1is a lateral-side schematic view showing a configuration of a microwave heating device10according to Embodiment 1. FIG.2is a top-side schematic view showing an internal configuration of the microwave heating device10according to Embodiment 1. InFIG.2, the top face of a heating chamber1, a microwave generation unit2and a radiation element3are omitted from the illustration. The same applies to the top-side schematic views for other embodiments to be described later. The microwave heating device10includes the heating chamber1, the microwave generation unit2, the radiation element3, hollow dielectric members4and a control unit100. The heating chamber1is a casing capable of storing therein a heating target X and having walls made of conductors. The microwave generation unit2includes a microwave oscillator21, a microwave amplifier22and a microwave-oscillation control unit23. The microwave oscillator21is a device that oscillates a microwave under the control of the microwave-oscillation control unit23. The microwave amplifier22is a device that amplifies the microwave oscillated by the microwave oscillator21. The microwave-oscillation control unit23controls oscillation of the microwave in the microwave oscillator21. The radiation element3is connected to the microwave generation unit2and radiates the microwave generated in the microwave generation unit2into the heating chamber1. The radiation element3is provided inside the heating chamber1and at one of the top-side wall, the bottom-side wall and the lateral-side walls. InFIG.1, a case is shown where the radiation element3is provided inside the heating chamber1and at the top-side wall. The hollow dielectric members4each generate plasma in response to the application of a current by a current adjustment unit102to be described later in the control unit100. FIG.3is a diagram showing a configuration of the hollow dielectric member4in the microwave heating device10according to Embodiment 1. The hollow dielectric member4is sealed with the inside thereof filled with a gas41, and electrodes42provided at both end portions thereof. The electrodes42are connected to the current adjustment unit102. The gas41in the hollow dielectric member4is switched, depending on what current is applied from the current adjustment unit102, between a plasma state in which plasma is generated and a gas state in which no plasma is generated. It is desired that the hollow dielectric member4be formed of a material with a low dielectric loss and a low dielectric constant. Further, it is desired that the gas41with which the inside of the hollow dielectric member4is filled be a gas containing a Group 18 element (rare gas element); however, a medium of nitrogen, oxygen or the like, or a mixed medium of nitrogen and oxygen may also be used. Further, in order to adjust the plasma generation level, a medium such as Hg, a Fractogel® TMAE or the like may be added to the gas41. One or more hollow dielectric members4are provided inside the heating chamber1along one of the walls other than the wall at which the radiation element3is provided. InFIG.2, a case is shown where six hollow dielectric members4are provided along a lateral-side wall1aof the heating chamber1, and six hollow dielectric members4are provided along another lateral-side wall1bthereof. Note that the wall(s) along which the hollow dielectric members4are provided, and the number of the provided hollow dielectric members4, are not limited to the configuration shown inFIG.2, and may be determined freely. The control unit100includes a plasma control unit101and the current adjustment unit102. The plasma control unit101controls the current adjustment unit102. The plasma control unit101has, for example, a timer (not illustrated), and makes switching among current-application patterns in response to the counting of the timer, to thereby control the current adjustment unit102. Here, the application patterns are pieces of information in which multiple application settings are specified as patterns, each indicating: which hollow dielectric member4is subject to the application; the current value of a current to be applied; an application time; and the like. The current adjustment unit102adjusts the current to be applied to the electrodes42of each of the hollow dielectric members4, under the control of the plasma control unit101. Specifically, the current adjustment unit102adjusts the current to be applied to the electrodes42of the hollow dielectric member4, to thereby set the gas41with which the inside of the hollow dielectric member4is filled into the plasma state in which plasma is generated or the gas state in which no plasma is generated so that the microwave is allowed to be transmitted. Further, when the gas41in the hollow dielectric member4is in the plasma state, the current adjustment unit102further adjusts the current value of the current to be applied, to thereby perform setting of the plasma state so that it is switched between a reflection mode in which the microwave is reflected and an absorption mode in which the microwave is absorbed. Under the control of the plasma control unit101, the current adjustment unit102sets the state of the gas41in each of one or more hollow dielectric members4among the provided hollow dielectric members4, to the plasma state. This causes the microwave having entered the heating chamber1to be reflected or absorbed by the hollow dielectric member4in the plasma state, so that the heating energy distribution in the heating chamber1varies. Multiple patterns for setting plasma states are made ready, and the current adjustment unit102changes the pattern of the plasma states for every time period. Thereby, the distribution of heating energy in the heating chamber1is equalized, so that uneven heating of the heating target X is suppressed. In the example ofFIG.2, a case is shown where the state of the gas41in the hollow dielectric member4a, one of the six hollow dielectric members4provided along the lateral-side wall1a, is set to the plasma state, and the other hollow dielectric members4are each set into the gas state. Note that the hollow dielectric member4to be set into the plasma state is not limited to one hollow dielectric member4a, and multiple hollow dielectric members4may be each set into the plasma state. As described above, according to Embodiment 1, a configuration is provided which includes: at least one hollow dielectric member4in which the gas41is sealed, the hollow dielectric member4having the electrodes42at both end portions thereof; and the control unit100having the plasma control unit101for controlling the state of the hollow dielectric member4, and the current adjustment unit102for adjusting a current to be applied to the electrodes42of the hollow dielectric member4, under the control of the plasma control unit101, the current adjustment unit102being connected to the electrodes42. The at least one hollow dielectric member4is provided along the wall other than the wall at which the radiation element3is provided. The plasma control unit101controls the state of the hollow dielectric member4so that it is put into one of the states of the plasma state in which the microwave is reflected by the gas, the plasma state in which the microwave is absorbed by the gas, and the gas state in which the microwave is allowed to be transmitted through the gas. Accordingly, it is possible to switch the state of the hollow dielectric member4into one of the states of the plasma state in which the microwave is reflected by the gas, the plasma state in which the microwave is absorbed by the gas, and the gas state in which the microwave is allowed to be transmitted through the gas, to thereby change the distribution of microwave heating energy in the heating chamber. Thus, the microwave heating energy can be equalized, and this makes it possible to suppress uneven heating of the heating target. Embodiment 2 FIG.4is a top-side schematic view showing an internal configuration of a microwave heating device10according to Embodiment 2. InFIG.4, the control unit100is omitted from the illustration. Further, with respect to the parts same as or equivalent to the components of the microwave heating device10according to Embodiment 1, the same reference numerals as the reference numerals used in Embodiment 1 are given thereto, and description thereof will be omitted or simplified. Two or more hollow dielectric members4are provided in a line inside the heating chamber1along at least one of the walls other than the wall at which the radiation element3is provided. InFIG.4, a case is shown where eight hollow dielectric members4are provided in a line along the lateral-side wall1aand eight hollow dielectric members4are provided in a line along the lateral-side wall1b. Under the control of the plasma control unit101, the current adjustment unit102puts two or more hollow dielectric members4provided in a line among the provided hollow dielectric members4, into the plasma state in which the microwave is reflected. InFIG.4, a case is shown where the eight hollow dielectric members4aprovided in a line along the lateral-side wall1aare each put into the plasma state in which the microwave is reflected. Further, inFIG.4, a case is shown where the eight hollow dielectric members4bprovided in a line along the lateral-side wall1bare each put into the gas state in which no plasma is generated. When two or more hollow dielectric members4provided in a line are each put into the plasma state in which the microwave is reflected, a virtual reflection surface for reflecting the microwave is formed. The microwave having entered the heating chamber1is reflected by the reflection surface formed by the hollow dielectric members4, to thereby cause the heating energy distribution in the heating chamber1to vary. Subsequently, under the control of the plasma control unit101, the current adjustment unit102changes the state of each of the hollow dielectric members4aput into the plasma state in which the microwave is reflected, into the gas state in which no plasma is generated so that the microwave is allowed to be transmitted. Namely, under the control of the plasma control unit101, the current adjustment unit102makes switching of the hollow dielectric members4abetween the plasma state and the gas state, so that switching between formation of the reflection surface and elimination of the formed reflection surface is performed. Due to the formation and the elimination of the reflection surface by the hollow dielectric members4, the distribution of heating energy varies temporally to be equalized, so that uneven heating of the heating target X is suppressed. As described above, according to Embodiment 2, two or more hollow dielectric members4are provided in in a line along at least one of the walls other than the wall at which the radiation element3is provided; the plasma control unit101controls the states of respective two or more hollow dielectric members among the hollow dielectric members4provided in a line so that the respective two or more hollow dielectric members are put into the plasma state in which the microwave is reflected. Accordingly, the virtual reflection surface due to plasma is formed, so that it is possible to change the distribution of microwave heating energy in the heating chamber. Thus, the microwave heating energy can be equalized, and this makes it possible to suppress uneven heating of the heating target. Embodiment 3 FIG.5is a lateral-side schematic view showing a configuration of a microwave heating device10according to Embodiment 3. FIG.6is a top-side schematic view showing an internal configuration of the microwave heating device10according to Embodiment 3. InFIG.5andFIG.6, the control unit100is omitted from the illustration. Further, with respect to the parts same as or equivalent to the components of the microwave heating device10according to Embodiment 1 or 2, the same reference numerals as the reference numerals used in Embodiment 1 or 2 are given thereto, and description thereof will be omitted or simplified. Two or more hollow dielectric members4are provided inside the heating chamber1along each one of two or more walls (a first wall and a second wall), that are other than the wall at which the radiation element3is provided and that are opposite to each other across the heating target X. Further, each of the hollow dielectric members4is provided at a position about 0.25 wavelength away from the corresponding wall. InFIG.5andFIG.6, a case is shown where eight hollow dielectric members4aare provided in a line along the lateral-side wall1a(the first wall) of the heating chamber1and eight hollow dielectric members4bare provided in a line along the lateral-side wall1b(the second wall) of the heating chamber1. Further, the hollow dielectric members4aare each provided at a position about 0.25 wavelength away from the wall1a, and the hollow dielectric members4bare each provided at a position about 0.25 wavelength away from the wall1b. When multiple hollow dielectric members4provided in a line are each put into the plasma state in which the microwave is reflected, a virtual reflection surface for reflecting the microwave is formed. The microwave having entered the heating chamber1is reflected by the reflection surface formed by the hollow dielectric members4, to thereby cause the heating energy distribution in the heating chamber1to vary. Note that the number of the provided hollow dielectric members4is not limited to the number shown inFIG.6, and may be determined freely if it is a number which enables a virtual reflection surface to be formed by either one of the sets of the hollow dielectric members4opposite to each other across the heating target X. Under the control of the plasma control unit101, the current adjustment unit102puts the row of the hollow dielectric members4aprovided in a line along the wall1athat is one of the opposite walls, into the plasma state in which the microwave is reflected. At the same time, the row of the hollow dielectric members4bprovided in a line along the other wall1bopposite to the wall1a, is put into the gas state in which no plasma is generated so that the microwave is allowed to be transmitted (hereinafter, referred to as a first set of states). Then, under the control of the plasma control unit101, the current adjustment unit102puts the row of the hollow dielectric members4aprovided in a line along the wall1aand each being in the plasma state in which the microwave is reflected, into the gas state, and puts the row of the hollow dielectric members4bprovided in a line along the other wall1bopposite to the wall1aand each being in the gas state, into the plasma state in which the microwave is reflected (hereinafter, referred to as a second set of states). The plasma control unit101performs control to make switching between the first set of states and the second set of states described above, alternately at predetermined time intervals. Under the control of the plasma control unit101, the current adjustment unit102adjusts the currents to be applied, to thereby switch the rows of the hollow dielectric members4a,4bbetween the first set of states and the second set of states described above, alternately at the predetermined time intervals. Accordingly, the position of the microwave standing wave generated in the heating chamber1is changed. With reference toFIG.7, description will be made about a variation in the position of the microwave standing wave generated in the heating chamber1. FIG.7includes diagrams each showing a position of the standing wave in the microwave heating device10according to Embodiment 3. Note thatFIG.7Ashows the position of the microwave standing wave in the first set of states described above, andFIG.7Bshows the position of the microwave standing wave in the second set of states described above. As shown inFIG.7AandFIG.7B, the row of the hollow dielectric members4ais placed at a position 0.25 wavelength away from the wall1a, and the row of the hollow dielectric members4bis placed at a position 0.25 wavelength away from the wall1bopposite to the wall1aacross the heating target X. First, as shown inFIG.7A, under the control of the plasma control unit101, the current adjustment unit102puts the row of the hollow dielectric members4ainto the plasma state in which the microwave is reflected, and puts the row of the hollow dielectric members4binto the gas state (the first set of states). As shown inFIG.7A, in the first set of states, a virtual reflection surface A is formed by the row of the hollow dielectric members4a. The thus-formed virtual reflection surface A reflects the microwave, resulting in the waveform of a standing wave B shown inFIG.7A. The nodes of the standing wave B are placed at positions Ba, and the antinodes of the standing wave B are placed at positions Bb. Then, as shown inFIG.7B, under the control of the plasma control unit101, the current adjustment unit102puts the row of the hollow dielectric members4binto the plasma state in which the microwave is reflected, and puts the row of the hollow dielectric members4ainto the gas state (the second set of states). As shown inFIG.7B, in the second set of states, a virtual reflection surface C is formed by the row of the hollow dielectric members4b. The thus-formed virtual reflection surface C reflects the microwave, resulting in the waveform of a standing wave D shown inFIG.7B. The nodes of the standing wave D are placed at positions Da, and the antinodes of the standing wave D are placed at positions Db. The positions of the nodes of the standing wave in the first set of states (the positions Ba inFIG.7A) coincide with the positions of the antinodes of the standing wave in the second set of states (for example, the positions Db inFIG.7B). Likewise, the positions of the nodes of the standing wave in the second set of states (the positions Da inFIG.7B) coincide with the positions of the antinodes of the standing wave in the first set of states (for example, the positions Bb inFIG.7A). In the case represented byFIG.7AandFIG.7B, when switching between the first set of states and the second set of states is performed, the positions of the nodes of the standing wave are shifted by a distance indicated by an arrow E. When the plasma control unit101and the current adjustment unit102switch the states of the hollow dielectric members4between the first set of states and the second set of states, the positions of the nodes and antinodes of the standing wave are shifted and thus the heating energy distribution is equalized on a time-average basis, so that uneven heating of the heating target X is suppressed. As described above, according to Embodiment 3, two or more hollow dielectric members4are provided in a line at respective positions about 0.25 wavelength away from the wall1aother than the wall at which the radiation element3is provided, and two or more hollow dielectric members4are provided in a line at respective positions about 0.25 wavelength away from the wall1bother than the wall at which the radiation element3is provided, the wall1bbeing opposite to the wall1aacross the heating target X. The plasma control unit101performs control to make switching between: the first set of states in which the hollow dielectric members4aprovided in a line along the wall1aare put into the plasma state in which the microwave is reflected while the hollow dielectric members4bprovided in a line along the wall1bare put into the gas state in which the microwave is allowed to be transmitted; and the second set of states in which the hollow dielectric members4bprovided in a line along the wall1bare put into the plasma state in which the microwave is reflected while the hollow dielectric members4aprovided in a line along the wall1aare put into the gas state in which the microwave is allowed to be transmitted. Accordingly, the positions of the nodes and antinodes of the standing wave are shifted and thus the heating energy distribution can be equalized on a time-average basis. Thus, it is possible to suppress uneven heating of the heating target. Embodiment 4 In Embodiment 4, a configuration in which the currents to be applied to the hollow dielectric members4are controlled on the basis of a temperature distribution in the heating chamber1, will be described. FIG.8is a block diagram showing a configuration of a control unit100A in a microwave heating device10according to Embodiment 4. The control unit100A in the microwave heating device10of Embodiment 4 is configured by the addition of a data processing unit103and a database104to the control unit100shown in each of Embodiments 1 to 3. Note that, in the following, with respect to the parts same as or equivalent to the components of the microwave heating device10according to each of Embodiments 1 to 3, the same reference numerals as the reference numerals used in each of Embodiment 1 to 3 are given thereto, and description thereof will be omitted or simplified. The control unit100A includes the data processing unit103, the database104, the plasma control unit101and the current adjustment unit102. The control unit100A is connected wirelessly or by wire to a temperature monitor200provided in the heating chamber1. The temperature monitor200includes, for example, a temperature sensor, and acquires temperature information indicating a temperature distribution in the heating chamber1. The temperature monitor200only has to be able to acquire the temperature information of the heating chamber1, and is provided at an appropriate position. The data processing unit103refers to the temperature information inputted from the temperature monitor200to thereby determine whether or not there is an unheated region in a region near the heating target X. Here, when, for example, a recommended position for the heating target X to be placed is predetermined in the heating chamber1, a region within a predetermined distance from the position is set as the region near the heating target X. Further, it is also allowed to identify the heating target X from imaging data obtained by imaging the inside of the heating chamber1, to thereby set a region in which the heating target X is placed, as the region near the heating target X. When having determined that there is an unheated region in the region near the heating target X, the data processing unit103refers to the database104to thereby acquire a control setting matched with the temperature information inputted from the temperature monitor200. The data processing unit103outputs the acquired control setting to the plasma control unit101. The database104is a storing region for associating each piece of temperature information with a corresponding control setting indicating values and application times of the currents to be applied to the electrodes42of the hollow dielectric members4, and for storing the resultant data. The plasma control unit101controls the current adjustment unit102in accordance with the control setting inputted from the data processing unit103. The current adjustment unit102adjusts the currents to be applied to the electrodes42of the hollow dielectric members4, under the control of the plasma control unit101. Next, description will be made about hardware configuration examples of the microwave heating device10. FIG.9AandFIG.9Bare diagrams each showing a hardware configuration example of the control unit100A in the microwave heating device10according to Embodiment 4. The functions of the data processing unit103, the plasma control unit101and the current adjustment unit102in the control unit100A of the microwave heating device10, are implemented by a processing circuit. Namely, the control unit100A of the microwave heating device10includes the processing circuit for implementing the functions. The processing circuit may be, as shown inFIG.9A, a processing circuit100aas dedicated hardware, or may be, as shown inFIG.9B, a processor100bwhich executes programs stored in a memory100c. When the data processing unit103, the plasma control unit101and the current adjustment unit102correspond to dedicated hardware as shown inFIG.9A, the processing circuit100ais, for example, a single circuit, a composite circuit, a programmed processor, a parallel-programmed processor, an Application Specific Integrated Circuit (ASIC), a Field-programmable Gate Array (FPGA) or any combination thereof. The functions of the data processing unit103, the plasma control unit101and the current adjustment unit102may be implemented by their respective processing circuits, or the functions may be implemented collectively by one processing circuit. When the data processing unit103, the plasma control unit101and the current adjustment unit102correspond to the processor100bas shown inFIG.9B, their respective functions are implemented by software, firmware or a combination of software and firmware. The software and the firmware are each written as a program(s) and stored in the memory100c. The processor100breads out and executes programs stored in the memory100cto thereby implement the functions of the data processing unit103, the plasma control unit101and the current adjustment unit102. Namely, the data processing unit103, the plasma control unit101and the current adjustment unit102are provided with the memory100cfor storing the programs by which, when they are executed by the processor100b, the steps shown inFIG.10to be described later are eventually executed. Further, it can also be said that these programs are programs for causing a computer to execute steps or processes of the data processing unit103, the plasma control unit101and the current adjustment unit102. Here, the processor100bmeans, for example, a Central Processing Unit (CPU), a processing device, an arithmetic device, a processor, a microprocessor, a microcomputer, a Digital Signal Processor (DSP), or the like. The memory100cmay, for example, be a non-volatile or volatile semiconductor memory such as a Random Access Memory (RAM), a Read Only Memory (ROM), a flash memory, an Erasable Programmable ROM (EPROM), an Electrically EPROM (EEPROM) or the like; a magnetic disc such as a hard disc, a flexible disc or the like; or an optical disc such as a mini disc, a Compact Disc (CD), a Digital Versatile Disc (DVD) or the like. It is noted that the functions of the data processing unit103, the plasma control unit101and the current adjustment unit102may be implemented partly by dedicated hardware and partly by software or firmware. In this manner, using hardware, software, firmware or any combination thereof, the processing circuit in the microwave heating device10can implement the functions. Next, description will be made about operations of the control unit100A. FIG.10is a flowchart showing the operations of the control unit100A in the microwave heating device10according to Embodiment 4. Upon acquisition of the temperature information from the temperature monitor200(Step ST1), the data processing unit103refers to a portion of the temperature information corresponding to the region near the heating target X, to thereby determine whether or not there is an unheated region (Step ST2). If there is an unheated region (Step ST2; YES), the data processing unit103refers to the database104to thereby acquire a control setting matched with the temperature information acquired in Step ST1(Step ST3). The data processing unit103outputs the acquired control setting to the plasma control unit101. The plasma control unit101controls the current adjustment unit102on the basis of the inputted control setting (Step ST4). The current adjustment unit102applies a current(s) to the electrodes42of the hollow dielectric member(s)4on the basis of such a control in Step ST4(Step ST5). Thereafter, processing in the flowchart returns to Step ST1. In contrast, if there is no unheated region (Step ST2; NO), the data processing unit103looks up the temperature of the heating target X, to thereby determine whether or not it has reached a preset temperature (Step ST6). When the temperature of the heating target X has not reached the preset temperature (Step ST6; NO), the data processing unit103instructs the plasma control unit101to continue heating using the current control setting (Step ST7). The plasma control unit101controls the current adjustment unit102on the basis of the instruction inputted from the data processing unit103(Step ST8). The current adjustment unit102applies a current(s) to the electrodes42of the hollow dielectric member(s)4on the basis of such a control in Step ST8(Step ST9). Thereafter, processing in the flowchart returns to Step ST1. On the other hand, when the temperature of the heating target X has reached the preset temperature (Step ST6; YES), the data processing unit103instructs the plasma control unit101to terminate heating (Step ST10). On the basis of the instruction inputted from the data processing unit103, the plasma control unit101controls the current adjustment unit102to thereby stop applying the current(s) (Step ST11), so that the processing is terminated. It is noted that, in the foregoing flowchart, processing is shown that terminates heating on the basis of the temperature of the heating target X determined in the determination processing of Step ST6; however, the heating may terminate in response to a predetermined heating period. As described above, according to Embodiment 4, the control unit100A includes the data processing unit103for acquiring the temperature information indicating a temperature distribution in the heating chamber1, and then referring to the database104in which control settings for controlling the state of each of the hollow dielectric members4are stored, to thereby acquire one of the control settings which is matched with the acquired temperature information. The plasma control unit101controls the state of each of the hollow dielectric members4in accordance with the control setting acquired by the data processing unit103. The current adjustment unit102adjusts, under the control of the plasma control unit, each current to be applied to the electrodes. Accordingly, the plasma state of each of the hollow dielectric members4can be controlled on the basis of the temperature distribution in the heating chamber. It is possible to suppress uneven heating of the heating target. It is noted that, in the foregoing Embodiment 4, a configuration is shown in which the microwave heating device10includes the database104; however, an external device may include the database104. Embodiment 5 In Embodiment 5, a configuration in which the database104is updated using temperature information acquired by the temperature monitor200will be described. FIG.11is a block diagram showing a configuration of a control unit100B in a microwave heating device10according to Embodiment 5. The control unit100B of Embodiment 5 is configured by the provision of a data processing unit103ainstead of the data processing unit103in the control unit100A shown in Embodiment 4 and by the addition of an update processing unit105. Note that, in the following, with respect to the components same as or equivalent to the components of the control unit100A in the microwave heating device10according to Embodiment 4, the same reference numerals as the reference numerals used in Embodiment 4 are given thereto, and description thereof will be omitted or simplified. The data processing unit103aoutputs, out of pieces of temperature information inputted from the temperature monitor200, each piece of temperature information after change of the plasma state of the hollow dielectric member4by the plasma control unit101and the current adjustment unit102, to the update processing unit105. The update processing unit105receives from the data processing unit103a, an input of the temperature information after the change of the plasma state. The update processing unit105causes the database104to store the received temperature information after the change of the plasma state. The database104stores temperature information before the change of the plasma state, a control setting, and the temperature information after the change of the plasma state so that they are associated with each other. At the time of acquiring a control setting on the basis of the temperature information inputted from the temperature monitor200, the data processing unit103arefers also to the temperature information after the change of the plasma state, to thereby acquire the control setting with which an intended temperature distribution will be established. Because the update processing unit105updates the database104by using the temperature information after the change of the plasma state, it becomes possible for the data processing unit103to acquire control information by which the heating target X will get into a suitably heated state. Further, the update processing unit105may perform learning processing on the control setting by using information indicating how the temperature information has varied after the change of the plasma state. On the basis of the learning result on the control setting, the update processing unit105updates the control setting stored in the database104. Because the update processing unit105performs learning processing on the control setting, it is possible to quickly perform optimum control of the plasma state. Next, hardware configuration examples of the control unit100B will be described. Note that the configuration that is the same as that in Embodiment 4 will be omitted from description. The data processing unit103aand the update processing unit105in the control unit100B correspond to the processing circuit100ashown inFIG.9A, or the processor100bshown inFIG.9Bwhich executes programs stored in the memory100c. As described above, according to Embodiment 5, the control unit100B includes the update processing unit105for acquiring, through the data processing unit103, the temperature information after change of the plasma state by the plasma control unit101, and then performing updating by causing the database104to associate the temperature information before and after the change of the plasma state with the corresponding control setting and to store resultant data. The data processing unit103refers to the database104after the updating, to thereby acquire a control setting on the basis of the temperature information that is currently given and the temperature information before and after application of the current. Accordingly, when the update processing has been repeated multiple times, it is possible to heat the heating target up to a state without uneven heating. Further, it is possible to accumulate each piece of information after the change of the plasma state, so that the control setting with which a desired temperature distribution will be established can be acquired more easily. In another aspect, according to Embodiment 5, the update processing unit105performs learning processing on the control setting by using information indicating how the temperature information has varied after the change of the plasma state. This makes it possible to perform optimum control of the plasma state for the temperature distribution in the heating chamber. It is noted that, in the foregoing Embodiment 4 and Embodiment 5, the description has been made about the control units100A,100B to be applied to the microwave heating devices10of Embodiments 1 to 3 shown inFIG.2,FIG.4andFIG.6. However, the microwave heating devices10to which the control units100A,100B are to be applied, are not limited to those having the configurations shown inFIG.2,FIG.4andFIG.6, and may include, for example, a microwave heating device10shown inFIG.12. FIG.12is a diagram showing another configuration example of the microwave heating device10according to either Embodiment 4 or 5, and is a top-side schematic view of an internal configuration of the microwave heating device10. InFIG.12, the control units100A,100B are omitted from the illustration. Hollow dielectric members4are provided in a line along everyone of the lateral-side walls1a,1b,1c,1dof the heating chamber1that cross the face at which the radiation element3is provided (for example, the top face shown inFIG.1). Further, rows of hollow dielectric members4are stacked. In the example ofFIG.12, a case is shown where three rows of hollow dielectric members4provided in a line along the wall1aare stacked. A case is also shown where three rows of hollow dielectric members4provided in a line along the wall1bare stacked; two rows of hollow dielectric members4provided in a line along the wall1care stacked; and two rows of hollow dielectric members4provided in a line along the wall1dare stacked. On the basis of the temperature information inputted from the temperature monitor200, the control unit100A or100B performs control to put any given hollow dielectric members4adjacent to each other among the multiple hollow dielectric members4, into the plasma state as the reflection mode. Further, the control unit performs control to put hollow dielectric members4other than the above, into the gas state in which the microwave is allowed to be transmitted. This causes the hollow dielectric members4to forma reflection surface. In the example ofFIG.12, a case is shown where a virtual reflection surface F is formed. Formation of a virtual reflection surface is controlled on the basis of the temperature information inputted from the temperature monitor200, so that the reflection direction of the microwave is controlled, and thus the heating region is controlled. It is possible to perform more effective heating control on the basis of the temperature information inputted from the temperature monitor200. As just described, according to another configuration in Embodiment 5, rows of hollow dielectric members4provided in a line along each of the walls1a,1b,1c,1dthat cross the wall at which the radiation element3is provided are provided, the rows along the corresponding one of walls1a,1b,1c,1dbeing stacked. The plasma control unit101controls the current to be applied to the electrodes42, in accordance with the control setting acquired by the data processing unit103, to thereby perform control of the hollow dielectric members4so that any given adjacent three or more of them are put into the plasma state in which the microwave is reflected, and hollow dielectric members4other than the three or more are put into the gas state in which the microwave is allowed to be transmitted. Accordingly, a virtual reflection surface matched with the temperature distribution in the heating chamber is formed, so that it is possible to perform heating region control matched with the temperature distribution. Thus, it is possible to perform more effective heating control matched with the temperature distribution. Embodiment 6 In Embodiment 6, a configuration in which a given region in the heating chamber1is heated intensively will be described. FIG.13is a lateral-side schematic view showing the configuration of a microwave heating device10A according to Embodiment 6. Note that, inFIG.13, a control unit100C is omitted from the illustration. FIG.14is a block diagram showing a configuration of the control unit100C in the microwave heating device10A according to Embodiment 6. The microwave heating device10A of Embodiment 6 is configured by the additional provision of a phase shifter24in the microwave generation unit2of the microwave heating device10shown in Embodiment 4. Further, it is configured by the provision of two radiation elements3. Furthermore, it is configured by the provision of the control unit100C instead of the control unit100A in the microwave heating device10shown in Embodiment 4. Note that, in the following, with respect to the parts same as or equivalent to the components of the microwave heating device10according to Embodiment 4, the same reference numerals as the reference numerals used in Embodiment 4 are given thereto, and description thereof will be omitted or simplified. A radiation element3aand a radiation element3bare provided at positions spatially apart from each other, and each radiate the microwave generated in the microwave generation unit2into the heating chamber1. The radiation elements3a,3bmay be of any type. Further, the number of thus-provided radiation elements3may be two or more, and multiple radiation elements3may be provided in a single straight line. To the radiation elements3a,3b, the phase shifter24in the microwave generation unit2is connected. The phase shifter24makes a difference in phase between the microwaves radiated from the respective radiation elements3a,3b. Because of the phase difference made by the phase shifter24, the radiation directions of the microwaves radiated from the radiation elements3a,3bare controlled at least in one direction. Since the heating chamber1is a closed space, a standing wave is generated therein, so that the beam of the microwave cannot be freely controlled. Thus, the plasma control unit101controls at least one of the hollow dielectric members4to be put into the plasma state as the absorption mode. Accordingly, a microwave in the heating chamber1is absorbed in the hollow dielectric member4. Because the microwave is absorbed, the standing wave in the heating chamber is suppressed, so that, in the heating chamber1, the beam of the microwave is controlled like in an open space. With reference toFIG.14, description will be made about details of the control unit100C. Like in Embodiment 4, a data processing unit103bin the control unit100C refers to the temperature information inputted from the temperature monitor200to thereby determine whether or not there is an unheated region in the region near the heating target X. When having determined that there is an unheated region in the region near the heating target X, the data processing unit103boutputs to the phase shifter24, a control instruction for causing it to make a difference in phase between the radiated microwaves. Further, when having outputted to the phase shifter24the control instruction for causing it to make a difference in phase between the radiated microwaves, the data processing unit103bacquires from the database104, a control setting for controlling at least one of the hollow dielectric members4to be put into the plasma state as the absorption mode. The database104stores control settings for the cases where a difference is made in phase between the microwaves by the phase shifter24. FIG.15is a top-side schematic view showing an internal configuration of the microwave heating device10A according to Embodiment 6. Hollow dielectric members4are provided in a line along each of the walls that cross a straight line extending in an alignment direction of the radiation elements3a,3b. In the example ofFIG.15, a case is shown where hollow dielectric members4aare provided in a line along the wall1athat crosses the straight line extending in the alignment direction of the radiation elements3a,3b, and hollow dielectric members4bare provided in a line along the wall1bthat crosses the straight line extending in the alignment direction of the radiation elements3a,3b. On the basis of the control setting acquired by the data processing unit103b, the plasma control unit101controls at least one of the hollow dielectric members4to be put into the plasma state as the absorption mode, and the other hollow dielectric members4to be put into the plasma state as the reflection mode. In the example ofFIG.15, a case is shown where, out of the row of the hollow dielectric members4aprovided along the wall1a, the plasma control unit101controls one hollow dielectric member4cto be put into the plasma state as the absorption mode, and the other hollow dielectric members4ato be put into the plasma state as the reflection mode. A case is also shown where, out of the row of hollow dielectric members4bprovided along the wall1b, the plasma control unit similarly controls one hollow dielectric member4dto be put into the plasma state as the absorption mode, and the other hollow dielectric members4bto be put into the plasma state as the reflection mode. By employing the configuration shown inFIG.15, the radiation direction of the microwave can be changed in the alignment direction of the radiation elements3a,3b. Next, hardware configuration examples of the control unit100C will be described. Note that the configuration that is the same as that in Embodiment 4 will be omitted from description. The data processing unit103bin the control unit100C corresponds to the processing circuit100ashown inFIG.9A, or the processor100bshown inFIG.9Bwhich executes programs stored in the memory100c. Next, description will be made about operations of the control unit100C. FIG.16is a flowchart showing the operations of the control unit100C in the microwave heating device10A according to Embodiment 6. Upon acquisition of the temperature information from the temperature monitor200(Step ST1), the data processing unit103brefers to a portion of the temperature information corresponding to the region near the heating target X, to thereby determine whether or not there is an unheated region (Step ST2). If there is an unheated region (Step ST2; YES), the data processing unit103boutputs to the phase shifter24, a control instruction for causing it to make a difference in phase between the microwaves radiated (Step ST21). Further, the data processing unit103brefers to the database104, to thereby acquire the control setting for the case where the difference is made in phase between the microwaves radiated from the radiation elements3a,3b(Step ST22). The data processing unit103boutputs the acquired control setting to the plasma control unit101. Thereafter, processing in the flowchart proceeds to Step ST4. On the other hand, if there is no unheated region (Step ST2; NO), processing proceeds to Step ST6. Other arrangement examples of the hollow dielectric members4in the microwave heating device10A will be described. The arrangement of the hollow dielectric members4in the microwave heating device10A may be determined freely if it is an arrangement capable of intensively heating the heating target X. FIG.17is a diagram showing another arrangement example of the hollow dielectric members4in the microwave heating device10A according to Embodiment 6.FIG.17is a top-side schematic view showing an internal configuration of the heating chamber1. In the foregoingFIG.13, the alignment direction of the radiation elements3a,3bis assumed to be one direction; however, a configuration may be employed in which two or more radiation elements3are aligned in each of mutually perpendicular straight lines. The phase shifter24makes a difference in phase between the microwaves radiated from the respective radiation elements3. Because of the phase differences made by the phase shifter24, the radiation direction of the microwave radiated from every radiation element3is controlled. In this case, as shown inFIG.17, hollow dielectric members4are provided in a line along each of: the walls1a,1bthat cross a straight line3A extending in the alignment direction of the radiation elements3a,3b; and the walls1c,1dthat cross a straight line3B extending in the alignment direction of the radiation elements3c,3d. Namely, a row of the hollow dielectric members4is provided along every wall that crosses the face at which the radiation elements3are provided (for example, the top face shown inFIG.13). Out of the hollow dielectric members4provided in a line along each of the walls1a,1b,1c,1d, the plasma control unit101controls at least one hollow dielectric member4to be put into the plasma state as the absorption mode. According to such a configuration, generation of the standing wave is suppressed on a plane that is parallel to the alignment plane of four or more radiation elements3, so that the microwaves are controlled two-dimensionally. This makes it possible to concentrate the microwave beams on a given point on the plane that is parallel to the plane on which the four or more radiation elements3are provided. FIG.18is a diagram showing another arrangement example of the hollow dielectric members4in the microwave heating device10A according to Embodiment 6.FIG.18is a top-side schematic view showing an internal configuration of the heating chamber1. InFIG.18, a case is shown where, hollow dielectric members4are provided in a line along each of the walls1a,1b,1c,1dof the heating chamber1and two rows of such hollow dielectric members provided in a line are stacked, to thereby form rows of hollow dielectric members4a,4b,4e,4f. Namely, two or more rows of hollow dielectric members4are provided along every wall that crosses the face at which the radiation elements3are provided (for example, the top face shown inFIG.13). On the basis of the control setting inputted from the data processing unit103b, the plasma control unit101makes a difference between current values for the respective rows of hollow dielectric members4a; a difference between current values for the respective rows of hollow dielectric members4b; a difference between current values for the respective rows of hollow dielectric members4e; and a difference between current values for the respective rows of hollow dielectric members4f. The plasma control unit101controls the rows of hollow dielectric members4so that the rows are put into the plasma states as the absorption modes with different absorption efficiencies. Specifically, the plasma control unit101sets a small current value for the hollow dielectric members4that form the row positioned nearer to the heating target X, and sets a large current value for the hollow dielectric members4that form the row positioned far from the heating target X. Accordingly, microwave absorption capability is enhanced and wave impedance matching is established with a region in which the heating target X is placed, so that it is possible to suppress the reflection of the microwave toward the center of the heating chamber1. This makes it possible to precisely control the beam of the microwave, and also to precisely control heating of the heating target X. As described above, according to Embodiment 6, two or more radiation elements3a,3bare provided, and the microwave generation unit2has the phase shifter24for making a difference in phase between the microwaves radiated by the two or more radiation elements3a,3b. Two or more hollow dielectric members4are provided in a line along each of the walls1a,1bthat cross the straight line extending in the alignment direction of the two or more radiation elements3a,3b. The plasma control unit101controls at least one hollow dielectric member4among the hollow dielectric members4, to be put into the plasma state in which the microwave is absorbed. Accordingly, the radiation direction of the microwave can be changed in the alignment direction of the radiation elements. Thus, it is possible to concentrate the beams of the microwaves on a region desired to be heated intensively, to thereby efficiently heat a region to be heated. In another aspect, according to Embodiment 6, two or more radiation elements3are aligned in a first alignment direction and other two or more radiation elements3are aligned in a second alignment direction, and the phase shifter24makes a difference in phase between the radiation elements3each provided in the corresponding one of the first alignment direction and the second alignment direction. Two or more hollow dielectric members4are provided in a line along each of the walls that cross a straight line extending in the first alignment direction, and two or more hollow dielectric members4are provided in a line along each of the walls that cross a straight line extending in the second alignment direction. The plasma control unit101controls, at least one hollow dielectric member4among the hollow dielectric members4provided along the walls1a,1bthat cross the straight line extending in the first alignment direction, and at least one hollow dielectric member4among the hollow dielectric members4provided along the walls1c,1dthat cross the straight line extending in the second alignment direction, to be put into the plasma state in which the microwave is absorbed. Accordingly, generation of the standing wave on the plane that is parallel to the alignment plane of the radiation elements can be suppressed. Thus, it is possible to concentrate the beams of microwaves on a given point on the plane that is parallel to the alignment plane of the radiation elements. In another aspect, according to Embodiment 6, rows of the hollow dielectric members4provided in a line along each of the walls1a,1bwhich cross the straight line extending in the first alignment direction are stacked, and rows of the hollow dielectric members4provided in a line along each of the walls1c,1dwhich cross the second alignment direction are stacked. Thus, it is possible to effectively suppress the standing wave generated in the heating chamber, so that the beams of the microwaves radiated into the heating chamber can be concentrated on the heating target. It is noted that, in the foregoing Embodiment 6, the description has been made using exemplary cases to be applied to the microwave heating device10according to Embodiment 4; however, this embodiment may be applied to the microwave heating device10according to Embodiment 5. Other than the above, unlimited combination of the embodiments, modification of any component in the embodiments and omission of any component in the embodiments may be made in the present invention, without departing from the scope of the invention. INDUSTRIAL APPLICABILITY It is preferable that the technique according to the invention be applied to a heating device or the like in which uneven heating is to be suppressed by using plasma. REFERENCE SIGNS LIST 1: heating chamber,1a,1b,1c,1d: wall,2: microwave generation unit,3,3a,3b: radiation element,4,4a,4b,4c,4d,4e,4f: hollow dielectric member,10,10A: microwave heating device,21: microwave oscillator,22: microwave amplifier,23: microwave-oscillation control unit,24: phase shifter,41: gas,42: electrode,100,100A,100B,100C: control unit,101: plasma control unit,102: current adjustment unit,103,103a,103b: data processing unit,104: database,105: update processing unit,200: temperature monitor. | 54,842 |
11862433 | DETAILED DESCRIPTION FIG.1shows a beam line ion implantation system that may be used with the inline surface engineering source according to one embodiment. The beam line ion implantation system may be used for processing a workpiece using a ribbon ion beam. The beam line ion implantation system includes an ion source100comprising a plurality of chamber walls defining an ion source chamber. In certain embodiments, the ion source100may be an RF ion source. In this embodiment, an RF antenna may be disposed against a dielectric window. This dielectric window may comprise part or all of one of the chamber walls. The RF antenna may comprise an electrically conductive material, such as copper. An RF power supply is in electrical communication with the RF antenna. The RF power supply may supply an RF voltage to the RF antenna. The power supplied by the RF power supply may be between 0.1 and 10 kW and may be any suitable frequency, such as between 1 and 100 MHz. Further, the power supplied by the RF power supply may be pulsed. In another embodiment, a cathode is disposed within the ion source chamber. A filament is disposed behind the cathode and energized so as to emit electrons. These electrons are attracted to the cathode, which in turn emits electrons into the ion source chamber. This cathode may be referred to as an indirectly heated cathode (IHC), since the cathode is heated indirectly by the electrons emitted from the filament. Other embodiments are also possible. For example, the plasma may be generated in a different manner, such as by a Bernas ion source, a capacitively coupled plasma (CCP) source, microwave or ECR (electron-cyclotron-resonance) ion source. The manner in which the plasma is generated is not limited by this disclosure. One chamber wall, referred to as the extraction plate, includes an extraction aperture. The extraction aperture may be an opening through which the ions1generated in the ion source chamber are extracted and directed toward a workpiece10. The workpiece10may be a silicon wafer, or may be another wafer suitable for semiconductor manufacturing, such as GaAs, GaN or GaP. The extraction aperture may be any suitable shape. In certain embodiments, the extraction aperture may be oval or rectangular shaped, having one dimension, referred to as the width (x-dimension), which may be much larger than the second dimension, referred to as the height (y-dimension). Disposed outside and proximate the extraction aperture of the ion source100are extraction optics110. In certain embodiments, the extraction optics110comprises one or more electrodes. Each electrode may be a single electrically conductive component with an aperture disposed therein. Alternatively, each electrode may be comprised of two electrically conductive components that are spaced apart so as to create the aperture between the two components. The electrodes may be a metal, such as tungsten, molybdenum or titanium. One or more of the electrodes may be electrically connected to ground. In certain embodiments, one or more of the electrodes may be biased using an electrode power supply. The electrode power supply may be used to bias one or more of the electrodes relative to the ion source so as to attract ions through the extraction aperture. The extraction aperture and the aperture in the extraction optics are aligned such that the ions1pass through both apertures. Located downstream from the extraction optics110may be a first quadrupole lens120. The first quadrupole lens120cooperates with other quadrupole lenses in the system to focus the ions1into an ion beam. Located downstream from the first quadrupole lens120is a mass analyzer130. The mass analyzer130uses magnetic fields to guide the path of the extracted ions1. The magnetic fields affect the flight path of ions according to their mass and charge. A mass resolving device150that has a resolving aperture151is disposed at the output, or distal end, of the mass analyzer130. By proper selection of the magnetic fields, only those ions1that have a selected mass and charge will be directed through the resolving aperture151. Other ions will strike the mass resolving device150or a wall of the mass analyzer130and will not travel any further in the system. A second quadrupole lens140may be disposed between the output of the mass analyzer130and the mass resolving device150. A collimator180is disposed downstream from the mass resolving device150. The collimator180accepts the ions1that pass through the resolving aperture151and creates a ribbon ion beam formed of a plurality of parallel or nearly parallel beamlets. The output, or distal end, of the mass analyzer130and the input, or proximal end, of the collimator180may be a fixed distance apart. The mass resolving device150is disposed in the space between these two components. A third quadrupole lens160may be disposed between the mass resolving device150and the input of the collimator180. A fourth quadrupole lens170may also be disposed between the mass resolving device150and the input of the collimator180. In certain embodiments, the quadrupole lenses may be disposed in other positions. For example, the third quadrupole lens160may be disposed between the second quadrupole lens140and the mass resolving device150. Additionally, one or more of the quadrupole lens may be omitted in certain embodiments. Located downstream from the collimator180may be an acceleration/deceleration stage190. The acceleration/deceleration stage190may be referred to as an energy purity module. The energy purity module is a beam-line lens component configured to independently control deflection, deceleration, and focus of the ion beam. For example, the energy purity module may be a vertical electrostatic energy filter (VEEF) or electrostatic filter (EF). The ions1exit the acceleration/deceleration stage190as an ion beam191and enter the end station200. The ion beam191may be a ribbon ion beam. The workpiece10is disposed in the end station200. Thus, the beam line ion implantation system comprises a plurality of components, terminating in an end station200. As described above, these components include the ion source100; the extraction optics110; the quadrupole lenses120,140,160,170; the mass analyzer130; the mass resolving device150; the collimator180; and the acceleration/deceleration stage190. It is noted that one or more of these components may not be included in the beam line ion implantation system. Further, while the above disclosure describes a ribbon ion beam, which has a width much greater than its height, other embodiments are also possible. For example, a scanned spot beam may enter the end station200. A scanned spot beam is an ion beam that is typically in the shape of a circle, which is scanned laterally to create the same effect as a ribbon ion beam. A controller195may be used to control the system. The controller195has a processing unit and an associated memory device. This memory device contains the instructions, which, when executed by the processing unit, enable the system to perform the functions described herein. This memory device may be any non-transitory storage medium, including a non-volatile memory, such as a FLASH ROM, an electrically erasable ROM or other suitable devices. In other embodiments, the memory device may be a volatile memory, such as a RAM or DRAM. In certain embodiments, the controller195may be a general purpose computer, an embedded processor, or a specially designed microcontroller. The actual implementation of the controller195is not limited by this disclosure. FIG.2shows an end station200according to one embodiment. As described above, the workpiece10is disposed in the end station200. The ion beam191enters the end station200and is directed toward the workpiece10. The workpiece10may be held by a platen210. The platen210may be capable of rotation about an axis perpendicular to the front surface of the platen210. The platen210may also be capable of rotation about an axis211parallel to the front surface of the platen210. Additionally, the platen210may be capable of linear motion along direction212. Of course, the platen210may also have less than all of these capabilities. Disposed in the end station200and proximate the ion beam191may be a plasma flood gun220. A plasma flood gun220is used to emit low energy electrons to reduce space charge blowup and to neutralize the workpiece10. Of particular note, the plasma flood gun220is only used to emit a net negatively charged flux in the form of electrons from a plasma formed of a rare or non-reactive gas, and not other plasma species such as atomic or molecular radicals from molecular dissociation. In other words, the plasma flood gun220uses an inert gas, such as xenon to emit electrons. The plasma flood gun220is not intended to change the properties of the workpiece10. In one embodiment, the plasma flood gun220may comprise a plasma chamber221that has a substantially metal-free inner surface. A radio-frequency coil222may be disposed within the plasma chamber221for directly exciting a gas enclosed in the chamber, thus creating and maintaining a desired plasma. The plasma chamber221may have, on one side, an elongated exit aperture223through which the plasma can flow out of the plasma chamber221and into engagement with the ions of ion beam191. A series of magnets224may be disposed about the plasma chamber221to contain and control the plasma created therein. In particular, the magnets224may be positioned outside the walls of the plasma chamber221and their respective magnetic fields extend through the wall of the plasma chamber221. More specifically, the interior portions of the plasma chamber221may be made out of a non-metallic conductive material such as graphite or silicon carbide (SiC). A feed-through gas pipe may be provided in a sidewall of the plasma chamber221through which one or more gaseous substances may be supplied to the plasma chamber221. The gaseous substances may include inert gases such as xenon (Xe), argon (Ar) or Krypton (Kr). The gas pressure is typically maintained in a range of 1-50 mTorr. The radio-frequency coil222may have an elongated shape that extends generally through the center of the plasma chamber221. One end of the radio-frequency coil222may be connected to an RF power supply, which may inductively couple RF electrical power in the plasma chamber221. The RF electrical power may operate at typical frequencies, such as, for example, 2 MHz, 13.56 MHz and 27.12 MHz. The radio-frequency coil222may be completely enclosed within the plasma chamber221. In a sidewall of the plasma chamber, the exit aperture223is positioned to allow the generated plasma to flow into contact with the ion beam191. For a ribbon-shaped ion beam, the exit aperture223may cover substantially the ribbon width. According to one embodiment, it may be desirable for the plasma from the plasma flood gun220to form a plasma bridge with an ion beam191passing just outside the plasma chamber221. As previously noted, the plasma chamber221may include a series of magnets224, such as either permanent magnets or electromagnets, arranged to contain and control the plasma created within the plasma chamber221. The characteristics of these magnets224can also be arranged to control the characteristics of the plasma as it exits the plasma chamber221through the exit aperture223. In other embodiments, the plasma flood gun220may be a Bernas type ion source, where a filament is used to produce thermoionic emission. A gas, such as argon is introduced into the plasma chamber. The emitted electrons are used to excite a plasma within the plasma chamber. The electrons from the plasma are then extracted from the plasma chamber through the exit aperture. In other words, the plasma flood gun220may be constructed in various ways and its implementation is not limited by this disclosure. Thus, the electrons from the plasma flood gun220may be confined by a magnetic field to direct their path toward the ion beam191. In certain embodiments, a plasma flood gun220may not be used. An auxiliary plasma source270is disposed within the end station200. Unlike the plasma flood gun220, the auxiliary plasma source270is used to emit ions and/or radicals into the area proximate the workpiece10through one or more exit apertures275. As is well known, a radical is a molecular or atomic species that has an unpaired valence electron. Consequently, radicals are typically highly reactive. Radicals are typically created by the disassociation of larger molecules in the auxiliary plasma source270. In certain embodiments, the auxiliary plasma source270is disposed within 30 cm of the workpiece10, although other embodiments are possible. While the auxiliary plasma source270is illustrated as being cylindrical, it is understood that this is merely illustrative, and the auxiliary plasma source270may be any shape. In certain embodiments, a heater240may also be disposed in the end station200. The heater240may be located near the auxiliary plasma source270, such that both heater240and auxiliary plasma source270are disposed on the same side of the ion beam191. The heater240may be any suitable device, including heat lamps, LEDs, or resistive heaters. WhileFIG.2shows the auxiliary plasma source270disposed between the ion beam191and the heater240, other configurations are also possible. For example, the heater240may be disposed between the ion beam191and the auxiliary plasma source270. In another embodiment, the heater240and the auxiliary plasma source270may be disposed on opposite sides of the ion beam191. In one embodiment, shown inFIG.3A, the auxiliary plasma source270comprises an outer housing231, which may be cylindrical, although other shapes are also possible. The outer housing231may be constructed of aluminum or some other suitable material. Within the outer housing231is an antenna232, which may be surrounded by a protective cover233. The antenna232may be constructed of a conductive material, such as a metal and may be U-shaped. The antenna232is coated with, or coaxial within, a protective cover233, which may be a ceramic material to protect the antenna232from the plasma274generated within the auxiliary plasma source270. The outer housing231includes one or more exit apertures275, through which the plasma274exits the auxiliary plasma source270and enters the end station200. In operation, a process gas is introduced into the volume defined by the outer housing231. The antenna232is energized using an RF power source235. This energy creates a plasma274within the auxiliary plasma source270. The plasma274then exits the auxiliary plasma source270via one or more exit apertures275. FIG.3Bshows the auxiliary plasma source270according to another embodiment. In this embodiment, the auxiliary plasma source270has the antenna252disposed outside the outer housing251. The antenna252is energized using an RF power source255. For example, the wall proximate to the antenna252may be a dielectric material so that energy from the antenna252passes through the wall and into the volume defined by the outer housing251. A process gas is introduced into this volume and when energized, creates a plasma274. The plasma274then exits the auxiliary plasma source270via one or more exit apertures275. Other types of devices may be used for the auxiliary plasma source270. For example, an indirectly heated cathode (IHC) ion source may be used. Alternatively, a Bernas source may be used. In another embodiment, an inductively coupled plasma (ICP) or capacitively coupled plasma (CCP) source may be used. Thus, the auxiliary plasma source270is not limited to those shown inFIGS.3A-3B. In certain embodiments, such as that shown inFIG.4A, the auxiliary plasma source270may be oriented such that the one or more exit apertures275emit the plasma274toward the workpiece10at the location where the ion beam191strikes the workpiece10. In this way, the ion beam191cooperates with the plasma274to process the workpiece10. For example, the ions and radicals in the plasma274may deposit on the workpiece10in the area that is being exposed to the ion beam191. As described with respect toFIG.2, the end station200may include a plasma flood gun220and/or a heater240, if desired. FIG.4Bshows the end station200according to another embodiment. In this embodiment, the auxiliary plasma source270is oriented such that the one or more exit apertures275are directly facing the workpiece10. In this way, the flow of plasma274is parallel to the ion beam191. As described with respect toFIG.2, the end station200may include a plasma flood gun220and/or a heater240, if desired In the embodiments shown inFIGS.4A-4B, a process gas may be introduced into the auxiliary plasma source270. The antenna is energized, such as through the use of a RF power supply. The energy in the antenna causes the process gas within the auxiliary plasma source270to ionize and form a plasma274. This plasma274then exits through the one or more exit apertures275toward the workpiece10. In certain embodiments, a voltage difference may exist between the auxiliary plasma source270and the workpiece10. For example, the auxiliary plasma source270may be biased more positively than the workpiece10. In some embodiments, the auxiliary plasma source270may be biased 0-5000V more positive than the workpiece10. In certain embodiments, the auxiliary plasma source270may be biased between 0-500V more positive than the workpiece10. In this embodiment, positive ions within the auxiliary plasma source270are accelerated toward the workpiece10. Alternatively, the auxiliary plasma source270may be biased more negatively than the workpiece10. In this embodiment, positive ions within the auxiliary plasma source270are somewhat repelled by the workpiece10. In other embodiments, the auxiliary plasma source270may be at the same potential as the workpiece10so that the ion and radical flux from the auxiliary plasma source270simply drifts through the one or more exit apertures275. In the embodiment shown inFIG.4A, as the platen210moves upward along direction212, a portion of the workpiece10is exposed to the ion beam191and the plasma274from the auxiliary plasma source270. After this exposure, that portion of the workpiece10may next be heated by the heater240. In the embodiment shown inFIG.4B, the workpiece10is first processed by the ion beam191and then by the plasma274when moving upward. After being exposed to the ion beam191and the plasma274, the workpiece10may then be subjected to a thermal process by the heater240. The use of heat following a treatment by the ion beam191and/or the plasma274may have beneficial applications. It is noted that any type of auxiliary plasma source may be employed in the configurations shown inFIGS.4A-4B. Thus, the choice of type of auxiliary plasma source270and its orientation are design decisions based on the process being performed and other considerations. The flow rate of the process gas into the auxiliary plasma source270as well as the energy applied by the antenna are factors in determining the number of radicals and ions that are extracted from the auxiliary plasma source270. In certain embodiments, the process gas is diluted with an inert gas to maintain the plasma or to reduce the number of radicals and ions of the desired species for process control. WhileFIG.1is described in connection with ion implantation, it is understood the end station200can be utilized with any semiconductor processing system. Having described a semiconductor processing system with a source engineering source, various applications of this semiconductor processing system will be described. In one embodiment, the semiconductor processing system ofFIG.1, using the configuration shown inFIG.4A, may be used to perform an ion implantation process. As described above, the end station ofFIG.4Adirects the plasma274from the auxiliary plasma source270toward the workpiece10at the location where the ion beam191impacts the workpiece10. In this way, there is interaction between the ion beam191and the plasma274simultaneous with the surface of workpiece10. In this embodiment, a target species is desired to be implanted into the workpiece10. For example, the target species may be a Group III element, a Group IV element, or a Group V element. For example, in one embodiment, arsenic may be the desired species. The desired species is introduced into the auxiliary plasma source270. The desired species may be introduced in the form of a molecule containing the target species. This desired species is energized to form a plasma274. As shown inFIG.5, the plasma274diffuses toward the workpiece10near the location where the ion beam191impacts the workpiece10. Ions and radicals from the plasma274may become disposed on the surface of the workpiece10, such as in the form of a film277. A gas, such as argon, xenon or krypton, is introduced into the ion source100(seeFIG.1) and used to create the ion beam191. In certain embodiments, the gas may be an inert species, defined as a Group VIII element, such as neon, argon, xenon, or krypton. The ion beam191collides with the ions and radicals from the plasma274that are proximate to or have been deposited as a film277on the workpiece10. These collisions transfer much of the energy from the ions in the ion beam191to the ions and radicals from the plasma274. This causes the ions and radicals from the plasma274to acquire the velocity needed to penetrate the surface of the workpiece10. Thus, the energy of the ions in the ion beam191is imparted to the ions and radicals from the plasma274. This allows the ions and radicals in film277to be driven into the workpiece10. In this embodiment, the ion beam191is used to knock in ions and radicals from the plasma274. Thus, unlike conventional ion implanters, the ions in the ion source100are used to provide energy to drive in the ions and radicals that are generated in the auxiliary plasma source270in the end station200. Thus, in this embodiment, the ion beam191is used to provide the energy, while the auxiliary plasma source270is used to supply the desired species. While the above description uses inert gasses and arsenic, these are purely illustrative and the disclosure is not limited to this embodiment. The ion beam191may be made from any species of ions. In some embodiments, certain species, such as inert elements or Group IV elements, may be used so that the ion beam does not affect the conductivity of a silicon wafer. The target species may be any desired species, including Group III elements, such as boron and gallium, and Group V elements, such as phosphorus and arsenic. In certain embodiments, the Group III elements and Group V elements may be combined with other elements to form molecules, such as BF3, AsH3, PH3, and others. In another embodiment, the semiconductor processing systems described herein may be used for an etching process. Specifically, the use of an auxiliary plasma source270may allow the creation of more chemically active radicals proximate the workpiece. In this case, the auxiliary plasma source270is used to create ions, radicals, and metastable neutrals of an etching chemistry, such as Group VII elements and molecules containing these elements. These ions and metastable neutrals exit the auxiliary plasma source270and drift toward the workpiece10. Because the ions from the auxiliary plasma source270have low energy, these ions deposit at or near the surface of the workpiece10. In one particular embodiment, a halogen containing gas is introduced into the auxiliary plasma source270to generate ions. The low energy ions and radicals that exit the auxiliary plasma source270may form a thin film on the surface of the workpiece10. This thin film reacts with the workpiece10to etch it with energy provided by the ion beam191. In certain embodiments, the ion beam191may comprise an inert gas, such as argon. In one embodiment, the embodiment ofFIG.4Ais used such that the ion beam191is directed toward the portion of the workpiece10while the film is being formed. In another embodiment, the embodiment ofFIG.4Bis used such that the ion beam191is directed toward the portion of the workpiece10after the film has been formed. In another particular embodiment, CF4and oxygen are ionized and dissociated in the auxiliary plasma source270. An ion beam191comprised of an inert gas, such as argon, is used to etch the surface of the workpiece10. In yet another particular embodiment, a native oxide layer may form on the surface of the workpiece10. This native oxide layer may be etched by ionizing hydrogen in the auxiliary plasma source270. An ion beam comprised of an inert gas, such as argon, is used to etch the native oxide from the surface of the workpiece10. In another embodiment, the semiconductor processing system ofFIGS.1-4may be used for deposition. The material to be deposited may be ionized in the auxiliary plasma source270. The material may be a dopant or may be a material that is used as a coating for the workpiece10. Ions and radicals from that material exit the auxiliary plasma source270and drift toward the workpiece10, where they are deposited on the surface of the workpiece10. In one particular embodiment, the process gas may be CH4, while the ion beam191comprises a Group IV element, such as carbon. This allows a more box-like profile in the workpiece10. In contrast, the use of the ion beam191alone creates a retrograde profile. Thus, in applications where the ion beam191and the auxiliary plasma source270are used concurrently, the ion beam191may be used to perform at least one of two functions. First, the ion beam191may supply the energy needed to drive the ions or radicals from the auxiliary plasma source270toward and into the workpiece10. One example of this is the use of the ion beam191to knock the ions from the plasma274into the workpiece10, as shown inFIG.5. Second, the ion beam191may supply additional species to facilitate or cause chemical reactions at the surface of the workpiece10. This may be accomplished in a number of ways. First, the ion beam191may weaken the bonds of the underlying workpiece10so that the surface of the workpiece10can react with deposited layer. Second, the ion beam191may intermix the deposited layer into the underlying workpiece10for more reactions. Third, the ion beam191may liberate or volatilize the new formed compound made from the deposited layer and the workpiece10. The sputter yield of this newly formed compound may be much higher than the sputter yield of the ion beam191on the workpiece10alone. For example, in an etching process, CF4and oxygen radicals create a CFx polymer type material with the silicon nitride on the surface of the workpiece10. The resulting SiFxCy compound is volatized by the energy of the ion beam191. In yet another embodiment, the use of the auxiliary plasma source270and the ion beam191may not be concurrent. For example, the workpiece10may be processed by one of these sources and then processed by the other of these sources at a later time. For example, in one embodiment, the auxiliary plasma source is used to provide a pre-treatment of the workpiece10. A flowchart of this process is shown inFIG.6. In this embodiment, the embodiment ofFIG.4AorFIG.4Bmay be used since the ion beam191is not active during the pre-treatment. First, as shown in Process500, the ion beam191is disabled. One or more etching species, such as ammonia (NH3) and NF3, are introduced into the auxiliary plasma source270, as shown in Process510. The auxiliary plasma source270creates ions and other radicals. These ions and radicals exit the auxiliary plasma source270and drift toward the workpiece10, where they react with the silicon oxide layer of the workpiece10, as shown in Process520. The workpiece10is scanned so that the portion of the workpiece10that was exposed to the ions and radicals is then heated by the heater240, as shown in Process530. The heat serves to sublime the reacted silicon oxide that is created on the surface of the workpiece10, as shown in Process540. This process is repeated until the surface of the workpiece10is cleaned. After this, the workpiece10may be subjected to another process by the ion beam191, as shown in Process550. Advantageously, the workpiece10remains in the end station200for the entirety of the pre-treatment and the second process shown in Process550. In other words, the workpiece10does not leave the end station between the pre-treatment and the second process. In another embodiment, the process described above can be performed when a workpiece10is not disposed on the platen210. In this embodiment, this process may serve to clean the platen210. In another embodiment, the auxiliary plasma source270is used in the post-treatment of a workpiece10. For example, a post treatment may be used to either passivate the surface of the workpiece10or to recover the damage caused by an ion implantation process. A flowchart of this is shown inFIG.7. First, as described above, the workpiece10is processed using the ion beam191. The process gas is then introduced into the auxiliary plasma source270, as shown in Process610. The process gas may comprise a hydrogen/nitrogen mixture. Ions and radicals from the auxiliary plasma source270are directed toward the surface of the workpiece10, as shown in Process620. The workpiece10is scanned past the heater240, at a temperature of, for example, between 100° C.-500° C., as shown in Process630. The damage recovery has been shown to work with forming gas at reduced temperature and is referred to as a plasma anneal. The passivation occurs from having radicals of hydrogen or nitrogen react with the dangling bonds of the surface, as shown in Process640. In one embodiment, the post-treatment shown inFIG.7is performed while the ion beam191is disabled. In another embodiment, the post-treatment may be performed using the embodiment shown inFIG.4B. Specifically, the workpiece10implanted by ion beam191. As the workpiece10is moved upward in direction212, the implanted portion is then exposed to the process gas from the auxiliary plasma source270. After this, that implanted portion is then heated. Thus, in this embodiment, the workpiece10is implanted by the ion beam191and post-treated during a single scan of the workpiece10. In other words, one portion of the workpiece is exposed to the ion beam while a second portion of the workpiece, different from the first portion, is exposed to the plasma. Thus, the present disclosure describes a semiconductor processing system where a source of ions and radicals is incorporated in the end station200. Conventionally, great efforts are made to ensure that no ions or radicals are introduced in the end station200. Specifically, plasma flood guns220are designed to insure that mostly electrons are emitted into the end station200. The present semiconductor processing system deliberately introduces ions and radicals into the end station200. In certain embodiments, these ions and radicals are introduced concurrently with the use of an ion beam191to perform applications that are not otherwise possible. While the above disclosure describes the use of an auxiliary plasma source270with a beam line ion implantation system, other embodiments are also possible. For example,FIG.8shows such an example. In this figure, the semiconductor processing system includes an ion source chamber700, comprised of a plurality of chamber walls701. In certain embodiments, one or more of these chamber walls701may be constructed of a dielectric material, such as quartz. An RF antenna710may be disposed on an exterior surface of a first dielectric wall702. The RF antenna710may be powered by a RF power supply720. The energy delivered to the RF antenna710is radiated within the ion source chamber700to ionize a feed gas, which is introduced via gas inlet730. In other embodiments, the gas is ionized in a different manner, such as through the use of an indirectly heated cathode (IHC), a capacitively coupled plasma source, an inductively coupled plasma source, a Bernas source or any other plasma generator. One chamber wall, referred to as the extraction plate740, includes an extraction aperture745through which ions may exit the ion source chamber700. The extraction plate740may be constructed of an electrically conductive material, such as titanium, tantalum or another metal. The extraction plate740may be in excess of 300 millimeters in width. Further, the extraction aperture745may be wider than the diameter of the workpiece10. In certain embodiments, extraction optics750, such as an electrode, may be disposed outside the extraction aperture745to accelerate ions generated within the ion source chamber700toward the workpiece10. The platen760is disposed outside the ion source chamber700proximate the extraction aperture745. The workpiece10is disposed on the platen760. The auxiliary plasma source270may be as described with respect toFIG.3Ain certain embodiments. In other embodiments, the auxiliary plasma source270may be as described with respect toFIG.3B. Further, the exit apertures275of the auxiliary plasma source270may be oriented as shown inFIG.4A or4B. In certain embodiments, a plasma flood gun220may be utilized. The plasma flood gun220functions as described above. All of the processes described herein may be performed using the configuration shown inFIG.8. The semiconductor processing system and method described herein have many advantages. In the case of implantation using knock in, the depth of the implantation may be more tightly controlled. Further, when a molecule, such as AsH3is implanted, the depth of the hydrogen ions may be better controlled using knock in. There are additional benefits associated with the utilization of knock in. First, the straggle from the implanted ions may be reduced due to the deposited film absorbing energy. This is beneficial for an application such as the source/drain extension where lateral straggle may cause short channel effects under the gate. Second, the resultant dopant profile becomes surface peaked, which would create a surface peaked carrier concentration. This is beneficial for applications such as contact where the near surface is consumed by the silicide process, and low contact resistance in this region is desirable. Third, the impending ions may sputter the deposited film to adjacent fin structures improving the sidewall doping of fins. In the case of etching, the use of an auxiliary plasma source270allows for the removal of a native oxide layer in the same end station as a subsequent process is performed in. An additional benefit of this configuration in etching and deposition applications is the ability to treat or create thicker films while maintaining low energy by a sequential process. Low energy may be useful so that unwanted sputtering or damage of underlying layers is prevented. In the case of sequential operation, the use of an auxiliary plasma source270in the end station eliminates the need to transport the workpiece after a pre-treatment cleaning process. This also reduces the amount of time between the cleaning and the process (i.e. deposition, implantation, etching). For example, if the application is sensitive to native oxide layers, a reduction in the time between cleaning the surface of the workpiece to subjecting the workpiece to the desired process minimizes the regrowth of the native oxide layer. The present disclosure is not to be limited in scope by the specific embodiments described herein. Indeed, other various embodiments of and modifications to the present disclosure, in addition to those described herein, will be apparent to those of ordinary skill in the art from the foregoing description and accompanying drawings. Thus, such other embodiments and modifications are intended to fall within the scope of the present disclosure. Furthermore, although the present disclosure has been described herein in the context of a particular implementation in a particular environment for a particular purpose, those of ordinary skill in the art will recognize that its usefulness is not limited thereto and that the present disclosure may be beneficially implemented in any number of environments for any number of purposes. Accordingly, the claims set forth below should be construed in view of the full breadth and spirit of the present disclosure as described herein. | 36,519 |
11862434 | DETAILED DESCRIPTION Hereinafter, the inventive concept and methods of accomplishing the same may be understood more readily by reference to the following detailed description of embodiments and the accompanying drawings. However, the inventive concept may be embodied in many different forms, and should not be construed as being limited to the embodiments set forth herein. Rather, these embodiments are provided so that this inventive concept will be thorough and complete and will fully convey the concept of the invention to those skilled in the art, and the inventive concept will only be defined by the appended claims. Unless defined otherwise, all terms used herein, including technical or scientific terms, have the same meaning as commonly understood by one of ordinary skill in the art to which this invention belongs. Terms such as those defined in commonly used dictionaries should be interpreted as having a meaning that is consistent with their meaning in the context of the relevant art and are not to be interpreted in an idealized or overly formal sense unless expressly so defined herein. The term used herein describes the embodiment of the present disclosure and not be limited to the present disclosure. As used herein, the singular forms “a”, “an”, and “the” are intended to include plural referents as well, unless the context clearly indicates otherwise. It will be further understood that the terms “comprise” and/or various conjugational forms of this verb, such as “comprisal”, “comprising”, “comprised”, do not preclude the presence or addition of one or more other constructions, components, devices, steps, actions. The term “and/or” in this description refers to each of the configuration or to various combinations thereof. The term used herein “part”, which processes at least one function or operation, for example, may mean software devices and hardware devices such as FPGA, or ASIC. However, “part” does not be limited by software or hardware. “part” may be composed of an addressable storage medium, or one or more processors running thereof. According to one exemplary embodiment of the inventive concept, “part” may include devices such as software devices, object-oriented software devices, class devices, and processes, functions, attributes, procedures, sub-routines, segments of program codes, drivers, firmware, microcode, circuits, data, databases, data structure, tables, arrays, and variables. Functions from devices and “part” may be separately performed by the plurality of devices and “part”, or be combined with additional devices. Hereinafter, embodiments of the inventive concept are described with reference toFIG.1toFIG.10. FIG.1schematically shows a substrate treating apparatus of the inventive concept. Referring toFIG.1, a substrate treating equipment1has an equipment front end module (EFEM)20and a treating module30. The EFEM20and the treating module30are arranged in a direction. The EFEM20has a load port10and a transfer frame21. The load port10is arranged in front of the EFEM20along a first direction11. The load port10has a plurality of support parts6. Each support part6is arranged in parallel along a second direction12, and a carrier4(e.g. a cassette player, FOUP) is mounted. The carrier receives a substrate ‘W’ to be processed and a substrate ‘W’ processed. The transfer frame21is arranged between the load port10and the treating module30. The transfer frame21comprises a first transfer robot25, the first transfer robot is arranged inside the transfer frame21and transfers the substrate ‘W’ between the load port10and the treating module30. The first transfer robot25moves along a transfer rail27installed along the second direction12, and the first transfer robot25transfers the substrate ‘W’ between the carrier4and the treating module30. The treating module30comprises a load lock chamber40, a transfer chamber50, and a process chamber60. The load lock chamber40is adjacently arranged to the transfer frame21. In one example, the load lock chamber40is arranged between the transfer chamber50and the EFEM20. Before the substrate ‘W’ to be processed is transferred to the process chamber60or the substrate ‘W’ processed is transferred to the EFEM20, the load lock chamber40provides a space where the substrate ‘W’ stands by. The transfer chamber50is adjacently arranged to the load lock chamber40. When viewed from above, the transfer chamber50is a polygon. Referring toFIG.1, when viewed from above, the transfer chamber50is a pentagon. At the outside of the transfer chamber50, the load lock chamber40and a plurality of process chambers60are arranged along a perimeter of the transfer chamber50. A passage (not shown) where the substrate ‘W’ is introduced and withdrawn is formed at each side walls of the transfer chamber50, the passage (not shown) connects the transfer chamber50and the load lock chamber40or connects process chambers60. Each passage has a door (not shown) which opens and closes the passage to seal the inside of the transfer chamber. A second transfer robot53is arranged inside of the transfer chamber50. The second transfer robot53transfers the substrate ‘W’ between the load lock chamber40and the process chambers60. The second transfer robot53transfers an untreated substrate ‘W’ which is stood by in the load lock chamber40to the process chamber60, or transfers a treated substrate ‘W’ to the load lock chamber40. And the second transfer robot53transfers the substrate ‘W’ among process chambers60for providing the substrate ‘W’ sequentially to the plurality of process chambers60. LikeFIG.1, when the transfer chamber50is a pentagon, the load lock chamber40is arranged at a side wall of the transfer chamber50which is adjacent to the EFEM20, and process chambers60are arranged sequentially at the other wall. The transfer chamber50may have various shape according to a requirement of a process module other than the above shape. The process chambers60are arranged along a perimeter of the transfer chamber50. A plurality of the process chambers60may be provided. In each process chamber60, a process treatment of the substrate ‘W’ is performed. In the process chamber60, the substrate ‘W’ is treated by receiving from the second transfer robot53, and the treated substrate ‘W’ is provided to the second transfer robot53. The process treatment of each process chamber60may be different. Hereinafter, a substrate treating apparatus1000performing a plasma treating process will be described. FIG.2shows a substrate treating apparatus performing a plasma treating process of a process chamber of theFIG.1. Referring toFIG.2, a substrate treating apparatus1000performs a predetermined process on the substrate ‘W’ using the plasma. For example, the substrate treating apparatus1000may etch or ash a thin film on the substrate ‘W’. The thin film may comprise a polysilicon film, a silicon oxide film, and a silicon nitride film. In addition, the thin film may be a native oxide film or a chemically generated oxide film. The substrate treating apparatus1000have a process treating unit200, a plasma generating unit400, and an exhaust unit600. The process treating unit200provides a treating space212in which a substrate ‘W’ is placed and the treating space212treats the substrate ‘W’. The plasma generating unit400discharges the process gas to generate the plasma, and supplies the plasma to the treating space212of the process treating unit200. The exhaust unit600discharges the process gas remaining in the process treating unit200and/or the reacted by-products generated in the substrate treating process to the outside, and the exhaust unit600maintains a pressure in the process treating unit200at a set pressure. The process treating unit200may comprise a housing210, a support unit230, and a baffle250. The housing210may have the treating space212therein, which performs the substrate treating process. An upper portion of the housing210is opened, and an opening (not shown) may be formed on side walls of the housing210. The substrate ‘W’ enters into the housing210via the opening (not shown). A door (not shown) which is kind of an open and close member may open and close the opening (not shown). In addition, an exhaust hole214is formed on a bottom surface of the housing210. The process gas and/or by-products in the treating space212may be exhausted to the outside via the exhaust hole214. The exhaust hole214may be connected to the configuration of the exhaust unit600, which will be described hereinafter. The support unit230supports the substrate ‘W’ in the treating space212. The support unit230may comprise a support plate232, and a support shaft234. The support plate232supports the substrate ‘W’ in the treating space212. The support plate232is supported by the support shaft234. The support plate232is connected to an external power source and generates static electricity by the applied power. The electrostatic force of static electricity may fix the substrate ‘W’ to the support unit230. The support shaft234may move an object. For example, the support shaft234may move the substrate ‘W’ up and down. For example, the support shaft234may be coupled to the support plate232, and may move the support plate232up and down to move the substrate ‘W’. The baffle250is positioned above the support unit230to face the support unit230. The baffle250may be arranged between the support unit230and the plasma generating unit400. The plasma generated from the plasma generating unit400may pass through a plurality of holes252formed in the baffle250. The baffle250allows the plasma entering the treating space212to be uniformly supplied to the substrate ‘W’. The holes252formed in the baffle250are provided in through-holes provided from the upper surface to the lower surface of the baffle250, and the holes252may be uniformly formed in each area of the baffle250. The plasma generating unit400may be positioned at the upper portion of the housing210. The plasma generating unit400generates the plasma by discharging the process gas, and supplies the generated plasma to the treating space212. The plasma generating unit400may comprise a plasma chamber410, a gas supply unit420, a power supply unit430, and a diffusion chamber440. An upper and a lower surface of the plasma chamber410may be opened. The plasma chamber410may be container having opened upper and lower surfaces. The plasma chamber410may be cylindrical shaped container having opened upper and lower surfaces. The plasma chamber410may have a plasma generating space412. In addition, a material of the plasma chamber410may comprise aluminum oxide (Al2O3). The upper surface of the plasma chamber410may be sealed by a gas supply port414. The gas supply port414may be connected to the gas supply unit420. The process gas may be supplied to the plasma generating space412through the gas supply port414. The gas supplied to the plasma generating space412may be introduced into the treating space212through the baffle250. The gas supply unit420may supply a process gas. The gas supply unit420may be connected to the gas supply port414. The process gas supplied by the gas supply unit420may comprise fluorine and/or hydrogen. The power supply unit430applies RF power to the plasma generating space412. The power supply unit430may be a plasma source that excites a process gas in the plasma generating space412to generate a plasma. The power supply unit430may comprise an antenna432, and a power source434. The antenna432may be an inductively coupled plasma (ICP) antenna. The antenna432may be provided in a coil shape. The antenna432may be wound multiple times on the plasma chamber410outside the plasma chamber410. The antenna432may be wound multiple times in a spiral shape on the plasma chamber410outside the plasma chamber410. The antenna432may be wound on the plasma chamber410in an area corresponding to the plasma generating space412. When viewed from a front cross section of the plasma chamber410, a height of one end of the antenna432may correspond to an upper portion of the plasma chamber410. When viewed from the front cross section of the plasma chamber410, a height of an opposite end of the antenna432may correspond to the lower portion of the plasma chamber410. The power source434may apply power to the antenna432. The power source434may apply a high frequency alternating current to the antenna432. The high frequency alternating current applied to the antenna432may form an inductive electric field in the plasma generating space412. The process gas supplied into the plasma generating space412may be converted to a plasma state by obtaining an energy required for ionization from the inductive electric field. Also, the power source434may also be connected to the one end of the antenna432. The power source434may be connected to one end of an antenna432, a height of the antenna432corresponds to the upper portion of the plasma chamber410. In addition, an opposite end of the antenna432may be grounded. The opposite end of the antenna432may be grounded, a height of the antenna432corresponds to the lower portion of the plasma chamber410. However, the power source434may be connected to the opposite end of the antenna432and the one end of the antenna432may be grounded. The diffusion chamber440may diffuse the plasma generated in the plasma chamber410. The diffusion chamber440may be arranged below the plasma chamber410. An upper portion and a lower portion of the diffusion chamber440may be opened. The diffusion chamber440may be an inverted funnel shape. The upper portion of the diffusion chamber440may have a diameter corresponding to the plasma chamber410. The lower portion of the diffusion chamber440may have a larger diameter than the upper portion of the diffusion chamber440. The lower portion diameter of the diffusion chamber440may be larger than the upper portion diameter. Also, the diffusion chamber440may have a diffusion space442. The plasma generated in the plasma generating space412may diffuse through the diffusion space442. The plasma introduced into the diffusion space442may be introduced into the treating space412through the baffle250. The exhaust unit600may exhaust process gases and by-products from the process treating unit200to the outside. The exhaust unit600may exhaust by-products generated in the process of treating the substrate ‘W’ to the outside of the substrate treating apparatus1000. The exhaust unit600may exhaust process gases supplied into the treating space212to the outside. The exhaust unit600may comprise an exhaust line602and a decompression member604. The exhaust line602may be connected to an exhaust hole214formed on the bottom surface of the housing210. Also, the exhaust line602may be connected to a decompression member604that provides decompression. Thus, the decompression member604may provide decompression to the treating space212. The decompression member604may be a pump. The decompression member604can discharge the plasma and by-products remaining in the treating space212to the outside of the housing210. In addition, the decompression member604may provide a decompression to maintain the pressure of the treating space212at a predetermined pressure. FIG.3shows a plasma chamber according to an embodiment of the inventive concept. Referring toFIG.3, a first coating film C1may be provided on inside walls of the plasma chamber410. The first coating film C1may cover the inside walls of the plasma chamber410. The first coating film C1may be provided on the inside walls of the plasma chamber410. The first coating film C1may be provided with the same thickness on the entire inside walls of the plasma chamber410. The first coating film C1may comprise yttrium fluoride (YF3). The first coating film C1may be coated on the inside walls of the plasma chamber410by a method of an atmospheric plasma spray (APS). However, the first coating film C1may be coated on the inside walls of the plasma chamber410by a method of an aerosol or a cold spray. FIG.4shows plasma flow generated from the plasma chamber ofFIG.3. Referring toFIG.4, a plasma P may be generated in the plasma generating space412of the plasma chamber410. Specifically, a process gas may be supplied to the plasma generating space412. The process gas supplied to the plasma generating space412may be excited with a state of the plasma P by an electric field which the antenna432forms. When viewed from a front cross-section of the plasma chamber410, the plasma P may move in a lateral direction. In addition, the plasma P may relatively move to the upper area and/or the lower area of the plasma chamber410. This is because one end of the antenna432is provided with a height corresponding to the upper area of the plasma chamber410, and an opposite end of the antenna432is provided with a height corresponding to the lower area of the plasma chamber410. Specifically, a power source434is connected to the one end of the antenna432. The opposite end of the antenna432is grounded. Thus, the one end of the antenna432and/or the opposite end have a greater potential value than the other area of the antenna432. Accordingly, the plasma P remaining in the plasma generating space412moves in a direction toward the upper and lower areas of the plasma chamber410than the central area of the plasma chamber410. In the case of an inductively coupled plasma apparatus for generating the plasma P using the antenna432wound multiple times on the plasma chamber410, the generated plasma P moves in a direction toward the inside walls of the plasma chamber410. Accordingly, the plasma chamber410is etched by a physical force of the plasma P colliding with the plasma chamber410, as well as a chemical reaction with the plasma P. That is, the problem that the chamber is etched by the plasma P occurs more frequently in the inductively coupled plasma apparatus than the capacitively coupled plasma apparatus. Generally, in order to minimize this problem, a method for coating yttrium oxide (Y2O3) on the inside walls of the chamber has been used. However, when a process gas comprising fluorine is applied, yttrium oxide (Y2O3) coating generates particles because the coating film is etched. In other words, the yttrium oxide (Y2O3) coating film has a low ability to suppress the generation of particles. However, according to an embodiment of the inventive concept, the first coating film C1comprising yttrium fluoride (YF3) is provided on the inside walls of the plasma chamber410. Yttrium fluoride (YF3) has a high ability for suppressing the generation of particles comparing to yttrium oxide (Y2O3). Accordingly, the generation of particles may be minimized in the plasma chamber410. The effect of suppressing the generation of particles is greater in the inductively coupled plasma apparatus for the same reasons as described above. FIG.5shows a plasma chamber according to another embodiment of the inventive concept. Referring toFIG.5, the first coating film C1and a second coating film C2may be provided on inside walls of the plasma chamber410. The first coating film C1and the second coating film C2may be formed of different materials, respectively. The first coating film C1may cover the inside walls of the plasma chamber410. The second coating film C2may cover the inside walls of the plasma chamber410. A second coating film C2may be provided on the inside walls of the plasma chamber410. The first coating film C1may be provided on the second coating film C2. The sum of the thicknesses of the first coating film C1and the second coating film C2can be the same in the entire area of the inside walls of the plasma chamber410. In addition, a bonding ability of the first coating film C1and the second coating film C2may be larger than that of the first coating film C1and the plasma chamber410. In addition, the difference between a coefficient of thermal expansion of the second coating film C2and that of the plasma chamber410may be smaller than the difference between the coefficient of thermal expansion of the second coating film C2and that of the first coating film C1. The first coating film C1may comprise yttrium fluoride (YF3). The second coating layer C2may comprise yttrium oxide (Y2O3). The first coating film C1and the second coating film C2may be coated on the inside walls of the plasma chamber410by the method of an Atmospheric Plasma Spray (APS). However, the first coating film C1and the second coating film C2may be coated on the inside walls of the plasma chamber410by the method of an aerosol or a cold spray. FIG.6shows plasma flow generated from the plasma chamber ofFIG.5. Referring toFIG.6, for the same or similar reasons as described above, the plasma P in the plasma generating space412can move in a lateral direction. In addition, the plasma P in the plasma generating space412can move in a direction toward the upper area and/or the lower area of the plasma chamber410when viewed from the front cross section of the plasma chamber410. The first coating film C1may be provided on the second coating film C2. The first coating film C1may comprise yttrium fluoride (YF3) having high particle suppression ability. That is, the first coating film C1directly collides with the plasma P of the plasma generating space412. However, since the first coating film C1has a superior particle suppressing ability as described above, the first coating film C1may minimize the generation of particles in the plasma generating space412. Also, when the first coating film C1is provided on the plasma chamber410, the first coating film C1may be damaged in the process of generating the plasma P, or the first coating film C1may be detached from the plasma chamber410. For example, when the plasma chamber410is provided in a material comprising aluminum oxide (Al2O3) and the first coating film C1is provided in a material comprising yttrium fluoride (YF3), the difference between the coefficient of thermal expansion of the first coating film C1and the coefficient of thermal expansion of the plasma chamber410is large. Heat is generated while generating the plasma P in the plasma generating space412. By this heat, the first coating film C1and the plasma chamber410are thermally deformed. When the difference between the coefficient of thermal expansion of the first coating film C1and the plasma chamber410is large, the degree of thermal deformation of the first coating film C1and the degree of thermal deformation of the plasma chamber410are different. Accordingly, the first coating film C1may be detached from the plasma chamber410by thermal deformation. However, in another embodiment of the inventive concept, the second coating film C2is provided on the plasma chamber410. In addition, the first coating film C1is provided on the second coating film C2. Here, the difference between the coefficient of thermal expansion of the second coating film C2and the coefficient of thermal expansion of the plasma chamber410is smaller than the difference between the coefficient of thermal expansion of the second coating film C2and the coefficient of thermal expansion of the first coating film C1. For example, when the first coating film C1comprises yttrium fluoride (YF3), the second coating film C2comprises yttrium oxide (Y2O3), and a material of the plasma chamber410comprises aluminum oxide (Al2O3), the difference between the coefficient of thermal expansion of the second coating film C2and the coefficient of thermal expansion of the plasma chamber410is smaller than the difference between the coefficient of thermal expansion of the second coating film C2and the coefficient of thermal expansion of the first coating film C1. The coefficient of thermal expansion of the second coating film C2may be the same or similar to the coefficient of thermal expansion of the plasma chamber410. That is, the degree of thermal deformation of the second coating film C2is the same as or similar to the degree of thermal deformation of the plasma chamber410. Therefore, detaching the second coating film C2from the plasma chamber410due to thermal deformation may be minimized. In addition, a bonding ability between the first coating film C1and the second coating film C2may be larger than that of the first coating film C1and the plasma chamber410. For example, when the first coating film C1comprises yttrium fluoride (YF3), the second coating film C2comprises yttrium oxide (Y2O3), and a material of the plasma chamber410comprises aluminum oxide (Al2O3), the bonding ability between the first coating film C1and the second coating film C2may be larger than the bonding ability between the first coating film C1and the plasma chamber410. Accordingly, even if the degree of thermal deformation of the first coating film C1and the second coating film C2are different, detaching the first coating film C1from the second coating film C2may be minimized. FIG.7shows a plasma chamber according to another embodiment of the inventive concept. Referring toFIG.7, the first coating film C1and the second coating film C2may be provided on inside walls of the plasma chamber410. The first coating film C1may cover the inside walls of the plasma chamber410. The second coating film C2may cover the inside walls of the plasma chamber410. A second coating film C2may be provided on the inside walls of the plasma chamber410. The first coating film C1may be provided on the second coating film C2. In addition, when viewed from a front cross-section of the plasma chamber, when it comes to a thickness of the first coating film C1, the thickness of an upper area and a lower area of the plasma chamber410is thicker than a central area of the plasma chamber410. The sum of the thicknesses of the first coating film C1and the second coating film C2may be the same in the entire area of the inside walls of the plasma chamber410. In addition, a bonding ability between the first coating film C1and the second coating film C2may be larger than that of the first coating film C1and the plasma chamber410. In addition, the difference between a coefficient of thermal expansion of the second coating film C2and that of the plasma chamber410may be smaller than the difference between the coefficient of thermal expansion of the second coating film C2and that of the first coating film C1. The first coating film C1may comprise yttrium fluoride (YF3). The second coating layer C2may comprise yttrium oxide (Y2O3). The first coating film C1and the second coating film C2may be coated on the inside walls of the plasma chamber410by the method of an atmospheric plasma spray (APS). However, the first coating film C1and the second coating film C2may be coated on the inside walls of the plasma chamber410by the method of an aerosol or a cold spray. FIG.8shows plasma flow generated from the plasma chamber ofFIG.7. Referring toFIG.8, for the same or similar reasons as described above, the plasma P in the plasma generating space412can move in a lateral direction. In addition, the plasma P in the plasma generating space412can move in a direction toward the upper area and/or the lower area of the plasma chamber410when viewed from the front cross-section of the plasma chamber410. Accordingly, etching the first coating film C1by the plasma P may be performed more in the upper area and the lower area of the plasma chamber410than the central area of the plasma chamber410. If the thickness of the first coating film C1and the second coating film C2are the same and the first coating film C1provided to the upper area and the lower area of the plasma chamber410is etched, the plasma chamber410should be replaced or the coating film of the plasma chamber410should be re-coated. However, according to another embodiment of the inventive concept, the thickness of the first coating film C1provided to the upper and lower areas of the plasma chamber410is thick. In other words, by making higher thickness of the first coating film C1which has a high ability of suppressing particles in the upper and lower areas of the plasma chamber410where frequently collided with the plasma P, a useful life of the plasma chamber410may be increased. Other embodiments of the inventive concept described inFIGS.7and8are the same as or similar to those of the above-described embodiments, and thus detailed descriptions thereof will be omitted. FIG.9shows a plasma chamber according to another embodiment of the inventive concept. Referring toFIG.9, the first coating film C1and a second coating film C2may be provided on inside walls of the plasma chamber410. The first coating film C1may cover the inside walls of the plasma chamber410. The second coating film C2may cover the inside walls of the plasma chamber410. The first coating film C1may be provided on the inside walls of the plasma chamber410. A second coating film C2may be provided on the inside walls of the plasma chamber410. The first coating film C1may be provided with the same thickness on the entire inside walls of the plasma chamber410. The second coating film C2may be provided with the same thickness on the entire inside walls of the plasma chamber410. The thickness of the first coating film C1and the second coating film C2may be similar. When viewed from a front cross section of the plasma chamber410, the first coating film C1may be provided to the upper and the lower areas of the plasma chamber410. When viewed from the front cross section of the plasma chamber410, the second coating film C2may be provided to the central area of the plasma chamber410. In addition, the difference between a coefficient of thermal expansion of the second coating film C2and that of the plasma chamber410may be smaller than the difference between the coefficient of thermal expansion of the second coating film C2and that of the first coating film C1. The first coating film C1may comprise yttrium fluoride (YF3). The second coating layer C2may comprise yttrium oxide (Y2O3). The first coating film C1and the second coating film C2may be coated on the inside walls of the plasma chamber410by the method of an Atmospheric Plasma Spray (APS). However, the first coating film C1and the second coating film C2may be coated on the inside walls of the plasma chamber410by the method of an aerosol or a cold spray. FIG.10shows plasma flow generated from the plasma chamber ofFIG.9. Referring toFIG.10, for the same or similar reasons as described above, the plasma P in the plasma generating space412can move in a lateral direction. In addition, the plasma P in the plasma generating space412can move in a direction toward the upper area and/or the lower area of the plasma chamber410when viewed from the front cross section of the plasma chamber410. In addition, a temperature of the plasma generating space412may be higher than the upper area and/or the lower area of the plasma chamber410. According to another embodiment of the inventive concept, the first coating film C1is provided on the upper and lower areas of the plasma chamber410. In addition, the second coating film C2is provided on a central area of the plasma chamber410. That is, since the upper area and/or the lower area of the plasma chamber410are in an area where a collision with the plasma P is frequent, the first coating film C1may be provided on the upper area and the lower area of the plasma chamber410, thereby maximally suppressing the generation of particles. In addition, since the central area of the plasma chamber410is the highest temperature area, the second coating film C2having a similar thermal expansion coefficient to the plasma chamber410is provided on the central area of the plasma chamber410. Accordingly, even if the second coating film C2is thermally deformed, detaching the second coating film C2from the plasma chamber410may be minimized. Other effects of other embodiments of the inventive concept described inFIGS.9and10are the same as or similar to those of the above-described embodiments, and thus detailed descriptions thereof will be omitted. The embodiments described above can be variously applied to the substrate treating apparatus using the plasma. For example, the embodiments described above may be applied to various apparatuses performing an ashing process, a deposition process, an etching process, or a clean process using the plasma. In addition, in the embodiments described above, the first coating film C1comprises yttrium fluoride (YF3), and the second coating film C2comprises yttrium oxide (Y2O3), but these are not limited hereto. For example, the first coating film C1may comprise any one of yttrium fluoride, yttrium oxide, and yttrium oxyfluoride (YOF), and the second coating film C2may comprise any one of yttrium fluoride, yttrium oxide, and yttrium oxyfluoride (YOF). The above description has been made for the illustrative purpose. Furthermore, the above-mentioned contents describe the exemplary embodiment of the inventive concept, and the inventive concept may be used in various other combinations, changes, and environments. That is, the inventive concept can be modified and corrected without departing from the scope of the inventive concept that is disclosed in the specification, the equivalent scope to the written disclosures, and/or the technical or knowledge range of those skilled in the art. The written embodiment describes the best state for implementing the technical spirit of the inventive concept, and various changes required in the detailed application fields and purposes of the inventive concept can be made. Accordingly, the detailed description of the inventive concept is not intended to limit the inventive concept to the disclosed embodiments. Furthermore, it should be construed that the attached claims include other embodiments. | 33,789 |
11862435 | DETAILED DESCRIPTION Referring now toFIG.1, a semiconductor processing device100includes a process chamber102. While a plasma-enhanced chemical vapor deposition process (PECVD) is shown, other semiconductor processes may be used. The semiconductor processing device100further includes a showerhead system110to deliver process gases to the process chamber102. A high-frequency (HF) RF generator120and a low-frequency (LF) RF generator124are connected by a matching network126to an electrode128arranged inside of a non-conducting portion130of a pedestal system134(shown in more detail inFIG.2). Another portion135of the pedestal system134has a substantially different electrical potential than the electrode128. For example the portion135may be connected to a ground reference potential. Alternately, the HF RF generator120, the LF RF generator124and the matching network126can be connected to the showerhead system110. The RF signal supplied by the matching network126has a power and a frequency sufficient to generate plasma from the process gas. In a typical process, the HF RF generator120may operate in a frequency range of 2-60 MHz, although other frequencies may be used. The LF RF generator124may operate in a frequency range of 100 kHz-2 MHz, although other frequencies may be used. Suitable power levels may include LF power at about 200-600 W and HF power at about 100-1500 W, although other power levels may be used. The process chamber may be operated at approximately 500 mT-12 Torr. The pedestal system134typically includes a chuck, a fork, or lift pins (all not shown) to hold and transfer a substrate136during and between deposition and/or plasma treatment reactions. The chuck may be an electrostatic chuck, a mechanical chuck or various other types of chuck. The process gases are introduced via inlet142. Multiple process gas lines142-1,142-2,143-3, are connected to a manifold150. The process gases may be premixed or not. Appropriate valving and mass flow control mechanisms (generally identified at144-1,144-2,144-3, . . . ) are employed to ensure that the correct gases are delivered during the deposition and plasma treatment phases of the process. In some examples, the chemical precursor(s) are initially delivered in the liquid form. For example only, the liquid may be vaporized and mixed with other process gases in a manifold that is heated above a vaporization temperature. Process gases exit the process chamber102via an outlet160. A vacuum pump164typically draws process gases out of the process chamber102and maintains a suitably low pressure within the reactor by a flow restriction device, such as a valve166. The system for reducing parasitic plasma according to the present disclosure can be retro-fit to existing systems and/or implemented when the semiconductor processing system is initially installed. The system suppresses unwanted (parasitic) plasma near RF powered surfaces (e.g. an electrode in a pedestal or showerhead) while providing a high impedance path to ground from those surfaces. The high impedance path is created using a plurality of spaced dielectric layers, which have a lower dielectric constant than can be achieved using a solid dielectric layer. Alternating gaps and dielectric layers may be terminated by a surface having a substantially different electrical potential such as a grounded conducting structure. Referring now toFIG.2A, the pedestal system134ofFIG.1is shown in further detail. The pedestal system134includes an adapter220. A collar230is connected to the adapter220. A conducting structure240including a first (e.g., upper surface242) is connected to the collar230and is arranged generally parallel to a pedestal platen252. The conducting structure240may be disk-shaped or another suitable shape. N dielectric layers250-1, . . . , and250-N (collectively N dielectric layers250) are arranged between the conducting structure240and the pedestal platen252, where N is an integer greater than one. The N dielectric layers250are arranged parallel to the pedestal platen252. The N dielectric layers250may be disk-shaped or another suitable shape. In some examples, a diameter of each of the N dielectric layers may decrease as a distance from the electrode increases. In some examples, a gap “g” is provided between the conducting structure240and a first one of the N dielectric layers250, between adjacent ones of the N dielectric layers250and between a last one of the N dielectric layers250and the pedestal platen252. The pedestal platen252may be made of a non-conducting material such as ceramic or other suitable material. In some examples, N=2, although additional or fewer dielectric disks may be used. An additional surface254or “mesa” may be provided on a top surface of the pedestal platen252. The substrate136may be arranged on an upper surface of the pedestal platen252or on the additional surface254or mesa. The pedestal platen252may include an inner cylindrical portion256that extends downwardly through an inner cylindrical portion258of the collar230. The pedestal platen252may include a flanged portion260that extends radially outwardly from a bottom end of the inner cylindrical portion258. The flanged portion260may mate with a recess262formed in the adapter220. A seal266such as an “O”-ring may be arranged between the recess262and the flanged portion260. The electrode128may be embedded in the pedestal platen252. In some examples, the electrode128may include a wire mesh or spaced conductors. In other examples, the conducting structure240may have a diameter that is greater than the adapter220, greater than the substrate136and/or less than the diameter of the pedestal platen252. In some examples, the adapter220, the collar230and the conducting structure240may be made of metal such as aluminum or another suitable conducting material. In some examples, the metal adapter220, the collar230and the conducting structure240are connected to RF ground or another electrical potential that is substantially different than the electrode128. The combination of the N dielectric layers250, the adapter220, the collar230and the conducting structure240provide RF shielding, which attenuates the RF fields below the pedestal platen252. This, in turn, significantly attenuates plasma density formed below the pedestal platen252. This design has been shown to reduce parasitic plasma density by a factor of about 5. The presence of conducting grounded surfaces (such as the adapter220, the collar230and/or the conducting structure240) near RF “hot” surfaces (such as the conducting structure240) presents a problem if the capacitive coupling of the RF “hot” surfaces to ground is too high. In some examples, coupling capacitance to ground may be limited to values less than 100 picoFarads (pF). Insertion of a dielectric sufficiently thick to provide low capacitive coupling (i.e. values less than 100 pF) typically results in very thick layers (many cm in size) that are either not practical or expensive to implement. In some examples, the present disclosure resolves this problem using the N dielectric layers or disks with a gap between them, where N is an integer greater than one. An equivalent circuit corresponding to the spaced N dielectric layers includes multiple capacitors that are connected in series. The net capacitance of the series connection of the equivalent capacitors is lower than the lowest capacitor value. For the dielectric stack shown inFIG.2A, the lowest capacitance in the series connection of the equivalent capacitors will generally correspond to the capacitance associated with the gap between the N dielectric layers250. Since the RF fields in the dielectric stack are still very high, plasma formation (plasma light-up) may occur between the N dielectric layers250. In some examples, the gap g is selected such that it is sufficiently small to prevent formation of “bulk” plasma. For example only, the gap g that is less than or equal to 3 mm tends to prevent plasma formation when N=2 for pressures and power levels that are typically used. However, the size of the gap g may be set to other values when N=2, when N>2, or when different pressures or RF power levels are used. The size of the gap and the number of dielectric layers may be selected to prevent plasma formation between the dielectric layers during the semiconductor process for the selected species and selected process conditions such as temperature, pressure and RF power and frequency. In some examples, the N dielectric layers250include a radially inner portion300having a first thickness in an axial direction and a protruding portion302that extends radially outwardly and has a second thickness in the axial direction. A difference between the first thickness and the second thickness is equal to the gap g. In some examples, one or more barriers320may be arranged between radially outer ends of the N dielectric layers250to prevent incursion of deposition precursor species between the N dielectric layers250. While only one barrier is shown, additional barriers may be arranged in other locations to prevent incursion of deposition precursor into the gaps. For example only, the barriers320may be made from any suitable dielectric material that does not shed particles. The barriers320tend to reduce the risk for creating a difficult to clean site that can lead to accumulation of film between the N dielectric layers250that could radiate particles into the process chamber102. Referring now toFIG.2B, in some examples, the N dielectric layers250may include an alignment structure generically identified at340such as one or more notches, holes, protrusions or other structures that are used to ensure that the angular orientation or clocking of the N dielectric layers250is not arbitrary. Additionally, one or more lift pin holes350may be provided in the N dielectric layers250and/or conducting structure240to provide sufficient clearance to allow lift pins to lift the substrate136. Referring now toFIG.3, a method400for reducing formation of parasitic plasma is shown. At404, the electrode128is embedded in the pedestal platen252. At408, the electrode128is connected to an RF bias. At412, N dielectric layers250are arranged adjacent to the pedestal platen252. At414, the conducting structure240or another surface having a substantially different electrical potential is arranged adjacent to the N dielectric layers250. At416, the conducting structure240is connected to RF ground of another electrical potential. At420, the RF bias is applied to the electrode128during a process, such as during deposition of a thin film in a PECVD process. Referring now toFIG.4, a system according to the present disclosure is used to reduce parasitic plasma that may occur near a showerhead500. The showerhead500includes a head portion504and a stem portion506. M dielectric layers510-1, . . . , and510-M (collectively referred to as the M dielectric layers510) are arranged horizontally adjacent to the head portion504. The M dielectric layers510can be disk-shaped. P dielectric portions520-1, . . . , and520-P (collectively referred to as the P dielectric portions520) are arranged vertically adjacent to the stem portion506. A conducting portion530is arranged adjacent to the M dielectric layers510and the P dielectric layers520. The conducting portion530may include a cylindrical stem portion534and a disk portion538that projects radially outwardly from one end of the cylindrical stem portion534. In some examples, the P dielectric layers520may have a cylindrical cross section and the M dielectric layers510have a disk shape similar to that shown inFIG.2B. The showerhead500is connected to an RF source, such as the RF generators120and124and the matching network126shown inFIG.1or any other suitable RF source. The conducting portion530may be connected to ground or another substantially different electrical potential. The RF shielding system inFIG.4tends to reduce formation of parasitic plasma near an upper surface of the showerhead500. Gaps are defined between the M dielectric layers510and the P dielectric layers520as described above. The size of the gaps and the number of dielectric layers may be selected to prevent plasma formation between the dielectric layers during the semiconductor process for the selected species and selected process conditions such as temperature, pressure and RF power and frequency. Referring now toFIG.5, another system according to the present disclosure is used to reduce parasitic plasma that may occur near a showerhead600. The showerhead600includes a head portion604and a stem portion606. A pedestal620is arranged below the showerhead600. A chuck, a fork, or lift pins generally identified at632hold and transfer a substrate628during and between deposition and/or plasma treatment reactions. A first supporting portion644is connected to a top portion646of the processing chamber. The first supporting portion644is arranged adjacent to the stem portion606of the showerhead600. The top portion646of the processing chamber or any other surface at a different electrical potential is arranged adjacent to the head portion604of the showerhead600. A plurality of dielectric layers or disks650are arranged between the head portion604and the top portion646. A first gap652is defined between the head portion604and a first one of the plurality dielectric layers650. A second gap654is defined between adjacent ones of the plurality dielectric layers650. A third gap656is defined between a last one of the plurality dielectric layers650and the supporting portion648. In some examples, the head portion604and the stem portion606of the showerhead600may be made of a conducting material and may be connected to an RF bias source. The first supporting portion644may be made of an insulating material. The pedestal620may be made of a conducting material and may be connected to a ground reference potential. As can be appreciated, the top portion646of the processing chamber has a substantially different electrical potential than the showerhead600. As a result, parasitic plasma may be formed in a gap between the showerhead and the top portion of the processing chamber. According to the present disclosure, the plurality of dielectric layers are separated by gaps and are arranged between the showerhead and the top portion of the processing chamber to eliminate the parasitic plasma that would otherwise be created. As with the preceding examples, the size of the gaps652,654and656and the number of dielectric layers650are selected to prevent plasma formation in the area between the showerhead600and the top portion646of the processing chamber during the semiconductor process for the selected species and selected process conditions such as temperature, pressure and RF power and frequency. The foregoing description is merely illustrative in nature and is in no way intended to limit the disclosure, its application, or uses. The broad teachings of the disclosure can be implemented in a variety of forms. Therefore, while this disclosure includes particular examples, the true scope of the disclosure should not be so limited since other modifications will become apparent upon a study of the drawings, the specification, and the following claims. For purposes of clarity, the same reference numbers will be used in the drawings to identify similar elements. As used herein, the phrase at least one of A, B, and C should be construed to mean a logical (A or B or C), using a non-exclusive logical OR. It should be understood that one or more steps within a method may be executed in different order (or concurrently) without altering the principles of the present disclosure. | 15,719 |
11862436 | DETAILED DESCRIPTION In the following detailed description, reference is made to the accompanying drawings, which form a part of the description. In the drawings, similar symbols typically identify similar components, unless context dictates otherwise. Furthermore, unless otherwise noted, the description of each successive drawing may reference features from one or more of the previous drawings to provide clearer context and a more substantive explanation of the current exemplary embodiment. Still, the exemplary embodiments described in the detailed description, drawings, and claims are not meant to be limiting. Other embodiments may be utilized, and other changes may be made, without departing from the spirit or scope of the subject matter presented herein. It will be readily understood that the aspects of the present disclosure, as generally described herein and illustrated in the drawings, may be arranged, substituted, combined, separated, and designed in a wide variety of different configurations, all of which are explicitly contemplated herein. Hereinafter, exemplary embodiments of a plasma processing apparatus and a plasma processing method of the present disclosure will be described in detail with reference to the accompanying drawings. However, it should be note that the plasma processing apparatus and the plasma processing method of the present disclosure are not limited to the exemplary embodiments to be described below. Further, the various exemplary embodiments can be appropriately combined as long as the contents of processings are not contradictory. In an apparatus configured to perform a processing by using plasma, a temperature of an upper electrode may be increased due to heat input from the plasma. Further, even if the temperature of the upper electrode is not increased that much, it may be required to maintain the upper electrode at a low temperature depending on a processing condition. In such a case, the upper electrode is controlled to a preset temperature by being cooled with a low-temperature coolant. If the low-temperature coolant is flown, a temperature of a pipeline through which the coolant flows and a temperature of a member cooled by the coolant are lowered, so that condensation may occur at portions of the pipeline and the member which are in contact with air. If such condensation takes places, an electric component provided at the upper electrode may be broken due to moisture generated by the condensation. Further, a water droplet formed by the moisture generated by the condensation may disturb distribution of a high frequency power supplied to an inside of a processing chamber via the upper electrode. In view of the foregoing, the present disclosure provides a technique of suppressing the condensation near the upper electrode. First Exemplary Embodiment [Configuration of Plasma Processing Apparatus1] FIG.1is a schematic cross sectional view illustrating an example of a plasma processing apparatus according to a first exemplary embodiment. The plasma processing apparatus1is configured to perform a plasma processing such as etching or film formation on a semiconductor wafer (hereinafter, simply referred to as “wafer”) as an example of a processing target object. The plasma processing apparatus1includes an apparatus main body10and a control device100. The plasma processing apparatus1is disposed within a clean room or the like in which a temperature and a humidity of air are regulated within preset ranges. The apparatus main body10has a substantially cylindrical processing vessel11made of, by way of example, aluminum having an anodically oxidized surface. The processing vessel11is frame-grounded. A column-shaped supporting table14is disposed at a bottom of the processing vessel11with an insulating plate13made of ceramic or the like therebetween, and a placing table16made of, by way of non-limiting example, aluminum is disposed on the supporting table14. The placing table16serves as a lower electrode. Disposed on a top surface of the placing table16is an electrostatic chuck18configured to attract and hold the wafer W by an electrostatic force. The electrostatic chuck18has a structure in which an electrode20made of a conductive film is embedded between a pair of insulating layers or insulating sheets. The electrode20is electrically connected with a DC power supply22. The wafer W is attracted to and held on a top surface of the electrostatic chuck18by an electrostatic force such as a Coulomb force generated in the top surface of the electrostatic chuck18by a DC voltage applied from the DC power supply22. To improve etching uniformity, a conductive edge ring24made of, for example, silicon is disposed on the top surface of the placing table16, surrounding the electrostatic chuck18. A cylindrical inner wall member26made of, by way of example, quartz is provided along side surfaces of the placing table16and the supporting table14. A path28is provided within the supporting table14, and a coolant from a chiller unit provided at an outside of the processing vessel11is supplied into the path28via a pipeline30a. The coolant supplied into the path28is returned back into the chiller unit via a pipeline30b. The chiller unit is configured to control a temperature of the coolant to be supplied into the path28. As the temperature-controlled coolant circulates within the path28, a temperature of the supporting table14is controlled, so that a temperature of the wafer W on the electrostatic chuck18is controlled via the electrostatic chuck18and the placing table16on the supporting table14. A pipeline32is provided within the supporting table14, the placing table16and the electrostatic chuck18. A heat transfer gas supplied into the pipeline32from a non-illustrated heat transfer gas supply mechanism is supplied into a gap between the wafer W and the electrostatic chuck18through the pipeline32. The heat transfer gas may be, for example, a helium gas. By controlling a pressure of the heat transfer gas supplied into the gap between the wafer W and the electrostatic chuck18, a heat transfer coefficient between the wafer W and the electrostatic chuck18can be controlled. A shower head34is disposed above the placing table16, facing the placing table16substantially in parallel. The shower head34also serves as an upper electrode. That is, the shower head34and the placing table16serve as a pair of electrodes (the upper electrode and the lower electrode). A space between the shower head34and the placing table16is configured as a plasma formation space. The shower head34is supported at an upper portion of the processing vessel11with an insulating shield member42therebetween. The shower head34includes a ceiling plate36disposed to directly face the placing table16; and a base member38configured to support the ceiling plate36from above. A multiple number of discharge holes37is formed through the ceiling plate36in a thickness direction thereof to discharge a processing gas into the processing vessel11. The ceiling plate36is made of, by way of non-limiting example, silicon or SiC. The base member38is made of a conductive material such as, but not limited to, aluminum having an anodically oxidized surface. The base member38supports the ceiling plate36at a lower portion thereof in a detachable manner. A diffusion space40through which the processing gas is supplied into the multiple number of discharge holes37is formed within the base member38. A multiple number of through holes41is formed in a bottom portion of the base member38to be located under the diffusion space40. These through holes41communicate with the discharge holes37, respectively. The base member38is provided with an inlet opening62through which the processing gas is introduced into the gas diffusion space40. One end of a pipeline64is connected to this inlet opening62, and the other end of the pipeline64is connected to a gas source66configured to supply the processing gas. The pipeline64is equipped with a mass flow controller (MFC)67and a valve68in sequence from an upstream side. When a plasma processing is performed on the wafer W on the electrostatic chuck18, the processing gas supplied from the gas source66is introduced into the diffusion space40via the pipeline64and diffused within the diffusion space40. The processing gas diffused in the diffusion space40is then supplied into the processing vessel11in a shower shape through the through holes41and the discharge holes37. Further, a path92is formed within the base member38, and a coolant from a chiller unit94provided at the outside of the processing vessel11is supplied into the path92via a pipeline93. The coolant supplied from the chiller unit94into the path92of the base member38via the pipeline93is circulated within the path92and then returned back into the chiller unit94via the pipeline93. The base member38and the pipeline93are connected with a non-illustrated insulating member therebetween. The chiller unit94is configured to control a temperature of the coolant to be supplied into the path92. The chiller unit94is an example of a temperature controller. As the temperature-controlled coolant circulates within the path92, a temperature rise of the shower head34due to the heat input from the plasma formed between the placing table16and the shower head34is suppressed. The temperature of the coolant circulated within the path92is lower than a dew point temperature of exterior air outside the processing vessel11. In the present exemplary embodiment, the temperature of the coolant is, for example, equal to or less than 0° C. The base member38having the path92formed therein is an example of a cooler. Further, a high frequency power supply48is electrically connected to the base member38via a power feed rod44and a matching device46. In the present exemplary embodiment, the power feed rod44is a hollow cylindrical member made of a conductive metal such as aluminum. The power feed rod44is an example of a conductive member. The high frequency power supply48is a power supply for plasma formation, and is configured to generate a high frequency power having a frequency equal to or higher than 13.56 MHz, for example, 60 MHz. The high frequency power generated by the high frequency power supply48is supplied to the base member38via the matching device46and the power feed rod44. The high frequency power supply48is an example of a plasma processor. The matching device46is configured to match a load impedance with an internal (or output) impedance of the high frequency power supply48. The matching device46serves to control the output impedance of the high frequency power supply48and the load impedance to be apparently matched with each other, when the plasma is formed within the processing vessel11. An output terminal of the matching device46is electrically connected with an upper end of the power feed rod46. The shower head34and a part of the power feed rod44are covered by a substantially cylindrical cover member11awhich is provided above a sidewall of the processing vessel11. The cover member11ais made of a conductive material such as aluminum, and is grounded via the processing vessel11. With this configuration, leakage of the high frequency power supplied to the shower head34to an outside of the apparatus main body10is suppressed. An opening44asurrounded by an insulating member is formed at a ceiling portion of the cover member11a, and the power feed rod44connects the base member38and the matching device46through the opening44a. A plurality of pipelines such as the pipeline64and the pipeline93is disposed within a space surrounded by the cover member11aand the shower head34. Besides these pipelines, electric components such as various kinds of sensors are also disposed within this space surrounded by the cover member11aand the shower head34. In the following, the space surrounded by the cover member11aand the shower head34is referred to as an “antenna chamber”. Furthermore, non-illustrated seal members are provided between the cover member11aand the processing vessel11, between the cover member11aand the pipeline64, between the opening44aand the power feed rod44, between the pipeline93and the cover member11a, and so forth, so that the antenna chamber has airtightness to some extent. A pressure gauge99is connected to the cover member11a. The pressure gauge99is configured to measure a pressure within the antenna chamber. A gas having a dew point temperature lower than that of the exterior air outside the processing chamber11is supplied into the antenna chamber from a gas source98via a pipeline95. The pipeline95is equipped with a valve96. In the following, the gas having the dew point temperature lower than that of the exterior air outside the processing chamber11is referred to as a “low-dew point gas”. In the present exemplary embodiment, the gas source98supplies dry air into the antenna chamber as the low-dew point gas. Alternatively, the low-dew point gas may be an inert gas such as an argon gas or a nitrogen gas as long as its dew point temperature is lower than the dew point temperature of the exterior air outside the processing chamber11. The valve96is an example of a gas supply. A high frequency power supply88is electrically connected via a matching device87to the placing table16serving as the lower electrode. The high frequency power supply88is a power supply for ion attraction (bias), and is configured to supply a high frequency power having a frequency ranging from 300 kHz to 13.56 MHz, for example, 2 MHz to the placing table16. The matching device87is configured to match a load impedance with an internal (or output) impedance of the high frequency power supply88. The matching device87serves to control the internal impedance of the high frequency power supply88and the load impedance to be apparently matched with each other, when the plasma is formed within the processing vessel11. An exhaust port80is provided at the bottom of the processing vessel11. An exhaust device84is connected to the exhaust port80via an exhaust line82and an APC (Auto Pressure Control) valve83. The exhaust device84has a vacuum pump such as a turbo molecular pump, and is capable of decompressing the inside of the processing vessel11to a required vacuum level. The APC valve83is configured to adjust a pressure within the processing vessel11. An opening85through which the wafer W is carried in/out is provided at the sidewall of the processing vessel11, and this opening85is opened or closed by a gate valve86. Further, a deposition shield12configured to suppress adhesion of an etching byproduct (deposit) to the processing vessel11is detachably provided along an inner sidewall of the processing vessel11. The deposition shield12is also provided on an outer surface of the inner wall member26. Near the bottom of the processing vessel12, an exhaust plate81is provided between the deposition shield12on the inner sidewall of the processing vessel11and the deposition shield12on the inner wall member26. The deposition shield12and the exhaust plate81may be made of, by way of example, an aluminum member coated with ceramic such as Y2O3. A GND block91, which is made of a conductive member and is DC-connected to the ground, is provided at the deposition shield12, which is disposed along the inner sidewall of the processing vessel11, such that it is located at a height position substantially on a level with the wafer W. The GND block91is configured to suppress an abnormal discharge within the processing vessel11. An overall operation of the apparatus main body10having the above-described configuration is controlled by the control device100. The control device100is equipped with a processor, a memory and an input/output interface. The memory stores therein a program or a processing recipe. The processor executes the program read from the memory, thus controlling the individual components of the apparatus main body10via the input/output interface according to the processing recipe read from the memory. When a processing using plasma is performed on the wafer W in the plasma processing apparatus1having the above-described configuration, the control device100performs the following controls over the individual components of the plasma processing apparatus1, for example. First, in the state that the wafer W is placed on the electrostatic chuck18, the control device100controls the MFC67and the valve68to supply a processing gas of a preset flow rate into the diffusion space40. The processing gas supplied into the diffusion space40is diffused within the diffusion space40, and then, supplied into the processing vessel11in a shower shape through the through holes41and the discharge holes37. Further, the control device100controls the APC valve83and the exhaust device84so that the inside of the processing vessel11is set to a preset pressure. Then, the control device100controls the high frequency power supply48to generate a high frequency power of a preset frequency for plasma formation and supplies this generated high frequency power to the shower head34via the power feed rod44. Accordingly, the processing gas within the processing vessel11is formed into plasma. Further, the control device100controls the high frequency power supply88to generate a high frequency power of a predetermined frequency for ion attraction (bias) and supplies this generated high frequency power to the placing table16. Accordingly, charged particles such as ions in the plasma are attracted into the wafer W on the electrostatic chuck18. As a result, a preset plasma processing such as etching is performed on the wafer W on the electrostatic chuck18. When performing the processing by using the plasma, a temperature of the shower head34may be increased due to the heat input from the plasma. Further, even if the temperature of the shower head is not increased that much, it may be required to maintain the shower head34at a low temperature depending on a processing condition. In such a case, the shower head34is controlled to a preset temperature by being cooled with the low-temperature coolant having a temperature controlled by the chiller unit94. If the low-temperature coolant is flown, a temperature of a surface of the pipeline93through which the coolant flows and a temperature of the base member38cooled by the coolant are lowered, so that the condensation may occur at portions of the pipeline93and the base member38which are in contact with air. If the condensation takes place, the electric components provided at the shower head34may be broken due to moisture generated by the condensation. Further, if water droplets are generated on a surface of the power feed rod44due to the moisture generated by the condensation, a surface resistance of the power feed rod33is disturbed, so that distribution of the high frequency power supplied to the shower head34via the power feed rod44may be disturbed. If the distribution of the high frequency power supplied to the shower head34is disturbed, distribution of the high frequency power supplied to the inside of the processing vessel11via the shower head34is also disturbed, resulting in deterioration of uniformity of the plasma processing upon the wafer W. It may be considered to cover, with a heat insulator, the members which are supposed to be cooled. However, since the multiple pipelines and the electric components such as the sensors are disposed within the antenna chamber surrounded by the cover member11a, there is little space for providing the heat insulator within the antenna chamber. Thus, it is difficult to cover all the members to be cooled with the heat insulator. In view of this, according to the present exemplary embodiment, the condensation within the antenna chamber is suppressed by filling the antenna chamber with the low-dew point gas. [Pressure Control within Antenna Chamber] FIG.2is a diagram illustrating an example of a pressure variation within the antenna chamber. In an initial state, the antenna chamber is filled with the same air as the exterior air outside the processing vessel11, and a pressure within the antenna chamber is set to a pressure P0(e.g., 1 atmosphere) which is the same as a pressure of the exterior air outside the processing vessel11. The exterior air outside the processing vessel11has a temperature of, e.g., 25° C. and a humidity of, e.g., 50%. In the present exemplary embodiment, the control device100controls the valve96to supply the low-dew point gas into the antenna chamber before starting the cooling of the shower head34by the chiller unit94. Since the inside of the antenna chamber has the airtightness to some extent, the pressure within the antenna chamber is increased, as illustrated inFIG.2, for example, as the low-dew point gas is supplied. By referring to a measurement value by the pressure gauge99, the control device100controls the valve96to stop the supply of the low-dew point gas into the antenna chamber at a time t1when the pressure within the antenna chamber reaches a pressure P1higher than the pressure P0of the exterior air outside the processing chamber11. The pressure P1is, for example, 1.2 atmosphere. Although the inside of the antenna chamber has the airtightness to some extent, the degree of the airtightness is not that high. Therefore, air and the low-dew point gas within the antenna chamber leak to the outside of the antenna chamber. As a result, the pressure within the antenna chamber gradually decreases. Then, the control device100controls the valve96to resume the supply of the low-dew point gas into the antenna chamber at a time t2when the pressure within the antenna chamber becomes equal to or less than a pressure P2which is higher than the pressure P0and lower than the pressure P1. The pressure P2may be, for example, 1.1 atmosphere. Accordingly, the pressure within the antenna chamber increases again. Then, the controller100controls the valve96to stop the supply of the low-dew point gas into the antenna chamber again at a time t3when the pressure within the antenna chamber becomes equal to or higher than the pressure P1. As stated above, in the present exemplary embodiment, the control device100controls the supply and the stop of the supply of the low-dew point gas into the antenna chamber such that the pressure within the antenna chamber becomes a positive pressure. Accordingly, the air containing moisture is exhausted slowly from the antenna chamber along with the low-dew point gas, so that the inside of the antenna chamber is filled with the low-dew point gas. Therefore, the condensation within the antenna chamber is suppressed. [Connection of Pipeline93and Cover Member11a] Here, if the pipeline93through which the coolant flows is directly fixed to the cover member11a, the cover member11amay be deprived of heat by the pipeline93which has been cooled by the coolant, and a temperature of the cover member11amay be decreased. Since the antenna chamber is filled with the low-dew point gas, condensation in an inside of the cover member11ais suppressed. However, since an outside of the cover member11ais in contact with the exterior air outside the cover member11a, condensation may occur at the outside of the cover member11a. In case that the condensation takes place at the outside of the cover member11a, electric components disposed at the outside of the apparatus main body10may be broken due to moisture generated by the condensation. In view of this, in the present exemplary embodiment, a heat insulating member900made of a material having low thermal conductivity is provided between the cover member11aand a flange93aof the pipeline93, and the flange93of the pipeline93is fixed to the cover member11aby a screw910.FIG.3is an enlarged cross sectional view illustrating an example of a method of fixing the pipeline93to the cover member11a. In the fixing method shown inFIG.3, the flange93aof the pipeline93is fixed to the cover member11aby the screw910which is made of a conductive material. Accordingly, a potential difference between the cover member11aand the pipeline93is reduced by the screw910. Further, if a material without having electromagnetic shielding property (the function to shield an electromagnetic wave) is used as the heat insulating member900, the high frequency power supplied to the shower head34may leak to the outside of the apparatus main body10from a gap between the cover member11aand the flange93a. For this reason, it is desirable that a member having the electromagnetic shielding property as well as the heat insulating property is used as the heat insulating member900. Accordingly, the transfer of the heat between the cover member11aand the pipeline93and the leakage of the high frequency power from the gap between the cover member11aand the pipeline93can be suppressed. As the member having the electromagnetic shielding property and the heat insulating property, a resin material having high heat insulating property and containing a power of a metal having conductivity may be considered. By way of non-limiting example, a PP (Poly Propylene) resin, a PC (Poly Carbonate) resin, an ABS (Acrylonitrile Butadiene Styrene) resin, a nylon resin, PBT (PolyButylene Terephthalate) resin, or a PPS (PolyPhenylene Sulfide) may be used as the resin material. Further, the conductive material in the form of the powder added to the resin material may be, by way of example, carbon fiber. Furthermore, gaps may exist between the cover member11aand the heat insulating member900and between the heat insulating member900and the flange93due to surface roughness of the cover member11a, the heat insulating member900and the flange93a. In views of this, in the present exemplary embodiment, metal seals920are provided between the cover member11aand the heating insulating member900and between the heat insulating member900and the flange93a, as illustrated inFIG.3, for example. Accordingly, the leakage of the high frequency power from the gaps between the cover member11aand the heat insulating member900and between the heat insulating member900and the flange93ais suppressed. Moreover, in the present exemplary embodiment, O-rings921are disposed between the cover member11aand the heat insulating member900and between the heat insulating member900and the flange93a, as depicted inFIG.3, for example. Accordingly, the airtightness of the antenna chamber can be maintained. Here, the method of fixing the pipeline93to the cover member11ais not limited to the example fixing method shown inFIG.3.FIG.4is an enlarged cross sectional view illustrating another example fixing method of the pipeline93to the cover member11a. In the fixing method shown inFIG.4, the flange93aof the pipeline93is fixed to the cover member11aby a screw911which is made of a material having low thermal conductivity, such as a resin. Accordingly, the heat transfer between the flange93aand the cover member11ais further suppressed. Furthermore, in the fixing method shown inFIG.4, since electric connection between the cover member11aand the pipeline93is not enough, the cover member11aand the flange93are connected through a jumper wire912. With the fixing method shown inFIG.4as well, the heat transfer between the cover member11aand the pipeline93and the leakage of the high frequency power from the gap between the cover member11aand the pipeline93are suppressed. FIG.5is an enlarged cross sectional view illustrating yet another example fixing method of the pipeline93to the cover member11a. In the fixing method shown inFIG.5, a heat insulating member901which does not have the electromagnetic shielding property and is made of a material having low thermal conductivity is disposed between the cover member11aand the flange93aof the pipeline93, and the flange93aof the pipeline93is fixed to the cover member11aby the screw910. Further, a paint902having the electromagnetic shielding property is coated on a side surface of the heat insulating member901. A mixture of a paint resin and a powder of a conductive material may be used as the paint902. Accordingly, the heat transfer between the cover member11aand the flange93ais suppressed by the heat insulating member901, and the leakage of the high frequency power from the gap between the cover member11aand the flange93ais suppressed by the paint902. Thus, the fixing method shown inFIG.5is also capable of suppressing the heat transfer between the cover member11and the pipeline93and the leakage of the high frequency power from the gap between the cover member11aand the pipeline93. FIG.6is an enlarged cross sectional view illustrating still yet another example fixing method of the pipeline93to the cover member11a. In the fixing method shown inFIG.6, the heat insulating member900is fixed to the cover member11aby a screw910b, and the flange93aof the pipeline93is fixed to the heat insulating member900by a screw910a. The screw910aand the screw910bare not in contact with each other. Accordingly, the heat transfer via the screws for fixing the heating insulating member900is suppressed. Furthermore, in the fixing method shown inFIG.6, since the electric connection between the cover member11aand the pipeline93is not enough, the cover member11aand the flange93aare connected through a jumper wire913. The fixing method shown inFIG.6is also capable of suppressing the heat transfer between the cover member11aand the pipeline93and the leakage of the high frequency power from the gap between the cover member11aand the pipeline93. [Plasma Processing Method] FIG.7is a flowchart illustrating an example of a plasma processing method according to the first exemplary embodiment. Processings shown inFIG.7are carried out as the control device100controls the individual components of the apparatus main body10. First, the control device100starts a supply of the low-dew point gas into the antenna chamber by opening the valve96(S10). Then, until the plasma processing upon the wafer W is completed, the control device100controls the supply and a stop of the supply of the low-dew point gas into the antenna chamber such that a pressure within the antenna chamber becomes a positive pressure. The process S10is an example of a supplying process. Subsequently, the control device100determines whether a preset time has elapsed after the supply of the low-dew point gas into the antenna chamber is begun (S11). The preset time in the process S11refers to a time required until the air containing the moisture is completely exhausted from a gap of the antenna chamber and the antenna chamber is thus filled with the low-dew point gas through the supply of the low-dew point gas into the antenna chamber. If the preset time has not elapsed after the supply of the low-dew point gas into the antenna chamber is begun (S11: No), the control device100performs the processing of the process S11again. Meanwhile, if the preset time has elapsed after the supply of the low-dew point gas into the antenna chamber is begun (S11: Yes), the control device100controls the chiller unit94to start cooling of the shower head34(S12). The process S12is an example of a cooling process. Thereafter, the control device100determines whether a predetermined time has elapsed after the cooling of the shower head34is begun (S13). The predetermined time in the process S13refers to a time required until the shower head34is cooled to a required temperature. If the predetermined time has not elapsed after the cooling of the shower head34is begun (S13: No), the control device100performs the processing of the process S13again. Meanwhile, if the predetermined time has elapsed after the cooling of the shower head34is begun (S13: Yes), the control device100performs the plasma processing upon the wafer W by controlling the individual components of the apparatus main body10(S14). The process S14is an example of a plasma process. Then, the example plasma processing method shown in the present flowchart is ended. So far, the first exemplary embodiment has been described. As stated above, the plasma processing apparatus1according to the present exemplary embodiment is equipped with the processing vessel11, the placing table16, the shower head34, the high frequency power supply48, the cover member11a, the base member38and the valve96. The placing table16is disposed within the processing vessel11and serves as the lower electrode. The shower head34serves as the facing electrode of the placing table16. The high frequency power supply48forms the plasma from the gas within the processing vessel11by supplying the high frequency power to the shower head34, and the wafer W on the placing table16is processed by the plasma. The cover member11acovers the shower head34from thereabove. The base member38is provided within the cover member11aand cools the shower head34by using the coolant having the temperature lower than the dew point temperature of the exterior air outside the processing vessel11. The valve96supplies the low-dew point gas having the dew point temperature lower than that of the exterior air into the space surrounded by the cover member11aand the shower head34. Accordingly, the condensation near the shower head34can be suppressed. Further, in the above-described first exemplary embodiment, the low-dew point gas is an inert gas or dry air. Therefore, the condensation within the antenna chamber surrounded by the cover member11aand the shower head34can be suppressed. Moreover, in the above-described first exemplary embodiment, the valve96controls a flow rate of the low-dew point gas such that the pressure within the antenna chamber surrounded by the cover member11aand the shower head34becomes a positive pressure. Accordingly, the air containing the moisture is pushed out from the antenna chamber, so that the condensation within the antenna chamber can be suppressed. In addition, in the above-described first exemplary embodiment, the plasma processing apparatus1is further equipped with the chiller unit94and the pipeline93. The chiller unit94is provided at the outside of the cover member11aand controls the temperature of the coolant to be supplied to the base member38. A part of the pipeline93is disposed within the cover member11a, and the rest of the pipeline93is disposed at the outside the cover member11a. The coolant the temperature of which is adjusted by the chiller unit94is supplied to the base member38through this pipeline93. Further, the pipeline93is fixed to the sidewall of the cover member11awith the heat insulating member900having the electromagnetic shielding property and the heat insulating property therebetween. With this configuration, the condensation at the cover member11acan be suppressed, and the leakage of the high frequency power from a joint portion between the cover member11aand the pipeline93can be suppressed. Second Exemplary Embodiment In the plasma processing apparatus1according to the first exemplary embodiment, as the low-dew point gas is supplied into the antenna chamber and the air containing the moisture is thus pushed out from the antenna chamber, the inside of the antenna chamber is filled with the low-dew point gas. If, however, the airtightness of the antenna chamber is low, it is difficult to suppress the introduction of the exterior air into the antenna chamber even if the inside of the antenna chamber is set to be under the positive pressure. Thus, the antenna chamber needs to have a certain degree of airtightness. If, however, the degree of the airtightness of the antenna chamber is increased, it takes time to replace the gas within the antenna chamber. In consideration of the foregoing, in a second exemplary embodiment, the gas within the antenna chamber is forcibly exhausted by the exhaust device84before the supply of the low-dew point gas into the antenna chamber is begun. Accordingly, the time required to replace the gas within the antenna chamber can be shortened. Furthermore, since the airtightness of the antenna chamber can be increased, the leakage of the low-dew point gas can be suppressed, so that the consumption of the low-dew point gas can be reduced. FIG.8is a schematic cross sectional view illustrating an example of a plasma processing apparatus1according to the second exemplary embodiment. The plasma processing apparatus1of the second exemplary embodiment is different from the plasma processing apparatus1of the first exemplary embodiment in that a pipeline89and a valve90are further provided. InFIG.8, parts assigned same reference numerals as those ofFIG.1have the same configurations or same functions as those ofFIG.1, and redundant description will be omitted. The pipeline89connects the antenna chamber and the exhaust device84via the valve90. The valve90is opened before the low-dew point gas is supplied into the antenna chamber. Air within the antenna chamber is exhausted via the pipeline89and the valve90by the exhaust device84. FIG.9is a diagram illustrating a pressure variation within the antenna chamber. In the present exemplary embodiment, the control device100opens the valve90before the low-dew point gas is supplied into the antenna chamber and controls the exhaust device84to exhaust the air within the antenna chamber. Accordingly, a pressure within the antenna chamber is decreased. Then, by referring to a measurement value of a pressure gauge99, the control device100closes the valve90and stops the exhaust device84at a time to when the pressure within the antenna chamber becomes equal to or less than a pressure P3lower than a pressure P0of the exterior air outside the processing vessel11. The pressure P3is, e.g., 0.1 atmosphere. Then, the control device100starts the supply of the low-dew point gas into the antenna chamber by controlling the valve96. By referring to the measurement value of the pressure gauge99, the control device100then stops the supply of the low-dew point gas into the antenna chamber by controlling the valve96at a time t1when the pressure within the antenna chamber becomes equal to or higher than a pressure P1. Thereafter, the same as in the first exemplary embodiment, the supply and the stop of the supply of the low-dew point gas into the antenna chamber are controlled such that the pressure within the antenna chamber becomes the positive pressure (that is, a pressure between the pressure P1and the pressure P2). [Plasma Processing Method] FIG.10is a flowchart illustrating an example of a plasma processing method according to the second exemplary embodiment. Processings shown inFIG.10are carried out as the control device100controls individual components of the apparatus main body10. First, the control device100turns the valve90into an open state and operates the exhaust device84, thus starting an exhaust of the air within the antenna chamber (S20). Then, by referring to the measurement value of the pressure gauge99, the control device100determines whether the pressure P within the antenna chamber becomes equal to or less than the pressure P3(S21). If the pressure P within the antenna chamber is higher than the pressure P3(S21: No), the control device100performs the processing of the process S21again. Meanwhile, if the pressure P within the antenna chamber becomes equal to or less than the pressure P3(S21: Yes), the control device100turns the valve90into a closed state and stops the operation of the exhaust device84, thus stopping the exhaust of the air within the antenna chamber (S22). Subsequently, the control device100starts the supply of the low-dew point gas into the antenna chamber by turning the valve96into the open state (S23). Then, by referring to the measurement value of the pressure gauge99, the control device100determines whether the pressure P within the antenna chamber becomes equal to or higher than the pressure P1(S24). If the pressure P within the antenna chamber is lower than the pressure P1(S24: No), the control device100performs the processing of the process S24again. Meanwhile, if the pressure P within the antenna chamber is equal to or higher than the pressure P1(S24: Yes), the control device100stops the supply of the low-dew point gas into the antenna chamber by turning the valve96into the closed state (S25). Thereafter, the processes S12to S14described inFIG.7are performed. So far, the second exemplary embodiment has been described. As stated above, the plasma processing apparatus1of the second exemplary embodiment is equipped with the exhaust device84configured to exhaust the gas within the antenna chamber which is surrounded by the cover member11aand the shower head34. The valve96begins the supply of the low-dew point gas after the pressure within the antenna chamber becomes equal to or less than the preset pressure P3. Accordingly, the time required to replace the gas within the antenna chamber can be shortened. Furthermore, the consumption of the low-dew point gas can be reduced. Third Exemplary Embodiment Since the power feed rod44is the hollow cylindrical member, air exists in an internal space of the power feed rod44. If the internal space of the power feed rod44and the antenna chamber do not communicate with each other, the air still exists in the internal space of the power feed rod44even if the inside of the antenna chamber is filled with the low-dew point gas. If the shower head34is cooled, the power feed rod44which supplies the high frequency power to the shower head34is deprived of heat by the shower head34, so that a temperature of the power feed rod44is lowered. If the temperature of the power feed rod44is lowered, the condensation may form on an inner wall of the power feed rod44due to moisture of the air which exists in the internal space of the power feed rod44. If the condensation forms on the inner wall of the power feed rod44, a surface resistance of the inner wall of the power feed rod44may be partially changed because of water droplets formed by the condensation. As a result, the distribution of the high frequency power supplied to the shower head34via the power feed rod44may be disturbed. In view of the foregoing, in a third exemplary embodiment, a through hole500through which the internal space of the power feed rod44and the antenna chamber communicate with each other is formed at a sidewall of the power feed rod44.FIG.11is a partially enlarged cross sectional view illustrating an example of a plasma processing apparatus1according to the third exemplary embodiment. If at least one through hole500is formed at the sidewall of the power feed rod44, the internal space of the power feed rod44and the antenna chamber are allowed to communicate with each other. Therefore, the condensation on the inner wall of the power feed rod44can be suppressed. If, however, the through hole500is formed at the sidewall of the power feed rod44, the surface resistance of the power feed rod44may differ at a surface portion of the power feed rod44where the through hole500is formed and a surface portion thereof where the through hole500is not formed. As a result, the distribution of the high frequency power supplied to the shower head34via the power feed rod44may become non-uniform. In view of this, it is desirable that multiple through holes500are formed at axially symmetrical positions of the sidewall of the power feed rod44and the respective through holes500have the same shape and the same size. Desirably, the number of the through holes500formed at the axially symmetrical positions of the sidewall of the power feed rod44may be equal to or larger than three. Moreover, it is desirable that the through holes500are formed at an upper portion of the sidewall of the power feed rod44. To elaborate, it is desirable that the through holes500are formed at, in portions of the sidewall of the power feed rod44disposed within the antenna chamber, a portion higher than a portion corresponding to a half of a length of the power feed rod44. With this configuration, the distribution of the high frequency power, which is non-uniform on the surface of the power feed rod44due to the presence of the through holes500formed at the sidewall thereof, may be improved as it approaches the shower head34. So far, the third exemplary embodiment has been described. As stated above, the plasma processing apparatus1according to the third exemplary embodiment is equipped with the hollow power feed rod44disposed within the cover member11aand configured to guide the high frequency power supplied from the high frequency power supply48to the shower head34. The through holes500are formed at the sidewall of the power feed rod44. The antenna chamber of the cover member11aand the internal space of the power feed rod44communicate with each other through the through holes500. Accordingly, the condensation on the inner wall of the power feed rod44can be suppressed. Fourth Exemplary Embodiment If the shower head34is cooled, the power feed rod44connected to the shower head34is deprived of heat by the shower head34. Accordingly, a part of the power feed rod44located at the outside the cover member11aand the matching device46connected to the power feed rod44may also be cooled. Since the part of the power feed rod44located at the outside of the cover member11aand the matching device46are in contact with the exterior air outside the cover member11a, the condensation may form if they are cooled. The part of the power feed rod44located at the outside the cover member11amay be covered with a thermal insulator. However, it may be difficult to find a space for disposing the thermal insulator. Furthermore, since it is difficult to cover all electric components within the matching device46with the thermal insulator, it is difficult to suppress the condensation on the electric components within the matching device46. In view of the foregoing, in a fourth exemplary embodiment, the cooling of the power feed rod44and the matching device46are suppressed by heating a part of the power feed rod44by a heater510, as illustrated inFIG.12, for example.FIG.12is a partially enlarged cross sectional view illustrating an example of a plasma processing apparatus1according to the fourth exemplary embodiment. The heater510is configured to heat a part of the power feed rod44by a power supplied from a heater power supply512via a pipeline511. Accordingly, the temperature decrease of the power feed rod44due to the deprival of heat by the shower head34is suppressed, so that the cooling of the matching device46is suppressed. Therefore, the condensation on the power feed rod44and the matching device46are suppressed. Further, if a distance between a position of the power feed rod44heated by the heater510and an end portion of the power feed rod44connected to the shower head34is short, the shower head34may be heated by the heater510. For the reason, it is desirable that the heater510is provided around an upper portion of the power feed rod44. To elaborate, it is desirable that the heater510is provided around, in portions of the power feed rod44disposed within the antenna chamber, a portion higher than a portion corresponding to a half of a length of the power feed rod44disposed within the antenna chamber. With this configuration, the temperature rise of the shower head34by the heater510can be suppressed. So far, the fourth exemplary embodiment has been described. As stated above, the plasma processing apparatus1according to the present exemplary embodiment is equipped with the power feed rod44and the heater510. A part of the power feed rod44is disposed within the cover member11a, and this power feed rod44guides the high frequency power supplied from the high frequency power supply48to the shower head34. The heater510covers a part of the power feed rod44and heats the power feed rod44. Accordingly, the condensation on, for example, the matching device46disposed at the outside of the cover member11aand connected to the power feed rod44can be suppressed. Fifth Exemplary Embodiment In the fourth exemplary embodiment, a part of the power feed rod44is heated by heat generated by the heater510as the power from the heater power supply512is supplied thereto. In a fifth exemplary embodiment, however, a part of the power feed rod44is heated by circulating a heated fluid around the power feed rod44. FIG.13is a partially enlarged cross sectional view illustrating an example of a plasma processing apparatus1according to the fifth exemplary embodiment. In the present exemplary embodiment, a heating jacket520having a path521therein is provided around a part of the power feed rod44disposed within the cover member11a. A fluid having a temperature controlled by a temperature control device523is supplied into the path521via a pipeline522to be circulated therein. The fluid supplied into and circulated within the path521may be a liquid or a gas. The temperature of the fluid supplied into and circulated within the path521is controlled by the temperature control device523such that it is higher than the temperature of the coolant circulated within the path92of the base member38. Accordingly, the part of the power feed rod44is heated by the heating jacket520, so that the cooling of the matching device46and the like is suppressed. Further, in the present exemplary embodiment, if a distance between a position of the part of the power feed rod44heated by the heating jacket520and the end portion of the power feed rod44connected to the shower head34is short, the shower head34may be heated by the heating jacket520. For the reason, it is desirable that the heating jacket520is provided around an upper portion of the power feed rod44. To elaborate, it is desirable that the heating jacket520is provided around, in portions of the power feed rod44disposed within the antenna chamber, a portion higher than a portion corresponding to the half of the length of the power feed rod44disposed within the antenna chamber. With this configuration, the temperature rise of the shower head34by the heating jacket520can be suppressed. So far, the fifth exemplary embodiment has been described. As stated above, the plasma processing apparatus1of the present exemplary embodiment is equipped with the power feed rod44and the heating jacket520. A part of the power feed rod44is disposed within the cover member11aand configured to guide the high frequency power supplied from the high frequency power supply48to the shower head34. The heating jacket520has therein the path through which the heated fluid flows, and covers a part of the power feed rod44. The heating jacket520heats the power feed rod44by the fluid flown in the path. Accordingly, the condensation on the part of the power feed rod44disposed outside the cover member11aand the condensation on the matching device46disposed outside the cover member11aare suppressed. Sixth Exemplary Embodiment In the fourth and fifth exemplary embodiments, a part of the power feed rod44is heated form the outside of the power feed rod44. In a sixth exemplary embodiment, however, the power feed rod44is heated by circulating a heated fluid within the hollow inside of the power feed rod44. FIG.14is a partially enlarged cross sectional view illustrating an example of a plasma processing apparatus1according to the sixth exemplary embodiment. In the present exemplary embodiment, an insulating fluid having a temperature controlled by a temperature control device531is supplied into the power feed rod44via a pipeline530a. The fluid supplied into the power feed rod44is then returned back into the temperature control device531via a pipeline530b. The temperature control device531is an example of a fluid supply. The fluid supplied into and circulated within the power feed rod44may be a liquid or a gas. The temperature of the fluid supplied into and circulated within the power feed rod44is controlled by the temperature control device531such that it is higher than the temperature of the coolant circulated in the path92of the base member38. Accordingly, the power feed rod44is heated, and the cooling of the matching device46is suppressed. Further, in the present exemplary embodiment, it is desirable that the fluid having the temperature controlled by the temperature control device531is supplied, in the space within the power feed rod44, from an upper portion of the space, and then, is returned back into the temperature control device531from a lower portion of the space. Accordingly, a temperature distribution in which a temperature of the lower portion of the power feed rod44is lower than a temperature of the upper portion thereof can be produced. Therefore, the temperature rise of the shower head34due to the fluid flowing in the power feed rod44can be suppressed. So far, the sixth exemplary embodiment has been described. As stated above, the plasma processing apparatus1according to the present exemplary embodiment is equipped with the hollow power feed rod44and the temperature control device531. The power feed rod44is disposed within the cover member11aand configured to guide the high frequency power supplied from the high frequency power supply48to the shower head34. The temperature control device531circulates, in the space within the power feed rod44, the fluid having the temperature higher than the temperature of the coolant circulated in the path92of the base member38. Accordingly, the condensation on the part of the power feed rod44disposed outside the cover member11aand the condensation on the matching device46disposed outside the cover member11aare suppressed. [Others] The above-described exemplary embodiments are not limiting, and various changes and modifications may be made within the scope of the present disclosure. By way of example, in the above-described various exemplary embodiments, though the condensation on the members within the antenna chamber is suppressed by filling the antenna chamber with the low-dew point gas, the present disclosure is not limited thereto. For example, as another exemplary embodiment, the antenna chamber may be maintained hermetically, and the air within the antenna chamber may be exhausted such that the pressure of the air within the antenna chamber becomes equal to or less than a preset pressure. The preset pressure may be, e.g., 0.1 atmosphere. This exemplary embodiment may be achieved by a plasma processing apparatus1prepared by omitting the pipeline95, the valve96and the gas source98from the plasma processing apparatus1shown inFIG.8, for example, and by adding an APC valve instead of the valve90. The APC valve is an example of a pressure controller. If the pressure of the air is lowered, the dew point temperature of the air is also lowered. Therefore, even if the antenna chamber is not filled with the low-dew point gas, the condensation within the antenna chamber can be suppressed if the pressure of the air within the antenna chamber is lowered. Furthermore, in the above-described first and second exemplary embodiments, the high frequency power for plasma formation is supplied to the shower head34. However, the present disclosure is not limited thereto. By way of example, the high frequency power for plasma formation may be supplied to the placing table16. Even in this case, the temperature of the shower head34may be increased due to the heat input from the plasma formed between the shower head34and the placing table16, so that the shower head34may be cooled and the condensation may be formed within the cover member11a. In consideration of this, by filing the inside of the cover member11awith the low-dew point gas as in the first and second exemplary embodiment, such condensation within the cover member11acan be suppressed. Moreover, the first exemplary embodiment or the second exemplary embodiment may be combined with any one of the third to sixth exemplary embodiments. Further, the third exemplary embodiment may be combined with the fourth exemplary embodiment or the fifth exemplary embodiment. In addition, in the above-described various exemplary embodiments, capacitively coupled plasma (CCP) is used as an example of a plasma source. However, the present disclosure is not limited thereto. By way of example, inductively coupled plasma (ICP), microwave-excited surface wave plasma (SWP), electron cyclotron resonance plasma (ECP), helicon wave plasma (HWP), or the like may be used as the plasma source. According to the exemplary embodiment, it is possible to suppress condensation in the vicinity of the upper electrode. From the foregoing, it will be appreciated that various embodiments of the present disclosure have been described herein for purposes of illustration, and that various modifications may be made without departing from the scope and spirit of the present disclosure. Accordingly, the various embodiments disclosed herein are not intended to be limiting. The scope of the inventive concept is defined by the following claims and their equivalents rather than by the detailed description of the exemplary embodiments. It shall be understood that all modifications and embodiments conceived from the meaning and scope of the claims and their equivalents are included in the scope of the inventive concept. The claims of the present application are different and possibly, at least in some aspects, broader in scope than the claims pursued in the parent application. To the extent any prior amendments or characterizations of the scope of any claim or cited document made during prosecution of the parent could be construed as a disclaimer of any subject matter supported by the present disclosure, Applicants hereby rescind and retract such disclaimer. Accordingly, the references previously presented in the parent applications may need to be revisited. | 57,856 |
11862437 | DETAILED DESCRIPTION When an edge ring is raised excessively and thus a lower surface thereof becomes higher than an upper surface of a support table, a gap is generated between the edge ring and the support table. Then, plasma enters below the edge ring through the gap, and thus an arc discharge may occur. In order to prevent this, the edge ring needs to be vertically moved as far as the lower surface is not beyond the upper surface of the support table. Therefore, there may be a case where the plasma cannot be more uniformed by restriction of a height of the edge ring, even if the plasma can be more uniformed by raising the edge ring. One embodiment of the present invention provides an edge ring that is provided along an outer circumference of a support table for supporting a substrate, and is capable of increasing a vertically movable range. According to one embodiment of this disclosure, an edge ring is provided which includes a first movable portion provided along an outer circumference of a support portion having an upper surface capable of holding a semiconductor substrate thereon, the first movable portion being movable in a direction perpendicular to the upper surface; a second movable portion provided along an outer circumference of the first movable portion, the second movable portion being movable in the direction; and a driving portion capable of moving the first movable portion in the direction by way of the second movable portion. Non-limiting, exemplary embodiments of the present disclosure will now be described with reference to the accompanying drawings. In the drawings, the same or corresponding reference marks are given to the same or corresponding members or components, and redundant explanations will be omitted. It is to be noted that the drawings are illustrative of the disclosure, and there is no intention to indicate scale or relative proportions among the members or components. Therefore, the specific size should be determined by a person having ordinary skill in the art in view of the following non-limiting embodiments. FIG.1is a view schematically illustrating a structure of a plasma processing apparatus according to one embodiment. As illustrated, a plasma processing apparatus10has a chamber11, which is provided with a gas supplying port13through which a process gas to be used in a plasma process is supplied and a gas exhausting port14through which the process gas is exhausted. A process gas-supplying source (not illustrated) is connected to the gas supplying port13through a predetermined pipe, and an exhausting apparatus (not illustrated) such as a vacuum pump is connected to gas exhausting port14. Additionally, the chamber11is formed of metal such as aluminum or alloys such as stainless steel. The chamber11is grounded. A support plate21is provided inside the chamber11. The support plate21may have an electrostatic chuck. With this, a substrate100, which is a target of the plasma processing, can be held on the upper surface of the support plate21. The support plate21is fixed to be located at substantially the center in the chamber11by a support member12. Additionally, an edge ring22is provided along an outer circumferential surface of the support plate21. The edge ring22is provided to adjust an electric field so that the electric field is not deflect in an outer circumference of the substrate100with respect to a vertical direction (a direction perpendicular to the upper surface of the substrate to be processed). Explanation is made later about structures of the support plate21and the edge ring22. Additionally, an electricity supply line31that supplies a high frequency power electricity is connected to the support plate21. The electricity supply line31has a blocking capacitor32, a matching box33, and a high frequency power source34connected thereto. High frequency power of predetermined frequency is supplied to the support plate21from the high frequency power source34. Namely, the support plate21also functions as a bottom electrode. Above the support plate21, an upper electrode42is provided to be faced with the support plate21. The upper electrode42is fixed to a member41provided on a top plate in the chamber11with a predetermined distance away from the support plate21so as to face parallel to the support plate21. By such a structure, the upper electrode42and the support plate21constitutes a pair of parallel plate electrodes. The upper electrode42has, for example, a disk shape. The upper electrode42is an electrode formed of, for example, silicon. Note that, the upper electrode42and member41are provided with multiple gas feed paths (not illustrated) that penetrate therethrough in a thickness direction. With this, the process gas is introduced inside the chamber11from gas supplying port13through the gas feed paths. An opening15, which allows the substrate100to be transferred into or out from the chamber11, is provided on a side surface of the chamber11. The opening15has a shutter52provided therein. The shutter52functions to partition an interior of the chamber11from the outside. When the substrate100is transferred in and out, the shutter52is opened to allow the opening15and the chamber11to be in communication with each other. In the opening15, a sensor53is provided which detects a position of a carrier arm of the substrate100conveyed into and out from the chamber11by the carrier arm (not illustrated). The sensor53may be, for example, a range sensor. Additionally, although not illustrated inFIG.1, an elevator23is provided on a bottom surface of the chamber11. The elevator23is described later. Referring now toFIGS.2and3, explanations are made on the support plate21and the edge ring22.FIG.2is a top plan view illustrating the support plate21and the edge ring22; andFIG.3is a cross-sectional partially enlarged view taken along a I-I line ofFIG.2. A small-diameter portion211of an upper plate21U of the support plate21is illustrated inFIG.2. The small-diameter portion211has a circular shape in planar view as illustrated, and serves as a support member supporting the substrate100thereon. The small-diameter portion211has, for example but not limited to, a slightly larger diameter than a diameter of the substrate100as illustrated inFIG.3. Therefore, an outer circumferential portion (for example, a bevel portion) of the substrate100extends outward the small-diameter portion211when the substrate100is supported by the small-diameter portion211. Additionally, as illustrated inFIG.3, the upper plate21U has a large-diameter portion212concentrically to the small-diameter portion211below the small-diameter portion211. With this, a step is created between the small-diameter portion211and the large-diameter portion212, and the upper surface of the large-diameter portion212is exposed. For example, the upper plate21U having such a shape can be formed of ceramic materials such as Al2O3and AlN. Additionally, the upper plate21U may be provided with an electrostatic chuck that can hold the substrate100electrostatically. The upper plate21U is fixed on a base21B by, for example, an adhesive and the like, as illustrated inFIG.3. The base21B can be formed of metal such as aluminum or alloys such as stainless steel. Additionally, conduits may be formed within the base21B. The base21B can adjust a temperature of the upper plate21U and then the substrate100supported thereon by supplying into the conduits a fluid adjusted to a predetermined temperature. The edge ring22is arranged to surround the support plate21. The edge ring22has a stationary ring221, an inner movable ring222(a first moving part), an outer movable ring223(a second moving part), and a lifter22L (drive). The stationary ring221, the inner movable ring222, and the outer movable ring223may be formed of, for example, silicon carbide (SiC) and the like. Additionally, the lifter22L is formed of aluminum (Al), in this embodiment, and the surface thereof is coated with yttria (Y2O3). With this coating, the lifter22L can be protected by charged particles and the like within plasma produced in the chamber11. The stationary ring221is composed of a cylindrical portion221C and a flange portion221F extending outward from a bottom end of the cylindrical portion221C. With this, the stationary ring221has a ring shape in planar view, and an L-shaped cross-section. The stationary ring221is arranged concentrically to the small-diameter portion211of the upper plate21U so that an inner circumferential surface of the cylindrical portion221C faces an outer circumferential surface of the small-diameter portion211of the upper plate21U. Additionally, the flange portion221F of the stationary ring221is placed on the large-diameter portion212of the upper plate21U. The upper surface of the cylindrical portion221C is lower than the upper surface of the small-diameter portion211of the upper plate21U in order not to touch the substrate100supported by the upper plate21U. The flange portion221F has a size that does not extend diametrically beyond the large-diameter portion212of the upper plate21U. The inner movable ring222is composed of a cylindrical portion222C and a flange portion222F extending outward from the upper end of the cylindrical portion222C. With this, the inner movable ring222has a ring shape in planar view, and an L-shaped cross-section. The inner movable ring222is arranged so that the cylindrical portion222C is placed on the flange portion221F of the stationary ring221in between the cylindrical portion221C of the stationary ring221and the outer movable ring223. Therefore, the inner movable ring222is arranged concentrically to the stationary ring221and the cylindrical portion221C of the small-diameter portion211of the upper plate21U. Additionally, a height of the inner movable ring222is approximately equal to a height of the outer movable ring223. Therefore, the upper surface of the inner movable ring222is flush with the upper surface of the outer movable ring223, when the inner movable ring222and the outer movable ring223are placed on the flange portion221F of the stationary ring221. The outer movable ring223is composed of a disk portion223C and a flange portion223F extending inward from the bottom end of the disk portion223C. The outer movable ring223is placed on the upper surface of the flange portion221F of the stationary ring221and is supported by the lifter22L. With this, the outer movable ring223is arranged concentrically to the upper plate21U, the stationary ring221and the inner movable ring222. Additionally, the flange portion223F of the outer movable ring223is located below the flange portion222F of the inner movable ring222. Here, as illustrated inFIG.3, the upper surface of the flange portion223F of the outer movable ring223and the lower surface of the flange portion222F of the inner movable ring222are kept away with each other only by a distance L The lifter221L, which has a cylinder shape with an inner surface224, is placed to surround the outside of the support plate21and the stationary ring221. Additionally, as illustrated inFIG.3, the lifter22L supports on an upper surface thereof the outer movable ring223. Moreover, for example, three recesses22D are formed (FIG.2) in a reverse surface of the lifter22L, and shafts23S of an elevator23are inserted into corresponding recesses22D, as illustrated inFIG.3. The lifter22L and the outer movable ring223can be moved upward and downward by the elevator23vertically moving the shafts23S. With the above-mentioned structure, when the elevator23raises the shafts23S, the lifter22L is lifted by the shafts23S, and thus the outer movable ring223is moved upward. When the flange portion223F of the outer movable ring223comes to contact the flange portion222F of the inner movable ring222along with the upward movement of the outer movable ring223, the inner movable ring222is also lifted, as illustrated inFIG.4. Namely, the inner movable ring222is raisable by the elevator23by way of the outer movable ring223. When the inner movable ring222is lifted by the outer movable ring223, the bottom end of the cylindrical portion222C is located below the lower surface of the outer movable ring223only by a distance L. Here, an upward movement distance of the lifter22L due to the elevator23is restricted so that the bottom end of the inner movable ring222is located at the same elevation as the upper end of the stationary ring221or lower. With this, a closed space SP is maintained which is surrounded by the stationary ring221, the inner movable ring222, the outer movable ring223, and the lifter22L. Next, referring to a comparative example, explanation is made on effects exerted by the above-described structure.FIGS.5A and5Bare partially expanded cross-sectional views illustrating an edge ring220according to the comparative example. As illustrated inFIG.5A, the edge ring220according to the comparative example includes a stationary ring220S, a movable ring220M, and a lifter220L, and is arranged at the outer circumference of a support plate210composed of an upper plate210U and a base210B. Additionally, as clearly understood by comparingFIG.5AwithFIG.3, the edge ring220according to the comparative example does not have a member corresponding to the inner movable ring222of for the edge ring22. Here, a case is considered where the move movable ring220M is moved upward by the lifter220L in order to adjust distribution of plasma produced within the plasma processing chamber (not illustrated) provided with the support plate210and the edge ring220. In this case, a gap G is generated as illustrated inFIG.5Bbetween the stationary ring220S and the movable ring220M when the movable ring220M is raised. When such a gap G is generated, an arc discharge may occur through the gap G. Additionally, because electric potential around the support plate210may change due to the gap G, there may be a situation where plasma distribution to be adjusted by changing a position of the edge ring22cannot be realized, and plasma uniformity may be deteriorated. On the other hand, according to the edge ring22of the embodiment, because the closed space SP is maintained even when the outer movable ring223is raised as described above, an arc discharge through a gap such as a gap G in the comparative example rarely occurs. Therefore, an effect is exerted where plasma is distributed as intended by moving the outer movable ring223in a wider range. Here, it is assumed that the stationary ring220S of the edge ring220in the comparative example and the stationary ring221of the edge ring22in the embodiment have the same dimensions; and that the movable ring220M of the edge ring220in the comparative example and the outer movable ring223of the edge ring22in the embodiment have the same thickness. In this case, a movable range of the outer movable ring223is increased by the distance L compared to the movable ring220M. Furthermore, when an edge ring is used in a plasma processing apparatus and thus the upper surface thereof is exposed to plasma, the edge ring may be worn. When this happens, the edge ring becomes thinner. As a result, in the edge ring220according to the comparative example, for example, a raising distance until the gap G is generated becomes shorter when the movable ring220M is raised. If the edge ring220cannot be raised further in order to avoid an arc discharge and the like through the gap G, a situation may arise where distribution of the plasma cannot be sufficiently adjusted. Therefore, the edge ring220needs to be highly frequently replaced, and maintenance costs expenses of the plasma processing apparatus might be increased. Additionally, downtime of the plasma processing apparatus may also be increased by replacing the edge ring220. In the edge ring22according to the embodiment, because the closed space SP is maintained by the cylindrical portion222C of the inner movable ring222even if the inner movable ring222and the outer movable ring223are worn, the rising distance (movable range) may be prevented from being decreased. Therefore, the edge ring22can be replaced less frequently than the edge ring220according to the comparative example. Along with this, maintenance costs and downtime of the plasma processing apparatus are expected to be lower. Modification Referring now toFIGS.6A and6B, explanation is made on an edge ring according to modification of the embodiment.FIGS.6A and6Bare partially enlarged views of a support plate and an edge ring according to the modification of the embodiment. In the edge ring according to the modification, shapes of a stationary ring and an inner movable ring are different from the stationary ring221and the inner movable ring222according to the embodiment, respectively, and other structures are the same. The edge ring according to the modification is described as follows, focusing on the difference. As illustrated inFIG.6A, an edge ring22M1according to the modification has a stationary ring221M1. The stationary ring221M1has a cylindrical shape and is arranged concentrically with the support plate21. Namely, the stationary ring221M1is different from the stationary ring221of the edge ring22according to the embodiment in that the stationary ring221M1does not have the flange portion221F. With this, the outer movable ring223is supported by the lifter22L without being placed on the flange portion221F. Additionally, the inner movable ring222of the edge ring22M1has a cylindrical portion222C and a flange portion222F. However, a lower surface of the cylindrical portion222C is in contact with the large-diameter portion212of the upper plate21U. Here, the cylindrical portion222C of the inner movable ring222extends lower than a lower surface of the outer movable ring223by a distance L1. Additionally, a lower surface of the flange portion222F of the inner movable ring222is in contact with an upper surface of collar portion233F of the outer movable ring223. According to such a structure, the inner movable ring222is lifted along with the upward movement of the outer movable ring223by the lifter22L. Here, an upward moving distance of the lifter22L by the elevator23(FIG.3) is restricted so that a bottom end of the inner movable ring222is at the same level of, or lower, the upper end of the stationary ring221. With this, as illustrated inFIG.6B, the closed space SP is maintained which is surrounded by the large-diameter portion212of the upper plate21U, the stationary ring221M1, the inner movable ring222, the outer movable ring223, and the lifter22L. Therefore, the effect exerted by the edge ring22according to the embodiment is also exerted by the edge ring22M1according to the modification. Note that, in the modification, the movable range of the outer movable ring223is increased more by the distance L1than the movable range of the movable ring220M of the edge ring220according to the comparative example. While certain embodiments have been described, these embodiments have been presented by way of example only, and are not intended to limit the scope of the inventions. Indeed, the novel embodiments described herein may be embodied in a variety of other forms; furthermore, various omissions, substitutions and changes in the form of the embodiments described herein may be made without departing from the spirit of the inventions. The accompanying claims and their equivalents are intended to cover such forms or modifications as would fall within the scope and spirit of the inventions. | 19,534 |
11862438 | DETAILED DESCRIPTION Hereinafter, embodiments of a plasma processing apparatus, a calculation method, and a calculation program will be described in detail with reference to the drawings. In the present disclosure, for example, an apparatus that performs plasma etching will be described in detail as a specific example of the plasma processing apparatus. Further, the plasma processing apparatus, the calculation method, and the calculation program to be disclosed are not limited by the embodiments. There is known a plasma processing apparatus for performing an etching process using plasma on a semiconductor wafer (hereinafter, referred to as a “wafer”). In the plasma processing apparatus, a focus ring is arranged to surround the wafer. Since the plasma processing apparatus includes the focus ring disposed to surround the wafer, a plasma state around the wafer becomes uniform so that uniformity of etching characteristics of the entire wafer surface can be obtained. However, the focus ring is consumed and its thickness becomes thinner by etching. In the plasma processing apparatus, the etching characteristics on the outer peripheral portion of the wafer deteriorate as the focus ring is consumed. Therefore, it is necessary to periodically replace the focus ring in the plasma processing apparatus. Conventionally, in plasma processing apparatus, a replacement time of the focus ring is determined based on past results such as the number of processed wafers, or whether the focus ring should be replaced or not is determined by periodically processing the wafer in which the etching characteristics on the outer peripheral portion of the wafer is monitored. However, the plasma processing apparatus performs the processings with different process recipes. For this reason, the plasma processing apparatus requires the use of a replacement time that gave a certain amount of margin to the past results and, thus, the productivity of the plasma processing apparatus decreases. Further, the periodic processing of the wafer that is monitored also decreases the productivity of the plasma processing apparatus. Although the above problems have been described based on the consumption of the focus ring, the same problem occurs for all consumable parts that are consumed by the plasma processing. Therefore, a technique for obtaining the degree of consumption of consumable parts that are consumed by the plasma processing is expected in the plasma processing apparatus. First Embodiment (Configuration of Plasma Processing Apparatus) First, a configuration of a plasma processing apparatus10according to a first embodiment will be described.FIG.1is a cross-sectional view showing an example of a schematic configuration of the plasma processing apparatus according to the first embodiment. The plasma processing apparatus10shown inFIG.1is a capacitively-coupled parallel-plate plasma etching apparatus. The plasma processing apparatus10includes a substantially cylindrical processing chamber12. The processing chamber12is made of, e.g., aluminum. Further, the processing chamber12has an anodically oxidized surface. A mounting table16is provided in the processing chamber12. The mounting table16includes an electrostatic chuck18and a base20. An upper surface of the electrostatic chuck18is a mounting surface on which a target object to be subjected to plasma processing is mounted. In the present embodiment, a wafer W that is the target object is mounted on the upper surface of the electrostatic chuck18. The base20has a substantially disc shape, and a main part thereof is made of a conductive metal, e.g., aluminum. The base20serves as a lower electrode. The base20is supported by a support portion14. The support portion14is a cylindrical member vertically extending upward from a bottom portion of the processing chamber12. A first high-frequency power supply HFS is electrically connected to the base20through a matching unit MU1. The first high-frequency power supply HFS is a power supply for plasma generation and applies a high-frequency power having a frequency in a range from 27 to 100 MHz, e.g., 40 MHz. Accordingly, plasma is generated directly on the base20. The matching unit MU1includes a circuit for matching output impedance of the first high-frequency power supply HFS with input impedance of a load side (base20side). Further, a second high-frequency power supply LFS is electrically connected to the base20through the matching unit MU2. The second high-frequency power supply LFS generates and applies a high-frequency power (high-frequency bias power) for attracting ions into the wafer W to the base20. As a result, a bias potential is generated in the base20. The high-frequency bias power has a frequency in a range from 400 kHz to 13.56 MHz, e.g., 3 MHz. The matching unit MU2includes a circuit for matching output impedance of the second high-frequency power supply LFS with input impedance of the load side (base20side). The electrostatic chuck18is disposed on the base20. The wafer W is attracted to and held on the electrostatic chuck18by an electrostatic force such as Coulomb force. The electrostatic chuck18includes an electrode μl for electrostatic adsorption in a main body portion formed of ceramic. A DC power supply22is electrically connected to the electrode μl through a switch SW1. The electrostatic force for attracting and holding the wafer W depends on a value of a DC voltage applied from the DC power supply22. On the mounting table16, a consumable part that is consumed by the plasma processing is mounted. For example, a focus ring FR is disposed as the consumable part to surround the wafer W on the electrostatic chuck18. The focus ring FR is provided to improve uniformity of plasma processing. The focus ring FR is formed of a material appropriately selected depending on the plasma processing to be performed. For example, the focus ring FR may be formed of silicon or quartz. A coolant channel24is formed in the base20. The coolant is supplied to the coolant channel24from a chiller unit provided outside of the processing chamber12through a line26a. The coolant supplied to the coolant channel24returns to the chiller unit through a line26b. An upper electrode30is provided in the processing chamber12. The upper electrode30is disposed above the mounting table16to be opposite to the mounting table16. The mounting table16and the upper electrode30are arranged to be substantially parallel to each other. The upper electrode30is supported at an upper portion of the processing chamber12via an insulating shielding member32. The upper electrode30includes an electrode plate34and an electrode holder36. The electrode plate34faces a processing space S, and a plurality of gas injection holes34aare formed in the electrode plate34. The electrode plate34is formed of a low resistance conductor or semiconductor with a small Joule heat. The upper electrode30is configured to perform a temperature control. For example, the upper electrode30includes a temperature control mechanism such as a heater (not shown) to perform the temperature control. The electrode holder36detachably holds the electrode plate34. The electrode holder36is made of a conductive material such as aluminum. A gas diffusion chamber36ais formed in the electrode holder36. In the electrode holder36, a plurality of gas through holes36bextend downward from the gas diffusion chamber36ato communicate with the gas injection holes34a. Further, a gas inlet port36cthrough which a processing gas is introduced into the gas diffusion chamber36ais formed in the electrode holder36. A gas supply line38is connected to the gas inlet port36c. A gas source group (GS)40is connected to the gas supply line38through a valve group (VG)42and a flow rate controller group (FRC)44. The valve group42includes a plurality of opening and closing valves. The flow rate controller group44includes a plurality of flow rate controllers that are mass flow controllers. Further, the gas source group40includes a plurality of gas sources for various kinds of gases required for plasma processing. The gas sources of the gas source group40are connected to the gas supply line38through the opening and closing valves and the mass flow controllers corresponding thereto. In the plasma processing apparatus10, one or more gases from one or more selected gas sources among the gas sources of the gas source group40are supplied to the gas supply line38. Each of one or more gases supplied to the gas supply line38is supplied to the gas diffusion chamber36aand is injected to the processing space S through the gas through holes36band the gas injection holes34a. Further, the plasma processing apparatus10further includes a ground conductor12a. The ground conductor12ais a substantially cylindrical ground conductor and extends upward from the sidewall of the processing chamber12so as to be located at a position higher than the height position of the upper electrode30. Further, in the plasma processing apparatus10, the deposition shield46is detachably provided along the inner wall of the processing chamber12. Further, the deposition shield46is also provided at an outer periphery of the support portion14. The deposition shield46prevents etching by-products (deposits) from adhering to the processing chamber12. The deposition shield46may be made of aluminum coated with ceramic such as Y2O3or the like. The deposition shield46is configured to perform a temperature control. For example, the deposition shield46includes a temperature control mechanism such as a heater (not shown) to perform the temperature control. A gas exhaust plate48is provided at the bottom portion side of the processing chamber12and between the support portion14and the inner wall of the processing chamber12. The gas exhaust plate48may be formed by coating aluminum with ceramic, e.g., Y2O3or the like. A gas exhaust port12eis provided below the gas exhaust plate48in the processing chamber12. A gas exhaust unit (EU)50is connected to the gas exhaust port12ethrough a gas exhaust line52. The gas exhaust unit50includes a vacuum pump such as a turbo molecular pump or the like so that a pressure in the space in the processing chamber12can be decreased to a predetermined vacuum level when performing the plasma processing. Further, a loading/unloading port12gfor the wafer W is provided at the sidewall of the processing chamber12. The loading/unloading port12gcan be opened and closed by a gate valve54. The operation of the plasma processing apparatus10configured as mentioned above is integrally controlled by a control unit100. The control unit100is, e.g., a computer and controls the respective components of the plasma processing apparatus10. The operation of the plasma processing apparatus10is integrally controlled by the control unit100. (Configuration of Mounting Table) Next, the mounting table16will be described in detail.FIG.2is a plan view showing the mounting table according to the first embodiment. As described above, the mounting table16includes the electrostatic chuck18and the base20. The electrostatic chuck18is formed of ceramic, and an upper surface thereof is a mounting region18aon which the wafer W and the focus ring FR are mounted. The mounting region18abecomes a substantially circular region in the plan view. As shown inFIG.1, the electrostatic chuck18includes the electrode μl for electrostatic adsorption in a region where the wafer W is disposed. The electrode μl is connected to the DC power supply22through the switch SW1. As shown inFIG.1, heaters HT are provided below the electrode μl in the mounting region (mounting surface)18a. The mounting region18ais divided into a plurality of division regions75, and the heaters HT are provided in the division regions75, respectively. For example, as shown inFIG.2, the mounting region18aincludes a central circular division region75aand an annular division region75b. The heaters HT are provided in the division region75aand75b, respectively. For example, a heater HT1is provided in the division region75aand a heater HT2is provided in the division region75b. The wafer W is disposed on the division region75a. The focus ring FR is disposed on the division region75b. In the present embodiment, the upper surface (mounting surface) of the mounting table16is divided into two division regions75aand75bto perform the temperature control. However, the number of division regions75is not limited to two, and may be three or more. The heaters HT are individually connected to the heater power supply HP shown inFIG.1through wirings (not shown). The heater power supply HP supplies individually adjusted electric powers to the heaters HT under the control of the control unit100. As a result, the heat generated by each heater HT is individually controlled, and the temperatures of the division regions75in the mounting region18aare individually adjusted. The heater power supply HP includes a power detection unit PD configured to detect a supply power supplied to each heater HT. Further, the power detection unit PD may be provided separately from the heater power supply HP by disposing on a wiring through which electric power flows from the heater power supply HP to each heater HT. The power detection unit PD detects the supply power supplied to each heater HT. For example, the power detection unit PD detects the amount of power [W] as the supply power supplied to each heater HT. The heater HT generates heat in accordance with the amount of power. For this reason, the amount of power supplied to the heater HT indicates a heater power. The power detection unit PD notifies the control unit100of power data indicating the detected supply power to each heater HT. Further, the mounting table16includes a temperature sensor (not shown) configured to detect a temperature of the heater HT in each division region75of the mounting region18a. The temperature sensor may be an element that measures the temperature while providing separately from the heater HT. Further, the temperature sensor may be an element that is disposed on a wiring through which electric power flows to the heater HT and detects the temperature by using the property in which electrical resistance increases as the temperature increases. Sensing values detected by each temperature sensor are sent to a temperature measuring unit TD. The temperature measuring unit TD measures a temperature of each division region75of the mounting region18afrom the respective sensor values. The temperature measuring unit TD notifies the control unit100of temperature data indicating the temperature of each division region75of the mounting region18a. Further, heat transfer gas such as He gas may be supplied between the upper surface of the electrostatic chuck18and the rear surface of the wafer W by a heat transfer gas supply mechanism and a gas supply line that are not illustrated. (Configuration of Control Unit) Next, the control unit100will be described in detail.FIG.3is a block diagram showing an example of a schematic configuration of the control unit100that controls the plasma processing apparatus according to the first embodiment. The control unit100may be, e.g., a computer and includes an external interface101, a process controller102, a user interface103, and a storage unit104. The external interface101is configured to communicate with the respective components of the plasma processing apparatus10to input and output various types of data. For example, power data indicating the supply power from the power detection unit PD to each heater HT is input to the external interface101. Further, temperature data indicating the temperature of each division region75of the mounting region18ais input to the external interface101from the temperature measuring unit TD. Further, the external interface101outputs to the heater power supply HP control data for controlling the supply power supplied to each heater HT. The process controller102includes a central processing unit (CPU) and controls the respective components of the plasma processing apparatus10. The user interface103includes a keyboard through which a process manager input commands to manage the plasma processing apparatus10, a display for visualizing and displaying an operation status of the plasma processing apparatus10, and the like. The storage unit104stores therein a control program (software) for realizing various processes performed by the plasma processing apparatus10under the control of the process controller102and recipes including processing condition data and the like. The storage unit104also stores parameters relating to an apparatus, a process, and the like for performing plasma processing. Further, the control program, the recipe, and the parameters may be stored in a computer-readable storage medium (e.g., a hard disk, an optical disk such as a DVD, a flexible disk, a semiconductor memory, or the like). Alternatively, the control program, the recipe, and the parameters may be stored in another device to be read online, e.g., through a dedicated line and used. The process controller102includes an internal memory for storing a program or data, reads out the control program stored in the storage unit104, and executes processing of the read-out control program. The process controller102serves as various processing units by executing the control program. For example, the process controller102serves as a heater control unit102a, a measurement unit102b, a parameter calculation unit102c, a setting temperature calculation unit102d, and an alarm unit102e. Further, in the present embodiment, although the case where the process controller102serves as various processing units will be described as an example, the present disclosure is not limited thereto. For example, the functions of the heater control unit102a, the measurement unit102b, the parameter calculation unit102c, the setting temperature calculation unit102d, and the alarm unit102emay be distributed and realized by a plurality of controllers and realized. However, in plasma processing, the progress of processing changes depending on the temperature. For example, in plasma etching, the progress speed of etching changes depending on the temperatures of the wafer W and the focus ring FR. Therefore, in the plasma processing apparatus10, it is conceivable to control the temperatures of the wafer W and the focus ring FR to a target temperature by using each heater HT. A flow of energy affecting the temperatures of the wafer W and the focus ring FR will be described. Hereinafter, the flow of energy affecting the temperature of the focus ring FR will be described only, but the flow of energy affecting the temperature of the wafer W is similar thereto.FIG.4schematically shows the flow of energy affecting the temperature of the focus ring. InFIG.4, the focus ring FR and the mounting table16including the electrostatic chuck (ESC)18are illustrated in a simplified manner. Further, in an example ofFIG.4, the flow of energy affecting the temperature of the focus ring FR with respect to one division region75(the division region75b) of the mounting region18aof the electrostatic chuck18is shown. The mounting table16includes the electrostatic chuck18and the base20. The electrostatic chuck18and the base20are bonded by a bonding layer19. The heater HT (the heater HT2) is provided in the electrostatic chuck18. The coolant channel24through which a coolant flows is formed in the base20. The heater HT2generates heat by the power supplied from the heater power supply HP, and a temperature thereof increases. InFIG.4, the power supplied to the heater HT2is denoted as a heater power Ph. In the heater HT2, a heat generation amount (heat flux) qhper unit area, which is obtained by dividing the heater power Phby an area A of the region where the heater HT2of the electrostatic chuck18is provided, is generated. In the plasma processing apparatus10, when temperatures of internal parts arranged in the processing chamber12such as the upper electrode30and the deposition shield46are controlled, radiant heat is generated from the internal parts. For example, when the temperatures of the upper electrode30and the deposition shield46are controlled at a high temperature to suppress adhesion of deposits, the radiant heat is input to the focusing ring FR from the upper electrode30and the deposition shield46. InFIG.4, the radiant heat from the upper electrode30and/or the deposition shield46to the focus ring FR is denoted as “qr.” Further, when the plasma processing is performed, heat is input to the focus ring FR from the plasma. InFIG.4, heat flux from the plasma per unit area, which is obtained by dividing the heat amount from the plasma to the focus ring FR by an area of the focus ring FR, is denoted as “qp.” The temperature of the focus ring FR is increased by input of the heat flux qpfrom the plasma and input of the radiant heat qr. The heat input by the radiant heat is proportional to the temperatures of the internal parts of the processing chamber12. For example, the heat input by the radiant heat is proportional to the fourth power of the temperatures of the upper electrode30and/or the deposition shield46. It is known that the heat input from the plasma is proportional to the product of the amount of ions in the plasma irradiated to the focus ring FR and a bias potential for attracting the ions in the plasma to the focus ring FR. The amount of ions in the plasma irradiated to the focus ring FR is proportional to an electron density of the plasma. The electron density of the plasma is proportional to the high-frequency power of the first high-frequency power supply HFS applied for the plasma generation. Further, the electron density of the plasma depends on a pressure inside the processing chamber12. The bias potential for attracting the ions in the plasma to the focus ring FR is proportional to the high-frequency power of the second high-frequency power supply LFS applied for the bias potential generation. Further, the bias potential for attracting the ions in the plasma to the focus ring FR depends on the pressure inside the processing chamber12. When the high-frequency power is not applied to the mounting table16, the ions are attracted to the mounting table16by a potential difference between a plasma potential generated when the plasma is generated and a potential of the mounting table16. Further, the heat input from the plasma includes irradiation to the focus ring FR by electrons or radicals in the plasma or heating by light emission of the plasma, a surface reaction on the focus ring FR due to ions and radicals, and the like. These components also depend on the powers of the high-frequency power supplies and/or the pressure inside the processing chamber12. In addition, the heat input from the plasma also depends on device parameters relating to the plasma generation, such as the distance between the mounting table16and the upper electrode30or the type of gas supplied to the processing space S. The heat transferred to the focus ring FR is transferred to the electrostatic chuck18. Here, not all the heat of the focus ring FR is transferred to the electrostatic chuck18, and the heat is transferred to the electrostatic chuck18depending on the difficulty of heat transfer such as the degree of contact between the focus ring FR and the electrostatic chuck18. The difficulty of heat transfer, which is the thermal resistance, is inversely proportional to a sectional area normal to a heat transfer direction. For this reason, inFIG.4, the difficulty of heat transfer from the focus ring FR to a surface of the electrostatic chuck18is denoted as the thermal resistance Rth·A per unit area between the focus ring FR and the surface of the electrostatic chuck18where A is the area of the region (division region75b) where the heater HT2is provided. Rthis a thermal resistance in the whole region where the heater HT2is provided. Further, inFIG.4, the heat input amount from the focus ring FR to the surface of the electrostatic chuck18is denoted as heat flux q per unit area from the focus ring FR to the surface of the electrostatic chuck18. Further, the thermal resistance Rth·A depends on the surface state of the electrostatic chuck18, the value of a DC voltage applied from the DC power supply22during the holding of the focus ring FR, and the pressure of the heat transfer gas supplied between an upper surface of the electrostatic chuck18and a rear surface of the focus ring FR. In addition, the thermal resistance Rth·A also depends on device parameters involved in the thermal resistance or thermal conductivity. The heat transferred to the surface of the electrostatic chuck18increases the temperature of the electrostatic chuck18and is also transferred to the heater HT2. InFIG.4, a heat input amount from the surface of the electrostatic chuck18to the heater HT2is denoted as heat flux qcper unit area from the surface of the electrostatic chuck18to the heater HT2. Meanwhile, the base20is cooled by a coolant flowing through the coolant channel24and cools the electrostatic chuck18being in contact therewith. At this time, inFIG.4, a heat loss amount from a rear surface of the electrostatic chuck18to the base20through the bonding layer19is denoted as heat flux qsusper unit area from the rear surface of the electrostatic chuck18to the base20. The heater HT2is cooled by this heat loss, and thereby, the temperature is reduced. The focus ring FR is consumed and its thickness becomes thinner by etching. In the plasma processing apparatus10, when the focus ring FR is consumed and the thickness thereof is reduced, the amount of heat input to the heater HT during plasma processing changes. Here, the change in the amount of heat input to the heater HT2due to the consumption of the focus ring FR will be described.FIG.5schematically shows a flow of energy before the focus ring is consumed. In addition, the heat input of the radiant heat is omitted due to a small influence. When the temperature of the heater HT2is controlled to be constant, the sum of the heat input amount input to the heater HT2and the heat generation amount generated by the heater HT2is equal to the heat loss amount lost from the heater HT2, at a position of the heater HT2. For example, in a non-ignition state in which the plasma is not ignited, the sum of the heat generation amount generated by the heater HT2is equal to the heat loss amount lost from the heater HT2. In an example of the “non-ignition state” shown inFIG.5, the heat amount of “10” is lost from the heater HT2by the cooling from the base20. When the temperature of the heater HT2is controlled to be constant, the heat amount of “10” is generated in the heater HT2by the heater power Phfrom the heater power supply HP. In an ignition state in which the plasma is ignited, the heat from the plasma is also input to the heater HT2through the electrostatic chuck18. The ignition state includes a transient state and a steady state. In the transient state, for example, a heat input amount of the focusing ring FR or the electrostatic chuck18is greater than the heat loss amount thereof, and thereby, the temperature of the focus ring FR or the electrostatic chuck18tends to increase over time. In the steady state, the heat input amount and the heat loss amount of the focus ring FR or the electrostatic chuck18are equal to each other, and thereby, the temperature of the focus ring FR or the electrostatic chuck18does not tend to increase over time, and the temperature becomes substantially constant. Further, in the ignition state, the temperature of the focus ring FR increases due to the heat input from the plasma until the wafer reaches the steady state. To the heater HT2, heat is transferred from the focus ring FR through the electrostatic chuck18. As described above, when the temperature of the heater HT2is controlled to be constant, the heat amount input to the heater HT2is equal to the heat amount lost from the heater HT2. The heat amount required for maintaining the temperature of the heater HT2to be constant is reduced in the heater HT2. For this reason, the power supplied to the heater HT2is reduced. For example, in an example of the “transient state” shown inFIG.5, a heat amount of “5” is transferred from the plasma to the focus ring FR. Further, the heat transferred to the focus ring FR is transferred to the electrostatic chuck18. Further, when the temperature of the focus ring FR is not in the steady state, a part of the heat transferred to the focus ring FR contributes to an increase of the temperature of the focus ring FR. The heat amount contributing to the increase in the temperature of the focus ring FR depends on the heat capacity of the focus ring FR. Therefore, the heat amount of “3” among the heat amount of “5” transferred to the focus ring FR is transferred from the focus ring FR to the surface of the electrostatic chuck18. The heat transferred to the surface of the electrostatic chuck18is transferred to the heater HT2. Further, when the temperature of the electrostatic chuck18is not in the steady state, a part of the heat transferred to the surface of the electrostatic chuck18contributes to an increase in the temperature of the electrostatic chuck18. The heat amount contributing to the increase in the temperature of the electrostatic chuck18depends on the heat capacity of the electrostatic chuck18. Therefore, a heat amount of “2” among the heat amount of “3” transferred to the surface of the electrostatic chuck18is transferred to the heater HT2. For this reason, when the temperature of the heater HT2is controlled to be constant, a heat amount of “8” is supplied to the heater HT2by the heater power Phfrom the heater power supply HP. Further, in an example of the “steady state” shown inFIG.5, the heat amount of “5” is transferred from the plasma to the focus ring FR. The heat transferred to the focus ring FR is transferred to the electrostatic chuck18. Further, when the temperature of the focus ring FR is in the steady state, the heat input amount and the heat output amount of the focus ring FR are equal to each other. Therefore, the heat amount of “5” transferred from the plasma to the focus ring FR is transferred from the focus ring FR to the surface of the electrostatic chuck18. The heat transferred to the surface of the electrostatic chuck18is transferred to the heater HT2. When the temperature of the electrostatic chuck18is in the steady state, a heat input amount and a heat output amount of the electrostatic chuck18are equal to each other. Therefore, the heat amount of “5” transferred to the surface of the electrostatic chuck18is transferred to the heater HT2. For this reason, when the temperature of heater HT2is controlled to be constant, a heat amount of “5” is supplied to the heater HT2by the heater power Phfrom the heater power supply HP. FIG.6schematically shows a flow of energy after the focus ring is consumed. The heat input of the radiant heat is omitted due to a small influence. InFIG.6, since the focus ring FR is consumed by the etching, the focus ring FR has a thickness thinner than that ofFIG.5. In the non-ignition state, even when the focus ring FR is consumed and its thickness is reduced, the flow of energy is the same as that before the consumption of the focus ring FR shown inFIG.5. In an example of the “non-ignition state” shown inFIG.6, the heat amount of “10” is lost from the heater HT2by the cooling from the base20. When the temperature of the heater HT2is controlled to be constant, the heat amount of “10” is generated in the heater HT2by the heater power Phfrom the heater power supply HP. In the ignition state, the heat from the plasma is also input to the heater HT2through the electrostatic chuck18. When the focus ring FR is consumed and its thickness is reduced, the heating time of the focus ring FR is shortened. For example, in an example of the “transient state” shown inFIG.6, a heat amount of “5” is transferred from the plasma to the focus ring FR. Further, the heat transferred to the focus ring FR is transferred to the electrostatic chuck18. Further, when the temperature of the focus ring FR is not in the steady state, a part of the heat transferred to the focus ring FR contributes to an increase of the temperature of the focus ring FR. For example, when the focus ring FR is consumed and its thickness is reduced, the heat amount of “4” among the heat amount of “5” transferred to the focus ring FR is transferred from the focus ring FR to the surface of the electrostatic chuck18. The heat transferred to the surface of the electrostatic chuck18is transferred to the heater HT2. Further, when the temperature of the electrostatic chuck18is not in the steady state, a part of the heat transferred to the surface of the electrostatic chuck18contributes to an increase in the temperature of the electrostatic chuck18. The heat amount contributing to the increase in the temperature of the electrostatic chuck18depends on the heat capacity of the electrostatic chuck18. Therefore, a heat amount of “3” among the heat amount of “4” transferred to the surface of the electrostatic chuck18is transferred to the heater HT2. For this reason, when the temperature of the heater HT2is controlled to be constant, a heat amount of “7” is supplied to the heater HT2by the heater power Phfrom the heater power supply HP. Further, in an example of the “steady state” shown inFIG.6, the heat amount of “5” is transferred from the plasma to the focus ring FR. The heat transferred to the focus ring FR is transferred to the electrostatic chuck18. Further, when the temperature of the focus ring FR is in the steady state, the heat input amount and the heat output amount of the focus ring FR are equal to each other. Therefore, the heat amount of “5” transferred from the plasma to the focus ring FR is transferred from the focus ring FR to the surface of the electrostatic chuck18. The heat transferred to the surface of the electrostatic chuck18is transferred to the heater HT2. When the temperature of the electrostatic chuck18is in the steady state, a heat input amount and a heat output amount of the electrostatic chuck18are equal to each other. Therefore, the heat amount of “5” transferred to the surface of the electrostatic chuck18is transferred to the heater HT2. For this reason, when the temperature of heater HT2is controlled to be constant, a heat amount of “5” is supplied to the heater HT2by the heater power Phfrom the heater power supply HP. As illustrated inFIGS.5and6, the power supplied to the heater HT2is lower in the ignition state than that in the non-ignition state. Further, in the ignition state, the power supplied to the heater HT2is lowered until the steady state. Further, in the transient state, even if the amount of heat input from the plasma is the same, the power supplied to the heater HT2changes depending on the thickness of the focus ring FR. Further, as shown inFIGS.5and6, when the temperature of the heater HT2is controlled to be constant, even if the state is any of the “non-ignition state,” the “transient state,” and the “steady state,” the heat amount of “10” is lost from the heater HT2by the cooling from the base20. That is, the heat flux qsusper unit area from the heater HT2to the coolant supplied to the coolant channel24formed inside the base20is always constant, and a temperature gradient from the heater HT2to the coolant is always constant. For this reason, the temperature sensor used to control the temperature of the heater HT2to be constant does not need to be directly installed in the heater HT2. For example, the temperature difference between the heater HT2and the temperature sensor is always constant as long as the temperature sensor is installed between the heater HT2and the coolant, such as the rear surface of the electrostatic chuck18, inside of the bonding layer19, and inside of the base20. Thus, by calculating the temperature difference ΔT between the temperature sensor and the heater HT2using thermal conductivity, thermal resistance, and the like of a material between the heater HT2and the temperature sensor and by adding the temperature difference ΔT to a value of the temperature detected by the temperature sensor, it is possible to output the temperature of the heater HT2and to control the actual temperature of the heater HT2so as to be constant. FIG.7shows an example of a change in the temperature of the focus ring and a change in the supply power to the heater.FIG.7illustrates an example of a result of measuring the temperature of the focus ring FR and the supply power to the heater HT2by controlling the temperature of the heater HT2so as to be constant, and igniting the plasma from the non-ignition state in which the plasma is not ignited. A solid line shown inFIG.7denotes a change in the supply power to the heater HT2in the case of a new focus ring FR (before consumption). The dashed line shown inFIG.7denotes a change in the supply power to the heater HT2in the case of the focus ring FR after the new focus ring FR is consumed and its thickness has become thinner than before. A period T1shown inFIG.7is the non-ignition state in which the plasma is not ignited. In the period T1, the supply power to the heater HT2is constant. A period T2shown inFIG.7is the ignition state in which the plasma is ignited and in the transient state. In the period T2, the supply power to the heater HT2is decreased. In the period T2, the temperature of the focus ring FR increases to a certain temperature. A period T3shown inFIG.7is the ignition state in which the plasma is ignited. In the period T3, the temperature of the focus ring FR becomes constant and in the steady state. If the electrostatic chuck18also enters the steady state, a tendency of the supply power to decrease stabilizes and the supply power to the heater HT2becomes substantially constant. The tendency of the power supplied to the heater HT2to decrease in the transient state, illustrated in the period T2ofFIG.7, is changed due to the heat input amount from the plasma to the focus ring FR, the thermal resistance between the focus ring FR and the surface of the electrostatic chuck18, the thickness of the focus ring FR and the like. As described above, when the temperature of the heater HT2is controlled to be constant, the heater power Phchanges depending on the heat input amount from the plasma to the focus ring FR, the thermal resistance between the focus ring FR and the surface of the electrostatic chuck18and/or the thickness of the focus ring FR. Therefore, a graph of the supply power to the heater HT2in the period T2shown inFIG.7may be modeled by taking the heat input amount from the plasma to the focus ring FR, the thermal resistance between the focus ring FR and the surface of the electrostatic chuck18and/or the thickness of the focus ring FR as parameters. That is, a change in the supply power to the heater HT2in the period T2may be modeled by calculation equations by taking the heat input amount from the plasma to the focus ring FR, the thermal resistance between the focus ring FR and the surface of the electrostatic chuck18and the thickness of the focus ring FR as parameters. In the present embodiment, the change in the supply power to the heater HT2in the period T2shown inFIG.7is modeled as an equation based on unit area. For example, the heat generation amount qhfrom the heater HT2per unit area when a heat flux is generated from the plasma may be expressed by the following equation (2) in an equation group 1. The heat generation amount qh0from the heater HT per unit area in the steady state when no heat flux is generated from the plasma may be expressed by the following equation (3) in the equation group 1. The thermal resistance Rthc·A per unit area between the surface of the electrostatic chuck18and the heater HT2may be expressed by the following equation (4) in the equation group 1. When a1, a2, a3, λ1, λ2, τ1, and τ2are expressed by the following equations (5) to (11) in the equation group 1 by taking the heat flux qpand the thermal resistance Rthas parameters, the heat generation amount qhmay be expressed by the following equation (1) in the equation group 1. (EquationGroup1)qh=qh0-qp-Rth·A·qpRthc·A·(λ1-λ2){(1+a2+a3a1·a3·λ2)(a1+λ1)exp(-tτ1)-(1+a2+a3a1·a3·λ1)(a1+λ2)exp(-tτ2)}(1)qh=Ph/A(2)qh0=Ph0/A(3)Rthc·A=zcκc(4)a1=1ρFR·CFR·zFR·Rth·A(5)a2=2ρc·Cc·zc·Rth·A(6)a3=2ρc·Cc·zc·Rthc·A(7)λ1=12{-(a1+a2+a3)+(a1+a2+a3)2-4a1a3}(8)λ2=12{-(a1+a2+a3)-(a1+a2+a3)2-4a1a3}(9)τ1=-1λ1(10)τ1=-1λ2(11) In the equation group 1, Phis the heater power [W] when the heat flux is generated from the plasma. Ph0is the heater power [W] in the steady state when no heat flux is generated from the plasma. qhis the heat generation amount [W/m2] from the heater HT2per unit area when the heat flux is generated from the plasma. qh0is the heat generation amount [W/m2] from the heater HT2per unit area in the steady state when no heat flux is generated from the plasma. qpis the heat flux [W/m2] per unit area from the plasma to the focus ring FR. Rth·A is the thermal resistance [K·m2/W] per unit area between the focus ring FR and the surface of the electrostatic chuck18. Rthc·A is the thermal resistance [K·m2/W] per unit area between the surface of the electrostatic chuck18and the heater. A is the area [m2] of the division region75(the division region75b) in which the heater HT2is provided. ρFRis the density [kg/m3] of the focus ring FR. CFRis the heat capacity [J/K·m2] per unit area of the focus ring FR. zFRis the thickness [m] of the focus ring FR. ρcis the density [kg/m3] of ceramic forming the electrostatic chuck18. Ccis the heat capacity [J/K·m2] per unit area of the ceramic forming the electrostatic chuck18. zcis the distance [m] from the surface of the electrostatic chuck18to the heater HT2. κcis the thermal conductivity [W/K·m] of the ceramic forming the electrostatic chuck18. t is the elapsed time [sec] after the plasma is ignited. Regarding a1expressed in the equation (5), 1/a1is a time constant indicating the difficulty of warming the focus ring FR. Further, with respect to a2expressed in the equation (6), 1/a2is a time constant indicating the difficulty of heat input into the electrostatic chuck18and the difficulty of warming the electrostatic chuck18. Further, with respect to a3expressed in the equation (7), 1/a3is a time constant indicating the difficulty of heat infiltration into the electrostatic chuck18and the difficulty of warming the electrostatic chuck18. The density ρFRof the focus ring FR and the heat capacity CFRper unit area of the focus ring FR are determined in advance from an actual configuration of the focus ring FR, respectively. The area A of the heater HT2, the density ρcof ceramic forming the electrostatic chuck18, and the heat capacity Ccper unit area of the ceramic forming the electrostatic chuck18are determined in advance from the actual configuration of the plasma processing apparatus10, respectively. The distance zcfrom the surface of the electrostatic chuck18to the heater HT2and the thermal conductivity κcof the ceramic forming the electrostatic chuck18are also determined in advance from the actual configuration of the plasma processing apparatus10. Rthc·A is determined in advance by the equation (4) from the thermal conductivity κcand the distance zc. The thickness zFRof the focus ring FR is determined to be a specific value in the case of the new focus ring FR, but the value of the thickness zFRchanges as the new focus ring FR is consumed by etching. Therefore, when the focus ring FR is consumed, the thickness zFRof the focus ring FR also becomes a parameter. The plasma processing apparatus10may perform plasma processings with various process recipes. The heat input amount from the plasma to the focus ring FR and the thermal resistance between the focus ring FR and the surface of the electrostatic chuck18during the plasma processing can be obtained as follows. For example, the plasma processing apparatus10performs the plasma processing after a new focus ring FR is disposed and measures the heater power Ph0of the heater HT2during the plasma processing. The heater power Phwhen there is heat flux from the plasma for each elapsed time t after the plasma is ignited, and the heater power Ph0in the steady state when there is no heat flux from the plasma may be obtained from the measurement results therefor in the plasma processing apparatus10. As expressed by the equation (2), by dividing the obtained heater power Phby the area A of the heater HT2, the heat generation amount qhof the heater HT2per unit area when there is the heat flux from the plasma may be obtained. Further, as expressed by the equation (3), by dividing the obtained heater power Ph0by the area A of the heater HT2, the heat generation amount qh0of the heater HT2per unit area in the steady state when there is no heat flux from the plasma may be obtained. As for the thickness zFRof the focus ring FR, in the case of the new focus ring FR, the value of the thickness of the new focus ring FR can be used. The thickness of the new focus ring FR may be stored in the storage unit104through an input from the user interface103or the like, and the value of the thickness stored in the storage unit104may be used. Alternatively, the thickness of the new focus ring FR may be obtained by measuring the value thereof by another measuring device through a network or the like. The heat flux qpand the thermal resistance Rth·A are obtained by performing fitting of the measurement results by using the equations (1) to (11) as the calculation model. In other words, when the thickness of the focus ring FR is determined to be a specific value as in the case of the new focus ring FR, the plasma processing apparatus10performs the fitting with the equations (1) to (11) by using the measurement results, so that the heat flux qpand the thermal resistance Rth·A can be obtained. In the steady state ofFIGS.5and6, the heat input amount from the plasma to the focus ring FR is added from the non-ignition state and is input to the heater HT2without mitigation. For this reason, the heat input amount from the plasma to the focus ring FR may be calculated from a value of the difference between the supply power in the non-ignition state of the period T1and the supply power in the steady state of the period T3shown inFIG.7. For example, the heat flux qpmay be calculated from a value obtained by calculating a difference between the heater power Ph0(in the non-ignition state) when there is no heat flux from the plasma and the heater power Phin the steady state of the period T3and converting the difference into a value per unit area, as expressed by the following equation (12). Further, the heat flux qpmay be calculated from a difference between the heat generation amount qh0from the heater HT2per unit area and the heat generation amount qhfrom the heater HT2per unit area, as expressed by the following equation (12). qp=(Ph0−Ph)/A=qh0−qh(12) In this manner, the heat input amount from the plasma to the focus ring FR and the thermal resistance between the focus ring FR and the surface of the electrostatic chuck18during the plasma processing are obtained. The plasma processing apparatus10performs the same plasma processing on each of the loading and unloading wafers W. In this case, the heat input amount from the plasma to the focus ring FR and the thermal resistance between the focus ring FR and the surface of the electrostatic chuck18in each plasma processing can be considered to be the same. When the heat input amount and the thermal resistance are obtained, the thickness zFRof the focus ring FR can be obtained as follows. For example, the plasma processing apparatus10performs the plasma processing and measures the heater power Ph0of the heater HT2during the plasma processing. The heater power Phwhen there is heat flux from the plasma for each elapsed time t after the plasma is ignited, and the heater power Ph0in the steady state when there is no heat flux from the plasma may be obtained from the measurement results in the plasma processing apparatus10. Then, as expressed by the equation (2), by dividing the obtained heater power Phby the area A of the heater HT2, the heat generation amount qhof the heater HT2per unit area when there is the heat flux from the plasma may be obtained. Further, as expressed by the equation (3), by dividing the obtained heater power Ph0by the area A of the heater HT2, the heat generation amount qh0of the heater HT2per unit area in the steady state when there is no heat flux from the plasma may be obtained. For the heat flux qpand the thermal resistance Rth·A, values obtained using a new focus ring FR are used, for example. The thickness zFRof the focus ring FR can be obtained by performing the fitting of the measurement results by using the above equations (1) to (11) as the calculation model. In other words, when the heat flux qpand the thermal resistance Rth·A are determined in advance, the plasma processing apparatus10uses the measurement results to perform the fitting with the equations (1) to (11), thereby obtaining the thickness zFRof the focus ring FR. Further, the graph of the temperature of the focus ring FR in the period T2shown inFIG.7may also be modeled by taking the heat input amount from the plasma to the focus ring FR, the thermal resistance between the focus ring FR and the surface of the electrostatic chuck18, and the thickness of the focus ring FR as parameters. In the present embodiment, a change in the temperature of the focus ring FR in the period T2is modeled as an equation based on unit area. For example, when a1, a2, a3, λ1, λ2, τ1, and τ2illustrated in the equations (5) to (11) are used by taking the heat flux qp, the thermal resistance Rth·A, and the thickness zFRas parameters, a temperature TFRof the focus ring FR may be expressed by the following equation (13). TFR=Th+qp·(Rth·A+Rthc·A)+qPρFR·CFR·zFR·(λ1-λ2){(1+a2+a3a1·a3·λ2)exp(-tτ1)-(1+a2+a3a1·a3·λ1)exp(-tτ2)}(13) Here, TFRis the temperature [° C.] of the focus ring. This the temperature [° C.] of the heater HT2that is controlled to be constant. The temperature Thof the heater may be obtained from the conditions at the actual time of controlling the temperature of the focus ring FR to be constant. When the heat flux qp, the thermal resistance Rth·A and the thickness zFRare obtained, the temperature TFRof the focus ring FR may be calculated from the equation (13). When the elapsed time t is sufficiently longer than the time constants τ1and τ2expressed in the equations (10) and (11), the equation (13) may be omitted as in the following equation (14). That is, in a case of calculating the temperature Thof the heater HT2when the temperature TFRof the focus ring FR becomes a target temperature after transition to the steady state of the period T3shown inFIG.7, the equation (13) may be expressed as the following equation (14). TFR=Th+qp·(Rth·A+Rthc·A) (14) For example, the temperature TFRof the focus ring FR may be obtained from the temperature Thof the heater, the heat flux qp, and the thermal resistances Rth·A and Rthc·A by the equation (14). Referring back toFIG.3, the heater control unit102acontrols temperatures of the respective heaters HT. For example, the heater control unit102aoutputs, to the heater power supply HP, control data indicating a supply power to each heater HT to control the supply power supplied from the heater power supply HP to each heater HT, thereby controlling temperatures of the respective heaters HT. At the time of the plasma processing, a target setting temperature of each heater HT is set in the heater control unit102a. For example, a target temperature is set as the setting temperature of the heater HT for each division region75of the mounting region18ain the heater control unit102a. The target temperature may be a temperature at which the plasma etching accuracy is the best. The heater control unit102acontrols the supply power to each heater HT such that each heater HT achieves the setting temperature at the time of the plasma processing. For example, the heater control unit102acompares the temperature of each division region75of the mounting region18arepresented by the temperature data input to the external interface101with the setting temperature of the corresponding division region75. This comparison is carried out for each division region75. By using the comparison results, the heater control unit102aspecifies the division region75having a temperature lower than the setting temperature and the division region75having a temperature higher than the setting temperature. The heater control unit102aoutputs, to heater power supply HP, control data for increasing the supply power to the division region75having a temperature lower than the setting temperature and control data for reducing the supply power to the division region75having a temperature higher than the setting temperature. The measurement unit102bmeasures the supply power supplied to each heater HT. In the present embodiment, the measurement unit102bmeasures the supply power to the heater HT2by using the supply power to the heater HT2represented by the power data input to the external interface101. For example, the measurement unit102bmeasures the supply power to the heater HT2when the plasma processing is performed while the supply power to the heater HT2is controlled by the heater control unit102asuch that the temperature of the heater HT2is constant. For example, the measurement unit102bmeasures the supply power to the heater HT2in a non-ignition state where the plasma is not ignited before the start of the plasma processing. Further, the measurement unit102bmeasures the supply power to the heater HT2in a transient state before the tendency of the supply power to the heater HT2to decrease stabilizes such that the supply power to the heater HT becomes constant after the plasma is ignited. Further, after the plasma is ignited, the measurement unit102bmeasures the supply power to the heater HT2in a steady state where the decrease of the supply power to the heater HT2is stopped and the supply power to the heater HT2becomes constant. The supply power to the heater HT2in the non-ignition state may be measured at least once, or an average of values obtained by measuring several times may be set as the supply power in the non-ignition state. The supply power to the heater HT2in the transient state and the steady state may be measured twice or more. Further, the timing of measuring the supply power may include the timing when the tendency of the supply power to decrease is large. Further, when the number of times of measurement is small, the measurement timing may be separated by a predetermined period of time. In the present embodiment, the measurement unit102bmeasures the supply power to the heater HT2at a predetermined time interval (e.g., at an interval of 0.1 second) during the plasma processing. Therefore, the supply power to the heater HT2in the transient state and the steady state is measured several times. The measurement unit102bmeasures the supply power to the heater HT2in the non-ignition state and the supply power to the heater HT2in the transient state in a predetermined cycle. For example, when the plasma processing is performed after the focus ring FR is replaced and a wafer W and a new focus ring FR that have not been consumed are mounted on the mounting table16, the measurement unit102bmeasures the supply power to the heater HT2in the non-ignition state and the supply power to the heater HT2in the transient state. The measurement unit102bmeasures the supply power to the heater HT2in the non-ignition state and the supply power to the heater HT2in the transient state whenever the wafer W is replaced and the replaced wafer W is mounted on the mounting table16to perform the plasma processing. Further, for example, the parameter calculation unit102cmay measure the supply power to the heater HT2in the non-ignition state and the supply power to the heater HT2in the transient state for each plasma processing. The parameter calculation unit102ccalculates a heat input amount and a thermal resistance by using the supply power in the non-ignition state and the supply power in the transient state measured by the measurement unit102bwhen a new focus ring FR is placed on the mounting table16and the plasma processing is performed. First, the parameter calculation unit102ccalculates the heat generation amount of the heater HT2for maintaining the temperature of the heater HT2at a predetermined temperature in the non-ignition state. For example, the parameter calculation unit102ccalculates the heater power Ph0in the non-ignition state from the supply power to the heater HT2in the non-ignition state. Further, the parameter calculation unit102ccalculates the thermal resistance between the focus ring FR and the mounting table16and the heat input amount flowing into the mounting table16from the plasma in the ignition state. For example, the parameter calculation unit102ccalculates the heat input amount and the thermal resistance by performing the fitting with a calculation model, which has the heat input amount and the thermal resistance as parameters and calculates the supply power in the transient state, by using the supply power in the non-ignition state and the supply power in the transient state. For example, the parameter calculation unit102ccalculates the heater power Ph0of the heater HT2in the non-ignition state for each elapsed time t. Further, the parameter calculation unit102ccalculates the heater power Phof the heater HT2in the transient state for each elapsed time t. The parameter calculation unit102ccalculates the heat generation amount qh0from the heater HT2per unit area in the non-ignition state for each elapsed time t by dividing the calculated heater power Ph0by an area A for the heater HT2. Further, the parameter calculation unit102ccalculates the heat generation amount qhfrom the heater HT2per unit area in the transient state for each elapsed time t by dividing the calculated heater power Phby the area A for the heater HT2. In addition, the parameter calculation unit102cperforms the fitting of the heat generation amount qhand the heat generation amount qh0for each elapsed time t by using the equations (1) to (11) as the calculation model, and calculates the heat flux qpand the thermal resistance Rth·A having the lowest degree of error. The thickness value of the new focus ring FR is used as the thickness zFRof the focus ring FR. Further, the parameter calculation unit102cmay calculate the heat input amount from the plasma to the focus ring FR from the difference between the supply power in the non-ignition state and the supply power in the steady state. For example, the parameter calculation unit102cmay calculate the heat flux qpby dividing the difference between the heater power Ph0in the non-ignition state and the heater power Phin the steady state by the area A of the heater HT2by using the equation (12). When the heat flux qpand the thermal resistance Rth·A during the plasma processing in the plasma processing apparatus10are given in advance by experiments or other methods, it is not necessary to calculate the heat flux qpand the thermal resistance Rth·A. Next, the parameter calculation unit102ccalculates the thickness zFRof the focus ring FR by using the supply power in the non-ignition state and the supply power in the transient state measured by the measurement unit102bwhen the wafer W is replaced and the replaced wafer W is mounted on the mounting table16and the plasma processing is performed. First, the parameter calculation unit102ccalculates the heat generation amount of the heater HT2for maintaining the temperature of the heater HT2at a predetermined temperature in the non-ignition state. For example, the parameter calculation unit102ccalculates the heater power Ph0in the non-ignition state from the supply power to the heater HT2in the non-ignition state. Then, the parameter calculation unit102ccalculates the thickness zFRof the focus ring FR. For example, the parameter calculation unit102ccalculate the thickness zFRof the focus ring FR by performing the fitting with a calculation model, which has the thickness zFRof the focus ring FR as a parameter and calculates the supply power in the transient state, by using the supply power in the non-ignition state and the supply power in the transient state. For example, the parameter calculation unit102ccalculates the heater power Ph0of the heater HT2in the non-ignition state for each elapsed time t. Further, the parameter calculation unit102ccalculates the heater power Phof the heater HT2in the transient state for each elapsed time t. The parameter calculation unit102ccalculates the heat generation amount qh0from the heater HT2per unit area in the non-ignition state for each elapsed time t by dividing the calculated heater power Ph0by an area A for the heater HT2. Further, the parameter calculation unit102ccalculates the heat generation amount qhfrom the heater HT2per unit area in the transient state for each elapsed time t by dividing the calculated heater power Phby the area A for the heater HT2. In addition, the parameter calculation unit102cperforms the fitting of the thickness zFRof the focus ring FR by using the equations (1) to (11) as the calculation model, and calculates the thickness zFRof the focus ring FR having the lowest degree of error. The values of the heat flux qpand the thermal resistance Rth·A obtained by using the new focus ring FR are used as the heat flux qpand the thermal resistance Rth·A. Alternatively, when the heat flux qpand the thermal resistance Rth·A are given in advance by experiments or other methods, the values of the given heat flux qpand the given thermal resistance Rth·A may be used. As a result, the plasma processing apparatus10according to the present embodiment is capable of determining the thickness zFRof the consumed focus ring FR. Here, when the plasma processing is continued, the focus ring FR is further consumed. For this reason, it is important for the plasma processing apparatus to check the thickness of the focus ring FR in a timely manner. However, since the focus ring FR is installed in the processing chamber12, it is not possible to directly measure the thickness of the focus ring FR. Therefore, in the conventional plasma processing apparatus, the replacement time of the focus ring is determined based on the past results such as the number of processed wafers W or whether the focus ring should be replaced or not is determined by periodically processing the wafer W in which the etching characteristics on the outer peripheral portion of the wafer is monitored. However, the plasma processing apparatus may perform the processings with different process recipes. For this reason, the plasma processing apparatus requires the use of a replacement time that gave a certain amount of margin to the past results and, thus, the productivity of the plasma processing apparatus decreases. Further, the periodic processing of the wafer that is monitored also decreases the productivity of the plasma processing apparatus. Therefore, for example, it is conceivable to arrange sensors in the processing chamber12and measure the thickness of the focus ring FR with the sensors. However, when the sensors are disposed in the processing chamber12, the manufacturing cost of the plasma processing apparatus10increases. Further, when the sensors are disposed in the processing chamber12, the sensors become a singular point and deteriorate the uniformity of the plasma processing around the singular point. Therefore, it is desirable to obtain the thickness of the focus ring FR in the plasma processing apparatus without disposing the sensors in the processing chamber12. The plasma processing apparatus10according to the present embodiment can obtain the thickness of the focus ring FR without disposing the sensors in the processing chamber12, and the degree of the consumption of the focus ring FR can be determined from the thickness of the focus ring FR. As described above, since the plasma processing apparatus10according to the present embodiment can obtain the thickness of the focus ring FR, it can be used as follows. For example, in a system in which a plurality of plasma processing apparatuses10are arranged to etch the wafer W, it is controlled such that the number of wafers W to be processed in the plasma processing apparatus10with a small consumption amount of the focus ring FR is increased to adjust the maintenance timing of the plasma processing apparatus10. As a result, the maintenance downtime of the entire system can be shortened, and the productivity can be improved. The setting temperature calculation unit102dcalculates a setting temperature of the heater HT2at which the focus ring FR reaches a target temperature by using the calculated heat input amount, thermal resistance, and thickness zFRof the focus ring FR. For example, the setting temperature calculation unit102dsubstitutes the calculated heat flux qp, the calculated thermal resistance Rth·A, and the calculated thickness zFRof the focus ring FR into the equations (5), (6), and (12) to obtain the values of a1, a2, a3, λ1, λ2, τ1and τ2expressed in the equations (5) to (11). The setting temperature calculation unit102duses the obtained a1, a2, a3, λ1, λ2, τ1and τ2to calculate the temperature Thof the heater HT2at which the temperature TFRof the focus ring FR becomes the target temperature from the equation (12). For example, the setting temperature calculation unit102dcalculates the temperature Thof the heater HT2at which the temperature TFRof the focus ring FR becomes the target temperature by setting the elapsed time t as a predetermined value large enough to be regarded as the steady state. The calculated temperature Thof the heater HT2is the temperature of the heater HT2that makes the temperature of the focus ring FR reach the target temperature. Further, the temperature Thof the heater HT2at which the temperature of the focus ring FR becomes the target temperature may be obtained from the equation (13). In addition, the setting temperature calculation unit102dmay calculate the temperature TFRof the focus ring FR at the current temperature Thof the heater HT2from the equation (14). For example, the setting temperature calculation unit102dcalculates the temperature TFRof the focus ring FR at the current temperature Thof the heater HT2when the elapsed time t is set to a predetermined value large enough to be regarded as the steady state. Next, the setting temperature calculation unit102dcalculates a difference ΔTFRbetween the calculated temperature TFRand the target temperature. Then, the setting temperature calculation unit102dmay calculate the temperature obtained by subtracting the difference ΔTFRfrom the current temperature Thof the heater HT2as the temperature of the heater HT2at which the temperature of the focus ring FR becomes the target temperature. The setting temperature calculation unit102dcorrects the setting temperature of the heater HT2set in the heater control unit102ato the temperature of the heater HT2that makes the temperature of the focus ring FR reach the target temperature. Therefore, the plasma processing apparatus10according to the present embodiment may accurately control the temperature of the focus ring FR during the plasma processing to the target temperature. The alarm unit102eissues an alarm based on a change in the thickness zFRof the focus ring FR calculated in a predetermined cycle by the parameter calculation unit102c. For example, the alarm unit102eissues the alarm when the thickness zFRof the focus ring FR is equal to or smaller than a predetermined threshold indicating the replacement time. The alarm may be in any manner as long as the replacement time can be notified to a process manager, an operator of the plasma processing apparatus10, or the like. For example, the alarm unit102edisplays a message notifying the replacement time on the user interface103. Accordingly, the plasma processing apparatus10according to the present embodiment may inform of the replacement time of the focus ring FR due to its consumption. (Flow of Processing) Next, a flow of a determination process that includes a calculation process in which the plasma processing apparatus10calculates the thickness of the focus ring FR, and determines the replacement time of the focus ring FR from the calculated thickness of the focus ring FR will be described.FIG.8is a flowchart showing an example of the flow of the determination process according to the first embodiment. This determination process is performed at a predetermined timing, e.g., at a timing when the plasma processing apparatus10starts the plasma processing. The heater control unit102acontrols a supply power to each heater HT such that each heater HT reaches a setting temperature (step S10). While the heater control unit102acontrols the supply power to each heater HT such that the temperature of each heater HT becomes a constant setting temperature, the measurement unit102bmeasures the supply power to the heater HT2in the non-ignition and the supply power to the heater HT2in the transient state (step S11). The parameter calculation unit102cdetermines whether the thickness of the focus ring FR is known or not (step S12). For example, when the plasma processing is the initial plasma processing after the focus ring FR is replaced, if the focus ring FR is new, it is determined that the design dimensions are known and the thickness of the focus ring is also known. Further, when the replaced focus ring FR is the used focus ring FR, if the thickness of the focus ring FR is measured in advance with, e.g., a micrometer before the replacement, it is determined that the thickness of the focus ring FR is known. It is also preferred that whether or not the thickness of the focus ring FR is known may be input from the user interface103, and the parameter calculation unit102cdetermines whether or not the thickness of the focus ring FR is known using the input result. For example, the plasma processing apparatus10is configured such that the thickness of the focus ring FR may be input from the user interface103. When the thickness of the focus ring FR is input from the user interface103, the parameter calculation unit102cmay determine whether or not the thickness of the focus ring FR is known. Alternatively, the thickness value of the focus ring FR such as a new focus ring FR whose thickness is known may be stored in the storage unit104, and then the thickness of the focus ring FR may be selectively input from the user interface103. When the thickness of the focus ring FR is known (YES in step S12), the parameter calculation unit102ccalculates a heat input amount and a thermal resistance by using the supply power in the non-ignition state and the supply power in the transient state measured by the measurement unit102b(step S13). For example, the parameter calculation unit102cperforms the fitting of the heat generation amount qhand the heat generation amount qh0for each elapsed time t by using the equations (1) to (11) as the calculation model, and calculates the heat flux qpand the thermal resistance Rth·A having the lowest degree of error. The known thickness value of the focus ring FR is used as the thickness zFRof the focus ring FR. The parameter calculation unit102cstores the calculated heat flux qpand the calculated thermal resistance Rth·A in the storage unit104(step S14), and the process is terminated. When the thickness of the focus ring FR is unknown (NO in step S12), the parameter calculation unit102ccalculates the thickness zFRof the focus ring FR by using the supply power in the non-ignition state and the supply power in the transient state measured by the measurement unit102b(step S15). For example, the parameter calculation unit102cperforms the fitting of the thickness zFRof the focus ring FR by using the equations (1) to (11) as the calculation model, and calculates the thickness zFRof the focus ring FR having the lowest degree of error. As for the heat flux qpand the thermal resistance Rth·A, the values stored in the storage unit104in step S14are used, for example. The alarm unit102edetermines whether the thickness zFRof the focus ring FR calculated by the parameter calculation unit102cis equal to or smaller than the predetermined threshold (step S16). If it is determined that the thickness zFRof the focus ring FR is not equal to or smaller than the predetermined threshold (NO in step S16), the process is terminated. On the other hand, if it is determined that the thickness zFRof the focus ring FR is equal to or smaller than the predetermined threshold (YES in step S16), the alarm unit102eissues an alarm (step S17) and the process is terminated. As described above, the plasma processing apparatus10according to the present embodiment includes the mounting table16, the heater control unit102a, the measurement unit102b, and the parameter calculation unit102c. The mounting table16includes the heater HT2configured to adjust the temperature of the mounting surface on which the focus ring FR that is consumed by the plasma processing is mounted. The heater control unit102acontrols the supply power supplied to the heater HT2such that the temperature of the heater HT2becomes a setting temperature. While the heater control unit102acontrols the supply power to the heater HT2such that the temperature of the heater HT2becomes constant, the measurement unit102bmeasures the supply power in the non-ignition state where the plasma is not ignited and the supply power in the transient state where the supply power to the heater HT2is decreased after the plasma is ignited. The parameter calculation unit102ccalculates the thickness zFRof the focus ring FR by performing the fitting of the thickness zFRof the focus ring FR with the calculation model, which has the thickness zFRof the focus ring FR as a parameter and calculates the supply power in the transient state, by using the supply power in the non-ignition state and the supply power in the transient state measured by the measurement unit102b. As a result, the plasma processing apparatus10determines the thickness of the focus ring FR and further determine the degree of consumption of the focus ring FR from the thickness of the focus ring FR. Moreover, the measurement unit102bmeasures the supply power in the non-ignition state and the supply power in the transient state in a predetermined cycle. The parameter calculation unit102ccalculates the thickness zFRof the focus ring FR by using the supply power in the non-ignition state and the supply power in transient supply power measured in each predetermined cycle. The alarm unit102eissues the alarm based on the change in the thickness zFRof the focus ring FR calculated by the parameter calculation unit102c. Accordingly, the plasma processing apparatus10can notify the replacement time due to the consumption of the focus ring FR. Second Embodiment Next, a schematic configuration of the plasma processing apparatus10according to a second embodiment will be described.FIG.9is a cross-sectional view showing an example of a schematic configuration of a plasma processing apparatus according to the second embodiment. A configuration of the plasma processing apparatus10according to the second embodiment is basically the same as that of the plasma processing apparatus10according to the first embodiment shown inFIG.1. Therefore, the difference therebetween is mainly described hereinafter, and like reference numerals will be given to like parts and redundant description thereof will be omitted. The mounting table16according to the second embodiment is divided into a first mounting table60that supports the wafer W and a second mounting table70that supports the focus ring FR. The first mounting table60has a substantially cylindrical shape with upper and lower surfaces directed vertically. An upper surface of the first mounting table60serves as a mounting surface60don which the wafer W is mounted. The mounting surface60dof the first mounting table60has substantially the same size as the wafer W. The first mounting table60includes an electrostatic chuck61and a base62. The base62is made of a conductive metal, e.g., aluminum having an anodically oxidized surface or the like. The base62serves as a lower electrode. The base62is supported by the supporting member14made of an insulator. The electrostatic chuck61has a flat disc-shaped upper surface serving as the mounting surface60don which the wafer W is mounted. The electrostatic chuck61is provided at a central portion of the first mounting table60when seen from the top. The electrostatic chuck61includes an electrode μl. The electrostatic chuck61further includes the heater HT1. A second mounting table70is provided to surround an outer peripheral surface of the first mounting table60. The second mounting table70is formed in a cylindrical shape whose inner diameter is greater than an outer diameter of the first mounting table60by a predetermined value. The first mounting table60and the second mounting table70are coaxially arranged. The second mounting table70has an upper surface serving as a mounting surface70don which the focus ring FR is mounted. The second mounting table70includes a base71and a focus ring heater unit72. The base71is made of a conductive metal similar to that of the base62. The base71is made of, e.g., aluminum having an anodically oxidized surface or the like. A lower portion of the base62is greater in a diametrical direction than an upper portion of the base62and extends in a flat plate shape up to a position of the lower part of the second mounting table70. The base71is supported by the base62. The focus ring heater unit72is supported by the base71. The focus ring heater unit72has an annular shape with a flat upper surface serving as a mounting surface70don which the focus ring FR is mounted. The focus ring heater unit72includes the heater HT2. A coolant channel24ais formed in the base62. The coolant is supplied to the coolant channel24afrom the chiller unit through the line26a. The coolant supplied to the coolant channel24areturns to the chiller unit through a line26b. Further, a coolant channel24bis formed in the base71. The coolant is supplied to the coolant channel24bfrom the chiller unit through a line27a. The coolant supplied to the coolant channel24breturns to the chiller unit through a line27b. The coolant channel24ais positioned below the wafer W and absorbs heat of the wafer W. The coolant channel24bis positioned below the focus ring FR and absorbs heat of the focus ring FR. Further, the upper electrode30is provided above the first mounting table60to face the first mounting table60in parallel therewith. The upper electrode30has a plurality of electromagnets80arranged on an upper surface of the upper electrode30. In the present embodiment, three electromagnets80ato80care arranged on the upper surface of the upper electrode30. The electromagnet80ahas a disc shape and is arranged on the upper surface of the upper electrode30that corresponds to the central portion of the first mounting table60. The electromagnet80bhas an annular shape to surround the electromagnet80aand is arranged on the upper surface of the upper electrode30that corresponds to an outer peripheral portion of the first mounting table60. The electromagnet80chas an annular shape has a size greater than the electromagnet80bto surround the electromagnet80band is arranged on the upper surface of the upper electrode30that corresponds to the second mounting table70. The electromagnets80ato80care individually connected to a power supply (not shown) and individually generate magnetic fields by powers supplied from the power supply. The power supplied from the power supply to each of the electromagnets80ato80cis controlled by the control unit100. The control unit100controls the power supply to control the power supplied to each of the electromagnets80ato80c, and thus the magnetic field generated from each of the electromagnets80ato80ccan be controlled. (Configuration of Control Unit) Next, the control unit100will be described in detail.FIG.10is a block diagram showing an example of a schematic configuration of the control unit that controls the plasma processing apparatus according to the second embodiment. A configuration of the control unit100according to the second embodiment is basically the same as that of the control unit100according to the first embodiment shown inFIG.3. Therefore, the difference therebetween is mainly described hereinafter, and like reference numerals will be given to like parts and redundant description thereof will be omitted. The storage unit104stores therein correction information104a. Further, the correction information104amay be stored in a computer-readable storage medium (e.g., a hard disk, an optical disk such as a DVD, a flexible disk, a semiconductor memory, or the like). Alternatively, the correction information104amay be stored in another device and may be read and used online through, e.g., a dedicated line. The correction information104ais data in which various types of information used for correcting the plasma processing conditions are stored. Details of the correction information104awill be described later. The process controller102further has a function of a plasma control unit102f. In the plasma processing apparatus10, the plasma is generated in the processing chamber12when the etching is performed. However, a height of a plasma sheath is changed due to the consumption of the focus ring FR, and thus the etching characteristics are changed. FIG.11schematically shows an example of a state of the plasma sheath.FIG.11shows the wafer W and the focus ring FR placed on the mounting table. The mounting table shown inFIG.11is a combination of the first mounting table60and the second mounting table70. Dwaferis a thickness of the wafer W. dwaferis a height from an upper surface of the wafer W to a plasma sheath interface above the wafer W. A thickness Dais a difference in height between a mounting surface of the mounting table on which the wafer W is mounted and a mounting surface of the mounting table on which the focus ring FR is mounted. For example, in the second embodiment, the thickness Dais a height difference between the mounting surface60dof the first mounting table60and the mounting surface70dof the second mounting table70. The thickness Dais determined as a fixed value depending on the configuration of the first mounting table60and the second mounting table70. The thickness zFRis the thickness of the focus ring FR. A thickness dFRis a height from an upper surface of the focus ring FR to a plasma sheath interface above the focus ring FR. A height difference ΔDwafer-FRbetween the plasma sheath interface above the wafer W and the plasma sheath interface above the focus ring FR can be expressed by the following equation (15). ΔDwafer-FR−(Da+Dwafer+dwafer)−(zFR+dFR) (15) For example, when the thickness zFRof the focus ring FR becomes thinner due to the consumption of the focus ring FR, the height difference Dwafer-FRis changed. For this reason, in the plasma processing apparatus10, the etching characteristics are changed. However, in the plasma processing apparatus10, the plasma state is changed due to the magnetic forces from the electromagnets80ato80c.FIG.12Ais a graph showing an example of a relationship between magnetic field strength and plasma electron density. As shown inFIG.12A, there is a proportional relationship between the magnetic field strength of the magnetic force applied to the plasma and the plasma electron density. The plasma electron density and a thickness of the plasma sheath have a relationship of the following equation (16). Sheaththickness=23(ε0Tee·Ne)(2VdcTe)3/4(16) Here, Neis the plasma electron density. Teis a plasma electron temperature [eV]. Vdcis a potential difference with the plasma. Vdcis a potential difference between the plasma and the wafer W in the case of plasma above the wafer W and is a potential difference between the plasma and the focus ring FR in the case of plasma on the focus ring FR. As shown in the equation (16), the thickness of the plasma sheath is inversely proportional to the electron density Ne. Therefore, there is an inversely proportional relationship between the magnetic field strength of the magnetic force applied to the plasma and the plasma electron density.FIG.12Bis a graph showing an example of the relationship between the magnetic field strength and the thickness of the plasma sheath. As shown inFIG.12B, the thickness of the plasma sheath is inversely proportional to the magnetic field strength of the magnetic force applied to the plasma. Therefore, in the plasma processing apparatus10according to the second embodiment, the magnetic field strength of the magnetic force generated from each of the electromagnets80ato80cis controlled in order to suppress the change in the etching characteristics due to the consumption of the focus ring FR. Referring back toFIG.10, the correction information104aaccording to the second embodiment stores a correction value for the power supplied to each of the electromagnets80ato80cfor each thickness of the focus ring FR. For example, the amount of power of each of the electromagnets80ato80c, at which the magnetic field strength that allows the height difference ΔDwafer-FRbetween the plasma sheath interface above the wafer W and the plasma sheath interface above the focus ring FR to be within a predetermined range can be obtained, is experimentally measured. For example, when AC power is supplied from the power supply to the electromagnet80, one of AC voltage, AC frequency and AC power is changed and the changed AC voltage, the changed AC frequency or the changed AC power is measured as the amount of power. When DC power is supplied from the power supply to the electromagnet80, either DC voltage or DC current amount is changed and the changed DC voltage or the changed DC current amount is measured as the amount of power. The predetermined range is, e.g., a range of ΔDwafer-FRin which a hole angle θ, when the wafer W is etched, is within an allowable accuracy. Based on the measurement result, for each thickness of the focus ring FR, the correction value of the power supplied to each of the electromagnets80ato80cthat allows the height difference ΔDwafer-FRto be within the predetermined range is stored in the correction information104a. The correction value may be a value of the amount of power itself at which the difference ΔDwafer-FRis within the predetermined range, or may be a difference value with respect to the standard amount of power that is supplied to each of the electromagnets80ato80cduring the plasma processing. In the present embodiment, the correction value is the value of the amount of power supplied to each of the electromagnets80ato80citself. Here, in the case where the plasma processing apparatus according to the second embodiment corrects the power supplied to the electromagnet80cto correct the height of the interface of the plasma sheath formed above the focus ring FR will be described. The correction information104aincludes the correction value of the supply power to the electromagnet80cfor each thickness of the focus ring FR. Alternatively, the plasma processing apparatus10may correct the power supplied to each of the electromagnets80aand80bto correct the height of the interface of the plasma sheath formed above the wafer W. In this case, the correction information104aincludes a correction value for the supply power to each of the electromagnets80aand80bfor each thickness of the focus ring FR. Further alternatively, the plasma processing apparatus10may correct the power supplied to each of the electromagnets80ato80cto correct the height of the interface of the plasma sheath formed above the focus ring FR and the height of the interface of the plasma sheath formed above the wafer W. In this case, the correction information104aincludes a correction value for the supply power to each of the electromagnets80ato80cfor each thickness of the focus ring FR. The plasma control unit102fcontrols the plasma processing such that the height difference ΔDwafer-FRbetween the plasma sheath interface above the wafer W and the plasma sheath interface above the focus ring FR is within the predetermined range. The plasma control unit102fcontrols the magnetic force of each of the electromagnets80ato80cbased on the thickness zFRof the focus ring FR calculated by the parameter calculation unit102c. For example, the plasma control unit102freads, from the correction information104a, the correction value of the power supplied to each of the electromagnets80ato80ccorresponding to the thickness zFRof the focus ring FR. Then, the plasma control unit102fcontrols the power supply connected to the electromagnets80ato80cso that the supply powers corresponding to the read correction values are supplied to the electromagnets80ato80c, respectively, during the plasma processing. In the present embodiment, the plasma control unit102fcontrols the power supply connected to the electromagnet80cso that the supply power corresponding to the correction value is supplied to the electromagnet80c. As a result, in the plasma processing apparatus10, the height difference ΔDwafer-FRbetween the plasma sheath interface above the wafer W and the plasma sheath interface above the focus ring FR becomes within the predetermined range. Accordingly, in the plasma processing apparatus10, the change in the etching characteristics due to the consumption of the focus ring FR can be suppressed. Next, a plasma control process using the plasma processing apparatus10according to the second embodiment will be described.FIG.13is a flowchart showing an example of the flow of determination process according to the second embodiment. The determination process according to the second embodiment is basically the same as the determination process according to the first embodiment shown inFIG.8. Therefore, the difference therebetween is mainly described hereinafter, and like reference numerals will be given to like parts and redundant description thereof will be omitted. The plasma control unit102fcontrols the plasma processing based on the thickness zFRof the focus ring FR calculated by the parameter calculation unit102c(step S18). For example, the plasma control unit102fcontrols the magnetic forces of the electromagnets80ato80cto allow the height difference ΔDwafer-FRbetween the plasma sheath interface above the wafer W and the plasma sheath interface above the focus ring FR to be within a predetermined range based on the thickness zFRof the focus ring FR. As described above, the plasma processing apparatus10according to the second embodiment further includes the plasma control unit102f. Based on the thickness zFRof the focus ring FR, the plasma control unit102fcontrols the plasma processing to allow the height difference between the interface of the plasma sheath formed above the wafer W and the interface of the plasma sheath formed above the focus ring FR to be within the predetermined range. Accordingly, the plasma processing apparatus10can suppress the differences in the etching characteristics of the wafers W. The plasma processing apparatus10according to the second embodiment further includes at least one electromagnet80arranged in parallel with at least one of the wafer W or the focus ring FR. The plasma control unit102fcontrols the supply power to the electromagnet80based on the thickness zFRof the focus ring FR, so that the magnetic force of the electromagnet80is controlled to allow the height difference between the interface of the plasma sheath formed above the wafer W and the interface of the plasma sheath formed above the focus ring FR to be within the predetermined range. Therefore, the plasma processing apparatus10can suppress the differences in the etching characteristics of the wafers W. In the determination process according to the second embodiment shown inFIG.13, the case where step S18is executed after step S15has been described as an example. However, the present disclosure is not limited thereto. For example, step S18may be executed consecutively during the plasma processing on the wafer W used in step S15. Further, step S18may be executed during the plasma processing on and after the next wafer W after the plasma processing on the wafer W used in step S15is completed. When step S18is continuously executed during the plasma processing on the wafer W used in step S15, the plasma control unit102fcontrols the magnetic forces of the electromagnets80ato80cin the period T3shown inFIG.7. When step S18is executed during the plasma processing on and after the next wafer W after the plasma processing on the wafer W used in step S15is completed, the plasma control unit102fcontrols the magnetic forces of the electromagnets80ato80cfrom the time period of the plasma ignition. When the magnetic forces of the electromagnets80ato80care changed from the initial setting values, the electron density of the plasma increases or decreases as shown inFIG.12A, so that the heat input amount from the plasma to the focus ring FR also increases or decreases. In this case, it is desirable that the thickness zFRof the focus ring FR calculated in step15is set as the known thickness of the focus ring FR, and the heat flux qpfrom the plasma and the thermal resistance Rth·A with the magnetic forces of the controlled electromagnets80ato80care calculated by executing steps S13and S14again. Then, the calculated heat flux qpand the calculated thermal resistance Rth·A are stored in the storage unit104as a new heat flux qpand a new thermal resistance Rth·A. Further, in the determination process according to the second embodiment shown inFIG.13, the case where step S18is executed between step S15and step S16has been described as an example. However, the present disclosure is not limited thereto. For example, step S18may be executed after “NO” in step16, that is, when it is determined that the thickness zFRof the focus ring FR is not equal to or smaller than the predetermined threshold. Therefore, it is possible to minimize the deterioration of reproducibility caused when the plasma processing on the wafer W is performed even when the thickness zFRof the focus ring FR is determined to be equal to or less than the predetermined threshold. Third Embodiment Next, a third embodiment will be described.FIG.14is a cross-sectional view showing an example of a schematic configuration of a plasma processing apparatus according to a third embodiment. A configuration of the plasma processing apparatus10according to the third embodiment is basically the same as that of the plasma processing apparatus10according to the second embodiment shown inFIG.9. Therefore, the difference therebetween is mainly described hereinafter, and like reference numerals will be given to like parts and redundant description thereof will be omitted. In the second mounting table70according to the third embodiment, an electrode is additionally provided at the mounting surface70don which the focus ring FR is mounted. For example, in the second mounting table70, an electrode73is additionally provided in the focus ring heater unit72to extend along the entire circumference of the focus ring heater unit72. The electrode73is electrically connected to a power supply74through wiring. The power supply74according to the third embodiment is a DC power supply and applies a DC voltage to the electrode73. The plasma state is changed due to the changes in the electrical characteristics of the surroundings of the plasma. For example, the state of the plasma above the focus ring FR changes depending on the magnitude of the DC voltage applied to the electrode73, which leads to the change in the thickness of the plasma sheath. Therefore, in the plasma processing apparatus10according to the third embodiment, the DC voltage applied to the electrode73is controlled to suppress the change in the etching characteristics due to the consumption of the focus ring FR. The correction information104aaccording to the third embodiment stores a correction value for the DC voltage applied to the electrode73for each thickness of the focus ring FR. For example, the DC voltage applied to the electrode73that allows the height difference ΔDwafer-FRbetween the plasma sheath interface above the wafer W and the plasma sheath interface above the focus ring FR to be within a predetermined range is experimentally measured. Based on the measurement results, for each thickness of the focus ring FR, the correction value of the DC voltage applied to the electrode73that allows the height difference ΔDwafer-FRto be within the predetermined range is stored in the correction information104a. The correction value may be a value of the DC voltage at which the difference ΔDwafer-FRis within the predetermined range, or may be a difference value with respect to the standard DC voltage applied to the electrode73during the plasma processing. In the present embodiment, the correction value is the value of the DC voltage applied to the electrode73itself. The plasma control unit102fcontrols the DC voltage applied to the electrode73based on the thickness zFRof the focus ring FR calculated by the parameter calculation unit102c. For example, the plasma control unit102freads, from the correction information104a, the correction value of the DC voltage applied to the electrode73corresponding to the thickness zFRof the focus ring FR. Then, the plasma control unit102fcontrols the power supply74so that the DC voltage corresponding to the read correction value is applied to the electrode73during the plasma processing. As a result, in the plasma processing apparatus10, the height difference ΔDwafer-FRbetween the plasma sheath interface above the wafer W and the plasma sheath interface above the focus ring FR becomes within the predetermined range. Accordingly, in the plasma processing apparatus10, the change in the etching characteristics due to the consumption of the focus ring FR can be suppressed. As described above, the plasma processing apparatus10according to the third embodiment further includes the electrode73that is provided at the mounting surface70don which the focus ring FR is mounted and to which a DC voltage is applied. Based on the thickness zFRof the focus ring FR, the plasma control unit102fcontrols the DC voltage applied to the electrode73to allow the height difference between the interface of the plasma sheath formed above the wafer W and the interface of the plasma sheath formed above the focus ring FR to be within the predetermined range. Accordingly, the plasma processing apparatus10can suppress the differences in the etching characteristics of the wafers W. Fourth Embodiment Next, a fourth embodiment will be described.FIG.15is a cross-sectional view showing an example of a schematic configuration of a plasma processing apparatus according to a fourth embodiment. A configuration of the plasma processing apparatus10according to the fourth embodiment is basically the same as that of the plasma processing apparatus10according to the second embodiment shown inFIG.9. Therefore, the difference therebetween is mainly described hereinafter, and like reference numerals will be given to like parts and redundant description thereof will be omitted. Each of the electrode plate34and the electrode support36of the upper electrode30according to the fourth embodiment is divided into a plurality of portions by an insulating member. For example, each of the electrode support36and the electrode plate34is divided into a central portion30aand a peripheral portion30bby an annular insulating member37. The central portion30ais formed in a disc shape and is arranged above the central portion of the first mounting table60. The peripheral portion30bis formed in an annular shape to surround the central portion30aand is arranged above the outer peripheral portion of the first mounting table60. In the upper electrode30according to the fourth embodiment, DC currents can be individually applied to the divided portions, and each of the divided portions serve as the upper electrode. For example, a variable DC power supply93ais electrically connected to the peripheral portion30bthrough a low-pass filter (LPF)90aand an on/off switch91a. A variable DC power supply93bis electrically connected to the central portion30athrough a low-pass filter (LPF)90band an on/off switch91b. The power respectively applied by the variable DC power supplies93aand93bto the central portion30aand the peripheral portion30bcan be controlled by the control unit100. The central portion30aand the peripheral portion30bserve as electrodes. The plasma state is changed due to the changes in the electrical characteristics of the surroundings of the plasma. For example, in the plasma processing apparatus10, the plasma state changes depending on the magnitudes of the voltages applied to the central portion30aand the peripheral portion30b, respectively. Therefore, in the plasma processing apparatus10according to the fourth embodiment, the voltages applied to the central portion30aand the peripheral portion30bare controlled to suppress the changes in the etching characteristics due to consumption of the focus ring FR. The correction information104aaccording to the fourth embodiment stores a correction value of the DC voltage applied to each of the central portion30aand the peripheral portion30bfor each thickness of the focus ring FR. For example, the DC voltages respectively applied to the central portion30aand the peripheral portion30bthat allow the height difference ΔDwafer-FRbetween the plasma sheath interface above the wafer W and the plasma sheath interface above the focus ring FR to be within a predetermined range is experimentally measured. Based on the measurement result, for each thickness of the focus ring FR, the correction values of the DC voltages respectively applied to the central portion30aand the peripheral portion30bthat allow the difference ΔDwafer-FRto be within the predetermined range is stored in the correction information104a. The correction values may be values of the DC voltages applied to the central portion30aand the peripheral portion30bthemselves, or a difference value with respect to the standard DC voltage applied to each of the central portion30aand the peripheral portion30bduring the plasma processing. In the present embodiment, the correction value is the value of the DC voltage applied to each of the central portion30aand the peripheral portion30b. Here, the case where the plasma processing apparatus10according to the fourth embodiment corrects the height of the interface of the plasma sheath formed above the focus ring FR by correcting the DC voltage applied to the peripheral portion30bis described. In the correction information104a, the correction value for the DC voltage applied to the peripheral portion30bis stored for each thickness of the focus ring FR. The plasma processing apparatus10may further divide the upper electrode30into multiple annular shaped portions and correct the DC voltage applied to each of the multiple annular shaped portions to correct the height of the interface of the plasma sheath formed above the wafer W. The plasma control unit102fcontrols the DC voltage applied to the peripheral portion30bbased on the thickness zFRof the focus ring FR calculated by the parameter calculation unit102c. For example, the plasma control unit102freads, from the correction information104a, the correction value of the DC voltage applied to the peripheral portion30bcorresponding to the thickness zFRof the focus ring FR. Then, the plasma control unit102fcontrols the variable DC power supply93aso that the DC voltage having the read correction value is supplied to the peripheral portion30bduring the plasma processing. As a result, in the plasma processing apparatus10, the height difference ΔDwafer-FRbetween the plasma sheath interface above the wafer W and the plasma sheath interface above the focus ring FR becomes within the predetermined range. Accordingly, in the plasma processing apparatus10, the changes in the etching characteristics due to the consumption of the focus ring FR can be suppressed. As described above, the upper electrode (gas supply unit)30according to the fourth embodiment is disposed to face the wafer W and the focus ring FR to inject processing gas and has the central portion30aand the peripheral portion30bthat serve as electrodes disposed in parallel with the wafer W and the focus ring FR. The plasma control unit102fcontrols the supply powers to the central portion30aand the peripheral portion30bbased on the thickness zFRof the focus ring FR to allow the height difference between the interface of the plasma sheath formed above the wafer W and the interface of the plasma sheath formed above the focus ring FR to be within the predetermined range. Accordingly, the plasma processing apparatus10can suppress the differences in the etching characteristics of the wafers W. Fifth Embodiment Next, a fifth embodiment will be described.FIG.16is a cross-sectional view showing an example of a schematic configuration of a plasma processing apparatus according to a fifth embodiment. A configuration of the plasma processing apparatus10according to the fifth embodiment is basically the same as that of the plasma processing apparatus10according to the second embodiment shown inFIG.9. Therefore, the difference therebetween is mainly described hereinafter, and like reference numerals will be given to like parts and redundant description thereof will be omitted. In the plasma processing apparatus10according to the fifth embodiment, the electromagnet80is not provided on the upper surface of the upper electrode30, and the second mounting table70can be moved up and down. (Configurations of First Mounting Table and Second Mounting Table) Configurations of principal parts of the first mounting table2and the second mounting table7according to the fifth embodiment will be described with reference toFIG.17.FIG.17is a schematic cross-sectional view showing the configurations of the principal parts of the first mounting table and the second mounting table according to the fifth embodiment. The first mounting table60includes the base62and the electrostatic chuck61. The electrostatic chuck61is adhered to the base62through an insulating layer64. The electrostatic chuck61is formed in a disc shape and provided coaxially with respect to the base62. In the electrostatic chuck61, the electrode μl is provided in an insulator. The upper surface of the electrostatic chuck61serves as the mounting surface60don which the wafer W is mounted. A flange portion61aprojecting outwardly in a radial direction of the electrostatic chuck61is formed at a lower end of the electrostatic chuck61. In other words, the electrostatic chuck61has different outer diameters depending on positions of the side surface. The electrostatic chuck61includes the heater HT1. The coolant channel24ais formed in the base62. The coolant channel24aand the heater HT1function as a temperature control mechanism for controlling the temperature of the wafer W. The heater HT1may not be provided in the electrostatic chuck61. For example, the heater HT1may be adhered to the lower surface of the electrostatic chuck61or may be interposed between the mounting surface60dand the coolant channel24a. The second mounting table70includes the base71and the focus ring heater unit72. The base71is supported by the base62. The focus ring heater unit72includes the heater HT2. A coolant channel24bis formed in the base71. The coolant channel24band the heater HT2function as a temperature control mechanism for controlling the temperature of the focus ring FR. The focus ring heater unit72is adhered to the base71through an insulating layer76. An upper surface of the focus ring heater unit72serves as the mounting surface70don which the focus ring FR is mounted. A sheet member having high thermal conductivity or the like may be provided on the upper surface of the focus ring heater unit72. The focus ring FR that is an annular member is coaxially provided with respect to the second mounting table70. A protruding portion FRa is protruded in a radial direction from an inner side surface of the focus ring FR. In other words, the focus ring FR has different the inner diameters depending on positions of the inner side surface thereof. For example, an inner diameter of a portion of the focus ring FR where the protruding portion FRa is not formed is greater than an outer diameter of the wafer W and an outer diameter of the flange portion61aof the electrostatic chuck61. On the other hand, an inner diameter of a portion of the focus ring FR where the protruding portion FRa is formed is smaller than the outer diameter of the flange portion61aof the electrostatic chuck61and greater than an outer diameter of a portion of the electrostatic chuck61where the flange portion61ais not formed. The focus ring FR is disposed on the second mounting table70in a state where the protruding portion FRa is separated from an upper surface of the flange portion61aof the electrostatic chuck61and also separated from a side surface of the electrostatic chuck61. In other words, a gap is formed between a lower surface of the protruding portion FRa of the focus ring FR and the upper surface of the flange portion61aof the electrostatic chuck61. Further, a gap is formed between a side surface of the protruding portion FRa of the focus ring FR and a side surface of the electrostatic chuck61where the flange portion61ais not formed. The protruding portion FRa of the focus ring FR is located above a gap110between the base62of the first mounting table60and the base71of the second mounting table70. In other words, when viewed from a direction perpendicular to the mounting surface60d, the protruding portion FRa overlaps with the gap110and covers the gap110. Accordingly, it is possible to suppress inflow of the plasma into the gap110. An elevating mechanism120for vertically moving the second mounting table70is provided at the first mounting table60. For example, the elevating mechanism120is provided at the first mounting table60to be positioned below the second mounting table70. The elevating mechanism120has therein an actuator and vertically moves the second mounting table70by extending and contracting a rod120aby using driving force of the actuator. The elevating mechanism120may obtain driving force for expanding and contracting the rod120aby converting the driving force of the motor by a gear or the like, or may obtain driving force for expanding and contracting the rod120aby a hydraulic pressure or the like. Between the first mounting table60and the second mounting table70, an O-ring112for interrupting vacuum is provided. The second mounting table70is configured not to be affected even if it is raised. For example, the cooling channel24bis configured as a flexible line or a mechanism capable of supplying a coolant even if the second mounting table70is vertically moved. The wiring for supplying power to the heater HT2may be configured as a flexible wiring or a mechanism that is electrically connected even if the second mounting table70is vertically moved. Further, the first mounting table60is provided with a conducting part130that is electrically connected to the second mounting table70. The conducting part130is configured to electrically connect the first mounting table60and the second mounting table70even if the second mounting table70is vertically moved by the elevating mechanism120. For example, the conducting part130is configured as a flexible wiring or a mechanism that is electrically connected by contact between a conductor and the base71even if the second mounting table70is vertically moved. The conducting part130is provided so that the second mounting table70and the first mounting table60have equal electrical characteristics. For example, a plurality of conducting parts130are provided on a circumferential surface of the first mounting table60. The RF power supplied to the first mounting table60is also supplied to the second mounting table70through the conducting part130. Alternatively, the conducting part130may be provided between the upper surface of the first mounting table60and the lower surface of the second mounting table70. The elevating mechanism120is arranged at multiple positions in a circumferential direction of the focus ring FR. In the plasma processing apparatus10according to the present embodiment, three elevating mechanisms120are provided. For example, the elevating mechanisms120are arranged on the side of the second mounting table70at a regular interval in a circumferential direction of the second mounting table70. For example, the elevating mechanisms120are disposed at positions on the side of the second mounting table70at an interval of 120° in the circumferential direction of the second mounting table70. Four or more elevating mechanisms120may be provided on the side of the second mounting table70. In the plasma processing apparatus10, when the plasma processing is performed, the focus ring FR is consumed and the thickness zFRof the focus ring FR is reduced. When the thickness zFRof the focus ring FR becomes thin, a height different occurs between the plasma sheath above the focus ring FR and the plasma sheath above the wafer W, and thus the etching characteristics are changed. Therefore, in the plasma processing apparatus10according to the fifth embodiment, the elevating mechanism120is controlled in response to the thickness zFRof the focus ring FR. The plasma control unit102fcontrols the elevating mechanism120based on the thickness zFRof the focus ring FR calculated by the parameter calculation unit102c. For example, the plasma control unit102fsubtracts the thickness zFRof the current focus ring FR from the thickness of a new focus ring FR to obtain the consumed thickness. The plasma control unit102fcontrols the elevating mechanism120to be moved up by the consumed thickness. FIGS.18A to18Cshow an example of a sequence of raising the second mounting table.FIG.18Ashows a state where a new focus ring FR is mounted on the second mounting table70. The height of the second mounting table70is adjusted so that the upper surface of the focus ring FR is located at a predetermined height when the new focus ring FR is mounted. For example, when the new focus ring FR is mounted on the second mounting table70, the height of the second mounting table70is adjusted so that the etching uniformity of the wafer W is obtained. As the wafer W is etched, the focus ring FR is also consumed.FIG.18Bshows a state where the focus ring FR is consumed. In the example shown inFIG.18B, the upper surface of the focus ring FR is consumed by 0.2 mm. In the plasma processing apparatus10, the thickness zFRof the focus ring FR is calculated by the parameter calculation unit102c, and the consumption amount of the focus ring FR is determined. Then, the plasma processing apparatus10controls elevating mechanism120to raise the second mounting base70in response to the consumption amount.FIG.18Cshows a state where the second mounting table70is raised. In the example shown inFIG.18C, the upper surface of the focus ring FR is raised by 0.2 mm by raising the second mounting table70. As a result, in the plasma processing apparatus10, the height difference ΔDwafer-FRbetween the plasma sheath interface above the wafer W and the plasma sheath interface above the focus ring FR falls within a predetermined range. Accordingly, in the plasma processing apparatus10, the change in the etching characteristics due to the consumption of the focus ring FR can be suppressed. As described above, the plasma processing apparatus10according to the fifth embodiment includes the elevating mechanism120configured to vertically move the focus ring FR. The plasma control unit102fcontrols the elevating mechanism120based on the thickness zFRof the focus ring FR 1 to allow the height difference between the interface of the plasma sheath formed above the wafer W and the interface of the plasma sheath formed above the focus ring FR to be within the predetermined range. Therefore, the plasma processing apparatus10can suppress the differences in the etching characteristics of the wafers W. While certain embodiments have been described, these embodiments have been presented by way of example only, and are not intended to limit the scope of the disclosures. Indeed, the embodiments described herein may be embodied in a variety of other forms. Furthermore, various omissions, substitutions and changes in the form of the embodiments described herein may be made departing from the scope of the accompanying claims and the spirit of the disclosures. The accompanying claims and their equivalents are intended to cover such forms or modifications as would fall within the scope and spirit of the disclosures. For example, the above-described plasma processing apparatus10is a capacitively coupled plasma processing apparatus10. However, it is possible to employ any plasma processing apparatus10. For example, the plasma processing apparatus10may be any type of plasma processing apparatus such as an inductively coupled plasma processing apparatus10or a plasma processing apparatus10for exciting a gas by a surface wave such as microwave. In the above-described embodiments, the case where the consumable part consumed by the plasma processing is the focus ring FR has been described as an example. However, the present disclosure is not limited thereto. Any consumable part may be used. For example, the wafer W is consumed by the plasma processing. Therefore, the wafer W may serve as the consumable part, and the plasma processing apparatus10may calculate the thickness of the wafer W. The aforementioned equations (1) to (13) may be applied to the calculation of the thickness of the wafer W by replacing the parameters regarding the focus ring FR such as the density, the heat capacity, and the thickness of the focus ring FR with the parameters regarding the wafer W. The mounting table16includes the heater HT1configured to adjust the temperature of the mounting surface on which the wafer W is mounted. The heater control unit102acontrols a supply power supplied to the heater HT1such that the heater HT1reaches a setting temperature. While the heater control unit102acontrols the supply power to the heater HT1such that the temperature of the heater HT1becomes constant, the measurement unit102bmeasures the supply power in the non-ignition state and the supply power in the transient state. The parameter calculation unit102ccalculates the thickness of the wafer W by performing fitting of the measurement results by using the equations (1) to (11) as a calculation model. Accordingly, the plasma processing apparatus10can obtain the thickness of the wafer W. In the above-described embodiments, as shown inFIG.2, the case where the mounting region18aof the electrostatic chuck18is divided into two division regions75in the radial direction has been described as an example. However, the present disclosure is not limited thereto. For example, the mounting region18amay be divided in the circumferential direction. For example, the division region75bon which the focus ring FR is disposed may be divided in the circumferential direction. FIG.19is a plan view showing a mounting table according to another embodiment. InFIG.19, the division region75bis divided into eight division regions75b1to75b8in the circumferential direction. The focusing ring FR is disposed on the division regions75b1to75b8. The heater HT2is provided in each of the division regions75b1to75b8. The heater control unit102acontrols the supply power to each heater HT2so that the heater HT2provided in each of the division regions75b1to75b8reaches a setting temperature set for each division region. While the heater control unit102acontrols the supply power to each heater HT2such that the temperature of the heater HT2becomes constant, the measurement unit102bmeasures the supply power in the non-ignition state and the supply power in the transient state for each heater HT2. For each heater HT2, the parameter calculation unit102ccalculates the thickness zFRof the focus ring FR by performing fitting with the calculation model by using the supply power in the non-ignition state and the supply power in the transient state measured by the measurement unit102b. Accordingly, the plasma processing apparatus10can obtain the thickness zFRof the focus ring FR for each of the division regions75b1to75b8. In the above-described embodiments, the case where the plasma state is changed by performing one of the change of the magnetic force of the electromagnet80, the change of the power supplied to the electrode73, the change of the powers supplied to the central portion30aand the peripheral portion30b, and the raising and lowering of the focus ring FR has been described as an example. However, the present disclosure is not limited thereto. The plasma state may be changed by changing an impedance. For example, the impedance of the second mounting table70may be changed. The plasma control unit102fcontrols the impedance of the second mounting table70based on the thickness zFRof the focus ring such that the height difference ΔDwafer-FRbetween the plasma sheath interface above the wafer W and the plasma sheath interface above the focus ring FR falls within a predetermined range. For example, a ring-shaped space is formed in the vertical direction inside the second mounting table70, and a ring-shaped conductor is provided in the space so as to be moved up and down by a conductor driving mechanism. The conductor is made of a conductive material such as aluminum. Therefore, the impedance of the second mounting table70can be changed by vertically moving the conductor by the conductor driving mechanism. Further, the second mounting table70may have any configuration as long as the impedance can be changed. The correction information104astores an impedance correction value for each thickness of the focus ring FR. For example, a height of the conductor that allows the height difference ΔDwafer-FRbetween the plasma sheath interface above the wafer W and the plasma sheath interface above the focus ring FR to be within a predetermined range is experimentally measured. In the correction information104a, for each thickness of the wafer W, a correction value of the height of the conductor that allows the height difference ΔDwafer-FRto be within the predetermined range is stored based on the measurement result. The plasma control unit102freads, from the correction information104a, a correction value for the height of the conductor that corresponds to the thickness zFRof the focus ring FR calculated by the parameter calculation unit102c. Then, the plasma control unit102fcontrols the conductor driving mechanism so that the height of the conductor becomes a height corresponding to the read correction value at the time of the plasma processing. Thus, in the plasma processing apparatus10, the height difference ΔDwafer-FRbetween the plasma sheath interface above the wafer W and the plasma sheath interface above the focus ring FR is within a predetermined range, and the differences in the etching characteristics of the wafers W can be suppressed. In the fourth embodiment described above, the case where the DC voltage is applied from the power supply74to the electrode73has been described as an example. However, the present disclosure is not limited thereto. For example, the power supply74may be an AC power supply. The plasma control unit102fmay control one of the frequency, the voltage, and the power of AC power supplied from the power supply74to the electrode73based on the thickness zFRof the focus ring FR such that the height difference ΔDwafer-FRbetween the plasma sheath interface above the wafer W and the plasma sheath interface above the focus ring FR falls within a predetermined range. Moreover, the above-described embodiments may be combined to be implemented. For example, the second embodiment and the third embodiment may be combined to control the magnetic force of the electromagnet80and the DC voltage applied to the electrode73such that the height difference between the plasma sheath interface above the wafer W and the plasma sheath interface above the focus ring FR falls within a predetermined range. In the sixth embodiment described above, the case where the elevating mechanism120is used to raise and lower the focus ring FR by vertically moving the second mounting table70has been described as an example. However, the present disclosure is not limited thereto. For example, a pin or the like is vertically moved and extend through the second mounting table70to raise and lower the focus ring FR only. In each of the above-described embodiments, the problem caused by the consumption of the focus ring has been described as an example. However, the present disclosure is not limited thereto. Since the same problem occurs in all consumable parts consumed by the plasma processing, for example, if a temperature of a protective cover made of an insulator disposed to surround the outer peripheral portion of the focus ring is also adjusted with a heater and the like, the degree of consumption can be obtained in the same manner described above. Further, the thickness of the wafer W mounted on the mounting table can be calculated by in the same manner described above. | 126,507 |
11862439 | DETAILED DESCRIPTION In a semiconductor device manufacturing process, substrate treatment such as film formation, etching, or the like is performed on a substrate such as a semiconductor wafer (hereinafter, referred to as “wafer”) or the like. In this substrate treatment, an electrostatic chuck may be used to fix the substrate on a mounting table. The electrostatic chuck attracts and holds a target object using an electrostatic attractive force such as Coulomb force, Johnson-Rahbek force, or the like. The substrate fixed on the electrostatic chuck is removed from the electrostatic chuck after the substrate treatment. The removal (dechucking) is performed by raising support pins that are movable to penetrate through the electrostatic chuck and lifting the substrate therefrom. The electrostatic chuck is an insulating member having therein an electrode plate, and an attraction holding surface thereof is made of a dielectric material. Therefore, residual charges are generated on the attraction holding surface of the electrostatic chuck due to charging caused by friction with the substrate or the like. The residual charges thus generated may cause a problem. For example, if a large amount of residual charges is accumulated, the substrate may be damaged during the above-described dechucking of the substrate. In addition, for example, if a large amount of residual charges is accumulated, the position of the substrate with respect to the support pins is shifted during the dechucking. Accordingly, the substrate may be transferred from the support pins to an undesirable position in a transfer unit. The above-described problem can be solved by performing charge neutralization on the electrostatic chuck for each substrate, for example. However, if the charge neutralization is performed for each substrate, the throughput deteriorates. In addition, as in the case described in Japanese Patent Application Publication No. 2014-137905, it is considered to provide a surface potential sensor for measuring the potential of the attraction surface of the electrostatic chuck and to perform charge neutralization when the charge amount of the electrostatic chuck is greater than a certain value. However, the charged particle beam device disclosed in Japanese Patent Application Publication No. 2014-137905 is not a substrate processing apparatus for performing substrate treatment such as film formation or the like. In the substrate processing apparatus, in the case of measuring the potential of the attraction surface of the electrostatic chuck using the surface potential sensor, it is necessary to provide the surface potential sensor at a position facing the electrostatic chuck. When the surface potential sensor is disposed at the position facing the electrostatic chuck, the substrate treatment is hindered. Therefore, the present disclosure prevents a problem that occurs when the substrate is attracted and held on the mounting table of the substrate processing apparatus by an electrostatic force or when the substrate is removed from the mounting table without hindering the substrate treatment and deteriorating the throughput. Hereinafter, a substrate processing apparatus and a charge neutralization method for a mounting table of the present embodiment will be described with reference to the drawings. Like reference numerals will be given to like parts having substantially the same function and structure throughout the specification and the drawings, and redundant description thereof will be omitted. FIGS.1and2are a vertical cross-sectional view and a horizontal cross-sectional view schematically showing a configuration of a film forming apparatus1as a substrate processing apparatus of the present embodiment, respectively.FIGS.3to6explain positions of a head40, a surface potential system50, a shield member60, and a charge neutralization mechanism80, which will be described later, in respective steps of a film forming process, respectively. The film forming apparatus1shown inFIGS.1and2performs, as substrate treatment, the film forming process by sputtering. Specifically, the film forming apparatus1forms an MgO film on a wafer W, for example. The film forming apparatus1includes a processing chamber10. The processing chamber10is depressurizable and accommodates a wafer W as a substrate. The processing chamber10is made of, e.g., aluminum, and is connected to a ground potential. A gas exhaust unit11for reducing a pressure in a space S in the processing chamber10is connected to a bottom portion of the processing chamber10through an APC valve12. In addition, a loading/unloading port13for the wafer W is formed on a sidewall of the processing chamber10. The loading/unloading port13is provided with a gate valve13afor opening and closing the loading/unloading port13. A mounting table14for horizontally mounting thereon the wafer W is disposed in the processing chamber10. The mounting table14has a base14aand an electrostatic chuck14b. The base14ahas a disc shape and is made of, e.g., aluminum. The base14ais provided with a heater (not shown) for heating the wafer W. A cooling mechanism may be provided instead of the heater, or both of the heater and the cooling mechanism may be provided. The electrostatic chuck14bhas a dielectric film and an electrode serving as an inner layer of the dielectric film. The electrostatic chuck14bis disposed on the base14a. A DC power supply (DC)15is connected to the electrode of the electrostatic chuck14b. The wafer W mounted on the electrostatic chuck14bis attracted and held on the electrostatic chuck14bby an electrostatic attractive force. Hereinafter, an upper surface14cof the electrostatic chuck14bserving as a substrate attraction surface will be referred to as “wafer attraction surface14c.” The mounting table14is connected to a driving mechanism16as a rotation driving unit. The driving mechanism16has, e.g., a supporting shaft16aand a driving unit16b. The supporting shaft16aextends vertically to penetrate through a bottom wall of the processing chamber10. A sealing member SL1is disposed between the supporting shaft16aand the bottom wall of the processing chamber10. The sealing member SL1seals a space between the bottom wall of the processing chamber10and the supporting shaft16aso that the supporting shaft16acan rotate and move vertically. The sealing member SL1is, e.g., a magnetic fluid seal. The upper end of the supporting shaft16ais connected to a center of a bottom surface of the mounting table14, and the lower end of the supporting shaft16ais connected to the driving unit16b. The driving unit16bgenerates a driving force for rotating and vertically moving the supporting shaft16a. The mounting table14rotates about an axis AX1as the supporting shaft16arotates about the axis AX1. The mounting table14moves vertically as the supporting shaft16amoves vertically. A target20made of Mg or a target21made of an activated metal such as Ti, Ta, or the like is disposed above the mounting table14. The targets20and21are held by metal holders20aand21a. The holders20aand21aare supported at a ceiling portion of the processing chamber10through insulating members20band21b, respectively. As will be described later, the target21is used to increase a vacuum level in the processing chamber10by a gettering action of the activated metal coated on an inner wall surface of the processing chamber10. Power supplies22aand22bare connected to the targets20and21through the holders20aand21a, respectively. The power supplies22aand22bare, e.g., DC power supplies. In addition, cathode magnets23aand23bare disposed outside the processing chamber10to face the targets20and21through the holders20aand21a, respectively. Magnet driving units (MD)24aand24bare connected to the cathode magnets23aand23b, respectively. The film forming apparatus1further includes a gas supply unit30for supplying a gas into the processing chamber10. The gas supply unit30includes, e.g., a gas source (GS)30a, a flow rate controller (FRC)30bsuch as a mass flow controller or the like, and a gas inlet30c. The gas source30astores a gas (e.g., Ar gas) that is excited in the processing chamber10. The gas source30ais connected to the gas inlet30cthrough the flow rate controller30b. The gas inlet30cintroduces a gas from the gas source30ainto the processing chamber10. When a gas is supplied from the gas supply unit30and a power is supplied from the power supply22aor22bto the corresponding target20or21, the gas supplied into the processing chamber10is excited. When the corresponding cathode magnet23aor23bis driven by the magnet driving unit24aor24b, a magnetic field is generated around the target20or21. Accordingly, plasma is concentrated near the target20or21. Then, positive ions in the plasma collide with the target20or21, so that a substance forming the target20or21is released from the corresponding target20or21. As a result, Mg is deposited on the wafer W in the case of the target20, and the activated metal coats the inner wall surface of the processing chamber10in the case of the target21. The film forming apparatus1includes the head40. The head40injects an oxidizing gas for oxidizing the Mg film formed on the wafer W toward the mounting table14. The head40has, e.g., a circular shape in a plan view, and an area thereof in a plan view is greater than that of the wafer attraction surface14cof the mounting table14. As shown inFIG.3, the head40moves between positions P1, P2, and P3by an operation of a driving mechanism70to be described later. The position P1is located above the mounting table14in the processing space S1between the targets20and21and the mounting table14. The position P2is distant from the processing space S1in the film forming apparatus1and is located in a space S2different from the processing space S1. Specifically, the position P2faces the position P1with the supporting shaft70aof the driving mechanism70to be described later interposed therebetween in a plan view. The position P3is not overlapped with the position P2in the space S2. One end of a connecting portion41extending in a direction orthogonal to an axis AX2of the supporting shaft70ais connected to a peripheral portion of the head40. The other end of the connecting portion41is connected to the supporting shaft70a. A gas line GL1for an oxidizing gas is formed in the head40, the connecting portion41, and the supporting shaft70a. The end portion of the gas line GL1opposite to the portion connected to the head40is located outside the processing chamber10and is connected to a gas supply unit31. The gas supply unit31has, e.g., a gas source (GS)31aand a flow rate controller (FRC)31bsuch as a mass flow controller or the like. The gas source31astores an oxidizing gas (e.g., O2gas). The gas source31ais connected to the gas line GL1through the flow rate controller31b. In the head40, the gas line GL1is connected to a plurality of gas injection holes40aformed at the head40. The gas injection ports40aare opened downward, i.e., toward the mounting table14. The film forming apparatus1further includes the surface potential system50as a charge amount measurement unit. The surface potential system50measures the charge amount on the wafer attraction surface of the mounting table14, i.e., the wafer attraction surface14cof the electrostatic chuck14b, in a non-contact manner. Specifically, the potential of the wafer attraction surface14cis measured in a non-contact manner. More specifically, the surface potential system50measures, in a non-contact manner, a potential of a portion of the wafer attraction surface14cthat is exposed through an opening60aof the shield member60to be described later. The measurement result of the surface potential system50is outputted to a controller (CNT)100to be described later. The charge amount at the portion exposed through the opening60aon the wafer attraction surface14cis calculated based on, e.g., the measurement result, the area of the opening60ain a plan view, and the like. As shown inFIG.4, the surface potential system50is moved between positions P11, P12, and P13by the operation of the driving mechanism70to be described later. The position P11is located above the mounting table14in the processing space S1between the targets20and21and the mounting table14. The position P12is distant from the processing space S1in the film forming apparatus1and is located in a space S2different from the processing space S1. Specifically, the position P12faces the position P11with the supporting shaft70aof the driving mechanism70to be described later interposed therebetween in a plan view. The position P13is not overlapped with the position P12in the space S2. The surface potential system50is disposed below one end of a supporting portion S1extending in a direction orthogonal to the axis AX2of the supporting shaft70a. The supporting shaft70ais connected to the other end of the supporting portion51. Further, the surface potential system50is disposed at a height position where the opening60aof the shield member60to be described later is located in a measurement target region A of the surface potential system50in a plan view. The film forming apparatus1further includes the shield member60. The shield member60can be disposed between the surface potential system50located at the position P11and the wafer attraction surface14cof the mounting table14. The shield member60has an opening60awhose area is smaller than that of the wafer attraction surface14cin a plan view. The shield member60has, e.g., a circular shape in a plan view, and an area thereof in a plan view is greater than that of the wafer attraction surface14cof the mounting table14. The opening60ahas, e.g., a sector shape in a plan view. The opening60ais formed such that a vertex60bof the central angle of the sector coincides with the center of rotation of the mounting table14, i.e., the axis AX1, in a plan view when the shield member60is located at a position P21to be described later. Further, the opening60ais formed such that the radial length of the sector is substantially equal to the radius of the attraction surface14c. In the present embodiment, the central angle of the sector of the opening60ais 90°. During the rotation of the mounting table14, the potential of the portion of the wafer attraction surface14cof the electrostatic chuck14bthat is exposed through the opening60ais measured by the surface potential system50. Accordingly, the potential in each of four regions obtained by equally dividing the wafer attraction surface14cof the electrostatic chuck14bin the circumferential direction can be measured. The shield member60is made of a metal such as aluminum or the like and is connected to a ground potential. As shown inFIG.5, the shield member60is moved between positions P21, P22, and P23by the operation of the driving mechanism70to be described later. The position P21is located above the mounting table14in the processing space S1between the targets20and21and the mounting table14. The position P22is distant from the processing space S1in the film forming apparatus1and is located in a space S2different from the processing space S1. Specifically, the position P22faces the position P21with a supporting shaft70aof the driving mechanism70to be described later interposed therebetween in a plan view. The position P23is not overlapped with the position P22in the space S2. One end of a connecting portion61extending in a direction orthogonal to the axis AX2of the supporting shaft70ais connected to a peripheral portion of the shield member60. The other end of the connecting portion61is connected to the supporting shaft70a. The film forming apparatus1further includes the driving mechanism70as a retreating mechanism. The driving mechanism70has, e.g., a supporting shaft70aand a driving unit70b. The supporting shaft70aextends along the axis AX2. The axis AX2is substantially parallel to the axis AX1, and extends vertically at the side of the mounting table14. The distance between the axis AX2and the center position of the head40and the distance between the axis AX2and the center position of the shield member60are substantially equal to the distance between the axis AX2and the axis AX1. The supporting shaft70aextends vertically to penetrate through the bottom wall of the processing chamber10. A sealing member SL2is disposed between the supporting shaft70aand the bottom wall of the processing chamber10. The sealing member SL2seals a space between the bottom wall of the processing chamber10and the supporting shaft70aso that the supporting shaft70acan rotate and move vertically. The sealing member SL2is, e.g., a magnetic fluid seal. The supporting portion51, the connecting portion41, and the connecting portion61are connected to the side surface of the supporting shaft70ain that order from top to bottom. The supporting portion51and the connecting portion61are connected to one side surface of the supporting shaft70a, and the connecting portion41is connected to the other side surface of the supporting shaft70a. The driving unit70bis connected to the lower end of the supporting shaft70a. The driving unit70bgenerates a driving force for rotating and vertically moving the supporting shaft70a. As the supporting shaft70arotates about the axis AX2, the head40, the surface potential system50, and the shield member60rotate about the axis AX2. As the supporting shaft70amoves vertically, the head40, the surface potential system50, and the shield member60move vertically. The film forming apparatus1further includes the charge neutralization mechanism80. The charge neutralization mechanism80performs charge neutralization on the wafer attraction surface14cof the mounting table14. In the present embodiment, the charge neutralization mechanism80performs the charge neutralization using an ionized gas. As shown inFIG.6, the charge neutralization mechanism80moves between positions P31and P32by an operation of a driving mechanism71to be described later. When the charge neutralization mechanism80is located at the position P31, the tip end of the charge neutralization mechanism80faces the mounting table14. The position P31is close to the mounting table14. The position P32is distant from the processing space S1between the targets20and21and the mounting table14in the film forming apparatus1. The positon P32is located in a space S2different from the processing space S1. The position P32is far from the mounting table14compared to the position P31. One end of a connecting portion81extending in a direction orthogonal to an axis AX3of a supporting shaft71aof the driving mechanism71to be described later is connected to the base of the charge neutralization mechanism80. The other end of the connecting portion81is connected to the supporting shaft71a. A gas line GL2for an ionized gas is formed at the connecting portion81and the supporting shaft71a. One end of the gas line GL2is connected to the charge neutralization mechanism80. The other end of the gas line GL2is located outside the processing chamber10and is connected to a gas supply unit32. The gas supply unit32has, e.g., a gas source (GS)32aand an ionization unit (IU)32b. The gas source32astores an ionization gas (e.g., N2gas). The gas source32ais connected to the gas line GL2through the ionization unit32b. The ionization unit32bionizes the ionization gas from the gas source32aby corona discharge, UV irradiation, soft X-ray irradiation, or the like to generate an ionized gas. The generated ionized gas is supplied to the charge neutralization mechanism80through the gas line GL2and is discharged from the tip end of the charge neutralization mechanism80toward the mounting table14. The film forming apparatus1further include the driving unit71. The driving unit71has, e.g., the supporting shaft71aand a driving unit (DU)71b. The supporting shaft71aextends along the axis AX3. The axis AX3is substantially parallel to the axis AX1and the axis AX2and extends vertically on the side of the mounting table14opposite to the supporting shaft70aside. Further, the supporting shaft71aextends vertically to penetrate through the bottom wall of the processing chamber10. A sealing member SL3is disposed between the supporting shaft71aand the bottom wall of the processing chamber10. The sealing member SL3seals the space between the bottom wall of the processing chamber10and the supporting shaft71aso that the supporting shaft71acan rotate. The sealing member SL3is, e.g., a magnetic fluid seal. The connecting portion81is connected to an upper end of the supporting shaft71a. The driving unit71bis connected to a lower end of the supporting shaft71a. The driving unit71bgenerates a driving force for rotating the supporting shaft71a. As the supporting shaft71arotates about the axis AX3, the charge neutralization mechanism80rotates about the axis AX3. The film forming apparatus1further includes a controller100. The controller100is, e.g., a computer including a CPU, a memory, and the like, and has a program storage unit (not shown). The program storage unit stores a program for controlling the driving units16b,70band71band the like to perform a film forming process to be described later in the film forming apparatus1. The program is recorded in a computer-readable storage medium and may be installed in the controller100from the storage medium. A part or the entire program may be realized by a dedicated hardware (circuit board). Next, a film forming process using the film forming apparatus1will be described with reference toFIGS.7to9.FIG.7is a flowchart for explaining the film forming process.FIG.8shows a state in the processing chamber10during a charge amount measuring process to be described later.FIG.9shows a state in the processing chamber10during a charge neutralization process to be described later. Before the film forming process is started, the head40is located at the position P3; the surface potential system50is located at the position P13; the shield member60is located at the position P23; and the charge neutralization mechanism80is located at the position P32. (Loading) As shown inFIG.7, first, the wafer W is loaded into the processing chamber10whose inner pressure is adjusted to a predetermined pressure (step S1). Specifically, the gate valve13ais opened, and a transfer mechanism (not shown) holding the wafer W is moved from a transfer chamber (not shown) in a vacuum atmosphere adjacent to the processing chamber10into the processing chamber10through the loading/unloading port13. Then, the wafer W is transferred to a position above the mounting table14. Next, the wafer W is transferred to the raised support pins (not shown). Thereafter, the transfer mechanism retreats from the processing chamber10, and the gate valve13ais closed. At the same time, the support pins are lowered, and the wafer W is mounted on the mounting table14and attracted and held on the electrostatic chuck14bby the electrostatic attractive force. (Coating) Next, the inner wall surface of the processing chamber10is coated (step S2). Specifically, the driving mechanism70is controlled such that the head40is located at the position P1; the surface potential system50is located at the position P12; and the shield member60is located at the position P22. The position of the charge neutralization mechanism80is maintained at the position P32. A gas is supplied from the gas supply unit30into the processing chamber10, and a power is supplied from the power supply22bto the target21. A magnetic field is generated by the magnet23b. At this time, the flow rate of the gas supplied from the gas supply unit30is, e.g., 10 sccm to 500 sccm, and the power supplied from the power supply22bto the target21is, e.g., 50 W to 1000 W. In this coating process, plasma is generated to be concentrate below the target21. Due to collision between positive ions in the generated plasma and the target21, an activated metal is released from the target21. The inner wall surface of the processing chamber10is coated with the activated metal. The vacuum level in the processing chamber10is increased due to the gettering action of the coated activated metal. Accordingly, a high-quality MgO layer can be formed. In the coating process, the head40is located at the position P1and the wafer W is covered with the head40, so that the contamination of the wafer W can be reduced or prevented. (Pre-Sputtering) Next, pre-sputtering is performed (step S3). Specifically, the gas is supplied from the gas supply unit30into the processing chamber10and the power is supplied from the power supply22ato the target20in a state where the head40is located at the position P1; the surface potential system50is located at the position P12; the shield member60is located at the position P22; and the charge neutralization mechanism80is located at the position P32. Further, a magnetic field is generated by the cathode magnet23a. At this time, the flow rate of the gas supplied from the gas supply unit30is, e.g., 10 sccm to 500 sccm, and the power supplied from the power supply22ato the target20is, e.g., 50 W to 1000 W. In the pre-sputtering process, plasma is generated and concentrated below the target20. Then, the surface of the target20is etched due to collision between positive ions in the generated plasma and the target20. Therefore, the surface of the target20that may be contaminated during another process can be removed. Accordingly, in a film forming process to be described later, an Mg film with less contamination can be formed. In the pre-sputtering process, the head40is located at the position P1and the wafer W is covered by the head40, so that the contamination of the wafer W can be reduced or prevented. (Mg Film Formation) Next, an Mg film is formed by sputtering (step S4). Specifically, the driving mechanism70is controlled such that the head40is located at the position P3; the surface potential system50is located at the position P13; and the shield member60is located at the position P23. The position of the charge neutralization mechanism80is maintained at the position P32. In this state, the mounting table14is rotated by the driving mechanism16, and the gas is supplied from the gas supply unit30into the processing chamber10. Further, the power is supplied from the power supply22ato the target20, and a magnetic field is generated by the cathode magnet23a. At this time, the rotation speed of the mounting table14is, e.g., 30 rpm to 300 rpm; the flow rate of the gas supplied from the gas supply unit30is, e.g., 10 sccm to 500 sccm; and the power supplied from the power supply22ato the target20is, e.g., 50 W to 1000 W. In the Mg film forming process, plasma is generated and concentrated below the target20. Mg is released from the surface of the target20due to collision between positive ions in the generated plasma and the target20. Accordingly, an Mg film is formed on the wafer W. In the Mg film forming process, the surface potential system50that has retreated from the position P11as the measurement position is located at the position P13, so that it is possible to prevent the Mg film formation from being hindered by the surface potential system50. (Oxidation) Next, the Mg film formed on the wafer W is oxidized (step S5). Specifically, the driving mechanism70is controlled such that the head40is located at the position P1; the surface potential system50is located at the position P12; and the shield member60is located at the position P22. The position of the charge neutralization mechanism80is maintained at the position P32. In this state, the mounting table14is rotated by the driving mechanism16, and the oxidizing gas is supplied from the gas supply unit31to the head40. At this time, the rotation speed of the mounting table14is, e.g., 30 rpm to 300 rpm; the flow rate of the oxidizing gas is, e.g., 10 sccm to 2000 sccm; and the temperature of the oxidizing gas is, e.g., 50° C. to 300° C. In the oxidation process, the Mg film formed on the wafer W is oxidized by the oxidizing gas injected from the head40toward the mounting table14. Accordingly, an MgO film is formed. The above-described steps S3to S5may be repeatedly performed in that order. (Unloading) Next, the wafer W is unloaded from the processing chamber10(step S6). Specifically, the driving mechanism70is controlled such that the head40is located at the position P3; the surface potential system50is located at the position P13; and the shield member60is located at the position P23. The position of the charge neutralization mechanism80is maintained at the position P32. Then, the attraction and holding of the wafer W by the electrostatic attractive force of the electrostatic chuck14bis released. The support pins (not shown) are raised, and the wafer W is transferred onto the support pins. The gate valve13ais opened, and the transfer mechanism (not shown) is moved from the transfer chamber (not shown) in a vacuum atmosphere adjacent to the processing chamber10into the processing chamber10through the loading/unloading port13. Next, the support pins are lowered, and the wafer W is transferred to the transfer mechanism. Thereafter, the transfer mechanism transfers the wafer W to the outside of the processing chamber10through the loading/unloading port13. Then, the gate valve13ais closed. (Charge Amount Measurement) Next, the charge amount on the wafer attraction surface14cof the electrostatic chuck14bis measured (step S7). Specifically, the driving mechanism70is controlled such that the head40is located at the position P2; the surface potential system50is located at the position P11; and the shield member60is located at the position P21. The position of the charge neutralization mechanism80is maintained at the position P32. In this state, the mounting table14is rotated by the driving mechanism16so that the portion of the wafer attraction surface14cthat is exposed through the opening60ato the surface potential system50is switched. Then, the surface potential system50performs measurement in synchronization with the rotation (e.g., whenever the mounting table14makes ¼ rotation). Specifically, as shown inFIG.8, the potential of the portion of the wafer attraction surface14cof the electrostatic chuck14bthat is exposed through the opening60ais sequentially measured by the surface potential system50. Accordingly, the surface potential in each of four regions (hereinafter, referred to as “divided regions”) obtained by equally dividing the wafer attraction surface14cof the electrostatic chuck14bin the circumferential direction is measured. Then, the controller100calculates the charge amount for each divided region based on the measured surface potential and the area of the opening60a. In other words, the controller100obtains the charge distribution on the wafer attraction surface14cof the electrostatic chuck14bbased on the measurement result of the surface potential system50and the area of the opening60a. (Abnormal Charging Determination) Next, it is determined whether or not the electrostatic chuck14bis abnormal based on the charge distribution on the wafer attraction surface14cof the electrostatic chuck14b(step S8). Specifically, the controller100determines whether or not there is a divided region on the wafer attraction surface14cof the electrostatic chuck14bwhere the charge amount exceeds a threshold value pre-stored in a storage unit (not shown). If the electrostatic chuck14bis normal, specifically, if there is no divided region where the charge amount exceeds the threshold value on the wafer attraction surface14cof the electrostatic chuck14b, the processing returns to step S1and a next wafer W to be processed is loaded. The processing returns to step S1after the driving mechanism70is controlled such that the head40is located at the position P3; the surface potential system50is located at the position P13; and the shield member60is located at the position P23. (Charge Neutralization) On the other hand, if the electrostatic chuck14bis abnormal, specifically, if there is a divided region on the wafer attraction surface14cof the electrostatic chuck14bwhere the charge amount exceeds the threshold value, the charge neutralization is performed on the wafer attraction surface14c(step S9). For example, the driving mechanism70is controlled such that the head40is located at the position P3; the surface potential system50is located at the position P13; and the shield member60is located at the position P23, and the driving mechanism71is controlled such that the position of the charge neutralization mechanism80is maintained at the position P31. In this state, the mounting table14is rotated by the driving mechanism16. Then, the ionized gas is supplied from the gas supply unit32to the charge neutralization mechanism80. In the charge neutralization process, the charge neutralization is performed on the wafer attraction surface14cof the electrostatic chuck14bby the ionized gas injected from the charge neutralization mechanism80toward the mounting table14as shown inFIG.9. Then, the driving mechanism71is controlled such that the charge neutralization mechanism80is located at the position P32. Thereafter, the processing returns to step S1, and a next wafer W to be processed is loaded. As described above, the film forming apparatus1of the present embodiment includes the charge neutralization mechanism80for neutralizing charges on the wafer attraction surface14c. Since the charge neutralization mechanism80can neutralize charges on the wafer attraction surface, it possible to prevent a problem that occurs when the wafer W is chucked on the electrostatic chuck14bof the mounting table14or when the wafer W is dechucked from the electrostatic chuck14b. The film forming apparatus1further includes the surface potential system50for measuring the charge amount on the wafer attraction surface14cof the mounting table14. Therefore, the charges on the wafer attraction surface14ccan be neutralized depending on the charging state of the wafer attraction surface14c. Since it is not necessary to perform the charge neutralization for each wafer W, the decrease in the throughput can be suppressed. The film forming apparatus1further includes the driving mechanism70for making the surface potential system50retreat from the position P11as the measurement position facing the wafer attraction surface14c. Therefore, the Mg film formation is not hindered by the surface potential system50. In the present embodiment, the film forming apparatus1includes the shield member60having the opening60aand the driving mechanism16. In the charge amount measuring process, the driving mechanism16rotates the mounting table14so that the portion of the wafer attraction surface14cthat is exposed through the opening60aof the shield member60to the surface potential system50located at the position P11is switched. The surface potential system50measures the charge amount, specifically, the potential of the portion of the wafer attraction surface14cthat is exposed through the opening60aof the shield member60. Therefore, the film forming apparatus1can obtain the charge amount distribution on the wafer attraction surface14c. Accordingly, the wafer W can be prevented from being damaged during dechucking due to local charging on the wafer attraction surface14c. Further, in the present embodiment, the driving mechanism70of the head40for oxidation serves as the retreating mechanism for making the surface potential system50and the shield member60retreat from the processing space S1(specifically, the position P11or P21) above the mounting table14. Therefore, it is possible to suppress the scaling up of the film forming apparatus1. Alternatively, the driving mechanism70of the head40for oxidation may serve as the retreating mechanism for only one of the surface potential system50and the shield member60. In the present embodiment, since the surface potential system50or the shield member60retreats from the processing space S1above the mounting table14, a moving mechanism for horizontally moving the mounting table14is not required and, thus, the conventional film forming apparatus can be used. In the present embodiment, the opening60aof the shield member60has a sector shape in a plan view, and the vertex60bof the central angle of the sector of the opening60acoincides with the axis AX1that is the center of rotation of the mounting table14by the driving mechanism16. Therefore, the charge amount in the divided regions obtained by equally dividing the wafer attraction surface14cin the circumferential direction can be measured by synchronizing the rotation of the mounting table14by the driving mechanism16with the measurement timing of the surface potential system50. The divided regions have no overlapping portions. In the case of calculating the charge amount based on the measurement result of the surface potential system50, the calculated charge amount is an average value within a potential measurement range. Therefore, if the charge amount measurement regions are overlapped unlike the present embodiment, it is difficult to accurately detect the charging state of the wafer attraction surface14c. Accordingly, in the present embodiment, the charging state of the wafer attraction surface14ccan be detected more accurately. Further, in the present embodiment, since the shield member60is made of a metal and is grounded, the measurement result of the surface potential system50is not affected by the shield member60. Accordingly, the charging state of the surface14ccan be accurately detected. FIG.10is a plan view showing another example of the shield member. The shield member60shown inFIG.2has the sector-shaped opening60ahaving a central angle of 90° in a plan view. However, the shape of the opening is not limited thereto. For example, the opening may have a sector shape having a central angle of 10° in a plan view as in the case of an opening110aof the shield member110shown inFIG.10. Similarly to the opening60a, the opening110ais formed such that the vertex of the central angle of the sector in a plan view coincides with the center of rotation of the mounting table14in a plan view. By using the shield member110, it is possible to detect the charge amount in each of 36 divided regions obtained by equally dividing the wafer attraction surface14cin the circumferential direction. By using a shield member having a sector-shaped opening, e.g., the opening110a, with a small central angle in a plan view, it is possible to obtain more accurate charge distribution on the wafer attraction surface14cof the electrostatic chuck14b. Therefore, extremely local charging on the wafer attraction surface14ccan be detected, which makes it possible to prevent defective dechucking caused by the extremely local charging. When the opening of the shield member has a sector shape in a plan view, an arc portion of the sector may be straight, or radially extending portions may be curved. FIG.11is a vertical cross-sectional view schematically showing a configuration of a film forming apparatus1ain which the shield member60shown inFIG.2and the shield member110shown inFIG.10can be replaced. In the film forming apparatus1ashown inFIG.11, the supporting shaft70ais divided into an upper supporting shaft70aiand a lower supporting shaft70a2. The head40is fixed to the lower supporting shaft70ai, and one of the shield members60and110is detachably fixed to the lower supporting shaft70ai. The surface potential system50is fixed to the upper supporting shaft70a2. The lower supporting shaft70aiand the upper supporting shaft70a2are connected through a driving unit72. The driving unit72generates a driving force for vertically moving the supporting shaft70a2. As the supporting shaft70a2moves vertically, the distance between the surface potential system50and the shield member60or110changes. Since the size of the measurement target region A of the surface potential system50is determined by the distance from the surface potential system50to a measurement target, the position of the surface potential system50is changed in response to the size of the opening of the shield member. For example, in the case of the shield member60having the large opening60a, the surface potential system50is located distant from the shield member69so that the measurement target region A becomes large as shown inFIG.2. In the case of the shield member having the small opening110a, the surface potential system50is located close to the shield member110so that the measurement target region A becomes small. If the shield members having openings with different sizes can be replaced as in this example, the resolution in detecting the charge amount on the wafer attraction surface14ccan be changed. Instead, a shield member having a variable opening size may be provided. By providing the driving unit72for generating a driving force for vertically moving the supporting shaft70a2to which the surface potential system50is fixed, it is possible to measure a potential of a wafer in accordance with a diameter of the wafer in the case where neither the shield member60nor the shield member110is installed. In the above description, when the wafer attraction surface14cof the electrostatic chuck14bis abnormal, the charge neutralization mechanism80performs charge neutralization on the entire wafer attraction surface14c. Alternatively, the charge neutralization mechanism80may perform charge neutralization only on a divided region of the wafer attraction surface14cwhere the charging abnormality has occurred. Specifically, the driving mechanism16is controlled such that the divided region of the wafer attraction surface14cwhere the charging abnormality has occurred is positioned below the charge neutralization mechanism80located at the position P31. In addition, the moving mechanism for vertically moving the neutralization mechanism80is provided to move the charge neutralization mechanism80close to the wafer attraction surface14c. Accordingly, the charge neutralization can be performed only on the divided region of the wafer attraction surface14cwhere the charging abnormality has occurred by the ionized gas from the charge neutralization mechanism80. In the above description, the charge amount on the wafer attraction surface14cis measured for each wafer W. However, the measurement may be performed for a predetermined number of wafers, e.g., two or more wafers. Undesirable charging is more likely to occur on an electrostatic chuck using Johnson-Rahbek force than on an electrostatic chuck using Coulomb force. Therefore, the charge amount is measured for each wafer in the case of the former electrostatic chuck that is often used in a high-temperature region (wafer temperature: 150° C. to 400° C.), and the charge amount is measured for every 50 wafers in the case of the latter electrostatic chuck that is often used in a low-temperature region (wafer temperature: −173° C. to a room temperature). In the above description, the ionized gas is supplied from the charge removing mechanism80to neutralize charges on the wafer attraction surface14c. However, the charge neutralization method is not limited thereto. For example, the gas in the processing chamber10may be ionized by UV irradiation or the like, and the charges may be neutralized by the ionized gas thus generated. While the apparatus for forming an MgO film has been described as an example, the present disclosure can be applied to another film forming apparatus. Further, the present disclosure can be applied to a substrate processing apparatus including an electrostatic chuck and configured to perform substrate treatment other than the film formation. In the above-described example, the supporting portion51and the connection portions41and61are connected to the supporting shaft70a, and the surface potential system50, the head40, and the shield member60are integrally rotated. However, the surface potential system50, the head40, and the shield member60may be independently rotated. In order to independently rotate the surface potential system50, the head40, and the shield member60, it is considered to concentrically arrange two cylindrical supporting shafts about one supporting shaft and to connect the supporting portion51and the connection portions41and61to the supporting shaft and the two cylindrical supporting shafts, respectively. By independently rotating the surface potential system50, the head40, and the shield member60, the position P2as a standby position of the head40at the time of measuring the charge amount, or the position P12or P22as a standby position of the surface potential system50or the shield member60at the time of coating or the like can be omitted. Accordingly, the size of the processing chamber can be reduced. In the above-described embodiment, the charge amount is measured after the unloading of the wafer. However, the charge amount may be measured before the loading of the wafer, such as start of processing of a processing lot, or the like. By measuring the charge amount before the loading of the wafer, the initial state of the electrostatic attraction surface can be detected. Accordingly, the wafer can be prevented from being loaded in an abnormal charging state. In the above embodiment, the charge amount on the electrostatic chuck is measured in a state where no wafer is mounted. However, the charge amount may be measured in a state where the wafer is loaded and mounted on the electrostatic chuck. Therefore, the amount of charges moved from the wafer to the electrostatic chuck can be monitored. Accordingly, it is possible to more effectively suppress defective dechucking. The embodiments of the present disclosure are illustrative in all respects and are not restrictive. The above-described embodiments can be embodied in various forms. Further, the above-described embodiments may be omitted, replaced, or changed in various forms without departing from the scope of the appended claims and the gist thereof. The following configurations are also included in the technical scope of the present disclosure.(1) There is provided a substrate processing apparatus for processing a substrate, comprising: a processing chamber accommodating the substrate, a mounting table disposed in the processing chamber and configured to attract and hold the substrate using an electrostatic attractive force; a charge amount measurement unit disposed in the processing chamber and configured to measure charge amount of a substrate attraction surface of the mounting table; a charge neutralization mechanism configured to neutralize the substrate attraction surface of the mounting table; and a retreating mechanism configured to make the charge amount measurement unit retreat from a measurement position facing the substrate attraction surface of the mounting table. With the configuration (1), the charge neutralization mechanism is provided to perform charge neutralization on the substrate attraction surface, so that it is possible to prevent a problem that occurs during chucking or dechucking of the substrate due to the electrostatic attractive force of the mounting table. Further, since the substrate processing apparatus includes the charge amount measurement unit, it is possible to perform charge neutralization on the substrate attraction surface depending on the charging state of the substrate attraction surface and, thus, it is not necessary to perform the charge neutralization for each substrate or the like. Accordingly, a decrease in the throughput can be suppressed. Further, since the substrate processing apparatus includes the retreating mechanism for making the charge amount measurement unit retreat from the measurement position facing the substrate attraction surface, the substrate treatment is not hindered by the charge amount measurement unit.(2) In the substrate processing apparatus of the configuration (1), the substrate processing apparatus further comprises a shield member disposable between the charge amount measurement unit located at the measurement position and the mounting table and provided with an opening smaller than the substrate attraction surface of the mounting table; and a rotation driving unit configured to rotate the mounting table. Further, the rotation driving unit may rotate the mounting table so that a portion of the substrate attraction surface of the mounting table that is exposed through the opening of the shield member to the charge amount measurement unit located at the measurement position is switched, and the charge amount measurement unit may sequentially perform the measurement on the portion of the substrate attraction surface of the mounting table that is exposed through the opening of the shield member. With the configuration (2), the charge amount distribution on the substrate attraction surface can be obtained, so that it is possible to prevent a problem caused by local charging on the substrate attraction surface (e.g., damages inflicted on the substrate during dechucking, or the like).(3) In the substrate processing apparatus of the configuration (2), the opening may have a sector shape in a plan view.(4) In the substrate processing apparatus of the configuration (3), a vertex of a central corner of the sector shaped opening may coincide with a rotation center of the mounting table rotated by the rotation driving unit. With the configuration (4), the charging state of the substrate attraction surface can be detected more accurately.(5) In the substrate processing apparatus of any one of the configurations (2) to (4), the shield member may be made of a metal and grounded. With the configuration (5), the charging state of the substrate attraction surface can be accurately detected.(6) In the substrate processing apparatus of any one of the configurations (1) to (5), the charge neutralization mechanism may perform charge neutralization when the charge amount of the substrate attraction surface of the mounting table exceeds a threshold value.(7) In the substrate processing apparatus of any one of the configurations (2) to (5), the charge neutralization mechanism may neutralize a portion of the mounting surface of the mounting table where the charge amount exceeds a threshold value.(8) There is provided a charge neutralization method for a mounting table disposed in a substrate processing apparatus for processing a substrate, the mounting table configured to attract and hold a substrate using an electrostatic attractive force, the method comprising: moving a charge amount measurement unit disposed in a processing chamber to measure charge amount of a substrate attraction surface of the mounting table to a measurement position facing the substrate attraction surface of the mounting table; measuring the charge amount using the charge amount measurement unit; neutralizing the substrate attraction surface of the mounting table according to a measurement result obtained in said measuring; and making the charge amount measurement unit retreat from the measurement position. While certain embodiments have been described, these embodiments have been presented by way of example only, and are not intended to limit the scope of the disclosures. Indeed, the embodiments described herein may be embodied in a variety of other forms. Furthermore, various omissions, substitutions and changes in the form of the embodiments described herein may be made departing from the spirit of the disclosures. The accompanying claims and their equivalents are intended to cover such forms or modifications as would fall within the scope and spirit of the disclosures. | 51,801 |
11862440 | DETAILED DESCRIPTION OF EXEMPLARY EMBODIMENTS FIG.1is a schematic sectional view showing semiconductor processing equipment according to an exemplary embodiment of the disclosure.FIG.2is a view explaining a lower electrode ofFIG.1. The size and thickness of each constituent element shown in the drawings are given merely for convenience of description, and exemplary embodiments of the disclosure are not limited thereto. Thicknesses of various layers and regions may be exaggerated in order to clearly express the layers and regions. In the specification, one direction of horizontal directions (width directions or lateral directions) is defined as a first direction DR1and one direction of vertical directions (thickness directions or height directions) crossing the first direction DR1is defined as a second direction DR2. Referring toFIGS.1and2, semiconductor processing equipment1may be used for a semiconductor process for processing substrates10such as semiconductor wafers. For example, the semiconductor process may include chemical vapor deposition (CVD), atomic layer deposition (ALD), conductor etching, dielectric etching, rapid thermal processing (RTP), ion implantation and physical vapor deposition (PVD), and/or other etching processes, a deposition process or a cleaning process. In the semiconductor process, gas mixtures may be introduced into a chamber20of the semiconductor processing equipment1and plasma may be used to initiate and sustain chemical reactions. In an embodiment, the semiconductor processing equipment1may include the chamber20, an upper electrode30disposed at a top portion of the chamber20, a substrate supporting structure50disposed in an interior of the chamber20, a vertical rod21supporting the substrate supporting structure50, a side structure61to65disposed adjacent to the substrate supporting structure50, and a gas supplier40disposed outside the chamber20. The substrate supporting structure50may include a lower electrode51, a first plate52, an attraction electrode53, and a second plate54. The side structure61to65may include a focus ring61, an upper edge ring62, a lower edge ring63, an isolator64, and a ground plate65. In an embodiment, the chamber20may have a substantially cylindrical shape. For example, an inner surface of the chamber20may be in a state of being subjected to alumite treatment (anodization). The interior of the chamber20may include a function of a processing chamber in which plasma processing such as an etching process, etc. is performed by plasma. In an embodiment, the chamber20may include, at one side thereof (for example, a top side), an opening area OA in which the upper electrode30may be disposed. The upper electrode30may be disposed in the opening area OA such that the upper electrode30closes the chamber20. An edge of the upper electrode30may be surrounded by the chamber20. Although not clearly shown, an insulating material may be interposed between the upper electrode30and the chamber20. In some embodiments, the upper electrode30may be grounded. A lower surface of the upper electrode30may be flat. The upper electrode30may be connected to the gas supplier40. In this case, the gas supplier40may supply a gas to the interior of the chamber20through the upper electrode30. The upper electrode30may receive the gas and may diffuse the received gas. For example, the upper electrode30may form a plasma sheath S having a center peak in a processing volume PV above a substrate10. In another example, the upper electrode30may form a plasma sheath S having a center peak and a plasma density peak in an edge region of the substrate10(for example, a region spaced apart from a center by 80 to 150 mm) (an edge peak). Here, the processing volume PV is defined by a space between the substrate supporting structure50and the upper electrode30and includes a space in which the substrate10is disposed.FIG.1illustrates an example in which, in a semiconductor process, plasma forms a plasma sheath having a center peak and a density peak in the edge region (an edge peak). That is, the plasma may have different densities in the processing volume PV in accordance with positions thereof from a center thereof. Due to non-uniformity of plasma density, for example, an etching rate may be variable between the center of the substrate10and an outer perimeter of the substrate10. Furthermore, due to non-uniformity of plasma density, for example, sheath bending and ion incidence angle tilt at the outer perimeter of the substrate may cause high aspect ratio contact (HARC) profile tilt. In the substrate supporting structure50, the lower electrode51, the first plate52, the attraction electrode53and the second plate54may be disposed in the second direction DR2in this order. The lower electrode51may be an electrostatic chuck (ESC). When a DC voltage or a high-voltage (HV) voltage is applied, the lower electrode51may cause the substrate10to be attracted toward the lower electrode51by Coulomb force and may maintain the substrate10in the attracted state. A step may be provided at an outer perimeter portion of the lower electrode51. The lower electrode51may be divided into a processing area PA and a side area EA disposed inside and outside the step of the outer perimeter portion, respectively. For example, in the lower electrode51, the height (thickness) of the processing area PA may be greater than the thickness of the side area EA. An angle of a wall formed by the step of the lower electrode51may be 80 to 90°. The processing area PA may overlap with an area where the substrate10is laid. An upper surface of the processing area PA may not be flat, but may be curved. That is, the upper surface of the processing area PA in the lower electrode51may include a curved surface. The side area EA may be an area where the focus ring61is mounted. In an embodiment, the upper surface of the processing area PA may have a shape similar to that of the plasma sheath S. For example, the shape of the upper surface of the processing area PA may be formed to have the same shape as the plasma sheath S. That is, in an embodiment, the upper surface of the processing area PA may have a first peak f1and a second peak f2respectively corresponding to a center peak and an edge peak. For example, the first peak f1corresponds to a central portion of the processing area PA and the second peak f2is disposed in an area adjacent to an edge of the processing area PA. For example, although not clearly shown, the first peak f1may have the form of a point on a plane and the second peak f2may have the form of a circle surrounding the point when viewed in a plan view. Each of the first peak f1and the second peak f2may have a maximum height in an area adjacent thereto (within a fine distance δ). In an embodiment, the height of the first peak f1may be greater than the height of the second peak f2. That is, the height of the lower electrode51may be maximized at a central portion thereof. The upper surface of the processing area PA may include a valley v1disposed between the first peak f1and the second peak f2. Although not clearly shown, the valley v1may have the form of a circle disposed between the first peak f1having the form of a point and the second peak f2having the form of a circle. The valley v1may have a minimum height in an area adjacent thereto (within a fine distance δ). For example, a height difference hl between the first peak f1and the valley v1may be 0.2 mm or less. The upper surface of the processing area PA may include a first inflection point it disposed between the first peak f1and the valley v1and a second inflection point i2disposed between the second peak f2and the valley v1. Each of the inflection points it and i2may be defined by a position where the sign of a bending moment of the upper surface of the processing area PA is varied. In an embodiment, a tilt (for example, θ1, θ2or θ3) of the upper surface of the lower electrode51may be 0.01 or less in all portions of the processing area PA. For example, the upper surface of the lower electrode51may have a maximum tilt (for example, θ1) at the first inflection point it or the second inflection point i2, but may have a tilt (for example, θ1, θ2or θ3) of 0.01 or less at the first inflection point i1, the second inflection point, and points adjacent thereto. The first plate52may be disposed on the lower electrode51. In an embodiment, the first plate52may be disposed throughout the entire surface of the processing area PA. An upper surface of the first plate52may be flat. Of course, a lower surface of the first plate52may be curved. The first plate52may have different thicknesses in accordance with positions thereof inside the step, due to the curved shape of the processing area PA of the lower electrode51disposed under the first plate52. For example, in an embodiment, the lower surface of the first plate52in an area overlapping with the processing area PA may be a curved surface. In addition, the thickness of the first plate52may be minimized in a portion overlapping with the first peak f1(for example, a central portion) from among portions of the area overlapping with the processing area PA. For example, the first plate52may include a dielectric material. For example, the dielectric material may include ceramic, aluminum oxide (Al2O3), etc. Although not shown, the first plate52may include a heating layer such as a multi-zone heating plate. An attraction electrode53may be disposed on the first plate52. The attraction plate53may be disposed inside the step of the first plate52and may overlap with the processing area PA of the lower electrode51. In an embodiment, the attraction electrode53may generate electrostatic force causing the substrate10to be attracted to the substrate supporting structure50. A DC voltage for attracting the substrate10may be applied to the attraction electrode53. For example, the attraction electrode53may be a composite ceramic including aluminum oxide (Al2O3) and a conductive material. The attraction electrode53may include an alumina titanium carbide material (an AlTiC material) as the conductive material. The second plate54may be disposed on the attraction electrode53. The second plate54may cover the attraction electrode53together with the first plate52. An edge portion of a lower surface of the second plate54may contact the first plate52. The second plate54may surround an upper surface and an edge of the attraction electrode53. An upper surface of the second plate54may be flat. For example, the second plate54may include the same material as the first plate52. Although not shown, the second plate54may include a heating layer such as a multi-zone heating plate, similarly to the first plate52. The substrate10may be laid on the upper surface of the second plate54. The upper surface of the second plate54may face the upper electrode30. In an embodiment, the substrate supporting structure50may include a plurality of first channels71and second channels72therein. For example, each first channel71is configured to allow a refrigerant to flow therethrough. The refrigerant may be supplied from a supply source to each first channel71. For example, as the refrigerant, a gas such as helium (He), nitrogen (N2), etc., water, a dedicated organic solvent, etc. may be used. The substrate supporting structure50may cool the substrate10attracted to the upper surface thereof by the refrigerant flowing through the first channels71. For example, each second channel72may be configured to allow helium (He) to flow therethrough. In an embodiment, each first channel71and each second channel72may be disposed in the lower electrode51. In an embodiment, the plurality of first channels71may have the same vertical width (height or thickness). In accordance with embodiments, each first channel71and each second channel72may be formed in the first plate52or the second plate54, or may be formed to extend through the lower electrode51, the first plate52, and the second plate54. In an embodiment, each second channel72may be connected to a channel hole extending through the first plate52, the attraction electrode53, and the second plate54. The channel hole may be exposed to an outside of the substrate supporting structure50at the upper surface of the second plate54. Although not clearly shown, a part of the first channels71may be connected to a discharge hole communicating with a lower side of the lower electrode51. In an embodiment, the substrate supporting structure50may further include a lift pin80extending through the lower electrode51, the first plate52, the attraction electrode53, and the second plate54. The lift pin80includes a function for vertically moving the substrate10disposed on the substrate supporting structure50. The vertical rod21may be disposed at a lower side of the substrate supporting structure50and may support the substrate supporting structure50. The vertical rod21may be disposed to extend through a bottom portion of the chamber20. In an embodiment, the vertical rod21may provide radio-frequency (RF) power to the lower electrode51. In accordance with embodiments, the vertical rod21may be configured to be rotatable. The focus ring61may be disposed on the lower electrode51in the side area EA of the lower electrode51. The focus ring61may be disposed to surround the first plate52and the second plate54at side edges of the first plate52and the second plate54(in the first direction DR1). The focus ring61may have a ring shape surrounding the periphery of the substrate10. For example, the focus ring61may include silicon and may converge plasma toward a surface of the substrate10, thereby enhancing the efficiency of plasma processing. In an embodiment, the focus ring61may be formed to have a greater height than the second plate54. The upper edge ring62may be disposed outside the focus ring61. The upper edge ring62may be disposed to surround the focus ring61. For example, the upper edge ring62may be a machined product including quartz (QTZ). The ground plate65may be disposed at one side (for example, a lower side) of the interior of the chamber20. An isolator64may be disposed between the ground plate65and the lower electrode51. The isolator64may include power supply lines therein. The isolator64may provide an electrical signal to the substrate supporting structure50(for example, the lower electrode51). In an embodiment, the isolator64may contact parts of edge portions of side and lower surfaces of the lower electrode51. In accordance with embodiments, the isolator64may support the lower electrode51. The lower edge ring63may be disposed at a lower side of the upper edge ring62and an outer edge of the isolator64. For example, the lower edge ring63may be a machined product including quartz (QTZ), similarly to the upper edge ring62. FIG.3is a view explaining the concept of an electric field generated from a lower electrode according to an exemplary embodiment of the disclosure.FIG.4is a view explaining a profile in semiconductor processing equipment according to an exemplary embodiment of the disclosure.FIG.5is a view explaining relation between an electric field vector and an ion incidence vector generated from a lower electrode in semiconductor processing equipment according to an exemplary embodiment of the disclosure.FIG.3shows a portion of the processing area PA of the lower electrode30. Each view ofFIG.5is an enlarged view of a portion A ofFIG.4. For convenience of description, a direction opposite to the first direction DR1is defined as a third direction DR3and a direction opposite to the second direction DR2is defined as a fourth direction DR4. That is, although the first direction DR1represents a right side, the second direction DR2an upward side, the third direction DR3a left side, and the fourth direction DR4a downward side, when viewed in the drawings, the first to fourth directions DR1to DR4may be understood as relative directions, without being limited to the above-described conditions. In addition, the first direction DR1and the third direction DR3are defined as corresponding to x-axis components and the second direction DR2and the fourth direction DR4are defined as corresponding to z-axis components. Referring toFIGS.1to5, an electric field, which is generated from the lower electrode51, may be generated in a zone contacting the upper surface of the lower electrode51(the upper surface of the processing area PA) and a zone closely adjacent to the upper surface of the lower electrode51in a direction normal to the upper surface of the lower electrode51. The electric field may be represented by a vector component having both a direction and a magnitude. In the following description, the vector component will be referred to as an “electric field vector ve2”. For example, a plurality of electric field vectors ve2generated from the lower electrode51may be formed in a tilted direction between the first direction DR1and the second direction DR2, in a tilted direction between the third direction DR3and the second direction DR2or in the second direction DR2in a zone contacting the upper surface of the lower electrode51and a zone closely adjacent to the upper surface of the lower electrode51. The electric field generated from the lower electrode51may be formed in a direction gradually approximate to the second direction DR2as the electric field extends gradually from the upper surface of the lower electrode51to a predetermined position. The following description will be given in conjunction with an example in which an ion incidence vector ve1is tilted in a tilted direction between the first direction DR1and the fourth direction DR4in a zone adjacent to a plasma sheath S. In addition, although the ion incidence vector ve1is practically determined by a sum of vectors of three-dimensional components (x, y and z-axis components), the ion incidence vector ve1will be described with reference to vectors of two-dimensional components (x and y-axis components). An ion incidence vector ve1to advance in a z-axis direction (the fourth direction DR4) may be tilted due to non-uniform density of plasma. For example, the direction of the ion incidence vector ve1may be determined by a direction represented by a sum of a vector magnitude in the fourth direction DR4and a vector magnitude in the first direction DR1. In an embodiment, the direction of the electric field vector ve2generated from the lower electrode51may face the ion incidence vector ve1. For example, the z-axis magnitude of an electric field generated from the lower electrode51(for example, a vector component in the second direction DR2) may be smaller than the z-axis magnitude of an ion (for example, a vector component in the fourth direction DR4). In addition, for example, the x-axis magnitude of the electric field generated from the lower electrode51(for example, a vector component in the third direction DR3) may be equal to the x-axis magnitude of the ion (for example, a vector component in the first direction DR1). A final ion incidence vector ve1′ reaching the substrate10may be adjusted in accordance with the following Expression 1: ve1′=ve1+ve2=ve11+ve12+ve21+ve22 [Expression 1] In such a manner, an x-axis component of the ion incidence vector ve1may be offset by an electric field vector ve2generated from the lower electrode51. Although not shown, a y-axis component of the ion incidence vector ve1may also be offset by an electric field vector ve2generated from the lower electrode51in a manner similar to the above-described manner. As a result, only a z-axis component of the ion incidence vector ve1(a component in the fourth direction DR4) may remain. Accordingly, the tilt angle of the final ion incidence vector ve1′ in an x-axis direction and/or a y-axis direction may be minimized That is, the direction of the final ion incidence vector ve1′ may be substantially a z-axis direction (the fourth direction DR4). FIG.6is a flowchart explaining a method for manufacturing semiconductor processing equipment in accordance with an exemplary embodiment of the disclosure.FIGS.7to10are views explaining a part of procedures ofFIG.6. The following description will be given mainly in conjunction with a method for manufacturing the substrate supporting structure50of the semiconductor processing equipment1. Referring toFIGS.6to10, the method for manufacturing the semiconductor processing equipment1may include measuring a plasma sheath using a reference lower electrode (S110), polishing an upper surface of the reference lower electrode such that the upper surface has a shape corresponding to a shape of the plasma sheath (S120), forming a first plate (S130), planarizing an upper surface of the first plate (S140), forming an attraction electrode (S150), and forming a second plate (S160). Operation S110of measuring the plasma sheath using the reference lower electrode corresponds to an operation of measuring a plasma sheath S in the semiconductor processing equipment1, using a reference lower electrode51a. The reference lower electrode51a(a first lower electrode51a) may be the lower electrode51which has a flat upper surface. In accordance with embodiments, the reference lower electrode51amay be an electrode separate from the lower electrode51constituting the substrate supporting structure50. In operation S110of measuring the plasma sheath using the reference lower electrode, it may be possible to measure the plasma sheath S through reference semiconductor processing equipment1aprovided with the reference lower electrode51a. As shown inFIG.8, operation S120of polishing the upper surface of the lower electrode51such that the upper surface has a shape corresponding to the shape of the plasma sheath S corresponds to an operation of polishing an upper surface of a lower electrode51b(a second lower electrode51b). In an embodiment, the second lower electrode51bmay be an electrode different from the first lower electrode51a. In an embodiment, the polishing may include a physical polishing process. In an embodiment, the upper surface of the second lower electrode51bmay be polished such that the upper surface has a shape identical or very similar to the shape of the plasma sheath S. The polishing may be performed at an outside of the chamber20, and the second lower electrode51bin a completely polished state may be manufactured as the lower electrode51according to the exemplary embodiment of the disclosure. Operation S130of forming the first plate corresponds to an operation of forming a first plate material52aon the lower electrode51, as shown inFIG.9. Operation S140of planarizing the upper surface of the first plate corresponds to an operation of polishing an upper surface of the first plate material52asuch that the upper surface becomes flat. The first plate52, which has a flat upper surface, may be disposed on the lower electrode51through the first plate formation operation S130and the planarization operation S140for the upper surface of the first plate. Thereafter, as shown inFIG.10, the substrate supporting structure50may be manufactured through sequential execution of the attraction electrode formation operation S150and the second plate formation operation S160. Thereafter, the substrate supporting structure50manufactured as described above may be disposed in a chamber20of the reference semiconductor processing equipment1aand, as such, the semiconductor processing equipment1may be manufactured. For example, the substrate supporting structure50manufactured as described above is substituted for the reference lower electrode51a, the first plate52, the attraction electrode53and the second plate54installed in the reference semiconductor processing equipment1aand, as such, the semiconductor processing equipment1may be manufactured. Hereinafter, semiconductor processing equipment according to another exemplary embodiment of the disclosure will be described. In the following description, no description will be given of constituent elements identical to those ofFIGS.1to10, and the constituent elements will be designated by reference numerals identical or similar to those ofFIGS.1to10. FIG.11is a schematic side view showing semiconductor processing equipment according to an exemplary embodiment of the disclosure. Referring toFIG.11, semiconductor processing equipment2according to the exemplary embodiment of the disclosure differs from the semiconductor processing equipment1ofFIG.1in that a substrate supporting structure50_1includes a lower electrode51_1having an upper surface with a shape different from that of the lower surface51in the semiconductor processing equipment1. The upper surface of the lower electrode51_1may be a set of planes having a predetermined tilt in a processing area PA. An angle may be formed between adjacent ones of the planes. In an embodiment, the tilt of each of the planes constituting the upper surface of the processing area PA may be 0.01 or less. FIG.12is a schematic side view showing semiconductor processing equipment according to an exemplary embodiment of the disclosure. Referring toFIG.12, semiconductor processing equipment3according to the exemplary embodiment of the disclosure differs from the semiconductor processing equipment1ofFIG.1in that the semiconductor processing equipment3includes first channels71_1having different vertical widths. In an embodiment, the first channels71_1may have different vertical widths (heights or thicknesses) in accordance with positions thereof due to a curved shape of a processing area PA in a lower electrode51. For example, the vertical width of each first channel71_1may be set to be proportional to a thickness of the lower electrode51at a position where the first channel71_1is disposed. FIG.13is a schematic side view showing semiconductor processing equipment according to an exemplary embodiment of the disclosure. Referring toFIG.13, semiconductor processing equipment4according to the exemplary embodiment of the disclosure differs from the semiconductor processing equipment1ofFIG.1in that, in a substrate supporting structure50_2, an upper surface of a first plate52_1thereof is curved, an attraction electrode53_1thereof is curved, and a lower surface of a second plate54_1thereof is curved corresponding to the attraction electrode53_1. In an embodiment, in a method for manufacturing the semiconductor processing equipment4, operation S140(FIG.6) of planarizing the upper surface of the first plate52_1may be omitted. Accordingly, an upper surface of the second plate54_1may have a shape curved corresponding to the shape of the upper surface of the first plate52_1(a processing area PA). As such, the attraction electrode53_1may have a shape curved corresponding to the shape of the upper surface of the first plate52_1. Accordingly, the lower surface of the second plate54_1may have a shape curved corresponding to the shape of the attraction electrode53_1and the shape of the upper surface of the first plate52_1. FIG.14is a schematic side view showing semiconductor processing equipment according to an exemplary embodiment of the disclosure. Referring toFIG.14, semiconductor processing equipment5according to the exemplary embodiment of the disclosure differs from the semiconductor processing equipment1ofFIG.1in that an upper surface of a second plate54_2is not flat. In an embodiment, embossing may be performed for the upper surface of the second plate54_2. As such, the second plate54_2may include a plurality of protrusions EB at the upper surface thereof. A substrate10may be laid on the protrusions EB of the substrate supporting structure50_3. In accordance with the exemplary embodiments of the disclosure, ion tilting in plasma processing may be minimized. As is traditional in the field, embodiments may be described and illustrated in terms of blocks which carry out a described function or functions. These blocks, which may be referred to herein as units or modules or the like, are physically implemented by analog and/or digital circuits such as logic gates, integrated circuits, microprocessors, microcontrollers, memory circuits, passive electronic components, active electronic components, optical components, hardwired circuits and the like, and may optionally be driven by firmware and/or software. The circuits may, for example, be embodied in one or more semiconductor chips, or on substrate supports such as printed circuit boards and the like. The circuits constituting a block may be implemented by dedicated hardware, or by a processor (e.g., one or more programmed microprocessors and associated circuitry), or by a combination of dedicated hardware to perform some functions of the block and a processor to perform other functions of the block. Each block of the embodiments may be physically separated into two or more interacting and discrete blocks without departing from the scope of the disclosure. Likewise, the blocks of the embodiments may be physically combined into more complex blocks without departing from the scope of the disclosure. An aspect of an embodiment may be achieved through instructions stored within a non-transitory storage medium and executed by a processor. While the embodiments of the disclosure have been described with reference to the accompanying drawings, it should be understood by those skilled in the art that various modifications may be made without departing from the scope of the disclosure and without changing essential features thereof. Therefore, the above-described embodiments should be considered in a descriptive sense only and not for purposes of limitation. | 29,712 |
11862441 | DETAILED DESCRIPTION In the following detailed description, reference is made to the accompanying drawings, which form a part hereof. The illustrative embodiments described in the detailed description, drawings, and claims are not meant to be limiting. Other embodiments may be utilized, and other changes may be made without departing from the spirit or scope of the subject matter presented here. Hereinafter, the disclosed embodiments will be described in detail with reference to drawings. The embodiments are not limited. In addition, the embodiments may be properly combined in a range where processing contents do not contract with each other. In the drawings, the same or corresponding parts will be denoted by the same reference numerals. In the following description, the “pattern” refers to the entire shape formed on a substrate. The pattern refers to all of the plurality of shapes formed on the substrate, such as, for example, a hole, a trench, and a line and space. In addition, the “recess” refers to a portion of a shape recessed in a thickness direction of the substrate, in the pattern formed on the substrate. In addition, he recess has a “side wall” as an inner peripheral surface of the recessed shape, a “bottom” as a bottom portion of the recessed shape, and a “top” that is a substrate surface continuous to the side wall, near the side wall. In addition, a space surrounded by the top is called an “opening.” The term “opening” is also used to refer to the entire space surrounded by the bottom and the side wall of the recess, or any position of the space. It is known that a shape abnormality is likely to occur when a deep hole having a high aspect ratio, such as a high aspect ratio contact (HARC), is formed. For example, a shape abnormality called bowing is known. The bowing is a shape abnormality in which when an opening is formed in a vertical direction, the inner peripheral surface of the opening bulges in a barrel shape in a lateral direction. In the embodiment, a film is formed on the side wall of the opening in order to suppress the occurrence of the shape abnormality such as bowing. Examples of the film formation method include atomic layer deposition (ALD), plasma-enhanced ALD (PEALD), chemical vapor deposition (CVD), plasma-enhanced CVD (PECVD), and plasma enhanced cyclic chemical vapor deposition (PECCVD). (Configuration Example of Plasma Processing System According to Embodiment) FIG.1is a view illustrating an example of a plasma processing system that may be used to carry out plasma processing according to the embodiment. A plasma processing system1000illustrated inFIG.1includes a controller Cnt, a stage1122a,a stage1122b,a stage1122c,a stage1122d,a storage container1124a,a storage container1124b,a storage container1124c,a storage container1124d, a loader module LM, a load lock chamber LL1, a load lock chamber LL2, a transfer chamber1121, and a plasma processing apparatus1010. The plasma processing apparatus1010may be, for example, a plasma processing apparatus1illustrated inFIG.2. The controller Cnt is a computer including, for example, a processor, a storage, an input device, and a display device, and controls each of units (to be described later) in the plasma processing system1000. The controller Cnt is connected to, for example, a transfer robot Rb1, a transfer robot Rb2, an observation device OC, and the plasma processing apparatus1010. The controller Cnt may also double as a controller100of the plasma processing apparatus1illustrated inFIG.2. The controller Cnt sends out control signals by operating according to a computer program (a program based on an input recipe) for controlling each of units of the plasma processing system1000. By the control signals from the controller Cnt, each of units of the plasma processing system1000, for example, the transfer robots Rb1and Rb2, and the observation device OC, and each of units of the plasma processing apparatus1010are controlled. In the plasma processing apparatus1010, according to the control signals from the controller Cnt, it is possible to control the selection and the flow rate of a gas to be supplied from a gas supply source15, the exhaust of an exhaust device65, the power supply from radio-frequency power supplies32and34, and the coolant flow rate and the coolant temperature. Each process of a substrate processing method according to the first and second embodiments may be executed when each of units of the plasma processing system1000is operated under the control by the controller Cnt. In the storage of the controller Cnt, a computer program for executing a plasma processing method according to the embodiment, and various data used for execution are stored in a readable manner. The stages1122ato1122dare arranged along one edge of the loader module LM. The storage containers1124ato1124dare provided on the stages1122ato1122d, respectively. Wafers W may be accommodated in the storage containers1124ato1124d. The transfer robot Rb1is provided in the loader module LM. The transfer robot Rb1takes out a wafer W accommodated in any one of the storage containers1124ato1124d,and transports the wafer W to the load lock chamber LL1or LL2. The load lock chambers LL1and LL2are provided along another edge of the loader module LM, and are connected to the loader module LM. The load lock chambers LL1and LL2constitute a preliminary decompression chamber. The load lock chambers LL1and LL2are individually connected to the transfer chamber1121. The transfer chamber1121is a chamber capable of being depressurized, and the transfer robot Rb2is provided in the transfer chamber1121. The plasma processing apparatus1010is connected to the transfer chamber1121. The transfer robot Rb2takes out the wafer W from the load lock chamber LL1or the load lock chamber LL2, and transports the wafer W to the plasma processing apparatus1010. The plasma processing system1000includes the observation device OC. The observation device OC may be provided at any location in the plasma processing system1000. As an example, the observation device OC is provided in an observation module OM adjacent to the loader module LM. The wafer W may be moved by the transfer robot Rb1and the transfer robot Rb2, between the observation module OM and the plasma processing apparatus1010. After the wafer W is accommodated in the observation module OM by the transfer robot Rb1, and the alignment of the wafer W is performed in the observation module OM, the observation device OC measures a groove width of, for example, a mask pattern on the wafer W, and transmits the measurement result to the controller Cnt. In the observation device OC, the groove width of, for example, a mask pattern formed on a plurality of regions of the top surface of the wafer W may be measured. The result of measurement by the observation device OC is used as, for example, a “detection result” in the embodiment to be described later (seeFIGS.11A and11B). As for the observation device OC, for example, an optical observation device, a weight scale, and an ultrasonic microscope may be used. (Configuration Example of Plasma Processing Apparatus According to Embodiment) The plasma processing apparatus1according to the embodiment of the present disclosure will be described with reference toFIG.2.FIG.2illustrates a vertical cross section of an example of the configuration of the plasma processing apparatus1according to the embodiment. The plasma processing apparatus1according to the embodiment is a parallel plate type plasma processing apparatus (a capacitively coupled plasma processing apparatus) in which a stage20and a gas shower head25are disposed while facing each other in a processing container10. The stage20has a function of holding a semiconductor substrate (hereinafter, simply referred to as a “wafer W”) and functions as a lower electrode. The gas shower head25has a function of supplying a gas into the processing container10, in a shower form, and functions as an upper electrode. The processing container10is cylindrical and is made of, for example, aluminum whose surface has been subjected to an alumite treatment (an anodizing treatment). The processing container10is electrically grounded. The stage20is provided on the bottom of the processing container10, and on the stage20, the wafer W is placed. The wafer W is an example of a substrate as a plasma processing target. The stage20is made of, for example, aluminum (Al), titanium (Ti), or silicon carbide (SiC). On the top surface of the stage20, an electrostatic chuck106is provided to electrostatically attract the substrate. The electrostatic chuck106has a structure in which a chuck electrode106ais interposed between insulators106b. A DC voltage source112is connected to the chuck electrode106a,and a DC current is supplied from the DC voltage source112to the chuck electrode106a. Accordingly, the wafer W is attracted to the electrostatic chuck106by a Coulomb force. On the electrostatic chuck106, an annular focus ring103is placed while surrounding the periphery of the wafer W. The focus ring103includes a conductive member, for example, silicon, and causes plasma to converge toward the top surface of the wafer W in the processing container10so as to improve the efficiency of etching. The stage20is supported by a support104. A coolant flow path104ais formed inside the support104. A coolant inlet pipe104band a coolant outlet pipe104care connected to the coolant flow path104a.A cooling medium, such as, for example, cooling water or brine, output from a chiller107circulates through the coolant inlet pipe104b,the coolant flow path104aand the coolant outlet pipe104c. Accordingly, the stage20and the electrostatic chuck106are cooled. A heat transfer gas supply source85supplies a heat transfer gas such as helium gas (He) or argon gas (Ar) to the back surface of the wafer W on the electrostatic chuck106through a gas supply line130. Through such a configuration, the temperature of the electrostatic chuck106is controlled by the cooling medium circulating through the coolant flow path104a,and the heat transfer gas supplied to the back surface of the wafer W. As a result, the substrate may be controlled to a predetermined temperature. The first radio-frequency power supply34is electrically connected to the gas shower head25via a matcher35. The first radio-frequency power supply34applies radio-frequency power (HF) for plasma excitation of, for example, 60 MHz, to the gas shower head25. In the embodiment, the radio-frequency power (HF) is applied to the gas shower head25, but may be applied to the stage20. The second radio-frequency power supply32is electrically connected to the stage20via a matcher33. The second radio-frequency power supply32applies radio-frequency power (LF) for bias of, for example, 13.56 MHz, to the stage20. The matcher35matches a load impedance to an internal (or output) impedance of the first radio-frequency power supply34. The matcher33matches a load impedance to an internal (or output) impedance of the second radio-frequency power supply32. The matcher35and the matcher33function such that when plasma is generated in the processing container10, the load impedances and the internal impedances of the first radio-frequency power supply34and the second radio-frequency power supply32are seemingly matched. The gas shower head25includes a ceiling electrode plate41having many gas supply holes55and a cooling plate42on which the ceiling electrode plate41is detachably hung and supported. The gas shower head25is attached while closing the opening of a ceiling of the processing container10via a shield ring40that covers the periphery of the gas shower head25. A gas introduction port45that introduces a gas is formed in the gas shower head25. A center-side diffusion chamber50aand an edge-side diffusion chamber50bdiverging from the gas introduction port45are provided in the gas shower head25. A gas output from the gas supply source15is supplied to the diffusion chambers50aand50bthrough the gas introduction port45, is diffused in each of the diffusion chambers50aand50b,and is introduced from the many gas supply holes55toward the stage20. An exhaust port60is formed on the bottom surface of the processing container10, and the inside of the processing container10is exhausted by the exhaust device65connected to the exhaust port60. Accordingly, the inside of the processing container10may be maintained at a predetermined degree of vacuum. A gate valve G is provided on the side wall of the processing container10. By opening/closing of the gate valve G, the wafer W is loaded and unloaded into/from the processing container10. An optical sensor108capable of measuring the intensity of light of each wavelength in plasma in the processing container10, through a quartz window109, is attached to the plasma processing apparatus1. The optical sensor108includes a first sensor108aand a second sensor108b.The first sensor108adetects the state of plasma generated in the processing container10. The detection result of the first sensor108ais used in a monitoring process and a determination process (to be described later). In addition, the second sensor108bdetects a pattern shape on the top surface of the wafer W placed on the stage20. The detection result of the second sensor108bis used in first to third detection processes (to be described later). The plasma processing apparatus1is provided with the controller100that controls operations of the entire apparatus. The controller100includes a central processing unit (CPU)105, a read only memory (ROM)110and a random access memory (RAM)115. The CPU105executes desired processes such as a film formation process, a monitoring process, a determination process, an etching process and first to third detection processes (to be described later) according to various recipes stored in these storage areas. In the recipes, for example, a process time, a pressure (exhaust of a gas), a radio-frequency power or a voltage, various gas flow rates, temperatures in the processing container10(for example, an upper electrode temperature, a side wall temperature of the processing container, and an electrostatic chuck temperature), and a temperature of the chiller107are described as apparatus control information related to process conditions. These recipes illustrating processing conditions or programs may be stored in a hard disk or a semiconductor memory. In addition, the recipes may be set at a predetermined position of a storage area while accommodated in a portable computer-readable storage medium such as a CD-ROM or a DVD. The controller100executes a monitoring process (to be described later) of causing the first sensor108ato monitor the plasma state in the processing container10. In addition, the controller100executes a determination process (to be described later) of determining whether the re-execution of a film formation process is required based on the detection result of the first sensor108aand determining a processing condition at the time of re-execution. In addition, the controller100performs first to third detection processes (to be described later) by detecting the pattern shape of the wafer W based on the detection result of the second sensor108b. At the time of plasma processing, the opening/closing of the gate valve G is controlled, and the wafer W is loaded into the processing container10and is placed on the stage20. A DC current is supplied from the DC voltage source112to the chuck electrode106a,so that the wafer W is attracted to and held by the electrostatic chuck106due to a Coulomb force. Subsequently, a gas for plasma processing, radio-frequency power (HF) for plasma excitation, and radio-frequency power (LF) for bias are supplied into the processing container10to generate plasma. Plasma processing (for example, film formation and etching) is performed on the wafer W by the generated plasma. After the plasma processing, a DC voltage (HV) having a positivity or a negativity opposite to that at the time of attraction of the wafer W is applied from the DC voltage source112to the chuck electrode106aso as to remove electric charges of the wafer W, and separate the wafer W from the electrostatic chuck106. The opening/closing of the gate valve G is controlled so that the wafer W is unloaded from the processing container10. (ALD and Sub-Conformal ALD) In the embodiment, as for a film formation process, a process using plasma is executed. The film formation process is not particularly limited as long as it is a process using plasma. For example, as described above, the PEALD, the PECVD, and the PECCVD may be used. First, ALD and sub-conformal ALD will be described with reference toFIG.3toFIGS.5A to5C.FIG.3is a flow chart illustrating the schematic flow of plasma processing according to the embodiment. The processing flow illustrated inFIG.3is common to the case of ALD and the case of sub-conformal ALD.FIGS.4A to4Dare views for explaining an example of the flow of the sub-conformal ALD.FIGS.5A to5Care views for explaining another example of the flow of the sub-conformal ALD. First, a wafer W on which a pattern is formed is provided in the processing container10(step S11). The wafer W is automatically loaded from the gate valve G by the transfer robot Rb2. Then, a first gas (also called a precursor) is introduced from the gas supply source15to the processing container10where the wafer W is disposed (step S12). A first component contained in the first gas is adsorbed on the top surface of the wafer W. Then, the inside of the processing container10is exhausted (purged) by the exhaust device65(step S13). Next, a second gas (also called a reaction gas) containing a second component that reacts with the first component is introduced from the gas supply source15to the processing container10to generate plasma of the second gas (step S14). The second component forms a film by reacting with the first component on the wafer W. Then, the inside of the processing container10is exhausted again by the exhaust device65(step S15). The controller100causes each of units to further execute a process such as etching after the film formation in steps S12to S15(step S16). Then, the controller100ends the process in each of units of the plasma processing apparatus1. Herein, descriptions have been made to the effect that each process is executed in one plasma processing apparatus1. Meanwhile, when the plasma processing system1000includes a plurality of plasma processing apparatuses1010, the film formation process and the etching process may be executed in different plasma processing apparatuses1010. In the ALD, a predetermined component is adsorbed and is reacted on/with a substance pre-existing on the substrate surface in a self-control manner so as to form a film. Thus, in the ALD, a sufficient processing time is generally provided, and thus conformal film formation is realized. In the case ofFIG.3, a sufficient long processing time is set for step S12and step S14. That is, processing conditions in step S12and step S14are set as saturation conditions. Accordingly, the adsorption of the first gas component on the wafer W, and the reaction between the first gas component and the second gas component reach saturation on the top surface of the wafer W so that a conformal film is formed. The conformal film is a film having a uniform thickness regardless of the position on the wafer W (for example, the position in the vertical direction). Whereas, in the sub-conformal ALD, the same process procedure as that in the ALD is used, while a control is performed such that at least one of adsorption and reaction of the film formation components does not reach saturation. That is, in the sub-conformal ALD, the same process procedure as that in the ALD is used, while the self-controlling adsorption or reaction on the top surface of the wafer W is not completed so that a sub-conformal film is formed. The sub-conformal film is a film whose film thickness varies according to the position on the wafer W (for example, the position in the vertical direction). At least the following two modes are present as processing modes of the sub-conformal ALD. (1) A precursor is adsorbed on the entire surface of the wafer W. A reaction gas introduced thereafter is controlled so as not to spread throughout the entire surface of the wafer W. (2) A precursor is adsorbed on only a part of the surface of the wafer W. A reaction gas introduced thereafter forms a film only on a portion of the surface on which the precursor is adsorbed. By using the method (1) or (2), it is possible to form a film whose thickness is gradually decreased from top to bottom, on the side wall of the pattern formed on the wafer W. A wafer W illustrated inFIGS.4A to4Dincludes an etching target film EL1, and a mask MA. A recess having an opening OP is formed in the stack of the etching target film EL1and the mask MA. First, the wafer W is provided in the processing container10(step S11inFIG.3). Then, a precursor P is introduced into the processing container10in which the wafer W is disposed (FIG.4A, and step S12inFIG.3). A sufficient processing time is provided to adsorb the precursor P so that the precursor P is adsorbed on the entire surface of the wafer W (FIG.4B). When the adsorption of the precursor P is completed, the inside of the processing container10is purged. Next, a reaction gas R is introduced into the processing container10(FIG.4C, and step S14inFIG.3). The introduced reaction gas R reacts with the precursor P on the wafer W and gradually forms a film F from the top side of the mask MA. Here, before the formation of the film F reaches the bottom side of the etching target film EL1, the reaction gas R is purged. Through a process performed in this manner, in using the ALD method, the film F may not be formed on the entire side wall of the recess, and may be formed only on the upper portions of the mask MA and the etching target film EL1(FIG.4D). InFIG.4D, the film F is formed on the upper portion and the top of the side wall of the recess, and is not formed on the lower portion and the bottom of the side wall. Next, the second method will be described with reference toFIGS.5A to5C. The wafer W illustrated inFIGS.5A to5Chas the same shape as the wafer W inFIGS.4A to4D. In the example ofFIGS.5A to5C, the precursor P is adsorbed only on the upper portion of the wafer W (FIG.5A). After the precursor P is purged, the reaction gas R is introduced to the processing container10(FIG.5B). Here, since the reaction gas R forms a film through a reaction only at the location where the precursor P is adsorbed, the film F is formed only on the upper portion of the pattern of the wafer W (FIG.5C). (Processing Conditions for Selective Adsorption and Reaction) FIGS.4A to4Dcorrespond to a case where step S14inFIG.3is executed under unsaturation conditions. In addition,FIGS.5A to5Ccorrespond to a case where step S12inFIG.3is executed under unsaturation conditions. When the processing time in step S12and step S14is sufficiently long, the formed film becomes conformal rather than sub-conformal. Thus, in the sub-conformal ALD, processing conditions are set such that at least one of adsorption and reaction of the film formation components does not reach saturation. Processing parameters to be adjusted to realize the sub-conformal ALD are, for example, the temperature of the stage20on which the wafer W is placed, the pressure in the processing container10, the flow rate and the introduction time of the precursor to be introduced, the gas flow rate and the introduction time of the reaction gas to be introduced, and the processing time. In addition, in the case of a process using plasma, the film formation position may also be adjusted by adjusting the value of radio-frequency (RF) power to be applied for plasma generation. In the case of the process inFIG.3, the second gas is formed into plasma in step S14, but the first gas of step S12may also be formed into plasma. (Example of Flow of Plasma Processing Method According to Embodiment) FIG.6is a flow chart for further explaining a plasma processing method according to the embodiment. In the plasma processing method according to the embodiment, the state of plasma generated during a film formation process (steps S12to S15inFIG.3) is monitored so as to realize highly accurate determination on the ending timing of the film formation process. First, a wafer W is provided in the processing container10(step S61). A pattern is formed on the wafer W in advance. For example, the same recess as those inFIGS.4A to4D, andFIGS.5A to5Cis formed. When both the etching and the film formation may be executed in the plasma processing apparatus1, the formation of the recess may also be executed in the plasma processing apparatus1. Next, the plasma processing apparatus1executes a first detection process (step S62). The first detection process is a process in which the pattern shape on the wafer W is detected by the second sensor108bor the observation device OC, so that the controller100determines processing conditions of a subsequent film formation process (step S63) based on the detection result. The pattern shape includes, for example, the aspect ratio of a recess or a surface profile. The first detection process may be performed at any time before or after the process of providing the wafer W (step S61) as long as the time is prior to the film formation process (step S63). The processing conditions of the film formation process (step S63) include, for example, the introduction amount of a first gas, the introduction amount of a second gas, a reaction time between the first gas and the second gas, a purging time, and the number of cycles. The first detection process will be described later. The controller100sends an instruction to each of units of the plasma processing apparatus1based on the processing conditions determined by the first detection process, to start the film formation process (step S63). First, the controller100introduces the first gas from the gas supply source15into the processing container10(step S631). When the processing time determined by the processing conditions has elapsed, the controller100ends the introduction of the first gas. The first gas is adsorbed on the top surface of the wafer W on the stage20. Next, the controller100controls the exhaust device65to purge the gas in the processing container10(step S632). Next, the controller100introduces the second gas from the gas supply source15into the processing container10(step S633). The controller100also applies radio-frequency power (HF) for plasma excitation from the first radio-frequency power supply34to the gas shower head25. The controller100also applies radio-frequency power (LF) from the second radio-frequency power supply32to the stage20. The radio-frequency power (HF) may also be applied to the stage20. Due to application of the radio-frequency power (LF, HF), plasma of the second gas is generated in the processing container10. Then, when the processing time based on the processing conditions determined by the first detection process has elapsed, the controller100ends the introduction of the second gas and the plasma generation. A component contained in the plasma of the second gas reacts with a component of the first gas on the top surface of the wafer W so as to form a film on the top surface of the wafer W. In parallel with the introduction of the second gas, the controller100executes a monitoring process (step S64A). The monitoring process is a process in which the first sensor108amonitors the plasma state in the processing container10, and the monitoring result is transmitted to the controller100, and is stored. Details of the monitoring process will be described later. Next, the controller100controls the exhaust device65to purge the gas in the processing container10(step S634). Accordingly, one cycle of the film formation process (step S63) is completed. Next, the controller100executes a determination process (step S64B) based on the monitoring result of the monitoring process (step S64A). The determination process is a process in which the controller100determines a subsequent process and processing conditions based on the monitoring result transmitted from the first sensor108a.The determination process may be executed for each cycle of the film formation process (step S63), or may be executed after the film formation process (step S63) is performed for a predetermined number of cycles. In the determination process, the controller100determines whether to re-execute the film formation process. In addition, when it is determined that the film formation process is to be re-executed, the controller100determines whether to repeat the process from the introduction of the first gas (step S631), or to repeat the process from the introduction of the second gas (step S633). In addition, when it is determined to re-execute the film formation process, the controller100selects processing conditions for the film formation process (step S63). InFIG.6, the determination process (step S64B) is executed after purging (step S634), but the determination process (step S64B) may be executed before purging or in parallel with purging. The controller100continues the process based on the determination result in the determination process. When it is determined to perform repetition from step S631(step S64B, repeat S631), the controller100repeats the above-described process in steps S631to S634. Meanwhile, when it is determined to perform repetition from step S633(step S64B, repeat S633), the controller100repeats the above-described process in steps S633to S634. In addition, when it is determined not to re-execute the film formation process (step S64B, no re-execution), the controller100proceeds to a second detection process (step S65). Similarly to the first detection process, the second detection process is a process in which the pattern shape on the wafer W is detected by the second sensor108bor the observation device OC, so that based on the detection result, the controller100determines a subsequent process (the film formation process (step S63) or the etching (step S66)) and processing conditions. The processing conditions of the etching (step S66) include, for example, the introduction amount of an etching gas, radio-frequency power, and a substrate temperature. The second detection process will be described later. When it is determined to re-execute the film formation process in the second detection process (step S65, re-execute), the controller100returns to step S63and repeats the process. Meanwhile, when it is determined not to re-execute the film formation process in the second detection process (step S65, no re-execution), the controller100executes etching under the determined processing conditions (step S66). Here, as in the case of the introduction of the second gas, the controller100may simultaneously execute the monitoring process. When the etching is ended, the controller100executes a third detection process (step S67). Similarly to the first and second detection processes, the third detection process is a process in which the pattern shape on the wafer W is detected by the second sensor108bor the observation device OC, so that based on the detection result, the controller100determines a subsequent process and processing conditions. The third detection process will be described later. When it is determined to re-execute the film formation process in the third detection process (step S67, re-execute film formation), the controller100returns to step S63and repeats the process. In addition, when it is determined to re-execute the etching process in the third detection process (step S67, re-execute etching), the controller100returns to step S66and repeats the process. Meanwhile, when it is determined to re-execute neither the film formation process nor the etching process in the third detection process (step S67, no re-execution), the controller100ends the process. Accordingly, the plasma processing of the embodiment is ended. (Monitoring Process/Determination Process) Next, the monitoring process in step S64A and the determination process in step S64B will be described.FIG.7is a flow chart for explaining the monitoring process and the determination process according to the embodiment. In the plasma processing according to the embodiment, in the monitoring process, the controller100monitors the state of the plasma generated during the film formation process. Then, based on the result of the monitoring process, the controller100executes the determination process of determining the ending timing of the film formation process. As described above, the monitoring process (step S64A) is executed in parallel with the process of introducing the second gas into the processing container10and forming the second gas into plasma, in the film formation process (step S63). Here, it is assumed that the monitoring process is started at a point in time when the processing of one wafer W is started. When the processing of the wafer W is started, the controller100causes the first sensor108ato start the monitoring process. When the second gas is introduced into the processing container10and step S633is started, the first sensor108adetects the plasma state in the processing container10(step S71). The timing when the first sensor108astarts to operate is not particularly limited, and the controller100may control the first sensor108abased on the processing recipe of the wafer W such that the processing is started. In the monitoring process, the first sensor108amonitors, for example, the amount of radicals generated by the plasma generation of the second gas. By the way, the coverage of the film formed on the pattern in the film formation process is determined by the temperature in the processing container10, the aspect ratio of the pattern as a processing target, and the dose amount of radicals generated in the processing container10. In the film formation process of the embodiment, the temperature in the processing container10is controlled by the predetermined processing condition, and the aspect ratio of the pattern may be derived from a design value in advance. Thus, if it is possible to know the dose amount of radicals during the film formation process, the coverage of the film to be formed by the film formation process may be estimated. Here, the coverage indicates the state of the film, including the thickness and the position of the formed film. For example, the coverage means a change in the film thickness according to the aspect ratio. The amount of radicals included in the plasma may be estimated from, for example, an electron density, and an ion density of the plasma. Therefore, although the amount of radicals is not directly monitored, another physical quantity indicating the plasma state only has to be monitored. The physical quantities indicating the plasma state may include, for example, an electron density, an ion density, a molecular⋅radical density, and an atomic⋅molecular ion mass. These physical quantities indicating the plasma state may be measured by, for example, spectroscopy (including those using laser), or an interference⋅reflection method. As for the spectroscopy, emission spectroscopy for measuring, for example, a radiant flux, an emission spectrum intensity, or a continuous spectrum intensity may be used. In addition, absorption spectroscopy such as a total absorption method, a self-absorption method, or a hook method may be used. In addition, spectroscopy using laser may be used. For example, a laser organic fluorescence method, a laser absorption spectroscopy, and a laser scattering method may be used. In addition, a microwave interferometry/reflection method, a laser interferometry/polarization method, or a Schlieren/shadow graph method may be used. The first sensor108ais a detection device capable of monitoring the physical quantity indicating the plasma state. As long as the physical quantity indicating the plasma state can be monitored, a specific configuration of the first sensor108ais not particularly limited. For example, as for the first sensor108a,an emission spectroscopic (Optical Emission Spectroscopy: OES) sensor may be used. In addition, as for the first sensor108a,an ultra-high resolution image sensor may be used. Then, information acquired by the first sensor108a,for example, an image, may be analyzed by the controller100so that the physical quantity may be calculated. The first sensor108amonitors the physical quantity indicating the state of plasma generated during the process in step S633, and transmits the monitoring result to the controller100. The controller100stores the received monitoring result in association with the timing. The controller100determines whether the film formation process (steps S631to S634) has ended (step S72). When it is determined that the film formation process has not ended (step S72, No), the controller100returns to step S71, and continues the monitoring process by the first sensor108a.Meanwhile, when it is determined that the film formation process has ended (step S72, Yes), the controller100proceeds to step S73and executes the determination process. (Determination Process) In the determination process, the controller100calculates the integrated value on the physical quantity at each timing which is obtained by the monitoring process. The physical quantity obtained by the monitoring process is stored in the controller100in association with the timing.FIG.8is a view for explaining the monitoring result obtained in the monitoring process according to the embodiment. In the example ofFIG.8, it is assumed that the first sensor108amonitors the amount of radicals in the plasma at every predetermined time (t1, t2, t3. . . ) and sends the amount as a numerical value to the controller100. Here, the monitored amount of radicals changes while the curve inFIG.8is drawn. The controller100calculates the integrated value of the monitoring results from the processing start of the wafer W to that point in time. In the example ofFIG.8, the controller100calculates the total value of S1, S2, S3. . . . Next, the controller100determines whether the calculated integrated value is equal to or greater than a predetermined value (step S73). Here, the “predetermined value” is calculated in advance as an amount of radicals required until a desired coverage is reached, based on the aspect ratio of the pattern on the wafer W, the temperature in the processing container10, and the desired coverage. When it is determined that the calculated integrated value is equal to or greater than the predetermined value (step S73, Yes), the controller100ends the film formation process (step S74). That is, in step S64B ofFIG.6, the controller100proceeds to the branch of “no re-execution,” and then executes step S65. Meanwhile, when it is determined that the calculated integrated value is less than the predetermined value (step S73, No), the controller100determines processing conditions for re-execution of the film formation process (step S75). The determined processing conditions may include processing times at the time of re-execution of steps S631and S633. For example, from the integrated value calculated in step S73, if the processing times of steps S631and S633to be subsequently executed are set to have the same lengths as those in the previous time, in the case where a desired coverage is exceeded, the controller100sets short processing times for steps S631and S633. In addition, the determined processing conditions may include a determination on whether to start the re-execution from step S631or from step S633. Then, the controller100re-executes the film formation process under the determined processing conditions (step S76). Then, the controller100proceeds to step S631or step S633according to the determined processing conditions. Since the controller100determines the degree of progress of the film formation process of the wafer W by the integrated value, for example, in the case where the plasma processing apparatus1is forcibly ended during the processing, it is possible to determine processing conditions subsequent to the recovery of the plasma processing apparatus1. (Monitoring Method Example 1 of First Sensor108a) By the way, the first sensor108amay monitor the plasma state on a basis of a point, a plane, or a three-dimension. Next, examples of a monitoring method in the monitoring process will be described. In Method Example 1 of detecting a physical quantity in the monitoring process according to the embodiment, when the first sensor108ais disposed on the side surface of the processing container10as illustrated inFIG.2, an image obtained by monitoring the plasma state on a basis of a plane in the direction of the side surface of the processing container10is used. The first sensor108ais, for example, an ultra-high resolution image sensor. In Method Example 1, plasma is displayed as a whitish object which is gradually diffused in the processing space with the lapse of time, in the obtained image. The diffusion or the intensity of the plasma corresponds to saturation or brightness of the white portion in the image. Thus, the controller100may acquire the value indicating the plasma state by analyzing the brightness or the saturation of the white portion in the obtained image. The first sensor108atransmits the acquired image to the controller100. The controller100analyzes the received image, and performs calculation of converting the plasma state into a numerical value based on, for example, the saturation or the brightness of the image. Then, the integrated value of the calculated numerical values is compared to a predetermined threshold value (the “predetermined value” inFIG.7). Through a process performed in this manner, the controller100may estimate the film formation state on the wafer W, and determine the ending timing of the film formation process based on the plasma state in the vicinity of the wafer W placed in the processing container10. (Monitoring Method Example 2 of First Sensor108a) In addition, unlike that illustrated inFIG.2, the first sensor108amay be disposed not to monitor the processing space in the vicinity of the wafer W in the lateral direction of the processing container10but to perform monitoring from above the processing container10downwards.FIG.9Ais a view for explaining Method Example 2 of detecting a physical quantity in the monitoring process according to the embodiment. As illustrated inFIG.9A, in Method Example 2, the first sensor108amonitors the entire surface of the wafer W from above. In the image illustrated inFIG.9A, a portion R1having a relatively large amount of radicals is displayed as a dark pattern, and a portion R2having a relatively small amount of radicals is displayed as a light pattern. The first sensor108aacquires such an image at every predetermined time (for example, every 50 nanoseconds). Then, the first sensor108atransmits the acquired image to the controller100. The controller100analyzes the image received from the first sensor108a,and digitizes the shade of a color corresponding to the amount of radicals.FIG.9Bis a view illustrating an example in which the image obtained by Method Example 2 ofFIG.9Ais digitized. In the example illustrated inFIG.9B,1,2, and3as digitized values of color shades are displayed at positions corresponding to the regions (R1and R2) inFIG.9A. First, the controller100divides a region including the plane of the wafer W into a plurality of regions having uniform areas. Then, an image corresponding to each region is analyzed and is digitized. Accordingly, the controller100may obtain the integrated value of values indicating the plasma state in each region for each image. As illustrated inFIG.9AandFIG.9B, when the plane of the wafer W is divided into a plurality of regions and a numerical value indicating the plasma state of each region is obtained, the controller100may determine the film formation state at each in-plane position of the wafer W. Thus, the controller100may also use the result of the monitoring process in improving the in-plane uniformity of the plasma processing. For example, according to the result of the monitoring process, the controller100may adjust the radio-frequency power to be applied to the stage20and the gas shower head, among processing conditions for a subsequent process, to different values depending on the in-plane position. FIG.10is a flow chart illustrating an example of the flow of the monitoring process based on Method Example 2 inFIG.9AandFIG.9B. In the example ofFIG.10, first, when the monitoring process is started, the first sensor108astarts to monitor the plasma state, and the acquired information is transmitted to the controller100and is stored (step S1101). Here, the first sensor108amonitors the entire surface of the wafer W. The controller100analyzes the received information, for example, an image, and calculates a numerical value indicating the plasma state for each of preliminary set regions (step S1102). Then, for each of the regions, the controller100calculates an integrated value in the film formation process executed until now, based on the calculated numerical values (step S1103). The controller100calculates a difference in the calculated integrated value between the regions (step S1104). Next, the controller100determines whether the integrated value calculated in step S1103is equal to or greater than a predetermined value (step S1105). Then, when it is determined that the integrated value is equal to or greater than the predetermined value (step S1105, Yes), the controller100determines whether the difference calculated in step S1104is equal to or lower than a predetermined value (step S1106). Then, when it is determined that the difference is equal to or lower than the predetermined value (step S1106, Yes), the controller100ends the film formation process (step S1107). Then, the controller100proceeds to step S65. Meanwhile, when it is determined that the integrated value calculated in step S1103is less than the predetermined value (step S1105, No), the controller100determines processing conditions for re-executing the film formation process (step S1108). Then, the film formation process based on the determined processing conditions is executed (step S1109). In this case, the film formation process is re-executed based on the processing conditions determined in step S1108and the processing step (S631or S633) as a re-execution target. Meanwhile, when it is determined that the difference calculated in step S1104is greater than the predetermined value (step S1106, No), the controller100determines processing conditions for canceling the difference in order to improve the in-plane uniformity (step S1110). Then, the controller100re-executes the film formation process based on the determined processing conditions (step S1109). Subsequently, the process proceeds to step S631or S633. Accordingly, the monitoring process of Method Example 2 is ended. As described above, in the plasma processing according to the embodiment, by monitoring the plasma state in the processing container10, it is possible to estimate the film formation state without inspecting the pattern itself on the wafer W. Thus, the plasma processing apparatus1according to the embodiment may highly accurately and simply determine the ending timing of the film formation process. Next, the first to third detection processes will be described. Here, descriptions will be made on the assumption that the detection in the first to third detection processes is executed by the second sensor108b.Meanwhile, the detection in the first to third detection processes may be executed by the observation device OC after the wafer W is transported to the observation module OM illustrated inFIG.1. (First Detection Process) The first detection process includes a process of detecting the shape or the dimension of the pattern on the wafer W by the second sensor108b,and a process of determining processing conditions of a subsequent process by the controller100based on the detection result of the second sensor108b. The second sensor108bdetects the shape or the dimension of the pattern on the wafer W through an optical method. The detection method by the second sensor108bis not particularly limited. The result of detection by the second sensor108bis transmitted to the controller100, and is stored in the storage such as the ROM110, or the RAM115. When the detection result is received, the controller100compares the detection result to a predetermined pattern dimension. Then, a difference between the predetermined pattern dimension and the detected dimension is calculated. The controller100adjusts processing conditions of a subsequent process based on the calculated difference. Then, the controller100determines processing conditions to be used in the subsequent process. At a point in time when the wafer W is disposed in the processing container10, in the case where the pattern formed on the wafer W deviates from a design value, when a subsequent process is executed under processing conditions based on a design, there is a high possibility that the state of a film to be finally formed may deviate from a design value. Therefore, in the embodiment, in the first detection process, the processing conditions are adjusted based on a difference between the design value and the actually measured value. (Second Detection Process) The second detection process includes a process of detecting the shape or the dimension of the pattern on the wafer W by the second sensor108b,and a process of determining a subsequent process and processing conditions by the controller100based on the detection result of the second sensor108b. The detection process of the second sensor108bin the second detection process is the same as the detection process in the first detection process. Meanwhile, at the time of execution of the second detection process, since the film formation process has ended, the shape of the pattern formed on the wafer W is different from that at the time of the first detection process. In addition, in the process of the controller100, a predetermined pattern dimension to be compared to the detection result is also different from that at the time of the first detection process. When the detection result is received, the controller100compares the detection result to the predetermined pattern dimension. Then, a difference between the predetermined pattern dimension and the detected dimension is calculated. The controller100determines whether to re-execute the film formation process (step S63) based on the calculated difference. For example, when the calculated difference is equal to or greater than a threshold value, the controller100determines to re-execute the film formation process. Meanwhile, when the calculated difference is less than the threshold value, the controller100determines not to re-execute the film formation process. When it is determined not to re-execute the film formation process, next, the controller100determines processing conditions of subsequent etching (step S66). For example, when the numerical value of the thickness of the film formed on the pattern, which is obtained from the detection result, is greater than a set value, the processing conditions are adjusted such that the etching effect becomes stronger. Then, the controller100determines the adjusted processing conditions, as processing conditions for etching (step S66). When the second sensor108bused in the second detection process is, for example, an infrared sensor, the second sensor108bmay directly measure the thickness of the film formed on the pattern. In this case, the controller100calculates a difference by comparing the result of detection by the second sensor108bto a predetermined film thickness. Then, the controller100determines whether to re-execute the film formation process (step S63) based on the calculated difference. Then, the controller100determines a subsequent process and processing conditions. (Third Detection Process) The third detection process includes a process of detecting the shape or the dimension of the pattern on the wafer W by the second sensor108b,and a process of determining a subsequent process and processing conditions by the controller100based on the detection result of the second sensor108b. The detection process of the second sensor108bin the third detection process is the same as the detection process in the first and second detection processes. Meanwhile, at the time of execution of the third detection process, since the film formation process and the etching process have ended, the shape of the pattern formed on the wafer W is different from that at the time of the first and second detection processes. In addition, in the process of the controller100, a predetermined pattern dimension to be compared to the detection result is also different from that at the time of the first and second detection processes. When the detection result is received, the controller100compares the detection result to the predetermined pattern dimension. Then, a difference between the predetermined pattern dimension and the detected dimension is calculated. The controller100determines whether to re-execute the film formation process (step S63) based on the calculated difference. For example, when the calculated difference is equal to or greater than a threshold value, and the detected dimension is smaller than the predetermined pattern dimension, the controller100determines to re-execute the film formation process. Meanwhile, when the calculated difference is less than the threshold value, the controller100determines not to re-execute the film formation process. In addition, the controller100determines whether to re-execute the etching process (step S66) based on the calculated difference. For example, when the calculated difference is equal to or greater than the threshold value, and the detected dimension is larger than the predetermined pattern dimension, the controller100determines to re-execute the etching process. When it is determined to re-execute the film formation process, next, the controller100determines processing conditions of the film formation process. For example, the processing conditions are determined such that a difference between a pattern shape obtained from the detection result and the predetermined pattern dimension is reduced. Then, the controller100executes the film formation process by using the determined processing conditions (FIG.6, step S67, “re-execute film formation”). In addition, when it is determined to re-execute the etching process, next, the controller100determines processing conditions of the etching process. For example, the processing conditions are determined such that a difference between a pattern shape obtained from the detection result and the predetermined pattern dimension is reduced. Then, the controller100executes the etching process by using the determined processing conditions (FIG.6, step S67, “re-execute etching”). When it is determined to re-execute neither the film formation process nor the etching process (FIG.6, step S67, “no re-execution”), the controller100ends the process. All of the first detection process, the second detection process and the third detection process may be realized by using the same detector, for example, the second sensor108bor the observation device OC, or different detectors may be used for the processes, respectively. In addition, the determination process may be executed by the controller100, or the first sensor108amay have a determination function so that a numerical value and a time stamp may be transmitted to the controller100. FIGS.11A and11Bare views illustrating an example of information stored in the storage in the plasma processing according to the embodiment. In the example illustrated inFIG.11A, the results detected in the first detection process, the second detection process, and the third detection process are stored in association with “time stamp.” Here, the detection result may be a specific dimension. In addition, shape abnormalities may be categorized in advance and a plurality of types may be defined, so that a type corresponding to the detection result may be stored. InFIG.11A, the detection results are categorized and are stored as, for example, “dimension A,” “dimension B,” etc. In addition, as the result of the monitoring process, numerical values associated with a plurality of time stamps may be stored, in associated with a time stamp each time step S633is executed once. In addition, when the first sensor108ais an image sensor, a plurality of images themselves may be stored. InFIG.11A, as the monitoring result, a value “V1” obtained by digitizing each of images acquired during step S633, and integrating the digitized values is stored. In addition, inFIG.11A, as the “determination result”, results of the first to third detection processes and the determination process are stored. For example, in the first detection process, a processing condition “X” for a subsequent process is stored. For example, in the second detection process, “re-execute” indicating re-execution of the film formation process, and a processing condition “Y” for the re-execution are stored. “Y” also includes information that identifies the step in which the process is executed. In addition, in the third detection process, “do not re-execute” indicating that neither etching nor film formation is re-executed is stored. In addition, due to no re-execution, “NA” (not applicable) is stored in the column of the processing condition. In addition, “re-execute” and “condition X” are stored in association with the monitoring process “V1.” This indicates that in the determination process, it has been determined that the film formation process is to be re-executed, and the corresponding processing condition is “X.” In addition,FIG.11Bis a configuration example when a dimension or a threshold value to be compared to a detection result in each process is stored in the storage. For example, in the first detection process, the detection result is compared to “dimension AA” so as to determine the processing condition of a subsequent process.FIGS.11A and11Bare an example, and the configuration of information stored in the storage to execute the first to third detection processes, the monitoring process and the determination process is not particularly limited. (Modification) In the above-described embodiment, the detection result of the first detection process (step S62), the monitoring result of the monitoring process (step S64A), the detection result of the second detection process (step S65), and the detection result of the third detection process (step S67) are used in, for example, adjusting processing conditions, and determining re-execution necessity of each process, in regard to the wafer W on which the processes have been executed. However, these detection results and the monitoring result may also be applied to not only the wafer W on which the processes have been executed, but also a wafer W′ to be processed after the wafer W. That is, a series of processes (steps S61to S67) are executed on the wafer W, and data is acquired in regard to, for example, the shape of the recess before the film formation process, the plasma state in the film formation process, the state of the film formed by the film formation process, and the state of the film and the shape of the pattern after the etching. Then, correlation between these is obtained. As an example, correlation is obtained in regard to the shape of the recess before the film formation process, the plasma state in the film formation process, and the state of the film formed by the film formation process. In another example, correlation is obtained in regard to the plasma state in the film formation process, the state of the film formed by the film formation process, and the state of the film and the pattern shape after the etching. These correlations may be stored as physical models in the storage in the controller Cnt. Then, conditions of the film formation process (step S63) or the etching (step S66) are corrected based on these physical models, and the corrected conditions are applied to the processing of the wafer W′. In an example, the physical models are constructed by repeating a cycle including processing execution, correlation acquisition, and condition correction. The construction of the physical models may be performed by machine learning. According to such a modification, the processing on the wafer W may be performed in a shorter time with higher accuracy than the processing on the wafer W. (Effect of Embodiment) The plasma processing method according to the embodiment includes a process (a), a process (b), a process (c), and a process (d). In the process (a), a substrate having a recess is provided in a processing container. In the process (b), plasma is generated in the processing container to form a film on the recess. In the process (c), a state of the plasma generated in the process (b) is monitored. In the process (d), necessity of re-execution of the process (b) and a processing condition for the re-execution are determined based on the monitored plasma state. Thus, according to the plasma processing method according to the embodiment, there is no need to inspect the pattern itself on the substrate, and by estimating the film formation state, it is possible to determine the necessity of re-execution of the film formation process and the processing condition suitable for a case of the re-execution. In addition, in the present plasma processing method, in order to monitor the plasma state during the film formation process, it is possible to estimate the film formation state without carrying the substrate out of the processing container. Thus, according to the present plasma processing method, it is possible to easily determine the ending timing of the film formation process with high accuracy. Thus, in the present plasma processing method, it is possible to stabilize the performance of the film formation process using plasma. In addition, in the plasma processing method according to the embodiment, the process (b) may include a process (b-1) and a process (b-2). In the process (b-1), a first gas may be introduced into the processing container and may be adsorbed on the recess. In the process (b-2), a second gas may be introduced into the processing container so that plasma of the second gas may be generated and reacted with a component of the first gas adsorbed on the recess to form a film. Then, in the process (c), a state of the plasma generated in the process (b-2) may be monitored. As described above, the plasma processing method according to the embodiment may be applicable to a film formation process, for example, ALD, which is realized in two stages of the adsorption of the first gas and the reaction of the second gas. In addition, the plasma processing method according to the embodiment, the process (b) may be ended before reaction between the component of the first gas and the component of the second gas is saturated on an entire surface of the recess. As described above, the plasma processing method according to the embodiment may be used to determine the ending timing of the film formation process in the sub-conformal ALD. Thus, according to the plasma processing method according to the embodiment, the ending timing of the film formation process may be highly accurately estimated, and then the film formation process may be ended before the film formed by the sub-conformal ALD reaches a saturation state. In addition, the plasma processing method according to the embodiment, in the process (c), a physical quantity indicating the plasma state may be monitored. Then, in the process (d), when an integrated value of the physical quantities obtained by monitoring is less than a predetermined value, re-execution of the process (b) is determined. Thus, according to the plasma processing method according to the embodiment, based on the integrated value of the physical quantities obtained by monitoring during the film formation process, it is possible to highly accurately estimate the state of the film formed from the processing start to that point in time. Thus, in the embodiment, even if the film formation process is interrupted for some reason, it is possible to estimate the film formation state at that point in time based on the monitoring result, and to resume the film formation process in order to make up for the shortage. In addition, the plasma processing method according to the embodiment, in the process (c), an amount of radicals in the plasma generated in the process (b) may be monitored. The amount of radicals may be calculated based on, for example, an electron density and an ion density. In addition, when the temperature in the processing container and the pattern shape on the substrate as a processing target are known, it is possible to estimate the film formation state based on the amount of radicals. Thus, according to the embodiment, it is possible to easily estimate the film formation state on the substrate by using the physical quantity that may be acquired by, for example, an emission spectroscopic sensor. In addition, the plasma processing method according to the embodiment, in the process (c), the plasma state in each of regions set in a surface where the substrate is disposed may be monitored. In the process (d), when an integrated value of physical quantities indicating the plasma state in each of the regions is less than a predetermined value, re-execution of the process (b) is determined. Thus, according to the embodiment, it is possible to determine the necessity of re-execution of the film formation process by estimating the film formation state in each region in the substrate plane. In addition, the plasma processing method according to the embodiment, in the process (c), the plasma state in each of regions set in a surface where the substrate is disposed may be monitored. Then, in the process (d), physical quantities indicating the plasma state in the regions, respectively, may be compared, and re-execution of the process (b) is determined when a difference is larger than a predetermined value. Thus, in the embodiment, it is possible to re-execute the film formation process such that the film formation state may become uniform in the regions in the substrate plane. Thus, the plasma processing method according to the embodiment may improve the in-plane uniformity in the film formation process. In addition, the plasma processing method according to the embodiment may further include a process (e), and a process (f). In the process (e), a state of the film on the recess is detected after the process (b) is executed. In the process (f), the process (b) is re-executed according to a detection result of the process (e). Thus, according to the plasma processing method according to the embodiment, through not only the monitoring of the plasma state, but also detection of the film state, it is possible to determine whether to further re-execute the film formation process. Thus, in the embodiment, it is possible to stabilize the performance of the film formation process using plasma and to realize highly accurate film formation. In addition, the plasma processing method according to the embodiment may further include a process (e), a process (f), and a process (g). In the process (e), a state of the film on the recess is detected after the process (b) is executed. In the process (f), processing conditions according to a detection result of the process (e) are determined. In the process (g), a base layer of a layer having the film formed on the recess is etched by using the layer as a mask, under the processing conditions determined in the process (f). Thus, in the embodiment, according to the film formation result, it is possible to adjust processing conditions of subsequent etching, and to realize highly accurate pattern formation. In addition, the plasma processing method according to the embodiment may further include a process (h). In the process (h), after the process (g) is executed, a shape of a pattern formed by the etching and/or the state of the film on the recess are detected, and then the process (b) or the process (g) is re-executed when a degree of coincidence between the detected shape and a predetermined shape is equal to or lower than a predetermined value. Thus, in the embodiment, it is possible to determine whether to further execute etching according to the shape after the etching. Thus, in the embodiment, it is possible to realize highly accurate pattern formation. In addition, the plasma processing method according to the embodiment may further include a process (i) and a process (j). In the process (i), a shape of the recess is detected before the process (b) is executed. In the process (j), processing conditions of the process (b) are determined according to a detection result of the process (i). Thus, in the embodiment, it is possible to determine processing conditions according to the state of the pattern on the substrate before the film formation or the etching is executed. Thus, in the embodiment, it is possible to realize highly accurate pattern formation. In addition, the plasma processing method according to the embodiment may further include a process (k), a process (l), and a process (m). In the process (k), correlation between the shape of the recess before film formation, the plasma state, and the state of the film formed in the process (b) is obtained based on the shape of the recess of the substrate before execution of the process (b), the plasma state monitored in the process (c), and the state of the recess of the substrate after execution of the process (b). In the process (l), the processing conditions in the process (b) are corrected based on the obtained correlation. In the process (m), plasma processing is executed by applying the corrected processing conditions to a substrate (a substrate to be processed after the substrate) different from the substrate on which, for example, the process (k), the process (l) and the process (m) have been executed. Thus, in the embodiment, each time the film formation process is executed on the substrate, it is possible to optimize the film formation conditions. In addition, the plasma processing method according to the embodiment may include a process (n), a process (o), a process (p), and a process (q). In the process (n), after the process (g) is executed, a shape of a pattern formed by the etching and/or the state of the film on the recess are detected. In the process (o), correlation between the state of the film before and after the process (g), the plasma state, and the shape of the pattern after the process (g) is obtained based on the state of the film detected in the process (e), the plasma state monitored in the process (c), and the shape of the pattern and/or the state of the film on the recess detected in the process (n). In the process (p), the processing conditions in the process (g) are corrected based on the obtained correlation. In the process (q), under the corrected processing conditions, a substrate different from the substrate on which, for example, the process (n), the process (o) and the process (p) have been executed is etched. Thus, in the embodiment, each time the substrate is etched, etching conditions may be optimized. In addition, the plasma processing apparatus according to the embodiment includes one or more processing containers and a controller. In addition, at least one of one or more processing containers is configured to perform etching. At least one of one or more processing containers is configured to perform film formation. One processing container may be configured to perform etching and film formation. The processing container includes a gas supply configured to supply a processing gas therein. The controller causes each of units to execute a plasma processing method including a process (a), a process (b), a process (c), and a process (d). In the process (a), a substrate having a recess is provided in the processing container. In the process (b), plasma is generated in the processing container to form a film on the recess. In the process (c), a state of the plasma generated in the process (b) is monitored. In the process (d), necessity of re-execution of the process (b) and processing conditions for the re-execution are determined based on the monitored plasma state. Thus, the plasma processing apparatus according to the embodiment may stabilize the performance of the film formation process using plasma, and may realize highly accurate pattern formation. A target to which the plasma processing method according to the embodiment is applied is not particularly limited as long as it is substrate processing using plasma. In addition, the plasma processing method according to the embodiment may be used in a 3D NAND or DRAM manufacturing process. In addition, the plasma processing method according to the embodiment may be used in, for example, processing of a high AR (aspect ratio) organic film, or processing of a mask for logic. According to the present disclosure, it is possible to stabilize the performance of a film formation process using plasma. From the foregoing, it will be appreciated that various embodiments of the present disclosure have been described herein for purposes of illustration, and that various Modifications may be made without departing from the scope and spirit of the present disclosure. Accordingly, the various embodiments disclosed herein are not intended to be limiting, with the true scope and spirit being indicated by the following claims. | 74,292 |
11862442 | DETAILED DESCRIPTION OF THE DISCLOSURE Hereinafter, a plasma process monitoring device and a plasma process chamber according to preferred embodiments will be described in detail with reference to the accompanying drawings. Here, when reference numerals are applied to constituents illustrated in each drawing, it should be noted that like reference numerals indicate like elements throughout the specification. In the following description of the present disclosure, a detailed description of known functions and configurations incorporated herein will be omitted when it may make the subject matter of the present disclosure unclear. Embodiments of the present disclosure are provided to more fully describe the present disclosure to those skilled in the art. Accordingly, the shape and size of elements in the drawings may be exaggerated for clarity. FIG.1is a schematic block diagram of a plasma process monitoring device according to one embodiment of the present disclosure and a plasma processing apparatus including the same,FIG.2is a side view of the plasma processing apparatus shown inFIG.1, andFIG.3is a block diagram of the selection area light transmitter shown inFIG.1.FIG.4Ais a top view of a conventional plasma processing apparatus in which a selection area light transmitter is not installed, andFIG.4Bis a top view of the plasma processing apparatus shown inFIG.1. As shown inFIGS.1to4, a plasma process monitoring device100is installed in a chamber110provided with a viewport120, and includes a selection area light transmitter130and a monitor140. The selection area light transmitter130may be disposed to face the viewport120formed in the chamber110, and may include a plurality of selective light blockers131for selectively blocking or transmitting plasma light emitted through the viewport120. The viewport120is divided into several areas by the selective light blockers131and plasma light is alternately blocked or transmitted so that the intensity or quantity of plasma light for each area in the chamber110may be measured. Here, the size of the selective light blockers131is not limited, but the selective light blockers131are preferably formed to have a size allowing a minimum quantity of plasma light to pass therethrough. The selective light blockers131may be arranged in parallel in the horizontal or vertical direction, and each of the selective light blockers131may be formed in a rectangular shape. In addition, to accurately measure plasma uniformity, the selective light blockers131are preferably arranged so as to be in close contact with each other such that no gaps are formed therebetween. Referring toFIG.3, the selection area light transmitter130may include a transparent LCD panel131and a switch132. The transparent LCD panel131may be disposed to face the viewport120. The transparent LCD panel131includes one or more LCD panel units31, each being divided into one or more areas31aand31band powered individually. In addition, the transparent LCD panel131may be formed so that plasma light is transmitted only through an area to which power is supplied. That is, when power is applied to the transparent LCD panel131, which is a kind of transparent film, the liquid crystal material inside the transparent LCD panel131is scattered, which causes light scattering. Thus, in the transparent LCD panel131, coloring (i.e., contrast) may be controlled using this phenomenon. In the present disclosure, a simplified LCD panel in which contrast is adjusted only in black is preferably used. Each of the areas31aand31bof each of the LCD panel units31constituting the transparent LCD panel131may be individually connected to a power source so that contrast may be adjusted in black in each area. That is, although the LCD panel unit31, which serves as a selective light blocker, is shown as being divided into two areas31aand31binFIG.3, the number of the divided areas is not limited thereto, and the LCD panel unit31may be divided into one or more areas. When the LCD panel unit31has one area, the LCD panel unit31may be provided in plural, and the LCD panel units31may be connected to each other to form the transparent LCD panel131. In this case, the size of the areas31aand31bof the LCD panel unit31is not limited, and the areas31aand31bare preferably formed to have a size allowing a minimum quantity of plasma light to pass therethrough. The switch132may be connected to the transparent LCD panel131, and may selectively supply power to each of the areas31aand31bof the LCD panel unit31. Accordingly, contrast in each of the areas31aand31bof the LCD panel unit31may be individually adjusted by controlling the switch132. For example, as shown inFIG.3, when the transparent LCD panel131includes one LCD panel unit31, the area of which is divided into two areas31aand31b, when power is applied only to the area31adisposed on the left side of the LCD panel unit31through the switch132, the contrast in the area31ais adjusted to be transparent so that plasma light is transmitted through the area31a, and the contrast in the area31bdisposed on the right side of the LCD panel unit31is adjusted to be black so that plasma light is blocked. Therefore, plasma light transmitted through the viewport120is not transmitted through the area31bdisposed on the right side, but is transmitted only through the area31adisposed on the left side. That is, the quantity of light passing through the area31bdisposed on the right side is 0%, and the quantity of light passing through the area31adisposed on the left side is 100%. The monitor140receives plasma light transmitted through at least one of the selective light blockers131to acquire information on the received plasma light, and monitors the uniformity of plasma generated in the chamber110based on the acquired information on the plasma light. In this case, the information on plasma light may include information on the intensity and quantity of plasma light transmitted through the selective light blockers131. The monitor140may be disposed outside of the chamber110, and may be connected to the selection area light transmitter130via an optical cable150having an optical probe151. Specifically, the optical probe151may be disposed close to the selection area light transmitter130, and may be optically connected to the monitor140via the optical cable150. Accordingly, the monitor140may analyze plasma light transmitted via the optical probe151and the optical cable150. For example, the optical cable150may be formed of optical fiber. The monitor140may be an apparatus, e.g., an optical emission spectroscope (OES), having an optical fiber for monitoring the intensity or quantity of plasma light. The optical emission spectroscope may detect light using the discontinuous electron energy levels of atoms and ions, i.e., may detect light emitted when electrons in a relatively high energy state transition to a relatively low energy state. However, the type of the monitor140is not limited to the optical emission spectroscope (OES), and the monitor140may include a camera for monitoring the intensity or quantity of plasma light. In addition, the monitor140may include a measurement sensor for measuring the intensity or quantity of plasma light therein, and may monitor the intensity or quantity of plasma light. When the monitor140includes the measurement sensor, the monitor140may be directly connected to the optical probe151without an optical fiber, i.e., the optical cable150, and may monitor the intensity or quantity of plasma light transmitted through the selection area light transmitter130. Analysis of the plasma light of a specific area transmitted through the selection area light transmitter130by the monitor140enables detection of an abnormal state of plasma according to positions in the chamber110and spatial interpretation of the plasma state. In addition, the monitor140may receive information on plasma light transmitted through each of the selective light blockers131and compare the received information, and based on the information, may determine the uniformity of distribution of plasma generated in the chamber110. In addition, a condenser160for extending and focusing the range of the angle of incidence of plasma light emitted from the inside of the chamber110and providing the plasma light to the monitor140may be further installed between the selection area light transmitter130and the monitor140. The condenser160may be formed of a specially processed concave lens. The concave lens may have a structure in which the curvature in the horizontal direction is larger than the curvature in the vertical direction. Accordingly, the condenser160may extend the range of the angle of incidence (B) of plasma light emitted from the inside of the chamber110to focus the plasma light. That is, according to a conventional apparatus, only a portion of plasma light is collected through the optical cable150, e.g., an optical fiber, of the monitor140, as shown inFIG.4A. On the other hand, according to one embodiment of the present disclosure, as shown inFIG.4B, the condenser160is further provided in front of the monitor140to receive light in a wide area inside the chamber110. Accordingly, the state of plasma may be uniformly analyzed from the center to the outermost part of a substrate W. Thus, this configuration may improve the performance of analyzing the plasma state. For example, to extend a range within which light in the chamber110is received, i.e., to increase the angle of incidence of plasma light, a specially processed concave lens may be inserted in the front of the monitor140, thereby significantly increasing a light receiving angle (e.g., about 160° or more). FIGS.5A,5B and5Cshow various examples of installation of the selection area light transmitter shown inFIG.1, andFIGS.6and7show examples of driving the selection area light transmitter shown inFIG.1. The structure and operation of the selection area light transmitter will be described with reference toFIGS.5A to7. As shown inFIGS.5A,5B and5C, the selection area light transmitter130may be formed to be larger than the viewport120and spaced apart from the viewport120(seeFIG.5A), or may be formed to be smaller than the viewport120and mounted on one side of the viewport120(seeFIG.5B). Alternatively, the selection area light transmitter130may be formed to have the same size as the viewport120and be mounted on one surface of the viewport120(seeFIG.5C). In this case, the selection area light transmitter130may be disposed so that the center of the selection area light transmitter130coincides with the center of the viewport120. When the selection area light transmitter130is mounted on one side of the viewport120, one side of the selection area light transmitter130and one side of the viewport120may be in contact with each other, and these surfaces may be bonded or coupled to each other using an adhesive or a fastening tool so that the selection area light transmitter130and the viewport120can be integrated. The selection area light transmitter130may be formed so that plasma light is transmitted through at least one of the selective light blockers131. For example, as shown inFIG.6, plasma light may be sequentially transmitted in one direction through the selective light blockers131. When plasma light is transmitted in this manner, changes in the quantity of plasma light may be continuously monitored, and the uniformity of plasma may be continuously measured. As shown inFIG.7, the number of the selective light blockers131provided in the selection area light transmitter130may vary. In addition, the selective light blockers131may be disposed so that the entire area of the chamber110or only the central area of the chamber is measured. Here, plasma may be concentrated in the central area of the chamber110, in which case only the central area of the chamber110may be measured. For example, as shown inFIG.7, when the selection area light transmitter130is provided with two selective light blockers131, the selective light blockers131may be formed to alternately block transmission of plasma light through the right area of the selection area light transmitter130and transmission of plasma light through the left area of the selection area light transmitter130. Accordingly, the intensities of plasma light respectively generated in the left and right areas of the chamber110may be compared with each other so that the uniformity of plasma distribution in the chamber110may be determined. In addition, when the selection area light transmitter130is provided with three selective light blockers131, the selection area light transmitter130may be set so that plasma light is alternately transmitted only through the selective light blocker131on the left side and the selective light blocker131on the right side. In this case, only the outer area of the chamber110may be measured. In addition, as shown inFIG.6, the selection area light transmitter130may be set so that plasma light is sequentially transmitted through the selective light blockers131. In this case, changes in the quantity of plasma light may be continuously measured. In addition, the selection area light transmitter130may be set so that plasma light is transmitted through the selective light blockers131in an arbitrary order rather than in a sequential order. In this case, the uniformity of plasma distribution may be measured by comparing the differences in light quantities. In addition, when the selection area light transmitter130is provided with four selective light blockers131, the selective light blockers131may be formed so that plasma light is alternately transmitted through the odd-numbered selective light blocker131and the even-numbered selective light blocker131. In addition, even when the selection area light transmitter130is provided with four selective light blockers131, the selection area light transmitter130may be set so that plasma light is alternately transmitted only through the left and right selective light blockers131, or so that plasma light is sequentially transmitted. In addition, even when the selection area light transmitter130is provided with four selective light blockers131, the selection area light transmitter130may be set so that plasma light is transmitted through the selective light blockers131in an arbitrary order rather than a sequential order. In this case, the uniformity of plasma distribution may be measured by comparing the differences in light quantities. FIG.8shows a block diagram of a selection area light transmitter according to another embodiment, which is included in the plasma process monitoring device ofFIG.1. As shown inFIGS.8and9, a selection area light transmitter230may include a frame231and shutter members232. The frame231may be disposed to face the viewport120, and an opening231amay be formed on one side thereof. The shutter members232may be provided in plural and arranged in a line in the frame231, and may selectively shield a certain area of the opening231a. That is, the shutter members232may serve as a selective light blocker, and a driving motor for rotationally driving or linearly moving the shutter members232may be provided on one side of each of the shutter members232. Accordingly, as shown inFIG.8, in the case of the frame231provided with two shutter members232aand232b, when the shutter member232bdisposed on the right side is driven by the driving motor, the opening231aformed on the right side is shielded, so that plasma light is not transmitted through the opening231aformed on the right side and plasma light is transmitted only through the opening231aformed on the left side. The size of the shutter members232aand232bis not limited, but the shutter members232aand232bare preferably formed to have a size allowing a minimum quantity of plasma light to pass therethrough. FIG.9is a block diagram of a selection area light transmitter according to another embodiment, which is included in the plasma process monitoring device ofFIG.1, andFIGS.10A and10Billustrate the set of polarizing filters shown inFIG.9in detail. As shown inFIGS.9,10A and10B, a selection area light transmitter330may include a set of polarizing filters331and a controller332. The set of polarizing filters331may include at least two polarizing filter31aand31barranged so as to overlap each other, and may be formed so that plasma light is selectively transmitted. When light vibrating in various directions encounters the polarizing filter31aand31b, only light vibrating in a specific direction may be transmitted through the polarizing filter31aand31b. The controller332may selectively block transmission of plasma light through the polarizing filter31aand31bby controlling the angle of each of the polarizing filter31aand31bprovided in the set of polarizing filters331. Specifically, as shown inFIGS.10A and10B, when two sets of polarizing filters331are provided on the left and right sides, respectively, when the arrangement angle of each of polarizing filters31band31bincluded in the set of polarizing filters331bdisposed on the right side is controlled by the controller332so that the polarizing filters31band31bform a right angle with respect to each other (e.g., one is arranged to transmit vertically polarized light, and the other is arranged to transmit horizontally polarized light), plasma light incident on the set of polarizing filters331bdisposed on the right side may be blocked. When the arrangement angle of each of polarizing filters31aand31aincluded in the set of polarizing filters331adisposed on the left side is controlled by the controller332so that the polarizing filters31aand31aare arranged in parallel (e.g., both are arranged to transmit vertically polarized light, or both are arranged to transmit horizontally polarized light), plasma light incident on the set of polarizing filters331adisposed on the left side may be transmitted (seeFIGS.10A and10B). FIG.11Ais a graph showing plasma light intensities over time measured using a conventional plasma process monitoring device, andFIG.11Bis a graph showing plasma light intensities over time measured using a plasma process monitoring device according to the present disclosure including two selection area light transmitters. As shown inFIG.4A, in a conventional plasma process monitoring device1, the selection area light transmitter130is not installed. Thus, all plasma light in the chamber110passes through the viewport120and is transmitted to the monitor140. Accordingly, the conventional plasma process monitoring device1may not measure the uniformity of plasma distribution in the chamber110. On the other hand, referring toFIG.10B, in the plasma process monitoring device100according to the present disclosure, the above-described selection area light transmitter130is installed. Therefore, the uniformity of plasma distribution in the chamber110may be measured by comparing the quantities of light in the left and right areas. In this case, it can be confirmed that, when plasma distribution is non-uniform, as the difference in the degree of opening in the left and right areas through which plasma light is transmitted increases, the difference in the quantity of light increases. In addition, referring toFIG.1, the monitor140may further include a photographing module141for photographing the arc discharge state of plasma light transmitted through the selective light blockers131. The photographing module141may be a charge-coupled device (CCD) camera. When a photographed image has a pixel having a predetermined level or higher, the monitor140may determine that arc discharge has occurred in the photographed area, and may output this information to the outside. As described above, since the plasma process monitoring device100includes the selection area light transmitter130disposed between the viewport120and the monitor140and for transmitting or blocking plasma light emitted through the viewport120, the uniformity and arc discharge state of plasma generated in the chamber110during performance of plasma processing may be monitored. In addition, upon determining that plasma uniformity is low through the monitor140, a plasma process environment may be optimized by controlling plasma process conditions, so that the distribution of plasma becomes uniform. Thus, an excellent and highly reliable semiconductor substrate may be fabricated. In addition, when an abnormal state of arc discharge is detected through the photographing module141of the monitor140, the facility may be repaired or the amount of reaction gas may be adjusted to suppress occurrence of arc discharge. Therefore, damage to the substrate W fabricated in the chamber110may be prevented. As shown inFIGS.1to10B, a plasma processing apparatus10including the plasma process monitoring device includes the chamber110, the viewport120, the selection area light transmitter130, and the monitor140. In the present embodiment, differences from the above-described example will mainly be described. The chamber110is a space where a plasma process is performed, and a chuck111on which the substrate W is placed may be installed in the chamber110. Here, the substrate W may be a semiconductor substrate, a metal substrate, or a glass substrate. Treatment of the substrate W may be performed through an etching process, a chemical vapor deposition process, an ashing process, a cleaning process, or the like, without being limited thereto. A gas feeder113may be provided on one side of the chamber110, and the gas feeder113may be connected to the inside of the chamber110via a gas feed pipe112. This configuration allows reaction gas for generating plasma to be fed into the chamber110. As the reaction gas, inert gas such as argon (Ar) and nitrogen (N2) may be used. Vacuum may be formed inside the chamber110, and a vacuum unit114may be connected to one side of the chamber110for formation of vacuum. The vacuum unit114may include a vacuum pump, a control valve for adjusting pressure, and the like. The viewport120is installed in the chamber110, and plasma light emitted from the chamber110is transmitted to the outside of the chamber110through the viewport120. Specifically, the viewport120may be disposed on a sidewall of the chamber110, and may be provided with a window for observing the state inside the chamber110in which an etching process, a deposition process, or the like is performed. Accordingly, since plasma light generated inside the chamber110may be emitted to the outside through the viewport120, whether plasma for performing an etching process or a deposition process is properly formed or whether the substrate W being processed is maintained in a stable may be confirmed from the outside. The selection area light transmitter130may be disposed to face the viewport120formed in the chamber110, and may include the selective light blockers131for selectively blocking plasma light emitted from the viewport120. The selection area light transmitter130may include the transparent LCD panel131and the switch132, include the frame231and the shutter members232, and include the set of polarizing filters331and the controller332. Since the configuration of the selection area light transmitter130is the same as that described above, description thereof is omitted. The monitor140receives plasma light transmitted through at least one of the selective light blockers131to acquire information on the received plasma light, and monitors the uniformity of plasma generated in the chamber110based on the acquired information on the plasma light. In this case, the information on plasma light may include information on the intensity and quantity of plasma light transmitted through the selective light blockers131. The operation of the plasma processing apparatus10including the plasma process monitoring device100will be described with reference toFIGS.1to10B. First, when the substrate W is placed on the chuck111in the chamber110, vacuum is formed inside the chamber110by operation of the vacuum unit114. In this state, reaction gas is fed into the chamber110by the gas feeder113. Then, when a high-frequency current is applied to the inside of the chamber110, the reaction gas is transformed into plasma, and an etching process, a deposition process, or the like may be performed. When plasma is formed in this manner, light generated in plasma is transmitted to the selection area light transmitter130through the viewport120. In this case, since the selection area light transmitter130is divided into several compartments by the selective light blockers131, when the selective light blockers131are selectively shielded, the space in the chamber110is divided into predetermined areas, and only the information on plasma light generated in a certain area may be transmitted to the monitor140. For example, when the selection area light transmitter130is formed as the transparent LCD panel131having one LCD panel unit31divided into two areas31aand31b, power is selectively applied to the areas31aand31bby the switch132and light is transmitted only through the area31ato which power is applied. That is, only plasma light supplied to the area31ais transmitted, and the area31bto which power is not supplied blocks light transmission. In addition, as shown inFIGS.6and7, the switch132may be controlled so that plasma light is transmitted only through desired areas. That is, by controlling the switch132, plasma light may be transmitted only through the central area or the outer area of the transparent LCD panel131, plasma light may be alternately transmitted, or plasma light may be sequentially transmitted in one direction. When plasma light is transmitted through at least one area31athrough the above process, the monitor140receives information on plasma light via the optical probe151and the optical cable150. When the monitor140receives information on plasma light transmitted through each of the areas31aand31bof the LCD panel unit31, plasma intensity may be measured for each area inside the chamber110, and the monitor140may compare plasma intensities for these areas to determine the uniformity of plasma generated in the chamber110. In addition, the selection area light transmitter130may include the frame231and the shutter members232or the set of polarizing filters331and the controller332, so that plasma light may be transmitted only through desired areas. Through this process, plasma uniformity may be confirmed, so that deposition uniformity or etching uniformity for each region of the substrate W in the chamber110may be confirmed. That is, when plasma intensity is biased in one direction in the chamber110, deposition or etching of a portion of the substrate W positioned in the plasma-concentrated area rapidly proceeds and deposition or etching of a portion of the substrate W positioned in the remaining area slowly proceeds. Accordingly, the thickness of the substrate W may be non-uniform. Therefore, when abnormal distribution of plasma light is detected through the monitor140, a plasma process environment may be optimized by controlling plasma process conditions. When the semiconductor substrate W is fabricated based on the optimized plasma process, an excellent and highly reliable semiconductor product may be realized. In addition, the arc discharge state of the plasma light of a certain area, which has been transmitted through the selective light blockers131, may be detected through the photographing module141of the monitor140. When arc discharge is detected, the facility may be repaired or the amount of reaction gas may be adjusted to suppress occurrence of arc discharge. Therefore, damage to the substrate W fabricated in the chamber110may be prevented. According to the present disclosure, the uniformity and arc discharge state of plasma generated in the chamber during performance of plasma processing can be monitored by including the selection area light transmitter disposed between the viewport and the monitor and for transmitting or blocking plasma light emitted from the viewport. In addition, upon determining that the uniformity of plasma light is low through the monitor, a plasma process environment can be optimized by controlling plasma process conditions. Thus, an excellent and highly reliable semiconductor substrate can be fabricated. In addition, when an abnormal state of arc discharge is detected through the photographing module of the monitor, occurrence of arc discharge can be suppressed by repairing the facility or adjusting the amount of reaction gas. Therefore, damage to a substrate fabricated in the chamber can be prevented. Meanwhile, embodiments of the present disclosure disclosed in the present specification and drawings are only provided to aid in understanding of the present disclosure and the present disclosure is not limited to the embodiments. It will be apparent to those skilled in the art that various modifications can be made to the above-described exemplary embodiments of the present disclosure without departing from the spirit and scope of the disclosure. Therefore, the scope of the present disclosure should be defined only by the appended claims. DESCRIPTION OF SYMBOLS 110: CHAMBER120: VIEWPORT130: SELECTION AREA LIGHT TRANSMITTER131: SELECTIVE LIGHT BLOCKERS131: TRANSPARENT LCD PANEL132: SWITCH140: MONITOR141: PHOTOGRAPHING MODULE150: OPTICAL CABLE151: OPTICAL PROBE160: CONDENSER231: FRAME231A: OPENING232: SHUTTER MEMBERS331: SET OF POLARIZING FILTERS332: CONTROLLER | 29,559 |
11862443 | MODE FOR CARRYING OUT THE INVENTION A sputtering target of the present invention comprises a target material, a sputtering face of the target material having at least one ramp provided to reduce a thickness of the target material at a position where erosion intensively concentrates during sputtering. In the sputtering target of the present invention, the sputtering face has a circular shape, and the ramp is formed at a position in a range of 14% or more and less than 60% of a diameter of the sputtering face so as to reduce the thickness of the target material toward an inner part of the sputtering face in the radial direction of the sputtering face. In the present invention, the “position where erosion intensively concentrates” means a position where erosion concentrates deeply, preferably a position where erosion concentrates most deeply, in other words, a part with a high horizontal magnetic field strength during sputtering, desirably a part with a maximum or maximal horizontal magnetic field strength on the sputtering face, and more preferably a part with a maximum horizontal magnetic field strength on the sputtering face. At this time, the vertical magnetic field strength at a position where erosion intensively concentrates (magnitude of a component of magnetic field vertical to the sputtering face) is desirably zero (0). For example, in a sputtering apparatus using a magnet such as an electromagnet, an electrical control that periodically controls electrical current changes a region where a magnetic field is generated every several seconds with the elapse of time. In the part with a high horizontal magnetic field strength on the sputtering face, an inert gas being plasmatized (or being ionized) is captured by a horizontal component of the magnetic field, and erosion of the target material can concentrate intensively at the position. More specifically, as shown inFIG.19, regions where magnetic field is generated change with the elapse of time, and parts with a high horizontal magnetic field strength (more specifically, parts encircled by a dotted line inFIG.19) can be formed on the sputtering face by electrically periodically switching positions of N poles and S poles of a plurality of electromagnets (e.g., by switching between a case A and a case B). As used herein, the magnetic field is generally indicated by physical quantity having dimension and orientation at every point in space (vector field), so that the “horizontal magnetic field” in the present invention means the magnitude of a component of the magnetic field that is horizontal to the sputtering face and, for example, can be represented as “magnetic flux density” that can be measured by a tesla meter, or the like. There is a direct proportional relationship between “magnetic flux density” (B) (unit: T (tesla)) and “magnetic field strength” (H) (unit: A/m) as shown by the following equation, so that the “horizontal magnetic field strength” can be determined by measuring the “magnetic flux density” on the sputtering face. B=μH [where μ as a proportional constant represents magnetic permeability] Therefore, erosion tends to intensively concentrate in a part with a high value of “magnetic flux density” on the sputtering face, desirably a part where a value of magnetic flux density is the maximum value or the maximal value. By providing at least one ramp at the position to reduce a thickness of a target material, the film thickness uniformity can be improved in a thin film that can be formed on a substrate during sputtering, particularly at the final stage of sputtering. During sputtering, the magnetic flux density in the part with a high horizontal magnetic field strength on the sputtering face (desirably, maximum value or maximal value thereof) is preferably 10 mT to 45 mT, more preferably 20 mT to 40 mT, and particularly preferably 25 mT to 35 mT. InFIG.20, a relationship between the magnetic flux density and a residual thickness (erosion amount) of the target material subjected to sputtering is schematically illustrated by a schematic view.FIG.20shows that erosion tends to intensively concentrate at a position where a value of magnetic flux density becomes the maximal value. As shown inFIG.2, the “position where erosion intensively concentrates” can exist near an outer peripheral part in the radial direction of the target material in a conventional disc shaped sputtering target having a circular sputtering face. In the present invention, the “position where erosion intensively concentrates” is not limited to such a position. A plurality of “positions where erosion intensively concentrates” may exist. The “position where erosion intensively concentrates” can include not only a bottom point of each erosion recess but also a surrounding region including the bottom point as shown inFIG.2. Specifically, the surrounding region may be in a range of 0.5 mm to 5.0 mm around the bottom point as a center of the erosion recess. Alternatively, the surrounding region may be a region, around the bottom point as a center, where erosion of 80% or more of the erosion of the bottom point is generated. When the sputtering face of the target material has a circular shape, a ramp is provided so as to reduce a thickness of the target material toward an outer side part of the sputtering face in the radial direction of the sputtering face as shown inFIG.5, (for convenience of explanation, other erosion parts are not shown inFIG.5), for example, in a range of 60% (lower limit) or more, preferably 65% or more, more preferably 70% or more of the diameter of the sputtering face, and less than 90% (upper limit), more preferably less than 85%, and still more preferably less than 80% of the diameter of the sputtering face. Conventionally, for example, as shown inFIGS.3and4, a thickness of target material has been increased at a position where erosion intensively concentrates in the aim of achieving prolongation of a life of sputtering target. As shown inFIG.4, however, as the thickness of the target material increases, the distance between the target material and the substrate (TS distance) becomes smaller. As a result, the film thickness uniformity of thin film to be formed on the substrate at the initial stage of sputtering is significantly degraded (inFIGS.3and4, for convenience of explanation, other erosion parts are not shown). As a result of the study of the present inventors, it has been found that sufficient film thickness uniformity cannot be obtained at the final stage of sputtering by the prior art. As it is schematically illustrated inFIG.6, when the thickness of the target material is increased at a position where erosion intensively concentrates in the target material conventionally for the sake of life prolongation, atoms tend to be intensively deposited in the middle part of the substrate, particularly at the final stage of sputtering. Therefore, the thickness increases in the middle part of the substrate and, in proportion thereto, the thickness decreases in the end part of the substrate. As a result, as shown inFIG.9(left), a large difference in thickness of a thin film to be formed is generated among the middle part, the end part, and the center of the substrate, leading to degradation of the film thickness uniformity. Whereas, in the present invention, as shown inFIG.7, the sputtering face can be positioned closer to a apparatus (magnetic field) by providing the above ramp to decrease the thickness of target material. In such a ramp part, horizontal magnetic field strength can be further increased. As a result, erosion can start from such a ramp part, and an erosion region can move (shift) to an edge side of the target material (FIG.8). Atoms can fly preferentially from such a position and shift toward the end parts of the substrate, thus enabling deposition of the atoms. Accordingly, intensive deposition of atoms can be avoided in the middle part of the substrate during sputtering, particularly at the final stage of sputtering, thus making it possible to suppress an increase in thickness thereof. As the erosion region moves to the edge side, an erosion amount generated in a region from the middle part to the center of the sputtering face increases, leading to an increase in the amount of atom flying from the vicinity of the center of the target material. As a result, a difference in thickness generated in the middle part, the end part, and the center decreases, thus making it possible to improve the film thickness uniformity at the final stage of sputtering (FIG.9(right)). According to the same principle, when the ramp is provided near the center of the sputtering face, deposition of atoms can be moved (shifted) toward the center of the substrate. As a result, similarly, intensive deposition of atoms in the middle part of the substrate can be avoided (FIG.10). In the present invention, the ramp is formed at a position in a range of 14% or more (lower limit), preferably 20% or more, more preferably 30% or more of the diameter of the sputtering face and less than 60% (upper limit), preferably 58% or less, more preferably 50% or less, and still more preferably 40% or less of the diameter of the sputtering face, to reduce the thickness of the target material toward an inner part of the sputtering face in the radial direction of the sputtering face. In the present invention, by providing such a ramp on the sputtering face, sufficient film thickness uniformity can be obtained at both the initial stage and the final stage of sputtering, particularly at the final stage. In the present invention, the initial stage of sputtering (or the initial stage of use of the sputtering target or the target material) means a time when power is consumed at the integral power consumption of, for example 200 kWh or less, preferably 100 kWh or less, and more preferably 50 kWh or less. In the present invention, the final stage (or the final stage of use of the sputtering target or the target material) of sputtering means a time when power is consumed, for example, at the integral power consumption of preferably 650 kWh or more, more preferably 700 kWh or more, and still more preferably 750 kWh or more. There is no particular limitation on depth (height) of ramp. The lower limit of the height is, for example, more than 0 mm, preferably 0.2 mm or more, and more preferably 0.5 mm or more, and the upper limit of the height is, for example, 10 mm or less, preferably 5 mm or less, and more preferably 3 mm or less. The present invention will be described in detail with reference to the following embodiments, but the present invention is not limited to the following embodiments. EMBODIMENTS The sputtering target of the present invention, as shown inFIG.11, includes a target material1whose sputtering face has a circular shape (including approximately circular shape). In the present invention, the sputtering face has a circular shape, but the shape of the entire target material is not particularly limited. In the embodiment shown inFIG.11, the target material1includes a flat circular (including approximately circular) first region A positioned at a center part of the sputtering face thereof, a flat ring-shaped second region B positioned around the first region, and a flat ring-shaped third region C positioned around the second region. In the present invention, the “sputtering face” means a surface of the target material that is subjected to sputtering, and the center part of the sputtering face means a part including a geometrical center of the sputtering face (e.g., a part including a center O of a circle in the shown embodiment). In the present invention, the “flat” means that no projection or recess is substantially formed. Here, the “no projection or recess is substantially formed” means that the projections and the recesses are not formed intentionally. Herein, surface roughness to the extent of about arithmetic average roughness of Ra=7 μm is permittable. In the present invention, the “ring-shaped” region means, as shown inFIG.11, a band-shaped region extending concentrically (including approximately concentrically) with an approximately fixed width (hereinafter referred to as “ring width”). The target material has a ramp provided to reduce the thickness of the target material, as mentioned above, at a position where erosion intensively concentrates, preferably, at a position where erosion concentrates most intensively, during sputtering. In the embodiment shown inFIG.11, there is a ramp between the second region B and the third region C, which will be described in detail below, in the target material1, and a thickness (T3) of the third region C is smaller than a thickness (T2) of the second region B. The thickness (T3) of the third region C is a thickness (T1) or more of the first region A, which will be described in detail below. In the embodiment shown inFIG.11, in the target material1, a diameter (W1) of the first region A is 14% or more, preferably 20% or more, more preferably 30% or more, still more preferably 31% or more, yet more preferably 32% or more, and most preferably 35% or more of a diameter (Rt) of the sputtering face, and is less than 60%, preferably less than 50%, and more preferably less than 40% of the diameter (Rt) of the sputtering face. When the diameter is in the above range, satisfactory film thickness uniformity can be obtained at the initial stage and the final stage, particularly at the final stage, of sputtering while achieving life prolongation of the sputtering target. An inner diameter (r) of the third region C is less than 90%, preferably 89% or less, more preferably 85% or less, still more preferably 80% or less, yet more preferably 75% or less, and further preferably 71% or less or 70% or less of the diameter (Rt) of the sputtering face, and is 60% or more, and more preferably 65% or more of the diameter (Rt) of the sputtering face. When the inner diameter is in this range, a ramp can be arranged at a position where erosion intensively concentrates, and thus satisfactory film thickness uniformity can be obtained at the initial stage and the final stage, particularly at the final stage, of sputtering while achieving the life prolongation of the sputtering target. Besides, intensive deposition can be suppressed in the center and the middle part, particularly in the middle part, of a thin film that can be formed on the substrate. As a result, a difference in thickness between the middle part and the end part can be decreased, thus making it possible to obtain uniform and excellent film thickness distribution over the entire area of the substrate. A ratio (T3/W3) of the thickness (T3) of the third region C to a ring width (W3) of the third region C is in a range of, for example, 0.1 or more, preferably 0.2 or more, and more preferably 0.3 or more, and is 1.1 or less, preferably 0.6 or less, and more preferably 0.5 or less. When the ratio is in this range, the position of the ramp can be adjusted more appropriately, and thus satisfactory film thickness uniformity can be obtained at the initial stage and the final stage, particularly at the final stage, of sputtering while achieving life prolongation of the sputtering target. The target material will be described in detail below. Target Material The target material can be made of a material selected from the group consisting of, for example, metals such as aluminum (Al), chromium (Cr), iron (Fe), tantalum (Ta), titanium (Ti), zirconium (Zr), tungsten (W), molybdenum (Mo), and niobium (Nb), and alloys thereof. Materials constituting the target material are not limited thereto. The material of the target material is preferably aluminum, and it is particularly preferred to use aluminum having a purity of, for example, 99.99% or more, and more preferably 99.999% or more. The material of the target material is also preferably an aluminum alloy. Such an aluminum alloy may contain metals, such as copper and silicon, and the content thereof is, for example, 2% by weight or less, and preferably 1% by weight or less. In the embodiment shown inFIG.11, the target material has a sputtering face including a first region A, a second region B, and a third region C. InFIG.11, the diameter (Rt) of the sputtering face is, for example, in a range of 260 mm to 325 mm. Preferably, a reverse face (surface opposite to the sputtering face) of the target material has a circular outer periphery. The reverse face has a diameter from the center to outer periphery in a range, for example, of 260 mm to 440 mm. First Region A In the embodiment shown inFIG.11, the first region A is a flat and circular region positioned in the center of the sputtering face. The diameter (W1) of the first region A is, for example, 10 mm to 180 mm, preferably 20 mm to 160 mm, and more preferably 30 mm to 130 mm. The thickness (T1) of the first region A is, for example, 10 mm to 35 mm, preferably 11 mm to 30 mm, and more preferably 12 mm to 25 mm. The first region A makes it possible to obtain such an effect that intensive deposition of a film onto the center and the middle part of the substrate during sputtering can be suppressed. Second Region B In the embodiment shown inFIG.11, the second region is a flat ring-shaped region that can be arranged apart from or adjacent to the circumference of the first region. The ring width (W2) of the second region B is, for example, 5 mm to 75 mm, preferably 10 mm to 50 mm, and more preferably 20 mm to 30 mm. The thickness (T2) of the second region B is, for example, 5 mm to 40 mm, preferably 10 mm to 30 mm, and more preferably 12 mm to 25 mm. The second region B can increase a deposition amount of a film onto the outer peripheral part at the middle part and the center of the substrate during sputtering. There is no particular limitation on distance (W2a) between the inner circumference of the second region B and the outer periphery of the first region A (width of an inside ramp part). The distance is, for example, 0 mm to 60 mm, preferably 5 mm to 40 mm, and more preferably 10 mm to 30 mm. The thickness (T2) of the second region B is larger than the thickness (T1) of the first region A, and a difference thereof is, for example, 0.5 mm to 10 mm, preferably 1 mm to 5 mm, and more preferably 1.5 mm to 4 mm. Providing a ramp can suppress intensive deposition of a film onto the middle part of the substrate during sputtering. Preferably, the thickness (T2) of the second region B is equivalent to the thickness of the target material of the conventional standard sputtering target. The sputtering face of the target material1includes a recessed face composed of the first region A and may further include a recessed face composed of the third region C, which will be described in detail below. These recessed faces will be formed lower than the conventional sputtering face. The recessed faces exist at positions where erosion intensively concentrates, so that the distance between the target material and the substrate (TS distance) will not be reduced in comparison with a conventional one. Therefore, the sputtering material in the present invention can have improved film thickness uniformity of a thin film that can be formed on the substrate at the initial stage and the final stage of sputtering. Surprisingly, the thickness (T2) of the second region B is equivalent to the thickness of a conventional target material but life prolongation of the sputtering target can be achieved. Third Region C In the present invention, the sputtering material may include the third region C. In the embodiment shown inFIG.11, the third region is a flat ring-shaped region that can be arranged apart from or adjacent to the circumference of the second region. The ring width (W3) of the third region C is, for example, 1 mm to 100 mm, preferably 20 mm to 80 mm, and more preferably 30 mm to 60 mm. The thickness (T3) of the third region C is, for example, 7 mm to 30 mm, preferably 10 mm to 27 mm, and more preferably 12 mm to 25 mm. The third region C can provide the improved film thickness uniformity of a thin film that can be formed on the substrate at the initial stage and the final stage, particularly at the final stage, of sputtering. There is no particular limitation on distance (W2c) between the inner circumference of the third region C and the outer periphery of the second region B (width of the outside ramp part). For example, the distance is 0 mm to 20 mm, preferably 1 mm to 10 mm, and more preferably 2 mm to 6 mm. The thickness (T3) of the third region C is smaller than the thickness (T2) of the second region B, and a difference thereof is, for example, 0.3 mm to 10 mm, preferably 0.5 mm to 6 mm, and more preferably 1 mm to 3 mm. As mentioned above, such a ramp is provided at a position where erosion intensively concentrates (or a position where erosion intensively concentrates can be formed by the ramp), giving both life prolongation of the sputtering target and improvement in film thickness uniformity at the initial stage and the final stage, particularly at the final stage, of sputtering. The thickness (T3) of the third region C is equal to or larger than the thickness (T1) of the first region A, and a difference thereof is, for example, 0 mm to 10 mm, preferably 0.5 mm to 8 mm, and more preferably 1 mm to 6 mm. This difference in height can increase a deposition amount of a film onto the outer periphery part of the substrate with respect to the center of the substrate during sputtering. Fourth Region D The present invention may further include a fourth region D outside the third region C (for example, see,FIG.15). A ring width (W4) of the fourth region D is, for example, of 1 mm to 30 mm, preferably 3 mm to 20 mm, and more preferably 5 mm to 15 mm. The thickness (T4) of the fourth region D is the same as the thickness (T2) or less than the thickness (T2), for example, 5 mm to 40 mm, preferably 10 mm to 30 mm, and more preferably 12 mm to 25 mm. There is no particular limitation on distance (W4c) between an inner circumference of the fourth region D and the outer periphery of the third region C (width of the ramp portion). The distance is, for example, 0 mm to 30 mm, preferably 0.1 mm to 10 mm, and more preferably 0.2 mm to 5 mm. The fourth region D can provide a space to mount a jig (contamination plate) for covering the target material so as prevent re-sticking thereto the sputter particles which generated during sputtering but did not reach the substrate. In other words, the fourth region D can control abnormal discharge due to excessive deposition caused by the re-sticking. Region X The present invention may further include a region X outside the fourth region D (for example, see,FIG.15). The region X is a ramp that can be formed on a side surface of the target material. Neither the region X nor the ramp inside the region D falls within the scope of “ramp” between the above second region B and third region C.A ring width (Wx) of the region X is, for example, 1 mm to 10 mm, preferably 2 mm to 7 mm, and more preferably 3 mm to 5 mm.A thickness (Tx) of the region X is, for example, 8 mm to 32 mm, preferably 10 mm to 30 mm, and more preferably 12 mm to 25 mm.The region X can eliminate clearance with the contamination plate, suppressing abnormal discharge during sputtering. Others In the present invention, there is no particular limitation on angle θ1that can be formed by the first region A and the second region B (hereinafter sometimes referred to as “inclination angle θ1”) if the angle θ1is smaller than a vertical angle (θ1=90°) (more specifically, see the angle θ1shown inFIG.15). The lower limit of the inclination angle θ1is preferably 1° or more, more preferably 1.5° or more, still more preferably 2° or more, and particularly preferably 5° or more, and the upper limit of the inclination angle θ1is preferably 70° or less, more preferably 50° or less, still more preferably 30° or less, and particularly preferably 10° or less. Specifically, the inclination angle θ1is in a range of 1°≤θ1≤70°, preferably 1.5°≤θ1≤50°, more preferably 2°≤θ1≤30°, and still more preferably 5°≤θ1≤10°. There is no particular limitation on angle θ2that can be formed by the second region B and the third region C (hereinafter sometimes referred to as “inclination angle θ2”) as long as the angle θ2is smaller than a vertical angle (θ2=90°) (more specifically, see the angle θ2shown inFIG.15). The lower limit of the inclination angle θ2is preferably 1° or more, more preferably 5° or more, still more preferably 10° or more, and particularly preferably 15° or more, and the upper limit of the inclination angle θ2is preferably 70° or less, more preferably 50° or less, still more preferably 30° or less, and particularly preferably 25° or less. More specifically, the inclination angle θ2is in a range of 1°≤θ2≤70°, preferably 5°≤θ2≤50°, more preferably 10°≤θ2≤30°, and still more preferably, 15°≤θ2≤25°. When the inclination angles θ1, θ2each is in the above range, the film thickness uniformity of a thin film that can be formed on the substrate is improved during sputtering, and abnormal discharge that can be generated at such corners can be suppressed. Supporting Member As shown inFIG.12, the sputtering target10may include a supporting member2to fix the sputtering target10to a sputtering apparatus such as a magnetron sputtering apparatus. The supporting member2is made of metal and can be made from a material selected from the group consisting of metals such as aluminum, copper, iron, chromium, nickel, and alloys thereof. The supporting member2is mainly composed of a ring for receiving the target material1and may further comprise a flange capable of fixing the supporting member2to the sputtering device. Preferably, the ring and the flange of the supporting member2are integrally formed from the above materials by cutting. There is no particular limitation on thickness (i.e., wall thickness) of the ring. The thickness is, for example, 5 mm to 20 mm, and preferably 10 mm to 15 mm. The thickness of the ring may be or may not be uniform. For example, as shown inFIG.12, the ring may be formed in a manner that its thickness increases as it gets close to the flange. As is described in detail below, the target material1is preferably bonded to the ring of the supporting member2by welding such as electron beam (EB) welding, or by joint via a soldering material which will be described in detail below. Preferably, the outer periphery of the ring of the supporting member2is formed flush with the outer periphery of the target material1. The outer periphery of the target material1and the supporting member2may be tapered, as shown inFIG.12. The flange of the supporting member2may be formed with a plurality of holes which allows the supporting member2to fix to the sputtering apparatus via fasteners such as bolts. There is no particular limitation on thickness of the flange. The thickness is, for example, 5 mm to 15 mm, preferably 8 mm to 12 mm, and more preferably 10 mm to 11 mm. Further, it is preferred that the thickness of the flange is uniform. There is no particular limitation on height of the supporting member2. The height is, for example, 10 mm to 30 mm, preferably 20 mm to 29 mm, and more preferably 25 mm to 29 mm. There is no particular limitation on entire height (i.e., distance from the top face of the second region B of the target material1to a reverse face of the flange of the supporting member2) of the sputtering target10. The height is, for example, 10 mm to 70 mm, preferably 13 mm to 65 mm, and more preferably 15 mm to 60 mm. In the embodiment shown inFIG.13, the sputtering target20may include, for example, a backing plate3which allows the sputtering target20to fix to a sputtering apparatus such as a magnetron sputtering apparatus and which can dissipate heat from the target material1. There is no particular limitation on backing plate3as long as it is made of a conductive material. Preferred is the baking plate3made of a material such as metal or alloy thereof. Examples of the metal and the alloy thereof include copper, copper alloy, aluminum, aluminum alloy, titanium, titanium alloy, tungsten, tungsten alloy, molybdenum, molybdenum alloy, tantalum, tantalum alloy, niobium, niobium alloy, stainless steel, and the like. From the viewpoint of workability, mechanical strength, durability, heat dissipation, and the like, it is preferred to use copper. Among them, from the viewpoint of high heat conductivity and high electrical conductivity, it is preferred to use oxygen-free copper (having a purity of 99.96% or more and oxygen concentration of 10 ppm or less). There is also no particular limitation on size and shape of the backing plate3. As shown inFIG.13, by using a soldering material4, the target material1can be joined to the backing plate3. There is no particular limitation on soldering material4. The soldering material4is a material containing metal or alloy having a low melting point (e.g., 723 K or lower). The material is made of metal selected from the group consisting of, for example, indium (In), tin (Sn), zinc (Zn), lead (Pb), silver (Ag), copper (Cu), bismuth (Bi), cadmium (Cd), and antimony (Sb), and alloys thereof. More specifically, examples thereof include In, In—Sn, Sn—Pb, Sn—Zn, Sn—Zn—In, In—Ag, Sn—Pb—Ag, Sn—Bi, Sn—Ag—Cu, Pb—Ag, Zn—Cd, Pb—Sn—Sb, Pb—Sn—Cd, Pb—Sn—In, Bi—Sn—Sb, and the like. The backing plate3may be formed with a plurality of holes to allow the backing plate3to fix to a sputtering apparatus via fasteners such as bolts. There is no particular limitation on thickness of the backing plate3. The thickness is, for example, 5 mm to 30 mm, preferably 7 mm to 29 mm, and more preferably 10 mm to 25 mm. There is no particular limitation on entire height of the sputtering target20(i.e., distance from the top face of the second region B of the target material1to the reverse face of the baking plate3). The height is, for example, 10 mm to 70 mm, preferably 13 mm to 65 mm, and more preferably 15 mm to 60 mm. Method for Manufacturing Sputtering Target According to the method for manufacturing a sputtering target of the present invention, for example, first, materials of a target materials are mixed and melted, followed by casting to form an ingot called a slab. The ingot is subjected to rolling and a heat treatment, followed by cutting into an optional shape with optional size, for example, a disc shape to obtain a preliminary formed body of the target material. After the preliminary formed body of the target material and a preliminary manufactured supporting member or backing plate are welded or joined via a soldering material or the like, the preliminary formed body of the target material is formed into a desired shape by cutting to produce a sputtering target. In the case of joint using a soldering material, the preliminary formed body of the target material and the supporting member or the backing plate can be joined using the above soldering material at a temperature in a range of 205° C. to 240° C. by vacuum joining. In the embodiment shown inFIG.12, the reverse face of the target material may be subjected to cutting across a joining surface between the target material and the supporting member by cutting. By cutting, a conical recess with a center of circle being a top may be formed. The depth to the top of such recess is usually 1 mm to 3 mm. When the reverse face of the target material has the above recess, the thickness (T1) of the first region A is a distance between the top face of the region A and a bottom face of the region A of which thickness is minimum (i.e., distance between the top face of the region A and the top of the recess). The thickness (T2) of the second region B is a distance between the top face of the region B and the bottom face of the region B of which thickness is maximum. The thickness (T3) of the third region C is a distance between the top face of the region C and the bottom face of the region C of which thickness is maximum (except for a joint part between the target material and the supporting member). In the present invention, the method for manufacturing a sputtering target is not limited to the above method. Sputtering Apparatus There is no particular limitation on sputtering apparatus, and commercially available sputtering apparatuses can be used without limitation. Among them, it is preferred to use a magnetron sputtering apparatus. In the magnetron sputtering apparatus, an inert gas made into plasma (or being ionized), e.g., argon, can be captured by using magnet, so that target atoms can be effectively sputtered from the target material, thus making it possible to increase a deposition rate of film onto the substrate. As a magnetron sputtering apparatus, an apparatus “ceraus Z-1000” manufactured by ULVAC, Inc is preferred, and an apparatus employing an electromagnet type magnet is particularly preferred. Alternatively, an apparatus “Endura” manufactured by Applied Materials, Inc. may be used. Among them, an apparatus using a Dura-type magnet is preferred. Substrate There is no particular limitation on substrate in as long as a thin film can be formed by using the above sputtering target and sputtering device. Examples of the substrate include a metal wafer made of silicon, copper, or the like, an oxide wafer made of zinc oxide, magnesium oxide, a glass substrate made of quartz, pyrex, and a resin substrate. There is no particular limitation on shape of the substrate, and circle is preferred. Further, there is no particular limitation on size of the substrate, and the size is, for example, 100 mm to 450 mm, preferably 150 mm to 300 mm, and more preferably 200 mm. Life Time of Sputtering Target The sputtering target of the present invention can have a life time at the integral power of 650 kWh to 750 kWh or more. The life time as used herein is a threshold having film thickness uniformity, e.g., integral power consumption by which sputtering can be performed without excessing 6.4%. In the present invention, such life time can be obtained as a result that the sputtering target of the present invention comprises the target material having the above shape and size. Among them, particularly such life time can be obtained because the sputtering face of the target material comprises the first region A, the second region B, and the third region C, and the diameter (W1) of the first region A is 14% or more and less than 60% of the diameter (Rt) of the sputtering face, and the inner diameter (r) of the third region is less than 90% of the diameter of the sputtering face. Film Thickness Uniformity of Thin Film to Be Formed on Substrate The film thickness uniformity of a thin film that can be formed on the substrate by the sputtering target of the present invention can be calculated from the formula: (max−min)/(max+min)×100(%) based on the maximum value (max) and the minimum value (min) of a value of a film thickness t (μm) calculated by the formula: t=Rv/Rs×106according to sheet resistance Rs(Ω/□) measured at the predetermined nine points on the thin film that can be formed on the substrate and known volume resistivity Rv(Ω·m) of the thin film. In the case of an aluminum thin film, Rv=2.9×10−8(Ω·m). The sheet resistance (Ω/□) of the thin film can be measured by using, for example, Omnimap RS35c manufactured by KLA-Tencor Corporation. The predetermined nine points where measurement is to be performed, for example, when the substrate having a diameter of 200 mm is used, for example, as shown inFIG.14, are a center and positions 47.5 mm away from the center (middle parts) and positions 95 mm away from the center (end parts) existing along each of an X axis and a Y axis (total 9 points). In the present invention, the film thickness uniformity is, for example, less than 6.4%, preferably less than 6.3%, and more preferably less than 6.0%. At the initial stage of sputtering (e.g., 0 and 200 kWh), the film thickness uniformity may be less than 6.4%, preferably less than 6.3%, and more preferably less than 6.0%. At the final stage (particularly at the time after a long time of 750 kWh or more has passed), the film thickness uniformity may still be less than 6.4%, preferably less than 6.3%, and more preferably less than 6.0%. As mentioned above, in the present invention, excellent film thickness uniformity can be obtained at the initial stage and the final stage, particularly at the final stage, of sputtering. In the following Examples, the present invention will be described in detail, but the present invention is not limited to the following Examples. EXAMPLES Example 1 An ingot (slab) was obtained by adding 0.5% by weight of copper to aluminum having a purity of 99.999% and melting the mixture, and casting the melt. The ingot was subjected to rolling and a heat treatment, followed by cutting into a disc shape using a milling machine to obtain a preliminary formed body of a target material having a diameter of 325 mm to a thickness of 18 mm. Such a preliminary formed body of the target material and the backing plate having a shape shown inFIG.13were joined together using a soldering material (In) at a temperature of 200° C. Furthermore, the preliminary formed body of the target material was formed into a shape shown inFIG.15by cutting with a lathe to produce a sputtering target. Each size of the target material is as mentioned below. Each symbol represents the corresponding region shown inFIG.15. The target material of the sputtering target according to Example 1 had a “ramp (W2c)” at a position where erosion concentrates most intensively as shown inFIG.15andFIG.18.Rt: 312 mmr: 215 mmT1: 13 mmT2: 15 mmT3: 14 mmT4: 15 mmTx: 12 mmθ1: 5.7°θ2: 21.8°W1: 120 mmW2: 25 mmW2a: 20 mmW2c: 2.5 mmW3: 35 mmW4: 10 mmW4c: 0.5 mmWx: 3 mmW1/Rt100=38.5%r/Rt×100=68.9%T3/W3=0.4 Height of the entire sputtering target (distance from the top face of the second region to the reverse face of the backing plate): 27.3 mm Example 2 In the same manner as in Example 1, a sputtering target of the Example 2 was produced. Each size of the target material is as mentioned below. Each symbol represents the corresponding region as shown inFIG.15. The target material of the sputtering target of Example 2 was a “ramp (W2c)” at a position where erosion concentrates most intensively as shown inFIG.15andFIG.18.Rt: 312 mmr: 220 mmT1: 13 mmT2: 15 mmT3: 13 mmT4: 15 mmTx: 12 mmθ1: 5.7°θ2: 21.8°W1: 120 mmW2: 25 mmW2a: 20 mmW2c: 5 mmW3: 32.5 mmW4: 10 mmW4c: 0.5 mmWx: 3 mmW1/Rt×100=38.5%r/Rt×100=70.5%T3/W3=0.4 Height of the entire sputtering target (distance from the top face of the second region to the reverse face of the backing plate): 27.3 mm Comparative Example 1 In the same manner as in Example 1, a sputtering target of Comparative Example 1 was produced. Each size of the target material is as mentioned below. The target material of the sputtering target of Comparative Example 1 had a ramp only in a region of X (standard shape).Rct: 312 mmrc: 306 mmTc1: 15 mmTcx: 12 mmWcx: 3 mm Height of the entire sputtering target (distance from the top face of the second region to the reverse face of the backing plate): 27.3 mm Comparative Example 2 In the same manner as in Example 1, a sputtering target of the Comparative Example 2 was produced. Each size of the target material is as mentioned below. The target material of the sputtering target of Comparative Example 2 had no “ramp” at a position where erosion concentrates most intensively.Rct: 312 mmrc: 306 mmTc1: 13 mmTc2: 15 mmTcx: 12 mmθc1: 5.7°Wc1: 120 mmWc2: 73 mmWc2a: 20 mmWcx: 3 mmWc1/Rct×100=38.5% Height of the entire sputtering target (distance from the top face of the second region to the reverse face of the backing plate): 27.3 mm Sputtering Using a magnetron sputtering apparatus (ceraus Z-1000 manufactured by ULVAC, Inc., magnet: electromagnet type) and the sputtering targets of Examples and Comparative Examples, a thin film was formed on a substrate having a diameter of 200 mm (silicon substrate manufactured by LG Siltron, Inc.) under the following conditions. <Sputtering Conditions> Output: 10 kWInert gas: argonSubstrate temperature: 25° C.Distance between target and substrate (TS distance): 40 mmEvaluation of Sputtering Target A sputtering operation was performed with respect to each sputtering target of Examples and Comparative Examples under the above conditions over a range of 0 to 800 kWh. A relation between the integral power consumption (kWh) and the film thickness uniformity (%) is shown inFIG.17. A residual thickness and an erosion amount at a position of the sputtering face (at 700 kWh in Comparative Example 1, or 800 kWh in Comparative Example 2, Example 1, and Example 2) is shown inFIG.18. As shown fromFIG.17, in the sputtering targets of Example 1 and Example 2, the film thickness uniformity can be maintained at less than 6% at the initial stage and the final stage, particularly at the final stage, of sputtering at an integral power consumption of 650 kWh to 750 kWh, and the target material was be able to use during a period longer than that of the conventional target materials. Whereas, the film thickness uniformity was degraded beyond 6% when the integral power consumption exceeds 500 kWh in Comparative Example 1 or the integral power consumption exceeds 650 kWh in Comparative Example 2. These results may be caused by the existence of a ramp provided to reduce the thickness of the target material at a position where erosion intensively concentrates in Examples 1 and 2. It is considered that, because of the existence of such a ramp, the erosion region moves (shifts) to the edge side of the target material, thus decreasing a difference in thickness generated at the middle part, the end part, and the center of the substrate, leading to an improvement in film thickness uniformity at the final stage (FIG.7toFIG.9, andFIG.18). INDUSTRIAL APPLICABILITY The sputtering target of the present invention can be employed in commercially available sputtering apparatus, particularly a magnetron sputtering apparatus, and a thin film having excellent film thickness uniformity can be formed on a substrate during sputtering, particularly at the final stage of sputtering. This is highly effective in formation of a thin film by sputtering. DESCRIPTION OF REFERENCE NUMERALS 1Target material2Supporting member3Backing plate4Soldering material10Sputtering target20Sputtering targetA First regionB Second regionC Third regionO Center of sputtering face | 42,773 |
11862444 | WORKING EXAMPLES Example 1 MoO3powder (Molymet) having an average particle size of 4.4 μm is reduced at 550° C. in an H2atmosphere (dew point τ(H2)=10° C.) for 17 minutes in a furnace. The Mo oxide powder obtained has an oxygen content of 73.1 at. %. It is placed in a graphite mould having the dimensions 260×240 mm and a height of 50 mm and densified in a hot press under vacuum at a pressing pressure of 45 MPa, a temperature of 750° C. and a hold time of 120 minutes. The compacted component displays a relative density (pore determination on a metallographic polished section) of 96% and comprises an MoO2phase in a proportion of 10% by volume, an MoO3phase in a proportion of 7% by volume and a proportion of substoichiometric molybdenum oxide phases of 83% by volume. The substoichiometric molybdenum oxide phase component is formed predominantly by Mo4O11. The determination of the phase composition in this and the following examples is carried out by means of Raman mapping and is explained in detail at the end of the examples. Example 2 36.2 mol % of MoO2powder (Plansee) and 63.8 mol % of MoO3powder (Molymet) are mixed and homogenized for 30 minutes in a ball mill equipped with zirconium oxide mixing balls (diameter 10 mm). The resulting powder mixture having an oxygen content of 72.5 at. % is placed in a graphite mould having a diameter of 70 mm and a height of 50 mm and densified in a spark plasma sintering (SPS) plant under vacuum at a pressing pressure of 40 MPa, a temperature of 775° C. and a hold time of 120 minutes. The compacted component has a relative density of 98%. It consists of an MoO2phase in a proportion of 2.7% by volume and a proportion of substoichiometric molybdenum oxide phases of 97.3% by volume in total. An MoO3phase could not be detected. The substoichiometric molybdenum oxide phase component is formed to an extent of 53% by volume by Mo4O11. Example 3 The proportion of coarse particles and agglomerates is sieved out from MoO2powder (Plansee SE) in a sieve (mesh opening 32 μm). 24 mol % of the MoO2powder obtained are mixed with 70 mol % of MoO3powder (Molymet) and 6 mol % of tantalum powder in a ploughshare mixer (Lodige) for 20 minutes so as to obtain a homogeneous distribution between the powder components. The powder mixture obtained is placed in a graphite mould having the dimensions 260×240 mm and a height of 50 mm and densified in a hot press under vacuum at a pressing pressure of 40 MPa, a temperature of 750° C. and a hold time of 60 minutes. The compacted component has a relative density of 95.6%. The target material obtained comprises an MoO2phase in a proportion of 10.3% by volume, an MoO3phase in a proportion of 19.2% by volume, substoichiometric molybdenum oxides in a total proportion of 68.4% by volume and a Ta2O5phase in a proportion of 2.1% by volume. The predominant component of the substoichiometric molybdenum oxides is Mo4O11in a proportion of 49.4% by volume. The further substoichiometric molybdenum oxides are (presumably) Mo18O52and a not yet known substoichiometric molybdenum oxide having an unknown composition. The Raman spectrum of this substoichiometric molybdenum oxide is shown inFIG.5. The microstructure of the target material determined by means of Raman mapping is shown inFIG.8. Regions comprising MoO2phase, regions comprising MoO3phase and regions comprising Ta2O5phase are discernible in the microstructure; these various phases are embedded as islands in a contiguous network formed by the substoichiometric molybdenum oxides Mo4O11, Mo18O52and the substoichiometric molybdenum oxide having an unknown composition. Example 4 Example 4 differs from Example 3 by variation of the hot pressing parameters; manufacture of the powder batch is carried out as in Example 3. The powder mixture is placed in a graphite mould having the dimensions 260×240 mm and a height of 50 mm and densified in a hot press under vacuum at a pressing pressure of 40 MPa, a temperature of 750° C. and a hold time of 240 minutes. The compacted component has a relative density of 97%. The target material obtained comprises an MoO2phase in a proportion of 8.1% by volume, an MoO3phase in a proportion of 5.5% by volume, substoichiometric molybdenum oxides in a total proportion of 85% by volume and a Ta2O5phase in a proportion of 1.4% by volume. The predominant component of the substoichiometric molybdenum oxides is Mo4O11in a proportion of 59.1% by volume.FIG.9shows the microstructure of the target material produced by means of Raman mapping. Example 5 Example 5 differs from Examples 3 and 4 by variation of the hot pressing parameters; the manufacture of the powder batch is carried out as in Example 3. The powder mixture is placed in a graphite mould having the dimensions 260×240 mm and a height of 50 mm and densified in a hot press under vacuum at a pressing pressure of 40 MPa, a temperature of 790° C. and a hold time of 120 minutes. The compacted component has a relative density of 99.7%. The target material obtained comprises an MoO2phase in a proportion of 5.7% by volume, substoichiometric molybdenum oxides in a proportion of 91.9% by volume and Ta2O5phase in a proportion of 2.4% by volume. An MoO3phase is not detectable. Among the substoichiometric molybdenum oxides, Mo4O11with a proportion of 47.2% by volume and the substoichiometric molybdenum oxide having an unknown composition with a proportion of 31.4% by volume make up the largest part. The Raman spectrum of the still unknown substoichiometric molybdenum oxide is depicted inFIG.5. The microstructure of the target material produced by means of Raman mapping is shown inFIG.10. To determine the proportions by volume of the various phases and the density of the target material, a metallographic polished section was produced by means of dry preparation from a representative part of a specimen by cutting a specimen having an area of about 10-15×10-15 mm2to size in a dry cutting process (diamond wire saw, bandsaw, etc.), cleaning it by means of compressed air, subsequently embedding it hot and conductively (C-doped) in phenolic resin, grinding and polishing it. Since at least the MoO3phase proportion is water-soluble, dry preparation is important. The polished section obtained in this way was subsequently analysed under an optical microscope. For the positionally resolved determination of the molybdenum oxide phases, use was made of a Raman microscope (Horiba LabRAM HR800) in which a confocal optical microscope (Olympus BX41) is coupled with a Raman spectrometer. The surface to be analysed was scanned over an area of 1×1 mm2by means of a focus laser beam (He—Ne laser, wavelength λ=632.81 nm, 15 mW total power) point-by-point in steps of 10 μm (the sample surface to be examined was fixed on a motorized XYZ table and the latter was moved). A complete Raman spectrum was produced for each one of the 100×100 measurement points (“Raman mapping”). Raman spectra are obtained from the backscattered radiation and are wavelength-dispersively split up by means of an optical grating (300 lines/mm; spectral resolution: 2.6 cm−1) and recorded by means of a CCD detector (1024×256 pixel multichannel CCD; spectral range: 200-1050 nm). In the case of a microscope objective having 10× enlargement and a numerical aperture NA of 0.25, which serves for focussing the laser beam from the Raman spectrometer, it was possible to achieve a theoretical measurement point size of 5.2 μm2. The excitation energy density (3 mW/μm2) is selected low enough to avoid phase transformations in the specimen. The penetration depth of the excitation radiation is limited to a few microns in the case of molybdenum oxides (in the case of pure MoO3here about 4 μm; but since a mixture of different phases is analysed, precise indication of the penetration depth is not possible). For each measurement point, the Raman signal was averaged over an acquisition time of 4 s, which gave a sufficiently good signal-to-noise ratio. A two-dimensional depiction of the surface composition of the specimen was produced by automated evaluation of these Raman spectra (evaluation software Horiba LabSpec 6) and the domain size, proportions by area, etc., of the various phases can be determined quantitatively therefrom. For precise identification of a molybdenum oxide phase, reference spectra of previously synthesized reference specimens or reference specimens of relatively large homogeneous specimen regions are recorded, with it being ensured that a reference spectrum corresponds precisely to one metal oxide phase. InFIGS.2to7typical reference spectra of MoO2, MO4O11, Mo18O52, a previously unknown substoichiometric MoOxoxide, MoO3and Ta2O5are shown (the intensity (count) of the scattered light versus the Raman shift (cm−1) is shown in the individual spectra). The analysis and assignment of the Raman spectra is carried out using the “Multivariant Analysis Modules” of the abovementioned evaluation software by means of the CLS method (classical least squares fitting). The specimen spectrum S is for this purpose represented as a linear combination of the individual normalized reference spectra Ri, where ciis the respective weighting factor and Δ is an offset value, S=ΣciRi+Δ. A colour corresponding to a metal oxide phase is subsequently assigned to each measurement point, with only the phase having the greatest weighting factor cibeing used for the colour assignment in each case. The magnitude (the absolute value) of the weighting factor cidetermines the brightness of the measurement point. This procedure is justified since the spectrum of one measurement point can generally be unambiguously assigned to a single metal oxide phase. For the objective used, a specimen spectra was obtained from all 100×100 measurement points, even when the measurement was made on a pore. In this case, the signal originated from a lower region located under the pore. If no Raman spectrum is obtained for individual measurement points, e.g. owing to a pore, this can be excluded from the determination of the proportions by area, i.e. the volume occupied by the pores of the target material is excluded from the total volume. The reported volumes for the individual molybdenum oxide phases therefore on their own add up to 100% without the pore volume. The method of analysis described here is particularly suitable for determining the relative proportions of the phase of various Mo oxides. In a repeat measurement (one specimen was measured 3 times in succession), a relative measurement error of ±10% (based on the phase component determined in each case) was found. The relative measurement error in the % by volume determination of the dopant oxides (e.g. Ta2O5) on the other hand was ±25%. It is therefore possible that the measured percentages by volume in the examples deviate slightly from the weighed-out amounts of dopant metal (e.g. tantalum) or dopant metal oxide (e.g. Ta2O5). The determination of the relative density is carried out by means of digital image analysis of optical micrographs of the metallographic polished section, in which the relative proportion by area of the pores is determined. For this purpose, preparation of the specimens was followed by recording of in each case three bright field micrographs having a size of 1×1 mm with 100× enlargement, with zones of obvious cavities or other damage such as scratches caused by dry preparation being avoided where possible. The images obtained were evaluated by means of the digital image analysis software implemented in the IMAGIC image data bank. For this purpose, the pore component (dark) was marked on the image as a function of the grey scale by means of a histogram. The lower limit of the interval was set at 0 (=black). On the other hand, the upper limit has to be estimated subjectively with the aid of the grey scale intensity histogram (255=white). The image region to be measured was set (ROI) in order to exclude the scale bars. The relative proportion by area (in percent) and the image coloured according to the selected grey scale interval (coloured means that this pixel was included in the measurement and accordingly counted as pore) is obtained as result. The value for the relative density was determined as arithmetic mean of three such porosity measurements. Example 6 In a series of experiments, the molybdenum-tantalum oxide target produced as described in Example 3 was nonreactively sputtered under different process conditions in order to check the reproducibility and process stability by means of the properties of the layer. Here, the reflectivity of the layers produced was used as criterion for the assessment. To determine the reflectivity, glass substrates (Corning Eagle XG, 50×50×0.7 mm3) were coated with molybdenum-tantalum oxide and a covering layer of 200 nm of Al. The reflection was measured through the glass substrate using a Perkin Elmer Lambda 950 photospectrometer. In order to obtain a very low reflectivity, the layer thickness of the molybdenum oxide was varied in the range from 40 to 60 nm in a first experiment, with the best result being able to be achieved at a layer thickness of 51 nm. This layer thickness was subsequently used and kept constant for all further experiments. Results from this series of experiments are shown inFIG.11. In the experiments, the sputtering power was varied in the range from 400 W to 800 W and the process pressure of the argon was varied in the range from 2.5×10−3mbar (11 sccm) to 1.0×10−2mbar (47 sccm). It can be seen that both the increase in the power by a factor of 2 from 400 W to 800 W and also the increase in the process pressure by a factor of 2 from 5×10−3mbar to 1×10−2mbar have only a negligible influence on the measured properties of the layer. The high process stability of the sputtering process using a molybdenum-tantalum oxide target was thus confirmed. Reproducible results can be achieved in a wide process window, in complete contrast to the reactive sputtering process using a metallic target, which is highly unstable. | 14,089 |
11862445 | DESCRIPTION OF EMBODIMENTS Hereinafter, an imaging mass spectrometer according to an embodiment of the present invention will be described with reference to the accompanying drawings. FIG.1is a schematic block configuration diagram of the imaging mass spectrometer of the present embodiment. The imaging mass spectrometer of the present embodiment includes a measurement unit1, a data analyzing unit2, an input unit3, and a display unit4. In addition, a Raman spectroscopic imaging measurement device5is illustrated as a device, which is different from the measurement unit1, for acquiring data to be processed by the data analyzing unit2although not a component of the imaging mass spectrometer. The measurement unit1executes imaging mass spectrometry on a sample100, and is a mass spectrometer obtained by combining an atmospheric pressure matrix-assisted laser desorption ionization (AP-MALDI) method for irradiating the sample with laser light under an atmospheric pressure atmosphere to ionize a substance in the sample and an ion-trap time-of-flight mass spectrometer (IT-TOFMS), for example, as disclosed in Patent Literature 1 and the like. In the measurement unit1, for example, by scanning a position irradiated with laser light for ionization in a two-dimensional region on the sample100such as a biological tissue section, mass spectrometry can be performed for a large number of measurement points (substantially micro areas) in the two-dimensional region. On the other hand, the Raman spectroscopic imaging measurement device5executes Raman spectroscopic analysis for each of a large number of measurement points set in a two-dimensional region on the same sample100as that subjected to imaging mass spectrometry to obtain a spectrum of Raman light by the sample100. The data analyzing unit2receives mass spectrometry data for each measurement point (micro area) obtained by the measurement unit1and spectrum data obtained by the Raman spectroscopic imaging measurement device5, and performs analysis processing based on these data. In order to perform characteristic analysis processing described later, the data analyzing unit2includes, as functional blocks, an MS imaging data storage section20, a Raman imaging data storage section21, an MS imaging graphic creation section22, a Raman imaging graphic creation section23, a signal intensity normalization processor24, a spatial resolution adjustment processor25, a statistical analysis processor26, and a display processor27. Although the data analyzing unit2can be configured by a hardware circuit, the data analyzing unit2is generally a computer such as a personal computer or a high-performance workstation. Each of the functional blocks can be embodied by executing dedicated data analysis software installed in the computer on the computer. In this case, the input unit3is a keyboard or a pointing device (such as a mouse) attached to the computer, and the display unit4is a display monitor. Next, an example of characteristic operation in the imaging mass spectrometer of the present embodiment will be described with reference toFIG.2. The measurement unit1executes scan measurement over a predetermined mass-to-charge ratio m/z range for each of a large number of measurement points set in a measurement region having a predetermined size on the sample100such as a biological tissue section to acquire mass spectrum data. The obtained data is transferred from the measurement unit1to the data analyzing unit2and stored in the MS imaging data storage section20. Separately from this, the Raman spectroscopic imaging measurement device5executes Raman spectroscopic analysis for each predetermined wavelength band (Raman band) for a large number of measurement points set in a two-dimensional region including the measurement region on the same sample100to acquire Raman spectrum data indicating the relationship between the scattering intensity and the wavelength. The obtained data is input from the Raman spectroscopic imaging measurement device5to the data analyzing unit2, and the data analyzing unit2stores the input data in the Raman imaging data storage section21. When a user performs a predetermined operation on the input unit3, the data analyzing unit2executes the following analysis processing using the data stored in each of the MS imaging data storage section20and the Raman imaging data storage section21as described above. The MS imaging graphic creation section22reads, for example, ion intensity data at intervals of 1 Da for each measurement point from the MS imaging data storage section20, and creates a large number of MS imaging graphics indicating the two-dimensional distribution of the ion intensity for each 1 Da (see reference numeral200inFIG.2). In addition, the Raman imaging graphic creation section23reads the scattering intensity data for each Raman band from the Raman imaging data storage section21, calculates, for example, a peak area for each Raman band, and uses the peak area as the scattering intensity to create one or a plurality of Raman imaging graphics indicating a two-dimensional distribution of the scattering intensity (see reference numeral300inFIG.2). As described above, the MS imaging graphic is an image indicating a two-dimensional distribution of the ion intensity for each mass-to-charge ratio, and the Raman imaging graphic is an image indicating a two-dimensional distribution of the scattering intensity for each Raman band. The MS imaging graphic and the Raman imaging graphic are analysis result images for (or including) the same measurement region of the same sample100, but generally have different spatial resolutions (resolutions) from each other. In addition, the MS imaging graphic and the Raman imaging graphic are completely different in the level of the value of the signal intensity at each measurement point, and thus the comparison of the two-dimensional distributions as they are is meaningless. Therefore, in order to compare or treat the MS imaging graphic and the Raman imaging graphic equally, two processes including a process of aligning the dynamic ranges of the signal intensity and a process of aligning the spatial resolutions are executed. Specifically, the signal intensity normalization processor24normalizes the ion intensity value of each measurement point and the scattering intensity value of each measurement point so that the maximum value of the ion intensity value in the MS imaging graphic and the maximum value of the scattering intensity value in the Raman imaging graphic become the same value (for example, the maximum value of the pixel value when the value of one data is expressed by an image). It is not necessary to normalize the intensity values between different MS imaging graphics or between different Raman imaging graphics (the normalization may be performed), and it is only required to normalize the ion intensities in all the MS imaging graphics and the scattering intensities in all the Raman imaging graphics. In addition, the spatial resolution adjustment processor25aligns the spatial resolutions by reducing the spatial resolution of the image having the higher spatial resolution by binning processing or the like, or conversely, by increasing the spatial resolution of the image having the lower spatial resolution by interpolation processing or the like, between the MS imaging graphic and the Raman imaging graphic. In the example illustrated inFIG.2, the spatial resolution of the MS imaging graphic is higher than that of the Raman imaging graphic, and the spatial resolution of the MS imaging graphic and the spatial resolution of the Raman imaging graphic are aligned by reducing the spatial resolution of the MS imaging graphic. The intensity values of the MS imaging graphic and the Raman imaging graphic with the aligned spatial resolutions are normalized. When the target measurement regions on the sample100in the imaging mass spectrometry and the Raman spectroscopic imaging are not completely the same, only the image corresponding to the region where both the measurement regions overlap may be cut out. Furthermore, in a case where distortion or deformation occurs in the acquired image due to the principle or characteristics of analysis or measurement, image processing for correcting such distortion or deformation may be performed. By the series of processing described above, the MS imaging graphic and the Raman imaging graphic become two-dimensional distribution images that can be handled equally although the analysis methods used are different. Therefore, the statistical analysis processor26executes hierarchical cluster analysis by collecting the MS imaging graphics and the Raman imaging graphics after such processing, and performs clustering by collecting images having similar two-dimensional intensity distributions. As a result, the MS imaging graphic and the Raman imaging graphic in which the ionic intensity distribution pattern and the Raman scattering intensity distribution pattern are similar to each other are classified into the same cluster. That is, regardless of the difference in the analysis method, two-dimensional distributions of information obtained for the same measurement region of the same sample are classified into the same cluster when the distributions are similar, and classified into different clusters when the distributions are different. The display processor27displays the result of the hierarchical cluster analysis on the screen of the display unit4in a predetermined form. This display form can be selected from, for example, various predetermined forms. Specifically, reduced images of one or a plurality of imaging graphics classified into the same cluster can be collectively displayed in a list for each cluster, or reduced images of representative imaging graphics can be displayed in a list one by one for each cluster, or when the user instructs one of the imaging graphics by a click operation or the like, imaging graphics included in the same cluster as the instructed imaging graphic can be displayed in a list. In addition, in the hierarchical cluster analysis, a dendrogram showing similarity between imaging graphics can be created, and such a dendrogram may be displayed (seeFIG.3). In addition, similarity between the imaging graphics may be visually expressed using a scatter diagram. In the imaging graphic, the two-dimensional intensity distribution is drawn using the gray scale or the color scale, and the display modes of the MS imaging graphic and the Raman imaging graphic may be easily distinguishable from each other so that the MS imaging graphic and the Raman imaging graphic can be recognized at a glance on the image indicating the classification result. For example, the display color may be different, the brightness of the display may be different, or the shape (for example, a frame may be attached to one side) and size of the display may be different. The device of the above embodiment is a device that uses the two-dimensional region on the sample as the measurement region, that is, the MS imaging graphic or the Raman imaging graphic is a two-dimensional image, but the device can also be a device that processes a three-dimensional MS imaging graphic or Raman imaging graphic using a three-dimensional region in the sample as a measurement region. FIGS.4A and4Bare conceptual diagrams of a three-dimensional MS imaging graphic. For example, as illustrated inFIG.4A, a sample101such as a small piece of an organ cut out from a living body is sliced very thinly and continuously to prepare a large number of sample slices. Here, the cut surfaces of the sample slices are parallel to the X-Y plane. The measurement unit1measures the inside of a two-dimensional measurement region on each sample slice. As a result, as illustrated inFIG.4B, MS imaging graphics102ato102ncorresponding to the sample slices are obtained. By arranging the images in the Z-axis direction with the positions on the X-axis and the Y-axis aligned, it is possible to obtain substantially three-dimensional MS imaging data. Therefore, a three-dimensional MS imaging graphic is drawn on the basis of these data. The same applies to the Raman imaging graphic. By performing processing similar to that performed on the two-dimensional imaging graphics described above on these images, it is possible to obtain a result of classifying the three-dimensional MS imaging graphics and the three-dimensional Raman imaging graphics by hierarchical cluster analysis. As described above, the imaging mass spectrometer according to the present invention can also be used for processing data extended to three dimensions. In the above embodiment, the hierarchical cluster analysis is executed on the MS imaging graphic and the Raman imaging graphic, but instead of the Raman imaging graphic, an image by an optional imaging analysis method other than mass spectrometry imaging can be used. For example, an image by an infrared (IR) imaging method, a fluorescence imaging method, or an X-ray spectroscopic imaging method can be targeted. In addition, it is also conceivable that both of the methods are mass spectrometry instead of two methods having completely different measurement principles such as mass spectrometry and Raman spectroscopic analysis. In this case, for example, the analysis method can be regarded as an analysis method of a type different from ordinary mass spectrometry without ion dissociation operation and MS/MS analysis or MSnanalysis with ion dissociation operation. In addition, even if the sample to be analyzed itself is the same, the generated ion species may be different when the ionization method at the time of mass spectrometry is different. Therefore, here, mass spectrometry with a different ionization method can also be regarded as a different type of analysis method. For example, mass spectrometry using a MALDI method and mass spectrometry using an ionization method in a SIMS method are different types of analysis methods. Therefore, the present invention can also be applied when the imaging graphics obtained by such a different type of analysis method are collectively classified using statistical analysis such as hierarchical cluster analysis. In addition, the above embodiment and other modifications are merely examples of the present invention, and it is a matter of course that modifications, corrections, additions, and the like appropriately made within the scope of the gist of the present invention are included in the claims of the present application. Various embodiments of the present invention have been described above with reference to the drawings. Finally, various aspects of the present invention will be described. According to a first aspect of the present invention, there is provided an imaging mass spectrometer that executes mass spectrometry on each of a plurality of micro areas set in a two-dimensional measurement region on a sample or a three-dimensional measurement region in a sample, the imaging mass spectrometer including:a first imaging graphic data acquisition section configured to acquire data constituting one or a plurality of first imaging graphics indicating an ion intensity distribution at one or a plurality of specific mass-to-charge ratios or in one or a plurality of mass-to-charge ratio ranges or indicating a distribution of a calculation result obtained by predetermined calculation processing based on the ion intensity distribution based on data obtained by mass spectrometry for a target sample;a second imaging graphic data acquisition section configured to acquire data constituting one or a plurality of second imaging graphics obtained by an analysis method that is a type different from the mass spectrometry with respect to the target sample;a first data processor configured to perform, on data acquired by the first imaging graphic data acquisition section and the second imaging graphic data acquisition section, data conversion processing of normalizing signal intensity in the one or plurality of first imaging graphics and signal intensity in the one or plurality of second imaging graphics;a second data processor configured to perform, on data acquired by the first imaging graphic data acquisition section and the second imaging graphic data acquisition section, data processing of aligning spatial resolutions of the one or plurality of first imaging graphics and the one or plurality of second imaging graphics; andan image classification processor configured to execute statistical analysis processing on an image for data after processing by the first and second data processor and to classify the one or plurality of first imaging graphics and the one or plurality of second imaging graphics on the basis of similarity or difference in spatial distribution. According to the imaging mass spectrometer of the first aspect, it is possible to efficiently and objectively execute analysis processing such as similarity in intensity distribution on a mass spectrometry imaging graphic obtained by imaging mass spectrometry and an imaging graphic obtained by imaging analysis such as infrared spectroscopic analysis or Raman spectroscopic analysis completely different from mass spectrometry or imaging mass spectrometry using another ionization method in which ion species generated are different even in the same mass spectrometry. Thereby, it is possible to provide the user with useful information about a target sample which is not known or inaccurate only from analysis of the mass spectrometry imaging graphic. In the imaging mass spectrometer of a second aspect of the present invention, in the device of the first aspect, the measurement region is a two-dimensional measurement region on a sample. According to the imaging mass spectrometer of the second aspect, for example, for a thin sample such as a biological tissue slice, it is easy to compare distribution situations of the same component among a plurality of samples. In the imaging mass spectrometer of a third aspect of the present invention, in the device of the first aspect, the measurement region is a three-dimensional measurement region in a sample. According to the imaging mass spectrometer of the third aspect, for example, for a thick sample such as a biological tissue section, it is easy to compare distribution situations of the same component among a plurality of samples. Further, in the imaging mass spectrometer of a fourth aspect of the present invention, the device of the first aspect further includes an image correction section that corrects a difference in shape of an object on an image by deforming one or both of an image based on data acquired by the first imaging graphic data acquisition section and an image based on data acquired by the second imaging graphic data acquisition section. Image deformation processing by the image correction section can include movement, rotation, enlargement/reduction, and the like of the entire image or a part thereof. According to the imaging mass spectrometer of the second aspect, even in a case where distortion occurs in the image obtained by analysis, and the same position on the sample does not correspond between the image based on the data acquired by the first imaging graphic data acquisition section and the image based on the data acquired by the second imaging graphic data acquisition section, the images can be made comparable to each other by the image deformation processing. Further, in the imaging mass spectrometer of a fifth aspect of the present invention, the device of the first aspect further includes a display processor that displays an image classification result by the image classification processor on a display unit in a predetermined format, and the display processor changes a visual aspect of a classification result of the first imaging graphic and a classification result of the second imaging graphic. The visual aspect mentioned here is, for example, a display color, display brightness (luminance), shape, size, and the like. According to the imaging mass spectrometer of the third aspect of the present invention, in the classification result display of the images, the user can easily distinguish the images by different analysis methods, and the classification result can be easily understood. In the imaging mass spectrometer of a sixth aspect of the present invention, the device of the first aspect further includes an integrated mass spectrum calculation unit that calculates and displays an integrated mass spectrum or an average mass spectrum in a specific part on a first imaging graphic set based on a classification result of an image by the image classification processor, using mass spectrum data obtained for a plurality of measurement points included in the specific part. According to the imaging mass spectrometer of the sixth aspect, in a case where a characteristic pattern is shown on a mass spectrometry imaging graphic, an integrated mass spectrum or an average mass spectrum assumed to correspond to a component present at the specific part can be presented to a user. REFERENCE SIGNS LIST 1. . . Imaging Mass Spectrometry Unit1. . . Measurement Unit100. . . Sample2. . . Data Analyzing Unit20. . . MS Imaging Data Storage Section21. . . Raman Imaging Data Storage Section22. . . MS Imaging Graphic Creation Section23. . . Raman Imaging Graphic Creation Section24. . . Signal Intensity Normalization Processor25. . . Spatial Resolution Adjustment Processor26. . . Statistical Analysis Processor27. . . Display Processor3. . . Input Unit4. . . Display Unit5. . . Raman Spectroscopic Imaging Measurement Device | 21,730 |
11862446 | DETAILED DESCRIPTION OF A PREFERRED EMBODIMENT Detailed descriptions of one or more preferred embodiments are provided herein. It is to be understood, however, that the present invention may be embodied in various forms. Therefore, specific details disclosed herein are not to be interpreted as limiting, but rather as a basis for the claims and as a representative basis for teaching one skilled in the art to employ the present invention in any appropriate manner. Wherever any of the phrases “for example,” “such as,” “including” and the like are used herein, the phrase “and without limitation” is understood to follow unless explicitly stated otherwise. Similarly, “an example,” “exemplary” and the like are understood to be non-limiting. The term “substantially” allows for deviations from the descriptor that do not negatively impact the intended purpose. Descriptive terms are understood to be modified by the term “substantially” even if the word “substantially” is not explicitly recited. Therefore, for example, the phrase “wherein the lever extends vertically” means “wherein the lever extends substantially vertically” so long as a precise vertical arrangement is not necessary for the lever to perform its function. The terms “comprising” and “including” and “having” and “involving” (and similarly “comprises”, “includes,” “has,” and “involves”) and the like are used interchangeably and have the same meaning. Specifically, each of the terms is defined consistent with the common United States patent law definition of “comprising” and is therefore interpreted to be an open term meaning “at least the following,” and is also interpreted not to exclude additional features, limitations, aspects, etc. Thus, for example, “a process involving steps a, b, and c” means that the process includes at least steps a, b and c. Wherever the terms “a” or “an” are used, “one or more” or “at least one” is understood, unless such interpretation is nonsensical in context. Although a range of calibration sets have been explored for ion mobility characterization, they exhibit a relatively narrow range of m/z and CCS values. The calibration systems employed for ion mobility-mass spectrometry (IM-MS) have largely been those already explored for ESI-MS, including Ultramark, polyalanine (Poly-Ala), and tetra(alkyl) ammonium salts (TAA salts). FIG.1shows that these compounds all have a similar degree of compactness (slope of CCS relative to m/z, and shown by the shaded area), with the fluorinated Ultramark calibrants exhibiting slightly more compact nature due to higher density of fluorine. The high proportion of ionizable atoms (e.g., O and N) in these calibrant systems result in limited m/z range for 1+ species, as higher masses tend to be multiply charged. For ions of these traditional calibrants in the 1+ charge state, the calibration range covered is limited. As shown by the small area occupied in the two-dimensional space by these two axes, these existing calibrants exhibit limited range in the CCS dimension (for N2): 100-400 Å2(top CCS boundary), and limited range in the m/z dimension (typically m/z range: 0-2000) (right m/z boundary). Furthermore, they exhibit limited diversity in compactness (e.g. slope of CCS relative to m/z). Therefore, there is a need for IM-MS calibrants that can overcome these limitations. The calibrants should provide a wider range for both the CCS and the m/z dimensions while exhibiting minimal dispersity in CCS dimension (narrow peak width). Additionally, the calibrants should be compatible with both positive and negative ion modes, should be technically simple to use, and should exhibit long shelf-lives. In an aspect, the present disclosure relates to compositions containing at least one calibrant compound, or cationic complex thereof, or anionic complex thereof, in which the at least one calibrant compound or the salt thereof or cationic complex thereof, or anionic complex thereof, may include an alcohol or an amine functionalized core and peripheral functionalities. The at least one calibrant compound or the salt thereof or cationic complex thereof, or anionic complex thereof, may include at least one core with at least one alcohol functionality, which may be selected from the group consisting of mono-functional cores, di-functional cores, tri-functional cores, tetra-functional cores, penta-functional cores, hexa-functional cores, octa-functional cores, and dendrimer-based cores comprising a plurality of alcohol functionalities. For example, mono-functional cores with at least one alcohol functionality may be selected from the group consisting of methanol, ethanol, 1-propanol, 2-propanol, 1-butanol, 2-butanol, 3-methyl-1-butanol, 3-methyl-2-butanol, 2-methyl-1-butanol, and 2,2-dimethyl 1-propanol; di-functional cores may be selected from the group consisting of ethylene glycol, 1,2-propane diol, 1,3-propane diol, 1,2-butane diol, 1,3-butane diol, 1,4-butane diol, 2,3-butane diol, 1,2-pentane diol, 1,5-pentane diol, 1,2-hexane diol, and 1,6-hexane diol; tri-functional cores may be selected from the group consisting of 1,2,4-butane triol, 1,2,6-butane triol, 1,1,1-tris-(hydroxymethyl)ethane, and 1,1,1-tris-(hydroxymethyl)propane; tetra-functional cores may be selected from the group consisting of pentaerythritol, erythritol, and threitol; penta-functional cores may be selected from the group consisting of xylitol, arabinitol, arabitol, adonitol, and triglycerol; hexa-functional cores may be selected from the group consisting of dipentaerythritol, allitol, dulcitol, iditol, talitol, sorbitol, galactitol, and mannitol; octafunctional core may be tripentaerythritol; and dendrimer-based cores may contain at least one layer of bis-MPA repeating units bonding to any one of mono-functional cores, di-functional cores, tri-functional cores, tetra-functional cores, penta-functional cores, hexa-functional cores, and/or octa-functional cores by esterification. The at least one calibrant compound or the salt thereof or cationic complex thereof, or anionic complex thereof, may include at least one core with at least one amine functionality, which may be selected from the group consisting of mono-functional cores, di-functional cores, tri-functional cores, tetra-functional cores, and dendrimer-based cores comprising a plurality of amine functionalities. For example, mono-functional cores with at least one amine functionality may be selected from the group consisting of methylamine, ethylamine, 1-propylamine, 2-propamine, 1-butylamine, 2-butylamine, and tert-butylamine; di-functional cores may be selected from the group consisting of ethylene diamine, 1,2-propane diamine, 1,3-propane diamine, 1,2-butane diamine, 1,3-butane diamine, 1,4-butane diamine, 2,3-butane diamine, 1,5-pentane diamine, 1,6-hexane diamine, and 1,7-heptane diamine; tri-functional cores may be selected from the group consisting of 2,2′-diaminoethylamine, bis(hexamethylene) triamine, triazine, and tris(2-aminoethyl)amine; tetra-functional cores may be selected from the group consisting of 3,3′diaminobenzidine, triethylenetetramine, and hexamethylenetetramine; and dendrimer-based cores may be selected from the group consisting of polyamidoamine, polypropylene imine, and polytriazine dendrimers. In another aspect, the present disclosure relates to compositions containing at least two calibrant compounds or salts thereof or cationic complex thereof, or anionic complex thereof, in which the at least two calibrant compounds or the salts thereof or cationic complex thereof, or anionic complex thereof, may contain the alcohol or amine functionalized cores and the peripheral functionalities. In another aspect, the present disclosure relates to methods of manufacturing the composition of the present disclosure, including mixing one, two, three, four, five, six, or more of the at least one core with at least one alcohol functionality, and subjecting the mixture to an esterification reaction. In another aspect, the present disclosure relates to methods of manufacturing the composition of the present disclosure, including mixing one, two, three, four, five, six, or more of the at least one core with at least one amine functionality, and subjecting the mixture to an amidation reaction. Compositions of the present disclosure may be used to calibrate any instruments that can measure mass, size, shape, and/or collisional cross section area (CCS) of molecules in a gas phase. In another aspect, the present disclosure relates to methods of calibrating a mass spectrometer, including providing the composition of the present disclosure, ionizing the at least one calibrant compound to provide at least one charged ion, collecting mass spectrometry data from the at least one charged ion, and calibrating the mass spectrometer based on the mass spectrometry data. The at least one charged ion may be singly-charged or multi-charged ion. Mass spectrometry data may contain a mass to charge ratio (m/z) of the at least one charged ion. The mass to charge ratio (m/z) of the at least one charged ion may be from about 1 m/z to about 15000 m/z, from about 1 m/z to about 14000 m/z, from about 1 m/z to about 13000 m/z, from about 1 m/z to about 12000 m/z, from about 1 m/z to about 11000 m/z, from about 1 m/z to about 10000 m/z, from about 1 m/z to about 9000 m/z, from about 1 m/z to about 9500 m/z, from about 1 m/z to about 9000 m/z, from about 1 m/z to about 8500 m/z, from about 1 m/z to about 8000 m/z, from about 10 m/z to about 8000 m/z, from about 100 m/z to about 8000 m/z, from about 250 m/z to about 8000 m/z, from about 500 m/z to about 8000 m/z, from about 750 m/z to about 8000 m/z, from about 1000 m/z to about 8000 m/z, from about 1500 m/z to about 8000 m/z, from about 1700 m/z to about 8000 m/z, from about 2000 m/z to about 8000 m/z, from about 2500 m/z to about 8000 m/z, from about 3000 m/z to about 8000 m/z, from about 3500 m/z to about 8000 m/z, from about 4000 m/z to about 8000 m/z, from about 4500 m/z to about 8000 m/z, from about 5000 m/z to about 8000 m/z, or from about 5500 m/z to about 8000 m/z, from about 1 m/z to about 7500 m/z, from about 1 m/z to about 7000 m/z, from about 1 m/z to about 6500 m/z, from about 1 m/z to about 6000 m/z, from about 10 m/z to about 6000 m/z, from about 50 m/z to about 6000 m/z, from about 100 m/z to about 6000 m/z, from about 250 m/z to about 6000 m/z, from about 500 m/z to about 6000 m/z, from about 750 m/z to about 6000 m/z, from about 1000 m/z to about 6000 m/z, from about 1500 m/z to about 6000 m/z, from about 2000 m/z to about 6000 m/z, from about 2500 m/z to about 6000 m/z, from about 3000 m/z to about 6000 m/z, from about 3500 m/z to about 6000 m/z, from about 4000 m/z to about 6000 m/z, from about 4500 m/z to about 6000 m/z, from about 5000 m/z to about 6000 m/z, or from about 5500 m/z to about 6000 m/z. In an embodiment, the mass to charge ratio (m/z) of the at least one charged ion may be from about 1 m/z to about 50 m/z, from about 50 m/z to about 100 m/z, from about 100 m/z to about 150 m/z, from about 150 m/z to about 200 m/z, from about 200 m/z to about 250 m/z, from about 250 m/z to about 300 m/z, from about 300 m/z to about 350 m/z, from about 350 m/z to about 400 m/z, from about 400 m/z to about 450 m/z, from about 450 m/z to about 500 m/z, from about 500 m/z to about 550 m/z, from about 550 m/z to about 600 m/z, from about 600 m/z to about 700 m/z, from about 700 m/z to about 800 m/z, from about 800 m/z to about 900 m/z, from about 900 m/z to about 1000 m/z, from about 1000 m/z to about 1100 m/z, from about 1100 m/z to about 1200 m/z, from about 1200 m/z to about 1300 m/z, from about 1300 m/z to about 1400 m/z, from about 1400 m/z to about 1500 m/z, from about 1500 m/z to about 1600 m/z, from about 1600 m/z to about 1700 m/z, from about 1700 m/z to about 1800 m/z, from about 1800 m/z to about 1900 m/z, from about 1900 m/z to about 2000 m/z, from about 2000 m/z to about 2100 m/z, from about 2100 m/z to about 2200 m/z, from about 2200 m/z to about 2300 m/z, from about 2300 m/z to about 2400 m/z, from about 2400 m/z to about 2500 m/z, from about 2500 m/z to about 2600 m/z, from about 2600 m/z to about 2700 m/z, from about 2700 m/z to about 2800 m/z, from about 2800 m/z to about 2900 m/z, from about 2900 m/z to about 3000 m/z, from about 3000 m/z to about 3100 m/z, from about 3100 m/z to about 3200 m/z, from about 3200 m/z to about 3300 m/z, from about 3300 m/z to about 3400 m/z, from about 3400 m/z to about 3500 m/z, from about 3500 m/z to about 3600 m/z, from about 3600 m/z to about 3700 m/z, from about 3700 m/z to about 3800 m/z, from about 3800 m/z to about 3900 m/z, from about 3900 m/z to about 4000 m/z, from about 4000 m/z to about 4250 m/z, from about 4250 m/z to about 4500 m/z, from about 4500 m/z to about 4750 m/z, from about 4750 m/z to about 5000 m/z, from about 5000 m/z to about 5250 m/z, from about 5250 m/z to about 5500 m/z, from about 5500 m/z to about 5750 m/z, from about 5750 m/z to about 6000 m/z, from about 6000 m/z to about 6250 m/z, from about 6250 m/z to about 6500 m/z, from about 6500 m/z to about 6750 m/z, from about 6750 m/z to about 7000 m/z, from about 7000 m/z to about 7500 m/z, from about 7500 m/z to about 8000 m/z, from about 8000 m/z to about 8500 m/z, from about 8500 m/z to about 9000 m/z, from about 9000 m/z to about 9500 m/z, from about 9500 m/z to about 10,000 m/z, from about 10,000 m/z to about 11,000 m/z, from about 11,000 m/z to about 12,000 m/z, from about 12,000 m/z to about 13,000 m/z, from about 13,000 m/z to about 14,000 m/z, from about 14,000 m/z to about 15,000 m/z. The mass spectrometry may be selected from the group consisting of accelerator mass spectrometry, isotope ratio mass spectrometry, MALDI-TOF, SELDI-TOF, electrospray ionization (ESI)-mass spectrometry, thermal ionization-mass spectrometry, and spark source mass spectrometry, and the mass spectrometer may be selected from the group of spectrometers useful for performing said mass spectrometry. In another aspect, the present disclosure relates to methods of calibrating an ion mobility spectrometer, including providing the composition of the present disclosure, ionizing the at least one calibrant compound to provide at least one charged ion, introducing the at least one charged ion into the ion mobility spectrometer, collecting ion mobility data from the at least one charged ion in a drift gas, and calibrating the ion mobility spectrometer based on the ion mobility data. The at least one charged ion may be singly-charged or multi-charged. The ion mobility data may contain a collision cross section (CCS) value of the at least one charged ion. The collision cross section (CCS) value of the at least one charged ion may be from about 10 Å2to about 1500 Å2, from about 10 Å2to about 1400 Å2, from about 10 Å2to about 1300 Å2, from about 10 Å2to about 1200 Å2, from about 10 Å2to about 1100 Å2, about 10 Å2to about 1000 Å2, from about 10 Å2to about 900 Å2, from about 100 Å2to about 900 Å2, from about 150 Å2to about 900 Å2, from about 150 Å2to about 850 Å2, from about 150 Å2to about 800 Å2, from about 150 Å2to about 750 Å2, from about 150 Å2to about 700 Å2, from about 150 Å2to about 650 Å2, from about 150 Å2to about 600 Å2, from about 200 Å2to about 1000 Å2, from about 200 Å2to about 950 Å2, from about 200 Å2to about 900 Å2, from about 200 Å2to about 850 Å2, from about 200 Å2to about 800 Å2, from about 200 Å2to about 750 Å2, from about 200 Å2to about 700 Å2, from about 200 Å2to about 650 Å2, from about 200 Å2to about 600 Å2, from about 200 Å2to about 550 Å2, from about 200 Å2to about 500 Å2, from about 200 Å2to about 450 Å2, from about 200 Å2to about 400 Å2, from about 200 Å2to about 350 Å2, from about 200 Å2to about 300 Å2, from about 200 Å2to about 250 Å2, from about 10 Å2to about 10 Å2, from about 10 Å2to about 50 Å2, from about 10 Å2to about 100 Å2, from about 10 Å2to about 110 Å2, from about 10 Å2to about 120 Å2, from about 10 Å2to about 130 Å2, from about 10 Å2to about 140 Å2, from about 10 Å2to about 150 Å2, from about 10 Å2to about 160 Å2, from about 10 Å2to about 170 Å2, from about 10 Å2to about 180 Å2, from about 10 Å2to about 190 Å2, or from about 10 Å2to about 200 Å2. In an embodiment, the collision cross section (CCS) value of the at least one charged ion may be from about 10 Å2to about 20 Å2, from about 20 Å2to about 30 Å2, from about 30 Å2to about 40 Å2, from about 40 Å2to about 50 Å2, from about 50 Å2to about 60 Å2, from about 60 Å2to about 70 Å2, from about 70 Å2to about 80 Å2, from about 80 Å2to about 90 Å2, from about 90 Å2to about 100 Å2, from about 100 Å2to about 110 Å2, from about 110 Å2to about 120 Å2, from about 120 Å2to about 130 Å2, from about 130 Å2to about 140 Å2, from about 140 Å2to about 150 Å2, from about 150 Å2to about 160 Å2, from about 160 Å2to about 170 Å2, from about 170 Å2to about 180 Å2, from about 180 Å2to about 190 Å2, from about 190 Å2to about 200 Å2, from about 200 Å2to about 225 Å2, from about 225 Å2to about 250 Å2, from about 250 Å2to about 275 Å2, from about 275 Å2to about 300 Å2, from about 300 Å2to about 325 Å2, from about 325 Å2to about 350 Å2, from about 350 Å2to about 375 Å2, from about 375 Å2to about 400 Å2, from about 400 Å2to about 425 Å2, from about 425 Å2to about 450 Å2, from about 450 Å2to about 475 Å2, from about 475 Å2to about 500 Å2, from about 500 Å2to about 525 Å2, from about 525 Å2to about 550 Å2, from about 550 Å2to about 575 Å2, from about 575 Å2to about 600 Å2, from about 600 Å2to about 625 Å2, from about 625 Å2to about 650 Å2, from about 650 Å2to about 675 Å2, from about 675 Å2to about 700 Å2, from about 700 Å2to about 725 Å2, from about 725 Å2to about 750 Å2, from about 750 Å2to about 775 Å2, from about 775 Å2to about 800 Å2, from about 800 Å2to about 850 Å2, from about 850 Å2to about 900 Å2, from about 900 Å2to about 950 Å2, from about 950 Å2to about 1000 Å2, from about 1000 Å2to about 1100 Å2, from about 1100 Å2to about 1200 Å2, from about 1200 Å2to about 1300 Å2, from about 1300 Å2to about 1400 Å2, or from about 1400 Å2to about 1500 Å2. The drift gas may be selected from the group consisting of helium, nitrogen, argon, and carbon dioxide. In another aspect, the present disclosure relates to methods of calibrating an ion mobility-mass spectrometer, including providing the composition of the present disclosure, ionizing the at least one calibrant compound to provide at least one charged ion, introducing the at least one charged ion into the ion mobility-mass spectrometer, collecting ion mobility data in a drift gas and mass spectrometer data from the at least one charged ion, and calibrating the ion mobility-mass spectrometer based on the ion mobility data and the mass spectrometer data. In another aspect, the present disclosure relates to methods of calibrating a light scattering spectrometer, including providing the composition of the present disclosure, dissolving the at least one calibrant compound to provide a solution of the at least one calibrant compound, introducing the solution of the at least one calibrant compound into the light scattering spectrometer, collecting light scattering data from the at least one calibrant compound, and calibrating the light scattering spectrometer based on the light scattering data. The light scattering data may contain the size of the at least one calibrant compound in the solution. In another aspect, the present disclosure relates to methods of calibrating a size exclusion chromatograph, including providing the composition of the present disclosure, dissolving the at least one calibrant compound to provide a solution of the at least one calibrant compound, introducing the solution of the at least one calibrant compound into the size exclusion chromatograph, collecting size exclusion data from the at least one calibrant compound; and calibrating the size exclusion chromatograph based on the size exclusion data. The size exclusion data may contain the size of the at least one calibrant compound in the solution. In another aspect, the present disclosure relates to methods of determining physical properties of a sample, including providing the composition of the present disclosure, providing the sample, collecting physical data from the at least one calibrant compound, calibrating an instrument capable of measuring the physical properties based on the physical data, and determining the physical properties of the sample. The physical properties of the sample may include mass, size, shape, and/or collisional cross section area of the sample in a drift gas. The instrument may be selected from the group consisting of mass spectrometer, ion mobility spectrometer, ion mobility-mass spectrometer, light scattering spectrometer, size exclusion chromatograph, and a combination thereof. Embodiments of the present disclosure include novel calibrants and methods of making these calibrants that contain multifunctional cores and/or dimethylolpropionic acid (bis-MPA), i.e., based polyester dendrimers. These core molecules or dendrimers may be functionalized on their periphery to prepare a series of singular discrete compounds with exact molecular weights and well-defined sizes. These functionalized cores and dendrimers may then be used as IMS calibrants. Each compound within a sample set may be composed of a core molecule with at least one alcohol functionality, or at least one amine functionality. Each of these alcohol or amine functionalities can then be coupled with an activated carboxylic acid to yield multiple ester or amide bonds. Functionalized cores or dendrimers (the latter based on the bis-MPA monomer) are prepared as singular discrete compounds that may exhibit a wider range of CCS and m/z values. In some embodiments, CCS values of greater than 800 Å2, and m/z values of in excess of 5500 (for singly charges species) can be measured, more than doubling the range of the existing common calibrants. To achieve higher CCS values, embodiments of the present disclosure may include the addition of alkyl chains onto the periphery of the cores to make “star-shaped” calibrants (with multiple alkyl arms). Fatty acids varying from short chains to long chains are coupled with the multifunctional cores or dendrimers. Though the addition of long alkyl chains may not significantly increase the propensity for charging (ease of complexation with cations), it does increase the size substantially, and therefore yields extended conformations with high CCS values but modest m/z values. In one embodiment, the present disclosure provides functionalized polyester dendrimers based on bis-MPA monomer that may be modified by esterification of their peripheral functionalities in order to prepare a set of singular, discrete compounds that may exhibit a wider range of CCS and m/z values. In particular, CCS values in excess of 800 Å2, and m/z values of in excess of 5500 (for singly charges species) can be measured, more than doubling the range of existing calibrants. In another embodiment, the present disclosure provides functionalized core molecules by reacting activated carboxylic acid derivatives with the alcohol and/or amine functionalities of the multifunctional cores. A set of discrete compounds may be generated that expand the available range of m/z calibration points as well as CCS calibration points for IM-MS characterization. For example, multifunctional core may have a formula I: X—[OH]n, in which n is an integer from 3 to 20, and X is a core comprised of alkane, ether, ester, amine, and/or amide functionalities or generations of alkane, ether, ester, amine, and/or amide dendrimers. Non-limiting examples of X—[OH]ncores are shown in Table 1. TABLE 1CoreXnSymbolCore Structurealkyl3C4D5Eether6F8Hamine345G1 dendrimer6C18D110E112F1 X—[OH]nmay be reacted with carboxylic acid derivatives, such as those of Formula II: where m is an integer from 1 to 30. For example, carboxylic acid derivatives may be selected from the group consisting of methanoic (formic) acid, ethanoic (acetic) acid, propanoic (proprionic) acid, butanoic (butyric) acid, pentanoic (valeric) acid, hexanoic (caprylic) acid, heptanoic (enanthic) acid, octanoic (caprylic) acid, nonanoic (pelargonic) acid, decanoic (capric) acid, undecanoic acid, dodecanoic (lauric) acid, tridecanoic acid, tetradecanoic (myristic) acid, pentadecanoic acid, hexadecanoic (palmitic acetic) acid, heptadecanoic (margaric acetic) acid, octadecanoic (stearic acetic) acid, nonadecanoic acid, eicosanoic (arachidic) acid, heneicosanoic acid, docosanoic (behenic) acid, tetracosanoic (lignoceric) acid, hexacosanoic (cerotic) acid, octacosanoic (montanic) acid, and triacosanoic (melissic) acid. In addition, X—[OH]nmay be reacted with carboxylic acid derivatives that include a hydrocarbon chain that may contain one or more branching points, one or more double bond, and/or one or more triple bond, such as arachidonic acid, cis-13-docosenoic acid, cis-11-eicosenoic acid, elaidic acid, linoleic acid, linolenic acid, linolelaidic acid, myristoleic, oleic acid, palm itoleic acid, petroselenic acid, and cis-15-tetracosenoic acid. A synthetic scheme for esterification of multifunctional cores or multifunctional dendrimer cores is shown below: wherein m=2, 6, 10, 16, or 20, n=3 to 20, and X is a core comprised of alkane, ether, ester, amine, and/or amide functionalities or generations of alkane, ether, ester, amine, and/or amide dendrimers (e.g., as shown in Table 1). These reactions may be achieved using dicyclohexylcarbodiimide (DCC) and 4-dimethylaminopyridine (DMAP) as a catalyst. FIG.2shows a calibrant based on a hexafunctional alcohol core C1 (n=6) (a bis-MPA dendrimer) that has been esterified with dodecyl (lauryl) esters to yield a compound with an exact molecular weight and a well-defined size. To evaluate the performance of the calibrants of the present disclosure in IM-MS, a mixture of the calibrants of the present disclosure shown in Table 2 and the existing standards, e.g., TAA salts, LCMS QC Ref, Poly-Ala, Ultramark, and SphericalCal Mix, are compared. TABLE 2Calibrant MixtureCore SymbolsIMS 004 C-FC, D, E, Fm = 4NAIMS 008 C-FC, D, E, Fm = 8NAIMS 012 C-FC, D, E, Fm = 12NAIMS 018 C1-F1C1, D1, E1, F1m = 18NAIMS 018 HHm = 18NAIMS 022 C-FC, D, E, Fm = 22NAIMS 100 C-FC, D, E, FNAy = 0IMS 103 C-FC, D, E, FNAy = 3IMS 103 C1-F1C1, D1, E1, F1NAy = 3IMS 103 HHNAy = 3 FIG.3shows that the addition of alkyl chains, e.g., from 4-carbon chain (IMS 004) to 22-carbon chain (IMS 022), onto cores and dendrimers provides a more extended conformation, and hence higher CCS values relative to m/z, (with values as high as 813 Å2, e.g., 18-carbon chain IMS 018 C1-F1 as indicated by open arrows), than the existing standards, e.g., TAA salts, LCMS QC Ref, Poly-Ala, and Ultramark, as shown inFIG.1. The SpheriCal standards exhibit a trend in compactness similar to the existing standards, but may extend the CCS range just beyond 400 Å2. All data correspond to Na+adducts. To achieve higher m/z, an embodiment of the present disclosure may include the incorporation of multiple halogen atoms into the calibrant compositions. Achieving high m/z can be a challenge in mass spectrometry because increases in the mass (m) tends to also increase the ability to carry charge (z). However, certain elements (e.g. iodine “I”) have a high atomic mass (A.M.=127) but may not have an increased propensity to carry charge (e.g. relative to elements like O, atomic mass=16, and N, atomic mass=14). To a lesser extent, the same may be true for fluorine (A.M.=19). Therefore, an embodiment of the present disclosure may include compounds with high I (or F) content that can exhibit very high masses in low charge states (hence high m/z) as well as very compact conformation with modest CCS values, despite high m/z values. For example, X—[OH]nmay be reacted with carboxylic acid derivatives, such as those of Formula IV: in which y is an integer from 0 to 5. For example, carboxylic acid derivatives may be selected from the group consisting of benzoic acid, 2-iodo benzoic acid, 3-iodo benzoic acid, 4-iodo benzoic acid, 2,3-diiodo benzoic acid, 2,4-diiodo benzoic acid, 2,5-diiodo benzoic acid, 2,6-diiodo benzoic acid, 3.4-diiodo benzoic acid, 3,5-diiodo benzoic acid, 2,3,4-triiodo benzoic acid, 2,3,5-triiodo benzoic acid, 2,3,6-triiodo benzoic acid, 3,4,5-triiodo benzoic acid, 2,3,4,5-tetraiodobenzoic acid, 2,3,4,6-tetraiodobenzoic acid, 2,3,5,6-tetraiodobenzoic acid, and 2,3,4,5,6-pentaiodobenzoic acid. A synthetic scheme for esterification of multifunctional cores or multifunctional dendrimer cores is shown below: e.g., y=0 or 3, n=3 to 20, and X as defined above. These reactions may be carried out in the presence of dicyclohexylcarbodiimide (DCC) and 4-dimethylaminopyridine (DMAP). Table 3 shows the chemical structures of some calibrants with triiodobenzoate functionalized cores in accordance with some embodiments of the present disclosure. TABLE 3CoreCalibrant StructureXnSymbolCore Structure(Calibrant Symbol)alkyl3C4D5Eether6F8HG1 dendrimer6C18D110E112F1 FIG.3shows that halogenated aromatics, e.g., triiodobenzoate functionalized core (IMS 103 C-F, IMS 103 C1-F1, and IMS 103 H), exhibit higher mass to size ratio, hence higher m/z, lower CCS values, and an overall more compact trend line than the existing standards, e.g., TAA salts, LCMS QC Ref, Poly-Ala, and Ultramark, as shown inFIG.1. This may increase the m/z values in the 1+ charge state from below 2000 to as high as 5571, with a CCS of only 576 Å2, e.g., IMS 103 C1-F1 (as indicated by arrows). The slope of IMS 103 C1-F1 together with IMS 103 C-F (as indicated by arrow heads) and IMS 103 H (as indicated by open arrow head) is smaller than that of IMS 004-024, indicating that IMS 103 calibrants are more compact than IMS 004-024 calibrants. IMS 103 calibrants achieve very high masses in low charge states (hence high m/z) as well as very compact conformation with modest CCS values, despite high m/z values. Size dispersity refers to the range of sizes that a single compound may exhibit. If the compounds are flexible, they may exhibit both very compact and very extended conformations. Embodiments of the present disclosure may include branched cores that lead to structures, which are more architecturally compact and therefore lack the ability to exhibit a wide range of shapes. This is in contrast, for example, to a long linear compound, which may exhibit either compact (wadded up) or extended (more elongated linear) conformations. FIG.4shows that the observed peak width in the CCS dimension is a function of both instrument resolution and the dispersities of conformation, which are sampled by the molecule in the gas phase. The series of dendrimers, e.g., IMS 100 C-F (see Example 7), IMS 004 C-F (with 4-carbon chain), and IMS 008 C-F (with 8-carbon chain), exhibit CCS dispersities as narrow as those observed by other calibrants, such as the trialkyl ammonium salts (TAA salts). The conformational dispersity of the dendrimer calibrants of the present disclosure may be as narrow as those measured for other calibrants. Embodiments of the present disclosure may include calibrants that exhibit the ability to complex with a range of cations and/or anions to achieve mass spectra and ion mobility spectra in both positive and negative ion modes. FIG.5shows an analysis in the positive mode of ionization, in which data for calibrations can be achieved, as long as the appropriate salt is used. In positive ion mode, with 0.1% sodium formate used as a cation source in 0.1% formic acid, IMS103 (IMS103-C, IMS103-D, IMS103-E, and IMS103-F) yields sodiated adducts. FIG.6shows an analysis in the negative mode of ionization, in which data for calibrations can be achieved, as long as the appropriate salt is used. In negative ion mode, with 1% ammonium acetate used as an anion source in 1% ammonia, IMS103 (IMS103-C, IMS103-D, and IMS103-E) yields acetate adducts. In another embodiment of the invention, compounds exhibiting a range of compactness, from high CCS and low m/z (more extended) to low CCS and high m/z (more compact) are disclosed. By tuning the compactness of the calibrants (e.g., varying peripheral groups from long, extended linear fatty acids, to short, mass-dense iodinated aromatic rings) a larger area of the ion mobility mass spectrometry graph may be covered by calibration points, rather than a single linear trend as observed by most of the existing calibrations systems. EXAMPLES Example 1 Butanoate Functionalized Cores (IMS 004) To a round bottom flask was added one or more of the following “core” compounds: ethylene glycol (“B”), tris(hydroxymethyl)ethane (“C”), pentaerythritol (“D”), xylitol (“E”), dipentaerythritol (“F”), tripentaerythritol “H”), or bis-MPA dendrimers made from the above cores. These were dissolved in tetrahydrofuran. 1.1 molar equivalents (per —OH of the hydroxyl terminated cores or dendrimers) of butanoic acid were added to the solution of cores. To these reagents were added 1.2 molar equivalents (per —OH of the hydroxyl terminated cores or dendrimers) of dicyclohexylcarbodiimide and 0.1 molar equivalents (per —OH of hydroxyl-terminated core or of dendrimer) of 4-dimethylaminopyridine (DMAP). The reaction mixture was stirred vigorously for approximately 12 hours at standard temperature and pressure. The reaction was monitored by MALDI-TOF MS to confirm completion of the reaction for each of the cores present in the reaction. After complete esterification is observed by MALDI-TOF MS, the flask contents were transferred to a separatory funnel, diluted with dichloromethane, extracted twice with 1M aqueous NaHSO4(sodium bisulfate) and extracted twice with 1M aqueous NaHCO3(sodium bicarbonate). The organic layer was reduced in vacuo to concentrate the sample. A MALDI-TOF MS spectra of the purified product confirmed the purity of the mixture of esterified products and is shown inFIG.7. FIG.7shows MALDI-TOF MS data for IMS 008 C-F, the product of octanoic acid functionalization of cores C, D, E, and F. Example 2 Octanoate Functionalized Cores (IMS 008 C-F) To a round bottom flask was added one or more of the following “core” compounds: tris(hydroxymethyl)ethane (“C”), pentaerythritol (“D”), xylitol (“E”), dipentaerythritol (“F”) made from the above cores. These were dissolved in tetrahydrofuran. 1.1 molar equivalents (per —OH of the hydroxyl terminated cores or dendrimers) of Octanoic Acid were added to the solution of cores. To these reagents were added 1.2 molar equivalents (per —OH of the hydroxyl terminated cores or dendrimers) of dicyclohexylcarbodiimide and 0.1 molar equivalents (per —OH of hydroxyl-terminated core or of dendrimer) of 4-dimethylaminopyridine (DMAP). The reaction mixture was stirred vigorously for approximately 12 hours at standard temperature and pressure. The reaction was monitored by MALDI-TOF MS to determine completion of the reaction for each of the cores present in the reaction. After complete esterification is observed by MALDI-TOF MS, the flask contents were transferred to a separatory funnel, diluted with dichloromethane, extracted twice with 1M aqueous NaHSO4(sodium bisulfate) and extracted twice with 1M aqueous NaHCO3(sodium bicarbonate). The organic layer was reduced in vacuo to concentrate the sample. A MALDI-TOF MS spectra of the purified product confirmed the purity of the mixture of esterified products and is shown inFIG.8. FIG.8shows MALDI-TOF MS data for IMS 008 C-F, the product of octanoic acid functionalization of cores C, D, E, and F. Example 3 Dodecanoate Functionalized Cores (IMS 012 C-F) FIG.9shows a scheme for the synthesis of IMS 012 C-F. To a round bottom flask was added one or more of the following “core” compounds: tris(hydroxymethyl)ethane (“C”), pentaerythritol (“D”), xylitol (“E”), dipentaerythritol (“F”) made from the above cores. These were dissolved in tetrahydrofuran. 1.1 molar equivalents (per —OH of the hydroxyl terminated cores or dendrimers) of Dodecanoic Acid were added to the solution of cores. To these reagents were added 1.2 molar equivalents (per —OH of the hydroxyl terminated cores or dendrimers) of dicyclohexylcarbodiimide and 0.1 molar equivalents (per —OH of hydroxyl-terminated core or of dendrimer) of 4-dimethylaminopyridine (DMAP). The reaction mixture was stirred vigorously for approximately 12 hours at standard temperature and pressure. The reaction was monitored by MALDI-TOF MS to determine completion of the reaction for each of the cores present in the reaction. After complete esterification is observed by MALDI-TOF MS, the flask contents were transferred to a separatory funnel, diluted with dichloromethane, extracted twice with 1M aqueous NaHSO4(sodium bisulfate) and extracted twice with 1M aqueous NaHCO3(sodium bicarbonate). The organic layer was reduced in vacuo to concentrate the sample. A MALDI-TOF MS spectra of the purified product confirmed the purity of the mixture of esterified products and is shown inFIG.10. FIG.10shows MALDI-TOF MS data for IMS 012 C-F, the product of dodecanoic acid functionalization of cores C, D, E, and F. Example 4 Octadecanoate Functionalized Core (IMS 018 H) To a round bottom flask was added one or more of the following “core” compounds: tripentaerythritol (“H”) made from the above cores. These were dissolved in tetrahydrofuran. 1.1 molar equivalents (per —OH of the hydroxyl terminated cores or dendrimers) of Octadecanoic Acid were added to the solution of cores. To these reagents were added 1.2 molar equivalents (per —OH of the hydroxyl terminated cores or dendrimers) of dicyclohexylcarbodiimide and 0.1 molar equivalents (per —OH of hydroxyl-terminated core or of dendrimer) of 4-dimethylaminopyridine (DMAP). The reaction mixture was stirred vigorously for approximately 12 hours at standard temperature and pressure. The reaction was monitored by MALDI-TOF MS to determine completion of the reaction for each of the cores present in the reaction. After complete esterification is observed by MALDI-TOF MS, the flask contents were transferred to a separatory funnel, diluted with dichloromethane, extracted twice with 1M aqueous NaHSO4(sodium bisulfate) and extracted twice with 1M aqueous NaHCO3(sodium bicarbonate). The organic layer was reduced in vacuo to concentrate the sample. A MALDI-TOF MS spectra of the purified product confirmed the purity of the mixture of esterified products and is shown inFIG.11. FIG.11shows MALDI-TOF MS data for IMS 018 H, the product of octadecanoic acid functionalization of core H (IMS018H). Example 5 Octadecanoate Functionalized G1 Dendrimer Cores (IMS 018 C1-F1) FIG.12shows a scheme for the synthesis of IMS 018 C1-F1. To a round bottom flask was added one or more of the following “core” compounds: the first generation of bis-MPA dendrimers from the following 4 cores: tris(hydroxymethyl)ethane (“C1”), pentaerythritol (“D1”), xylitol (“E1”), dipentaerythritol (“F1”) made from the above cores. These were dissolved in tetrahydrofuran. 1.1 molar equivalents (per —OH of the hydroxyl terminated cores or dendrimers) of Octadecanoic Acid were added to the solution of cores. To these reagents were added 1.2 molar equivalents (per —OH of the hydroxyl terminated cores or dendrimers) of dicyclohexylcarbodiimide and 0.1 molar equivalents (per —OH of hydroxyl-terminated core or of dendrimer) of 4-dimethylaminopyridine (DMAP). The reaction mixture was stirred vigorously for approximately 12 hours at standard temperature and pressure. The reaction was monitored by MALDI-TOF MS to determine completion of the reaction for each of the cores present in the reaction. After complete esterification is observed by MALDI-TOF MS, the flask contents were transferred to a separatory funnel, diluted with dichloromethane, extracted twice with 1M aqueous NaHSO4(sodium bisulfate) and extracted twice with 1M aqueous NaHCO3(sodium bicarbonate). The organic layer was reduced in vacuo to concentrate the sample. A MALDI-TOF MS spectra of the purified product confirmed the purity of the mixture of esterified products and is shown inFIG.13. FIG.13shows MALDI-TOF MS data for IMS 018 C1-F1, the product of octadecanoic acid functionalization of cores C1, D1, E1, and F1. Example 6 Docosanoate Functionalized Cores (IMS 022 C-F) To a round bottom flask was added one or more of the following “core” compounds: tris(hydroxymethyl)ethane (“C”), pentaerythritol (“D”), xylitol (“E”), dipentaerythritol (“F”) made from the above cores. These were dissolved in tetrahydrofuran. 1.1 molar equivalents (per —OH of the hydroxyl terminated cores or dendrimers) of Docosanoic Acid were added to the solution of cores. To these reagents were added 1.2 molar equivalents (per —OH of the hydroxyl terminated cores or dendrimers) of dicyclohexylcarbodiimide and 0.1 molar equivalents (per —OH of hydroxyl-terminated core or of dendrimer) of 4-dimethylaminopyridine (DMAP). The reaction mixture was stirred vigorously for approximately 12 hours at standard temperature and pressure. The reaction was monitored by MALDI-TOF MS to determine completion of the reaction for each of the cores present in the reaction. After complete esterification is observed by MALDI-TOF MS, the flask contents were transferred to a separatory funnel, diluted with dichloromethane, extracted twice with 1M aqueous NaHSO4(sodium bisulfate) and extracted twice with 1M aqueous NaHCO3(sodium bicarbonate). The organic layer was reduced in vacuo to concentrate the sample. A MALDI-TOF MS spectra of the purified product confirmed the purity of the mixture of esterified products and is shown inFIG.14. FIG.14shows MALDI-TOF MS data for IMS 022 C-F, the product of docosanoic acid functionalization of cores C, D, E, and F. Example 7 Benzoate Functionalized Cores (IMS 100 C-F) To a round bottom flask was added one or more of the following “core” compounds: tris(hydroxymethyl)ethane (“C”), pentaerythritol (“D”), xylitol (“E”), dipentaerythritol (“F”) made from the above cores. These were dissolved in tetrahydrofuran. 1.1 molar equivalents (per —OH of the hydroxyl terminated cores or dendrimers) of Benzoic Acid were added to the solution of cores. To these reagents were added 1.2 molar equivalents (per —OH of the hydroxyl terminated cores or dendrimers) of dicyclohexylcarbodiimide and 0.1 molar equivalents (per —OH of hydroxyl-terminated core or of dendrimer) of 4-dimethylaminopyridine (DMAP). The reaction mixture was stirred vigorously for approximately 12 hours at standard temperature and pressure. The reaction was monitored by MALDI-TOF MS to determine completion of the reaction for each of the cores present in the reaction. After complete esterification is observed by MALDI-TOF MS, the flask contents were transferred to a separatory funnel, diluted with dichloromethane, extracted twice with 1M aqueous NaHSO4(sodium bisulfate) and extracted twice with 1M aqueous NaHCO3(sodium bicarbonate). The organic layer was reduced in vacuo to concentrate the sample. A MALDI-TOF MS spectra of the purified product confirmed the purity of the mixture of esterified products and is shown inFIG.15. FIG.15shows MALDI-TOF MS data for IMS 100 C-F, the product of benzoic acid functionalization of cores C, D, E, and F. Example 8 Triiodobenzoate Functionalized Cores (IMS 103 C-F) FIG.16shows a scheme for the synthesis of IMS 103 C-F. To a round bottom flask was added one or more of the following “core” compounds: tris(hydroxymethyl)ethane (“C”), pentaerythritol (“D”), xylitol (“E”), dipentaerythritol (“F”) made from the above cores. These were dissolved in tetrahydrofuran. 1.1 molar equivalents (per —OH of the hydroxyl terminated cores or dendrimers) of Triiodobenzoic Acid were added to the solution of cores. To these reagents were added 1.2 molar equivalents (per —OH of the hydroxyl terminated cores or dendrimers) of dicyclohexylcarbodiimide and 0.1 molar equivalents (per —OH of hydroxyl-terminated core or of dendrimer) of 4-dimethylaminopyridine (DMAP). The reaction mixture was stirred vigorously for approximately 12 hours at standard temperature and pressure. The reaction was monitored by MALDI-TOF MS to determine completion of the reaction for each of the cores present in the reaction. After complete esterification is observed by MALDI-TOF MS, the flask contents were transferred to a separatory funnel, diluted with dichloromethane, extracted twice with 1M aqueous NaHSO4(sodium bisulfate) and extracted twice with 1M aqueous NaHCO3(sodium bicarbonate). The organic layer was reduced in vacuo to concentrate the sample. A MALDI-TOF MS spectra of the purified product confirmed the purity of the mixture of esterified products and is shown inFIG.17. FIG.17shows MALDI-TOF MS data for IMS 103 C-F, the product of triiodobenzoic acid functionalization of cores C, D, E, and F. Example 9 Triiodobenzoate Functionalized Cores (IMS 103 H) To a round bottom flask was added one or more of the following “core” compounds: tripentaerythritol (“H”) made from the above cores. These were dissolved in tetrahydrofuran. 1.1 molar equivalents (per —OH of the hydroxyl terminated cores or dendrimers) of Triiodobenzoic Acid were added to the solution of cores. To these reagents were added 1.2 molar equivalents (per —OH of the hydroxyl terminated cores or dendrimers) of dicyclohexylcarbodiimide and 0.1 molar equivalents (per —OH of hydroxyl-terminated core or of dendrimer) of 4-dimethylaminopyridine (DMAP). The reaction mixture was stirred vigorously for approximately 12 hours at standard temperature and pressure. The reaction was monitored by MALDI-TOF MS to determine completion of the reaction for each of the cores present in the reaction. After complete esterification is observed by MALDI-TOF MS, the flask contents were transferred to a separatory funnel, diluted with dichloromethane, extracted twice with 1M aqueous NaHSO4(sodium bisulfate) and extracted twice with 1M aqueous NaHCO3(sodium bicarbonate). The organic layer was reduced in vacuo to concentrate the sample. A MALDI-TOF MS spectra of the purified product confirmed the purity of the mixture of esterified products and is shown inFIG.18. FIG.18shows MALDI-TOF MS data for IMS 004 H, the product of triiodobenzoic acid functionalization of core H. Example 10 Triiodobenzoate Functionalized G1 Dendrimer Cores (IMS 103 C1-F1) FIG.19shows a scheme for the synthesis of IMS 103 C1-F1. To a round bottom flask was added one or more of the following “core” compounds: the first generation of bis-MPA dendrimers from the following 4 cores: tris(hydroxymethyl)ethane (“C1”), pentaerythritol (“D1”), xylitol (“E1”), dipentaerythritol (“F1”) made from the above cores. These were dissolved in tetrahydrofuran. 1.1 molar equivalents (per —OH of the hydroxyl terminated cores or dendrimers) of Triiodobenzoic Acid are added to the solution of cores. To these reagents were added 1.2 molar equivalents (per —OH of the hydroxyl terminated cores or dendrimers) of dicyclohexylcarbodiimide and 0.1 molar equivalents (per —OH of hydroxyl-terminated core or of dendrimer) of 4-dimethylaminopyridine (DMAP). The reaction mixture was stirred vigorously for approximately 12 hours at standard temperature and pressure. The reaction was monitored by MALDI-TOF MS to determine completion of the reaction for each of the cores present in the reaction. After complete esterification is observed by MALDI-TOF MS, the flask contents were transferred to a separatory funnel, diluted with dichloromethane, extracted twice with 1M aqueous NaHSO4(sodium bisulfate) and extracted twice with 1M aqueous NaHCO3(sodium bicarbonate). The organic layer was reduced in vacuo to concentrate the sample. A MALDI-TOF MS spectra of the purified product confirmed the purity of the mixture of esterified products and is shown inFIG.20. FIG.20shows MALDI-TOF MS data for IMS 103 C1-F1, the product of triiodobenzoate acid functionalization of cores C1, D1, E1 and F1. Example 11 Triiodobenzoate Functionalized Amine Cores FIG.21shows the MALDI-TOF mass spectrum for the product, i.e., N,N,N-Tris-(2-aminoethyl)amine-tris(triodobenzamide) or N,N′,N″-(nitrilotris(ethane-2,1-diyI))tris(2,3,5-triiodobenzamide) of the amidation reaction between N,N,N-tris(2-aminoethyl)amine and 2,3,5-triiodobenzoic acid. Example 12 Stability of IMS Calibrants FIG.22shows representative example of stability of IMS calibrants under ambient conditions—IMS 103 H at 0 months (bottom panel) and after 9 months (top panel) of storage. This data shows after 9 months at ambient conditions (e.g., exposed to room temperature, light, and air), no sign of degradation of these calibrants was observed. Advantages of the present disclosure include calibrant compounds exhibiting a range of compactness, from high CCS with low m/z (more extended) to low CCS with high m/z (more compact). These compounds may serve as calibration points that cover a larger area of the ion mobility-mass spectrometry graph. The compactness of the calibrants may be tuned (e.g. varying peripheral groups from long, extended linear fatty acids, to short, mass-dense iodinated aromatic rings) to adjust the range of values on the x-axis (e.g. m/z) relative to those on the y-axis (e.g. CCS) in ion mobility-mass spectrometry spectra in order to improve the quality of calibration. Thus, these calibrants may be used in a variety of analytical instruments, in addition to IM-MS, e.g., in a mass spectrometer, an ion mobility spectrometer, a light scattering spectrometer, and a size exclusion chromatograph. All references cited in this specification are herein incorporated by reference as though each reference was specifically and individually indicated to be incorporated by reference. The citation of any reference is for its disclosure prior to the filing date and should not be construed as an admission that the present disclosure is not entitled to antedate such reference by virtue of prior invention. It will be understood that each of the elements described above, or two or more together may also find a useful application in other types of methods differing from the type described above. Without further analysis, the foregoing will so fully reveal the gist of the present disclosure that others can, by applying current knowledge, readily adapt it for various applications without omitting features that, from the standpoint of prior art, fairly constitute essential characteristics of the generic or specific aspects of this disclosure set forth in the appended claims. The foregoing embodiments are presented by way of example only; the scope of the present disclosure is to be limited only by the following claims. | 50,867 |
11862447 | DETAILED DESCRIPTION OF THE INVENTION An embodiment of the present invention is directed to an apparatus (also referred to herein as a DART-neutral excluder-MS) for detecting a substance, the apparatus comprising: a direct analysis in real time (DART) apparatus; a mass spectrometer (MS) apparatus; and a neutral excluder. The neutral excluder may be in communication with the DART and MS to form a direct analysis in real time-neutral excluder-mass spectrometer (DART-neutral excluder-MS). An embodiment of the present invention is also directed to an apparatus for detecting a substance, the apparatus comprising: a mesh; direct analysis in real time with mass spectrometry (“DART-MS”) apparatus; a DART-MS substance chamber; and a DART-MS interface comprising a purified gas flow. The mesh may comprise a metal or other suitable material. In another embodiment, the DART-MS substance chamber may comprise: a housing; a cavity in communication with a mass spectrometry (“MS”) inlet; an orifice directing a direct analysis in real time (“DART”) ion stream; an orifice for receiving a substance; and a cavity for receiving a substance and DART ion stream wherein the DART ion stream contacts the substance. In one embodiment, the apparatus for detecting a substance comprises: a direct analysis in real time with mass spectrometry (“DART-MS”) apparatus; a neutral excluder; a particulate filter; an after-DART modifier; and a vessel. The neutral excluder may comprise: a first housing having a first end and second end and forming an outer cavity space; a second housing with a first end and second end, disposed within the outer cavity space, and forming a middle cavity space; a third housing with a first and second end, disposed within the middle cavity, and forming an inner cavity; a first inlet for receiving ionized matter; and a second inlet for receiving gas. The apparatus may further comprise an organic solvent. The apparatus may further comprise a suction pump. An embodiment of the present invention is directed to an apparatus for detecting a substance, the apparatus comprising: a direct analysis in real time (DART) apparatus; a mass spectrometer (MS) apparatus; and a neutral excluder. The DART may be a pulsed DART or a continuous flow DART. The neutral excluder may be in communication with the DART and MS to form a direct analysis in real time-neutral excluder-mass spectrometer (DART-neutral excluder-MS). The neutral excluder may comprise: a housing; a first inlet for receiving purified air and/or alcohol vapors; a second inlet for receiving a substance; a first outlet in communication with a pump; and a second outlet in communication with a mass spectrometer. The housing may comprise a first half comprising the first inlet and second outlet. The housing may also comprise a second half comprising the second inlet and first outlet. The DART-neutral excluder-MS may further comprise a conduit in communication with the first outlet and a suction pump. The DART-neutral excluder-MS may also comprise a vessel containing a vaporous alcohol in communication with the first inlet. The apparatus may comprise: a mesh; direct analysis in real time with mass spectrometry (“DART-MS”) apparatus; a DART-MS substance chamber; and a DART-MS interface comprising a purified gas flow. The DART-MS substance chamber may comprise: a housing; a cavity in communication with an MS inlet; an orifice directing a DART ion stream; an orifice for receiving a substance; and a cavity for receiving a substance and DART ion stream wherein the DART ion stream contacts the substance. The purified gas may comprise, but not be limited to, air, nitrogen, helium, or a combination thereof. The DART-MS substance chamber may be in communication with the DART-MS interface. The DART-MS substance chamber and DART-MS interface may be at least partially disposed between the DART and MS. Gas may be flowed through the apparatus to purify the substance. An embodiment of the present invention is also directed to a method for detecting a substance, the method comprising: flowing a substance into a DART ion stream; generating a mixture comprising ionic and non-ionic particulate matter in a gas phase; flowing the mixture into a neutral excluder; contacting the mixture with an alcohol; separating the ionic particulate matter from the non-ionic particular matter in the mixture; and flowing the ionic particulate matter into a mass spectrometer. In one embodiment, the method comprises: flowing a substance in an after-DART modifier; contacting the substance with a DART ion stream to form a gaseous ionized substance; flowing the gaseous ionized substance into a neutral excluder to form a purified gaseous ionized substance and neutral matter; and flowing neutral matter into a particulate filter. The method may further comprise flowing the purified gaseous ionized substance into a mass spectrometer. The method may further comprise flowing a gas through the neutral excluder. An embodiment of the present invention is also directed to a method for detecting a substance, the method comprising: flowing a dust into a DART ion stream to form a mixture of ionic and non-ionic matter in a gas phase; flowing the mixture into a neutral excluder; contacting the mixture with purified air; separating the ionic matter from the non-ionic matter in the mixture; and flowing the ionic matter into a mass spectrometer. The purified air may comprise alcohol vapors and the alcohol may comprise methanol, ethanol, 2-propanol, butanol, or a combination thereof. The method may further comprise applying a negative pressure and/or suction to flow the mixture into and/or through the neutral excluder. The method may further comprise: flowing the mixture into a first channel; flowing ions and/or ionic matter into a second channel; flowing purified air into a third channel; contacting the ions and/or ionic matter with the purified air an intersection of the second and third channel to form a flow of ions and/or ionic matter in purified air, and flowing the ionic matter in purified air out of the neutral excluder. In one embodiment, the method may comprise: contacting a substance with a mesh; at least partially disposing the mesh and substance within a DART-MS substance chamber; contacting the substance with a DART-MS ion stream to produce gaseous ion of the substance; flowing the gaseous ions of the substance into a DART-MS interface; and isolating the gaseous ions of the substance from other matter. The gaseous ions of the substance may be isolated by a flow of gas, e.g., purified gas. In another embodiment, the method further comprises flowing the isolated gaseous ions of the substance into a mass spectrometer. Gas may be flowed through the apparatus and may purify the substance. The substance may be organic or not organic. The substance may comprise agricultural products including nuts and/or other agricultural products as described herein. The nuts may comprise, but not be limited to, pistachios. The substance may comprise agricultural dust including, but not limited to, pistachio dust. The mass spectrometer may be any mass spectrometer including, but not limited to, an ion mobilization mass spectrometer, a tandem mass spectrometer, a Fourier-transform mass spectrometer, an ion cyclotron resonance mass spectrometer, a matrix-assisted laser desorption and/or ionization time-of-flight mass spectrometer, an inductively coupled plasma mass spectrometer, or a combination thereof. The mass spectrometer may be used in combination with a gas chromatograph, a liquid chromatograph, or a combination thereof. The apparatus may also further comprise a liquid and/or gas chromatograph. The apparatus may prevent fouling of the mass spectrometer. Fouling may be prevented by separating ions from neutral particles in the neutral excluder to reduce the amount of substance and/or increase the purity and/or proportion of ions entering the mass spectrometer. The apparatus may be capable of continuous monitoring. Continuous monitoring may be performed by disposing a substance into the apparatus at a constant rate. The apparatus may also be a capable of interval monitoring, batch monitoring, pulse monitoring, or a combination thereof. Interval monitoring, batch monitoring, pulse monitoring may be performed by disposing a substance into the apparatus at intervals, as a batch of substance, or as a pulse of substance, respectively. The term “substance” is defined as a chemical compound. The chemical compound may be in an ionized state and may be a solid, liquid, and/or gas. The substance may be particulate matter, a dust, a fine, an extract, or a combination thereof. The term “dust” is defined as the particles generated by agricultural processing. “Dust” may include, but is not limited to, nut dust, nut particles, nut particulate matter, particulate nut waste; and dust, particles, particulate matter, and particulate waste from any of the following: agricultural products, nuts, including but not limited to, pistachios, almonds, pecans, walnuts, cashews, peanuts, other nut products; corn, soybean, wheat, grains, sorghum, rice, chili, coffee, grapes, cocoa, cacao, legumes, chocolate, potatoes, tuberous vegetables, cereal, figs, animal feed other agricultural products; carrots, radishes, cassava, artichoke, jicama, sweet potato, yam, taro, water chestnut, turmeric, ginseng, lotus root, ginger, groundnut, turnips, parsley root, alfalfa, barley, oats, cereals, rye, canola, cottonseed, beets, sugarcane, roughages, pasture grass, hay, silage, straw, cornstalk; or a combination thereof. “Dust” may further include, but is not limited to, shells, shavings, or chaff derived from the substances listed herein. The terms “ion” or “ionic matter” are defined as matter that has a non-neutral charge. Turning now to the figures,FIG.1shows DART-neutral excluder-MS40with a modifier after DART and in a curtain gas of neutral excluder. Substance42is flowed into separator46via conduit44. Waste is removed from separator46via conduit48by vacuum50. Substance42then flows into modifier after DART54. Substance is ionized with DART52and flowed to neutral excluder56. Purified air58is flowed through conduit60and into vessel64where gas58contacts alcohol62before flowing into neutral excluder56to contact and purify substance42. Waste matter is captured by particulate filter68. Flow throughout the system is maintained, at least in part, by suction pump70. Purified ionized substance is flowed into mass spectrometer66from neutral excluder56. FIG.2shows DART-neutral excluder-MS72with a modifier after DART and in a curtain gas of neutral excluder. Substance42is flowed into modifier after DART54. Substance is ionized with DART52and flowed to neutral excluder56. Purified air58is flowed through conduit60and into vessel64where gas58contacts alcohol62before flowing into neutral excluder56to contact and purify substance42. Waste matter is captured by filter68. Flow throughout the system is maintained, at least in part, by suction pump70. Purified ionized substance is flowed into mass spectrometer66from neutral excluder56. FIG.3shows neutral excluder channel system74shown with the interior channel regions of a neutral excluder. Gas flow76that includes, but is not limited to, dust, aerosols, vapors, and ions enters channel78. The gas flow bifurcates at channel intersection80. At least part of gas flow76enters channel84, with remaining gas flow82exiting channel80. Purified air enters through channel88and meets with the gas flow at channel intersection90to form gas ions in purified air. The gas ions in purified air may then enter a capillary tube channel92to be directed to a mass spectrometer for analysis. Neutral excluder channel system74is charged to allow the separation of ions from neutral particles and direct ions to capillary tube channel92. Insulators86are disposed along channel84. Optionally, insulators86are ceramic insulator layers. FIG.4shows the total aflatoxin in pistachio-associated dust. Aflatoxin is detected in samples of pistachio-associated dust. FIG.5shows aflatoxin standards IMS. Aflatoxins B1 and G2 and an aflatoxin mixture show distinct peaks. FIG.6shows the detection limit of aflatoxin using mass spectrometry where aflatoxin at 1 ng/μL is equivalent to 1 ppb and aflatoxin at 10 ng/μL is equivalent to 10 ppb. Aflatoxin at 10 ng/μL shows a larger peak than 1 ng/μL. FIG.7shows the chemical structures of key aflatoxins. Aflatoxins B194, B296, G198, G2100, M1102, and M2104. FIG.8shows the chemical and physical properties of aflatoxins and explosive substances RDX, PETN, and Tetryl. The molar masses and vapor pressures for aflatoxins are similar to the explosive substances. FIG.9shows results from heating a substance spiked with four aflatoxins where there was an increased mass ion intensity for aflatoxins. Spectra106shows peaks for B1108, B2110, G1112, and G2114. FIG.10shows a DART-neutral excluder-MS116with an attached filter. DART118is in communication with neutral excluder56. Neutral excluder56is in communication with mass spectrometer66and particle68. FIG.11Ashows a DART-neutral excluder-MS120with an improved DART and a first-generation DART for reference. DART-neutral excluder-MS120comprises improved DART122, mass spectrometer66, neutral excluder56, and filter68. Improved DART122is in communication with neutral excluder56. Neutral excluder56is in communication with filter68and mass spectrometer66. First-generation DART51is shown for reference and may be used in place of improved DART122.FIG.11Bshows a DART-neutral excluder-MS124with tubular DART126. DART-neutral excluder-MS124comprises tubular DART126, neutral excluder56, mass spectrometer66, and filter68. Tubular DART126is in communication with neutral excluder56. Neutral excluder56is in communication with neutral excluder66and filter68. FIG.12AandFIG.12Bshow a DART-neutral excluder-MS with improved DART embodiments.FIG.12Ashows DART-neutral excluder-MS128comprising improved DART130, neutral excluder56, mass spectrometer66and filter68. Improved DART130is in communication with neutral excluder56. Neutral excluder56is in communication with mass spectrometer66and filter68.FIG.12Bshows DART-neutral excluder-MS132comprising DART134, neutral excluder56, filter68, conduit138, conduit140, conduit144, conduit146, electrodes136, and electrodes142. Electrodes136are attached to DART134. DART134is in communication with conduit138and conduit140. Conduit140is in communication with neutral excluder56. Electrodes142are attached to neutral excluder56. Neutral excluder56is in communication with conduit144, filter68, and conduit146. A substance to be analyzed flows into conduit138and contacts DART ion stream from DART134to form ionized particles. The substance passes through conduit140and flows into neutral excluder56. Air flows into neutral excluder56via conduit144and neutral excluder56separates ions from neutral particles. Ions enter a mass spectrometer and neutral particles enter filter68and filtered air passes into conduit146. FIG.13shows a cyclone separator. Cyclone separator148comprises input150, vessel152, collection bin154, and outlet156. Outlet156is attached to vessel152. Vessel152is attached to collection bin154and outlet156. FIG.14AandFIG.14Bshow a DART-neutral excluder-MS and a sample mesh. Setup158comprises DART mount160and mass spectrometer66. Sample mount162comprises outer plate164and mesh166. FIG.15shows dust collection from a pistachio nut production belt. Dust collection system168comprises inlet cone172and conduit174. Dust is collected from moving pistachio belt170. FIG.16shows a DART-MS apparatus modified to analyze dust or extract, with mass spectrometer66and DART mounting176positioned to accept a DART-MS substance chamber and DART-MS interface. FIG.17shows prepared substance178. Solvent substance was dried on stainless-steel mesh180to form substance extract182. FIG.18shows DART-MS substance chamber184in detail. Housing188rests on mounting190and orifice186allows a DART ion stream to contact substance extract182dried on stainless-steel mesh180. FIG.19shows DART-MS interface192with neutral excluder56including chamber194facilitating substance isolation with purified air. Neutral excluder56is attached to DART-MS substance chamber196. DART51is positioned to direct its ion stream at a substance at least partially disposed within DART-MS substance chamber196. FIG.20shows DART-neutral excluder-MS apparatus with a modifier after DART198. DART51is in communication with modifier after DART200. FIG.21shows DART-neutral excluder-MS apparatus202. Neutral excluder56is in communication with mass spectrometer66via second outlet208; suction conduit210via chamber196; DART51via second inlet204; and purified air conduit206via chamber194. FIG.22shows neutral excluder56. Neutral excluder56comprises housing212, which comprises first half218and second half220. First half218comprises first inlet216and second outlet224. Second half220comprises second inlet214and first outlet222. FIG.23shows a neutral excluder with labeled flows226. Dust and gas ion flow228enters the neutral excluder. A suction flow230is applied to draw dust and gas ion flow228through the neutral excluder. Flow of purified air236enters and combines with dust and gas ion flow228to form a flow of gas ion in purified air234, which subsequently exits the neutral excluder by second outlet (tube connection)238. Optionally, purified air234may be shielded by ceramic plate232. FIG.24shows the mass spectrometry spectra of ambient air in a pistachio processing plant and of dust samples off a surface in the pistachio processing plant. Spectrum of ambient air240is compared to spectrum of dust sample242. Peaks244,246, and248do not appear in spectrum of ambient air240, and indicate the presence of aflatoxin. FIG.25shows real-time monitoring of aflatoxin B1 on pistachio flow for 120 minutes. Peaks for a protonated amino acid at 146 Da, aflatoxin B1 at 313 Da, and an adduct ion of aflatoxin B1 at 146 Da are shown. FIG.26shows real-time monitoring of aflatoxin B1 on pistachio flow for 50 minutes. Peaks for a protonated amino acid at 146 Da, aflatoxin B1 at 313 Da, and an adduct ion of aflatoxin B1 at 146 Da are shown. FIG.27shows real-time monitoring of aflatoxin B1 on pistachio flow between 75 and 120 minutes. Peaks for a protonated amino acid at 146 Da, aflatoxin B1 at 313 Da, and an adduct ion of aflatoxin B1 at 146 Da are shown. FIG.28shows the results from DART-MS analysis of various aflatoxins and associated adduct ions. Aflatoxin ions are adducted according to the formula MH++B→MH+B. Graph250shows an aflatoxin+extract substance with ion-adducted aflatoxins B1 and B2 at peaks252and254, respectively. FIG.29shows LC/MS chromatograph256identifying aflatoxins in dust substances with a diameter greater than about 250 μm at peak258. FIG.30shows LC/MS chromatograph260identifying aflatoxins in dust substances with diameters between about 125 μm to about250pm at peak262. FIG.31shows LC/MS chromatograph264identifying aflatoxins in dust substances with diameters less than about 125 μm at peak266. FIG.32shows example results from an analysis of pistachio dust. The table shows that pistachio dust particles less than 125 microns in diameter have the greater amount of aflatoxin B1. FIGS.33A,FIG.33B, andFIG.33Cshow graphs268,274, and278of direct dust sampling from room air, with DART at 450° C. and no heater. Monitoring dust with known aflatoxin is shown by peaks270and276and monitoring dust without aflatoxin is shown by peak272and280. FIG.34shows the dissociation of aflatoxin, an adducted ion, and a proton by mass spectrometry. Aflatoxin B1282, adducted ion284, and proton286are associated before entering a mass spectrometer. Aflatoxin B1282, adducted ion284, and proton286can dissociate into aflatoxin B1282and proton286, and adducted ion284. Alternatively, aflatoxin B1282, adducted ion284, and proton286can dissociate into aflatoxin282, and adducted ion284and proton286. FIG.35shows the dissociation of an adducted ion. The adducted ion can dissociate into fragment ions. FIG.36Ashows showing the mass spectrometry spectra of an adducted ion. Spectrum of fragmentation of unknown ion (146 Da) at 38V288and spectrum of fragmentation of protonated 2-amino heptanoic acid (146 Da) at 38V290show similar peaks292and294.FIG.36Bshows the mass spectrometry spectra of an adducted ion. Spectrum of 3-aminoheptnaoic acid at −38V296; spectrum of 7-aminoheptanoic acid at −38V298; and spectrum of dust −38V300show similar peaks302and304. The identity of the adducted ion may be 2-aminoheptanoic acid, 3-aminoheptanoic acid, 7-aminoheptanoic acid, or a combination thereof. The apparatus may comprise a neutral excluder. The neutral excluder may comprise: a first housing having a first end and second end and forming an outer cavity space; a second housing with a first end and second end, disposed within the outer cavity space, and forming a middle cavity space; a third housing with a first and second end, disposed within the middle cavity, and forming an inner cavity; a first inlet for receiving ionized matter; and a second inlet for receiving gas. The outer cavity may receive an ionized gas. The middle cavity may receive a gas. The inner cavity may receive a gas comprising e.g., a purified ionized gas. The first end of the first housing may have an orifice. Waste gas may exit through the orifice. The second end of the first housing may be sealed. The first end of the second housing may be in communication with the outer cavity. The second end of the second housing may be sealed. The first end of the third housing may be in communication with the outer cavity. The second end of the third housing may be in communication with a mass spectrometer. The neutral excluder may be in communication with a mass spectrometer, a DART, an after-DART modifier, a particular filter, a vessel, or a combination thereof. The apparatus may further comprise an alcohol. The alcohol may comprise, but not be limited to, propanol, alcohol or other vapor modifiers including volatile organic compounds. The propanol may comprise, but not be limited to,2-propanol. The apparatus may further comprise a suction pump. The apparatus may also comprise a gas. The gas may be purified and may comprise, but not be limited to, air, nitrogen, helium or a combination thereof. The apparatus may further comprise a substance. Gas may be flowed through the neutral excluder and may function to purify the substance. The substance may be organic or not organic. The substance may comprise agricultural products including nuts and/or other agricultural products, including those described herein. The nuts may comprise, but not be limited to, pistachios. The substance may comprise agricultural dust including, but not limited to, pistachio dust. The DART may be a pulsed DART or a continuous flow DART. The apparatus may analyze a substance. The substance may be organic or not organic. The substance may comprise agricultural products including nuts and/or agricultural products as described above. The nuts may comprise pistachios. The substance may comprise agricultural dust including, but not limited to, pistachio dust. The substances may comprise particle sizes of at least about 5 μm, about 5 μm to about 500 μm, about 25 μm to about 450 μm, about 50 μm to about 400 μm, about 75 μm to about 350 μm, about 100 μm to about 300 μm, about 125 μm to about 250 μm, about 150 μm to about 225 μm, about 175 μm to about 200 μm, or about 500 μm. The apparatus may comprise a separator. The separator may comprise a cyclone separator, filter, centrifuge, or a combination thereof. The neutral excluder may comprise an insulator. The insulator may be a layer of material at least partially disposed along the housing and/or channel of the neutral excluder. The insulator may comprise a ceramic material, air, an inert gas, a mesh, a foam, other porous material, or a combination thereof. The apparatus and/or method of the present invention may be used to analyze a substance. The substance may comprise organic matter or not organic matter. The substance may be a solid and/or solid particulate, e.g., dust. The substance may comprise agricultural products including but not limited to nuts and/or grains. The nuts may comprise, but not be limited to, pistachios. The substance may comprise agricultural dust including, but not limited to, dust from agricultural products and/or nuts. The nuts may comprise, but not be limited to, pistachios, almonds, pecans, walnuts, cashews, peanuts, other nut products, or a combination thereof. The agricultural products may comprise, but not be limited to, corn, soybean, wheat, grains, sorghum, rice, chili, coffee, grapes, cocoa, cacao, legumes, chocolate, potatoes, tuberous vegetables, cereal, figs, animal feed, other agricultural products, or a combination thereof. The tuberous vegetables may comprise carrots, radishes, cassava, artichoke, jicama, sweet potato, yam, taro, water chestnut, turmeric, ginseng, lotus root, ginger, groundnut, turnips, parsley root, or a combination thereof. Animal feed may comprise alfalfa, barley, oats, cereals, or a combination thereof. The substance may also comprise a toxin, contaminant, explosive agent, pathogen, amino acid, or a combination thereof. DART ionization, in combination with mass spectrometry, may be used to characterize particulate matter suspended in a flow of gas for the direct determination of aflatoxins without liquid extraction or handling by humans. This invention allows for continuous and/or live detection of aflatoxins in pistachios and other nut and agricultural products. Isopropanol vapors may be introduced into the substance flow to suppress the mass spectral response ions from large numbers of constituents in the substance dust that produce ions of relatively moderate intensity and which complicate the appearance of the mass spectral response. The addition of vapors of isopropanol at least partially eliminates ions between 250 and 600 Da, making a clean baseline for response to aflatoxin adducts. A DART-neutral excluder-MS particulate matter detection limit may be at least 20 ppb. The limits of intensity detection may be reduced by a natural abundance of a substance also with ion mass of 458 Da. An ion at 457 Da is also observed in a substance. In instances when aflatoxin is not present in the measurement, the intensity for 457 Da greater than 458 Da. This inequality may be reversed in the presence of aflatoxin such that the 457 Da ion abundance is less than the 458 Da ion abundance. An additive to replace the 146 Da ion mass may be used. The substance responsible for the 146 Da ion (and thus the adduct 458 Da ion for aflatoxin B1) may be a constituent in the dust and may have a strong proton affinity or favorable ionization properties with DART. Efforts to suppress the formation of this ion have been unsuccessful; however, substitution or replacement might be useful since there is a substance that does produce a 458 Da ion, which is usually checked against 457 Da for detecting aflatoxins. A substance may be used to “tailor” and adduct to a specific mass of choice, for example to locate the adduct ion in a mass region of ultra-low abundance of signal. Detection limits and false positives may be significantly improved with use of the additive. An alternative gas to isopropanol may be used in the DART-neutral excluder-MS. The addition of vapors of isopropanol (rubbing alcohol) to the DART-neutral excluder-MS may improve the measurement of dust for aflatoxins by suppressing the ionization of naturally abundant constituents in the dust. This simplifies the analytical signal (i.e., mass spectra) and this improves interpretations of the mass spectra. Other possible vapor may include, but are not limited to, other volatile organic compounds. The apparatus may be operated under different flow rates. Ionic matter may be flowed into the mass spectrometer at a rate of at least about 0.1 L/min, about 0.1 L/min to about 1.0 L/min, about 0.2 L/min to about 0.9 L/min, about 0.3 L/min to about 0.8 L/min, about 0.4 L/min to about 0.7 L/min, about 0.5 L/min to about 0.6 L/min, or about 1.0 L/min. The substance may be flowed at a rate of at least about 0.2 L/min, about 0.2 L/min to about 2.0 L/min, about 0.4 L/min to about 1.8 L/min, about 0.6 L/min to about 1.6 L/min, about 0.8 L/min to about 1.4 L/min, about 1.0 L/min to about 1.2 L/min, or about 2.0 L/min into the DART energy stream. The DART ion/energy stream may be flowed at rate of at least about 0.3 L/min, about 0.3 L/min to about 3.0 L/min, about 0.6 L/min to about 2.7 L/min, about 0.9 L/min to about 2.4 L/min, about 1.2 L/min to about 2.1 L/min, about 1.5 L/min to about 1.8 L/min, or about 3.0 L/min. The gas phase substance may be passed through the neutral excluder. The substance may comprise a mixture of ionic and nonionic matter. The matter may be particulate matter, dust, gaseous matter, or a combination thereof. The substance may be flowed through the neutral excluder to purify the substance by separating the ionic matter from the nonionic matter. The apparatus may further comprise a suction pump. The suction pump may cause a flow at a rate of at least about 0.1 L/min, about 0.1 L/min to about 5.0 L/min, about 0.5 L/min to about 4.5 L/min, about 1.0 L/min to about 4.0 L/min, about 1.5 L/min to about 3.5 L/min, about 2.0 L/min to about 3.0 L/min, or about 5 L/min. Purified air may be flowed into the neutral excluder at a rate of at least about 0.1 L/min, about 0.1 L/min to about 1.9 L/min, about 0.3 L/min to about 1.7 L/min, about 0.5 L/min to about 1.5 L/min, about 0.7 L/min to about 1.3 L/min, about 0.7 L/min to about 1.1 L/min, or about 1.9 L/min. Ions generated by DART treatment of particulates in a substance flow may pass through the neutral excluder and into the interface of a mass spectrometer, the reaction region of an ion mobility spectrometer, into an ion mobility spectrometer/mass spectrometer, or a combination thereof. The ions generated by DART may be subjected to mass analysis, mobility analysis, or combination thereof. Mass analysis may be performed by mobility or mass spectrometer, including tandem mass spectrometers. The apparatus and method of the present invention may detect toxins in substances. The toxins may comprise aflatoxins. The aflatoxins may comprise the B1, B2, G1, G2, M1, or M2 variants, or a combination thereof. The substances may originate from bins, aspirator units, conveyor or moving belts, the dynamic headspace above nuts, shells, half-shells, or a combination thereof. The substances may comprise a powder or a powder dissolved in a solvent. The substance may comprise particulate matter or particulate matter dissolved in a solvent. The substance may be dried to form an extract. The drying may occur at room temperature. The substance may be vaporized or made gaseous. The substance may be vaporized or made gaseous by a vacuum, and increased temperature, or a combination thereof. The vaporized or gaseous substance may be contacted with gas ions. The gas ions may comprise, but not be limited to,63Ni. The substance may be analyzed for at least about 1 minute, about 1 minute to about 30 minutes, about 5 minutes to about 25 minutes, about 10 minutes to about 20 minutes, or about 30 minutes. The mass spectral response of aflatoxins may be analyzed with respect to the formation and identity of ions derived from DART ionization. Without being bound by a single theory, an ion at 146 Da may be formed from a constituent of substance (e.g., pistachio) matrices. The 146 Da ion may be attributed to a protonated monomer (i.e., MH+, where M is a molecule). The molecule M may have a strong proton affinity which is consistent with a nitrogen-containing substance and the mass may be consistent with a single nitrogen in the substance. The compound may be known from isotropic analysis to contain seven carbon atoms best matching the formula C7H15NO2(atomic mass of 145 g/mol). The molecule may be an amino acid or an ion derived from amino acid after heating (at temperatures of at least 300° C.) in the DART ion source. The 146 Da ion may form an adduct with the aflatoxin molecule (e.g., B1, with atomic mass of 314 g/mol) to form an ion at 458 Da. Other aflatoxins with characteristic atomic masses may also form adducts with the 146 Da 1 ion. The 458 Da ion may be decomposed using a capillary tube interface before reaching the analyzer of the mass spectrometer. A 145 Da ion may also be formed from a constituent of substance (e.g., pistachio) matrices. The 145 Da ion and/or 146 Da ion may be an amino acid. The ions may include, but are not limited to, an ion of 2-aminoheptanoic acid, 3-aminohepatanoic acid, 7-aminoheptanoic acid, or a combination thereof. References to aflatoxins throughout the specification mean aflatoxins in their anionic and/or ionic form and in their natural state and state analyzed through mass spectrometry, HPLC, and/or any other analyzed method. Multiple substances may be taken sequentially or simultaneously. The apparatus and method may analyze the substances on-site without the need to transport the substances from the agricultural processing site. The substances may be monitored continuously and in real-time. Effective substance monitoring based on dust analysis at the aspirator may prevent high level of toxins from entering an agricultural processing facility. Dust substances be obtained by vacuum trapping or mechanical collection. The apparatus and method may have a toxin detection limit at about 1.0 ppb. The presence of toxin in substance may be determined in approximately 5 seconds. The substance volume entering the apparatus may be at least about 0.5 μL, about 0.5 μL to about 3 μL, about 1.0 μL to about 2.5 μL, about 1.5 μL to about 2.0 μL, or about 3. Embodiments of the present invention provide a technology-based solution that overcomes existing problems with the current state of the art in a technical way to satisfy an existing problem for the detection of a substance, e.g., a toxin and/or contaminant, in an agricultural product. Embodiments of the present invention achieve important benefits over the current state of the art, such as increased ease and accuracy in detecting a substance at a production line and/or facility. Some of the unconventional steps of embodiments of the present invention include the combination of DART, a neutral excluder, and a mass spectrometer to detect a substance in solid particulate material. INDUSTRIAL APPLICABILITY The invention is further illustrated by the following non-limiting examples. Example 1 A method for the extraction of nuts and removal of oil was developed. Several methods were evaluated for removing the oils from the dust substances including thin-layer-chromatography (TLC), different extraction methods, and different types of columns. Two types of columns were analyzed. First, immunoaffinity columns specific for aflatoxin were utilized. The columns did work to ‘concentrate’ aflatoxin. A simple filter column, e.g., alumina, was evaluated and did remove the oils from pistachio dust. Further analysis using pistachio dust spiked with a known amount of standard aflatoxin resulted in less than 10% loss of aflatoxin and removal of the oils. Calibration curves were completed for several different injection methods for using IMS including electrospray, direct injection using corona discharge, GC-heated port, and paper-spray. The IMS response to aflatoxin shows multiple peaks and/or shifting of peaks depending upon the quantity of aflatoxin. This is typical when using IMS technology. A ‘pass-fail’ system is useful in accordance with the present invention. Example 2 An aflatoxin mixture was purchased and analyzed using several different IMS introduction methods. A commercially available product was also used as a control system to validate aflatoxin amounts in substances. The products were aflatoxin test strips which were used to provide test substances to determine if aflatoxin was present at quantities greater than or equal to either 10 ppb or 20 ppb. The difference in the indicated concentration was controlled by the amount of solvent used. The result was not quantitative. For instance, if the substance had 500 ppb aflatoxin, this system told the user that aflatoxin is present at a concentration greater than or equal to the cutoff limit used (10 or 20 ppb). The same result would have been indicated for 21 ppb aflatoxin. Electrospray IMS (ESI-IMS) was investigated as an introduction method. These results indicated that ESI-IMS is potentially a viable technology for substance introduction. However, ESI-IMS was susceptible to both particulates and oils in the substance matrix and also the need for a longer ‘purging’ period was found between substances. The use of a gas chromatograph (GC) heated injection port as the approach to introduce aflatoxin standards to an IMS was investigated. In a GC injection port the solvent and substance were heated to a high temperature with the intent to volatilize the substance and solvent. The volatilized chemicals were then swept into the IMS using a flowing gas stream. Direct injection with corona discharge was used. This method was shown to detect aflatoxin below the limit of detection needed. Paper-spray IMS was constructed for introduction of the substance into the IMS. This proved to be a good option if dust is collected on a filter for testing. The inlet system of the present invention eliminated drying of the paper from the heated gas that originated from the IMS. This inlet system has an addition of two exit ports that are connected to a small pump. Example 3 Standards were prepared to review response over a range of quantities. These standards also served to determine the limit of detection for the instrument. Based upon the results from instrument procedures, the paper-spray and electrospray substance introduction technologies were transported along with the laboratory bench top IMS. Substances were collected from a pistachio processing facility and then transported back to a portable lab for extraction and analysis. The paper-spray-IMS demonstrated that it was capable of measuring aflatoxin under field conditions. This was correlated with the use of the aflatoxin test strips. Dust spiked with aflatoxin was placed onto pistachio nuts to look at percentage of aflatoxin recovered for testing. Dust was obtained from beside one of the first conveyor belts early in the processing plant at a farm. The following treatments were then performed for testing the effectiveness of measuring aflatoxin: (1) 200 mg pistachio dust with no added aflatoxin standard; (2) 200 mg pistachio dust with aflatoxin standard added at 40 ppb, added prior to columns; (3) no pistachio dust with aflatoxin standard added at 40 ppb, added prior to columns; (4); 200 mg pistachio dust with 20 ppb aflatoxin standard, added at the end of treatment; and (5) no pistachio dust with 20 ppb aflatoxin standard, added at end of the treatment. For the test setup, a glass vacuum manifold was assembled and one large UTC enviroclean oil filter column was placed in one of the five inlet ports of the manifold. 1000 μl pipette tips were placed into the top of each filter to act as a holding basin for the liquid to be passed through each filter. Clean 15 ml conical tubes were placed under each port to collect the filtered substances. 200 mg of pistachio dust was weighed out for each of treatments 1, 2, and 4. The dust was added to individual 15 ml conical tubes. 4 ml of 70% methanol was added to tubes 1, 2, 3, 4, and 5. 4 μl of aflatoxin standard was added to substances 2 and 3. All substances were shaken for one minute. With the vacuum turned on and not exceeding 34 kPa, 2 ml of each substance were passed through each corresponding filter and collected in the conical tubes below. 2 μl of aflatoxin standard was added to substances 4 and 5. All substances were mixed gently. 250 μl of each substance was transferred into an individual epi tube. 250 μl of deionized water was also added to each epi tube and mixed gently using the pipette. A test strip was added to each epi tube and allowed to develop for fifteen minutes. The pistachio dust alone did not have aflatoxin levels at or higher than 20 ppb. The spiked substances all tested positive and it was inferred from these results that there was minimal loss of aflatoxin during the process. Overall, this test concluded that the extraction process designed to remove aflatoxin from pistachio dust was effective and did appear to give an accurate quantification of the amount of aflatoxin present in the original substance. The preceding examples can be repeated with similar success by substituting the generically or specifically described reactants and/or operating conditions of this invention for those used in the preceding examples. Note that in the specification and claims, “about” or “approximately” means within twenty percent (20%) of the numerical amount cited. Although the invention has been described in detail with particular reference to these embodiments, other embodiments can achieve the same results. Variations and modifications of the present invention will be obvious to those skilled in the art and it is intended to cover in the appended claims all such modifications and equivalents. The entire disclosures of all references, applications, patents, and publications cited above are hereby incorporated by reference. | 41,743 |
11862448 | DESCRIPTION OF THE ILLUSTRATIVE EMBODIMENTS For the purposes of promoting an understanding of the principles of this disclosure, reference will now be made to a number of illustrative embodiments shown in the attached drawings and specific language will be used to describe the same. This disclosure relates to an electrostatic linear ion trap (ELIT) including an apparatus for calibrating or resetting the charge detector thereof, and to means and methods for controlling both. In one embodiment, an example of which will be described in detail below with respect toFIGS.3A-3E, the calibration apparatus is controlled in a manner which calibrates or resets the charge detector of the ELIT to a predefined reference charge level between ion measurement events. In another embodiment, an example of which will be described in detail below with respect toFIGS.5A-5F, the calibration apparatus is controlled in a manner which calibrates or resets the charge detector of the ELIT to a predetermined reference charge level between charge detection events. For purposes of this disclosure, the phrase “charge detection event” is defined as detection of a charge associated with an ion passing a single time through the charge detector of the ELIT, and the phrase “ion measurement event” is defined as a collection of charge detection events resulting from oscillation of an ion back and forth through the charge detector a selected number of times or for a selected time period. Referring toFIG.1, a charge detection mass spectrometer (CDMS)10is shown including an embodiment of an electrostatic linear ion trap (ELIT)14with control and measurement components coupled thereto and including an apparatus for calibrating or resetting the charge detector of the ELIT14. In the illustrated embodiment, the CDMS10includes an ion source12operatively coupled to an inlet of the ELIT14. As will be described further with respect toFIG.6A, the ion source12illustratively includes any conventional device or apparatus for generating ions from a sample and may further include one or more devices and/or instruments for separating, collecting, filtering, fragmenting and/or normalizing ions according to one or more molecular characteristics. As one illustrative example, which should not be considered to be limiting in any way, the ion source12may include a conventional electrospray ionization source, a matrix-assisted laser desorption ionization (MALDI) source or the like, coupled to an inlet of a conventional mass spectrometer. The mass spectrometer may be of any conventional design including, for example, but not limited to a time-of-flight (TOF) mass spectrometer, a reflectron mass spectrometer, a Fourier transform ion cyclotron resonance (FTICR) mass spectrometer, a quadrupole mass spectrometer, a triple quadrupole mass spectrometer, a magnetic sector mass spectrometer, or the like. In any case, the ion outlet of the mass spectrometer is operatively coupled to an ion inlet of the ELIT14. The sample from which the ions are generated may be any biological or other material. In the illustrated embodiment, the ELIT14illustratively includes a charge detector CD surrounded by a ground chamber or cylinder GC and operatively coupled to opposing ion mirrors M1, M2respectively positioned at opposite ends thereof. The ion mirror M1is operatively positioned between the ion source12and one end of the charge detector CD, and ion mirror M2is operatively positioned at the opposite end of the charge detector CD. Each ion mirror M1, M2defines a respective ion mirror region R1, R2therein. The regions R1, R2of the ion mirrors M1, M2, the charge detector CD, and the spaces between the charge detector CD and the ion mirrors M1, M2together define a longitudinal axis22centrally therethrough which illustratively represents an ideal ion travel path through the ELIT14and between the ion mirrors M1, M2as will be described in greater detail below. In the illustrated embodiment, voltage sources V1, V2are electrically connected to the ion mirrors M1, M2respectively. Each voltage source V1, V2illustratively includes one or more switchable DC voltage sources which may be controlled or programmed to selectively produce a number, N, programmable or controllable voltages, wherein N may be any positive integer. Illustrative examples of such voltages will be described below with respect toFIGS.2A and2Bto establish one of two different operating modes of each of the ion mirrors M1, M2as will be described in detail below. In any case, ions move within the ELIT14along the longitudinal axis22extending centrally through the charge detector CD and the ion mirrors M1, M2under the influence of electric fields selectively established by the voltage sources V1, V2. The voltage sources V1, V2are illustratively shown electrically connected by a number, P, of signal paths to a conventional processor16including a memory18having instructions stored therein which, when executed by the processor16, cause the processor16to control the voltage sources V1, V2to produce desired DC output voltages for selectively establishing ion transmission and ion reflection electric fields, TEF, REF respectively, within the regions R1, R2of the respective ion mirrors M1, M2. P may be any positive integer. In some alternate embodiments, either or both of the voltage sources V1, V2may be programmable to selectively produce one or more constant output voltages. In other alternative embodiments, either or both of the voltage sources V1, V2may be configured to produce one or more time-varying output voltages of any desired shape. It will be understood that more or fewer voltage sources may be electrically connected to the mirrors M1, M2in alternate embodiments. The charge detector CD is illustratively provided in the form of an electrically conductive cylinder which is electrically connected to a signal input of a charge sensitive preamplifier (or charge sensitive amplifier) CP, and the signal output of the charge preamplifier CP is electrically connected to the processor16. The charge preamplifier CP is illustratively operable in a conventional manner to receive a charge signal (CH) corresponding to a charge induced on the charge detection cylinder CD by an ion passing therethrough, to produce a charge detection signal (CHD) corresponding thereto and to supply the charge detection signal CHD to the processor16. In some embodiments, the charge preamplifier CP may include conventional feedback components, e.g., one or more resistors and/or other conventional feedback circuitry, coupled between the output and at least one of the inputs thereof. In some alternate embodiments, the charge preamplifier CP may not include any resistive feedback components, and in still other alternate embodiments the charge preamplifier CP may not include any feedback components at all. In any case, the processor16is, in turn, illustratively operable to receive and digitize charge detection signals CHD produced by the charge preamplifier CP, and to store the digitized charge detection signals CHD in the memory18. The processor16is further illustratively coupled to one or more peripheral devices20(PD) for providing signal input(s) to the processor16and/or to which the processor16provides signal output(s). In some embodiments, the peripheral devices20include at least one of a conventional display monitor, a printer and/or other output device, and in such embodiments the memory18has instructions stored therein which, when executed by the processor16, cause the processor16to control one or more such output peripheral devices20to display and/or record analyses of the stored, digitized charge detection signals. The voltage sources V1, V2are illustratively controlled in a manner, as described in detail below, which selectively traps an ion entering the ELIT14and causes the trapped ion to oscillate back and forth between the ion mirrors M1, M2such that it repeatedly passes through the charge detection cylinder CD. A plurality of charge and oscillation period values are measured at the charge detection cylinder CD, and the recorded results are processed to determine mass-to-charge ratio, charge and mass values of the ion trapped in the ELIT14. Referring now toFIGS.2A and2B, embodiments are shown of the ion mirrors M1, M2respectively of the ELIT14depicted inFIG.1. Illustratively, the ion mirrors M1, M2are identical to one another in that each includes a cascaded arrangement of 4 spaced-apart, electrically conductive mirror electrodes. For each of the ion mirrors M1, M2, a first mirror electrode301has a thickness W1and defines a passageway centrally therethrough of diameter P1. An endcap32is affixed or otherwise coupled to an outer surface of the first mirror electrode301and defines an aperture A1centrally therethrough which serves as an ion entrance and/or exit to and/or from the corresponding ion mirror M1, M2respectively. In the case of the ion mirror M1, the endcap32is coupled to, or is part of, an ion exit of the ion source12illustrated inFIG.1. The aperture A1for each endcap32illustratively has a diameter P2. A second mirror electrode302of each ion mirror M1, M2is spaced apart from the first mirror electrode301by a space having width W2. The second mirror electrode302, like the mirror electrode301, has thickness W1and defines a passageway centrally therethrough of diameter P2. A third mirror electrode303of each ion mirror M1, M2is likewise spaced apart from the second mirror electrode302by a space of width W2. The third mirror electrode302has thickness W1and defines a passageway centrally therethrough of width P1. A fourth mirror electrode304is spaced apart from the third mirror electrode303by a space of width W2. The fourth mirror electrode304illustratively has a thickness of W1and is formed by a respective end of the ground cylinder, GC disposed about the charge detector CD. The fourth mirror electrode304defines an aperture A2centrally therethrough which is illustratively conical in shape and increases linearly between the internal and external faces of the ground cylinder GC from a diameter P3defined at the internal face of the ground cylinder GC to the diameter P1at the external face of the ground cylinder GC (which is also the internal face of the respective ion mirror M1, M2). The spaces defined between the mirror electrodes301-304may be voids in some embodiments, i.e., vacuum gaps, and in other embodiments such spaces may be filled with one or more electrically non-conductive, e.g., dielectric, materials. The mirror electrodes301-304and the endcaps32are axially aligned, i.e., collinear, such that a longitudinal axis22passes centrally through each aligned passageway and also centrally through the apertures A1, A2. In embodiments in which the spaces between the mirror electrodes301-304include one or more electrically non-conductive materials, such materials will likewise define respective passageways therethrough which are axially aligned, i.e., collinear, with the passageways defined through the mirror electrodes301-304and which illustratively have diameters of P2or greater. Illustratively, P1>P3>P2, although in other embodiments other relative diameter arrangements are possible. A region R1is defined between the apertures A1, A2of the ion mirror M1, and another region R2is likewise defined between the apertures A1, A2of the ion mirror M2. The regions R1, R2are illustratively identical to one another in shape and in volume. As described above, the charge detector CD is illustratively provided in the form of an elongated, electrically conductive cylinder positioned and spaced apart between corresponding ones of the ion mirrors M1, M2by a space of width W3. In on embodiment, W1>W3>W2, and P1>P3>P2, although in alternate embodiments other relative width arrangements are possible. In any case, the longitudinal axis22illustratively extends centrally through the passageway defined through the charge detection cylinder CD, such that the longitudinal axis22extends centrally through the combination of the passageways defined by the regions R1, R2of the ion mirrors M1, M2and the passageway defined through the charge detection cylinder CD. In operation, the ground cylinder GC is illustratively controlled to ground potential such that the fourth mirror electrode304of each ion mirror M1, M2is at ground potential at all times. In some alternate embodiments, the fourth mirror electrode304of either or both of the ion mirrors M1, M2may be set to any desired DC reference potential, or to a switchable DC or other time-varying voltage source. In the embodiment illustrated inFIGS.2A and2B, the voltage sources V1, V2are each configured to each produce four DC voltages D1-D4, and to supply the voltages D1-D4to a respective one of the mirror electrodes301-304of the respective ion mirror M1, M2. In some embodiments in which one or more of the mirror electrodes301-304is to be held at ground potential at all times, the one or more such mirror electrodes301-304may alternatively be electrically connected to the ground reference of the respective voltage supply V1, V2and the corresponding one or more voltage outputs D1-D4may be omitted. Alternatively or additionally, in embodiments in which any two or more of the mirror electrodes301-304are to be controlled to the same non-zero DC values, any such two or more mirror electrodes301-304may be electrically connected to a single one of the voltage outputs D1-D4and superfluous ones of the output voltages D1-D4may be omitted. Each ion mirror M1, M2is illustratively controllable and switchable, by selective application of the voltages D1-D4, between an ion transmission mode (FIG.2A) in which the voltages D1-D4produced by the respective voltage source V1, V2establishes an ion transmission electric field (TEF) in the respective region R1, R2thereof, and an ion reflection mode (FIG.2B) in which the voltages D1-D4produced by the respect voltage source V1, V2establishes an ion reflection electric field (REF) in the respective region R1, R2thereof. As illustrated by example inFIG.2A, once an ion from the ion source12flies into the region R1of the ion mirror M1through the inlet aperture A1of the ion mirror M1, the ion is focused toward the longitudinal axis22of the ELIT14by an ion transmission electric field TEF established in the region R1of the ion mirror M1via selective control of the voltages D1-D4of V1. As a result of the focusing effect of the transmission electric field TEF in the region R1of the ion mirror M1, the ion exiting the region R1of the ion mirror M1through the aperture A2of the ground chamber GC attains a narrow trajectory into and through the charge detector CD, i.e., so as to maintain a path of ion travel through the charge detector CD that is close to the longitudinal axis22. An identical ion transmission electric field TEF may be selectively established within the region R2of the ion mirror M2via like control of the voltages D1-D4of the voltage source V2. In the ion transmission mode, an ion entering the region R2from the charge detection cylinder CD via the aperture A2of M2is focused toward the longitudinal axis22by the ion transmission electric field TEF within the region R2so that the ion exits the ion mirror M2through the aperture A1thereof. As illustrated by example inFIG.2B, an ion reflection electric field REF established in the region R2of the ion mirror M2via selective control of the voltages D1-D4of V2acts to decelerate and stop an ion entering the ion region R2from the charge detection cylinder CD via the ion inlet aperture A2of M2, to accelerate the ion in the opposite direction back through the aperture A2of M2and into the end of the charge detection cylinder CD adjacent to M2as depicted by the ion trajectory42, and to focus the ion toward the central, longitudinal axis22within the region R2of the ion mirror M2so as to maintain a narrow trajectory of the ion back through the charge detector CD toward the ion mirror M1. An identical ion reflection electric field REF may be selectively established within the region R1of the ion mirror M1via like control of the voltages D1-D4of the voltage source V1. In the ion reflection mode, an ion entering the region R1from the charge detection cylinder CD via the aperture A2of M1is decelerated and stopped by the ion reflection electric field REF established within the region R1, then accelerated in the opposite direction back through the aperture A2of M1and into the end of the charge detection cylinder CD adjacent to M1, and focused toward the central, longitudinal axis22within the region R1of the ion mirror M1so as to maintain a narrow trajectory of the ion back through the charge detector CD and toward the ion mirror M2. An ion that traverses the length of the ELIT14and is reflected by the ion reflection electric field REF in the ion regions R1, R2in a manner that enables the ion to continue traveling back and forth through the charge detection cylinder CD between the ion mirrors M1, M2as just described is considered to be trapped within the ELIT14. Example sets of output voltages D1-D4produced by the voltage sources V1, V2respectively to control a respective one of the ion mirrors M1, M2to the ion transmission and reflection modes described above are shown in TABLE I below. It will be understood that the following values of D1-D4are provided only by way of example, and that other values of one or more of D1-D4may alternatively be used. TABLE IIon MirrorOperating ModeOutput Voltages (volts DC)TransmissionV1: D1 = 0, D2 = 95, D3 = 135, D4 = 0V2: D1 = 0, D2 = 95, D3 = 135, D4 = 0ReflectionV1: D1 = 190, D2 = 125, D3 = 135, D4 = 0V2: D1 = 190, D2 = 125, D3 = 135, D4 = 0 While the ion mirrors M1, M2and the charge detection cylinder CD are illustrated inFIGS.1-2Bas defining cylindrical passageways therethrough, it will be understood that in alternate embodiments either or both of the ion mirrors M1, M2and/or the charge detection cylinder CD may define non-cylindrical passageways therethrough such that one or more of the passageway(s) through which the longitudinal axis22centrally passes represents a cross-sectional area and profile that is not circular. In still other embodiments, regardless of the shape of the cross-sectional profiles, the cross-sectional areas of the passageway defined through the ion mirror M1may be different from the passageway defined through the ion mirror M2. The voltage sources V1, V2are illustratively controlled in a manner which selectively establishes ion transmission and ion reflection electric fields in the region R1of the ion mirror M1and in the region R2of the ion mirror M2in a manner which allows ions to enter the ELIT14from the ion source12, and which causes an ion to be selectively trapped within the ELIT14such that the trapped ion repeatedly passes through the charge detector CD as it oscillates within the ELIT14between the ion mirrors M1and M2. A charge induced on the charge detector CD each time an ion passes therethrough is detected by the charge preamplifier CP, and a corresponding charge detection signal (CHD) is produced by the charge preamplifier CP. The magnitude and timing of timing of the charge detection signal (CHD) produced by the charge preamplifier CP is recorded by the processor16for each charge detection event as this term is defined herein. Each charge detection event record illustratively includes an ion charge value, corresponding to a magnitude of the detected charge, and an oscillation period value, corresponding to the elapsed time between charge detection events, and each charge detection event record is stored by the processor16in the memory18. The collection of charge detection events resulting from oscillation of an ion back and forth through the charge detector CD a selected number of times or for a selected time period, i.e., a making up an ion measurement event as this term is defined herein, are then processed to determine charge, mass-to-charge ratio and mass values of the ion. In one embodiment, the ion measurement event data are processed by computing, with the processor16, a Fourier Transform of the recorded collection of charge detection events. The processor16is illustratively operable to compute such a Fourier Transform using any conventional digital Fourier Transform (DFT) technique such as for example, but not limited to, a conventional Fast Fourier Transform (FFT) algorithm. In any case, the processor16is then illustratively operable to compute an ion mass-to-charge ratio value (m/z), an ion charge value (z) and ion mass values (m), each as a function of the computed Fourier Transform. The processor16is illustratively operable to store the computed results in the memory18and/or to control one or more of the peripheral devices20to display the results for observation and/or further analysis. It is generally understood that the mass-to-charge ratio (m/z) of an ion oscillating back and forth through the charge detector CD of an ELIT between opposing ion mirrors M1, M2thereof is inversely proportional to the square of the fundamental frequency ff of the oscillating ion according to the equation: m/z=C/ff2, where C is a constant that is a function of the ion energy and also a function of the dimensions of the respective ELIT, and the fundamental frequency ff is determined directly from the computed Fourier Transform. The value of the ion charge, z, is proportional to the magnitude FTMAG of the fundamental frequency ff, taking into account the number of ion oscillation cycles. In some cases, the magnitude(s) of one or more of the harmonic frequencies of the FFT may be added to the magnitude of the fundamental frequency for purposes of determining the ion charge, z. In any case, ion mass, m, is then calculated as a product of m/z and z. The processor16is thus operable to compute m/z=C/ff2, z=F(FTMAG) and m=(m/z)(z). Multiple, e.g., hundreds or thousands or more, ion trapping events are typically carried out for any particular sample from which the ions are generated by the ion source12, and ion mass-to-charge, ion charge and ion mass values are determined/computed for each such ion trapping event. The ion mass-to-charge, ion charge and ion mass values for such multiple ion trapping events are, in turn, combined to form spectral information relating to the sample. Such spectral information may illustratively take different forms, examples of which include, but are not limited to, ion count vs. mass-to-charge ratio, ion charge vs. ion mass (e.g., in the form of an ion charge/mass scatter plot), ion count vs. ion mass, ion count vs. ion charge, or the like. Referring again toFIG.1, the illustrated ELIT14further includes a charge generator CG electrically connected to the processor16and electrically connected to a charge generator voltage source VCG. In the illustrated embodiment, the charge generator voltage source VCG is programmable or manually controllable to produce one or more DC voltages, voltage pulses and/or voltage waveforms of any magnitude, shape, duration and/or frequency. In alternate embodiments, the charge generator voltage source VCG may be operatively coupled to the processor16so that the processor16may control the charge generator voltage source VCG to produce one or more DC voltages, voltage pulses and/or voltage waveforms of any magnitude, shape, duration and/or frequency. In the illustrated embodiment at least one charge outlet passage24of the charge generator CG illustratively extends through the ground chamber GC such that a charge outlet26of the charge outlet passage24is in fluid communication with a space36defined between the inner surface of the ground chamber GC and the outer surface of the charge detection cylinder CD. In the illustrated embodiment, a single charge outlet passage24is shown extending through the ground chamber GC, although in alternate embodiments multiple charge outlet passages may extend through the ground chamber GC. In such embodiments, two or more charge outlet passages may be singly spaced apart, or spaced apart in groups of two or more, axially and/or radially along the charge detection cylinder CD. In one embodiment, the charge generator CG is configured to be responsive to a control signal C produced by the processor16to generate free charges28which pass through the charge outlet26of the one or more charge outlet passages24into the space36defined between the inner surface of the ground chamber or cylinder GC and the outer surface of the electrically conductive charge detection cylinder CD. In the illustrated embodiment, the charges28produced by the charge generator are positive charges, although the charge generator CG may in alternate embodiments be configured to produce negative charges or to selectively produce positive or negative charges. In one embodiment, the charge generator CG is configured, or controllable using conventional control circuitry and/or conventional control techniques, to be responsive to activation of the control signal C produced by the control circuit16to generate and supply to the space36within the ELIT14a predictable number of free charges28, within any desired tolerance level, per unit of time. The unit of time may have any desired duration. In such embodiments, the total number of charges28supplied by the charge generator CG to the space36within the ELIT14in response to a single activation of the control signal C is thus controllable as a function of the number of charges28produced by the charge generator CG per unit time and a duration, i.e., pulse width, of the active portion of the control signal C. In alternate embodiments, the charge generator CG may be configured to produce a programmable number of charges28per unit time. In still other embodiments, the charge detector CG may be configured such that the number of charges28produced thereby in response to the control signal C is constant and predictable, or programmable, within any desired tolerance level, regardless and independently of the duration of the control signal C. In such embodiments, the number of charges28supplied by the charge generator CG to the space36within the ELIT14in response to any single activation of the control signal C is thus constant and predictable, and the total number of charges28that may be supplied by the charge generator CG to the space36within the ELIT14is controllable as a function of the total number of charges28produced with each single activation of the control signal C and the total number of activations of the control signal C produced by the processor16. The charge generator CG may be provided in the form of any conventional charge generator. As one example, the charge generator CG may be or include a conventional filament responsive to a voltage or current applied thereto to generate and produce the free charges28. As another example, the charge generator CG may be or include an electrically conductive mesh or grid responsive to a voltage or current applied thereto to generate and produce the free charges28. As yet another example, the charge generator CG may be or include a particle charge generator configured to produce the free charges in the form of charged particles from a sample source. Examples of such particle charge generators may include, but are not limited to, an electrospray ionization (ESI) source, a matrix-assisted Laser Desorption Ionization (MALDI) source, or the like. In any case, the charge generator CG is operable to generate and supply charges to the space36within the ELIT14via the charge outlet(s) of the one or more charge outlet passages extending into, and/or fluidly coupled to, the space36. With no charge induced on the charge detector CD by a charged particle passing therethrough or by one or more free charges28produced by the charge generator GC, the charge detection cylinder CD illustratively operates at or near a reference charge level CHREF. As the charge detection cylinder CD is not powered or grounded, the reference charge level CHREFis typically tens of charges (i.e., elementary charges “e”) or less, although in some applications the reference charge level CHREFmay be more than tens of charges. As described above, the charge generator CG is responsive to control signals C produced by the processor16or other control signal generating circuitry to generate charges28of desired polarity which then pass into the space36between the inner surface of the ground cylinder GC and the outer surface of the charge detection cylinder CD. As the ground cylinder GC is generally maintained at ground potential and the charge detection cylinder CD typically operates at or near ground potential, the space36is substantially a field-free region. In some embodiments, the one or more charge outlet passages24and/or the body of the charge generator CG illustratively include(s) one or more regions in which an electric field of suitable direction is established by the voltage source VCG (or by some other source(s)) for the purpose of accelerating the generated charges28into the field free region36so that the accelerated charges28then travel through the field free region36toward and into contact with the outer surface of the charge detection cylinder CD. When such charges28contact the outer surface of the charge detection cylinder CD, they impart their respective charges onto the charge detection cylinder CD. In this regard, the generation of charges28by the charge generator GC, and travel of the generated charges through the field free region36toward and into contact with the outer surface of the charge detection cylinder to thereby impart their charges onto the charge detection cylinder defines a “charge injection” process via which the generated charges28calibrate or reset the charge detection cylinder CD and/or the charge sensitive preamplifier CP in some embodiments thereof. Such injected charges may illustratively be removed from the charge detection cylinder CD by applying an equal amount of opposite charge, and may therefore illustratively be used to calibrate and/or reset the charge detection cylinder in some applications and/or to calibrate or reset the charge preamplifier in other applications. The “charge injection” process just described is different from a “charge induction” process in which charge may be induced on the charge detection cylinder CD by establishing a voltage difference between the charge detection cylinder CD and a voltage reference, e.g., ground potential. One illustrative technique for inducing charge on the charge detection cylinder CD without physically coupling one or more wires and/or one or more electronic devices to the charge detection cylinder CD is to configure the charge generator GC such that the voltage source VCG establishes a potential of desired polarity on the at least one charge outlet passage24. Establishing a DC potential on the at least one charge outlet passage24without generating charges28will generally create an electric field between the at least one charge outlet passage24and the charge detection cylinder CD, thus inducing a DC voltage and, in turn, a charge on the charge detection cylinder CD. The magnitude of the induced charge will generally be dependent upon the strength of the established electric field and thus upon the magnitude of the voltage applied by the voltage source VCG to the at least one charge outlet passage24. Such induced charges may illustratively be removed or modified by applying a different voltage, e.g., ground or other potential, to the charge detection cylinder CD, and may therefore be used to compensate for switching voltages applied to the ion mirror(s) M1and/or M2, and for calibrating the charge preamplifier CP in some embodiments thereof. In alternate embodiments of the charge generator CG described above in which the charge generator CG is operable to generate free charges, the charge generator CG may thus be configured to operate as a charge induction antenna. In such embodiments, the voltage source VCG is controlled, illustratively by the processor16, to produce a DC voltage, a voltage pulse or a series of voltage pulses, or a voltage waveform which is/are applied to the charge outlet passage(s)24to create or establish one or more corresponding electric fields between the charge outlet passage(s)24generally (and in some embodiments the charge outlet(s)26specifically) and the charge detection cylinder CD to thereby induce a corresponding charge or charges on the charge detection cylinder. In such embodiments, the charge outlet passage(s)24may, but need not, include one or more charge outlets26in fluid communication with the space36. In some embodiments, for example, in which the charge generator CG is configured strictly for charge induction, the charge outlet passage(s)24may be or include one or more electrically conductive rods, probes, filaments or the like which does/do not include any outlets for dispensing or otherwise producing free charges. In other embodiments in which the charge generator CG is configured to operate as a charge induction device and a charge injection device, the charge outlet passage(s)24will illustratively include one or more charge outlets24as described above for dispensing or otherwise producing free charges28. Thus, in some embodiments, the charge generator CG is illustratively configured to operate strictly as a charge injection device in which the charge generator CG is responsive to control signals C to generate charges28of suitable polarity and to accelerate the generated charges28out of the at least one charge outlet26of the at least one charge outlet passage24and into the field free region36such that the generated charges28travel through the field free region36toward and into contact with the external surface of the charge detection cylinder CD to impart their charges on the charge detection cylinder CD. In alternate embodiments, the charge generator CG may illustratively be configured to operate strictly as a charge induction device in which the charge generator CG is responsive to control signals C to apply at least one voltage of suitable magnitude and polarity to establish a corresponding electric field within the region36between the at least one charge outlet passage24and the charge detection cylinder CD to induce a DC voltage, and thus a charge, on the charge detection cylinder CD. In other alternate embodiments, the charge generator CD may illustratively be configured to operate both (e.g., simultaneously or separately) as a charge injection device and as a charge induction device in which the charge generator CG is responsive to control signals C produced by the processor16to generate charges28of suitable polarity and/or to apply one or more voltages of suitable magnitude and polarity to establish an electric field within the region36between the at least one charge outlet passage24and the charge detection cylinder CD to (i) induce a DC voltage, and thus a charge, on the charge detection cylinder CD, and (ii) to also accelerate the generated charges28, under the influence of the established electric field within the region36, toward and into contact with the external surface of the charge detection cylinder CD to impart their charges on the charge detection cylinder CD. The charge generator CG may thus be configured and operable strictly as a charge injector, strictly as a charge inducer or as a combination charge injector and charge inducer. In embodiments in which the charge generator CG is configured and operable as a charge injector to produce a controlled number of charges28which then travel to, or are transported to, and in contact with the outer surface of the charge detection cylinder CD, such charges illustratively impart a target charge level, CHT, on the charge detection cylinder CD. In one embodiment, the number and polarity of the generated charges28may be selected to impart a target charge level CHTthat is greater than CHREF, e.g., to achieve a constant target charge level CHTwhich is above CHREFand any noise induced thereon, and in other embodiments the number and polarity of the generated charges28may be selected to impart a target charge level CHTthat is less than CHREF, e.g., to achieve a target charge level CHTat or near a zero charge level. In embodiments in which the charge generator CG is configured and operable as a charge inducer to controllably establish an electric field which induces a DC voltage or potential on the charge detection cylinder CD, such DC voltage or potential illustratively induces the target charge level CHTof suitable magnitude and polarity on the charge detection cylinder CD. In embodiments in which the charge generator CG is configured and operable as a combination charge injector and charge inducer, the net charge induced and imparted on the charge detection cylinder is the target charge CHTof suitable magnitude and polarity. The reference charge level CHREFon the charge detection cylinder CD is subject to one or more potentially significant sources of charge noise which may introduce uncertainty in charge detection events as a result of uncertainty in the reference charge level at any point in time. Referring toFIG.3A, for example, a plot is shown of charge CH on the charge detection cylinder CD vs. time in which no charge detection events are present but in which an example charge noise waveform50is shown superimposed on the reference charge level CHREF. In embodiments in which the charge sensitive preamplifier CP does not include feedback components, one such source of such charge noise50is an accumulation of charges on the charge detection cylinder CD and thus at the input of the charge sensitive preamplifier CP during normal operation thereof. In this and other embodiments, capacitance of the charge detector CD also contributes, as does spurious noise caused by external events and extraneous charges induced on the charge detection cylinder resulting from switching of either or both of the ion mirrors M1, M2between ion transmission and ion reflection modes of operation. Such charge noise50, from any source, is undesirable as it can produce false charge detection events and/or can require setting a charge detection threshold higher than desired. As an example of the former case, the plot ofFIG.3Afurther illustrates an example charge detection threshold CHTH1implemented in the ion mass detection system10for the purpose of distinguishing valid charge detection events from the reference charge level CHREF. In the illustrated example, two peaks52,54of the charge noise50present at and around CHREFexceed CHTH1and will thus be incorrectly or falsely detected as valid charge detection events, thereby corrupting the ion measurement event data for the ion(s) being evaluated. As an example of the latter case, a second example charge detection threshold CHTH2is also illustrated inFIG.3Awhich is illustratively positioned safely above the highest peak of the charge noise50so as to avoid false charge detection events of the type just described. However, the higher charge detection threshold CHTH2leaves an undesirably large range of undetectable charge values between CHTH2and CHREFwhich would otherwise be detectable but for the high level of charge noise50. In the embodiment of the ELIT14illustrated inFIG.1, the charge generator CG is illustratively implemented and controlled to selectively generate a target number of charges28which are transported through the field free region36to, and into contact with, the outer surface of the charge detection cylinder CD, e.g., under the influence of one or more suitably directed electric fields at or within the charge generator CG as described above. The charges28deposited on the charge detection cylinder CD illustratively combine with any charge noise carried on the charge detection cylinder CD to produce a substantially constant, predictable and repeatable target charge level, CHT, on the charge detection cylinder CD. In one example embodiment, the target number and polarity of the generated charges28may be selected to impart a target charge level CHTon the charge detection cylinder which is greater in magnitude than the combination of the reference charge level CHREFand any charge noise present on the charge detection cylinder CD. The target charge level CHTin this example embodiment thus envelopes and overrides the combination of CHREFand any charge noise, leaving a new and substantially constant charge reference in the form of CHT. Alternatively or additionally, the charge generator CG may be controlled to induce a suitable charge on the charge detection cylinder CD by controlling the voltage source VCG to apply one or more corresponding voltages to the charge generator CG. In alternate embodiments, the target number and polarity of the generated charges28may be selected to neutralize at least one or the combination of the reference charge level CHREFand any charge noise present on the charge detection cylinder CD so as to induce a resulting target charge level CHTon the charge detection cylinder CD which is less than CHREF, e.g., to achieve a target charge level CHTor near a zero charge level. Such a result may illustratively be accomplished by controlling the charge generator CG to first inject positive charges and to then inject negative charges, or to alternatively induce a suitable charge on the charge detection cylinder CD by controlling the voltage source VCG to apply one or more corresponding voltages to the charge generator CG. In some embodiments in which an amount of charge noise50at the input charge sensitive preamplifier CP is specifically targeted (e.g., in embodiments in which the charge sensitive preamplifier does not include any feedback components as described above), the target charge level CHTmay be a charge magnitude and/or polarity which, when deposited or imparted on the charge detection cylinder CD, acts to clear such charge noise50therefrom and thus from the input of the charge preamplifier so as to reset the charge sensitive preamplifier CP to predictable operating conditions. In any case, the target number of charges28generated by the charge generator CG and transported to, and in contact with, the outer surface of the charge detection cylinder CD and/or the charge induced on the charge detection cylinder CD by the operation of the charge generator CG, operate to set the charge detection cylinder CD to a substantially predictable and repeatable target charge level CHT, as illustrated by example inFIG.3B. The target charge level CHTestablishes a “new” reference charge level against which subsequent charge detection events are measured. As the new reference charge level CHTis substantially repeatable, a substantial reduction in the charge difference between a charge detection threshold CHTH3and CHTcan be realized as also illustrated inFIG.3B, thereby increasing the range of detectable ion charge as compared with conventional ELITs. Referring now toFIGS.4A-4E, simplified diagrams of the ELIT14ofFIG.1are shown demonstrating sequential control and operation of the ion mirrors M1, M2, as described above, and of the charge generator CG to calibrate or reset the charge detection cylinder CD between ion measurement events. Referring toFIG.4A, the ELIT14has just concluded an ion measurement event in which an ion was trapped in the ELIT14and in which the processor16was operable to control the voltage sources V1, V2to control the ion mirrors M1, M2to the ion reflection modes of operation (R) in which ion reflection electric fields were established in the regions R1, R2of each respective ion mirror M1, M2. The ion thus oscillated back and forth between M1and M2, each time passing through the charge detection cylinder CD whereupon the charge induced thereby on the charge detection cylinder CD was detected by the charge preamplifier CP and the ion detection event was recorded by the processor16. After the ion had oscillated back and forth through the ELIT14between the ion mirrors M1, M2a selected number of times or for a selected time period, the processor16was operable to control the voltage source V2to control the ion mirror M2to the ion transmission mode (T) of operation by establishing an ion transmission field within the region R2of the ion mirror M2, while maintaining the ion mirror M1in the ion reflection mode (R) of operation as illustrated inFIG.4A. As a result, the trapped ion exits the ion mirror M2via the aperture A2of M2as illustrated by the ion trajectory60inFIG.4A. When the ELIT14has been operating in the state illustrate inFIG.4Afor a selected time period, or for a selected time period in which no charge detection events occur, the processor16is operable to supply a control signal C to the charge generator CG to cause the charge generator CG to controllably generate a target number of free charges28and supply the free charges28to the space36defined between the ground cylinder GC and the charge detection cylinder CD, as illustrated inFIG.4B. In charge injection operation of the charge generator CG, the generated free charges28travel toward, and into contact with, the external surface of the charge detection cylinder CD through the field-free region36as described above. In charge induction operation, an electric field established by the charge generator voltage source VCG or other electric field generation structure induces a charge, on the charge detection cylinder CD. As the ion mirror M1has been in the reflection mode (R) of operation and the ion mirror M2has been in the transmission mode (T) of operation for a time period sufficient to clear the ELIT14of an ions, no ions are transported through the charge detection cylinder CD as the free charges28are generated and travel to the charge detection cylinder CD during charge injection operation. As such, the target number of charges28generated by the charge generator CG contacting the outer surface of the charge detection cylinder CD and imparting their charges thereon operate to calibrate or reset the charge detection cylinder CD to a substantially constant, predictable and repeatable target charge level CHTas described above. In charge induction operation, the charge induced on the charge detection cylinder CD by the electric field established by the charge generator CG may similarly be used for calibration and/or reset. Referring now toFIG.4C, after the charge detection cylinder CD has been calibrated to the target charge level CHT, the processor16is operable to control the voltage source V1to control the ion mirror M1to the ion transmission mode of operation (T) by establishing an ion transmission field within the region R1of the ion mirror M1, while also maintaining the ion mirror M2in the ion transmission mode (T) of operation. As a result, ions generated by the ion source12and entering the ion mirror M1are passed through the ion mirror M1, through the charge detection cylinder CD, through the ion mirror M2and out of the ion mirror M2via the aperture A1of the ion mirror M2as described above and as illustrated by the ion trajectory62inFIG.4C. In some embodiments, a conventional ion detector25, e.g., one or more microchannel plate detectors, is positioned adjacent to the ion exit aperture A1of the ion mirror M2, and ion detection information provided by the detector25to the processor16may be used to adjust one or more of the components and/or operating conditions of the ELIT14to ensure adequate detection of ions passing through the charge detection cylinder CD. Referring now toFIG.4D, after both of the ion mirrors M1, M2have been operating in ion transmission operating mode for a selected time period, the processor16is operable to control the voltage source V2to control the ion mirror M2to the ion reflection mode (R) of operation by establishing an ion reflection field within the region R2of the ion mirror M2, while maintaining the ion mirror M1in the ion transmission mode (T) of operation as shown. As a result, ions generated by the ion source12and entering the ion mirror M1are passed through the ion mirror M1, through the charge detection cylinder CD, and into the ion mirror M2where they are reflected back into the charge detection cylinder CD by the ion reflection field (R) established in the region R2of M2, as illustrated by the ion trajectory64inFIG.4D. Referring now toFIG.4E, the processor16is operable to control the voltage source V1to control the ion mirror M1to the ion reflection mode (R) of operation by establishing an ion reflection field within the region R1of the ion mirror M1, while maintaining the ion mirror M2in the ion reflection mode (R) of operation as shown. In one embodiment, the processor16is illustratively operable, i.e., programmed, to control the ELIT14in a “random trapping mode” in which the processor16is operable to control the ion mirror M1to the reflection mode (R) of operation after the ELIT has been operating in the state illustrated inFIG.4D, i.e., with M1in ion transmission mode and M2in ion reflection mode, for a selected time period. Until the selected time period has elapsed, the ELIT14is controlled to operate in the state illustrated inFIG.4D. In an alternate embodiment, the processor16is operable, i.e., programmed, to control the ELIT14in a “trigger trapping mode” in which the processor16is operable to control the ion mirror M1to the reflection mode (R) of operation until an ion is detected at the charge detector CD. Until such detection, the ELIT14is controlled to operate in the state illustrated inFIG.4D. Detection by the processor16of a charge on the charge detector CD is indicative of an ion passing through the charge detector CD toward the ion mirror M1or toward the ion mirror M2, and serves as a trigger event which causes the processor16to control the voltage source V1to switch the ion mirror M1to the ion reflection mode (R) of operation to thereby trap the ion within the ELIT14. With both of the ion mirrors M1, M2controlled to the ion reflection operating mode (R), the ion is made to oscillate back and forth between the regions R1and R2of the respective ion mirrors M1, M2by the ion reflection electric fields established therein, as described above and as illustrated by the ion trajectory66depicted inFIG.4E. In one embodiment, the processor16is operable to maintain the operating state illustrated inFIG.4Euntil the ion passes through the charge detection cylinder CD a selected number of times. In an alternate embodiment, the processor16is operable to maintain the operating state illustrated inFIG.4Efor a selected time period after controlling M1to the ion reflection mode (R) of operation. When the ion has passed through the charge detection cylinder CD a selected number of times or has oscillated back-and-forth between the ion mirrors M1, M2for a selected period of time, the processor16is operable, i.e., programmed, to control the voltage source V2to control the ion mirror M2to the ion transmission mode (T) of operation by establishing an ion transmission field within the region R2of the ion mirror M2, while maintaining the ion mirror M1in the ion reflection mode (R) of operation as illustrated inFIG.4A. The process then repeats for as many times as desired. The charge cylinder calibration or reset technique described with respect toFIGS.4A-4Emay alternatively or additionally be implemented with the ELIT14between charge detection events. It will be understood, however, that in such embodiments dimensions of the ELIT14, and the axial lengths of the ion mirrors M1, M2in particular, must be sized to allow for the activation of and subsequent generation of the free charges28by the charge generator GC, the deposition of the generated free charges28on the external surface of the charge detection cylinder CD and stabilization of the resulting target charge level CHTon the charge detection cylinder CD, and/or of charge inducement on the charge detection cylinder CD by a suitably established electric field, all between the time that a trapped ion traveling through the ELIT14leaves the charge detection cylinder CD and is reflected back into the charge detection cylinder by one of the ion mirrors M1, M2. Referring now toFIGS.5A-5F, simplified diagrams of the ELIT14ofFIG.1are shown demonstrating sequential control and operation of the ion mirrors M1, M2, as described above, and of the charge generator CG to calibrate or reset the charge detection cylinder CD between such charge detection events. Referring toFIG.5A, a single ion70is shown traveling through the ELIT14at a time T1in the direction of the arrow A from the region R1of the ion mirror M1toward the charge detection cylinder CD. As illustrated in the accompanying plot of charge CH on the charge detection cylinder CD vs. time, the detected charge signal80is at the charge reference CHREF. InFIG.5B, the ion70is shown at a subsequent time T2in which it has progressed along the direction A of travel and entered the charge detection cylinder CD. The detected charge signal80accordingly shows a step just prior to T2indicative of the detected charge induced on the charge detection cylinder CD by the ion70contained therein. At a further subsequent time T3, the ion70has progressed further along the direction A of travel and has approached the end of the charge detection cylinder CD, as illustrated inFIG.5C. The peak of the charge detection signal80is accordingly reaching its end at T3. At still a further subsequent time T4, the ion70still traveling in the direction A has just exited the charge detection cylinder CD and is poised to enter the region R2of the ion mirror M2as illustrated inFIG.5D. Upon detecting the attendant falling edge of the charge detection signal80at time T4, i.e., upon detection by the processor16of the absence of the charge detection signal that is produced by the charge preamplifier CP when an ion is passing through the charge detection cylinder CD and is inducing its charge on the charge detection cylinder, the processor16is operable to produce the control signal C at time T5to activate the charge generator CG as indicated by the rising edge of the control signal90. At a subsequent time T6, the charge generator CG is responsive to the control signal C to produce a selected number of free charges28, and such free charges28then travel through the field-free region36and into contact with the exterior surface of the charge detection cylinder CD to deposit the target number of free charges28thereon. Alternatively or additionally, the charge generator CG may be responsive to the control signal C to generate an electric field between the at least one charge outlet passage24and the charge detection cylinder CD which induces a corresponding charge, on the charge detection cylinder CD. At a subsequent time T7, the ion reflection electric field (R) established in the region R2of the ion mirror M2has trapped and reversed the direction of the ion70so that it is now traveling in the opposite direction B toward the entrance of the charge detection cylinder CD adjacent to the ion mirror M2as illustrated inFIG.5E. The processor16has deactivated the control signal C at T7as indicated by the falling edge of the control signal90. In response to deactivation of the control signal C, the charge generator CG has stopped generating free charges28, and the last of the generated charges28are shown inFIG.5Emoving toward the exterior surface of the charge detection cylinder CD. Alternatively or additionally, the charge generator CG may be responsive to the control signal C at T7to stop generating the electric field described above. Thereafter at time T8, the ion70traveling in the direction B has reentered the charge detection cylinder CD as indicated by the rising edge of the charge detection signal80at T8as illustrated inFIG.5F. Between T7and T8, the generated free charges28deposited on the charge detection cylinder CD settle and stabilize to result in the target charge level CHTon the charge detection cylinder CD which becomes the new charge reference for the charge detection signal80as also illustrated inFIG.5F. Alternatively or additionally, calibration or reset may be accomplished via charge induction as described above. A process identical to that illustrated inFIGS.5A-5Foccurs at the opposite end of the ELIT14and continues with each oscillation of the ion70within the ELIT14until the ion mirror M2is opened to allow the ion70to exit the aperture A1thereof. EXAMPLES The following examples are provided to illustrate three specific applications; one in which the charge generator CG is controlled to selectively produce free charges28as part of a charge injection process to deposit or impart a respective net charge on the charge detection cylinder CD, one in which the charge generator CG is controlled as part of a charge induction process to selectively induce a charge on the charge detection cylinder, and one in which the charge generator CG is controlled as part of a charge preamplifier calibration process to selectively induce a high frequency charge on the charge detection signal during normal operation of the ELIT in which mass and charge of a charged particle is measured thereby, to process the detected high frequency charges and to use the information provided thereby to compensate for any drift in gain of the charge preamplifier over time. It will be understood that such applications are provided only by way of example, and should not be understood to limit the concepts described herein in any way. The first example application is specifically targeted at embodiments in which the charge sensitive preamplifier does not include any feedback components, or at least in which the charge sensitive preamplifier does not include any feedback components operable to bleed or otherwise dissipate or remove charges that may build up or otherwise accumulate on the charge detection cylinder CD as charges are induced thereon by trapped ions passing therethrough. In such embodiments, charge that builds up or accumulates on the charge detection cylinder raises the base charge level at the input of the charge sensitive preamplifier, thus causing the output of the charge preamplifier to drift upwardly and, eventually, to the level of the supply voltage of the charge sensitive preamplifier. In such embodiments, the charge generator CG is configured to operate in charge injection mode, and the processor16is operable to control the charge generator CG to generate free charges28of appropriate polarity and quantity which, when deposited or imparted on the charge detection cylinder CD, counteracts the accumulated or built up charge thereby resetting the charge level of the charge detection cylinder CD and the input of the charge sensitive preamplifier to the reference charge level CHREFor other selectable charge level. The second example application is specifically targeted at embodiments in which the charge generator is configured to operate in charge induction mode to counteract or at least reduce charges induced on the charge detection cylinder CD by electric field transients produced when switching either or both of the ion mirrors M1, M2between ion transmission and ion reflection modes as described above. Generally, each time the voltage source V1and/or V2is controlled by the processor16to modify the respective voltages applied to the ion mirror M1and/or the ion mirror M2to switch from an ion transmission electric field TEF to an ion reflection electric field REF or vice versa, the switching from one electric field to the other creates an electric field transient which induces a corresponding transient charge on the charge detection cylinder CD. This transient charge, at least in some instances, saturates the output of the charge sensitive preamplifier for some period of time, and in other instances causes the charge sensitive preamplifier to produce one or more pulses detectable by the processor16. In either instance, such outputs produced by the charge sensitive preamplifier do not correspond to charges induced on the charge detection cylinder CD by a trapped ion passing therethrough, and following any such switching of either ion mirror M1, M2or simultaneously of both ion mirrors M1, M2charge detection data collection by the processor16is conventionally paused or delayed for a period of time to allow the transient charge induced on the charge detection cylinder CD to dissipate. In this regard, the processor16is operable in this second example to control the charge generator CG and/or the voltage source VCG to produce a counter-pulse each time one or both of the ion mirrors M1, M2is/are switched between ion transmission and reflection modes, wherein such counter-pulse induces a charge on the charge detection cylinder CD equal or approximately equal and opposite to the transient charge induced on the charge detection cylinder CD by the switching of the ion mirror(s) M1and/or M2so as to counteract or at least reduce the net transient charge induced on the charge detection cylinder by such switching of the ion mirror(s) M1and/or M2. Illustratively, the shape, duration and/or magnitude of the voltage counter-pulse produced by the voltage source VCG is controlled to create an electric field between the charge generator CG and the charge detection cylinder CD having a corresponding shape, duration and/or magnitude to induce a charge on the charge detection cylinder which is equal and opposite to the transient charge induced on the charge detection cylinder CD by the switching of the ion mirror(s) M1, M2. Such counter-pulsing by the voltage source VCG illustratively avoids saturating the charge preamplifier CP and, in any case, provides for the processing of charge detection data following switching of the ion mirror(s) M1and/or M2much sooner than in conventional ELIT and/or CDMS instruments. It will be understood that the transient charge induced on the charge detection cylinder CD by the switching of the ion mirror M1may be different from that induced by the switching of the ion mirror M2, either of which may be different from that induced when simultaneously switching both ion mirrors M1, M2, and that any such transient charges induced on the charge detection cylinder CD when switching either or both ion mirrors M1, M2from transmission mode to reflection mode may be different than when switching from reflection mode to transient mode. The processor16may thus be programmed in this example application to control the shape, duration and/or magnitude of the voltage counter-pulse produced by the voltage source VCG differently, depending upon how and which of the ion mirrors M1, M2(or both) are being switched, to selectively create an appropriate electric field between the charge generator CG and the charge detection cylinder CD which has a corresponding shape, duration and/or magnitude to induce a charge on the charge detection cylinder which is equal and opposite to any such transient charge being induced on the charge detection cylinder CD by such switching of the ion mirror(s) M1and/or M2. The third example application is specifically targeted at embodiments in which the charge sensitive preamplifier may be susceptible to drift in gain over time, e.g., due to one or any combination of, but not limited to, amplifier operating temperature, amplifier operating temperature gradients, and signal history. In such embodiments, the charge generator CG is illustratively controlled to selectively induce high frequency charges on the charge detection cylinder CD during normal operation of the ELIT14in which mass and charge of charged particles are measured thereby as described herein, to process the detected high frequency charges and to use information provided thereby to compensate for any drift in gain of the charge sensitive preamplifier CP over time. In this regard, the simplified flowchart ofFIG.7illustrates an example process200for controlling the charge generator voltage source VCG and/or the charge generator CG to continually induce high frequency charges on the charge detection cylinder CD and to use the corresponding information in the resulting charge detection signals CHD to compensate for gain drift in the charge sensitive preamplifier over time. The process200is illustratively stored in the memory18in the form of instructions executable by the processor16to control operation of the charge generator voltage source VCG and/or the charge generator CG and to process the charge detection signals CHD as just described. In this regard, the process200begins at step202where the processor16is operable to set a counter, j, equal to 1 or some other starting value. Thereafter at step204the processor16is operable to control the voltage source VCG and/or the charge generator CG to produce a high frequency voltage of suitable constant or stable magnitude to create a corresponding high-frequency electric field between the outlet26, e.g., in the form of an antenna or other suitable structure, of the charge generator CG and the charge detection cylinder CD which induces a corresponding high frequency charge on the charge detection cylinder CD. The term “high frequency,” as used in this embodiment, should be understood to mean a frequency that is at least high enough so that the resulting portion of the frequency domain charge detection signal CHD during normal operation of the ELIT14is distinguishable from the portion of CHD resulting from detection of charge induced by a charged particle, i.e., an ion, passing through the charge detection cylinder. In this regard, the “high frequency” should at least be higher than the highest oscillation frequency of any ion oscillating back and forth in the ELIT14as described above. The high frequency voltage produced by VCG and/or CG may take any shape, e.g., square, sinusoidal, triangular, etc., and have any desired duty cycle. In one example embodiment, which should not be considered limiting in any way, the high frequency voltage produced at the antenna26is a square wave which, in the frequency domain, includes only the fundamental frequency and odd harmonics. Following step204, the process200advances to step206where the processor16is operable to measure the charge, CI, induced on the charge detector CD by the high frequency signal produced at the antenna26by processing the corresponding charge detection signal CHD produced by the charge sensitive preamplifier CP. Thereafter at step208, the processor16is operable to convert the time-domain charge detection signal CHD to a frequency domain charge detection signal, CIF, e.g., using any conventional signal conversion technique such a discrete Fourier transform (DFT), fast Fourier transform (FFT) or other conventional technique. Thereafter at step210, the processor16is operable to determine the peak magnitude, PM, of the fundamental frequency of the charge detection signal CIF. Thereafter at step212, the processor16is operable to compare the counter value, j, to a target value, N. Generally, N will be the sample size of a data set containing multiple, sequentially measured values of PM, and will define the size of a moving average window used to track the drift of the charge sensitive preamplifier CP. In this regard, N may have any positive value. Generally, lower values of N will produce a more responsive but less smooth moving average, and higher values of N will conversely produce a less responsive but more smooth moving average. Typically, N will be selected based on the application. In one example application, which should not be considered limiting in any way, N is 100, although in other applications N may be less than 100, several hundred, 1000 or several thousand. If, at step212, the processor16determines that j is less than or equal to N, the process200advances to step214where the processor16is operable to add PM(j) to an N-sample data set stored in the memory18. Thereafter at step216, the processor is operable to increment the counter, j, and to then loop back to step206. If, at step212, the processor216instead determines that j is greater than N, the process200advances to step218where the processor16is operable to determine an average, AV, of the N-sample data set value PM1-N. In one embodiment, the processor16is illustratively operable at step218to compute AV as an algebraic average of PM1-N, although in alternate embodiments the processor16may be operable at step218to compute AV using one or more other conventional averaging techniques or processes. Steps202-218of the process200are illustratively executed prior to operation of the instrument10to measure a spectrum of masses and charges of ions generated from a sample as described herein. In this regard, the purpose of steps202-218is to build an N-sample data set of peak magnitude values PM and to establish a baseline gain or gain factor, AV, of the charge sensitive preamplifier CP prior to normal operation of the ELIT14to measure ion mass and charge as described herein. It will be understood, however, that in other embodiments steps202-218may be re-executed at any time, e.g., randomly, periodically or selectively, to reestablish the baseline gain or gain factor. Following step218, the processor16is illustratively operable to begin a CDMS analysis of a sample by the instrument10as described herein, e.g., by controlling the voltage sources V1and V2to measure masses and charges of ions generated from a sample with the ELIT14. Thereafter at step222, as such operation of the instrument10and ELIT14is taking place, and as the charge generator CG is continually controlled to induce the high frequency charge HFC on the charge detection cylinder CD, the processor16is operable, for each charge detection signal CHD produced by the charge sensitive preamplifier in response to a charge induced on the charge detection cylinder CD by a charged particle passing therethrough, to (a) determine PM, e.g., in accordance with steps206-210or other conventional process for determining PM, (b) add PM to the N-sample data set and delete the oldest PM value so as to advance the N-sample data set “window” by one data point, (c) determine a new average, NAV, of the now updated N-sample data set, e.g., in accordance with step218or other conventional averaging techniques, (d) determine a charge sensitive preamplifier gain calibration factor, GCF, as a function of AV and NAV, and (e) modify the portion of the charge detection signal CHD produced by the charge sensitive preamplifier in response to a charge induced on the charge detection cylinder CD by a charged particle passing therethrough as a function of GCF to compensate for any drift in gain of the charge sensitive preamplifier CP. It will be understood that any of several conventional techniques may be used by the processor16at step222(d) to determine GCF. In one embodiment, for example, GCF may be the ratio GCF=NAV/AV or GCF=AV/NAV. In other embodiments, AV may be normalized, e.g., to a value of 1 or some other value, and NAV may be similarly normalized as a function of the normalized AV to produce GCF in the form of a normalized multiplier. Other techniques will occur to those skilled in the art, and it will be understood that any such other techniques are intended to fall within the scope of this disclosure. In any case, the processor16is illustratively operable at step222(e) to modify the portion of the charge detection signal CHD produced by the charge sensitive preamplifier in response to a charge induced on the charge detection cylinder CD by a charged particle passing therethrough to compensate for any drift in gain of the charge sensitive preamplifier CP by multiplying the peak magnitude of this portion of the charge detection signal CH by GCF. Those skilled in the art will recognize other techniques for executing step222(e) to include in GCF other factors that may affect the gain of CP, to include one or more weighting values to boost or attenuate the gain of CP based on one or more factors, or the like. Referring now toFIG.8, an example plot of CHD vs. frequency is shown depicting an example of the charge detection signal CHD processed at step222(a) which includes charge peaks300corresponding to detection of charge induced on the charge detection cylinder CD of the ELIT14by a charged particle passing therethrough and additional charge peaks400corresponding to detection of the high frequency charge HFC simultaneously induced on the charge detection cylinder CD by the charge generator CG. As described herein, the frequency of the high-frequency charges induced on the charge detection cylinder CD by the antenna26of the charge generator CG is at least sufficiently higher than the oscillation frequency of the charged particle oscillating back and forth through the ELIT14to enable the two charge sources to be distinguishable from one another. The peak magnitude PM of the fundamental frequency of the induced high frequency charge HFC determined at step222(a) of the process200is also illustrated inFIG.8. Referring toFIG.9, an example plot of the peak magnitude PM of the fundamental frequency of the high frequency charge HFC induced on the charge detection cylinder CG by the charge generator vs. time410is shown which includes the baseline gain value AV computed at step218and which includes an example drift in the gain of the charge sensitive preamplifier CP over time during operation of the instrument10. It will be understood that whereasFIG.9depicts the gain drift as being linearly increasing over time, the gain drift may alternatively be non-linear or piecewise liner and/or may decrease over time or increase at times and decrease at others. In any case, the baseline gain value AV computed at step218occurs during the time window W1between times TO and T1, step220is executed at time T1, and the charge sensitive preamplifier gain drifts thereafter between T1and T3.FIG.9further depicts progressive movement of the N-sample time window repeatedly executed at step222(b), i.e., with each charge detection signal CHD resulting from a charge induced on the charge detection cylinder CD by a charged particle passing therethrough. One such example time window W2is shown extending from midway between TO and T1to T2, and another example time window W3is shown extending between times T2and T. Referring now toFIG.10, a plot is shown of an N-sample data set moving average (NAV)420over time of the peak magnitude signal410illustrated inFIG.9, as determined by the processor16at step222(c) of the process200. In the illustrated example, the moving average NAV smooths the peak magnitude signal410to a linearly increasing function from the baseline gain or gain factor AV. As described above, NAV and AV are illustratively used by the processor16at steps222(d) and222(e) to modify the portion of the charge detection signal CHD produced by the charge sensitive preamplifier in response to a charge induced on the charge detection cylinder CD by a charged particle passing therethrough to compensate for any drift in gain of the charge sensitive preamplifier CP by multiplying the peak magnitude of this portion of the charge detection signal CH by GCF. Referring now toFIG.6A, a simplified block diagram is shown of an embodiment of an ion separation instrument100which may include the ELIT14illustrated and described herein, and which may include the charge detection mass spectrometer (CDMS)10illustrated and described herein, and which may include any number of ion processing instruments which may form part of the ion source12upstream of the ELIT14and/or which may include any number of ion processing instruments which may be disposed downstream of the ELIT14to further process ion(s) exiting the ELIT14. In this regard, the ion source12is illustrated inFIG.6Aas including a number, Q, of ion source stages IS1—ISQwhich may be or form part of the ion source12. Alternatively or additionally, an ion processing instrument110is illustrated inFIG.6Aas being coupled to the ion outlet of the ELIT14, wherein the ion processing instrument110may include any number of ion processing stages OS1—OSR, where R may be any positive integer. Focusing on the ion source12, it will be understood that the source12of ions entering the ELIT14may be or include, in the form of one or more of the ion source stages IS1—ISQ, one or more conventional sources of ions as described above, and may further include one or more conventional instruments for separating ions according to one or more molecular characteristics (e.g., according to ion mass, ion mass-to-charge, ion mobility, ion retention time, or the like) and/or one or more conventional ion processing instruments for collecting and/or storing ions (e.g., one or more quadrupole, hexapole and/or other ion traps), for filtering ions (e.g., according to one or more molecular characteristics such as ion mass, ion mass-to-charge, ion mobility, ion retention time and the like), for fragmenting or otherwise dissociating ions, for normalizing or shifting ion charge states, and the like. It will be understood that the ion source12may include one or any combination, in any order, of any such conventional ion sources, ion separation instruments and/or ion processing instruments, and that some embodiments may include multiple adjacent or spaced-apart ones of any such conventional ion sources, ion separation instruments and/or ion processing instruments. In any implementation which includes one or more mass spectrometers, any one or more such mass spectrometers may be implemented in any of the forms described herein. Turning now to the ion processing instrument110, it will be understood that the instrument110may be or include, in the form of one or more of the ion processing stages OS1—OSR, one or more conventional instruments for separating ions according to one or more molecular characteristics (e.g., according to ion mass, ion mass-to-charge, ion mobility, ion retention time, or the like) and/or one or more conventional ion processing instruments for collecting and/or storing ions (e.g., one or more quadrupole, hexapole and/or other ion traps), for filtering ions (e.g., according to one or more molecular characteristics such as ion mass, ion mass-to-charge, ion mobility, ion retention time and the like), for fragmenting or otherwise dissociating ions, for normalizing or shifting ion charge states, and the like. It will be understood that the ion processing instrument110may include one or any combination, in any order, of any such conventional ion separation instruments and/or ion processing instruments, and that some embodiments may include multiple adjacent or spaced-apart ones of any such conventional ion separation instruments and/or ion processing instruments. In any implementation which includes one or more mass spectrometers, any one or more such mass spectrometers may be implemented in any of the forms described herein. As one specific implementation of the ion separation instrument100illustrated inFIG.6A, which should not be considered to be limiting in any way, the ion source12illustratively includes 3 stages, and the ion processing instrument110is omitted. In this example implementation, the ion source stage IS1is a conventional source of ions, e.g., electrospray, MALDI or the like, the ion source stage IS2is a conventional ion filter, e.g., a quadrupole or hexapole ion guide, and the ion source stage IS3is a mass spectrometer of any of the types described above. In this embodiment, the ion source stage IS2is controlled in a conventional manner to preselect ions having desired molecular characteristics for analysis by the downstream mass spectrometer, and to pass only such preselected ions to the mass spectrometer, wherein the ions analyzed by the ELIT14will be the preselected ions separated by the mass spectrometer according to mass-to-charge ratio. The preselected ions exiting the ion filter may, for example, be ions having a specified ion mass or mass-to-charge ratio, ions having ion masses or ion mass-to-charge ratios above and/or below a specified ion mass or ion mass-to-charge ratio, ions having ion masses or ion mass-to-charge ratios within a specified range of ion mass or ion mass-to-charge ratio, or the like. In some alternate implementations of this example, the ion source stage IS2may be the mass spectrometer and the ion source stage IS3may be the ion filter, and the ion filter may be otherwise operable as just described to preselect ions exiting the mass spectrometer which have desired molecular characteristics for analysis by the downstream ELIT14. In other alternate implementations of this example, the ion source stage IS2may be the ion filter, and the ion source stage IS3may include a mass spectrometer followed by another ion filter, wherein the ion filters each operate as just described. As another specific implementation of the ion separation instrument100illustrated inFIG.6A, which should not be considered to be limiting in any way, the ion source12illustratively includes 2 stages, and the ion processing instrument110is again omitted. In this example implementation, the ion source stage IS1is a conventional source of ions, e.g., electrospray, MALDI or the like, the ion source stage IS2is a conventional mass spectrometer of any of the types described above. This is the implementation described above with respect toFIG.1in which the ELIT14is operable to analyze ions exiting the mass spectrometer. As yet another specific implementation of the ion separation instrument100illustrated inFIG.6A, which should not be considered to be limiting in any way, the ion source12illustratively includes 2 stages, and the ion processing instrument110is omitted. In this example implementation, the ion source stage IS1is a conventional source of ions, e.g., electrospray, MALDI or the like, and the ion processing stage OS2is a conventional single or multiple-stage ion mobility spectrometer. In this implementation, the ion mobility spectrometer is operable to separate ions, generated by the ion source stage IS1, over time according to one or more functions of ion mobility, and the ELIT14is operable to analyze ions exiting the ion mobility spectrometer. In an alternate implementation of this example, the ion source12may include only a single stage IS1in the form of a conventional source of ions, and the ion processing instrument110may include a conventional single or multiple-stage ion mobility spectrometer as a sole stage OS1(or as stage OS1of a multiple-stage instrument110). In this alternate implementation, the ELIT14is operable to analyze ions generated by the ion source stage IS1, and the ion mobility spectrometer OS1is operable to separate ions exiting the ELIT14over time according to one or more functions of ion mobility. As another alternate implementation of this example, single or multiple-stage ion mobility spectrometers may follow both the ion source stage IS1and the ELIT14. In this alternate implementation, the ion mobility spectrometer following the ion source stage IS1is operable to separate ions, generated by the ion source stage IS1, over time according to one or more functions of ion mobility, the ELIT14is operable to analyze ions exiting the ion source stage ion mobility spectrometer, and the ion mobility spectrometer of the ion processing stage OS1following the ELIT14is operable to separate ions exiting the ELIT14over time according to one or more functions of ion mobility. In any implementations of the embodiment described in this paragraph, additional variants may include a mass spectrometer operatively positioned upstream and/or downstream of the single or multiple-stage ion mobility spectrometer in the ion source12and/or in the ion processing instrument110. As still another specific implementation of the ion separation instrument100illustrated inFIG.6A, which should not be considered to be limiting in any way, the ion source12illustratively includes 2 stages, and the ion processing instrument110is omitted. In this example implementation, the ion source stage IS1is a conventional liquid chromatograph, e.g., HPLC or the like configured to separate molecules in solution according to molecule retention time, and the ion source stage IS2is a conventional source of ions, e.g., electrospray or the like. In this implementation, the liquid chromatograph is operable to separate molecular components in solution, the ion source stage IS2is operable to generate ions from the solution flow exiting the liquid chromatograph, and the ELIT14is operable to analyze ions generated by the ion source stage IS2. In an alternate implementation of this example, the ion source stage IS1may instead be a conventional size-exclusion chromatograph (SEC) operable to separate molecules in solution by size. In another alternate implementation, the ion source stage IS1may include a conventional liquid chromatograph followed by a conventional SEC or vice versa. In this implementation, ions are generated by the ion source stage IS2from a twice separated solution; once according to molecule retention time followed by a second according to molecule size, or vice versa. In any implementations of the embodiment described in this paragraph, additional variants may include a mass spectrometer operatively positioned between the ion source stage IS2and the ELIT14. Referring now toFIG.6B, a simplified block diagram is shown of another embodiment of an ion separation instrument120which illustratively includes a multi-stage mass spectrometer instrument130and which also includes the charge detection mass spectrometer (CDMS)10illustrated and described herein implemented as a high-mass ion analysis component. In the illustrated embodiment, the multi-stage mass spectrometer instrument130includes an ion source (IS)12, as illustrated and described herein, followed by and coupled to a first conventional mass spectrometer (MS1)132, followed by and coupled to a conventional ion dissociation stage (ID)134operable to dissociate ions exiting the mass spectrometer132, e.g., by one or more of collision-induced dissociation (CID), surface-induced dissociation (SID), electron capture dissociation (ECD) and/or photo-induced dissociation (PID) or the like, followed by an coupled to a second conventional mass spectrometer (MS2)136, followed by a conventional ion detector (D)138, e.g., such as a microchannel plate detector or other conventional ion detector. The CDMS10is coupled in parallel with and to the ion dissociation stage134such that the CDMS10may selectively receive ions from the mass spectrometer136and/or from the ion dissociation stage132. MS/MS, e.g., using only the ion separation instrument130, is a well-established approach where precursor ions of a particular molecular weight are selected by the first mass spectrometer132(MS1) based on their m/z value. The mass selected precursor ions are fragmented, e.g., by collision-induced dissociation, surface-induced dissociation, electron capture dissociation or photo-induced dissociation, in the ion dissociation stage134. The fragment ions are then analyzed by the second mass spectrometer136(MS2). Only the m/z values of the precursor and fragment ions are measured in both MS1and MS2. For high mass ions, the charge states are not resolved and so it is not possible to select precursor ions with a specific molecular weight based on the m/z value alone. However, by coupling the instrument130to the CDMS10, it is possible to select a narrow range of m/z values and then use the CDMS10to determine the masses of the m/z selected precursor ions. The mass spectrometers132,136may be, for example, one or any combination of a magnetic sector mass spectrometer, time-of-flight mass spectrometer or quadrupole mass spectrometer, although in alternate embodiments other mass spectrometer types may be used. In any case, the m/z selected precursor ions with known masses exiting MS1can be fragmented in the ion dissociation stage134, and the resulting fragment ions can then be analyzed by MS2(where only the m/z ratio is measured) and/or by the CDMS instrument10(where the m/z ratio and charge are measured simultaneously). Low mass fragments, i.e., dissociated ions of precursor ions having mass values below a threshold mass value, e.g., 10,000 Da (or other mass value), can thus be analyzed by conventional MS, using MS2, while high mass fragments (where the charge states are not resolved), i.e., dissociated ions of precursor ions having mass values at or above the threshold mass value, can be analyzed by CDMS10. It will be understood that the dimensions of the various components of the ELIT14and the magnitudes of the electric fields established therein, as implemented in any of the systems10,100,120illustrated in the attached figures and described above, may illustratively be selected so as to establish a desired duty cycle of ion oscillation within the ELIT14, corresponding to a ratio of time spent by an ion in the charge detection cylinder CD and a total time spent by the ion traversing the combination of the ion mirrors M1, M2and the charge detection cylinder CD during one complete oscillation cycle. For example, a duty cycle of approximately 50% may be desirable for the purpose of reducing noise in fundamental frequency magnitude determinations resulting from harmonic frequency components of the measured signals. Details relating to such dimensional and operational considerations for achieving a desired duty cycle, e.g., such as 50%, are illustrated and described in U.S. Patent Application Ser. No. 62/616,860, filed Jan. 12, 2018, U.S. Patent Application Ser. No. 62/680,343, filed Jun. 4, 2018 and International Patent Application No. PCT/US2019/013251, filed Jan. 11, 2019, all entitled ELECTROSTATIC LINEAR ION TRAP DESIGN FOR CHARGE DETECTION MASS SPECTROMETRY, the disclosures of which are all expressly incorporated herein by reference in their entireties. It will be further understood that one or more charge detection optimization techniques may be used with the ELIT14in any of the systems10,100,120, e.g., for trigger trapping or other charge detection events. Examples of some such charge detection optimization techniques are illustrated and described in U.S. Patent Application Ser. No. 62/680,296, filed Jun. 4, 2018 and in co-pending International Patent Application No. PCT/US2019/013280, filed Jan. 11, 2019, both entitled APPARATUS AND METHOD FOR CAPTURING IONS IN AN ELECTROSTATIC LINEAR ION TRAP, the disclosures of which are both expressly incorporated herein by reference in their entireties. It will be still further understood that the charge detection cylinder calibration or reset apparatus and techniques illustrated in the attached figures and described herein may be used in each of two or more ELITs and/or in each of two or more ELIT regions in applications which include at least one ELIT array having two or more ELITs or having two or more ELIT regions. Examples of some such ELITs and/or ELIT arrays are illustrated and described in U.S. Patent Application Ser. No. 62/680,315, filed Jun. 4, 2018 and in co-pending International Patent Application No. PCT/US2019/013283, filed Jan. 11, 2019, both entitled ION TRAP ARRAY FOR HIGH THROUGHPUT CHARGE DETECTION MASS SPECTROMETRY, the disclosures of which are both expressly incorporated herein by reference in their entireties. It will be further understood that one or more ion source optimization apparatuses and/or techniques may be used with one or more embodiments of the ion source12as part of or in combination with any of the systems10,100,120illustrated in the attached figures and described herein, some examples of which are illustrated and described in U.S. Patent Application Ser. No. 62/680,223, filed Jun. 4, 2018 and entitled HYBRID ION FUNNEL-ION CARPET (FUNPET) ATMOSPHERIC PRESSURE INTERFACE FOR CHARGE DETECTION MASS SPECTROMETRY, and in co-pending International Patent Application No. PCT/US2019/013274, filed Jan. 11, 2019 and entitled INTERFACE FOR TRANSPORTING IONS FROM AN ATMOSPHERIC PRESSURE ENVIRONMENT TO A LOW PRESSURE ENVIRONMENT, the disclosures of which are both expressly incorporated herein by reference in their entireties. It will be still further understood that any of the systems10,100,120illustrated in the attached figures and described herein may be implemented in or as part of systems configured to operate in accordance with real-time analysis and/or real-time control techniques, some examples of which are illustrated and described in U.S. Patent Application Ser. No. 62/680,245, filed Jun. 4, 2018 and co-pending International Patent Application No. PCT/US2019/013277, filed Jan. 11, 2019, both entitled CHARGE DETECTION MASS SPECTROMETRY WITH REAL TIME ANALYSIS AND SIGNAL OPTIMIZATION, the disclosures of which are both expressly incorporated herein by reference in their entireties. It will be still further understood that in any of the systems10,100,120illustrated in the attached figures and described herein, the ELIT14may be replaced with an orbitrap, and that the charge detection cylinder calibration or reset apparatus and techniques illustrated in the attached figures and described herein may be used with such an orbitrap. An example of one such orbitrap is illustrated and described in U.S. Patent Application Ser. No. 62/769,952, filed Nov. 20, 2018 and in co-pending International Patent Application No. PCT/US2019/013278, filed Jan. 11, 2019, both entitled ORBITRAP FOR SINGLE PARTICLE MASS SPECTROMETRY, the disclosures of which are both expressly incorporated herein by reference in their entireties. It will be yet further understood that one or more ion inlet trajectory control apparatuses and/or techniques may be used with the ELIT14of any of the systems10,100,120illustrated in the attached figures and described herein to provide for simultaneous measurements of multiple individual ions within the ELIT14. Examples of some such ion inlet trajectory control apparatuses and/or techniques are illustrated and described in U.S. Patent Application Ser. No. 62/774,703, filed Dec. 3, 2018 and in co-pending International Patent Application No. PCT/US2019/013285, filed Jan. 11, 2019, both entitled APPARATUS AND METHOD FOR SIMULTANEOUSLY ANALYZING MULTIPLE IONS WITH AN ELECTROSTATIC LINEAR ION TRAP, the disclosures of which are both expressly incorporated herein by reference in their entireties. While this disclosure has been illustrated and described in detail in the foregoing drawings and description, the same is to be considered as illustrative and not restrictive in character, it being understood that only illustrative embodiments thereof have been shown and described and that all changes and modifications that come within the spirit of this disclosure are desired to be protected. For example, it will be understood that the ELIT14illustrated in the attached figures and described herein is provided only by way of example, and that the concepts, structures and techniques described above may be implemented directly in ELITs of various alternate designs. Any such alternate ELIT design may, for example, include any one or combination of two or more ELIT regions, more, fewer and/or differently-shaped ion mirror electrodes, more or fewer voltage sources, more or fewer DC or time-varying signals produced by one or more of the voltage sources, one or more ion mirrors defining additional electric field regions, or the like. As another example, while the concepts, structures and/or techniques of this disclosure have been described as being implemented in an electrostatic linear ion trap (ELIT), it will be understood that such concepts, structures and/or techniques are not intended to be limited to ELITs or variants thereof, but rather are intended to be applicable to any conventional charge detector or charge detection apparatus. Accordingly, any conventional charge detector or charge detection apparatus implementing the concepts, structures and/or techniques illustrated in the attached figures and described herein are intended to fall within the scope of this disclosure. | 96,425 |
11862449 | DETAILED DESCRIPTION OF THE INVENTION A method for sampling a sample liquid includes the step of providing the sample liquid through a sample fluid conduit. The sample fluid conduit comprises a membrane comprising pores. The membrane prevents the passage of the sample liquid through the pores at a first pressure of the sample liquid in the sample fluid conduit. A surface sampling capture probe is provided having a distal end. The capture probe includes a solvent supply conduit with an open end and a solvent exhaust conduit with an open end. Solvent composition flows at the distal end of the capture probe from the open end of the solvent supply conduit to the open end of the exhaust conduit, and establishes a liquid junction with the membrane. A second pressure is established within the liquid junction at the membrane. The second pressure is lower than the first pressure, thereby drawing sample liquid through the pores of the membrane by the second pressure at the liquid junction. The extracted sample liquid is combined with the flowing solvent composition of the capture probe and flows into the open end of the exhaust conduit of the capture probe. A system for sampling a liquid includes a sample fluid conduit including a membrane having pores. The membrane barrier prevents the passage of the sample liquid through the pores at a first pressure of the sample liquid in the sample fluid conduit. A surface sampling capture probe has a distal end. The capture probe includes a solvent supply conduit with an open end and a solvent exhaust conduit with an open end. A solvent composition flowing at the distal end of the capture probe from the open end of the solvent supply conduit to the open end of the exhaust conduit establishes a liquid junction with the membrane and establishes a second pressure within the liquid junction at the membrane. The second pressure is lower than the first pressure. Sample liquid will be drawn through the pores of the membrane by the second pressure at the liquid junction and the extracted sample liquid combines with the flowing solvent composition of the capture probe and flow into the open end of the exhaust conduit of the capture probe. A method for sampling a liquid and for performing chemical analysis on a liquid are also disclosed. The method can further include the step of conducting mass spectrometry on the extracted sample liquid. The system can also be used to withdraw sample from a flowing sample liquid for other chemical analysis methods and devices. The method can include the step of collecting the solvent composition and sample liquid from the exhaust conduit of the capture probe in a storage container for later analysis by any suitable chemical analysis method or device. The system can include a storage container for collecting the solvent composition and sample liquid from the exhaust conduit of the capture probe. The storage container can have differing designs and sizes. The method can utilize a number of different solvent compositions. The solvent composition when in a liquid junction with the membrane has a junction fluid diameter, and the surface tension of the solvent composition and selection of the membrane material should prevent expansion of the junction fluid diameter beyond two times the diameter of the distal end of the capture probe. The surface tension of the solvent composition should also not permit the solvent composition to flow through the pores of the membrane at the second pressure. Suitable solvents include methanol or acetonitrile mixed with water, formic acid, ammonium acetate, ammonium hydroxide, acetic acid, ammonium formate, or isopropyl alcohol. The solvent composition can include a component that is a solvent for an analyte of interest in the sample liquid, for example, methanol or acetonitrile. The solvent composition can include a solvent liquid and a high surface tension component having a surface tension higher than that of the solvent liquid for example, water or isopropyl alcohol. The solvent composition can include an acid or base component for ionizing an analyte of interest in the sample fluid for example, formic acid, ammonium acetate, ammonium hydroxide, acetic acid or ammonium formate. The solvent composition can include a reactant for an analyte of interest in the sample liquid to produce an analyte reaction product which analyte reaction product provides increased sensitivity for mass spectrometry relative to the unreacted analyte of interest for example, the molecular tagging of cysteines with benzoquinones. The system can further include a chemical analysis device. The chemical analysis device can include a mass spectrometer. Other chemical analysis methods and devices that are suitable for use with the invention include spectroscopic detection (fluorescence, Raman, etc.), conductivity measurement, or pH detection. The capture probe can have different designs. In one aspect, the capture probe comprises an outer probe housing having a coaxial inner solvent exhaust conduit, and an annular solvent supply conduit between the solvent exhaust conduit and the outer prove housing. The surface tension of the solvent composition does not permit the solvent composition to flow through the pores of the membrane at the second pressure. It is possible to operate the capture probe at a third pressure, less than the pressure of the sample fluid but not low enough to draw significant amounts of the sample fluid through the pores. The construction of the membrane can vary. The membrane can be made from polycarbonate (PCT), polyester (PET), polytetrafluoroethylene (PETE), polydimethylsiloxane (PDMS), polyether ether ketone (PEEK), nylon, silver or glass Fiber. The membrane pores can have differing dimensions, for example from 0.01 to 10 μm. The thickness of the membrane can vary, for example from 0.1 to 1000 μm. The membrane can have track-etched or tortuous pores and can be coated with polymer films and can have 1 to 108pores/cm2. The sample fluid conduit can be provided in a sample fluid conduit housing. The housing can have differing designs and sizes. The sample fluid conduit can be provided in a microfluidic device. The fluid does not have to flow constantly, for example, fluid can be flowed into the cell, halted and then sampled. There is shown inFIGS.1-4a system10for porous membrane enabled mass spectrometry characterization of microfluidic devices. The system10includes a capture probe14and a suction nebulizer18. The capture probe14can include an outer tube22with distal open end23and an inner tube26with distal open end27arranged in substantially coaxial arrangement. Other capture probe designs are possible. The capture probe14receives solvent from a suitable solvent source30. Solvent received from source30travels through the capture probe14in annular solvent supply conduit38formed between the outer tube22and the inner tube26. The inner tube26defines an exhaust conduit42and has a distal end27. The suction nebulizer18applies suction as by a suitable pump or in the embodiment shown a supply of nebulizer gas46which is introduced into nebulizer passageway48through inlet50and flows past open end54of exhaust passageway44. The flow of nebulizer gas contacts solvent at the open end54to create a nebulizer spray56of the sample solvent into MS inlet58. The flow of nebulizer gas creates a low pressure at the open end54and thereby within the exhaust conduit44and within the exhaust conduit42of the capture probe14it also creates a low-pressure zone in the exhaust conduit42within the inner tube26. Control of the suction nebulizer18can be affected to control the flow of solvent through the exhaust conduit26. Control of the solvent source can be affected through a suitable valve32through an inlet opening34. The supply of solvent and the exhaust of solvent can be controlled by a suitable processor. The balance of solvent flows in the solvent supply conduit38and the solvent exhaust conduit42creates a liquid microjunction106. A microfluidic device60includes a wall64and a porous membrane68defining a flow channel76. The porous membrane68includes pores72. A sample solution75containing analyte77is provided in the flow channel76at pressure P1. The sample solution can enter the flow channel76at any suitable fluid inlet80and exit at a suitable fluid exit84. The sample fluid can flow in the flow channel76as indicated by arrow90. The size of the pores72and the surface tension of the sample fluid is such that the sample fluid may enter the pores72as shown by meniscus78, but does not pass through the pores72. The sample solution76is contained by the microfluidic device60at pressure P1when the pressure outside the microfluidic device60is that pressure P0. P0can be any outside pressure, such as atmospheric pressure. In operation, as shown inFIG.3, the capture probe14is brought into proximity to the microfluidic device60and solvent is caused to flow through the annular solvent supply conduit38solution as shown by arrows98. The section nebulizer18is operated to withdraw solvent solution through the exhaust conduit42as indicated by arrow102. This will cause the formation of a liquid microjunction106between distal end23of the capture probe14and the porous membrane68. The balance between solvent supply and withdrawal can be controlled to create a pressure P2within the liquid microjunction106. P2is less than P0and less than P1. At P2the pressure differential between P2and P1is sufficient to overcome the surface tension of the solvent solution75within the pores72such that some sample fluid110will be drawn through the pores72and into the exhaust conduit42. The pressure within the liquid microjunction can be controlled by control of the solvent supply rate and the solvent exhaust rate.FIG.4illustrates the condition where the supply and exhaust solvent flows are controlled to provide a liquid microjunction114with a pressure P3within the microjunction114. The pressure P3is less that P1, but greater than P2. The pressure differential between P1and P3is insufficient to draw sample solution75through the pores72, and is insufficient to drive solvent from the capture probe14into the flow channel76. P3should not be so great that solvent is forced through the pores72and into the flow channel76microfluidic device60as this could contaminate or dilute the sample solution75in the flow channel76. The system can be controlled on demand to change the solvent flow rates to a pressure, for example P2, that will withdraw sample fluid from the membrane76. The invention provides for the on-line/in situ chemical analysis of microfluidic flow cells through the combination of a microfluidic device with a porous polymer membrane wall and sampling with liquid microjunction-surface sampling capture probe mass spectrometry (MS). This enables online chemical characterization of constituents within the device by MS. This combination provides a system and method to continuously sample and chemically characterize small volumes of liquid directly from a microfluidic device at any point along a 2D surface in near real-time and without greatly negatively altering the state of the microfluidic system. The invention can also be used for the chemical analysis of living systems in microfluidic devices continuously without destruction or modification to the biological system. The microfluidic device is fabricated with a porous membrane surface on one side of the device, or on several sides. The capture probe MS sampling device can form a liquid microjunction between the membrane surface which extracts nL-to-uL volumes from the microfluidic device, through the membrane and into the capture probe. The liquid extracts can then be chemically characterized by mass spectrometry, or another chemical analysis technology. The porous membrane of the microfluidic device also allows selective liquid extraction at any point along the membrane surface. The use of a porous membrane microfluidic device in a configuration that allows for chemical analysis at any point on the surface of the device, without destroying the function and lifetime of the device. Chemical analysis of dynamic fluid systems often precludes the use of mass spectrometry as it is destructive. The invention provides a way to measure the chemistry within a microfluidic flow cell at any point along a 2D surface using mass spectrometry. Uses include the on-line measure of chemical dynamics within microfluidic devices with mass spectrometric detection. Chemical mapping of over the entire surface of a microfluidic device is possible to show chemical differences occurring in different regions of the device. The invention permits repeated chemical measure at single or multiple points anywhere on the microfluidic device providing temporally resolved chemical information. Mass spectrometric chemical detection within microfluidic devices can be performed without dismantling the device or negatively influencing its function. The capture probe that was used also included a vacuum suction capillary. The capture probe was made using three capillaries co-axially aligned. The outer capillary was stainless steel (˜1.067 mm-i.d.ט0.686 mm-o.d.×3.5 cm long) connected to a PEEK T-manifold (IDEX Health & Science LLC, Oak Harbor, WA, USA). One of the ports connected to the sampling end of the capture probe and the other connected to house vacuum to provide suction through this tube. This served to prevent any pooling of solvent on the sample surface when solvent delivery exceeded aspiration at the initialization of the capture probe device, but it did not influence normal capture probe operation. The middle capillary was stainless steel (˜0.406 mm-i.d.ט0.508 mm-o.d.×7.0 cm long) connected to the mass spectrometer ion source electrical ground. A stainless-steel capillary (0.178 μm-i.d.×0.330 μm-o.d.ט30 cm long) was used as the inner tube and acted as the nebulizing capillary of an atmospheric pressure chemical ionization (APCI) ion source of a Q-Exactive HF orbitrap mass spectrometer (ThermoFisher Scientific, Waltham, MA, USA). The middle and inner capillaries were secured to another PEEK T-manifold (IDEX Health & Science LLC, Oak Harbor, WA, USA). Solvent was delivered by a high-performance liquid chromatography (HPLC) pump (model 1100, Agilent Technologies, Santa Clara, CA, USA) into the annulus region of the capture probe. Nebulizing gas (nitrogen) in the ion source was used to control the solvent aspiration rate through the probe. This was set to slightly exceed the solvent delivery rate to the capture probe from the HPLC. A stable liquid vortex was maintained at the surface of the probe. Upon contact of the capture probe with a surface, a liquid microjunction was formed between the surface and the capture probe. The capture probe was connected to a XYZ stage (MS-2000, Applied Scientific Instrumentation, Eugene, OR, USA) which was used to control the movement of the probe. Control of the stage was done using custom control software developed in house using Delphi 3 computer language (Borland Software Corp., Scotts Valley, CA). Mass spectra were acquired continuously using a sheath gas flow=80, auxiliary gas flow=40, capillary temperature=250° C., source temperature=400° C., and APCI current=5 μA. Specific scan settings were optimized for each experiment. Caffeine and d3-caffeine were monitored simultaneously using all ion fragmentation (AIF) scans of m/z 190-200 with a scan window of m/z 100-200 (normalized collision energy (NCE)=50 eV, resolution=45,000, automatic gain control (AGC)=1e6, injection time=100 ms). A common fragment ion to caffeine and d3-caffeine (m/z 138) was used to corroborate experiments. The invention permits the efficient extraction of small amounts of fluid from a microfluidic flow cell with a porous membrane conducted in situ without significantly affecting its operation. To validate the ability to extract fluid through the porous membrane wall, a single-channel (500 μm wide and 160 μm deep) microfluidic flow cell was designed. The channel was sealed using a 0.4 μm pore size track etched, hydrophobic PETE membrane. The flow cell was fed with a constant 10 μL/min flow of 2.55 μM caffeine in water. Based on the pore size of the membrane and the surface tension of water, the 2.55 μM caffeine solution flowed through the channel rather than out of the porous membrane. The solvent of the capture probe was optimized to achieve efficient analyte extraction without negatively impacting the flow cell. Typically, solvents such as acetonitrile and methanol are used in capture probe operation, but these solvents have sufficiently low surface tension that they can wet the entire membrane surface upon contact with the capture probe. A solvent composition of 75/25/0.1 ACN/H2O/FA (v/v/v) was found to enable liquid microjunction formation without wetting of the PETE membrane beyond the area of the capture probe. To demonstrate the continuous fluid extraction through the porous membrane, the capture probe was positioned ˜20-40 μm above the membrane surface in order to form a liquid microjunction between the membrane surface and the capture probe. Liquid extraction through the PETE membrane was monitored by mass spectrometric detection of caffeine that was present in the solvent flowing through the flow cell. To quantitate the amount of caffeine detected, d3-caffeine was added to the capture probe extraction solvent to act as an internal standard. The capture probe extraction solvent was made up by mixing 75/25/0.1 ACN/H2O/FA at 150 μL/min with 44 μM d3-caffeine in water (final concentration of 0.29 μM) at 1 μL/min. FIG.5shows extracted ion chronograms of m/z 195.1 (black) and m/z 198.1 (grey) corresponding to caffeine and d3-caffeine, respectively.FIG.5shows continuous fluid extraction through the PETE membrane by the capture probe. A liquid microjunction was formed at t=1 min, which immediately resulted in a mass spectrometric signal of caffeine (˜6 s elution time). The capture probe remained in this position for 14 min before it was lifted away from the surface, breaking the liquid microjunction. This is reflected by the sharp decrease in caffeine signal at t=15 min. Continuous extraction of caffeine was observed over the 14 min time period where the liquid microjunction was in place. Hence, this data shows continuous extraction of small volumes of liquid from the flow cell through the porous membrane and into the capture probe. D3-caffeine signal (grey line) was approximately constant over the duration indicating no matrix effects were observed and that no loss of capture probe solvent, wicking of solvent into the flow cell, was occurring. One concern of using capture probe to extract liquid through the porous membrane wall is the transport of capture probe solvent into the flow cell itself. If this occurs, then the act of sampling by a liquid microjunction may negatively alter or dilute the chemistry occurring in the flow cell. Additionally, for biological systems, exposure to relatively harsh extraction solvents may negatively impact the system. To determine if and to what extent capture probe solvent enters the flow cell through the porous membrane, 100% water without any analyte was infused through the flow cell and outflows were collected under varying flow rates (5-15 μL/min) with and without liquid microjunction formation over the PETE membrane. Since 0.29 μM d3-caffeine is present only in the capture probe solvent, any d3-caffeine signal in collected outflows is from transfer of capture probe solvent into the flow cell. D3-caffeine signals were statistically the same (99% confidence) without capture probe sampling and with capture probe sampling using 5, 10 and 15 μL/min water flow rate in the flow cell. This result indicates that capture probe solvent had not entered the flow cell. Based on the limit of detection of the mass spectrometer in this configuration for d3-caffeine (˜1 nM), this data shows that <0.4% of capture probe solvent had been introduced into the flow cell. This data is also corroborated by the constant d3-caffeine signals observed inFIG.5. If capture probe solvent entered the flow cell there would be reduced d3-caffeine signal, which was not observed. Control of the extent of liquid extraction can be tuned for each application to minimally perturb the system within the device. Liquid extraction through the porous membrane is likely influenced by several factors including porous membrane pore size, liquid flow rate in the flow cell and capture probe sampling parameters, such as extraction solvent, flow rate, capture probe-to-surface distance, and capture probe capillary dimensions. Briefly, the inner capillary retraction length and capture probe-to-surface distance were found to be critical factors that govern surface sampling. Here, inner capillary retraction lengths were fixed at ˜500 μm, but the distance of the capture probe from the membrane surface could vary as the capture probe is moved. The effect of capture probe-to-surface distance, the thickness of the liquid microjunction, on fluid extraction efficiency is shown inFIG.6. Extraction efficiencies were determined by measuring the mass of flow cell outflows and by quantitation of caffeine by capture probe-MS. Fluid extraction efficiency through the porous membrane as a function of capture probe-to-surface distance is shown inFIG.6for flow cell flow rate=10 μL/min, capture probe flow rate=151 μL/min, and membrane pore size=0.4 μm. Fluid extraction efficiency is the fraction of flow cell flow rate pulled into the capture probe, and was determined directly by weighing the mass of flow cell outflows with and without capture probe sampling and by quantitation of a known concentration of analyte present in the flow cell by capture probe-MS. In the latter method the amount mass spectrometric signal of caffeine was quantitated and used to determine how much flow cell fluid became integrated into the capture probe. In the flow cell 10 μL/min of 2.55 μM caffeine in water was continuously flowed and a membrane with a pore size of 0.4 μm was used to seal the device. The capture probe used a flow rate of 151 μL/min 0.29 μM d3-caffeine in 75/25/0.1 (v/v/v) ACN/H2O/FA. Flow cell outflows for each capture probe-to-surface distance were collected into 1 mL Eppendorf tubes for 3 min and weighed. Blanks (no capture probe sampling) were used as a reference for normal flow cell outflow masses. In the same experiment the concentration of caffeine sampled by capture probe was calculated by measure of caffeine and d3-caffeine by capture probe-MS. Caffeine signal was normalized to the internal standard and transformed into a quantitative concentration using an externally measured calibration curve. Three replicate experiments were conducted for each condition. Given the flow rate through the flow cell is known, extracted flow rates were converted relative to the fraction of flow cell flow rate extracted (FIG.6) to facilitate comparisons between conditions.FIG.6shows that the capture probe-to-surface distance inversely correlates with fluid extraction efficiency, with ˜30% of flow cell fluid sampled by the capture probe when position directly over the membrane surface (capture probe-to-surface distance=0 μm). Above 60 μm the liquid microjunction could no longer be reliably maintained. Using the MS quantitation methodology outlined for the experiments inFIG.6, the capture probe flow rate was varied from 75-175 μL/min using 0.29 μM d3-caffeine in 75/25/0.1 (v/v/v) ACN/H2O/FA while keeping the flow cell flow rate, capture probe-to-surface distance and MS ion source aspiration conditions constant.FIG.7shows a capture probe flow rate with flow cell flow rate=10 μL/min, capture probe-to-surface distance=20 μm, and membrane pore size=0.4 μm. As the capture probe solvent flow rate increased the fluid extraction efficiency decreased. Above 175 μL/min the capture probe solvent flow rate becomes greater than the self-aspiration rate of the MS ion source, resulting in the capture probe overflowing with solvent and no fluid being extracted from the flow cell. As the capture probe solvent flow rate is lowered below 175 μL/min, there was greater extraction efficiency through the porous membrane. An improvement of liquid extraction by ˜10 fold was achieved by decreasing capture probe flow rate from 175 to 75 μL/min (3% to 20%, respectively). Increased extraction efficiency with decreasing capture probe flow rate is explained by considering the effective negative pressure exerted by the capture probe. A flow rate of 151 μL/min was used for the remainder of these experiments. Fluid extraction efficiency was determined using membrane pore sizes of 0.1, 0.2, 0.4 and 5 μm in diameter (FIG.8) while keeping capture probe flow rate, capture probe-to-surface distance and MS ion source aspiration conditions constant.FIG.8shows data for flow cell flow rate=10 μL/min, capture probe flow rate=150 μL/min, and capture probe-to-surface distance=20 μm. At 5 μm pore diameter 92% of the flow cell fluid is extracted by the capture probe, while for the 0.1 μm pore size membrane this dropped to 1% (0.1 μL/min). Smaller pore size requires greater vacuum pressure to extract the same amount of liquid through the membrane. FIG.9shows the extracted flow rate dependence on the fluid flow rate within the flow cell. The increasing flow cell flow rate is inversely related to the amount of extracted flow. Extraction efficiencies were determined by measuring the mass of flow cell outflows and by quantitation of caffeine by capture probe-MS. To demonstrate reproducible and repeated sampling across the porous membrane surface of the channel the capture probe was continuously rastered forward and backward 27 times in 15 min across the same location of the channel at a rate of 0.1 mm/s (FIG.10). Effectively, these scans demonstrate periodic monitoring of the fluid channel over several minutes. A 2.55 μM caffeine solution was continuously flowed through the flow cell at a rate of 10 μL/min. Transects across the channel result in a Gaussian-like signal profile that remained consistent for all 27 replicate scans. The use of a porous membrane enables sampling and chemical imaging of dynamic microfluidic devices. As a proof-of-concept a microfluidic device with a two-input Y-tee channel was fabricated and sealed using a 0.4 μm porous PETE membrane (FIG.11).FIG.11shows optical image of the microfluidic flow cell with a Y-shaped channel. The dashed area was selected for MS imaging inFIG.12. Input channels were 0.75 mm wide and 0.165 mm deep, and the combined channel was 1 mm wide and 0.165 mm deep. To validate the imaging resolution and accuracy of the chemical imaging capability, input channel #1 was fed with 15 μL/min of 2.55 μM propranolol (a.q.) and input channel #2 was fed with 15 μL/min of 2.55 μM caffeine (a.q.). The two inputs and the central channel were then imaged using the capture probe-MS system (FIG.12).FIG.12shows extracted ion chronograms of m/z 195.1 (black) and m/z 260.1 (light grey) corresponding to caffeine and proporanolol, respectively. To image the surface the capture probe was rastered across the flow cell at 0.25 mm/s, with 0.25 mm spacing between lanes for 41 lanes. The image comprised a 10×10 mm surface area (41×41 px image). The resulting capture probe MS image aligned well with the flow cell design. Since the membrane surface is relatively flat, a constant capture probe-to-surface distance could be maintained throughout the imaging experiment. As expected with this type of device, the two solutions fed into the individual input channels remain separate even within the central (combined) channel. Since input flow rates are relatively high, the velocity of fluid in the mixed channel is ˜3 mm/s (30 μL/min, 1×0.165 mm rectangular channel). Thus, there is very little time in the imaged area for the two components to mix (<2 sec). This is observed clearly in the MS image where the two components can be seen separated in the central channel. These images demonstrate the ability of capture probe to identify chemically heterogenous regions within a dynamic system anywhere along the porous membrane surface. Note, the same device can be imaged repeatedly to monitor for changes over time. There is shown inFIGS.13A-13Han embodiment of the invention in which a single conduit124serves as one or both of the solvent supply conduit and the solvent/sample exhaust conduit. Positive pressure is applied to solvent within the conduit124to cause solvent to be expelled from the open end126of the conduit124and form a liquid microjunction with the membrane122. This is followed by subsequent withdrawal of a sample from the surface such as by applying a reduced or negative pressure within the conduit124. This will create a low pressure within the liquid microjunction that is less than the pressure of the sample liquid on the other side of the membrane122. For example, inFIG.13A, the collection probe124is positioned above the surface spot to be analyzed. InFIGS.13B through13E, the liquid solvent conducted upon the surface begins to build up upon the surface. InFIGS.13F through13H, the pressure within the conduit124is reduced so that an analyte-rich solution is drawn through the membrane122, and into the conduit124or a separate exhaust conduit. It can be seen from the view ofFIGS.13B through13E, the area or spot over which the sample is covered by the liquid solution increases in size (i.e. diameter) as the liquid solution accumulates upon the surface. Such an occurrence can be advantageous in that the solution which is subsequently withdrawn from the surface for analysis contains sample amounts from the relatively broad area covered by the liquid agent. The invention as shown in the drawings and described in detail herein disclose arrangements of elements of particular construction and configuration for illustrating preferred embodiments of structure and method of operation of the present invention. It is to be understood however, that elements of different construction and configuration and other arrangements thereof, other than those illustrated and described may be employed in accordance with the spirit of the invention, and such changes, alternations and modifications as would occur to those skilled in the art are considered to be within the scope of this invention as broadly defined in the appended claims. In addition, it is to be understood that the phraseology and terminology employed herein are for the purpose of description and should not be regarded as limiting. | 30,732 |
11862450 | DETAILED DESCRIPTION OF PREFERRED EMBODIMENTS As mentioned above, it is an object of the present invention to provide an ion optical arrangement comprising a collision/reaction cell, which ion optical arrangement is suitable for use in a mass spectrometer, in which the collision/reaction gas can be used only when necessary, while avoiding the relatively complicated dual path ion optics arrangement described in British patent application GB 2 535 754. It is another object of the invention to reduce the noding effect in an ion optical arrangement, such as a collision/reaction cell. In accordance with the invention, the first object may be achieved by switching the operation modes of the ion optical arrangement between:A. a first operation mode including a pressurized collision cell, andB. a second operation mode along the same optical axis with an evacuated collision cell. This switching between operation modes can be achieved without exchanging any components, that is, by using the components present in the ion optical arrangement. The first operation mode uses a radio frequency (RF) electric focusing field while the second operation mode uses a static (DC) electric focusing field. The first mode of operation can be a low energy RF operation mode while the second mode of operation can be a high energy static operation mode. In GB 2 546 060, which is herewith incorporated by reference in this document, the concept of a pre-mass filtered collision cell interfaced to a multi-collector mass spectrometer is disclosed. An RF quadrupole pre-mass filter is used which also introduces noding effects similar to the RF collision cell. In the collision cell the ion beam trajectories are altered by the collisions and the strong phase correlation to the oscillating RF field of the ions traveling through the quadrupole is disturbed by the collisions and thus leads to less mass dependent transmission effects. The small dependence of the trajectories depending on the mass is known as “noding”. It is a result of the spatial oscillations of the ions inside a multipole. Depending on the number of oscillations of the ions, they leave the cell with an angle/position vector that is mass dependent. This effect can be amplified by the tuning parameters such as the potentials of the entry and exit lenses which determine the input and exit parameters of the ion beam entering and exiting the collision cell. The DC bias potential of the multipole rods also determines the travel velocity of the ions through the collision cell and has an influence on the noding. By using higher order multipoles, from quadrupoles (4 poles) to hexapoles (6 poles) or octupoles (8 rods or poles), higher order oscillations are added to the ion trajectories which make the mass dependent differences of the trajectories less pronounced and which at the same time increase the acceptance input aperture of the collision cell. However, this beneficial effect is limited. The pressurization of the collision cell by introducing a collision gas (e.g. helium) flow in the order of several ml/min results in multiple collisions of the ions with the collision gas, which in turn results in scattering and random movements of the ions. These scattering events further reduce the phase correlation of the ion beam trajectories to the oscillating RF field and thus reduce the noding effect. The more collisions the ions undergo the smaller the noding effect is. Especially for heavier ions multiple collisions result into both a reduction of the kinetic energy and a reduction of the energy spread of the ions, which improves the focusing conditions and which is known as collisional focusing. The momentum transfer per collision becomes more efficient the more the difference in mass between both collision partners is reduced and might even stop the movement of the ions. For lighter masses approaching the low mass range of helium (He), the overall transmission efficiency through the pressurized collision cell is significantly reduced. This can partly be compensated by adding an axial electrical field gradient to the cell potential that actively drags ions from the entry to the exit aperture and therefore allows for an increased number of collisions as well as for higher transmission for lighter ions. The noding effect can be reduced by using higher order multipoles with high gas pressures and axial fields, but it cannot be eliminated completely. Accurate and precise isotope ratio measurements using collision cells requires the availability of a calibrated standard and extensive calibration procedures. Tuning parameters need to be controlled carefully. The invention provides a collision cell that can be switched to a static high energy DC transfer lens to completely avoid noding effects. Collision cells usually require high gas pressure inside the collision cell volume to induce sufficient collisions and chemical reactions (when a reaction gas is used). Therefore, the pumping apertures at the entrance and the exit are usually rather small, in the order of 1-3 mm diameter. For an efficient high energy transport through the collision cell arrangement, an improved pumping mechanism has to be established. The present invention additionally provides a solution to the noding problem by providing a collision/reaction cell that varies the number of oscillations the ions undergo in the RF field. That can be done by:1. a variation of the RF frequency, and/or2. a variation of the ions' energy/velocity in axial direction, and/or3. any other lens element that influences the ion velocity. The variation of the axial energy can be achieved by, for example, superimposing an oscillation on the rod bias voltage (DC potential of the rods that defines the energy the ions have in the multipole) and/or by applying an oscillating voltage to the vanes (which may also be referred to as drag electrodes in some embodiments, seeFIGS.4A &4B). The amplitude of the applied variation is preferably such that the number of oscillations which the ions undergo changes by at least 1 over the length of the collision cell. As mentioned above, the number of oscillations n is given by the frequency and the velocity of an ion: n=f·l·m2E withf=frequency,l=length of multipole,m=ion mass, andE=ion energy. In an embodiment, the minimum number of oscillations is in the order of 10 (f=1 MHz, l=100 mm, m=7 amu and E=5 eV). Hence the frequency variation should be at least 10 percent (it is noted that the number of oscillations n is directly proportional to f) or the energy variation should be at least 20 percent. The solution to the collision cell problem consists of a collision/reaction cell that can be operated in two modes. In a first mode the collision cell is driven with electrical RF fields at low beam energy and high gas pressures in the collision cell mode. In a second mode the collision cell uses DC fields at high beam energy and low gas pressures. In the RF mode the rods may be driven in two groups. The first group is connected with one of the two RF outputs and the other group of rods is connected with the other RF output (180° phase shifted with respect to the first output, see the rods11and11′ inFIG.2A). The rods of the multipole are aligned to the optical axis of the ion optics. The optical axis can be straight or curved. Due to the alternating potential of the rods the ions are actively refocused into the center of the setup. Without the focusing nature of the RF field the ions would be strayed by the collisions with the gas in the cell. In the DC mode the setup is driven substantially without gas and at a high beam energy. Therefore, a focusing RF field is not necessary. In accordance with the invention, the RF rods are segmented in at least two or three sections along the optical axis and the setup is switched to DC only mode such that effectively it works as an einzel lens. Since an einzel lens consists of three cylindrical elements that are placed coaxially on the center axis, the rods may be partitioned into three parts or sections. With such a setup both the RF-field of the multipole as well as the DC potentials of the einzel lens can be applied. Beside the einzel lens concept with three segments a DC-only mode is also possible with just two segments. In the DC mode the ions can have a much higher energy compared to the RF mode. Ion optics for ion beams with low energy are difficult to focus since the high charge density of the beam leads to a radial space charge expansion of the beam (space charge effects). Ion beam energies of several thousand eV minimize space charge effects and allow beam focusing at high ion beam currents. With the einzel lens arrangement according to the invention the ions stay at energies in the keV (kilo electronvolt) range and thus space charge effects are much reduced compared to beam energies of a few eV. The described principle of segmenting a multipole lens in order to switch between low energy RF mode and high energy DC mode can be applied not just to a multipole collision cell arrangement but also to a quadrupole mass spectrometer or any other RF multipole arrangement. This invention allows to switch a low energy RF mode ion optical setup to a high energy DC mode setup along the same optical axis. Since the two described modes can be altered just by applying different potentials to the lenses, the limiting factor for the switching time is most likely the gas pressure in the housing of the cell. For the RF mode the housing is ideally completely sealed with small (1-3 mm) diameter apertures at the entry and the exit of the collision cell housing. For the operation in the high energy DC einzel lens mode an increased pumping cross section is required to efficiently pump out residual gas as memory from a previous experiment where the arrangement has been operated as a low energy high pressure collision/reaction cell. The suggested techniques do not require expensive mechanical feed-throughs. In the first case the movement inside the vacuum is induced via a steel capillary. In the second case an electrical feed through is sufficient to induce the movement inside the vacuum. The altered potential of the foil might be combined with the potential of one of the lenses. Accordingly, the invention provides at least the following advantages:Switching between high energy DC einzel lens ion optics and low energy RF multipole lens ion optics without intervention to the vacuum system.Switching may be done by switching electronic supplies only.The high pressure collision cell may be operated by a mechanical switch to increase pumping efficiency in case of high energy and high vacuum DC operation mode.Proposed multipole arrangement of hexapole or octupole or even higher order reduces noding effects.There is only one optical axis in the system (no bypass optical axis). This allows a compact geometry and reduced aberrations.Since there is only one ion optical axis, the tuning of the system is much easier compared to a complicated deflection setup where the ion beam has to be steered along a bent bypass axis to circumvent the collision cell or vice versa.The principle of a segmented multipole lens also can be applied to a quadrupole mass filter lens. This allows the ion optical instrument to be switched from a low energy front-end RF multipole lens design to a high energy DC lens design without any noding effects.The high energy DC mode gives higher sensitivity and thus overcomes the limitations of a low energy multipole setup.The switching between the two modes allows to configure a unique instrumental setup which allows to switch to the collision mode for specific applications only and to run the same instrument in the high energy DC mode simply by switching electric power supplies. FIG.1schematically shows a collision cell according to the prior art. The collision cell1is shown to comprise a housing18in which a multipole arrangement is accommodated. In the example shown, the multipole arrangement is a hexapole arrangement comprising six elongate poles or rods11which constitute electrodes. A radio frequency (RF) voltage may be fed to opposite pairs of poles11to produce an RF electric field. Ions can enter the collision cell through an entrance aperture13and leave the collision cell through an exit aperture15. The RF field produced by the multipole arrangement focuses the ions on the longitudinal axis of the arrangement. This is particularly relevant when a collision gas is present in the collision cell, as collisions may cause the ions to deviate from their path. FIG.2Ashows a multipole arrangement, in the example shown a hexapole arrangement, without a collision cell. As inFIG.1, RF (radio frequency) voltages may be applied to the alternating rods11and11′ to generate an RF field in the arrangement that focuses ions and guides them through the arrangement. The RF field may be applied when the collision cell is pressurized. It is noted that such a multipole arrangement may not only be used in a collision cell but also in a mass filter, for example. When the collision cell is not pressurized, or at least has a lower pressure due to which the influence of the gas on the ion trajectories is reduced, the ions can have a higher energy and the RF field is not required to guide the ions. Instead, in accordance with the invention a so-called einzel lens may be used to guide the ions. FIG.2Bschematically shows an ion optic einzel lens consisting of three consecutive tube sections or rings10A,10B &10C which are electrically isolated relative to each other. A first section10A may have a first voltage V1, the second section10B may have a second voltage V2, while the third section V3 may have a third voltage V3. In some embodiments, the first voltage V1 and the third voltage V3 may be substantially equal, for example both may be equal to −1 kV. The second voltage V2 may then, for example, be equal to −2 kV. Depending on the polarity of the ions, positive voltages may be used instead, for example +1 kV, +2 kV and +1 kV respectively. It will be understood that other voltages may also be used, depending on the ions and the dimensions of the multipole arrangement. In some applications, the second voltage V2 may be equal to +1 kV, +5 kV, −1 kV or −5 kV, for example. Exemplary trajectories of ions passing through such an arrangement will later be explained in more detail with reference toFIG.6B. It has been found that it is impractical to combine the rods11and the rings10A-10C in the same collision cell or other multipole arrangement. In accordance with the invention, therefore, the rods11and the rings10A-10C are combined into a single structure, which is schematically shown inFIGS.3A &3B. FIG.3Ashows a multipole arrangement according to the invention. In the embodiment ofFIG.3A, the rods have been partitioned into sections11A,11B and11C (and similarly into11A′,11B′ and11C′). In the mode of operation illustrated inFIG.3A, the rods function as the rods11inFIG.2Aand all three sections of each rod carry the same RF voltage. In this respect, there is no functional difference withFIG.2A. However, in the mode of operation illustrated inFIG.3B, a different DC voltage is applied to consecutive ones of the rod sections11A,11B and11C, so that the rods are used in the same way as the rings10A,10B &10C ofFIG.2B. That is, the rod sections11A-11C can be said to simulate the rings10A-10C. In this way, the rods are used to constitute an einzel lens. It is noted that in the mode of operation ofFIG.3Bthe RF voltage ofFIG.3Ais typically not applied. In the embodiment ofFIGS.3A and3B, the einzel lens structure is constituted by segmented rods. Alternatively, or additionally, it is possible to provide an einzel lens structure by using other segmented electrodes, such as vanes which are often provided in the spacings between the rods of a multipole arrangement. Vanes are typically longitudinal, flat electrodes which may be used to provide axial fields, such as drag fields. By segmenting vanes instead of, or in addition to segmenting rods, an einzel lens structure can also be achieved. FIGS.4A &4Bschematically show segmented electrodes, constituted by vanes, arranged between the rods of a multipole lens arrangement, whileFIGS.5A &5Bschematically show voltage generation circuits and the resulting voltages.FIGS.4A &5Acorrespond with a first or RF operation mode whileFIGS.4B &5Bcorrespond with a second or DC operation mode. InFIG.4A, the multipole rods11are supplied with RF voltages. The vanes17(that is,17A,17B &17C together) are in the example shown used for creating an axial electric field gradient which causes a drag force. Depending on the direction of the field gradient, the drag force either accelerates or decelerates the ions passing through the multipole arrangement. Here a positive potential gradient is applied to the electrodes that induces a field gradient in the center of the arrangement. By this gradient the ions are pulled towards the exit (that is, accelerated), even when they almost have come to rest due to complete momentum transfer to the collision gas. The potential gradient can be created by two potentials that are applied on each side of the electrodes in combination with a resistor chain on the electrodes or with a homogeneous resistance of the material itself, as will be explained with reference toFIGS.5A &5B. FIG.4Bshows the same setup with three potentials applied along the segmented vanes17, as illustrates inFIG.5B. With a potential being applied at the entrance side and at the end of the first segment17A, a constant potential is applied to the first segment. The other two potentials are applied to the second segment17B and the third segment17C respectively. In the second or DC operation mode, the RF power supply for the multipole rods is typically switched off, the rods may be grounded or a DC potential may be supplied to them. FIGS.5A &5Bschematically show how suitable voltages may be applied to the vanes in the respective operation modes. Each vane17(comprising the vane sections17A,17B &17C) is shown to comprise a resistor network RN which includes electrode elements EE coupled by a series arrangement of resistors R. For each section17A,17B &17C a respective voltage source VSA, VSB & VSC is provided, which can be connected to the resistor network RN via a number of switches SW1to SW5. It is noted that the three vane sections17A,17B &17C are combined here into a single physical vane17which, however, is shown to have three distinct (but electrically connected) electrical sections, each having its own voltage source. In the first operation mode shown inFIG.5A, the switches SW1to SW5are all open. The first voltage source VS1supplies a voltage to the first resistor and hence to the entrance end (which may typically be arranged near a collision cell entrance13, for example, seeFIG.1) of the vane17A. Switch SW5connects the last resistor and hence the exit end (which may typically be arranged near a collision cell exit15, for example, seeFIG.1) of the vane17C to ground. As a result, there is a voltage or potential gradient U1along the length l of the combined vanes17A-17C, as shown inFIG.5A. This voltage gradient U1produces an electric field gradient between the poles11of the multipole arrangement (seeFIG.4A). In the second operation mode shown inFIG.5B, the switches SW1to SW5are all closed. The first voltage source VS1supplies a first voltage to the first vane section17A, the second voltage source VS2supplies a second, different voltage to the second vane section17B while the third voltage source VS3supplies a third voltage to the third vane section17C. In the example shown inFIG.5B, the first voltage and the third voltage are substantially equal, while the second voltage is higher than both the first and the third voltage. This voltage distribution U2causes the vane sections to act as an einzel lens. FIG.6Aschematically shows a multipole arrangement of a collision cell1according to the invention in a first operation mode, in which the rods are used as an RF multipole. The collision cell1is shown to have a housing18, in which the multipole arrangement is accommodated. The collision cell1is further shown to comprise an entrance electrode12and an exit electrode14, which comprises an exit opening15. All three segments11A,11B &11C of each rod have the same DC voltage in this first or RF operation mode, as inFIG.3A. This DC voltage may or may not be equal to zero (ground). In the partially expandedFIG.6Cit can be seen that the ions do not follow straight lines but have oscillating trajectories. It can also be seen, as shown inFIG.6A, that the ions fan out evenly at the exit opening15. This is the suppressed noding effect that may occur in the RF operation mode and which will later be discussed in more detail. The electrical field lines EFL are also schematically shown inFIG.6C. FIG.6Bschematically shows the same ion guide as inFIG.6A, but where different DC voltages are applied to each of the sections of the rods, as inFIG.3B, so as to provide an einzel lens. An RF voltage is not applied inFIG.6B. The trajectories of the ions (three different trajectories T are shown) depend on the entrance angles but no longer on the substantially random parameters as in the RF operation mode shown inFIG.6A. The DC voltages that may be used are, for example, between −1 kV and −2 kV at a beam energy of 2 keV (high energy). It can be seen that the einzel lens causes ions having different trajectories to pass through the exit opening15. The einzel lens can therefore be said to focus the ions in the second or DC operation mode, in which the ions may have a high energy. It is noted that according to another aspect of the invention, the collision cell may be heated to reduce so-called memory effects. That is, by heating the collision cell to a temperature of, for example, 50° C., stray ions are less likely to remain on the electrodes (rods and/or vanes) and on the inner walls of the collision cell. It will be understood that stray ions which remain behind in an experiment may detrimentally influence any further experiment. A suitable temperature range is 40° C. to 70° C., preferably 45° C. to 55° C. Heating a collision cell is preferably achieved using electric heating. As mentioned above, a problem that may arise in a multipole arrangement is noding. This effect is illustrated inFIG.7. A multipole arrangement, which may be part of a collision cell1or of a mass filter, comprises rods or poles11, to which an RF voltage may be applied. An entrance electrode (front plate)12is provided with an entrance opening13for letting an ion beam113enter the multipole arrangement. An exit electrode (back plate)14is provided with an exit opening15for letting the (modified) ion beam IB′ exit the multipole arrangement. As can be seen, some ions follow slightly different trajectories, resulting in the modified ion beam IB′. While the original ion beam113was substantially uniform, the ion beam IB′ exiting the multipole arrangement is no longer uniform, different ions exiting at slightly different angles. The trajectories shown inFIG.7are of ions having the same energy but different masses. Since different masses follow different trajectories, the probability that ions pass through the exit opening15(instead of hitting the end plate14) is also mass dependent. In addition, the focusing of the ions emerging from the multipole arrangement in a subsequent ion optical device (such as a mass analyzer) may also become mass dependent. It will be clear that this is undesirable. In embodiments of the invention, therefore, the RF frequency of the voltage supplied to the rods is varied. That is, the RF frequency is not kept constant but is changed over time. Frequency changes of at least 10% are preferred, although smaller frequency changes such as 5% may in some embodiment also be used, also depending on the length of the multipole arrangement. Frequency changes of 15% or 20% may, however, be more effective in some multipole arrangements. That is, at an RF frequency of 1 MHz, for example, the frequency is preferably made to vary at least from 0.90 MHz to 1.10 MHz (−10% and +10%). The resulting RF frequency may vary over time in various ways: sawtooth, square or sinusoidal, for example. Instead of, or in addition to changing the RF frequency to reduce the noding effect, it is also possible to superimpose a (preferably RF) frequency upon any DC bias voltage that is supplied to the multipole arrangement, even when the DC bias voltage is zero. As mentioned above, an aspect of the invention is operating a collision cell in a pressurized mode and in an evacuated (that is, non-pressurized) mode. This requires that the collision cell can be pressurized and depressurized rapidly. In particular, a pressure release mechanism is desired that is fast and effective. According to an aspect of the invention, therefore, valve mechanisms are provided which are particularly suitable for use in a collision cell having a pressurized and an evacuated operation mode, such as, but not limited to, the collision cell of the present invention. FIGS.8A &8Bshow a mechanism20for adjusting the pumping cross section of a collision cell housing18having rods11. The mechanism20is shown to comprise a door or flap21which is connected via a hinge22to the housing18of the collision cell1. The flap21can be operated by an actuator23of which one end is connected to the flap21and the other end is connected to a support element24attached to the housing18. The actuator23shown inFIGS.8A &8Bis a Bourdon tube. A Bourdon tube comprises a bent tube. The bending radius of the bent tube can be decreased if the pressure difference between the inner part and the outer part of tube increases. To this end, a gas tube25, which is also connected to the support element24, is connected with the actuator23. In the embodiment shown, the gas flows from the gas tube25through a channel in the support element24into the actuator23when the gas pressure in the gas tube25is higher than the gas pressure surrounding the actuator23. By letting gas flow into the actuator, its bending radius decreases (the actuator straightens) and the flap is opened. Conversely, the gas flows from the actuator23through the support element24into the gas tube25when the gas pressure in the gas tube25is lower than in the actuator23. By letting gas flow out of the actuator, its bending radius increases (the actuator curves) and the flap is closed. Thus, by providing a pressure difference between the gas tube25and the air (or other gas) outside the actuator23, the flap can be quickly opened or closed, thus allowing the gas pressure in the interior of the collision cell1to quickly assume the gas pressure on its outside. It is noted that the collision cell1may be accommodated in a near-vacuum environment, while the gas tube may be connected with an environment under atmospheric pressure. The gas used for inflating the inflatable actuator may be air. As the interior volume of the actuator23and the gas tube25may be small, only a small amount of air or other gas is needed to inflate the actuator. This air or other gas may be provided by a gas reservoir or by a pump. Thus, a small pump or valve can be sufficient to indirectly operate the relatively large flap. By using a Bourdon tube or similar actuator, a fast and effective pressure regulation of a collision cell can be achieved. However, a Bourdon tube is not the only type of actuator that may be used in a collision cell or similar pressurized chamber, as will be further explained with reference toFIG.9. FIG.9schematically shows an electrostatic opening mechanism used in a collision cell. The collision cell1is shown to comprise a housing18in which rods11are accommodated. An ion beam IB can pass through the collision cell1, through openings in the front plate12and back plate14respectively. In the embodiment shown, part of the wall of the housing18is provided with through holes16which can be closed off by a movable foil. This foil is located in a spacing between the housing18and a plate19. Both the housing18and the plate19contain electrically conductive material and may both be made of metal, or at least contain a metal layer or other conductive layer. The plate19, which extends substantially parallel to the housing18, may be flat but may alternatively be curved to accommodate any curvature of the housing18. In the embodiment shown, the foil comprises two layers: a conductive layer30and an electrically insulating layer31. A further electrically insulating layer32is attached to the plate19. In an alternative embodiment, the foil consists of three layers: the conductive layer30and both insulating layers31&32. Further layers may be added, as long as the foil remains sufficiently flexible. A suitable material for the insulating layers31&32is Kapton, but other materials, for example other polyimides, may also be used. The conductive layer may be made of copper foil, for example. As mentioned above, the flexible foil is located in the spacing between the housing18and the plate19. One edge of the foil may be attached to the housing18while the opposite edge may be attached to the plate19, such that the foil bridges the spacing. By applying DC voltages to the conductive layer, the position of the foils can be changed, as shown inFIG.9Aby the arrows which indicate the possible movement of the substantially S-shaped spacing-bridging portion of the foil. Referring toFIG.9B, the housing18will typically be connected to ground (GND). The conductive plate19can be connected to a high voltage, indicated by HV inFIG.9B, thus creating a voltage difference over the spacing between the housing18and the plate19. If the conductive layer30is connected to a high voltage, then the foil will be repelled by the plate19and attracted by the housing18. As a consequence, the foil will tend to move towards the housing and the S-shaped spacing bridging part will move to the right (see alsoFIG.9A). In other words, electrical forces Felpulling the foil towards the housing cause a mechanical force Fmto the right inFIG.9B. The foil will cover the through holes16and the interior of the collision cell will be closed off. Referring toFIG.9C, the through holes16can be opened by connecting the conductive layer30to ground instead of to the high voltage (HV). This will cause the foil to be repelled by the housing18and to be attracted by the plate19, which in turn cause the S-shaped spacing bridging part to move to the left (see alsoFIG.9A). In other words, electrical forces Felpulling the foil towards the plate19cause a mechanical force Fmto the left inFIG.9C. The foil will no longer cover the through holes16and the interior of the collision cell will be open to the surrounding atmosphere. As the movement of the foil is controlled by voltages, which can be switched extremely quickly, and as the foil can have a very low mass, the movement of the foil can be very quick. Accordingly, the pressure inside the collision cell1can be adjusted very rapidly and switching between a pressurized state and an evacuated state can be carried out almost instantly. The exemplary mass spectrometer10schematically shown inFIG.10comprises a collision cell1, which can be a collision cell as described above, but may be replaced by another type of ion guide. The mass spectrometer10may further comprise a plasma source1, such as an ICP (inductively coupled plasma) source, for generating an ion beam IB1. The mass spectrometer may further comprise a mass filter3, such as a magnetic sector mass filter. In the magnetic sector mass filter, the ion beam1131is separated into partial beams IB2having different m/z (mass versus charge) ratios, which partial beams can be detected by the detector assembly4, which may be a multiple detector assembly. The mass spectrometer10may further comprise a pump for lowering the gas pressure in the collision cell1, a valve associated with the pump, a voltage source5for supplying DC and AC (RF) voltages to the collision cell1, and a controller for controlling the various components of the mass spectrometer10. The valve may comprise a foil-based valve and/or a Bourdon tube-based valve as described above. Aspects of the invention comprise:a) A multipole collision cell with variation of the number of oscillations in RF mode in order to average mass dependent trajectories (noding effect).b) A multipole collision cell that is able to transmit an ion beam without RF potentials (no noding effect).c) The ability to transmit high energy ions (kilovolt range).d) Segmented multipoles (two, three or more segments per rod).e) A multipole collision cell where not the rods but drag electrodes (such as vanes) are segmented in order to transmit ions in a DC-only mode.f) A collision cell that is switchable between collision mode (filled with gas) and transmission mode (no gas) where the pumping cross section can be switched according to the cell mode.g) No additional cross section in gas mode and additional cross section for transmission mode. These aspects of the invention may be used in isolation or in combination. Although the invention has been described above mainly with reference to a collision gas, a reaction gas may additionally, or alternatively, be used. That is, the present invention also provides a reaction cell, as well as a collision/reaction cell. In some embodiments, the cell may have not two but three modes of operation: a collision mode, a reaction mode and a vacuum mode. It will be understood that in the vacuum mode, the pressure inside the cell may be greater than zero, but very small, such that any gas present in the cell has a negligible influence on the ions entering the cell. It will be understood by those skilled in the art that the invention is not limited to the embodiments shown and that many additions and/or modifications can be made without departing from the scope of the invention as defined in the appending claims. | 34,169 |
11862451 | DESCRIPTION OF EMBODIMENTS One embodiment of the orthogonal acceleration time-of-flight mass spectrometer according to the present invention is hereinafter described with reference to the drawings. In the following descriptions, the orthogonal acceleration time-of-flight mass spectrometer according to the present embodiment may be simply called the “mass spectrometer”. It should be noted that the components in the drawings are schematically depicted, with their respective shapes and scales appropriately altered from their actual shapes and scales so that the features of the present embodiment can be easily understood. FIG.1shows a schematic configuration of the mass spectrometer1according to the present embodiment. The mass spectrometer1includes an ionization unit having an ionization chamber10formed inside, and a vacuum chamber100combined with the ionization unit. The vacuum chamber100includes a first intermediate vacuum chamber11, second intermediate vacuum chamber12and analysis chamber13. The ionization chamber10is at substantially atmospheric pressure, while the first intermediate vacuum chamber11, second intermediate vacuum chamber12and analysis chamber13have the configuration of a differential pumping system in which their degrees of vacuum are gradually increased in the mentioned order. The ionization chamber10is equipped with an electrospray ionization (ESI) source101which ionizes a liquid sample by spraying the liquid sample in the form of droplets while imparting electric charges to those droplets. Although the ion source in the present embodiment is an ESI source, a different type of ion source can also be used. An ion source configured to ionize a gas sample or solid sample may also be used. The ions generated within the ionization chamber10are introduced into the first intermediate vacuum chamber11through a capillary102provided in the partition member between the ionization chamber10and the first intermediate vacuum chamber11. The capillary102is heated by a heat source (not shown). The ions generated within the ionization chamber10are drawn into the first intermediate vacuum chamber11by a flow of gas which is formed due to the pressure difference between the ionization chamber10(which is at substantially atmospheric pressure) and the first intermediate vacuum chamber11. The solvent in the droplets which still remains in the flow of gas is removed while the gas is passing through the heated capillary102. The first intermediate vacuum chamber11contains a multipole ion guide111. The ion beam is converged into the vicinity of the ion optical axis C1 by this multipole ion guide111. The ion beam converged within the first intermediate vacuum chamber11enters the second intermediate vacuum chamber12through the hole formed at the apex of a skimmer cone112provided in the partition member between the first and second intermediate vacuum chambers11and12. The second intermediate vacuum chamber12contains a quadrupole mass filter121which separates ions according to their mass-to-charge ratios, a collision cell123containing a multipole ion guide122, and a front transfer electrode124for transporting ions ejected from the collision cell123(this electrode corresponds to the front part of a transfer electrode130for transporting ions from the collision cell123to the orthogonal accelerator132). The members located on the front side of the front transfer electrode123(on the side where the ESI source101is present) are positioned so that their respective central axes coincide with the ion optical axis C1. The inner space of the collision cell123is continuously or intermittently supplied with a collision-induced dissociation (CID) gas, such as argon or nitrogen. The multipole ion guide122in the collision cell123includes a plurality of rod electrodes arranged so that the space surrounded by these electrodes gradually widens toward the exit end of the collision cell123. According to this configuration, a potential gradient for transporting ions toward the exit of the collision cell123can be created by simply applying a radio-frequency voltage to each rod electrode. At the exit of the collision cell123, a ring-shaped exit electrode1231having an opening1232(seeFIGS.4and5) for ejecting ions generated in the collision cell123is located. A partition wall164is provided between the second intermediate vacuum chamber12and the analysis chamber13(seeFIG.2). The partition wall164consists of an extended part1641protruding from the inner wall surface of the vacuum chamber100and a partition member1642fixed to the extended part1641with screws (not shown) on the side facing the analysis chamber13. The vacuum chamber100and the extended part1641in the present embodiment are prepared as separate members. Alternatively, the extended part1641may be integrated with the vacuum chamber100. The analysis chamber13contains: a rear transfer electrode131for transporting ions coming from the second intermediate vacuum chamber12to the orthogonal accelerator132(this electrode corresponds the rear part of the transfer electrode130for transporting ions from the collision cell123to the orthogonal accelerator132); an orthogonal accelerator132including a pusher electrode1321and an puller electrode1322facing each other across an ion optical axis C2 (orthogonal acceleration region); a second accelerator133for accelerating ions directed from the orthogonal accelerator132toward the flight space; a reflectron134for forming a path for repelling ions within the flight space; an ion detector135; and a flight tube136and a back plate137located on the periphery of the flight space. The reflectron134, flight tube136and back plate137collectively define the flight space for the ions. The reflectron134consists of a front reflectron1341and a rear reflectron1342. A grid is formed in each of the entrance and exit electrodes of the front reflectron1341. Thus, as shown inFIG.3, a field-free flight space is formed within the flight space between the reflectron134and the orthogonal accelerator132, while a rising potential gradient is formed within the space surrounded by the front reflectron1341, as well as another rising potential gradient formed within the space surrounded by the rear reflectron1342. The multipole ion guide111in the first intermediate vacuum chamber11, as well as the quadrupole mass filter121and the collision cell123in the second intermediate vacuum chamber12are each fixed to and positioned on the wall surface of the vacuum chamber100. The front transfer electrode124in the second intermediate vacuum chamber12is fixed to and positioned on the collision cell123. The mass spectrometer1according to the present embodiment is characterized in that the components which define the ion optical axes C1 and C2 are arranged so that the ion optical axis C2, which is the central axis of the rear transfer electrode131and the orthogonal accelerator132, is shifted from the ion optical axis C1 in the direction opposite to the direction in which ions are accelerated by the orthogonal accelerator132. FIG.2is an enlarged view showing the transfer electrode130, orthogonal accelerator132and the surrounding area.FIG.4is a diagram showing the positional relationship of the ion optical axes C1 and C2. The transfer electrode130includes the front transfer electrode124in the second intermediate vacuum chamber12and the rear transfer electrode131extending from inside the second intermediate vacuum chamber12into the analysis chamber13through the partition wall1642. As shown inFIG.4, the front transfer electrode124consists of two ring electrodes1241and1242. These two ring electrodes1241and1242are fixed to each other via an insulation member161. The frontmost ring electrode1241in the front transfer electrode124is fixed to the exit electrode1231of the collision cell123via an insulation member161, whereby the front transfer electrode124is positioned. The collision cell123is fixed to the vacuum chamber100via a fixing member150. The ring electrodes1241and1242have central openings151and152for allowing ions to pass through, respectively. As shown inFIG.5, the opening151of the ring electrode1241has a larger diameter than the opening1232of the exit electrode1231of the collision cell123as well as the opening152of the ring electrode1242. The collision cell123and the ring electrodes1241and1242are arranged so that the central axis of the opening1232of the exit electrode1231of the collision cell123is aligned with the central axis of the openings151and152of the ring electrodes1241and1242(ion optical axis C1). As shown inFIG.6, the rear transfer electrode131consists of four ring electrodes1311,1312,1313and1314. These four ring electrodes1311,1312,1313and1314are also fixed to each other via insulation members162and163. The frontmost ring electrode1311(on the side of the ionization chamber10) is located within the second intermediate vacuum chamber12, while the other three ring electrodes1312,1313and1314are located within the analysis chamber13. The insulation member162connecting the two ring electrodes1311and1312on the front side has an outer shape corresponding to the opening formed in the partition member1642separating the second intermediate vacuum chamber12and the analysis chamber13. The insulation member162is fitted in this opening. The insulation member162thus held is slidable along the ion optical axis C2. The outer shape of the insulation member162in the present embodiment has a circular in outer shape. The ring electrode1311in the second intermediate vacuum chamber12has a circular opening153having a larger diameter than the opening152of the ring electrode1242. The ring electrodes1312,1313and1314in the analysis chamber13have rectangular openings154,155and156, respectively, which correspond to the opening formed in the ion-entrance surface of the orthogonal accelerator132located after these electrodes. At a predetermined position169on the side wall of the vacuum chamber100within the analysis chamber13, a plate-shaped base member167having a rectangular opening at its center is fixed. In the present embodiment, the vacuum chamber100and the base member167are prepared as separate parts. Alternatively, the base member167may be integrated with the vacuum chamber100. A base plate138made of an electrically conductive material and having two ion-passing openings is fixed to the upper surface of the base member167via an insulation member168. Located on the upper surface of the base plate138is a plate-shaped spacer member141made of an electrically conductive material and having an ion-passing opening, on which a rectangular positioning plate140made of an electrically conductive material and having an ion-passing opening is fixed. The rearmost ring electrodes1314in the rear transfer electrode131is fixed to this positioning plate140via a conducting member165and an insulation member166. Also fixed to the positioning plate140is an ion acceleration unit, which includes the orthogonal accelerator132formed by the pusher and puller electrodes1321and1322, as well as the second accelerator133. Additionally, the ion detector135is fixed to the base plate138. The ion acceleration unit includes, on the positioning plate140, the second accelerator133formed by alternately stacking insulation members and acceleration electrodes, on which the puller electrode1322is placed via an insulation member and an elastic member, on which the pusher electrode1321is further placed via an insulation member. The puller electrode1322is a grid-shaped electrode. The acceleration electrodes are ring-shaped electrodes each of which has a central opening for allowing ions to pass through. The configuration according to the present embodiment in which the spacer member141is used to make the level of the ion optical axis C2 higher than that of the ion optical axis C1 is nothing more than a specific example. The ion optical axis C2 may be shifted from the ion optical axis C1 without using the spacer member141, for example, by appropriately adjusting the thickness of one or more members among the base member167, insulation member168, base plate138and positioning plate140. In a conventional orthogonal acceleration time-of-flight mass spectrometer, the components from the capillary102to the orthogonal accelerator132are arranged so that their respective central axes (ion optical axis C) are aligned with each other. A portion of the gradually spreading ion beam travelling forward after exiting from the exit electrode of the collision cell is extracted from an area around the ion optical axis C by the front and rear transfer electrodes and introduced into the orthogonal accelerator. By comparison, in the orthogonal acceleration time-of-flight mass spectrometer1according to the present embodiment, the central axes of the components from the capillary102to the front transfer electrode124are aligned to form one ion optical axis, C1, while those of the rear transfer electrode131and the orthogonal accelerator132are aligned to form another ion optical axis, C2. The spacer member141is provided to shift the ion optical axis C2 from the ion optical axis C1 in the direction opposite to the direction in which ions are accelerated by the orthogonal accelerator132. The effect obtained by shifting the ion optical axis C2 from the ion optical axis C1 in this manner has been confirmed by a simulation. The simulation result is hereinafter described. FIGS.7and8show the result of the simulation of the sectional shape of an ion beam entering the orthogonal accelerator132in the orthogonal acceleration time-of-flight mass spectrometer1according to the present embodiment (present example), and that of an ion beam entering the orthogonal accelerator in a conventional orthogonal acceleration time-of-flight mass spectrometer (conventional example). In the conventional example, the ion beam is almost equally spread toward both the pusher and puller electrodes with respect to the ion optical axis C when entering the orthogonal accelerator. By comparison, in the present example, the ion beam is biased toward the pusher electrode1321when entering the orthogonal accelerator132. FIGS.9and10show the spread ΔX of the position X of the ions at the point in time of the acceleration of the ions within the orthogonal accelerator and the distribution ΔVx of the velocity component Vx in the direction of the orthogonal acceleration in the previously described embodiment and the conventional example, respectively. The spread ΔX of the position X of the ions in the conventional example (FIG.10; 1.2 mm) is smaller than in the present embodiment (FIG.9; 1.7 mm). The kinetic energy imparted to each ion within the orthogonal accelerator changes depending on the position of the ion within the orthogonal accelerator. However, the variation in the time of flight due to this difference in kinetic energy will be compensated for while the ions fly in the electric field created by the reflectron. Specifically, among the ions having the same mass-to-charge ratio, an ion having a larger amount of kinetic energy will fly deeper into the repelling electric field. This has the effect of cancelling the variation in the time of flight due to the positional spread of the ions in the direction of the acceleration within the acceleration space. In particular, when the reflectron described in Patent Literature 6 is used, the variation in the time of flight can be compensated for over an even wider range of energy. Accordingly, the positional variation of the ions within the orthogonal accelerator poses no serious problem in improving the mass-resolving power, provided that the ions are within a range of energy that can be compensated for by the reflectron. On the other hand, the difference ΔVx in the velocity component Vx of the ions in the direction of the orthogonal acceleration within the orthogonal accelerator gives rise to a turnaround time at the beginning of the orthogonal acceleration of each ion. The variation in the time of flight due to this turnaround time cannot be cancelled by the reflectron. As shown inFIG.9, by adopting the configuration according to the present embodiment, the difference ΔVx in the velocity component of the ions in the direction of the orthogonal acceleration is decreased as compared to the conventional example (from 1.2 mm/μs to 0.9 mm/μs). This reduces the decrease in the mass-resolving power due to the variation in the time of flight originating from the turnaround time. FIG.11shows the result of a measurement in which the mass-resolving power for a positive ion (m/z=1971) and a negative ion (m/z=1625) was measured by a real orthogonal acceleration time-of-flight mass spectrometer, with the position of the ion optical axis C2 relative to the ion optical axis C1 varied.FIG.12shows the results of a simulation in which the mass-resolving power for a positive ion (m/z=922) was calculated for different positions of the ion optical axis C2 relative to the ion optical axis C1. InFIGS.11and12, the horizontal axis represents the position of the central axis of the pusher and puller electrodes1321and1322of the orthogonal accelerator132(ion optical axis C2) relative to the central axis of the exit electrode1231of the collision cell123(ion optical axis C1), while the vertical axis represents the mass-resolving power. In bothFIGS.11and12, it can be seen that the mass-resolving power becomes higher as the ion optical axis C2 is gradually shifted from the ion optical axis C1 in the positive direction (i.e., in the direction opposite to the direction of the orthogonal acceleration of the ions). The distribution of the ions around the ion optical axis C1 is such that the number of ions becomes larger as the position to the optical axis C1 is closer, and vice versa. Accordingly, while the mass-resolving power becomes higher as the ion optical axis C2 is shifted farther from the ion optical axis C1, an excessive shift will cause a considerable decrease in the amount of the ions passing through the openings153-156of the rear transfer electrode131, lowering the measurement sensitivity of the ions. Accordingly, the relationship between the mass-to-charge ratio and the sensitivity should be considered in determining the magnitude by which the ion optical axis C2 is shifted from the ion optical axis C1. In order to improve the mass-resolving power without significantly sacrificing the measurement sensitivity, it is appropriate to shift the axis by roughly one half (e.g., within a range from 25% to 75%) of the width, in the acceleration direction, of the opening of the ring electrode which blocks the ions (in the present embodiment, the length of the shorter side of the opening154). In the present embodiment, the shift of the ion optical axis C2 from the ion optical axis C1 is approximately 0.3 mm. In many cases, shifting the axis by an amount corresponding to 25% of the width, in the acceleration direction, of the opening of the ion-blocking ring electrode will significantly improve the mass-resolving power. On the other hand, shifting the axis by an amount greater than 75% of that width will cause a considerable decrease in the amount of the ions passing through the opening and lowers the measurement sensitivity of the ions. The results in the examples ofFIGS.11and12demonstrate that shifting the ion optical axis C2 from the ion optical axis C1 in the negative direction lowers the mass-resolving power. This is due to the fact that shifting the ion optical axis C2 in the negative direction brings the incident position of the ions closer to the puller electrode1322, which causes the amount of kinetic energy imparted within the orthogonal accelerator132to be decreased and consequently go out of the range of the kinetic energy which can be compensated for by the reflectron. When a reflectron having a wider range for compensating for the variation in the kinetic energy imparted in the orthogonal accelerator is used, the mass-resolving power can also be improved even with a configuration in which the ion optical axis C2 is shifted in the negative direction. Patent Literature 5 discloses the idea of creating a steeper potential gradient within the orthogonal accelerator132in order to shorten the turnaround time. However, creating a steeper potential gradient within the orthogonal accelerator132means that the spread of the energy imparted to the ions depending on the incident position of each ion becomes greater and may possibly exceed the range of the spread of energy that can be compensated for by the reflectron. The puller electrode is normally a grid electrode in which a number of holes for allowing ions to pass through are formed in a lattice pattern. Applying a high voltage to a grid electrode produces a lens effect, which causes the direction of flight of the ions to bend after their passage through the holes. This effect may prevent some ions from reaching the ion detector135and lower the signal intensity. It may also cause a temporal aberration in the trajectory of the ions deviated from the central axis and lower the mass-resolving power. The amount of divergence ΔVy of an ion after its passage through a grid electrode (i.e., the change in the velocity of an ion in the y-axis direction before and after its passage through the grid) is expressed by the following equation: ΔVy=qEP/2mVx(1) where q is the number (or amount) of the charge of the ion, E is the electric field created at the grid electrode, P is the grid interval, m is the mass of the ion, and Vx is the velocity of the ion in the x-axis direction. As can be understood from equation (1), the stronger the electric field created at the grid electrode is, the larger the change in the velocity of the ion in the y-axis direction is. The y-axis is orthogonal to both the direction of the injection of the ions into the orthogonal accelerator132(z-axis) and the direction of the acceleration axis (x-axis). As can be seen inFIG.13which shows the simulation result based on equation (1), increasing the potential gradient created within the orthogonal accelerator132leads to a significant change in the velocity component of the ion in the y-axis direction. Consequently, the signal intensity will be lowered due to some ions failing to reach the ion detector135. A temporal aberration may also occur in the trajectory of the ions deviated from the central axis and lower the mass-resolving power. Increasing the magnitude of a pulse voltage applied in the orthogonal accelerator132also requires a high-output power source and incurs an increase in cost. Applying a high voltage also increases the possibility of electric discharge, which may possibly lower the mass-resolving power or mass accuracy as well as cause some problem in the power source or other related sections. The previous embodiment is a specific example and can be appropriately changed or modified along the gist of the present invention. In the previous embodiment, a portion of the ion beam exiting from the collision cell123is extracted by each of the ring electrodes1312and1314which form the rear transfer electrode131. It is not always necessary to use two or more ring electrodes for this purpose. It is possible to use a single ring electrode to extract a portion of the ion beam exiting from the collision cell123. In that case, the single ring electrode should be arranged so that the central axis of the ion-passage opening formed in the electrode is shifted from the central axis of the collision cell123in a direction along the axis of acceleration of the ions (and preferably, in the direction opposite to the direction of the acceleration of the ions). In the previous embodiment, the components which define the ion optical axes C1 and C2 are arranged so that the ion optical axis C1 of the components located on the front side of the front transfer electrode124is parallel to the ion optical axis C2 of the rear transfer electrode131and the orthogonal accelerator132. As another possible arrangement, the collision cell123(more exactly, the collision cell123and the front transfer electrode124, or the components on the front side of the collision cell123) may be tilted with respect to the rear transfer electrode131and the orthogonal accelerator132around the center of the entrance of the collision cell123so as to shift (or tilt) the ion optical axis C2 with respect to the central axis C1 of the exit electrode of the collision cell123. In the previous embodiment, the rear transfer electrode131and the orthogonal accelerator132are arranged so that they have a common central axis (ion optical axis C2). It is not always necessary for their respective central axes to coincide with each other. The minimum requirement is that the ion beam which has passed through the rear transfer electrode131should enter the orthogonal accelerator132. However, making their respective central axes coincide with each other is advantageous in that the ion beam which has passed through the rear transfer electrode131can be directed at an appropriate position between the pusher and puller electrodes1321and1322so that the ions are less likely to collide with these electrodes and be lost. The previous embodiment is concerned with the configuration for the orthogonal acceleration of ions ejected from the collision cell123. The previously described configuration can be similarly employed for the orthogonal acceleration of ions generated by a different type of component, such as an ion trap. The previously embodiment is configured as a tandem system including the quadrupole mass filter121as the front mass separator. The previously described configuration can be similarly employed in a device in which ions generated by the ion source are directly subjected to the orthogonal acceleration for the measurement. [Modes] A person skilled in the art can understand that the previously described illustrative embodiments are specific examples of the following modes of the present invention. (Clause 1) An orthogonal acceleration time-of-flight mass spectrometer according to one mode of the present invention includes:an ion ejector configured to eject measurement-target ions in a predetermined direction;an orthogonal accelerator configured to accelerate ions in a direction orthogonal to the direction in which the ions are ejected;a ring electrode located between the ion ejector and the orthogonal accelerator, the ring electrode having an opening for allowing ions to pass through and arranged so that the central axis of the opening is shifted from the central axis of the ion ejector in a direction along the axis of acceleration of the ions by the orthogonal accelerator;a reflectron electrode configured to create a repelling electric field for reversing the direction of the ions accelerated by the orthogonal accelerator; andan ion detector configured to detect ions after the direction of flight of the ions is reversed by the reflectron electrode. In the orthogonal acceleration time-of-flight mass spectrometer described in Clause 1, measurement-target ions are ejected from the ion ejector in a predetermined direction. The orthogonal accelerator imparts kinetic energy to the ions in a direction orthogonal to the aforementioned direction. The ions are thereby made to fly in a reciprocal path within a drift space, to be ultimately detected by the ion detector. In the orthogonal acceleration time-of-flight mass spectrometer described in Clause 1, a portion of the gradually spreading ion beam traveling from the ion ejector is extracted by the ring electrode whose central axis is located at a position shifted from the central axis of the ion ejector, i.e., the central axis of the ion beam. As compared to the configuration in which the ion beam is extracted from an area around the central axis of the ion beam, the present configuration can reduce the angular spread of the ion beam entering the orthogonal accelerator. This shortens the turnaround time and improves the mass-resolving power, without sacrificing the signal intensity and mass accuracy. Since the potential gradient created within the orthogonal accelerator only needs to be as steep as a conventional gradient, there is no need to use a high-output power source, and no increase in the production cost is incurred. (Clause 2) The orthogonal acceleration time-of-flight mass spectrometer described in Clause 1 may be configured as follows: the orthogonal accelerator is formed by a pusher electrode and a puller electrode which are a pair of plate electrodes; and the ring electrode is arranged so that the central axis of the opening of the ring electrode lies halfway between the pusher electrode and the puller electrode. In the orthogonal acceleration time-of-flight mass spectrometer described in Clause 2, the central axis of the opening of the ring electrode lies halfway between the pusher electrode and the puller electrode forming the orthogonal accelerator. Therefore, the cluster of ions which have passed through the opening of the ring electrode can enter an area around the center of the orthogonal acceleration space without colliding with the pusher or puller electrode. (Clause 3) In the orthogonal acceleration time-of-flight mass spectrometer described in Clause 1 or 2, the ring electrode may be arranged so that the central axis of the opening of the ring electrode is shifted from the central axis of the ion ejector in a direction opposite to the direction in which ions are accelerated by the orthogonal accelerator. In the orthogonal acceleration time-of-flight mass spectrometer described in Clause 1 or 2, the central axis of the opening of the ring electrode may be shifted from the central axis of the ion ejector either in the direction in which ions are accelerated by the orthogonal accelerator or in the opposite direction. However, it should be noted that the reflectron used in the orthogonal acceleration time-of-flight mass spectrometer has a limited range of kinetic energy within which the reflectron can cancel the spread of the time of flight due to the difference in the kinetic energy imparted to the individual ions caused by the positional spread of the ions within the orthogonal accelerator. When the ring electrode is arranged so that the central axis of the opening of the ring electrode is shifted from the central axis of the ion ejector in the direction of the acceleration of the ions, the cluster of ions will enter an area which is rather close to the puller electrode. In that case, the kinetic energy imparted to the cluster of ions will be low and may possibly fail to fall within the aforementioned range if there is only a narrow range of kinetic energy within which the variation of the kinetic energy can be cancelled by the reflectron. Accordingly, it is preferable to adopt the configuration in which the ring electrode is arranged so that the central axis of the opening of the ring electrode is shifted from the central axis of the ion ejector in the direction opposite to the direction of the acceleration of the ions so as to inject the cluster of ions into an area which is rather close to the pusher electrode, as in the orthogonal acceleration time-of-flight mass spectrometer described in Clause 3. (Clause 4) The orthogonal acceleration time-of-flight mass spectrometer described in any of Clauses 1-3 may include an arrangement of a plurality of the ring electrodes. In the orthogonal acceleration time-of-flight mass spectrometer described in Clause 4, the angular spread of the ion beam entering the orthogonal accelerator can be even more reduced by the openings of the plurality of ring electrodes. REFERENCE SIGNS LIST 1. . . Orthogonal Acceleration Time-of-Flight Mass Spectrometer10. . . Ionization Chamber101. . . ESI (Electrospray Ionization) Source11. . . First Intermediate Vacuum Chamber111. . . Multipole Ion Guide12. . . Second Intermediate Vacuum Chamber121. . . Quadrupole Mass Filter122. . . Multipole Ion Guide123. . . Collision Cell1231. . . Exit Electrode124. . . Front Transfer Electrode1241,1242. . . Ring Electrode13. . . Analysis Chamber130. . . Transfer Electrode131. . . Rear Transfer Electrode1311,1312,1313,1314. . . Ring Electrode132. . . Orthogonal Accelerator1321. . . Pusher Electrode1322. . . Puller Electrode133. . . Second Accelerator134. . . Reflectron1341. . . Front Reflectron1342. . . Rear Reflectron135. . . Ion Detector136. . . Flight Tube137. . . Back Plate138. . . Base Plate140. . . Positioning Plate141. . . Spacer Member150. . . Fixing Member | 32,655 |
11862452 | In the different figures, the same reference signs refer to the same or analogous elements. All the figures are schematic, not necessarily to scale, and generally only show parts which are necessary to elucidate example embodiments, wherein other parts may be omitted or merely suggested. DETAILED DESCRIPTION Example embodiments will now be described more fully hereinafter with reference to the accompanying drawings. That which is encompassed by the claims may, however, be embodied in many different forms and should not be construed as limited to the embodiments set forth herein; rather, these embodiments are provided by way of example. Furthermore, like numbers refer to the same or similar elements or components throughout. The present disclosure will be described with respect to particular embodiments and with reference to certain drawings but the disclosure is not limited thereto but only by the claims. The drawings described are only schematic and are non-limiting. In the drawings, the size of some of the elements may be exaggerated and not drawn on scale for illustrative purposes. The dimensions and the relative dimensions do not correspond to actual reductions to practice of the disclosure. Furthermore, the terms first, second, third and the like in the description and in the claims, are used for distinguishing between similar elements and not necessarily for describing a sequence, either temporally, spatially, in ranking or in any other manner. It is to be understood that the terms so used are interchangeable under certain circumstances and that the embodiments of the disclosure described herein are capable of operation in other sequences than described or illustrated herein. Moreover, the terms top, bottom, over, under and the like in the description and the claims are used for descriptive purposes and not necessarily for describing relative positions. It is to be understood that the terms so used are interchangeable with their antonyms under certain circumstances and that the embodiments of the disclosure described herein are capable of operation in other orientations than described or illustrated herein. It is to be noticed that the term “comprising”, used in the claims, should not be interpreted as being restricted to the means listed thereafter; it does not exclude other elements or steps. It is thus to be interpreted as specifying the presence of the stated features, integers, steps or components as referred to, but does not preclude the presence or addition of one or more other features, integers, steps or components, or groups thereof. The term “comprising” therefore covers the situation where only the stated features are present and the situation where these features and one or more other features are present. Thus, the scope of the expression “a device comprising means A and B” should not be interpreted as being limited to devices consisting only of components A and B. It means that with respect to the present disclosure, the only relevant components of the device are A and B. Reference throughout this specification to “one embodiment” or “an embodiment” means that a particular feature, structure or characteristic described in connection with the embodiment is included in at least one embodiment of the present disclosure. Thus, appearances of the phrases “in one embodiment” or “in an embodiment” in various places throughout this specification are not necessarily all referring to the same embodiment, but may. Furthermore, the particular features, structures or characteristics may be combined in any suitable manner, as would be apparent to one of ordinary skill in the art from this disclosure, in one or more embodiments. Similarly, it should be appreciated that in the description of example embodiments of the disclosure, various features of the disclosure are sometimes grouped together in a single embodiment, figure, or description thereof for the purpose of streamlining the disclosure and aiding in the understanding of one or more of the various inventive aspects. This method of disclosure, however, is not to be interpreted as reflecting an intention that the claimed disclosure requires more features than are expressly recited in each claim. Rather, as the following claims reflect, inventive aspects lie in less than all features of a single foregoing disclosed embodiment. Thus, the claims following the detailed description are hereby expressly incorporated into this detailed description, with each claim standing on its own as a separate embodiment of this disclosure. Furthermore, while some embodiments described herein include some but not other features included in other embodiments, combinations of features of different embodiments are meant to be within the scope of the disclosure, and form different embodiments, as would be understood by those in the art. For example, in the following claims, any of the claimed embodiments can be used in any combination. In the description provided herein, numerous specific details are set forth. However, it is understood that embodiments of the disclosure may be practiced without these specific details. In other instances, well-known methods, structures and techniques have not been shown in detail in order not to obscure an understanding of this description. Reference will be made to transistors. These are devices having a first main electrode such as a drain, a second main electrode such as a source and a control electrode such as a gate for controlling the flow of electrical charges between the first and second main electrodes. It will be clear for a person skilled in the art that the present disclosure is also applicable to similar devices that can be configured in any transistor technology, including for example, but not limited thereto, CMOS, BiCMOS, Bipolar and SiGe BiCMOS technology. The following terms are provided solely to aid in the understanding of the disclosure. As used herein, and unless otherwise specified, the term “source/drain” is used to refer to “source and/or drain”. Likewise, a “source/drain structure” (e.g., a source/drain region) is a “source structure and/or drain structure” (e.g., a source region and/or a drain region). In a first aspect, the present disclosure relates to a method for forming a contact isolation for a semiconductor device, comprising: (a) providing a semiconductor structure comprising a trench exposing a contact thereunder, (b) filling a bottom of the trench with a sacrificial material, (c) infiltrating the sacrificial material with a ceramic material, and (d) removing the sacrificial material. Upon removing the sacrificial material, the ceramic material remains and forms the contact isolation. In embodiments, the semiconductor device may be a complementary field-effect transistor. In embodiments, the semiconductor structure may be an intermediate structure for a complementary field-effect transistor. In embodiments, the intermediate structure may comprise a semiconductor substrate (e.g., a Si substrate), an auxiliary region (e.g., a SiGe region) on the semiconductor substrate and a semiconductor region (e.g., a Si region) on the auxiliary region. Such an auxiliary region (e.g., SiGe region) can, for example, may be desirable in that it can be selectively removed (e.g., with respect to the Si region or Si substrate), selectively recessed or selectively oxidized (e.g., to from an inner spacer). This is for example useful in forming a gate-all-around (e.g., in a replacement metal gate module). In embodiments, the semiconductor substrate may be for defining therein a first channel for a CFET. In embodiments, the semiconductor region may be for defining therein a second channel for a CFET. In embodiments, the semiconductor region may be overlaid with one or more gate lines. In embodiments, the gate lines may each be covered with a gate cap (e.g., a Si3N4gate cap) and flanked with gate spacers (e.g., a Si3N4gate spacers). In embodiments, the trench may separate gate spacers of two adjacent gate lines. In embodiments, the trench may penetrate through the semiconductor region and the auxiliary region. In embodiments, the contact may comprise a contact liner (e.g., TiN) and a contact metal (e.g., W). The contact can aid in reducing the contact resistance and in interface preparation. In embodiments, the contact may overlay a source/drain region. In embodiments, the source/drain region may be a p-doped epitaxial source/drain region (e.g., a B-doped embedded SiGe). In embodiments, step b may comprise: (b1) filling the trench with the sacrificial material, and (b2) etching back the sacrificial material. In embodiments, step b2 may comprise an H2/He-based plasma etching. A H2/He-based plasma etching allows to etch the sacrificial material at a relatively low etch rate (e.g., about eight to ten times slower as compared to using a standard O2-based plasma), thereby allowing to well control the etching depth. In embodiments, step b2 may comprise etching back the sacrificial material to a thickness of 30 nm or less, and in some examples 20 nm or less or 10 nm or less (e.g., from 1 to 10 nm). In embodiments, the sacrificial material may comprise functional groups suitable for coordinating with the first precursor (cf. infra). In embodiments, the sacrificial material may comprise a Lewis basic functional group (e.g., an electron donor for coordinating with a Lewis acid). In embodiments, the Lewis basic functional group may comprise a heteroatom (e.g.,0or N). In embodiments, the Lewis basic functional group may comprise a carbonyl, ester, amide or amine functionality. In embodiments, the sacrificial material may be a spin-on-carbon (SoC), a poly(methyl methacrylate) (PMMA) or a polyphthalamide (PPA), for example an SoC or a PMMA. One suitable SoC may for example be HM710 from JSR micro. In embodiments, the ceramic material may be a metal oxide. In embodiments, the ceramic material may be an oxide of Al (e.g., Al2O3), Hf (e.g., HfO2), Zr (e.g., ZrO2), Ti (e.g., TiOx), Ru (e.g., RuOx) or Si (e.g., SiO2). In embodiments, the ceramic material may have a relative dielectric constant of 15 or less, for example 10 or less or 5 or less. For example, Al2O3has relative dielectric constant around 8.5-9.0 and SiO2around 3.5-4.5; compared to Si3N4which is often used as a material for a contact isolation before now and which is around 6.2. According to the present disclosure, any sacrificial material defined herein can be used with any ceramic material defined herein. As non-limitative examples, the sacrificial material can be SoC and the ceramic material can be an oxide of Al (e.g., Al2O3); the sacrificial material can be a PMMA and the ceramic material can be an oxide of Al (e.g., Al2O3); the sacrificial material can be SoC and the ceramic material can be an oxide of Si (e.g., SiO2); or the sacrificial material can be PMMA and the ceramic material can be an oxide of Si (e.g., SiO2). In embodiments, step c may comprise: (c1) exposing the sacrificial material to a first precursor, and (c2) exposing the sacrificial material to a second precursor. The first and second precursor are thus precursors for forming the ceramic material and may in that sense alternatively be referred to respectively as ‘first ceramic material precursor’ and ‘second ceramic material precursor’. In embodiments, the first precursor may be a Lewis acidic metal compound and wherein the second precursor may be an oxidant. In embodiments, the Lewis acidic metal compound may be selected from 2Al(CH3)3(trimethylaluminium, TMA), HfCl4, Zn(C2H5)2, TiCl4, SiCl4or ToRuS-blend (e.g., from Air Liquide). In embodiments, the first precursor may coordinate selectively to the sacrificial material with respect to other exposed materials of the semiconductor structure (e.g., the gate cap, gate spacers, and semiconductor region). In embodiments, the oxidant may be H2O or O3. In embodiments, step c may be performed in a reaction chamber. In embodiments, step c1 may further comprise, after exposing the sacrificial material to the first precursor, purging the reaction chamber with an inert gas (e.g., N2). In embodiments, step c2 may further comprise, after exposing the organic sacrificial material to the first precursor, purging the reaction chamber with an inert gas (e.g., N2). In embodiments, step c may comprise a sequential infiltration synthesis. In embodiments, a sequence comprising step c1 and step c2 may be performed from 1 to 100 times, for example from 2 to 20 times, or from 3 to 10 times. In embodiments, the method may comprise a step e, after step c, of: (e) growing a further ceramic material on the ceramic material. In embodiments, step e may be performed before or after step d. In embodiments, the further ceramic material may be SiO2. In embodiments, step e may comprise growing SiO2on an alkylaluminium seeding layer using an alkoxysilanol (e.g., tris(tert-pentoxy)silanol, TPS; or tris(tert-butoxy)silanol, TBS). In embodiments, the method may comprise in step c infiltrating the sacrificial material with an alkylaluminium (e.g., TMA) and subsequently in step e growing SiO2on the alkylaluminium using the alkoxysilanol. In embodiments, step d may comprise removing the sacrificial material selectively with respect to the ceramic material. In embodiments, step d may comprise an O2-based (e.g., Ar/O2) plasma etching. Such an O2-based plasma etching can be desirable in that, for at least some sacrificial materials (e.g., PPA), the effect of the ceramic material shrinking upon removing the sacrificial material (cf. infra) was observed to be more pronounced than when a reducing chemistry such as N2/H2is used instead. The thickness in the latter case did also decrease, but to a lesser degree. It was surprisingly realized within the present disclosure that by infiltrating the sacrificial material with a ceramic material and subsequently removing the sacrificial material, the ceramic material shrinks, yielding a contact isolation with the desired characteristics (e.g., being sufficiently thin). This is especially true if the thickness of the sacrificial material was already relatively thin to begin with, as for example obtainable by etching it back in a relatively slow and controlled fashion (cf. supra). As such, the thickness of the resulting contact isolation can be effectively controlled through the sacrificial material thickness and the amount of ceramic material infiltrated therein (e.g., a number of SIS cycles). Furthermore, the obtained contact isolation also typically has a top profile which is relatively flat and this independently of the top profile of the underlying layers (e.g., the contact and/or source/drain region). In embodiments, the contact isolation may have a thickness of 20 nm or less, in some examples 10 nm or less, or 5 nm or less. In embodiments, any feature of any embodiment of the first aspect may independently be as correspondingly described for any embodiment of any of the other aspects. In a second aspect, the present disclosure relates to a semiconductor structure for forming a contact isolation for a semiconductor device, comprising: (i) a trench, (ii) a contact abutting a bottom of the trench, and (iii) a sacrificial material infiltrated with a ceramic material filling the bottom of the trench. In embodiments, the semiconductor structure may be obtained after step c of the first aspect. In embodiments, any feature of any embodiment of the second aspect may independently be as correspondingly described for any embodiment of any of the other aspects. The disclosure will now be described by a detailed description of several embodiments of the disclosure. It is clear that other embodiments of the disclosure can be configured according to the knowledge of the person skilled in the art without departing from the true technical teaching of the disclosure, the disclosure being limited only by the terms of the appended claims. Formation of a Contact Isolation for a Semiconductor Device By way of example, the formation of a contact isolation in accordance with the present disclosure for a complementary field-effect transistor (CFET) is described below with reference toFIG.1AandFIG.1B. We now refer to section a ofFIG.1A. An intermediate structure in the formation of the CFET was provided, comprising a Si wafer100, a SiGe region200on the Si wafer100and a Si region110on the SiGe region200; wherein the Si wafer100was for defining therein a first channel of the CFET and the Si region110was for defining therein a second channel of the CFET. The Si region110was overlaid with gate lines300, each covered with a Si3N4gate cap310and flanked with Si3N4gate spacers320. A trench400separated two adjacent gate lines' gate spacers320and penetrated through the Si region110and the SiGe region200, exposing a B-doped embedded SiGe (eSiGe:B) p-doped epitaxial source/drain region500, for the first channel, grown on the Si wafer100. We now refer to section b ofFIG.1A. The trench400was covered with a TiN contact liner (not depicted) and overfilled with W contact metal610, followed by a planarization step (e.g., a chemical-mechanical planarization) stopping on the gate cap310. We now refer to section c ofFIG.1A. The contact liner and contact metal610were etched back using a SF6-based plasma, to obtain a contact600with a targeted thickness (e.g., the thickness of TiN+W over the source/drain region) of 10 nm. We now refer to section d ofFIG.1A. The trench400was overfilled with a sacrificial material700comprising a Lewis basic functional group, such as a spin-on-carbon (SoC) or poly(methyl methacrylate) (PMMA). We now refer to section e ofFIG.1B. The sacrificial material700was etched back using a H2/He-based plasma; the latter providing a relatively slow etching which allows to tightly control the depth of the etch-back and thus the amount of sacrificial material700remaining in the trench400. For instance, the etch-back rate of SoC was lower than 1 nm/s (about eight to ten times slower as compared to using a standard O2-based plasma). We now refer to section f ofFIG.1B. The sacrificial material700was infiltrated with a ceramic material800(e.g., selected from Al2O3, HfO2, ZrO2, TiOx, RuOxor SiO2), using a sequential infiltration synthesis based on a first precursor (e.g., a Lewis acidic metal compound, cf. supra) and a second precursor (e.g., an oxidant; cf. supra). Herein, a non-metal oxide (e.g., SiO2) may be utilized to minimize the contamination risk. We now refer to section f ofFIG.1B. The sacrificial material700was removed using an O2-based plasma treatment, thereby leaving the ceramic material as contact isolation900with a shrunken thickness of about 10 nm. It is to be understood that although example embodiments, specific constructions and configurations, as well as materials, have been discussed herein for devices according to the present disclosure, various changes or modifications in form and detail may be made without departing from the scope and technical teachings of this disclosure. For example, any formulas given above are merely representative of procedures that may be used. Functionality may be added or deleted from the block diagrams and operations may be interchanged among functional blocks. Steps may be added or deleted to methods described within the scope of the present disclosure. While some embodiments have been illustrated and described in detail in the appended drawings and the foregoing description, such illustration and description are to be considered illustrative and not restrictive. Other variations to the disclosed embodiments can be understood and effected in practicing the claims, from a study of the drawings, the disclosure, and the appended claims. The mere fact that certain measures or features are recited in mutually different dependent claims does not indicate that a combination of these measures or features cannot be used. Any reference signs in the claims should not be construed as limiting the scope. | 20,080 |
11862453 | DETAILED DESCRIPTION Typically, a MOSFET is formed by dividing a semiconductor substrate into a plurality of active channel regions—e.g., using shallow trench isolation (STI)—with each active channel region forming the basis of single MOSFET. Source and drain electrodes are formed at opposite ends of the channel, and a gate structure is deposited, spanning the source and drain electrodes and the semiconductor channel material between the electrodes. The gate structure is typically a stack including a dielectric layer in contact with the semiconductor material and with the source and drain electrodes, a work-function metal layer above the dielectric layer (for purposes of this discussion, the semiconductor substrate may be considered the “bottom” of the transistor structure regardless of the orientation of the transistor structure relative to an observer), and a conductive metal gate electrode layer above the work-function metal layer. The work-function metal layer may be, for example, titanium nitride, tantalum nitride, or titanium aluminum carbide. In order to form the gate stack structure, spacers of an insulating or dielectric material (e.g., silicon nitride) may be formed, serving as the walls of a void to be filled with the gate stack materials. The dielectric layer is deposited first, typically using a vapor deposition technique—i.e., chemical vapor deposition (CVD) or physical vapor deposition (PVD). The dielectric layer may be formed directly on the silicon channel layer, or a thin layer of interfacial oxide may first be formed on the silicon layer. The work-function metal layer is then deposited over the dielectric layer (or over the interfacial oxide), again typically using a vapor deposition technique (CVD or PVD). The balance of the void may then be filled with the conductive metal gate electrode layer by CVD, PVD, atomic layer deposition (ALD), or any other suitable deposition technique. Because of the nature of vapor deposition techniques, the dielectric layer and the work-function metal layer are deposited not only at the bottom of the void formed by the spacers, but on the sidewalls of that void as well. Therefore, deposition of the dielectric layer and the work-function metal layer decrease the void volume not only by the thickness of two layers at the bottom of the void, but also by the thicknesses of two layers on each of the sidewalls. Thus, the sidewall-to-sidewall distance is decreased by four layer thicknesses before the conductive metal gate material is deposited. As transistor feature sizes decrease at ever-smaller process nodes, the fraction of the void volume occupied by the dielectric layer and the work-function metal layer increases, decreasing the fraction of that volume available for the conductive metal gate material, and thereby increasing the resistance of the conductive gate electrode. And because the surface area of the conductive metal gate material will be smaller at the top of the gate stack, the contact resistance of the gate will also increase. For example, at a 5-nm process node, the source-to-drain distance may be only 20 nm. With the dielectric layer and the work-function metal layer occupying 2-3 nm each, the void remaining for the conductive metal gate material may have a dimension of only 8-12 nm in the source-to-drain direction. That dimension becomes even smaller at smaller process nodes (e.g., a 3-nm process node) as the source-to-drain distance shrinks but the layer thicknesses remain about the same. However, the sidewall portions of the dielectric layer and the work-function metal layer do not contribute to operation of the transistor. Therefore, in accordance with implementations of the subject matter of this disclosure, the gate stack of a metal gate MOSFET is formed with a higher proportion of the conductive gate metal material, by eliminating the sidewall portions of at least the work-function metal layer. According to a first implementation of the subject matter of this disclosure, the gate stack may be formed as described above, and then the sidewalls of the work-function metal layer, as well as most (or all) of the conductive gate metal material are selectively etched away, leaving the dielectric layer on the bottom and sidewalls, but only the bottom portion of the work-function metal (and possibly a small amount of the conductive gate metal material). Depositing and then etching away the conductive gate metal material, as opposed to not depositing the conductive gate metal material at all, provides a topography which facilitates the selective removal of the work-function metal from the side walls. The void that results within the dielectric layer sidewalls, after the work-function metal is removed from the sidewalls, is then filled with the conductive gate metal material (e.g., aluminum or tungsten). In a variant of this first implementation, the sidewalls of the work-function metal layer may be selectively etched away before any of the conductive gate metal material is deposited. However, the selective etching may be more difficult than when the conductive gate metal material is first deposited and then etched away. According to either variant of the first implementation, the resulting gate structure has a cross section, when viewed perpendicular to the source-to-drain direction, having a U-shaped dielectric layer within the spacers, a work-function metal layer across the bottom of the “U” of the dielectric layer, and a volume of the conductive gate metal material above the work-function metal layer and between the dielectric material sidewalls. The top of the gate stack may be polished using typical techniques such as Chemical-Mechanical Planarization (CMP). According to a second implementation of the subject matter of this disclosure, instead of a using vapor deposition techniques to deposit the dielectric layer and the work-function metal layer, the dielectric layer and the work-function metal layer may be deposited using a deposition technique that provides greater control, so that neither the dielectric layer nor the work-function metal layer is deposited on the sidewalls. For example, atomic-layer deposition (ALD) may be used to deposit the dielectric layer and the work-function metal layer. Alternatively, a pulsed deposition layer (PDL) technique, which provides a degree of control similar to ALD at a speed comparable to vapor deposition techniques, may be used. The result according to this second implementation is that the dielectric layer and the work-function metal layer are formed only at the bottom of the gate-forming void within the spacers, and the remaining void is then filled with the conductive metal gate material (e.g., aluminum or tungsten). Regardless of which implementation is used, the contact area of the conductive metal gate will be larger than for a corresponding structure formed according to typical processes. Therefore, the contact resistance between the gate and any circuit element coupled to the gate will be reduced as compared to the typical structure. The subject matter of this disclosure may be better understood by reference toFIGS.1-4. FIG.1illustrates the various stages in the formation of a transistor gate stack according to the first implementation described above. As of stage101, a MOSFET111has been fully formed according to conventional techniques. Semiconductor substrate121(which forms the active transistor channel) and spacer sidewalls131define a gate space or void141with a cross section that is larger in the dimension normal to substrate121(“height”) than in the dimension parallel to the major plane of substrate121(“width”). Gate space or void141contains, on its “bottom” wall—i.e., the wall adjacent substrate121—and its “side” walls—i.e., the walls formed by spacers131, U-shaped layers of dielectric material151and work-function metal161. The remainder of space or void141is filled with a conductive metal gate material171(e.g., aluminum or tungsten). As of stage102, the originally deposited conductive metal gate material171has been selectively removed. The selective removal may be performed by etching. In some implementations, this etching may be implemented by gas phase etching by chlorine plasma combined with wet etching. In some implementations, all of the conductive metal gate material171may be removed at stage102, but in other implementations, a small amount of the conductive metal gate material171may remain along the bottom wall, as shown at112. As of stage103, the work-function metal161has been selectively removed from the side walls of gate space or void141. Again, the removal of work-function metal161may be performed by etching. The portion112of conductive metal gate material remains, and the now-empty portions of gate space or void141is filled with the conductive metal gate material171at stage104. As discussed above, the result is that a higher proportion of gate space or void141is filled with conductive metal gate material171than in typical transistor gate stack structures. The “top” of this structure can be polished by chemical mechanical planarization (“CMP”). FIG.2illustrates the various stages in the formation of a transistor gate stack according to the second implementation described above. As of stage201, semiconductor substrate221(which forms the active transistor channel) and spacer sidewalls231define a gate space or void241with a cross section that is larger in the dimension normal to substrate221(“height”) than in the dimension parallel to the major plane of substrate221(“width”). The gate space or void241is empty and its “bottom” wall—i.e., the wall adjacent substrate121—is exposed semiconductor substrate221. In some implementations, there may be a thin layer of interfacial oxide—e.g., a silicon oxide—on top of the transistor channel. As of stage202, the dielectric material layer261is selectively grown on top of the exposed semiconductor substrate. The dielectric material may be grown with atomic layer deposition, (“ALD”) or pulsed deposition layer deposition (“PDL”), which is ALD-type step coverage at CVD-type rates leading to high throughput. Selectively growing the dielectric material leads to coverage of the “bottom” wall—i.e., the wall adjacent substrate121—of the gate-space or void241without covering the side walls. As of stage203, the work-function metal271is selectively grown on top of the dielectric material layer261. Again, the work-function metal layer271may be grown with ALD or PDL. Selectively growing the work-function metal271on top of the dielectric material layer261leads to coverage of the “bottom” wall—i.e., the wall adjacent substrate121—of the gate-space or void241on top of the dielectric layer without covering the side walls. As of stage204, the empty portion of the gate space or void241is filled with the conductive metal gate material281. As discussed above, the result is that a higher proportion of gate space or void241is filled with conductive metal gate material281than in typical transistor gate stack structures. As in the implementation ofFIG.1, the top of this structure can be polished by CMP. In order to use a transistor formed in accordance with the implementation ofFIG.1or the implementation ofFIG.2, a gate contact is formed atop the transistor gate stack so that a gate control voltage may be applied.FIG.3illustrates such a gate contact301formed atop the metal gate material171of a transistor formed according to the first implementation described above in connection withFIG.1. Gate contact301will have lower contact resistance than gate contacts in typical transistors as a result of the larger surface area of the conductive metal gate material171at the top of the structure. The same would be even more true in the case of a transistor formed according to the second implementation described above in connection withFIG.2(not shown), because of the even larger surface area of metal gate material281in the absence of dielectric material151. FIG.4is a flow diagram illustrating a method according to implementations of this disclosure for forming a metal gate transistor as described above. At401, a semiconductor channel in a semiconductor substrate is formed. At402, source and drain electrodes are deposited to define a source-to-drain direction of the semiconductor substrate. At403, dielectric spacers are provided above the source electrode and perpendicular to the source-to-drain direction define a gate space, where layers of dielectric material and work-function metal may be deposited on the bottom and side walls at404. The work-function metal is etched away from the side walls at405, and the gate space is filled with conductive metal gate material at406. The top of this structure can be polished by CMP (not shown) before method400ends. Thus it is seen that a transistor having a metal gate with a higher proportion of the conductive gate material, as well as methods for forming such a transistor, have been provided As used herein and in the claims which follow, the construction “one of A and B” shall mean “A or B.” It is noted that the foregoing is only illustrative of the principles of the invention, and that the invention can be practiced by other than the described embodiments, which are presented for purposes of illustration and not of limitation, and the present invention is limited only by the claims which follow. | 13,441 |
11862454 | DETAILED DESCRIPTION OF THE INVENTION Hereinafter, embodiments will be described with reference to drawings. However, the embodiments can be implemented with various modes. It will be readily appreciated by those skilled in the art that modes and details can be changed in various ways without departing from the spirit and scope of the present invention. Thus, the present invention should not be interpreted as being limited to the following description of the embodiments. In the drawings, the size, the layer thickness, or the region is exaggerated for clarity in some cases. Therefore, embodiments of the present invention are not limited to such a scale. Note that the drawings are schematic views showing ideal examples, and embodiments of the present invention are not limited to the shapes or values shown in the drawings. Note that the ordinal numbers such as “first”, “second”, and the like in this specification and the like are used for convenience and do not denote the order of steps or the stacking order of layers. Therefore, for example, description can be made even when “first” is replaced with “second” or “third”, as appropriate. In addition, the ordinal numbers in this specification and the like are not necessarily the same as those which specify one embodiment of the present invention. Note that in this specification, terms for describing arrangement, such as “over”, “above”, “under”, and “below”, are used for convenience in describing a positional relation between components with reference to drawings. Further, the positional relation between components is changed as appropriate in accordance with a direction in which each component is described. Thus, the positional relation is not limited to that described with a term used in this specification and can be explained with another term as appropriate depending on the situation. The “semiconductor device” in this specification and the like means all devices which can operate by utilizing semiconductor characteristics. A semiconductor element such as a transistor, a semiconductor circuit, an arithmetic device, and a memory device are each an embodiment of a semiconductor device. An imaging device, a display device, a liquid crystal display device, a light-emitting device, an electro-optical device, a power generation device (including a thin film solar cell, an organic thin film solar cell, and the like), and an electronic device may each include a semiconductor device. In this specification and the like, a transistor is an element having at least three terminals of a gate, a drain, and a source. In addition, the transistor has a channel region between a drain (a drain terminal, a drain region, or a drain electrode) and a source (a source terminal, a source region, or a source electrode), and current can flow through the drain, the channel region, and the source. Note that in this specification and the like, a channel region refers to a region through which current mainly flows. Further, functions of a source and a drain might be switched when transistors having different polarities are employed or a direction of current flow is changed in circuit operation, for example. Therefore, the terms “source” and “drain” can be switched in this specification and the like. Note that in this specification and the like, the expression “electrically connected” includes the case where components are connected through an “object having any electric function”. There is no particular limitation on an “object having any electric function” as long as electric signals can be transmitted and received between components that are connected through the object. Examples of an “object having any electric function” are a switching element such as a transistor, a resistor, an inductor, a capacitor, and elements with a variety of functions as well as an electrode and a wiring. Note that in this specification and the like, a “silicon oxynitride film” refers to a film that contains oxygen at a higher proportion than nitrogen, and a “silicon nitride oxide film” refers to a film that contains nitrogen at a higher proportion than oxygen. In this specification and the like, the terms “film” and “layer” can be interchanged with each other depending on the case or circumstances. For example, the term “conductive layer” can be changed into the term “conductive film” in some cases. Also, the term “insulating film” can be changed into the term “insulating layer” in some cases. In this specification, the term “parallel” indicates that the angle formed between two straight lines is greater than or equal to −10° and less than or equal to 10°, and accordingly also includes the case where the angle is greater than or equal to −5° and less than or equal to 5°. The term “substantially parallel” indicates that the angle formed between two straight lines is greater than or equal to −30° and less than or equal to 30°. The term “perpendicular” indicates that the angle formed between two straight lines is greater than or equal to 80° and less than or equal to 100°, and accordingly also includes the case where the angle is greater than or equal to 85° and less than or equal to 95°. The term “substantially perpendicular” indicates that the angle formed between two straight lines is greater than or equal to 60° and less than or equal to 120°. Embodiment 1 In this embodiment, a semiconductor device of one embodiment of the present invention will be described with reference toFIGS.1A to1C,FIG.2,FIGS.3A to3C,FIGS.4A to4C, FIGS.5A to5C,FIGS.6A to6D,FIGS.7A and7B,FIGS.8A to8C,FIGS.9A to9C,FIGS.10A and10B,FIGS.11A to11C,FIGS.12A to12C,FIGS.13A and13B,FIGS.14A to14D,FIGS.15A to15D,FIGS.16A and16B,FIGS.17A and17B, andFIGS.18A to18D. Structural Example 1 of Semiconductor Device FIG.1Ais a top view of a transistor100that is a semiconductor device of one embodiment of the present invention.FIG.1Bis a cross-sectional view taken along the dashed dotted line X1-X2inFIG.1A, andFIG.1Cis a cross-sectional view taken along the dashed dotted line Y1-Y2inFIG.1A. Note that inFIG.1A, some components of the transistor100(e.g., an insulating film serving as a gate insulating film) are not illustrated to avoid complexity. The direction of the dashed dotted line X1-X2may be called a channel length direction of the transistor, and the direction of the dashed dotted line Y1-Y2may be called a channel width direction of the transistor. As inFIG.1A, some components might not be illustrated in some top views of transistors described below. The transistor100includes a conductive film104functioning as a gate electrode over a substrate102, an insulating film106over the substrate102and the conductive film104, an insulating film107over the insulating film106, an oxide semiconductor film108over the insulating film107, a conductive film112afunctioning as a source electrode electrically connected to the oxide semiconductor film108, and a conductive film112bfunctioning as a drain electrode electrically connected to the oxide semiconductor film108. The transistor100also includes insulating films114and116over the oxide semiconductor film108and the conductive films112aand112b, a metal oxide film132over the insulating film116, and a metal oxide film134over the metal oxide film132. The metal oxide film132contains at least one metal element that is the same as a metal element contained in the oxide semiconductor film108. The metal oxide film134includes a region where the metal oxide film134is mixed with the metal oxide film132. In some cases, the insulating films106and107are collectively referred to as a first insulating film, and the first insulating film has a function of a gate insulating film of the transistor100. In some cases, the insulating films114and116are collectively referred to as a second insulating film, and the second insulating film has a function of supplying oxygen to the oxide semiconductor film108. When impurities such as hydrogen or moisture enters the oxide semiconductor film108in the transistor100, the impurities are bonded to oxygen vacancies formed in the oxide semiconductor film108, producing electrons serving as carriers. The carriers due to the impurities tend to make the transistor100be normally on. Therefore, for stable transistor characteristics, it is important to reduce impurities such as hydrogen or moisture in the oxide semiconductor film108and to reduce oxygen vacancies in the oxide semiconductor film108. Then, in the structure of the transistor of one embodiment of the present invention, excess oxygen is introduced into an insulating film over the oxide semiconductor film108, here, the insulating films114and116over the oxide semiconductor film108, whereby oxygen is moved from the insulating films114and116to the oxide semiconductor film108to fill oxygen vacancies in the oxide semiconductor film108. However, in some cases, oxygen introduced into the insulating films114and116is diffused to the outside by heat treatment during the manufacturing process of the transistor100, and cannot be favorably moved to the oxide semiconductor film108. However, in the semiconductor device of one embodiment of the present invention, the metal oxide films132and134are provided in an upper portion of the transistor100, specifically, over the insulating film116. The provision of the metal oxide films132and134can inhibit outward diffusion of oxygen from the insulating films114and116. In addition, the provision of the metal oxide films132and134can inhibit entry of impurities (e.g., hydrogen and water) from the outside. Being provided with excess oxygen, the insulating films114and116each include a region containing oxygen in excess of that in the stoichiometric composition (oxygen excess region). In other words, the insulating films114and116are insulating films capable of releasing oxygen. The oxygen excess region is formed in the insulating films114and116in such a manner that oxygen is introduced into the insulating films114and116after the deposition, for example. Oxygen can be introduced by a method in which acceleration energy is applied to an oxygen gas under reduced pressure, specifically, an ion implantation method, an ion doping method, a plasma immersion ion implantation method, plasma treatment, or the like. When oxygen is introduced, a substrate is preferably heated because a larger amount of oxygen can be introduced. The substrate temperature at the time when oxygen is introduced is preferably higher than room temperature and lower than 350° C., for example. For the above plasma treatment, an apparatus with which an oxygen gas is made to be plasma by high-frequency power (also referred to as a plasma etching apparatus or a plasma ashing apparatus) is preferably used. The amount of released oxygen can be found by measuring an insulating film by thermal desorption spectroscopy (TDS). For example, the amount of released oxygen molecules from the insulating films114and116is more than or equal to 8.0×1014/cm2, preferably more than or equal to 1.0×1015/cm2, and further preferably more than or equal to 1.5×1015/cm2 by TDS. Note that the surface temperature of the films in TDS is higher than or equal to 100° C. and lower than or equal to 700° C., preferably higher than or equal to 100° C. and lower than or equal to 500° C. In one embodiment of the present invention, in order to form an oxygen-excess region in the insulating films114and116, the metal oxide film132is formed over the insulating film116and oxygen is introduced into the insulating films114and116through the metal oxide film132. Therefore, the metal oxide film132preferably has a function of allowing oxygen to pass through. Introducing oxygen through the metal oxide film132into the insulating films114and116enables favorable introduction of oxygen into the insulating films114and116. Furthermore, the metal oxide film132has a function of inhibiting oxygen from being released outside except during the introduction of oxygen. The metal oxide film132may contain at least a metal element that is also contained in the oxide semiconductor film108, for example. When the metal oxide film132is formed using a material containing indium, oxygen can be favorably introduced into the insulating films114and116. Examples of a material containing indium that can be used for the metal oxide film132include indium oxide containing tungsten oxide, indium zinc oxide containing tungsten oxide, indium oxide containing titanium oxide, indium tin oxide containing titanium oxide, indium tin oxide (ITO), indium zinc oxide, and indium tin oxide containing silicon (ITSO). Note that the above indium-containing materials are conductive materials with light-transmitting properties. Among the above materials, it is particularly preferable to use ITSO for the metal oxide film132because ITSO can be deposited over an insulating film having roughness or the like with favorable coverage. In one embodiment of the present invention, the metal oxide film134is provided over the metal oxide film132. The provision of the metal oxide film134can further inhibit oxygen in the insulating films114and116from diffusing to the outside. When the metal oxide film134is formed using a material containing aluminum, outward diffusion of oxygen from the insulating films114and116and/or entry of impurities (e.g., hydrogen and water) from the outside can be suppressed. Examples of a material containing aluminum that can be used for the metal oxide film134include aluminum oxide. There is a region in which the metal oxide film132and the metal oxide film134are mixed. Here, the region in which the metal oxide film132and the metal oxide film134are mixed will be described with reference toFIG.2. FIG.2is a cross-sectional view of a stacked structure including the oxide semiconductor film108, the insulating films114and116, and the metal oxide films132and134. A mixed region136is formed near an interface between the metal oxide film132and the metal oxide film134. The thickness of the mixed region136is greater than or equal to 1 nm and less than or equal to 10 nm, preferably greater than or equal to 1 nm and less than or equal to 3 nm. In the case where the metal oxide film132is formed of a conductive material and the metal oxide film134is formed of an insulating material, for example, the formation of the mixed region136can reduce the conductivity of the metal oxide film132. Furthermore, the formation of the mixed region136in the entire region of the metal oxide film132can make the metal oxide film132electrically insulated. The mixed region136can be formed, for example, when the metal oxide film134is formed by a sputtering method and the sputtered atoms get into the metal oxide film132. Alternatively, the mixed region136can be formed by thermodiffusion near the interface between the metal oxide film132and the metal oxide film134, when the metal oxide film134is formed over the metal oxide film132and then the metal oxide films are subjected to heat treatment (at a temperature of 100° C. or higher and 350° C. or lower, for example). The provision of the insulating films114and116over the oxide semiconductor film108in the above manner makes it possible to move oxygen in the insulating films114and116to the oxide semiconductor film108, whereby oxygen vacancies formed in the oxide semiconductor film108can be filled. Furthermore, the provision of the metal oxide films132and134over the insulating film116can inhibit oxygen in the insulating films114and116from diffusing to the outside. The provision of the metal films132and134over the insulating film116can also inhibit entry of impurities from the outside. Thus, a novel semiconductor device with high reliability, in which oxygen vacancies in the oxide semiconductor film108are filled and entry of impurities is inhibited, can be provided. Constituent elements of the semiconductor device of this embodiment will be described below in detail. <Substrate> There is no particular limitation on the property of a material and the like of the substrate102as long as the material has heat resistance high enough to withstand at least heat treatment to be performed later. For example, a glass substrate, a ceramic substrate, a quartz substrate, a sapphire substrate, or the like may be used as the substrate102. Alternatively, a single crystal semiconductor substrate or a polycrystalline semiconductor substrate made of silicon, silicon carbide, or the like, a compound semiconductor substrate made of silicon germanium or the like, an SOI (silicon on insulator) substrate, or the like may be used as the substrate102. In the case where a glass substrate is used as the substrate102, a glass substrate having any of the following sizes can be used: the 6th generation (1500 mm×1850 mm), the 7th generation (1870 mm×2200 mm), the 8th generation (2200 mm×2400 mm), the 9th generation (2400 mm×2800 mm), and the 10th generation (2950 mm×3400 mm). Thus, a large-sized display device can be manufactured. Alternatively, a flexible substrate may be used as the substrate102, and the transistor100may be provided directly on the flexible substrate. Alternatively, a separation layer may be provided between the substrate102and the transistor100. The separation layer can be used when part or the whole of a semiconductor device formed over the separation layer is separated from the substrate102and transferred onto another substrate. In such a case, the transistor100can be transferred to a substrate having low heat resistance or a flexible substrate as well. <Conductive Film> The conductive film104functioning as a gate electrode and the conductive films112aand112bfunctioning as a source electrode and a drain electrode, respectively, can each be formed using a metal element selected from chromium (Cr), copper (Cu), aluminum (Al), gold (Au), silver (Ag), zinc (Zn), molybdenum (Mo), tantalum (Ta), titanium (Ti), tungsten (W), manganese (Mn), nickel (Ni), iron (Fe), and cobalt (Co); an alloy containing any of these metal element as its component; an alloy including a combination of any of these metal elements; or the like. Furthermore, each of the conductive films104,112a, and112bmay have a single-layer structure or a stacked-layer structure of two or more layers. For example, a single-layer structure of an aluminum film containing silicon, a two-layer structure in which a titanium film is stacked over an aluminum film, a two-layer structure in which a titanium film is stacked over a titanium nitride film, a two-layer structure in which a tungsten film is stacked over a titanium nitride film, a two-layer structure in which a tungsten film is stacked over a tantalum nitride film or a tungsten nitride film, a three-layer structure in which a titanium film, an aluminum film, and a titanium film are stacked in this order, and the like can be given. Alternatively, an alloy film or a nitride film which contains aluminum and one or more elements selected from titanium, tantalum, tungsten, molybdenum, chromium, neodymium, and scandium may be used. The conductive films104,112a, and112bcan be formed using a light-transmitting conductive material such as indium tin oxide, indium oxide containing tungsten oxide, indium zinc oxide containing tungsten oxide, indium oxide containing titanium oxide, indium tin oxide containing titanium oxide, indium zinc oxide, or indium tin oxide to which silicon oxide is added. A Cu—X alloy film (X is Mn, Ni, Cr, Fe, Co, Mo, Ta, or Ti) may be used for the conductive films104,112a, and112b. The use of a Cu—X alloy film enables the manufacturing cost to be reduced because wet etching process can be used in the processing. <Gate Insulating Film> As each of the insulating films106and107functioning as a gate insulating film of the transistor100, an insulating layer including at least one of the following films formed by a plasma enhanced chemical vapor deposition (PECVD) method, a sputtering method, or the like can be used: a silicon oxide film, a silicon oxynitride film, a silicon nitride oxide film, a silicon nitride film, an aluminum oxide film, a hafnium oxide film, an yttrium oxide film, a zirconium oxide film, a gallium oxide film, a tantalum oxide film, a magnesium oxide film, a lanthanum oxide film, a cerium oxide film, and a neodymium oxide film. Note that instead of a stacked structure of the insulating films106and107, an insulating film of a single layer formed using a material selected from the above or an insulating film including three or more stacked layers may be used. Note that the insulating film107that is in contact with the oxide semiconductor film108functioning as a channel region of the transistor100is preferably an oxide insulating film and preferably includes a region including oxygen in excess of the stoichiometric composition (oxygen-excess region). In other words, the insulating film107is an insulating film which is capable of releasing oxygen. In order to provide the oxygen excess region in the insulating film107, the insulating film107is formed in an oxygen atmosphere, for example. Alternatively, the oxygen excess region may be formed by introduction of oxygen into the insulating film107after the deposition. In the case where hafnium oxide is used for the insulating film107, the following effect is attained. Hafnium oxide has a higher dielectric constant than silicon oxide and silicon oxynitride. Therefore, by using hafnium oxide, the thickness of the insulating film107can be made large as compared with the case where silicon oxide is used; thus, leakage current due to tunnel current can be low. That is, it is possible to provide a transistor with a low off-state current. Moreover, hafnium oxide with a crystalline structure has higher dielectric constant than hafnium oxide with an amorphous structure. Therefore, it is preferable to use hafnium oxide with a crystalline structure in order to obtain a transistor with a low off-state current. Examples of the crystalline structure include a monoclinic crystal structure and a cubic crystal structure. Note that one embodiment of the present invention is not limited to the above examples. In this embodiment, a silicon nitride film is formed as the insulating film106, and a silicon oxide film is formed as the insulating film107. A silicon nitride film has a higher dielectric constant than a silicon oxide film and needs a larger thickness for capacitance equivalent to that of a silicon oxide film Thus, when a silicon nitride film is included in the gate insulating film of the transistor100, the physical thickness of the insulating film can be increased. This makes it possible to suppress a decrease in withstand voltage of the transistor100and furthermore to increase the withstand voltage, thereby inhibiting electrostatic breakdown of the transistor100. <Oxide Semiconductor Film> The oxide semiconductor film108contains In, Zn, and M (M is Ti, Ga, Y, Zr, La, Ce, Nd, Sn, or Hf). Typically, In—Ga oxide, In—Zn oxide, or In-M-Zn oxide can be used for the oxide semiconductor film108. It is particularly preferable to use In-M-Zn oxide for the semiconductor film108. In the case where the oxide semiconductor film108includes In-M-Zn oxide, it is preferable that the atomic ratio of metal elements of a sputtering target used for forming the In-M-Zn oxide satisfy In M and Zn M As the atomic ratio of metal elements of such a sputtering target, In:M:Zn=1:1:1, In:M:Zn=1:1:1.2, In:M:Zn=2:1:3, In:M:Zn=3:1:2, and In:M:Zn=4:2:4.1 are preferable. Note that the atomic ratio of metal elements in the formed oxide semiconductor film108vary from the above atomic ratio of metal elements of the sputtering target within a range of ±40% as an error. For example, when a sputtering target with an atomic ratio of In to Ga and Zn of 4:2:4.1 is used, the atomic ratio of In to Ga and Zn in the oxide semiconductor film108may be 4:2:3 or in the vicinity of 4:2:3. Note that in the case where the oxide semiconductor film108is formed of In-M-Zn oxide, the proportion of In and the proportion of M, not taking Zn and O into consideration, are preferably greater than 25 atomic % and less than 75 atomic %, respectively, and more preferably greater than 34 atomic % and less than 66 atomic %, respectively. The energy gap of the oxide semiconductor film108is 2 eV or more, preferably 2.5 eV or more, further preferably 3 eV or more. With the use of an oxide semiconductor having such a wide energy gap, the off-state current of the transistor100can be reduced. The thickness of the oxide semiconductor film108is greater than or equal to 3 nm and less than or equal to 200 nm, preferably greater than or equal to 3 nm and less than or equal to 100 nm, further preferably greater than or equal to 3 nm and less than or equal to 50 nm. An oxide semiconductor film with low carrier density is used as the oxide semiconductor film108. For example, the carrier density of the oxide semiconductor film108is greater than or equal to 1×10−9/cm3and less than 8×1011/cm3, preferably greater than or equal to 1×10−9/cm3and less than 1×1011/cm3, further preferably greater than or equal to 1×10−9/cm3and less than 1×1010/cm3. Note that, without limitation to the compositions and materials described above, a material with an appropriate composition may be used in accordance with required semiconductor characteristics and electrical characteristics (e.g., field-effect mobility and threshold voltage) of a transistor. Further, in order to obtain required semiconductor characteristics of a transistor, it is preferable that the carrier density, the impurity concentration, the defect density, the atomic ratio of a metal element to oxygen, the interatomic distance, the density, and the like of the oxide semiconductor film108be set to be appropriate. Note that it is preferable to use, as the oxide semiconductor film108, an oxide semiconductor film in which the impurity concentration is low and density of defect states is low, in which case the transistor can have more excellent electrical characteristics. Here, the state in which impurity concentration is low and density of defect states is low (the number of oxygen vacancies is small) is referred to as “highly purified intrinsic” or “substantially highly purified intrinsic”. A highly purified intrinsic or substantially highly purified intrinsic oxide semiconductor film has few carrier generation sources, and thus can have a low carrier density. Thus, a transistor in which a channel region is formed in the oxide semiconductor film rarely has a negative threshold voltage (is rarely normally on). A highly purified intrinsic or substantially highly purified intrinsic oxide semiconductor film has a low density of defect states and accordingly has a low density of trap states in some cases. Further, a highly purified intrinsic or substantially highly purified intrinsic oxide semiconductor film has an extremely low off-state current; even when an element has a channel width of 1×106 μm and a channel length (L) of 10 μm, the off-state current can be less than or equal to the measurement limit of a semiconductor parameter analyzer, i.e., less than or equal to 1×10−13 A, at a voltage (drain voltage) between a source electrode and a drain electrode of from 1 V to 10 V. Accordingly, the transistor in which the channel region is formed in the highly purified intrinsic or substantially highly purified intrinsic oxide semiconductor film can have a small variation in electrical characteristics and high reliability. Charges trapped by the trap states in the oxide semiconductor film take a long time to be released and may behave like fixed charges. Thus, the transistor whose channel region is formed in the oxide semiconductor film having a high density of trap states has unstable electrical characteristics in some cases. As examples of the impurities, hydrogen, nitrogen, alkali metal, alkaline earth metal, and the like are given. Hydrogen contained in the oxide semiconductor film108reacts with oxygen bonded to a metal atom to be water, and also causes an oxygen vacancy in a lattice from which oxygen is released (or a portion from which oxygen is released). Due to entry of hydrogen into the oxygen vacancy, an electron serving as a carrier is generated in some cases. Furthermore, in some cases, bonding of part of hydrogen to oxygen bonded to a metal atom causes generation of an electron serving as a carrier. Thus, a transistor including an oxide semiconductor film that contains hydrogen is likely to be normally on. For this reason, it is preferable that hydrogen be reduced as much as possible in the oxide semiconductor film108. Specifically, the hydrogen concentration in the oxide semiconductor film108, which is measured by secondary ion mass spectrometry (SIMS), is lower than or equal to 2×1020atoms/cm3, preferably lower than or equal to 5×1019atoms/cm3, further preferably lower than or equal to 1×1019atoms/cm3, still further preferably lower than or equal to 5×1018atoms/cm3, yet further preferably lower than or equal to 1×1018atoms/cm3, even further preferably lower than or equal to 5×1017atoms/cm3, or further preferably lower than or equal to 1×1016atoms/cm3. When silicon or carbon that is one of elements belonging to Group 14 is contained in the oxide semiconductor film108, oxygen vacancies are increased in the oxide semiconductor film108, and the oxide semiconductor film108becomes an n-type film. Thus, the concentration of silicon or carbon (the concentration is measured by SIMS) in the oxide semiconductor film108or the concentration of silicon or carbon (the concentration is measured by SIMS) in the vicinity of an interface with the oxide semiconductor film108is set to be lower than or equal to 2×1018 atoms/cm3, preferably lower than or equal to 2×1017 atoms/cm3. In addition, the concentration of alkali metal or alkaline earth metal of the oxide semiconductor film108, which is measured by SIMS, is set to be lower than or equal to 1×1018 atoms/cm3, preferably lower than or equal to 2×1016 atoms/cm3. Alkali metal and alkaline earth metal might generate carriers when bonded to an oxide semiconductor, in which case the off-state current of the transistor might be increased. Therefore, it is preferable to reduce the concentration of alkali metal or alkaline earth metal of the oxide semiconductor film108. Further, when containing nitrogen, the oxide semiconductor film108easily becomes n-type by generation of electrons serving as carriers and an increase of carrier density. Thus, a transistor including an oxide semiconductor film that contains nitrogen is likely to have normally-on characteristics. For this reason, nitrogen in the oxide semiconductor film is preferably reduced as much as possible; the concentration of nitrogen which is measured by SIMS is preferably set, for example, lower than or equal to 5×1018 atoms/cm3. The oxide semiconductor film108may have a non-single-crystal structure, for example. The non-single-crystal structure includes, for example, a CAAC-OS described later, a polycrystalline structure, an nc-OS, an a-like OS, and an amorphous structure. Among the non-single-crystal structure, the amorphous structure has the highest density of defect states, whereas CAAC-OS has the lowest density of defect states. The oxide semiconductor film108may have an amorphous structure, for example. The oxide semiconductor films having the amorphous structure each have disordered atomic arrangement and no crystalline component, for example. Alternatively, the oxide films having an amorphous structure have, for example, an absolutely amorphous structure and no crystal part. Note that the oxide semiconductor film108may be a mixed film including two or more of the following: a region having an amorphous structure, a region having a microcrystalline structure, a region having a polycrystalline structure, a region of CAAC-OS, and a region having a single-crystal structure. The mixed film has a single-layer structure including, for example, two or more of a region having an amorphous structure, a region having a microcrystalline structure, a region having a polycrystalline structure, a CAAC-OS region, and a region having a single-crystal structure in some cases. Furthermore, in some cases, the mixed film has a stacked-layer structure including two or more of a region having an amorphous structure, a region having a microcrystalline structure, a region having a polycrystalline structure, a CAAC-OS region, and a region having a single-crystal structure. <Protective Insulating Film> The insulating films114and116have a function of a protective insulating film. The insulating films114and116contain oxygen. Furthermore, the insulating film114is an insulating film that allows oxygen to pass through. Note that the insulating film114also functions as a film that relieves damage to the oxide semiconductor film108at the time of forming the insulating film116in a later step. A silicon oxide film, a silicon oxynitride film, or the like with a thickness greater than or equal to 5 nm and less than or equal to 150 nm, preferably greater than or equal to 5 nm and less than or equal to 50 nm can be used as the oxide insulating film114. In addition, it is preferable that the number of defects in the insulating film114be small and typically, the spin density corresponding to a signal that appears at g=2.001 due to a dangling bond of silicon be lower than or equal to 3×1017 spins/cm3 by electron spin resonance (ESR) measurement. This is because if the density of defects in the insulating film114is high, oxygen is bonded to the defects and the amount of oxygen that passes through the insulating film114is decreased. Note that not all oxygen entering the insulating film114from the outside move to the outside of the insulating film114and some oxygen remains in the insulating film114. Furthermore, movement of oxygen occurs in the insulating film114in some cases in such a manner that oxygen enters the insulating film114and oxygen contained in the insulating film114moves to the outside of the insulating film114. When an oxide insulating film that allows oxygen to pass through is formed as the insulating film114, oxygen released from the insulating film116provided over the insulating film114can be moved to the oxide semiconductor film108through the insulating film114. The insulating film114can be formed using an oxide insulating film having a low density of states due to nitrogen oxide. Note that the density of states due to nitrogen oxide can be formed between the energy of the valence band maximum (Ev_os) and the energy of the conduction band minimum (Ec_os) of the oxide semiconductor film. A silicon oxynitride film that releases less nitrogen oxide, an aluminum oxynitride film that releases less nitrogen oxide, and the like can be used as the above oxide insulating film. Note that a silicon oxynitride film that releases a small amount of nitrogen oxide is a film of which the amount of released ammonia is larger than the amount of released nitrogen oxide in thermal desorption spectroscopy analysis; the amount of released ammonia is typically greater than or equal to 1×1018/cm3 and less than or equal to 5×1019/cm3. Note that the amount of released ammonia is the amount of ammonia released by heat treatment with which the surface temperature of the film becomes a temperature higher than or equal to 50° C. and lower than or equal to 650° C., or preferably higher than or equal to 50° C. and lower than or equal to 550° C. Nitrogen oxide (NOx; x is greater than 0 and less than or equal to 2, preferably greater than or equal to 1 and less than or equal to 2), typically NO2or NO, forms levels in the insulating film114, for example. The level is positioned in the energy gap of the oxide semiconductor film108. Therefore, when nitrogen oxide is diffused to the vicinity of the interface between the insulating film114and the oxide semiconductor film108, an electron is in some cases trapped by the level on the insulating film114side. As a result, the trapped electron remains in the vicinity of the interface between the insulating film114and the oxide semiconductor film108; thus, the threshold voltage of the transistor is shifted in the positive direction. Nitrogen oxide reacts with ammonia and oxygen in heat treatment. Since nitrogen oxide contained in the insulating film114reacts with ammonia contained in the insulating film116in heat treatment, nitrogen oxide contained in the insulating film114is reduced. Therefore, an electron is hardly trapped at the vicinity of the interface between the insulating film114and the oxide semiconductor film108. By using such an oxide insulating film, the insulating film114can reduce the shift in the threshold voltage of the transistor, which leads to a smaller change in the electrical characteristics of the transistor. Note that in an ESR spectrum at 100 K or lower of the insulating film114, by heat treatment of a manufacturing process of the transistor, typically heat treatment at a temperature higher than or equal to 300° C. and lower than the strain point of the substrate, a first signal that appears at a g-factor of greater than or equal to 2.037 and less than or equal to 2.039, a second signal that appears at a g-factor of greater than or equal to 2.001 and less than or equal to 2.003, and a third signal that appears at a g-factor of greater than or equal to 1.964 and less than or equal to 1.966 are observed. The split width of the first and second signals and the split width of the second and third signals that are obtained by ESR measurement using an X-band are each approximately 5 mT. The sum of the spin densities of the first signal that appears at a g-factor of greater than or equal to 2.037 and less than or equal to 2.039, the second signal that appears at a g-factor of greater than or equal to 2.001 and less than or equal to 2.003, and the third signal that appears at a g-factor of greater than or equal to 1.964 and less than or equal to 1.966 is lower than 1×1018 spins/cm3, typically higher than or equal to 1×1017 spins/cm3 and lower than 1×1018 spins/cm3. In the ESR spectrum at 100 K or lower, the first signal that appears at a g-factor of greater than or equal to 2.037 and less than or equal to 2.039, the second signal that appears at a g-factor of greater than or equal to 2.001 and less than or equal to 2.003, and the third signal that appears at a g-factor of greater than or equal to 1.964 and less than or equal to 1.966 correspond to signals attributed to nitrogen oxide (NOx; x is greater than or equal to 0 and less than or equal to 2, preferably greater than or equal to 1 and less than or equal to 2). Typical examples of nitrogen oxide include nitrogen monoxide and nitrogen dioxide. In other words, the lower the total spin density of the first signal that appears at a g-factor of greater than or equal to 2.037 and less than or equal to 2.039, the second signal that appears at a g-factor of greater than or equal to 2.001 and less than or equal to 2.003, and the third signal that appears at a g-factor of greater than or equal to 1.964 and less than or equal to 1.966 is, the smaller amount of nitrogen oxide the oxide insulating film contains. The concentration of nitrogen of the above oxide insulating film measured by SIMS is lower than or equal to 6×1020 atoms/cm3. The above oxide insulating film is formed by a PECVD method at a substrate temperature higher than or equal to 220° C., higher than or equal to 280° C., or higher than or equal to 350° C. using silane and dinitrogen monoxide, whereby a dense and hard film can be formed. The insulating film116is formed using an oxide insulating film that contains oxygen at a higher proportion than oxygen in the stoichiometric composition. Part of oxygen is released by heating from the oxide insulating film containing more oxygen than that in the stoichiometric composition. The oxide insulating film containing oxygen in excess of that in the stoichiometric composition is an oxide insulating film of which the amount of released oxygen converted into oxygen atoms is greater than or equal to 8.0×1014atoms/cm2, preferably greater than or equal to 1.0×1015atoms/cm2in TDS. Note that the temperature of the film surface in the TDS is higher than or equal to 100° C. and lower than or equal to 700° C., preferably higher than or equal to 100° C. and lower than or equal to 500° C. A silicon oxide film, a silicon oxynitride film, or the like with a thickness greater than or equal to 30 nm and less than or equal to 500 nm, preferably greater than or equal to 50 nm and less than or equal to 400 nm can be used as the insulating film116. It is preferable that the amount of defects in the insulating film116be small, and typically the spin density corresponding to a signal which appears at g=2.001 due to a dangling bond of silicon, be lower than 1.5×1018 spins/cm3, more preferably lower than or equal to 1×1018 spins/cm3 by ESR measurement. Note that the insulating film116is provided more apart from the oxide semiconductor film108than the insulating film114is; thus, the insulating film116may have higher defect density than the insulating film114. Further, the insulating films114and116can be formed using insulating films formed of the same kinds of materials; thus, a boundary between the insulating films114and116cannot be clearly observed in some cases. Thus, in this embodiment, the boundary between the insulating films114and116is shown by a dashed line. Although a two-layer structure of the insulating films114and116is described in this embodiment, the present invention is not limited to this structure. For example, a single-layer structure of either one of the insulating films114and116may be employed. <Metal Oxide Film> The metal oxide film132has a function of allowing oxygen to pass through. The provision of the metal oxide film132makes it possible to introduce oxygen favorably into the insulating films114and116. Furthermore, the metal oxide film132has a function of inhibiting release of oxygen except during the introduction of oxygen. The metal oxide film132contains at least one metal element that is the same as one of those contained in the oxide semiconductor film108. In the case where the oxide semiconductor film108contains In, Zn, and M (M is Ti, Ga, Y, Zr, La, Ce, Nd, Sn, or Hf), for example, the metal oxide film132contains In, Zn, or M It is particularly preferable that the metal oxide film132be a conductive film containing In or a semiconductor film containing In. The metal oxide film134has a function of inhibiting release of oxygen and a function of blocking impurities such as oxygen, hydrogen, water, alkali metal, and alkaline earth metal. The provision of the metal oxide film134makes it possible to inhibit outward diffusion of oxygen from the oxide semiconductor film108, outward diffusion of oxygen contained in the insulating films114and116, and entry of hydrogen, water, or the like into the oxide semiconductor film108from the outside. It is preferable that the metal oxide film134contain aluminum (Al), gallium (Ga), yttrium (Y), or hafnium (Hf). Examples of a material that can be used for the metal oxide film134include aluminum oxide, aluminum oxynitride, aluminum nitride oxide, gallium oxide, gallium oxynitride, gallium nitride oxide, yttrium oxide, yttrium oxynitride, yttrium nitride oxide, hafnium oxide, hafnium oxynitride, and hafnium nitride oxide. It is particularly preferable to use aluminum oxide for the metal oxide film134, in which case outward diffusion of oxygen from the oxide semiconductor film108and the insulating films114and116and entry of hydrogen, water, or the like into the oxide semiconductor film108from the outside can be inhibited. It is preferable to form the metal oxide film134by a sputtering method or an atomic layer deposition (ALD) method. Note that the above-described various films such as the conductive film, the insulating film, the oxide semiconductor film, and the metal oxide film can be formed by a sputtering method, a chemical vapor deposition (CVD) method, a vacuum evaporation method, a pulsed laser deposition (PLD) method, or the like. Alternatively, the above-described various films such as the conductive film, the insulating film, and the oxide semiconductor film can be formed by a plasma enhanced chemical vapor deposition (PECVD) method, a thermal CVD method, or an ALD method. As an example of a thermal CVD method, a metal organic chemical vapor deposition (MOCVD) method can be given. Further alternatively, the above-described various films such as the conductive film, the insulating film, the oxide semiconductor film, and the metal oxide film can be formed by a coating method or a printing method. A thermal CVD method has an advantage that no defect due to plasma damage is generated since it does not utilize plasma for forming a film. Deposition by a thermal CVD method may be performed in such a manner that a source gas and an oxidizer are supplied to a chamber at a time while the pressure in the chamber is set to an atmospheric pressure or a reduced pressure, and the source gas and the oxidizer react with each other in the vicinity of the substrate or over the substrate. Deposition by an ALD method may be performed in such a manner that the pressure in a chamber is set to an atmospheric pressure or a reduced pressure, source gases for reaction are sequentially introduced into the chamber, and then the sequence of the gas introduction is repeated. For example, two or more kinds of source gases are sequentially supplied to the chamber by switching respective switching valves (also referred to as high-speed valves). For example, a first source gas is introduced, an inert gas (e.g., argon or nitrogen) or the like is introduced at the same time as or after the introduction of the first gas so that the source gases are not mixed, and then a second source gas is introduced. Note that in the case where the first source gas and the inert gas are introduced at a time, the inert gas serves as a carrier gas, and the inert gas may also be introduced at the same time as the introduction of the second source gas. Alternatively, the first source gas may be exhausted by vacuum evacuation instead of the introduction of the inert gas, and then the second source gas may be introduced. The first source gas is adsorbed on the surface of the substrate to form a first layer; then the second source gas is introduced to react with the first layer; as a result, a second layer is stacked over the first layer, so that a thin film is formed. The sequence of the gas introduction is repeated plural times until a desired thickness is obtained, whereby a thin film with excellent step coverage can be formed. The thickness of the thin film can be adjusted by the number of repetition times of the sequence of the gas introduction; therefore, an ALD method makes it possible to accurately adjust the film thickness and thus is suitable for manufacturing a minute FET. The above-described variety of films such as the conductive film, the insulating film, the oxide semiconductor film, and the metal oxide film in this embodiment can be formed by an ALD method or a thermal CVD method such as an MOCVD method. For example, in the case where an In—Ga—Zn—O film is formed, trimethylindium, trimethylgallium, and dimethylzinc are used. Note that the chemical formula of trimethylindium is In(CH3)3. The chemical formula of trimethylgallium is Ga(CH3)3. The chemical formula of dimethylzinc is Zn(CH3)2. Without limitation to the above combination, triethylgallium (chemical formula: Ga(C2H5)3) can be used instead of trimethylgallium, and diethylzinc (chemical formula: Zn(C2H5)2) can be used instead of dimethylzinc. For example, in the case where a hafnium oxide film is formed with a deposition apparatus employing ALD, two kinds of gases, i.e., ozone (O3) as an oxidizer and a source gas which is obtained by vaporizing liquid containing a solvent and a hafnium precursor compound (hafnium alkoxide or hafnium amide such as tetrakis(dimethylamide)hafnium (TDMAH)) are used. Note that the chemical formula of tetrakis(dimethylamide)hafnium is Hf[N(CH3)2]4. Examples of another material liquid include tetrakis(ethylmethylamide)hafnium. For example, in the case where an aluminum oxide film is formed with a deposition apparatus employing ALD, two kinds of gases, i.e., H2O as an oxidizer and a source gas which is obtained by vaporizing liquid containing a solvent and an aluminum precursor compound (e.g., trimethylaluminum (TMA)) are used. Note that the chemical formula of trimethylaluminum is Al(CH3)3. Examples of another material liquid include tris(dimethylamide)aluminum, triisobutylaluminum, and aluminum tris(2,2,6,6-tetramethyl-3,5-heptanedionate). For example, in the case where a silicon oxide film is formed with a deposition apparatus employing ALD, hexachlorodisilane is adsorbed on the surface where a film is to be formed, chlorine contained in the adsorbate is removed, and radicals of an oxidizing gas (e.g., O2or dinitrogen monoxide) are supplied to react with the adsorbate. For example, in the case where a tungsten film is formed with a deposition apparatus employing ALD, a WF6gas and a B2H6gas are sequentially introduced plural times to form an initial tungsten film, and then a WF6gas and an H2gas are introduced at a time, so that a tungsten film is formed. Note that an SiH4gas may be used instead of a B2H6gas. For example, in the case where an oxide semiconductor film, e.g., an In—Ga—Zn—O film is formed with a deposition apparatus employing ALD, an In(CH3)3gas and an O3gas) are used to form an InO layer, then a Ga(CH3)3gas and an O3gas) are used to form a GaO layer, and then a Zn(CH3)2gas and an O3gas) are used to form a ZnO layer. Note that the order of these layers is not limited to this example. A mixed compound layer such as an InGaO layer, an InZnO layer, or a GaZnO layer may be formed by mixing these gases. Note that although an H2O gas which is obtained by bubbling with an inert gas such as Ar may be used instead of an O3gas), it is preferable to use an O3gas), which does not contain H. Instead of an In(CH3)3gas, an In(C2H5)3may be used. Instead of a Ga(CH3)3gas, a Ga(C2H5)3gas may be used. Furthermore, a Zn(CH3)2gas may be used. Structural Example 2 of Semiconductor Device A structural example which is different from the transistor100inFIGS.1A to1Cwill be described with reference toFIGS.3A to3C. Note that in the case where a portion has a function similar to that described above, the same hatch pattern is applied to the portion, and the portion is not especially denoted by a reference numeral in some cases. FIG.3Ais a top view of a transistor150that is a semiconductor device of one embodiment of the present invention.FIG.3Bis a cross-sectional view taken along the dashed dotted line X1-X2inFIG.3A, andFIG.3Cis a cross-sectional view taken along the dashed dotted line Y1-Y2inFIG.3A. The transistor150includes a conductive film104functioning as a gate electrode over a substrate102, an insulating film106over the substrate102and the conductive film104, an insulating film107over the insulating film106, an oxide semiconductor film108over the insulating film107, an insulating film114over the oxide semiconductor film108, an insulating film116over the insulating film114, a metal oxide film132over the insulating film116, a metal oxide film134over the metal oxide film132, a conductive film112afunctioning as a source electrode electrically connected to the oxide semiconductor film108through an opening141aprovided in the insulating films114and116and the metal oxide films132and134, and a conductive film112bfunctioning as a drain electrode electrically connected to the oxide semiconductor film108through an opening141bprovided in the insulating films114and116and the metal oxide films132and134. The metal oxide film132contains at least one metal element that is the same as a metal element contained in the oxide semiconductor film108. The metal oxide film134includes a region where the metal oxide film134is mixed with the metal oxide film132. Although the transistor100described above has a channel-etched structure, the transistor150inFIGS.3A to3Chas a channel-protective structure. Thus, the semiconductor device of one embodiment of the present invention can have either the channel-etched structure or the channel-protective structure. As with the transistor100described above, the transistor150is provided with the insulating films114and116that are formed over the oxide semiconductor film108; therefore, oxygen contained in the insulating films114and116can fill oxygen vacancies in the oxide semiconductor film108. In addition, the provision of the metal oxide films132and134over the insulating film116makes it possible to inhibit entry of impurities into the oxide semiconductor film108from the outside. The other components of the transistor150are similar to those of the transistor100described above, and an effect similar to that of the transistor100can be obtained. Structural Example 3 of Semiconductor Device A structural example different from the transistor150inFIGS.3A to3Cwill be described with reference toFIGS.4A to4C. Note that in the case where a portion has a function similar to that described above, the same hatch pattern is applied to the portion, and the portion is not especially denoted by a reference numeral in some cases. FIG.4Ais a top view of a transistor160that is a semiconductor device of one embodiment of the present invention.FIG.4Bis a cross-sectional view taken along the dashed dotted line X1-X2inFIG.4A, andFIG.4Cis a cross-sectional view taken along the dashed dotted line Y1-Y2inFIG.4A. The transistor160includes a conductive film104functioning as a gate electrode over a substrate102, an insulating film106over the substrate102and the conductive film104, an insulating film107over the insulating film106, an oxide semiconductor film108over the insulating film107, an insulating film114over the oxide semiconductor film108, an insulating film116over the insulating film114, a metal oxide film132over the insulating film116, a metal oxide film134over the metal oxide film132, a conductive film112afunctioning as a source electrode electrically connected to the oxide semiconductor film108, and a conductive film112bfunctioning as a drain electrode electrically connected to the oxide semiconductor film108. The metal oxide film132contains at least one metal element that is the same as a metal element contained in the oxide semiconductor film108. The metal oxide film134includes a region where the metal oxide film134is mixed with the metal oxide film132. Note that the transistor160is different from the transistor150inFIGS.3A to3Cin the shapes of the insulating films114and116and the metal oxide films132and134. Specifically, the insulating films114and116and the metal oxide films132and134of the transistor160have island shapes and are provided over a channel region of the oxide semiconductor film108. The other components are similar to those of the transistor150, and an effect similar to that of the transistor150can be obtained. As with the transistor100described above, the transistor160is provided with the insulating films114and116over the oxide semiconductor film108; therefore, oxygen contained in the insulating films114and116can fill oxygen vacancies in the oxide semiconductor film108. Further, the provision of the metal oxide films132and134over the insulating film116makes it possible to inhibit entry of impurities into the oxide semiconductor film108from the outside. Structural Example 4 of Semiconductor Device A structural example different from the transistor100inFIGS.1A to1Cwill be described with reference toFIGS.5A to5C. Note that in the case where a portion has a function similar to that described above, the same hatch pattern is applied to the portion, and the portion is not especially denoted by a reference numeral in some cases. FIG.5Ais a top view of a transistor170that is a semiconductor device of one embodiment of the present invention.FIG.5Bis a cross-sectional view taken along the dashed dotted line X1-X2inFIG.5A, andFIG.5Cis a cross-sectional view taken along the dashed dotted line Y1-Y2inFIG.5A. The transistor170includes a conductive film104functioning as a first gate electrode over a substrate102, an insulating film106over the substrate102and the conductive film104, an insulating film107over the insulating film106, an oxide semiconductor film108over the insulating film107, a conductive film112afunctioning as a source electrode electrically connected to the oxide semiconductor film108, a conductive film112bfunctioning as a drain electrode electrically connected to the oxide semiconductor film108, an insulating film114over the oxide semiconductor film108and the conductive films112aand112b, an insulating film116over the insulating film114, a metal oxide film132over the insulating film116, a metal oxide film134over the metal oxide film132, and conductive films120aand120bover the metal oxide film134. As with the transistor100, the transistor170is provided with the insulating films114and116over the oxide semiconductor film108; therefore, oxygen contained in the insulating films114and116can fill oxygen vacancies in the oxide semiconductor film108. Further, the provision of the metal oxide films132and134over the insulating film116makes it possible to inhibit entry of impurities into the oxide semiconductor film108from the outside. In the transistor170, the insulating films114and116and the metal oxide films132and134have a function of a second gate insulating film of the transistor170. In the transistor170, the conductive film120ahas a function of, for example, a pixel electrode used for a display device. The conductive film120ais connected to the conductive film112bthrough an opening142cprovided in the insulating films114and116and metal oxide films132and134. In the transistor170, the conductive film120bfunctions as a second gate electrode (also referred to as a back gate electrode). As illustrated inFIG.5C, the conductive film120bis connected to the conductive film104functioning as the first gate electrode through openings142aand142bprovided in the insulating films106,107,114, and116and the metal oxide films132and134. Accordingly, the conductive film120band the conductive film104are supplied with the same potential. Note that although the structure in which the openings142aand142bare provided so that the conductive film120band the conductive film104are connected to each other is described in this embodiment, one embodiment of the present invention is not limited thereto. For example, a structure in which only one of the openings142aand142bis provided so that the conductive film120band the conductive film104are connected to each other, or a structure in which the openings142aand142bare not provided and the conductive film120band the conductive film104are not connected to each other may be employed. Note that in the case where the conductive film120band the conductive film104are not connected to each other, it is possible to apply different potentials to the conductive film120band the conductive film104. As illustrated inFIG.5B, the oxide semiconductor film108is positioned to be opposite each of the conductive film104functioning as the first gate electrode and the conductive film120bfunctioning as the second gate electrode, and is sandwiched between the two conductive films functioning as gate electrodes. The lengths in the channel length direction and the channel width direction of the conductive film120bfunctioning as the second gate electrode are longer than those in the channel length direction and the channel width direction of the oxide semiconductor film108. The whole oxide semiconductor film108is covered with the conductive film120bwith the insulating films114and116and the metal oxide films132and134positioned therebetween. In addition, since the conductive film120bfunctioning as the second gate electrode is connected to the conductive film104functioning as the first gate electrode through the openings142aand142bprovided in the insulating films106,107,114and116and the metal oxide films132and134; a side surface of the oxide semiconductor film108in the channel width direction faces the conductive film120bfunctioning as the second gate electrode with the insulating films114and116and the metal oxide films132and134positioned therebetween. In other words, the transistor170has the following structure in the channel width direction: the conductive film104functioning as the first gate electrode and the conductive film120bfunctioning as the second gate electrode are connected to each other in the openings provided in the insulating films106and107functioning as a gate insulating film and the insulating films114and116and the metal oxide films132and134functioning as the second gate insulating film; and the conductive film104functioning as the first gate electrode and the conductive film120bfunctioning as the second gate electrode surround the oxide semiconductor film108, with the insulating films106and107functioning as the gate insulating film and the insulating films114and116and the metal oxide films132and134functioning as the second gate insulating film positioned between the conductive film104or120band the oxide semiconductor film108. Such a structure makes it possible that the oxide semiconductor film108included in the transistor170is electrically surrounded by electric fields of the conductive film104functioning as the first gate electrode and the conductive film120bfunctioning as the second gate electrode. The device structure of a transistor, like that of the transistor170, in which electric fields of a first gate electrode and a second gate electrode electrically surround an oxide semiconductor film where a channel region is formed can be referred to as a surrounded channel (s-channel) structure. Since the transistor170has the s-channel structure, an electric field for inducing a channel can be effectively applied to the oxide semiconductor film108by the conductive film104functioning as the first gate electrode; therefore, the current drive capability of the transistor170can improve and high on-state current characteristics can be obtained. In addition, since the on-state current can be increased, it is possible to reduce the size of the transistor170. In addition, since the transistor170has a structure in which the oxide semiconductor film108is surrounded by the conductive film104functioning as the first gate electrode and the conductive film120bfunctioning as the second gate electrode, the mechanical strength of the transistor170can be increased. Structural Example 5 of Semiconductor Device Structural examples different from the transistor100inFIGS.1A to1Cwill be described with reference toFIGS.6A to6D. Note that in the case where a portion has a function similar to that described above, the same hatch pattern is applied to the portion, and the portion is not especially denoted by a reference numeral in some cases. FIGS.6A to6Dare cross-sectional views illustrating variations of the transistor100inFIGS.1B and1C. A transistor100A inFIGS.6A and6Bhas the same structure as the transistor100inFIGS.1B and1Cexcept that the oxide semiconductor film108has a three-layer structure. Specifically, the oxide semiconductor film108of the transistor100A includes an oxide semiconductor film108a, an oxide semiconductor film108b, and an oxide semiconductor film108c. A transistor100B inFIGS.6C and6Dhas the same structure as the transistor100inFIGS.1B and1Cexcept that the oxide semiconductor film108has a two-layer structure. Specifically, the oxide semiconductor film108of the transistor100B includes an oxide semiconductor film108band an oxide semiconductor film108c. Here, a band structure including the oxide semiconductor films108a,108b, and108cand the insulating films in contact with the oxide semiconductor films108band108cis described with reference toFIGS.7A and7B. FIG.7Ashows an example of a band structure in the thickness direction of a stack including the insulating film107, the oxide semiconductor films108a,108b, and108c, and the insulating film114.FIG.7Bshows an example of a band structure in the thickness direction of a stack including the insulating film107, the oxide semiconductor films108band108c, and the insulating film114. For easy understanding, the conduction band minimum (Ec) of each of the insulating film107, the oxide semiconductor films108a,108b, and108c, and the insulating film114is shown in the band diagrams. In the band structure ofFIG.7A, a silicon oxide film is used as each of the insulating films107and114, an oxide semiconductor film formed using a metal oxide target having an atomic ratio of metal elements of In:Ga:Zn=1:3:2 is used as the oxide semiconductor film108a, an oxide semiconductor film formed using a metal oxide target having an atomic ratio of metal elements of In:Ga:Zn=1:1:1 is used as the oxide semiconductor film108b, and an oxide semiconductor film formed using a metal oxide target having an atomic ratio of metal elements of In:Ga:Zn=1:3:2 is used as the oxide semiconductor film108c. In the band structure ofFIG.7B, a silicon oxide film is used as each of the insulating films107and114, an oxide semiconductor film formed using a metal oxide target having an atomic ratio of metal elements of In:Ga:Zn=1:1:1 is used as the oxide semiconductor film108b, and a metal oxide film formed using a metal oxide target having an atomic ratio of metal elements of In:Ga:Zn=1:3:2 is used as the oxide semiconductor film108c. As illustrated inFIGS.7A and7B, the energy level of the conduction band minimum gradually varies between the oxide semiconductor film108aand the oxide semiconductor film108band between the oxide semiconductor film108band the oxide semiconductor film108c. In other words, the energy level at the bottom of the conduction band is continuously varied or continuously connected. To obtain such a band structure, there exists no impurity, which forms a defect state such as a trap center or a recombination center, at the interface between the oxide semiconductor film108aand the oxide semiconductor film108bor at the interface between the oxide semiconductor film108band the oxide semiconductor film108c. To form a continuous junction between the oxide semiconductor film108aand the oxide semiconductor film108band between the oxide semiconductor film108band the oxide semiconductor film108c, it is necessary to form the films successively without exposure to the air by using a multi-chamber deposition apparatus (sputtering apparatus) provided with a load lock chamber. With the band structure ofFIG.7AorFIG.7B, the oxide semiconductor film108bserves as a well, and a channel region is formed in the oxide semiconductor film108bin the transistor with the stacked-layer structure. The provision of the oxide semiconductor film108aand/or the oxide semiconductor film108cenables the oxide semiconductor film108bto be distanced away from trap states. In addition, the trap states might be more distant from the vacuum level than the energy level of the conduction band minimum (Ec) of the oxide semiconductor film108bfunctioning as a channel region, so that electrons are likely to be accumulated in the trap states. When the electrons are accumulated in the trap states, the electrons become negative fixed electric charge, so that the threshold voltage of the transistor is shifted in the positive direction. Therefore, it is preferable that the energy level of the trap states be closer to the vacuum level than the energy level of the conduction band minimum (Ec) of the oxide semiconductor film108b. Such a structure inhibits accumulation of electrons in the trap states. As a result, the on-state current and the field-effect mobility of the transistor can be increased. InFIGS.7A and7B, the energy level of the conduction band minimum of each of the oxide semiconductor films108aand108cis closer to the vacuum level than that of the oxide semiconductor film108b. Typically, a difference in energy level between the conduction band minimum of the oxide semiconductor film108band the conduction band minimum of each of the oxide semiconductor films108aand108cis 0.15 eV or more or 0.5 eV or more and 2 eV or less or 1 eV or less. That is, the difference between the electron affinity of each of the oxide semiconductor films108aand108cand the electron affinity of the oxide semiconductor film108bis 0.15 eV or more or 0.5 eV or more and 2 eV or less or 1 eV or less. In such a structure, the oxide semiconductor film108bserves as a main path of current and functions as a channel region. In addition, since the oxide semiconductor films108aand108ceach contain one or more metal elements that are the same as those contained in the oxide semiconductor film108bin which a channel region is formed, interface scattering is less likely to occur at the interface between the oxide semiconductor film108aand the oxide semiconductor film108bor at the interface between the oxide semiconductor film108band the oxide semiconductor film108c. Thus, the transistor can have high field-effect mobility because the movement of carriers is not hindered at the interface. To prevent each of the oxide semiconductor films108aand108cfrom functioning as part of a channel region, a material having sufficiently low conductivity is used for the oxide semiconductor films108aand108c. Alternatively, a material which has a smaller electron affinity (a difference in energy level between the vacuum level and the conduction band minimum) than the oxide semiconductor film108band has a difference in energy level in the conduction band minimum from the oxide semiconductor film108b(band offset) is used for the oxide semiconductor films108aand108c. Furthermore, to inhibit generation of a difference between threshold voltages due to the value of the drain voltage, it is preferable to form the oxide semiconductor films108aand108cusing a material whose energy level of the conduction band minimum is closer to the vacuum level than that of the oxide semiconductor film108bby 0.2 eV or more, preferably 0.5 eV or more. It is preferable that the oxide semiconductor films108aand108cnot have a spinel crystal structure. This is because if the oxide semiconductor films108aand108chave a spinel crystal structure, constituent elements of the conductive films112aand112bmight be diffused to the oxide semiconductor film108bat the interface between the spinel crystal structure and another region. Note that each of the oxide semiconductor films108aand108cis preferably a CAAC-OS, which will be described later, in which case a higher blocking property against constituent elements of the conductive films112aand112b, for example, copper elements, is obtained. The thickness of each of the oxide semiconductor films108aand108cis greater than or equal to a thickness that is capable of inhibiting diffusion of the constituent elements of the conductive films112aand112bto the oxide semiconductor film108b, and less than a thickness that inhibits supply of oxygen from the insulating film114to the oxide semiconductor film108b. For example, when the thickness of each of the oxide semiconductor films108aand108cis greater than or equal to 10 nm, diffusion of the constituent elements of the conductive films112aand112bto the oxide semiconductor film108bcan be inhibited. When the thickness of each of the oxide semiconductor films108aand108cis less than or equal to 100 nm, oxygen can be effectively supplied from the insulating films114and116to the oxide semiconductor film108b. When the oxide semiconductor films108aand108care each an In-M-Zn oxide in which the atomic ratio of the element M (M is Ti, Ga, Y, Zr, La, Ce, Nd, or Hf) is higher than that of In, the energy gap of each of the oxide semiconductor films108aand108ccan be large and the electron affinity thereof can be small. Therefore, a difference in electron affinity between the oxide semiconductor film108band each of the oxide semiconductor films108aand108cmay be controlled by the proportion of the element M. Furthermore, an oxygen vacancy is less likely to be generated in the oxide semiconductor layer in which the atomic ratio of Ti, Ga, Y, Zr, La, Ce, Nd, or Hf is higher than that of In because Ti, Ga, Y, Zr, La, Ce, Nd, and Hf are each a metal element that is strongly bonded to oxygen. When an In-M-Zn oxide is used for the oxide semiconductor films108aand108c, the proportions of In and M, not taking Zn and O into consideration, are as follows: the atomic percentage of In is preferably less than 50 atomic % and the atomic percentage of M is greater than 50 atomic % and further preferably the atomic percentage of In is less than 25 atomic % and the atomic percentage of M is greater than 75 atomic %. Alternatively, a gallium oxide film may be used as each of the oxide semiconductor films108aand108c. Furthermore, in the case where each of the oxide semiconductor films108a,108b, and108cis an In-M-Zn oxide, the proportion of M atoms in each of the oxide semiconductor films108aand108cis higher than that in the oxide semiconductor film108b. Typically, the proportion of M atoms in each of the oxide semiconductor films108aand108cis 1.5 or more times, preferably twice or more times, or further preferably three or more times as high as that in the oxide semiconductor film108b. Furthermore, in the case where the oxide semiconductor films108a,108b, and108care each an In-M-Zn oxide, when the oxide semiconductor film108bhas an atomic ratio of In:M:Zn=x1:y1:z1and the oxide semiconductor films108aand108ceach have an atomic ratio of In:M:Zn=x2:y2:z2, y2/x2is larger than y1/x1, preferably y2/x2is 1.5 or more times as large as y1/x1, further preferably, y2/x2is two or more times as large as y1/x1, or still further preferably y2/x2is three or more times or four or more times as large as y1/x1. In this case, it is preferable that in the oxide semiconductor film108b, y1be higher than or equal to x1because a transistor including the oxide semiconductor film108bcan have stable electric characteristics. However, when y1is three or more times as large as x1, the field-effect mobility of the transistor including the oxide semiconductor film108bis reduced. Accordingly, y1is preferably smaller than three times x1. In the case where the oxide semiconductor film108bis an In-M-Zn oxide and a target having the atomic ratio of metal elements of In:M:Zn=x1:y1:z1is used for depositing the oxide semiconductor film108b, x1/y1is preferably greater than or equal to ⅓ and less than or equal to 6, or further preferably greater than or equal to 1 and less than or equal to 6, and z1/y1is preferably greater than or equal to ⅓ and less than or equal to 6, or further preferably greater than or equal to 1 and less than or equal to 6. Note that when z1/y1is greater than or equal to 1 and less than or equal to 6, a CAAC-OS to be described later is easily formed as the oxide semiconductor film108b. Typical examples of the atomic ratio of the metal elements of the target include In:M:Zn=1:1:1, In:M:Zn=1:1:1.2, and In:M:Zn=3:1:2. In the case where the oxide semiconductor films108aand108care each an In-M-Zn oxide and a target having an atomic ratio of metal elements of In:M:Zn=x2:y2:z2is used for depositing the oxide semiconductor films108aand108c, x2/y2is preferably less than x1/y1, and z2/y2is preferably greater than or equal to ⅓ and less than or equal to 6, or further preferably greater than or equal to 1 and less than or equal to 6. When the atomic ratio of M with respect to indium is high, the energy gap of the oxide semiconductor films108aand108ccan be large and the electron affinity thereof can be small; therefore, y2/x2is preferably higher than or equal to 3 or higher than or equal to 4. Typical examples of the atomic ratio of the metal elements of the target include In:M:Zn=1:3:2, In:M:Zn=1:3:4, In:M:Zn=1:3:5, In:M:Zn=1:3:6, In:M:Zn=1:4:2, In:M:Zn=1:4:4, In:M:Zn=1:4:5, and In:M:Zn=1:5:5. Furthermore, in the case where the oxide semiconductor films108aand108care each an In-M oxide, when a divalent metal element (e.g., zinc) is not included as M, the oxide semiconductor films108aand108cwhich do not include a spinel crystal structure can be formed. As each of the oxide semiconductor films108aand108c, for example, an In—Ga oxide film can be used. The In—Ga oxide can be formed by a sputtering method using an In—Ga metal oxide target (In:Ga=7:93), for example. To deposit the oxide semiconductor films108aand108cby a sputtering method using DC discharge, on the assumption that an atomic ratio of In:M is x:y, it is preferable that y/(x+y) be less than or equal to 0.96, or further preferably less than or equal to 0.95, for example, 0.93. In each of the oxide semiconductor films108a,108b, and108c, the proportions of the atoms in the above atomic ratio vary within a range of ±40% as an error. The structures of the transistors of this embodiment can be freely combined with each other. <Method 1 for Manufacturing Semiconductor Device> Next, a method for manufacturing the transistor100that is a semiconductor device of one embodiment of the present invention will be described with reference toFIGS.8A to8C,FIGS.9A to9C, andFIGS.10A and10B. Note thatFIGS.8A to8C,FIGS.9A to9C, andFIGS.10A and10Bare cross-sectional views illustrating the method for manufacturing the semiconductor device. First, a conductive film is formed over the substrate102and processed through a lithography process and an etching process, whereby the conductive film104functioning as a gate electrode is formed (seeFIG.8A). In this embodiment, a glass substrate is used as the substrate102, and as the conductive film104functioning as a gate electrode, a 100-nm-thick tungsten film is formed by a sputtering method. Then, the insulating films106and107functioning as gate insulating films are formed over the conductive film104(seeFIG.8B). In this embodiment, a 400-nm-thick silicon nitride film as the insulating film106and a 50-nm-thick silicon oxynitride film as the insulating film107are formed by a PECVD method. The insulating film106has a stacked-layer structure of silicon nitride films. Specifically, the insulating film106can have a three-layer stacked-layer structure of a first silicon nitride film, a second silicon nitride film, and a third silicon nitride film. An example of the three-layer stacked-layer structure can be formed as follows. For example, the first silicon nitride film can be formed to have a thickness of 50 nm under the conditions where silane at a flow rate of 200 sccm, nitrogen at a flow rate of 2000 sccm, and an ammonia gas at a flow rate of 100 sccm are supplied as a source gas to a reaction chamber of a PECVD apparatus, the pressure in the reaction chamber is controlled to 100 Pa, and a power of 2000 W is supplied using a 27.12 MHz high-frequency power source. The second silicon nitride film can be formed to have a thickness of 300 nm under the condition where silane at a flow rate of 200 sccm, nitrogen at a flow rate of 2000 sccm, and an ammonia gas at a flow rate of 2000 sccm are supplied as a source gas to the reaction chamber of the PECVD apparatus; the pressure in the reaction chamber is controlled to 100 Pa, and a power of 2000 W is supplied using a 27.12 MHz high-frequency power source. The third silicon nitride film can be formed to have a thickness of 50 nm under the condition where silane at a flow rate of 200 sccm and nitrogen at a flow rate of 5000 sccm are supplied as a source gas to the reaction chamber of the PECVD apparatus; the pressure in the reaction chamber is controlled to 100 Pa, and a power of 2000 W is supplied using a 27.12 MHz high-frequency power source. Note that the first silicon nitride film, the second silicon nitride film, and the third silicon nitride film can be each formed at a substrate temperature of 350° C. When the insulating film106has the three-layer stacked-layer structure of silicon nitride films, for example, in the case where a conductive film containing copper (Cu) is used as the conductive film104, the following effect can be obtained. The first silicon nitride film can inhibit diffusion of a copper (Cu) element from the conductive film104. The second silicon nitride film has a function of releasing hydrogen and can improve withstand voltage of the insulating film functioning as a gate insulating film. The third silicon nitride film releases a small amount of hydrogen and can inhibit diffusion of hydrogen released from the second silicon nitride film. The insulating film107is preferably an insulating film containing oxygen to improve characteristics of an interface with the oxide semiconductor film108formed later. Next, the oxide semiconductor film108is formed over the insulating film107(seeFIG.8C). In this embodiment, an oxide semiconductor film is formed by a sputtering method using an In—Ga—Zn metal oxide target (having an atomic ratio of In:Ga:Zn=1:1:1.2), a mask is formed over the oxide semiconductor film through a lithography process, and the oxide semiconductor film is processed into a desired shape, whereby the oxide semiconductor film108having an island shape is formed. After the oxide semiconductor film108is formed, heat treatment may be performed at a temperature higher than or equal to 150° C. and lower than the strain point of the substrate, preferably higher than or equal to 200° C. and lower than or equal to 450° C., further preferably higher than or equal to 300° C. and lower than or equal to 450° C. The heat treatment performed here serves as one kind of treatment for increasing the purity of the oxide semiconductor film and can reduce hydrogen, water, and the like contained in the oxide semiconductor film108. Note that the heat treatment for the purpose of reducing hydrogen, water, and the like may be performed before the oxide semiconductor film108is processed into an island shape. A gas baking furnace, an electric furnace, a rapid thermal annealing (RTA) apparatus, or the like can be used for the heat treatment to which the oxide semiconductor film108is subjected. With the use of an RTA apparatus, the heat treatment can be performed at a temperature higher than or equal to the strain point of the substrate if the heating time is short. Therefore, the heat treatment time can be shortened. The heat treatment to which the oxide semiconductor film108is subjected may be performed in an atmosphere of nitrogen gas, oxygen gas, clean dry air (also referred to as CDA, which is an air with a water content of 20 ppm or less, preferably 1 ppm or less, further preferably 10 ppb or less), or rare gas (e.g., argon or helium). The atmosphere of nitrogen gas, oxygen gas, CDA, or rare gas preferably does not contain hydrogen, water, and the like. The purity of the nitrogen gas, the oxygen gas, or CDA is preferably increased, for example. Specifically, the purity of the nitrogen gas, the oxygen gas, or CDA is preferably 6N (99.9999%) or 7N (99.99999%). When a gas which is highly purified to have a dew point of −60° C. or lower, preferably −100° C. or lower, is used as the nitrogen gas, the oxygen gas, or CDA, entry of moisture and the like into the oxide semiconductor film108can be minimized. Further, the oxide semiconductor film108may be subjected to another heat treatment in an oxygen atmosphere or a CDA atmosphere after the heat treatment in a nitrogen atmosphere or a rare gas atmosphere. As a result, hydrogen, water, and the like can be released from the oxide semiconductor film108and oxygen can be supplied to the oxide semiconductor film108at the same time. Consequently, the amount of oxygen vacancies in the oxide semiconductor film108can be reduced. Here, thermal profiles of heat treatment performed on the oxide semiconductor film108in a gas baking furnace will be described with reference toFIGS.16A and16BandFIGS.17A and17B.FIGS.16A and16BandFIGS.17A and17Beach show a thermal profile of heat treatment in a gas baking furnace. Note that each ofFIGS.16A and16BandFIGS.17A and17Bis a thermal profile showing the temperature raised to a predetermined temperature (here, 450° C.; hereinafter referred to as a first temperature) and dropped to a predetermined temperature (here, higher than or equal to room temperature and lower than or equal to 150° C.; hereinafter referred to as a second temperature). When the oxide semiconductor film108is subjected to heat treatment, the treatment can be divided into two steps using two kinds of gases as shown inFIG.16A. For example, a nitrogen gas is introduced into a gas baking furnace in the first step. Then, the temperature is raised to the first temperature over one hour, and the heat treatment is performed at the first temperature for another one hour. After that, the temperature is dropped to the second temperature over the next one hour. In the second step, the nitrogen gas is replaced by a mixed gas of nitrogen and oxygen. Then, the time taken to raise the temperature to the first temperature is one hour, and the heat treatment is performed at the first temperature for another one hour. After that, the temperature is dropped to the second temperature over the next one hour. Alternatively, when the oxide semiconductor film108is subjected to heat treatment, the treatment can be performed in one step using two kinds of gases as shown inFIG.16B. For example, first, a nitrogen gas is introduced into a gas baking furnace. Then, the temperature is raised to the first temperature over one hour, and the heat treatment is performed at the first temperature for another one hour. After that, the gas is changed from the nitrogen gas to CDA. After the gas change, the heat treatment is performed for another one hour, and the temperature is dropped to the second temperature over the next one hour. The thermal profile of the heat treatment in the gas baking furnace shown inFIG.16Brequires less processing time than the thermal profile of the heat treatment in the gas baking furnace shown inFIG.16A; accordingly, semiconductor devices can be provided with higher productivity. Alternatively, when the oxide semiconductor film108is subjected to heat treatment, the treatment can be performed in two steps using two kinds of gases as shown inFIG.17A. For example, first, a nitrogen gas is introduced into a gas baking furnace in the first step. Then, the temperature is raised to the first temperature over one hour, and the heat treatment is performed at the first temperature for another one hour. After that, the gas is changed from the nitrogen gas to CDA. After the gas change, the heat treatment is performed for another one hour, and the temperature is dropped to the second temperature over the next one hour. In the second step, CDA is replaced by a nitrogen gas. Then, the temperature is raised to the first temperature over one hour, and the heat treatment is performed at the first temperature for another one hour. After that, the gas is changed from the nitrogen gas to CDA. After the gas change, the heat treatment is performed for another one hour, and the temperature is dropped to the second temperature over the next one hour. Alternatively, when the oxide semiconductor film108is subjected to heat treatment, the treatment can be performed in two steps using two kinds of gases as shown inFIG.17B. For example, first, a nitrogen gas is introduced into a gas baking furnace in the first step. Then, the temperature is raised to the first temperature over one hour, and the heat treatment is performed at the first temperature for two hours. After that, the temperature is dropped to the second temperature over the next one hour. In the second step, the temperature is raised to the first temperature over one hour, and the heat treatment is performed at the first temperature for two hours. After that, the gas is changed from the nitrogen gas to CDA. After the gas change, the heat treatment is performed for another two hours, and then the temperature is dropped to the second temperature over the next one hour. As far as the thermal profiles of heat treatment performed on the oxide semiconductor film108in a gas baking furnace are concerned, it is preferable that the oxide semiconductor film108be first heated in a nitrogen gas as shown inFIGS.16A and16BandFIGS.17A and17B. When the oxide semiconductor film108is first heated in a nitrogen gas, oxygen, which is one of the principal components of the oxide semiconductor film108, and hydrogen in the oxide semiconductor film108react with each other to form an OH group. Then, the OH group is released from the surface of the oxide semiconductor film108as H2O. In other words, owing to the first nitrogen gas, hydrogen in the oxide semiconductor film108can be captured. However, heating the oxide semiconductor film108with only a nitrogen gas makes oxygen be released from the oxide semiconductor film108as H2O, whereby oxygen vacancies are formed in the oxide semiconductor film108. Thus, the nitrogen gas is replaced by either a mixed gas of nitrogen and oxygen or CDA as shown inFIGS.16A and16BandFIGS.17A and17B, in which case oxygen contained in the gas can fill the oxygen vacancies in the oxide semiconductor film108. Note that although the heat treatment is performed for one or two consecutive hours after the temperature becomes stable at the predetermined temperature inFIGS.16A and16BandFIGS.17A and17B, one embodiment of the present invention is not limited thereto. For example, the processing time of heat treatment in the nitrogen gas in the first step inFIG.17Bmay be one to 10 hours inclusive. As the processing time of the first step inFIG.17Bis increased, a larger amount of hydrogen can be released from the oxide semiconductor film108, which is preferable. In addition, time for baking with the use of either a mixed gas of nitrogen and oxygen or CDA may be set longer (e.g., one to 10 hours inclusive) as necessary. Increasing the heating time in an oxygen-containing atmosphere makes it possible to favorably fill the oxygen vacancies formed in the oxide semiconductor film108. In the case where the oxide semiconductor film is formed by a sputtering method, a rare gas (typically argon), oxygen, or a mixed gas of a rare gas and oxygen is used as a sputtering gas, as appropriate. In the case where the mixed gas of a rare gas and oxygen is used, the proportion of oxygen to a rare gas is preferably increased. In addition, increasing the purity of a sputtering gas is necessary. For example, as an oxygen gas or an argon gas used for a sputtering gas, a gas that is highly purified to have a dew point of −60° C. or lower, further preferably −100° C. or lower is used, whereby entry of moisture or the like into the oxide semiconductor film108can be minimized. In the case where the oxide semiconductor film108is formed by a sputtering method, a chamber in a sputtering apparatus is preferably evacuated to be a high vacuum state (to the degree of about 5×10-7 Pa to 1×10-4 Pa) with an adsorption vacuum evacuation pump such as a cryopump in order to remove water or the like, which serves as an impurity for the oxide semiconductor film108, as much as possible. Alternatively, a turbo molecular pump and a cold trap are preferably combined so as to prevent a backflow of a gas, especially a gas containing carbon or hydrogen from an exhaust system to the inside of the chamber. Next, the conductive films112aand112bfunctioning as source and drain electrodes are formed over the insulating film107and the oxide semiconductor film108(seeFIG.9A). In this embodiment, the conductive films112aand112bare formed in the following manner: a stack including a 50-nm-thick tungsten film and a 400-nm-thick aluminum film is formed by a sputtering method, a mask is formed over the stack through a lithography process, and the stack is processed into desired shapes. Although the conductive films112aand112beach have a two-layer stacked-layer structure in this embodiment, one embodiment of the present invention is not limited thereto. For example, the conductive films112aand112beach may have a three-layer stacked-layer structure including a 50-nm-thick tungsten film, a 400-nm-thick aluminum film, and a 100-nm-thick titanium film. After the conductive films112aand112bare formed, a surface of the oxide semiconductor film108(on a back channel side) may be cleaned. The cleaning may be performed, for example, using a chemical solution such as phosphoric acid. The cleaning using a chemical solution such as a phosphoric acid can remove impurities (e.g., an element contained in the conductive films112aand112b) attached to the surface of the oxide semiconductor film108. Note that a recessed portion might be formed in part of the oxide semiconductor film108in the step of forming the conductive films112aand112band/or the cleaning step. Through the above steps, the transistor100is formed. Next, over the transistor100, specifically, over the oxide semiconductor film108and the conductive films112aand112b, the insulating films114and116functioning as protective insulating films of the transistor100are formed (seeFIG.9B). Note that after the insulating film114is formed, the insulating film116is preferably formed in succession without exposure to the air. After the insulating film114is formed, the insulating film116is formed in succession without exposure to the air while at least one of the flow rate of a source gas, pressure, a high-frequency power, and a substrate temperature is adjusted, whereby the concentration of impurities attributed to the atmospheric component at the interface between the insulating film114and the insulating film116can be reduced and oxygen in the insulating films114and116can be moved to the oxide semiconductor film108; accordingly, the amount of oxygen vacancies in the oxide semiconductor film108can be reduced. As the insulating film114, a silicon oxynitride film can be formed by a PECVD method, for example. In this case, a deposition gas containing silicon and an oxidizing gas are preferably used as a source gas. Typical examples of the deposition gas containing silicon include silane, disilane, trisilane, and silane fluoride. Examples of the oxidizing gas include dinitrogen monoxide and nitrogen dioxide. An insulating film containing nitrogen and having a small number of defects can be formed as the insulating film114by a PECVD method under the conditions where the ratio of the oxidizing gas to the deposition gas is higher than 20 times and lower than 100 times, preferably higher than or equal to 40 times and lower than or equal to 80 times and the pressure in a treatment chamber is lower than 100 Pa, preferably lower than or equal to 50 Pa. In this embodiment, a silicon oxynitride film is formed as the insulating film114by a PECVD method under the conditions where the substrate102is held at a temperature of 220° C., silane at a flow rate of 50 sccm and dinitrogen monoxide at a flow rate of 2000 sccm are used as a source gas, the pressure in the treatment chamber is 20 Pa, and a high-frequency power of 100 W at 13.56 MHz (1.6×10−2 W/cm2 as the power density) is supplied to parallel-plate electrodes. As the insulating film116, a silicon oxide film or a silicon oxynitride film is formed under the following conditions: the substrate placed in a treatment chamber of the PECVD apparatus that is vacuum-evacuated is held at a temperature higher than or equal to 180° C. and lower than or equal to 280° C., preferably higher than or equal to 200° C. and lower than or equal to 240° C.; the pressure is greater than or equal to 100 Pa and less than or equal to 250 Pa, preferably greater than or equal to 100 Pa and less than or equal to 200 Pa with introduction of a source gas into the treatment chamber; and a high-frequency power of greater than or equal to 0.17 W/cm2 and less than or equal to 0.5 W/cm2, preferably greater than or equal to 0.25 W/cm2 and less than or equal to 0.35 W/cm2 is supplied to an electrode provided in the treatment chamber. As the deposition conditions of the insulating film116, the high-frequency power having the above power density is supplied to a reaction chamber having the above pressure, whereby the degradation efficiency of the source gas in plasma is increased, oxygen radicals are increased, and oxidation of the source gas is promoted; thus, the oxygen content in the insulating film116becomes higher than that in the stoichiometric composition. On the other hand, in the film formed at a substrate temperature within the above temperature range, the bond between silicon and oxygen is weak, and accordingly, part of oxygen in the film is released by heat treatment in a later step. Thus, it is possible to form an oxide insulating film which contains oxygen at a higher proportion than the stoichiometric composition and from which part of oxygen is released by heating. Note that the insulating film114functions as a protective film for the oxide semiconductor film108in the step of forming the insulating film116. Therefore, the insulating film116can be formed using the high-frequency power having a high power density while damage to the oxide semiconductor film108is reduced. Note that in the deposition conditions of the insulating film116, when the flow rate of the deposition gas containing silicon with respect to the oxidizing gas is increased, the amount of defects in the insulating film116can be reduced. Typically, it is possible to form an oxide insulating layer in which the amount of defects is small, i.e., the spin density of a signal which appears at g=2.001 originating from a dangling bond of silicon is lower than 6×1017 spins/cm3, preferably lower than or equal to 3×1017 spins/cm3, further preferably lower than or equal to 1.5×1017 spins/cm3 by ESR measurement. As a result, the reliability of the transistor can be improved. Heat treatment may be performed after the insulating films114and116are formed. The heat treatment can reduce nitrogen oxide contained in the insulating films114and116. By the heat treatment, part of oxygen contained in the insulating films114and116can be moved to the oxide semiconductor film108, so that the amount of oxygen vacancies included in the oxide semiconductor film108can be reduced. The temperature of the heat treatment performed on the insulating films114and116is typically higher than or equal to 150° C. and lower than or equal to 400° C., preferably higher than or equal to 300° C. and lower than or equal to 400° C., further preferably higher than or equal to 320° C. and lower than or equal to 370° C. The heat treatment may be performed under an atmosphere of nitrogen, oxygen, CDA, or a rare gas (argon, helium, and the like). Note that a gas baking furnace, an electric furnace, an RTA apparatus, or the like can be used for the heat treatment, in which it is preferable that hydrogen, water, and the like not be contained in the nitrogen, oxygen, ultra-dry air, or a rare gas. In this embodiment, the heat treatment is performed at 350° C. for one hour in an atmosphere of nitrogen and oxygen. Then, the metal oxide film132is formed over the insulating film116(seeFIG.9C). The metal oxide film132can be formed using a conductive film containing indium or a semiconductor film containing indium. In this embodiment, a 5-nm-thick ITSO film is formed, as the metal oxide film132, with the use of a sputtering apparatus. Note that the thickness of the metal oxide film132is preferably greater than or equal to 1 nm and less than or equal to 20 nm, or greater than or equal to 2 nm and less than or equal to 10 nm, in which case oxygen is favorably transmitted and release of oxygen can be inhibited. Next, oxygen140is introduced into the insulating films114and116through the metal oxide film132(seeFIG.10A). Examples of the method for introducing the oxygen140into the insulating films114and116through the metal oxide film132include an ion doping method, an ion implantation method, and a plasma treatment method. For the plasma treatment method, high-density plasma may be generated by exciting oxygen with a microwave. By application of a bias voltage to the substrate side when the oxygen140is introduced, the oxygen140can be effectively introduced into the insulating films114and116. With the use of an ashing apparatus, for example, power density of the bias voltage applied to the substrate side of the ashing apparatus may be greater than or equal to 1 W/cm2 and less than or equal to 5 W/cm2. The substrate temperature during introduction of the oxygen140is higher than room temperature and lower than 350° C., preferably higher than or equal to 100° C. and lower than or equal to 250° C., whereby the oxygen can be introduced efficiently into the insulating films114and116. In this embodiment, an ashing apparatus is used. An02gas is introduced into the ashing apparatus and a bias is applied to the substrate side, whereby the oxygen140is introduced into the insulating films114and116. Oxygen is introduced into the insulating films114and116with the metal oxide film132provided thereover; thus, the metal oxide film132functions as a protective film that inhibits oxygen from being released from the insulating films114and116. Accordingly, a larger amount of oxygen can be introduced into the insulating films114and116. Next, the metal oxide film134is formed over the metal oxide film132, whereby the transistor100inFIGS.1A to1Cis formed (seeFIG.10B). A conductive film containing aluminum, an insulating film containing aluminum, or the like can be used as the metal oxide film134. For example, aluminum is deposited by a sputtering method as a conductive film over the metal oxide film132, and the deposited aluminum is subjected to oxygen plasma treatment or heat treatment in an oxygen atmosphere, whereby an aluminum oxide film can be formed as the metal oxide film134over the metal oxide film132. Alternatively, an aluminum oxide film is formed by an ALD method as an insulating film over the metal oxide film132, whereby an aluminum oxide film as the metal oxide film134can be formed over the metal oxide film132. Further, heat treatment may be performed after the formation of the metal oxide films132and134, so that excess oxygen contained in the insulating films114and116can be diffused into the oxide semiconductor film108to fill oxygen vacancies in the oxide semiconductor film108. Alternatively, either one of or each of the metal oxide films132and134is formed by thermal deposition, so that excess oxygen contained in the insulating films114and116can be diffused into the oxide semiconductor film108to fill oxygen vacancies in the oxide semiconductor film108. The temperature of the heat treatment that can be performed after the formation of the metal oxide films132and134is typically higher than or equal to 150° C. and lower than or equal to 400° C., preferably higher than or equal to 300° C. and lower than or equal to 400° C., and further preferably higher than or equal to 320° C. and lower than or equal to 370° C. Through the above-described process, the transistor100illustrated inFIGS.1A to1Ccan be fabricated. <Method 2 for Manufacturing Semiconductor Device> Next, a modification example of the method for manufacturing the transistor100inFIGS.1A to1Cthat is a semiconductor device of one embodiment of the present invention will be described with reference toFIGS.11A to11C.FIGS.11A to11Care cross-sectional views illustrating a method for manufacturing a semiconductor device. First, the steps up to the step shown inFIG.9Bare performed. Then, a halogen element139is introduced into the insulating films114and116(seeFIG.11A). Examples of the halogen element include fluorine and chlorine. The halogen element139may be introduced into the insulating films114and116from above the insulating film116by an ion doping method, an ion implantation method, or a plasma treatment method, using a gas containing fluorine or a gas containing chlorine. Examples of the gas containing fluorine include carbon tetrafluoride (CF4), sulfur hexafluoride (SF6), nitrogen trifluoride (NF3), trifluoromethane (CHF3), silicon tetrafluoride (SiF4), and perfluorocyclobutane (C4F8). Examples of the gas containing chlorine include chlorine (C12), boron trichloride (BCl3), silicon tetrachloride (SiCl4), and carbon tetrachloride (CCl4). By application of a bias voltage to the substrate side when the halogen element139is introduced, the halogen element139can be effectively introduced into the insulating films114and116. As the bias voltage, for example, an ashing apparatus is used, and power density applied to a substrate side of the ashing apparatus can be greater than or equal to 1 W/cm2 and less than or equal to 5 W/cm2. The substrate temperature during introduction of the halogen element139is higher than room temperature and lower than 350° C., preferably higher than or equal to 100° C. and lower than or equal to 250° C., whereby the halogen element can be introduced efficiently into the insulating films114and116. In this embodiment, an ashing apparatus is used. A CF4gas or a SF6gas is introduced into the ashing apparatus and a bias is applied to the substrate side, so that the halogen element139is introduced into the insulating films114and116. Note that by introducing the halogen element139from above the insulating film116, the halogen element can be distributed such that the concentration of the halogen element is higher as it is closer to the upper surface of the insulating film116. <Halogen Element in Insulating Film> Here, the concept of introducing the halogen element139into the insulating films114and116will be described with reference toFIGS.18A to18D. FIG.18Ais a cross-sectional view illustrating an enlarged view of the semiconductor device. The insulating film116shown inFIG.18Aincludes a region145. The region145is a region including a halogen element at high concentrations. In other words, the halogen element is contained at lower concentrations in the vicinity of the oxide semiconductor film108. By introducing a halogen element from the upper surface side of the insulating film116for example, the halogen element can be introduced into the insulating film116such that the concentration of the halogen element is higher as it is closer to the upper surface of the insulating film116. The oxide semiconductor film108might have an n-type conductivity because of the entry of a halogen element into the oxide semiconductor film108; therefore, it is preferable to introduce a halogen element into the insulating film116that is positioned away from the oxide semiconductor film108as illustrated inFIG.18A. On the other hand, a halogen element that enters the oxide semiconductor film108might be bonded to a constituent element of the oxide semiconductor film108and be brought into a stable state; accordingly, variations in reliability tests (e.g., positive gate bias temperature tests) might be reduced. In the case where fluorine is used as a halogen element and an In—Ga—Zn-based oxide is used as the oxide semiconductor film108, for example, fluorine and In might be bonded to each other to be form a stable state. <Silicon Oxide Containing Fluorine> Next, the concept of introducing fluorine as a halogen element into silicon oxide used as the insulating film116inFIG.18Awill be described below with reference toFIGS.18B to18D. Silicon oxide (SiO2) including two oxygen atoms per silicon atom is assumed. One silicon atom is bonded to four oxygen atoms, and one oxygen atom is bonded to two silicon atoms (seeFIG.18B). When two fluorine atoms enter the silicon oxide, bonds of one oxygen atom to two silicon atoms are cut ( . . . Si—O—Si . . . +2F→ . . . Si—O—Si . . . +2F). Then, the fluorine atoms are bonded to the silicon atoms whose bonds to the oxygen atom have been cut ( . . . Si—O—Si . . . +2F→ . . . Si—F F—Si . . . +O). At this time, the oxygen atom whose bonds have been cut becomes excess oxygen (seeFIG.18C). The excess oxygen contained in silicon oxide can reduce oxygen vacancies in the oxide semiconductor film Oxygen vacancies in the oxide semiconductor film serve as hole traps or the like. Accordingly, excess oxygen contained in silicon oxide can lead to stable electrical characteristics of the transistor. Furthermore, when one fluorine atom and one hydrogen atom enter silicon oxide, a bond of one of four oxygen atoms bonded to one silicon atom is cut ( . . . Si—O—Si . . . +F+H→ . . . Si—O—Si . . . +F+H). Then, the fluorine atom is bonded to the silicon atom whose bond to the oxygen atom has been cut ( . . . Si—O—Si . . . +F+H→ . . . Si—F—O—Si . . . +H). Then, the oxygen atom having been bonded to the silicon atom is bonded to the hydrogen atom and is terminated ( . . . Si—F—O—Si . . . +H→ . . . Si—F H—O—Si . . . ; seeFIG.18D). When silicon oxide includes hydrogen traps, the hydrogen concentration of the oxide semiconductor film can be reduced. Note that hydrogen is an impurity in the oxide semiconductor film. For example, when hydrogen enters oxygen vacancy sites in an oxide semiconductor film, electrons serving as carriers might be generated. Thus, when silicon oxide includes hydrogen traps, the carrier density in the channel formation region can be lowered; as a result, the threshold voltage of the transistor can be shifted in the positive direction by the amount corresponding to the reduction of the carrier density. In other words, the transistor can have electrical characteristics close to normally-off characteristics. Hydrogen trapped in silicon oxide requires high energy to be eliminated. Accordingly, elimination of the trapped hydrogen is hard to occur in silicon oxide. As described above, when fluorine is contained in silicon oxide, generation of excess oxygen and/or the trap of hydrogen occurs. Note that in the case where excess oxygen is consumed to reduce oxygen vacancies in the oxide semiconductor film, the amount of oxygen in the silicon oxide becomes smaller than that before fluorine enters the silicon oxide. In the case where hydrogen in the oxide semiconductor film is trapped, the amount of hydrogen in the silicon oxide becomes larger than that before fluorine enters the silicon oxide. In order for the transistor to have stable electrical characteristics which are close to normally-off characteristics, excess oxygen and hydrogen traps are set at adequate amounts, which are attained for example by setting the fluorine concentration higher than the hydrogen concentration in the silicon oxide. After the introduction of the halogen element139, the steps shown inFIG.9CandFIGS.10A and10Bare performed, whereby a semiconductor device in which the insulating films114and116contain the halogen element can be manufactured. Containing the halogen element in the insulating films114and116enables further increase of excess oxygen in the insulating films114and116, which is preferable. AlthoughFIG.11Aillustrates an example in which the halogen element139is introduced from above the insulating film116, one embodiment of the present invention is not limited thereto. The halogen element139may be introduced by a method shown inFIG.11BorFIG.11C. FIG.11Bis a cross-sectional view of a manufacturing step in which the halogen element139is introduced after the metal oxide film132is formed as shown inFIG.9C. FIG.11Cis a cross-sectional view of a manufacturing step in which the halogen element139is introduced after the metal oxide film134is formed as shown inFIG.10B. As shown inFIGS.11B and11C, the halogen element139may be introduced into the insulating films114and116through the metal oxide films132and134if it is in a step after the insulating film116is formed. In the case where the manufacturing step shown inFIG.11Bis performed, the metal oxide film132also contains the halogen element139. In the case where the manufacturing step shown inFIG.11Cis performed, the metal oxide films132and134also contain the halogen element139. <Method 3 for Manufacturing Semiconductor Device> Next, a method for manufacturing the transistor150inFIGS.3A to3Cthat is a semiconductor device of one embodiment of the present invention will be described with reference toFIGS.12A to12CandFIGS.13A and13B.FIGS.12A to12CandFIGS.13A and13Bare cross-sectional views illustrating a method for manufacturing the semiconductor device. First, the steps up to the step shown inFIG.8Care performed, and then the insulating films114and116and the metal oxide film132are formed over the insulating film107and the oxide semiconductor film108(seeFIG.12A). Then, oxygen140is introduced into the insulating films114and116through the metal oxide film132(seeFIG.12B). Then, the metal oxide film134is formed over the metal oxide film132(seeFIG.12C). Next, a mask is formed over the metal oxide film134by a lithography process, and the openings141aand141bare formed in desired regions in the insulating films114and116and the metal oxide films132and134. Note that the openings141aand141breach the oxide semiconductor film108(seeFIG.13A). Then, a conductive film is formed over the oxide semiconductor film108and the metal oxide film134to cover the openings141aand141b, a mask is formed over the conductive film through a lithography process, and the conductive film is processed into desired shapes, whereby the conductive films112aand112bare formed (seeFIG.13B). Through the above process, the transistor150illustrated inFIGS.3A to3Ccan be manufactured. Note that the transistor160inFIGS.4A to4Ccan be manufactured in such a manner that the insulating films114and116are left over a channel region of the oxide semiconductor film108at the formation of the openings141aand141b. <Method 4 for Manufacturing Semiconductor Device> Next, a method for manufacturing the transistor170that is a semiconductor device of one embodiment of the present invention will be described with reference toFIGS.14A to14DandFIGS.15A to15D.FIGS.14A and14CandFIGS.15A and15Care each a cross-sectional view in the channel length direction of the transistor170in the manufacturing process, andFIGS.14B and14DandFIGS.15B and15Dare each a cross-sectional view in the channel width direction of the transistor170in the manufacturing process. First, the steps up to the step inFIG.10Bare performed (seeFIGS.14A and14B). Next, a mask is formed over the metal oxide film134through a lithography process, and the opening142cis formed in a desired region in the insulating films114and116and the metal oxide films132and134. In addition, a mask is formed over the metal oxide film134through a lithography process, and the openings142aand142bare formed in desired regions in the insulating films106,107,114, and116, and the metal oxide films132and134. Note that the opening142creaches the conductive film112b. The openings142aand142breach the conductive film104(seeFIGS.14C and14D). Note that the openings142aand142band the opening142cmay be formed in the same step or may be formed by different steps. In the case where the openings142aand142band the opening142care formed in the same step, for example, a gray-tone mask or a half-tone mask can be used. Next, a conductive film120is formed over the metal oxide film134to cover the openings142a,142b, and142c(seeFIGS.15A and15B). For the conductive film120, for example, a material containing one of indium (In), zinc (Zn), and tin (Sn) can be used. In particular, for the conductive film120, a light-transmitting conductive material such as indium oxide containing tungsten oxide, indium zinc oxide containing tungsten oxide, indium oxide containing titanium oxide, indium tin oxide containing titanium oxide, indium tin oxide, indium zinc oxide, or indium tin oxide containing silicon oxide can be used. Moreover, the conductive film120is favorably formed using the same kind of material as the metal oxide film132, in which case the manufacturing cost can be reduced. The conductive film120can be formed by a sputtering method, for example. In this embodiment, a 110-nm-thick ITSO film is formed by a sputtering method. Next, a mask is formed over the conductive film120through a lithography process, and the conductive film120is processed into desired shapes to form the conductive films120aand120b(seeFIGS.15C and15D). Through the above process, the transistor170illustrated inFIGS.5A to5Ccan be manufactured. In Embodiment 1, one embodiment of the present invention has been described. Note that one embodiment of the present invention is not limited to the above examples. In other words, various embodiments of the invention are described in this embodiment and the other embodiments, and one embodiment of the present invention is not limited to a particular embodiment. For example, an example in which an oxide semiconductor film is included in a channel region is described in this embodiment; however, one embodiment of the present invention is not limited to this example. Depending on cases or conditions, silicon, germanium, silicon germanium, silicon carbide, gallium arsenide, aluminum gallium arsenide, indium phosphide, gallium nitride, an organic semiconductor, or the like may be used in one embodiment of the present invention. The structure and method described in this embodiment can be implemented by being combined as appropriate with any of the other structures and methods described in the other embodiments. Embodiment 2 In this embodiment, the structure of an oxide semiconductor film included in a semiconductor device of one embodiment of the present invention will be described in detail. First, structures that can be included in an oxide semiconductor film will be described below. An oxide semiconductor is classified into a single crystal oxide semiconductor and a non-single-crystal oxide semiconductor. Examples of a non-single-crystal oxide semiconductor include a c-axis aligned crystalline oxide semiconductor (CAAC-OS), a polycrystalline oxide semiconductor, a nanocrystalline oxide semiconductor (nc-OS), an amorphous-like oxide semiconductor (a-like OS), and an amorphous oxide semiconductor. In addition, examples of a crystalline oxide semiconductor include a single crystal oxide semiconductor, a CAAC-OS, a polycrystalline oxide semiconductor, and a microcrystalline oxide semiconductor. From another perspective, an oxide semiconductor is classified into an amorphous oxide semiconductor and a crystalline oxide semiconductor. Examples of a crystalline oxide semiconductor include a single crystal oxide semiconductor, a CAAC-OS, a polycrystalline oxide semiconductor, and an nc-OS. It is known that an amorphous structure is generally defined as being metastable and unfixed, and being isotropic and having no non-uniform structure. In other words, an amorphous structure has a flexible bond angle and a short-range order but does not have a long-range order. This means that an inherently stable oxide semiconductor cannot be regarded as a completely amorphous oxide semiconductor. Moreover, an oxide semiconductor that is not isotropic (e.g., an oxide semiconductor that has a periodic structure in a microscopic region) cannot be regarded as a completely amorphous oxide semiconductor. Note that an a-like OS has a periodic structure in a microscopic region, but at the same time has an unstable structure as described below. For this reason, an a-like OS has physical properties similar to those of an amorphous oxide semiconductor. Even when an amorphous oxide semiconductor having an unstable structure as one of definitions can be used for a channel formation region of a transistor, the transistor may be insufficient for practical use as a product. The same matter applies to an a-like OS. Thus, it is preferable that components of an amorphous oxide semiconductor and an a-like OS be rarely included or be not included at all in products. <CAAC-OS> A CAAC-OS is one of oxide semiconductors having a plurality of c-axis aligned crystal parts (also referred to as pellets). Note that a CAAC-OS can be referred to as an oxide semiconductor including c-axis aligned nanocrystals (CANC). In a combined analysis image (also referred to as a high-resolution TEM image) of a bright-field image and a diffraction pattern of a CAAC-OS, which is obtained using a transmission electron microscope (TEM), a plurality of pellets can be observed. However, in the high-resolution TEM image, a boundary between pellets, that is, a grain boundary is not clearly observed. Thus, in the CAAC-OS, a reduction in electron mobility due to the grain boundary is less likely to occur. FIG.19Ashows an example of a high-resolution TEM image of a cross section of the CAAC-OS which is obtained from a direction substantially parallel to the sample surface. Here, the TEM image is obtained with a spherical aberration corrector function. The high-resolution TEM image obtained with a spherical aberration corrector function is particularly referred to as a Cs-corrected high-resolution TEM image in the following description. Note that the Cs-corrected high-resolution TEM image can be obtained with, for example, an atomic resolution analytical electron microscope JEM-ARM200F manufactured by JEOL Ltd. The CAAC-OS observed with a TEM will be described below.FIG.19Ashows an example of a high-resolution TEM image of a cross section of the CAAC-OS layer which is observed from a direction substantially parallel to the sample surface. The high-resolution TEM image is obtained with a spherical aberration corrector function. The high-resolution TEM image obtained with a spherical aberration corrector function is particularly referred to as a Cs-corrected high-resolution TEM image. The Cs-corrected high-resolution TEM image can be obtained with, for example, an atomic resolution analytical electron microscope JEM-ARM200F manufactured by JEOL Ltd. FIG.19Bis an enlarged Cs-corrected high-resolution TEM image of a region (1) inFIG.19A.FIG.19Bshows that metal atoms are arranged in a layered manner in a pellet. Each metal atom layer has a configuration reflecting unevenness of a surface over which the CAAC-OS is formed (hereinafter, the surface is referred to as a formation surface) or a top surface of the CAAC-OS, and is arranged parallel to the formation surface or the top surface of the CAAC-OS. As shown inFIG.19B, the CAAC-OS has a characteristic atomic arrangement. The characteristic atomic arrangement is denoted by an auxiliary line inFIG.19C.FIGS.19B and19Cprove that the size of a pellet is approximately 1 nm to 3 nm, and the size of a space caused by tilt of the pellets is approximately 0.8 nm. Therefore, the pellet can also be referred to as a nanocrystal (nc). Here, according to the Cs-corrected high-resolution TEM images, the schematic arrangement of pellets5100of a CAAC-OS over a substrate5120is illustrated by such a structure in which bricks or blocks are stacked (seeFIG.19D). The part in which the pellets are tilted as observed inFIG.19Ccorresponds to a region5161shown inFIG.19D. FIG.20Ashows a Cs-corrected high-resolution TEM image of a plane of the CAAC-OS observed from a direction substantially perpendicular to the sample surface.FIGS.20B,20C, and20D are enlarged Cs-corrected high-resolution TEM images of regions (1), (2), and (3) inFIG.20A, respectively.FIGS.20B,20C, and20Dindicate that metal atoms are arranged in a triangular, quadrangular, or hexagonal configuration in a pellet. However, there is no regularity of arrangement of metal atoms between different pellets. Next, a CAAC-OS analyzed by X-ray diffraction (XRD) will be described. For example, when the structure of a CAAC-OS including an InGaZnO4crystal is analyzed by an out-of-plane method, a peak appears at a diffraction angle (2θ) of around 31° as shown inFIG.21A. This peak is derived from the (009) plane of the InGaZnO4crystal, which indicates that crystals in the CAAC-OS have c-axis alignment, and that the c-axes are aligned in a direction substantially perpendicular to the formation surface or the top surface of the CAAC-OS. Note that in structural analysis of the CAAC-OS by an out-of-plane method, another peak may appear when 2θ is around 36°, in addition to the peak at 2θ of around 31°. The peak of 2θ at around 36° indicates that a crystal having no c-axis alignment is included in part of the CAAC-OS. It is preferable that in the CAAC-OS analyzed by an out-of-plane method, a peak appear when 29 is around 31° and that a peak not appear when 2θ is around 36°. On the other hand, in structural analysis of the CAAC-OS by an in-plane method in which an X-ray is incident on a sample in a direction substantially perpendicular to the c-axis, a peak appears when 2θ is around 56°. This peak is derived from the (110) plane of the InGaZnO4crystal. For the CAAC-OS, when analysis (ϕ scan) is performed with 2θ fixed at around 56° and with the sample rotated using a normal vector of the sample surface as an axis (ϕ axis), as shown inFIG.21B, a peak is not clearly observed. In contrast, for a single crystal oxide semiconductor of InGaZnO4, when ϕ scan is performed with 2θ fixed at around 56°, as shown inFIG.21C, six peaks which are derived from crystal planes equivalent to the (110) plane are observed. Accordingly, the structural analysis using XRD shows that the directions of a-axes and b-axes are irregularly oriented in the CAAC-OS. Next, a CAAC-OS analyzed by electron diffraction will be described. For example, when an electron beam with a probe diameter of 300 nm is incident on a CAAC-OS including an InGaZnO4crystal in a direction parallel to the sample surface, a diffraction pattern (also referred to as a selected-area transmission electron diffraction pattern) shown inFIG.22Acan be obtained. In this diffraction pattern, spots derived from the (009) plane of an InGaZnO4crystal are included. Thus, the electron diffraction also indicates that pellets included in the CAAC-OS have c-axis alignment and that the c-axes are aligned in a direction substantially perpendicular to the formation surface or the top surface of the CAAC-OS. Meanwhile,FIG.22Bshows a diffraction pattern obtained in such a manner that an electron beam with a probe diameter of 300 nm is incident on the same sample in a direction perpendicular to the sample surface. As shown inFIG.22B, a ring-like diffraction pattern is observed. Thus, the electron diffraction also indicates that the a-axes and b-axes of the pellets included in the CAAC-OS do not have regular alignment. The first ring inFIG.22Bis considered to be derived from the (010) plane, the (100) plane, and the like of the InGaZnO4crystal. The second ring inFIG.22Bis considered to be derived from the (110) plane and the like. Moreover, the CAAC-OS is an oxide semiconductor having a low density of defect states. Defects in the oxide semiconductor are, for example, a defect due to impurity and oxygen vacancies. Therefore, the CAAC-OS can be regarded as an oxide semiconductor with a low impurity concentration, or an oxide semiconductor having a small number of oxygen vacancies. The impurity contained in the oxide semiconductor might serve as a carrier trap or serve as a carrier generation source. Furthermore, oxygen vacancies in the oxide semiconductor serve as carrier traps or serve as carrier generation sources when hydrogen is captured therein. Note that the impurity means an element other than the main components of the oxide semiconductor, such as hydrogen, carbon, silicon, or a transition metal element. For example, an element (specifically, silicon or the like) having higher strength of bonding to oxygen than a metal element contained in an oxide semiconductor extracts oxygen from the oxide semiconductor, which results in disorder of the atomic arrangement and reduced crystallinity of the oxide semiconductor. A heavy metal such as iron or nickel, argon, carbon dioxide, or the like has a large atomic radius (or molecular radius), and thus disturbs the atomic arrangement of the oxide semiconductor and decreases crystallinity. An oxide semiconductor having a low density of defect states (a small number of oxygen vacancies) can have a low carrier density. Such an oxide semiconductor is referred to as a highly purified intrinsic or substantially highly purified intrinsic oxide semiconductor. A CAAC-OS has a low impurity concentration and a low density of defect states. That is, a CAAC-OS is likely to be highly purified intrinsic or substantially highly purified intrinsic oxide semiconductors. Thus, a transistor including a CAAC-OS rarely has negative threshold voltage (is rarely normally on). The highly purified intrinsic or substantially highly purified intrinsic oxide semiconductor has few carrier traps. An electric charge trapped by the carrier traps in the oxide semiconductor takes a long time to be released. The trapped electric charge may behave like a fixed electric charge. Thus, the transistor which includes the oxide semiconductor having a high impurity concentration and a high density of defect states might have unstable electrical characteristics. However, a transistor including a CAAC-OS has small variation in electrical characteristics and high reliability. Since the CAAC-OS has a low density of defect states, carriers generated by light irradiation or the like are less likely to be trapped in defect states. Therefore, in a transistor using the CAAC-OS, change in electrical characteristics due to irradiation with visible light or ultraviolet light is small. <nc-OS> An nc-OS has a region in which a crystal part is observed and a region in which a crystal part is not clearly observed in a high-resolution TEM image. In most cases, the size of a crystal part included in the nc-OS is greater than or equal to 1 nm and less than or equal to 100 nm, or greater than or equal to 1 nm and less than or equal to 10 nm. An oxide semiconductor including a nanocrystal that is a microcrystal with a size greater than or equal to 1 nm and less than or equal to 10 nm, or a size greater than or equal to 1 nm and less than or equal to 3 nm is specifically referred to as an nc-OS. In a high-resolution TEM image of the nc-OS, for example, a grain boundary is not clearly observed in some cases. Note that there is a possibility that the origin of the nanocrystal is the same as that of a pellet in a CAAC-OS. Therefore, a crystal part of the nc-OS may be referred to as a pellet in the following description. In the nc-OS, a microscopic region (for example, a region with a size greater than or equal to 1 nm and less than or equal to 10 nm, in particular, a region with a size greater than or equal to 1 nm and less than or equal to 3 nm) has a periodic atomic arrangement. There is no regularity of crystal orientation between different pellets in the nc-OS. Thus, the orientation of the whole film is not observed. Accordingly, in some cases, the nc-OS cannot be distinguished from an amorphous oxide semiconductor, depending on an analysis method. For example, when the nc-OS is subjected to structural analysis by an out-of-plane method with an XRD apparatus using an X-ray having a diameter larger than the size of a pellet, a peak which shows a crystal plane does not appear. Furthermore, a diffraction pattern like a halo pattern is observed when the nc-OS is subjected to electron diffraction using an electron beam with a probe diameter (e.g., 50 nm or larger) that is larger than the size of a pellet (the electron diffraction is also referred to as selected-area electron diffraction). Meanwhile, spots appear in a nanobeam electron diffraction pattern of the nc-OS when an electron beam having a probe diameter close to or smaller than the size of a pellet is applied. Moreover, in a nanobeam electron diffraction pattern of the nc-OS, regions with high luminance in a circular (ring) pattern are shown in some cases. Also in a nanobeam electron diffraction pattern of the nc-OS layer, a plurality of spots is shown in a ring-like region in some cases. Since there is no regularity of crystal orientation between the pellets (nanocrystals) as mentioned above, the nc-OS can also be referred to as an oxide semiconductor including random aligned nanocrystals (RANC) or an oxide semiconductor including non-aligned nanocrystals (NANC). The nc-OS is an oxide semiconductor having more regularity than an amorphous oxide semiconductor. Therefore, the nc-OS is likely to have a lower density of defect states than an amorphous oxide semiconductor. Note that there is no regularity of crystal orientation between different pellets in the nc-OS. Therefore, the nc-OS has a higher density of defect states than the CAAC-OS. <Amorphous Oxide Semiconductor> The amorphous oxide semiconductor is such an oxide semiconductor having disordered atomic arrangement and no crystal part. An example of the amorphous oxide semiconductor is an oxide semiconductor with a non-crystalline state like quartz. In a high-resolution TEM image of the amorphous oxide semiconductor, crystal parts cannot be found. When the amorphous oxide semiconductor is subjected to structural analysis by an out-of-plane method with an XRD apparatus, a peak which shows a crystal plane does not appear. A halo pattern is observed when the amorphous oxide semiconductor is subjected to electron diffraction. Furthermore, a spot is not observed and a halo pattern appears when the amorphous oxide semiconductor is subjected to nanobeam electron diffraction. There are various understandings of an amorphous structure. For example, a structure whose atomic arrangement does not have ordering at all is called a completely amorphous structure. Meanwhile, a structure which does not have long-range ordering but might have ordering within the range from an atom to the nearest neighbor atom or the second-nearest neighbor atom is called an amorphous structure in some cases. Therefore, the strictest definition does not permit an oxide semiconductor to be called an amorphous oxide semiconductor as long as even a negligible degree of ordering is present in an atomic arrangement. At least an oxide semiconductor having long-term ordering cannot be called an amorphous oxide semiconductor. Accordingly, because of the presence of a crystal part, for example, a CAAC-OS and an nc-OS cannot be called an amorphous oxide semiconductor or a completely amorphous oxide semiconductor. <a-Like OS> In a high-resolution TEM image of the a-like OS, a void may be observed. Furthermore, in the high-resolution TEM image, there are a region where a crystal part is clearly observed and a region where a crystal part is not observed. The a-like OS has an unstable structure because it contains a void. To verify that an a-like OS has an unstable structure as compared with a CAAC-OS and an nc-OS, a change in structure caused by electron irradiation will be described below. An a-like OS (referred to as Sample A), an nc-OS (referred to as Sample B), and a CAAC-OS (referred to as Sample C) are prepared as samples subjected to electron irradiation. Each of the samples is an In—Ga—Zn oxide. First, a high-resolution cross-sectional TEM image of each sample is obtained. The high-resolution cross-sectional TEM images show that all the samples have crystal parts. Note that a crystal part is determined as follows. It is known that a unit cell of the InGaZnO4crystal has a structure in which nine layers including three In—O layers and six Ga—Zn—O layers are stacked in the c-axis direction. The distance between the adjacent layers is equivalent to the lattice spacing on the (009) plane (also referred to as d value). The value is calculated to be 0.29 nm from crystal structural analysis. Accordingly, a portion where the lattice spacing between lattice fringes is greater than or equal to 0.28 nm and less than or equal to 0.30 nm is regarded as a crystal part of InGaZnO4. Each of lattice fringes corresponds to the a-b plane of the InGaZnO4crystal. FIG.23shows the change in the average size of crystal parts (at 22 points to 45 points) in each sample. Note that the crystal part size corresponds to the length of a lattice fringe.FIG.23indicates that the crystal part size in the a-like OS increases with an increase in the cumulative electron dose. Specifically, as shown by (1) inFIG.23, a crystal part of approximately 1.2 nm at the start of TEM observation grows to a size of approximately 2.6 nm at a cumulative electron dose of 4.2×108e−/nm2. In contrast, the crystal part size in the nc-OS and the CAAC-OS shows little change from the start of electron irradiation to a cumulative electron dose of 4.2×108 e−/nm2. Specifically, as shown by (2) and (3) inFIG.23, the average crystal sizes in an nc-OS and a CAAC-OS are approximately 1.4 nm and approximately 2.1 nm, respectively, regardless of the cumulative electron dose. In this manner, growth of the crystal part in the a-like OS is induced by electron irradiation. In contrast, in the nc-OS and the CAAC-OS, growth of the crystal part is hardly induced by electron irradiation. Therefore, the a-like OS has an unstable structure as compared with the nc-OS and the CAAC-OS. The a-like OS has a lower density than the nc-OS and the CAAC-OS because it contains a void. Specifically, the density of the a-like OS is higher than or equal to 78.6% and lower than 92.3% of the density of the single crystal oxide semiconductor having the same composition. The density of each of the nc-OS and the CAAC-OS is higher than or equal to 92.3% and lower than 100% of the density of the single crystal oxide semiconductor having the same composition. Note that it is difficult to deposit an oxide semiconductor layer having a density of lower than 78% of the density of the single crystal oxide semiconductor layer. For example, for an oxide semiconductor having an atomic ratio of In:Ga:Zn=1:1:1, the density of single crystal InGaZnO4with a rhombohedral crystal structure is 6.357 g/cm3. Accordingly, for the oxide semiconductor having an atomic ratio of In:Ga:Zn=1:1:1, the density of the a-like OS is higher than or equal to 5.0 g/cm3 and lower than 5.9 g/cm3. For example, for the oxide semiconductor having an atomic ratio of In:Ga:Zn=1:1:1, the density of each of the nc-OS and the CAAC-OS is higher than or equal to 5.9 g/cm3 and lower than 6.3 g/cm3. Note that single crystals with the same composition do not exist in some cases. In that case, single crystal oxide semiconductor layers with different compositions are combined at a desired ratio, which makes it possible to calculate density equivalent to that of a single crystal oxide semiconductor layer with the desired composition. The density of a single crystal oxide semiconductor having the desired composition can be calculated using a weighted average according to the combination ratio of the single crystal oxide semiconductors with different compositions. Note that it is preferable to use as few kinds of single crystal oxide semiconductors as possible to calculate the density. As described above, oxide semiconductors have various structures and various properties. Note that an oxide semiconductor may be a stacked film including two or more films of an amorphous oxide semiconductor, an a-like OS, a microcrystalline oxide semiconductor, and a CAAC-OS, for example. The semiconductor device of one embodiment of the present invention can be formed using an oxide semiconductor film having any of the above structures. <Formation Method of CAAC-OS Film> An example of a method for forming a CAAC-OS film will be described below. FIG.24is a schematic view illustrating the inside of a deposition chamber. The CAAC-OS film can be formed by a sputtering method. As shown inFIG.24, a substrate5220and a target5230are arranged to face each other. Plasma5240is generated between the substrate5220and the target5230. The plasma5240includes an ion5201generated by ionization of a composition of a sputtering gas. The ion5201is accelerated to move toward the target5230, and when the ion5201collides with the target5230, a pellet5200that is a pellet-like particle is separated from the target5230. At that time, a particle5203formed from an atom contained in the target5230is concurrently separated. Then, the pellet5200and the particle5203receive electric charge in the plasma5240and thus are charged. An oxide thin film5206has been already deposited over the substrate5220. After reaching a surface of the oxide thin film5206, the pellet5200and the particle5203are deposited to avoid another pellet5200. This deposition is caused by repelling force (repulsive force) generated on the surfaces of the pellets5200that are electrically charged with the same polarity (negative in this case). Note that the substrate5220is heated, and the pellet5200and the particle5203that are deposited migrate over the surface of the substrate5220. The oxide thin film5206and the pellet5200over the substrate5220have cross-sectional shapes shown inFIG.25A. Note that the pellet5200has a shape obtained by cleavage of the target5230. An In-M-Zn oxide (M represents Ti, Ga, Y, Zr, La, Ce, Nd, Sn, or Hf), for example, has a cross-sectional shape shown inFIG.25Band a top-view shape shown inFIG.25C. <Deposition Models of CAAC-OS and nc-OS> A deposition model of the CAAC-OS will be described in detail below. The distance d between the substrate5220and the target5230(also referred to as a target-substrate distance (T-S distance)) is greater than or equal to 0.01 m and less than or equal to 1 m, preferably greater than or equal to 0.02 m and less than or equal to 0.5 m. The deposition chamber is mostly filled with a deposition gas (e.g., an oxygen gas, an argon gas, or a mixed gas containing oxygen at 5 vol % or higher) and the pressure in the deposition chamber is controlled to be higher than or equal to 0.01 Pa and lower than or equal to 100 Pa, preferably higher than or equal to 0.1 Pa and lower than or equal to 10 Pa. Here, discharge starts by application of a voltage at a certain value or higher to the target5230, and the plasma5240is observed. The magnetic field forms a high-density plasma region in the vicinity of the target5230. In the high-density plasma region, the deposition gas is ionized, so that an ion5201is generated. Examples of the ion5201include an oxygen cation (O+) and an argon cation (Ar+). A heating mechanism may be provided under the substrate5220although not shown in the drawing. The target5230is attached to a backing plate although not shown in the drawing. A plurality of magnets is arranged to face the target5230with the backing plate positioned therebetween. A sputtering method in which the disposition speed is increased by utilizing a magnetic field of magnets is referred to as a magnetron sputtering method. Here, the target5230has a polycrystalline structure which includes a plurality of crystal grains and in which a cleavage plane exists in any of the crystal grains. The ion5201generated in the high-density plasma region is accelerated toward the target5230side by an electric field, and then collides with the target5230. At this time, the pellet5200, which is a flat-plate-like or pellet-like sputtered particle, is separated from the cleavage plane. The cross section and the top-view of the pellet5200is as shown inFIG.25BandFIG.25C, respectively. Note that the structure of the pellet5200may be distorted by an impact of collision of the ion5201. The pellet5200is a flat-plate-like (pellet-like) sputtered particle having a triangle plane, e.g., regular triangle plane. Alternatively, the pellet5200is a flat-plate-like (pellet-like) sputtered particle having a hexagon plane, e.g., regular hexagon plane. However, the shape of a flat plane of the pellet5200is not limited to a triangle or a hexagon. For example, the flat plane may have a shape formed by combining two or more triangles. For example, a quadrangle (e.g., rhombus) may be formed by combining two triangles (e.g., regular triangles). The thickness of the pellet5200is determined in accordance with the kind of the deposition gas and the like. For example, the thickness of the pellet5200is greater than or equal to 0.4 nm and less than or equal to 1 nm, preferably greater than or equal to 0.6 nm and less than or equal to 0.8 nm. In addition, for example, the width of the pellet5200is greater than or equal to 1 nm and less than or equal to 3 nm, preferably greater than or equal to 1.2 nm and less than or equal to 2.5 nm. The surface of the pellet5200may be negatively or positively charged when the pellet5200passes through the plasma5240. That is because, for example, the pellet5200receives a negative charge from O2−in the plasma5240. As a result, oxygen atoms on the surface of the pellet5200may be negatively charged. In addition, when passing through the plasma5240, the pellet5200is sometimes combined with indium, the element M, zinc, oxygen, or the like in the plasma5240to grow up. The pellet5200and the particle5203that have passed through the plasma5240reach a surface of the substrate5220. Note that some of the particles5203are discharged to the outside by a vacuum pump or the like because of their smallness in mass. After the gaps between the pellets5200are filled with the particles5203, a layer with a thickness approximately the same as that of the pellet5200is formed. That is, the CAAC-OS includes nanocrystalline pellets5200in the initial stage. For the deposition model of the CAAC-OS, a plurality of nanocrystalline pellets5200are bonded to each other in the lateral direction over the substrate5220, whereby a first layer is formed. Then, other pellets5200are deposited over the first layer, whereby a second layer is formed. With repetition of this cycle, a structure including a plurality of stacked layers is formed. A deposition way of the pellets5200changes according to the surface temperature of the substrate5220or the like. For example, if the surface temperature of the substrate5220is high, migration of the pellets5200occurs over the substrate5220. As a result, a proportion of the pellets5200that are directly connected with each other without the particles5203increases, whereby a CAAC-OS with high orientation is made. The surface temperature of the substrate5220for formation of the CAAC-OS is higher than or equal to 100° C. and lower than 500° C., preferably higher than or equal to 140° C. and lower than 450° C., or further preferably higher than or equal to 170° C. and lower than 400° C. Therefore, even when a large-sized substrate of the 8th generation or more is used as the substrate5220, a warp or the like hardly occur. On the other hand, if the surface temperature of the substrate5220is low, the migration of the pellets5200over the substrate5220does not easily occur. As a result, the pellets5200are stacked to form an nc-OS or the like with low orientation (seeFIG.26). In the nc-OS, the pellets5200are possibly deposited equidistantly from one another since the pellets5200are negatively charged. Therefore, the nc-OS film has low orientation but some regularity, and thus it has a denser structure than an amorphous oxide semiconductor. When spaces between pellets are extremely small, the pellets may form a large pellet. The inside of the large pellet has a single crystal structure. For example, the size of the pellet may be greater than or equal to 10 nm and less than or equal to 200 nm, greater than or equal to 15 nm and less than or equal to 100 nm, or greater than or equal to 20 nm and less than or equal to 50 nm, when seen from the above. The pellets5200are considered to be deposited on the substrate5220according to the deposition model described above. Thus, a CAAC-OS can be deposited even when a formation surface does not have a crystal structure; therefore, a growth mechanism in this case is different from epitaxial growth. In addition, a uniform film of a CAAC-OS or an nc-OS can be formed even over a large-sized glass substrate or the like. For example, even when the surface of the substrate5220(formation surface) has an amorphous structure (e.g., such as amorphous silicon oxide), a CAAC-OS can be formed. In addition, even when the surface of the substrate5220(formation surface) has an uneven shape, the pellets5200are aligned along the shape. According to the deposition model described above, a CAAC-OS with high crystallinity can be formed even on a film formation surface with an amorphous structure. The structure and method described in this embodiment can be implemented by being combined as appropriate with any of the other structures and methods described in the other embodiments. Embodiment 3 In this embodiment, a display device that includes a semiconductor device of one embodiment of the present invention is described with reference toFIGS.27A to27C. <Display Device> The display device illustrated inFIG.27Aincludes a region including pixels of display elements (hereinafter the region is referred to as a pixel portion502), a circuit portion provided outside the pixel portion502and including a circuit for driving the pixels (hereinafter the portion is referred to as a driver circuit portion504), circuits each having a function of protecting an element (hereinafter the circuits are referred to as protection circuits506), and a terminal portion507. Note that the protection circuits506are not necessarily provided. A part or the whole of the driver circuit portion504is preferably formed over a substrate over which the pixel portion502is formed, in which case the number of components and the number of terminals can be reduced. When a part or the whole of the driver circuit portion504is not formed over the substrate over which the pixel portion502is formed, the part or the whole of the driver circuit portion504can be mounted by COG or tape automated bonding (TAB). The pixel portion502includes a plurality of circuits for driving display elements arranged in X rows (X is a natural number of 2 or more) and Y columns (Y is a natural number of 2 or more) (hereinafter, such circuits are referred to as pixel circuits501). The driver circuit portion504includes driver circuits such as a circuit for supplying a signal (scan signal) to select a pixel (hereinafter, the circuit is referred to as a gate driver504a) and a circuit for supplying a signal (data signal) to drive a display element in a pixel (hereinafter, the circuit is referred to as a source driver504b). The gate driver504aincludes a shift register or the like. The gate driver504areceives a signal for driving the shift register through the terminal portion507and outputs a signal. For example, the gate driver504areceives a start pulse signal, a clock signal, or the like and outputs a pulse signal. The gate driver504ahas a function of controlling the potentials of wirings supplied with scan signals (hereinafter, such wirings are referred to as scan lines GL_1to GL_X). Note that a plurality of gate drivers504amay be provided to control the scan lines GL_1to GL_X separately. Alternatively, the gate driver504ahas a function of supplying an initialization signal. Without being limited thereto, the gate driver504acan supply another signal. The source driver504bincludes a shift register or the like. The source driver504breceives a signal (video signal) from which a data signal is derived, as well as a signal for driving the shift register, through the terminal portion507. The source driver504bhas a function of generating a data signal to be written to the pixel circuit501which is based on the video signal. In addition, the source driver504bhas a function of controlling output of a data signal in response to a pulse signal produced by input of a start pulse signal, a clock signal, or the like. Furthermore, the source driver504bhas a function of controlling the potentials of wirings supplied with data signals (hereinafter such wirings are referred to as data lines DL_1to DL_Y). Alternatively, the source driver504bhas a function of supplying an initialization signal. Without being limited thereto, the source driver504bcan supply another signal. The source driver504bincludes a plurality of analog switches or the like, for example. The source driver504bcan output, as the data signals, signals obtained by time-dividing the video signal by sequentially turning on the plurality of analog switches. The source driver504bmay include a shift register or the like. A pulse signal and a data signal are input to each of the plurality of pixel circuits501through one of the plurality of scan lines GL supplied with scan signals and one of the plurality of data lines DL supplied with data signals, respectively. Writing and holding of the data signal to and in each of the plurality of pixel circuits501are controlled by the gate driver504a. For example, to the pixel circuit501in the m-th row and the n-th column (m is a natural number of less than or equal to X, and n is a natural number of less than or equal to Y), a pulse signal is input from the gate driver504athrough the scan line GL_m, and a data signal is input from the source driver504bthrough the data line DL_n in accordance with the potential of the scan line GL_m. The protection circuit506shown inFIG.27Ais connected to, for example, the scan line GL between the gate driver504aand the pixel circuit501. Alternatively, the protection circuit506is connected to the data line DL between the source driver504band the pixel circuit501. Alternatively, the protection circuit506can be connected to a wiring between the gate driver504aand the terminal portion507. Alternatively, the protection circuit506can be connected to a wiring between the source driver504band the terminal portion507. Note that the terminal portion507means a portion having terminals for inputting power, control signals, and video signals to the display device from external circuits. The protection circuit506is a circuit that electrically connects a wiring connected to the protection circuit to another wiring when a potential out of a certain range is applied to the wiring connected to the protection circuit. As illustrated inFIG.27A, the protection circuits506are provided for the pixel portion502and the driver circuit portion504, so that the resistance of the display device to overcurrent generated by electrostatic discharge (ESD) or the like can be improved. Note that the configuration of the protection circuits506is not limited to that, and for example, the protection circuit506may be configured to be connected to the gate driver504aor the protection circuit506may be configured to be connected to the source driver504b. Alternatively, the protection circuit506may be configured to be connected to the terminal portion507. InFIG.27A, an example in which the driver circuit portion504includes the gate driver504aand the source driver504bis shown; however, the structure is not limited thereto. For example, only the gate driver504amay be formed and a separately prepared substrate where a source driver circuit is formed (e.g., a driver circuit substrate formed with a single crystal semiconductor film or a polycrystalline semiconductor film) may be mounted. Each of the plurality of pixel circuits501inFIG.27Acan have the structure illustrated inFIG.27B, for example. The pixel circuit501illustrated inFIG.27Bincludes a liquid crystal element570, a transistor550, and a capacitor560. As the transistor550, any of the transistors described in the above embodiments can be used. The potential of one of a pair of electrodes of the liquid crystal element570is set in accordance with the specifications of the pixel circuit501as appropriate. The alignment state of the liquid crystal element570depends on written data. A common potential may be supplied to one of the pair of electrodes of the liquid crystal element570included in each of the plurality of pixel circuits501. Furthermore, the potential supplied to one of the pair of electrodes of the liquid crystal element570in the pixel circuit501in one row may be different from the potential supplied to one of the pair of electrodes of the liquid crystal element570in the pixel circuit501in another row. As a driving method of the display device including the liquid crystal element570, any of the following modes can be used, for example: a twisted nematic (TN) mode, a super-twisted nematic (STN) mode, a vertical alignment (VA) mode, a multi-domain vertical alignment (MVA) mode, a patterned vertical alignment (PVA) mode, an in-plane-switching (IPS) mode, a fringe field switching (FFS) mode, an axially symmetric aligned micro-cell (ASM) mode, an optically compensated birefringence (OCB) mode, a ferroelectric liquid crystal (FLC) mode, an antiferroelectric liquid crystal (AFLC) mode, an FFS mode, a transverse bend alignment (TBA) mode, and the like. Other examples of the driving method of the display device include an electrically controlled birefringence (ECB) mode, a polymer dispersed liquid crystal (PDLC) mode, a polymer network liquid crystal (PNLC) mode, and a guest-host mode. Note that the present invention is not limited to these examples, and various liquid crystal elements and driving methods can be applied to the liquid crystal element and the driving method thereof. In the pixel circuit501in the m-th row and the n-th column, one of a source electrode and a drain electrode of the transistor550is electrically connected to the data line DL_n, and the other is electrically connected to the other of the pair of electrodes of the liquid crystal element570. A gate electrode of the transistor550is electrically connected to the scan line GL_m. The transistor550has a function of controlling whether to write a data signal by being turned on or off. One of a pair of electrodes of the capacitor560is electrically connected to a wiring to which a potential is supplied (hereinafter referred to as a potential supply line VL), and the other is electrically connected to the other of the pair of electrodes of the liquid crystal element570. The potential of the potential supply line VL is set in accordance with the specifications of the pixel circuit501as appropriate. The capacitor560functions as a storage capacitor for storing written data. For example, in the display device including the pixel circuit501inFIG.27B, the pixel circuits501are sequentially selected row by row by the gate driver504aillustrated inFIG.27A, whereby the transistors550are turned on and a data signal is written. When the transistors550are turned off, the pixel circuits501in which the data has been written are brought into a holding state. This operation is sequentially performed row by row; thus, an image can be displayed. Alternatively, each of the plurality of pixel circuits501inFIG.27Acan have the structure illustrated inFIG.27C, for example. The pixel circuit501illustrated inFIG.27Cincludes transistors552and554, a capacitor562, and a light-emitting element572. Any of the transistors described in the above embodiments can be used as one or both of the transistors552and554. One of a source electrode and a drain electrode of the transistor552is electrically connected to a wiring to which a data signal is supplied (hereinafter referred to as a data line DL_n). A gate electrode of the transistor552is electrically connected to a wiring to which a gate signal is supplied (hereinafter referred to as a scan line GL_m). The transistor552has a function of controlling whether to write a data signal by being turned on or off. One of a pair of electrodes of the capacitor562is electrically connected to a wiring to which a potential is supplied (hereinafter referred to as a potential supply line VL_a), and the other is electrically connected to the other of the source electrode and the drain electrode of the transistor552. The capacitor562functions as a storage capacitor for storing written data. One of a source electrode and a drain electrode of the transistor554is electrically connected to the potential supply line VL_a. Furthermore, a gate electrode of the transistor554is electrically connected to the other of the source electrode and the drain electrode of the transistor552. One of an anode and a cathode of the light-emitting element572is electrically connected to a potential supply line VL_b, and the other is electrically connected to the other of the source electrode and the drain electrode of the transistor554. As the light-emitting element572, an organic electroluminescent element (also referred to as an organic EL element) or the like can be used, for example. Note that the light-emitting element572is not limited to an organic EL element; an inorganic EL element including an inorganic material may be used. A high power supply potential VDD is supplied to one of the potential supply line VL_a and the potential supply line VL_b, and a low power supply potential VSS is supplied to the other. For example, in the display device including the pixel circuit501inFIG.27C, the pixel circuits501are sequentially selected row by row by the gate driver504aillustrated inFIG.27A, whereby the transistors552are turned on and a data signal is written. When the transistors552are turned off, the pixel circuits501in which the data has been written are brought into a holding state. Furthermore, the amount of current flowing between the source electrode and the drain electrode of the transistor554is controlled in accordance with the potential of the written data signal. The light-emitting element572emits light with a luminance corresponding to the amount of flowing current. This operation is sequentially performed row by row; thus, an image can be displayed. Although the structures including the liquid crystal element570or the light-emitting element572as a display element of the display device are described in this embodiment, one embodiment of the present invention is not limited to these structures and a variety of elements may be included in the display device. For example, the display device includes at least one of a liquid crystal element, an EL element (e.g., an EL element including organic and inorganic materials, an organic EL element, or an inorganic EL element), an LED (e.g., a white LED, a red LED, a green LED, or a blue LED), a transistor (a transistor that emits light depending on current), an electron emitter, electronic ink, an electrophoretic element, a grating light valve (GLV), a plasma display panel (PDP), a display element using micro electro mechanical systems (MEMS), a digital micromirror device (DMD), a digital micro shutter (DMS), MIRASOL (registered trademark), an interferometric modulator display (IMOD) element, a MEMS shutter display element, an optical-interference-type MEMS display element, an electrowetting element, a piezoelectric ceramic display, a display element using a carbon nanotube, and the like. Alternatively, the display device may include a display medium whose contrast, luminance, reflectivity, transmittance, or the like is changed by electrical or magnetic effect. Examples of display devices including electron emitters are a field emission display (FED) and an SED-type flat panel display (SED: surface-conduction electron-emitter display). Examples of display devices including liquid crystal elements include a liquid crystal display (e.g., a transmissive liquid crystal display, a transflective liquid crystal display, a reflective liquid crystal display, a direct-view liquid crystal display, or a projection liquid crystal display). An example of a display device including electronic ink or electrophoretic elements is electronic paper. In the case of a transflective liquid crystal display or a reflective liquid crystal display, some of or all of pixel electrodes function as reflective electrodes. For example, some or all of pixel electrodes are formed to contain aluminum, silver, or the like. In such a case, a memory circuit such as an SRAM can be provided under the reflective electrodes. Thus, the power consumption can be further reduced. A progressive type display, an interlace type display, or the like can be employed as the display type of the display device of this embodiment. Further, color elements controlled in a pixel at the time of color display are not limited to three colors: R, G, and B (R, G, and B correspond to red, green, and blue, respectively). For example, four pixels of the R pixel, the G pixel, the B pixel, and a W (white) pixel may be included. Alternatively, a color element may be composed of two colors among R, G, and B as in PenTile layout. The two colors may differ among color elements. Alternatively, one or more colors of yellow, cyan, magenta, and the like may be added to RGB. Further, the size of a display region may be different depending on respective dots of the color elements. Embodiments of the disclosed invention are not limited to a display device for color display; the disclosed invention can also be applied to a display device for monochrome display. White light (W) may be emitted from a backlight (e.g., an organic EL element, an inorganic EL element, an LED, or a fluorescent lamp) in the display device. Furthermore, a coloring layer (also referred to as a color filter) may be provided in the display device. As the coloring layer, red (R), green (G), blue (B), yellow (Y), or the like may be combined as appropriate, for example. With the use of the coloring layer, higher color reproducibility can be obtained than in the case without the coloring layer. In this case, by providing a region with the coloring layer and a region without the coloring layer, white light in the region without the coloring layer may be directly utilized for display. By partly providing the region without the coloring layer, a decrease in luminance due to the coloring layer can be suppressed, and 20% to 30% of power consumption can be reduced in some cases when an image is displayed brightly. Note that in the case where full-color display is performed using self-luminous elements such as organic EL elements or inorganic EL elements, the elements may emit light of their respective colors R, G, B, Y, and W. By using self-luminous elements, power consumption can be further reduced as compared to the case of using the coloring layer in some cases. The structures described in this embodiment can be used in appropriate combination with any of the structures described in the other embodiments. Embodiment 4 In this embodiment, a display device including a semiconductor device of one embodiment of the present invention and an electronic device in which the display device is provided with an input device will be described with reference toFIGS.28A and28B,FIGS.29A and29B,FIG.30,FIGS.31A and31B,FIGS.32A and32B, andFIG.33. <Touch Panel> In this embodiment, a touch panel2000including a display device and an input device will be described as an example of an electronic device. In addition, an example in which a touch sensor is used as an input device will be described. FIGS.28A and28Bare perspective views of the touch panel2000. Note thatFIGS.28A and28Billustrate only main components of the touch panel2000for simplicity. The touch panel2000includes a display device2501and a touch sensor2595(seeFIG.28B). The touch panel2000also includes a substrate2510, a substrate2570, and a substrate2590. The substrate2510, the substrate2570, and the substrate2590each have flexibility. Note that one or all of the substrates2510,2570, and2590may be inflexible. The display device2501includes a plurality of pixels over the substrate2510and a plurality of wirings2511through which signals are supplied to the pixels. The plurality of wirings2511are led to a peripheral portion of the substrate2510, and parts of the plurality of wirings2511form a terminal2519. The terminal2519is electrically connected to an FPC2509(1). The substrate2590includes the touch sensor2595and a plurality of wirings2598electrically connected to the touch sensor2595. The plurality of wirings2598are led to a peripheral portion of the substrate2590, and parts of the plurality of wirings2598form a terminal. The terminal is electrically connected to an FPC2509(2). Note that inFIG.28B, electrodes, wirings, and the like of the touch sensor2595provided on the back side of the substrate2590(the side facing the substrate2510) are indicated by solid lines for clarity. As the touch sensor2595, a capacitive touch sensor can be used. Examples of the capacitive touch sensor are a surface capacitive touch sensor and a projected capacitive touch sensor. Examples of the projected capacitive touch sensor are a self capacitive touch sensor and a mutual capacitive touch sensor, which differ mainly in the driving method. The use of a mutual capacitive type is preferable because multiple points can be sensed simultaneously. Note that the touch sensor2595illustrated inFIG.28Bis an example of using a projected capacitive touch sensor. Note that a variety of sensors that can sense proximity or touch of a sensing target such as a finger can be used as the touch sensor2595. The projected capacitive touch sensor2595includes electrodes2591and electrodes2592. The electrodes2591are electrically connected to any of the plurality of wirings2598, and the electrodes2592are electrically connected to any of the other wirings2598. The electrodes2592each have a shape of a plurality of quadrangles arranged in one direction with one corner of a quadrangle connected to one corner of another quadrangle as illustrated inFIGS.28A and28B. The electrodes2591each have a quadrangular shape and are arranged in a direction intersecting with the direction in which the electrodes2592extend. A wiring2594electrically connects two electrodes2591between which the electrode2592is positioned. The intersecting area of the electrode2592and the wiring2594is preferably as small as possible. Such a structure allows a reduction in the area of a region where the electrodes are not provided, reducing variation in transmittance. As a result, variation in luminance of light passing through the touch sensor2595can be reduced. Note that the shapes of the electrodes2591and the electrodes2592are not limited thereto and can be any of a variety of shapes. For example, a structure may be employed in which the plurality of electrodes2591are arranged so that gaps between the electrodes2591are reduced as much as possible, and the electrodes2592are spaced apart from the electrodes2591with an insulating layer interposed therebetween to have regions not overlapping with the electrodes2591. In this case, it is preferable to provide, between two adjacent electrodes2592, a dummy electrode electrically insulated from these electrodes because the area of regions having different transmittances can be reduced. Note that as a material of the conductive films such as the electrodes2591, the electrodes2592, and the wirings2598, that is, wirings and electrodes forming the touch panel, a transparent conductive film containing indium oxide, tin oxide, zinc oxide, or the like (e.g., ITO) can be given. For example, a low-resistance material is preferably used as a material that can be used as the wirings and electrodes forming the touch panel. For example, silver, copper, aluminum, a carbon nanotube, graphene, or a metal halide (such as a silver halide) may be used. Alternatively, a metal nanowire including a plurality of conductors with an extremely small width (for example, a diameter of several nanometers) may be used. Further alternatively, a net-like metal mesh with a conductor may be used. For example, an Ag nanowire, a Cu nanowire, an Al nanowire, an Ag mesh, a Cu mesh, or an Al mesh may be used. For example, in the case of using an Ag nanowire as the wirings and electrodes forming the touch panel, a visible light transmittance of 89% or more and a sheet resistance of 40 Ω/cm2or more and 100 Ω/cm2or less can be achieved. Since the above-described metal nanowire, metal mesh, carbon nanotube, graphene, and the like, which are examples of the material that can be used as the wirings and electrodes forming the touch panel, have high visible light transmittances, they may be used as electrodes of display elements (e.g., a pixel electrode or a common electrode). <Display Device> Next, the display device2501will be described in detail with reference toFIGS.29A and29B.FIGS.29A and29Bcorrespond to cross-sectional views taken along dashed-dotted line X1-X2inFIG.28B. The display device2501includes a plurality of pixels arranged in a matrix. Each of the pixels includes a display element and a pixel circuit for driving the display element. <Structure with EL Element as Display Element> First, a structure that uses an EL element as a display element will be described below with reference toFIG.29A. In the following description, an example of using an EL element that emits white light will be described; however, the EL element is not limited to this element. For example, EL elements that emit light of different colors may be included so that the light of different colors can be emitted from adjacent pixels. For the substrate2510and the substrate2570, for example, a flexible material with a vapor permeability of lower than or equal to 10−5g/(m2·day), preferably lower than or equal to 10−6g/(m2·day) can be favorably used. Alternatively, materials whose thermal expansion coefficients are substantially equal to each other are preferably used for the substrate2510and the substrate2570. For example, the coefficients of linear expansion of the materials are preferably lower than or equal to 1×10−3/K, further preferably lower than or equal to 5×10−5/K, and still further preferably lower than or equal to 1×10−5/K. Note that the substrate2510is a stacked body including an insulating layer2510afor preventing impurity diffusion into the EL element, a flexible substrate2510b, and an adhesive layer2510cfor attaching the insulating layer2510aand the flexible substrate2510bto each other. The substrate2570is a stacked body including an insulating layer2570afor preventing impurity diffusion into the EL element, a flexible substrate2570b, and an adhesive layer2570cfor attaching the insulating layer2570aand the flexible substrate2570bto each other. For the adhesive layer2510cand the adhesive layer2570c, for example, materials that include polyester, polyolefin, polyamide (e.g., nylon, aramid), polyimide, polycarbonate, polyurethane, an acrylic resin, an epoxy resin, or a resin having a siloxane bond can be used. A sealing layer2560is provided between the substrate2510and the substrate2570. The sealing layer2560preferably has a refractive index higher than that of air. In the case where light is extracted to the sealing layer2560side as illustrated inFIG.29A, the sealing layer2560can also serve as an optical element. A sealant may be formed in the peripheral portion of the sealing layer2560. With the use of the sealant, an EL element2550can be provided in a region surrounded by the substrate2510, the substrate2570, the sealing layer2560, and the sealant. Note that an inert gas (such as nitrogen or argon) may be used instead of the sealing layer2560. A drying agent may be provided in the inert gas so as to adsorb moisture or the like. For example, an epoxy-based resin or a glass frit is preferably used as the sealant. As a material used for the sealant, a material which is impermeable to moisture or oxygen is preferably used. The display device2501illustrated inFIG.29Aincludes a pixel2505. The pixel2505includes a light-emitting module2580, the EL element2550and a transistor2502tthat can supply electric power to the EL element2550. Note that the transistor2502tfunctions as part of the pixel circuit. The light-emitting module2580includes the EL element2550and a coloring layer2567. The EL element2550includes a lower electrode, an upper electrode, and an EL layer between the lower electrode and the upper electrode. In the case where the sealing layer2560is provided on the light extraction side, the sealing layer2560is in contact with the EL element2550and the coloring layer2567. The coloring layer2567is positioned in a region overlapping with the EL element2550. Accordingly, part of light emitted from the EL element2550passes through the coloring layer2567and is emitted to the outside of the light-emitting module2580as indicated by an arrow inFIG.29A. The display device2501includes a light-blocking layer2568on the light extraction side. The light-blocking layer2568is provided so as to surround the coloring layer2567. The coloring layer2567is a coloring layer having a function of transmitting light in a particular wavelength region. For example, a color filter for transmitting light in a red wavelength range, a color filter for transmitting light in a green wavelength range, a color filter for transmitting light in a blue wavelength range, a color filter for transmitting light in a yellow wavelength range, or the like can be used. Each color filter can be formed with any of various materials by a printing method, an inkjet method, an etching method using a photolithography technique, or the like. An insulating layer2521is provided in the display device2501. The insulating layer2521covers the transistor2502tand the like. Note that the insulating layer2521has a function of covering the roughness caused by the pixel circuit to provide a flat surface. The insulating layer2521may have a function of suppressing impurity diffusion. This can prevent the reliability of the transistor2502tor the like from being lowered by impurity diffusion. The EL element2550is formed over the insulating layer2521. A partition2528is provided so as to overlap with an end portion of the lower electrode of the EL element2550. Note that a spacer for controlling the distance between the substrate2510and the substrate2570may be formed over the partition2528. A scan line driver circuit2504includes a transistor2503tand a capacitor2503c. Note that the driver circuit can be formed in the same process and over the same substrate as those of the pixel circuits. The wirings2511through which signals can be supplied are provided over the substrate2510. The terminal2519is provided over the wirings2511. The FPC2509(1) is electrically connected to the terminal2519. The FPC2509(1) has a function of supplying a video signal, a clock signal, a start signal, a reset signal, or the like. Note that the FPC2509(1) may be provided with a printed wiring board (PWB). Any of the transistors described in the above embodiments may be used as one or both of the transistors2502tand2503t. The transistors used in this embodiment each include an oxide semiconductor film which is highly purified and in which formation of oxygen vacancies is suppressed. In the transistors, the current in an off state (off-state current) can be made small. Accordingly, an electrical signal such as an image signal can be held for a longer period, and a writing interval can be set longer in an on state. Accordingly, the frequency of refresh operation can be reduced, which leads to an effect of suppressing power consumption. In addition, the transistors used in this embodiment can have relatively high field-effect mobility and thus are capable of high speed operation. For example, with such transistors which can operate at high speed used for the display device2501, a switching transistor of a pixel circuit and a driver transistor in a driver circuit portion can be formed over one substrate. That is, a semiconductor device formed using a silicon wafer or the like is not additionally needed as a driver circuit, by which the number of components of the semiconductor device can be reduced. In addition, by using a transistor which can operate at high speed in a pixel circuit, a high-quality image can be provided. <Structure with Liquid Crystal Element as Display Element> Next, a structure including a liquid crystal element as a display element is described below with reference toFIG.29B. In the description below, a reflective liquid crystal display device that performs display by reflecting external light is described; however, one embodiment of the present invention is not limited to this type of liquid crystal display device. For example, a light source (e.g., a back light or a side light) may be provided to form a transmissive liquid crystal display device or a transflective liquid crystal display device. The display device2501illustrated inFIG.29Bhas the same structure as the display device2501illustrated inFIG.29Aexcept the following points. The pixel2505in the display device2501illustrated inFIG.29Bincludes a liquid crystal element2551and the transistor2502tthat can supply electric power to the liquid crystal element2551. The liquid crystal element2551includes a lower electrode (also referred to as a pixel electrode), an upper electrode, and a liquid crystal layer2529between the lower electrode and the upper electrode. By the application of a voltage between the lower electrode and the upper electrode, the alignment state of the liquid crystal layer2529in the liquid crystal element2551can be changed. Furthermore, in the liquid crystal layer2529, a spacer2530aand a spacer2530bare provided. Although not illustrated inFIG.29B, an alignment film may be provided on each of the upper electrode and the lower electrode on the side in contact with the liquid crystal layer2529. As the liquid crystal layer2529, thermotropic liquid crystal, low-molecular liquid crystal, high-molecular liquid crystal, polymer dispersed liquid crystal, ferroelectric liquid crystal, or antiferroelectric liquid crystal can be used. Such a liquid crystal material exhibits a cholesteric phase, a smectic phase, a cubic phase, a chiral nematic phase, an isotropic phase, or the like depending on conditions. In the case of employing a horizontal electric field mode liquid crystal display device, liquid crystal exhibiting a blue phase for which an alignment film is unnecessary may be used. In the case where a liquid crystal exhibiting a blue phase is used, an alignment film is not necessarily provided, so that rubbing treatment is also unnecessary. Accordingly, electrostatic discharge damage caused by the rubbing treatment can be prevented and defects and damage of the liquid crystal display device in the manufacturing process can be reduced. The spacers2530aand2530bare formed by selectively etching an insulating film. The spacers2530aand2530bare provided in order to control the distance between the substrate2510and the substrate2570(the cell gap). Note that the spacers2530aand2530bmay have different sizes from each other and are preferably have a columnar or spherical shape. Although the spacers2530aand2530bare provided on the substrate2570side in the non-limiting structure inFIG.29B, they may be provided on the substrate2510side. The upper electrode of the liquid crystal element2551is provided on the substrate2570side. An insulating layer2531is provided between the upper electrode and the coloring layer2567and the light-blocking layer2568. The insulating layer2531has a function of covering the roughness caused by the coloring layer2567and the light-blocking layer2568to provide a flat surface. As the insulating layer2531, an organic resin film may be used, for example. The lower electrode of the liquid crystal element2551has a function of a reflective electrode. The display device2501illustrated inFIG.29Bis of a reflective type which performs display by reflecting external light at the lower electrode and making the light pass through the coloring layer2567. Note that in the case of forming a transmissive liquid crystal display device, a transparent electrode is provided as the lower electrode. The display device2501illustrated inFIG.29Bincludes an insulating layer2522. The insulating layer2522covers the transistor2502tand the like. The insulating layer2522has a function of covering the roughness caused by the pixel circuit to provide a flat surface and a function of forming roughness on the lower electrode of the liquid crystal element. In this way, roughness can be formed on the surface of the lower electrode. Therefore, when external light is incident on the lower electrode, the light is reflected diffusely at the surface of the lower electrode, whereby visibility can be improved. Note that in the case of forming a transmissive liquid crystal display device, a structure without such roughness may be employed. <Touch Sensor> Next, the touch sensor2595will be described in detail with reference toFIG.30.FIG.30corresponds to a cross-sectional view taken along dashed-dotted line X3-X4inFIG.28B. The touch sensor2595includes the electrodes2591and the electrodes2592provided in a staggered arrangement on the substrate2590, an insulating layer2593covering the electrodes2591and the electrodes2592, and the wiring2594that electrically connects the adjacent electrodes2591to each other. The electrodes2591and the electrodes2592are formed using a light-transmitting conductive material. As a light-transmitting conductive material, a conductive oxide such as indium oxide, indium tin oxide, indium zinc oxide, zinc oxide, or zinc oxide to which gallium is added can be used. Note that a film containing graphene may be used as well. The film containing graphene can be formed, for example, by reducing a film containing graphene oxide. As a reducing method, a method with application of heat or the like can be employed. The electrodes2591and the electrodes2592may be formed by, for example, depositing a light-transmitting conductive material on the substrate2590by a sputtering method and then removing an unnecessary portion by any of various patterning techniques such as photolithography. Examples of a material for the insulating layer2593are a resin such as an acrylic resin or an epoxy resin, a resin having a siloxane bond, and an inorganic insulating material such as silicon oxide, silicon oxynitride, or aluminum oxide. Openings reaching the electrodes2591are formed in the insulating layer2593, and the wiring2594electrically connects the adjacent electrodes2591. A light-transmitting conductive material can be favorably used as the wiring2594because the aperture ratio of the touch panel can be increased. Moreover, a material with higher conductivity than the conductivities of the electrodes2591and2592can be favorably used for the wiring2594because electric resistance can be reduced. One electrode2592extends in one direction, and a plurality of electrodes2592are provided in the form of stripes. The wiring2594intersects with the electrode2592. Adjacent electrodes2591are provided with one electrode2592provided therebetween. The wiring2594electrically connects the adjacent electrodes2591. Note that the plurality of electrodes2591are not necessarily arranged in the direction orthogonal to one electrode2592and may be arranged to intersect with one electrode2592at an angle of more than 0 degrees and less than 90 degrees. The wiring2598is electrically connected to any of the electrodes2591and2592. Part of the wiring2598functions as a terminal. For the wiring2598, a metal material such as aluminum, gold, platinum, silver, nickel, titanium, tungsten, chromium, molybdenum, iron, cobalt, copper, or palladium or an alloy material containing any of these metal materials can be used. Note that an insulating layer that covers the insulating layer2593and the wiring2594may be provided to protect the touch sensor2595. A connection layer2599electrically connects the wiring2598to the FPC2509(2). As the connection layer2599, any of various anisotropic conductive films (ACF), anisotropic conductive pastes (ACP), or the like can be used. <Touch Panel> Next, the touch panel2000will be described in detail with reference toFIG.31A.FIG.31Acorresponds to a cross-sectional view taken along dashed-dotted line X5-X6inFIG.28A. In the touch panel2000illustrated inFIG.31A, the display device2501described with reference toFIG.29Aand the touch sensor2595described with reference toFIG.30are attached to each other. The touch panel2000illustrated inFIG.31Aincludes an adhesive layer2597and an anti-reflective layer2569in addition to the components described with reference toFIG.29A. The adhesive layer2597is provided in contact with the wiring2594. Note that the adhesive layer2597attaches the substrate2590to the substrate2570so that the touch sensor2595overlaps with the display device2501. The adhesive layer2597preferably has a light-transmitting property. A heat curable resin or an ultraviolet curable resin can be used for the adhesive layer2597. For example, an acrylic resin, a urethane-based resin, an epoxy-based resin, or a siloxane-based resin can be used. The anti-reflective layer2569is positioned in a region overlapping with pixels. As the anti-reflective layer2569, a circularly polarizing plate can be used, for example. Next, a touch panel having a structure different from that illustrated inFIG.31Awill be described with reference toFIG.31B. FIG.31Bis a cross-sectional view of a touch panel2001. The touch panel2001illustrated inFIG.31Bdiffers from the touch panel2000illustrated inFIG.31Ain the position of the touch sensor2595relative to the display device2501. Different parts are described in detail below, and the above description of the touch panel2000is referred to for the other similar parts. The coloring layer2567is positioned under the EL element2550. The EL element2550illustrated inFIG.31Bemits light to the side where the transistor2502tis provided. Accordingly, part of light emitted from the EL element2550passes through the coloring layer2567and is emitted to the outside of the light-emitting module2580as indicated by an arrow inFIG.31B. The touch sensor2595is provided on the substrate2510side of the display device2501. The adhesive layer2597is provided between the substrate2510and the substrate2590and attaches the touch sensor2595to the display device2501. As illustrated inFIG.31AorFIG.31B, light may be emitted from the light-emitting element to one or both of upper and lower sides of the substrate. <Driving Method of Touch Panel> Next, an example of a method for driving a touch panel will be described with reference toFIGS.32A and32B. FIG.32Ais a block diagram illustrating the structure of a mutual capacitive touch sensor.FIG.32Aillustrates a pulse voltage output circuit2601and a current sensing circuit2602. Note that inFIG.32A, six wirings X1to X6represent the electrodes2621to which a pulse voltage is applied, and six wirings Y1to Y6represent the electrodes2622that detect changes in current.FIG.32Aalso illustrates capacitors2603that are each formed in a region where the electrodes2621and2622overlap with each other. Note that functional replacement between the electrodes2621and2622is possible. The pulse voltage output circuit2601is a circuit for sequentially applying a pulse voltage to the wirings X1to X6. By application of a pulse voltage to the wirings X1to X6, an electric field is generated between the electrodes2621and2622of the capacitor2603. When the electric field between the electrodes is shielded, for example, a change occurs in the capacitor2603(mutual capacitance). The approach or contact of a sensing target can be sensed by utilizing this change. The current sensing circuit2602is a circuit for detecting changes in current flowing through the wirings Y1to Y6that are caused by the change in mutual capacitance in the capacitor2603. No change in current value is detected in the wirings Y1to Y6when there is no approach or contact of a sensing target, whereas a decrease in current value is detected when mutual capacitance is decreased owing to the approach or contact of a sensing target. Note that an integrator circuit or the like is used for sensing of current values. FIG.32Bis a timing chart showing input and output waveforms in the mutual capacitive touch sensor illustrated inFIG.32A. InFIG.32B, sensing of a sensing target is performed in all the rows and columns in one frame period.FIG.32Bshows a period when a sensing target is not sensed (not touched) and a period when a sensing target is sensed (touched). Sensed current values of the wirings Y1to Y6are shown as the waveforms of voltage values. A pulse voltage is sequentially applied to the wirings X1to X6, and the waveforms of the wirings Y1to Y6change in accordance with the pulse voltage. When there is no approach or contact of a sensing target, the waveforms of the wirings Y1to Y6change in accordance with changes in the voltages of the wirings X1to X6. The current value is decreased at the point of approach or contact of a sensing target and accordingly the waveform of the voltage value changes. By detecting a change in mutual capacitance in this manner, the approach or contact of a sensing target can be sensed. <Sensor Circuit> AlthoughFIG.32Aillustrates a passive type touch sensor in which only the capacitor2603is provided at the intersection of wirings as a touch sensor, an active type touch sensor including a transistor and a capacitor may be used.FIG.33illustrates an example of a sensor circuit included in an active type touch sensor. The sensor circuit inFIG.33includes the capacitor2603and transistors2611,2612, and2613. A signal G2is input to a gate of the transistor2613. A voltage VRES is applied to one of a source and a drain of the transistor2613, and one electrode of the capacitor2603and a gate of the transistor2611are electrically connected to the other of the source and the drain of the transistor2613. One of a source and a drain of the transistor2611is electrically connected to one of a source and a drain of the transistor2612, and a voltage VSS is applied to the other of the source and the drain of the transistor2611. A signal G1is input to a gate of the transistor2612, and a wiring ML is electrically connected to the other of the source and the drain of the transistor2612. The voltage VSS is applied to the other electrode of the capacitor2603. Next, the operation of the sensor circuit inFIG.33will be described. First, a potential for turning on the transistor2613is supplied as the signal G2, and a potential with respect to the voltage VRES is thus applied to the node n connected to the gate of the transistor2611. Then, a potential for turning off the transistor2613is applied as the signal G2, whereby the potential of the node n is maintained. Then, mutual capacitance of the capacitor2603changes owing to the approach or contact of a sensing target such as a finger, and accordingly the potential of the node n is changed from VRES. In reading operation, a potential for turning on the transistor2612is supplied as the signal G1. A current flowing through the transistor2611, that is, a current flowing through the wiring ML is changed in accordance with the potential of the node n. By sensing this current, the approach or contact of a sensing target can be sensed. In each of the transistors2611,2612, and2613, any of the transistors described in the above embodiments can be used. In particular, it is preferable to use any of the transistors described in the above embodiments as the transistor2613because the potential of the node n can be held for a long time and the frequency of operation of resupplying VRES to the node n (refresh operation) can be reduced. The structures described in this embodiment can be used in appropriate combination with any of the structures described in the other embodiments. Embodiment 5 In this embodiment, a display module and electronic devices that include a semiconductor device of one embodiment of the present invention are described with reference toFIG.34andFIGS.35A to35G. <Display Module> In a display module8000illustrated inFIG.34, a touch panel8004connected to an FPC8003, a display panel8006connected to an FPC8005, a backlight8007, a frame8009, a printed board8010, and a battery8011are provided between an upper cover8001and a lower cover8002. The semiconductor device of one embodiment of the present invention can be used for, for example, the display panel8006. The shapes and sizes of the upper cover8001and the lower cover8002can be changed as appropriate in accordance with the sizes of the touch panel8004and the display panel8006. The touch panel8004can be a resistive touch panel or a capacitive touch panel and can be formed to overlap the display panel8006. A counter substrate (sealing substrate) of the display panel8006can have a touch panel function. A photosensor may be provided in each pixel of the display panel8006to form an optical touch panel. The backlight8007includes light sources8008. Note that although a structure in which the light sources8008are provided over the backlight8007is illustrated inFIG.34, one embodiment of the present invention is not limited to this structure. For example, a structure in which the light sources8008are provided at an end portion of the backlight8007and a light diffusion plate is further provided may be employed. Note that the backlight8007need not be provided in the case where a self-luminous light-emitting element such as an organic EL element is used or in the case where a reflective panel or the like is employed. The frame8009protects the display panel8006and also functions as an electromagnetic shield for blocking electromagnetic waves generated by the operation of the printed board8010. The frame8009may function as a radiator plate. The printed board8010is provided with a power supply circuit and a signal processing circuit for outputting a video signal and a clock signal. As a power source for supplying power to the power supply circuit, an external commercial power source or a power source using the battery8011provided separately may be used. The battery8011can be omitted in the case of using a commercial power source. The display module8000may be additionally provided with a member such as a polarizing plate, a retardation plate, or a prism sheet. <Electronic Device> FIGS.35A to35Gillustrate electronic devices. These electronic devices can each include a housing9000, a display portion9001, a speaker9003, an operation key9005(including a power switch or an operation switch), a connection terminal9006, a sensor9007(a sensor having a function of measuring force, displacement, position, speed, acceleration, angular velocity, rotational frequency, distance, light, liquid, magnetism, temperature, chemical substance, sound, time, hardness, electric field, current, voltage, power, radiation, flow rate, humidity, gradient, oscillation, odor, or infrared rays), a microphone9008, and the like. The electronic devices illustrated inFIGS.35A to35Gcan have a variety of functions, for example, a function of displaying a variety of information (a still image, a moving image, a text image, and the like) on the display portion, a touch panel function, a function of displaying a calendar, the date, the time, and the like, a function of controlling processing with a variety of software (programs), a wireless communication function, a function of being connected to a variety of computer networks with a wireless communication function, a function of transmitting and receiving a variety of data with a wireless communication function, a function of reading a program or data stored in a storage medium and displaying the program or data on the display portion, and the like. Note that functions of the electronic devices illustrated inFIGS.35A to35Gare not limited thereto, and the electronic devices can have a variety of functions. Although not illustrated inFIGS.35A to35G, the electronic devices may each have a plurality of display portions. The electronic devices may each have a camera or the like and a function of taking a still image, a function of taking a moving image, a function of storing the taken image in a storage medium (an external storage medium or a storage medium incorporated in the camera), a function of displaying the taken image on the display portion, and the like. Although not illustrated inFIGS.35A to35G, the electronic devices may be provided with an antenna or the like to have a wireless communication function. The electronic devices illustrated inFIGS.35A to35Gwill be described in detail below. FIG.35Ais a perspective view of a portable information terminal9100. The display portion9001of the portable information terminal9100is flexible and thus can be incorporated along the curved surface of the housing9000. Furthermore, the display portion9001includes a touch sensor, and operation can be performed by touching a screen with a finger, a stylus, or the like. For example, by touching an icon displayed on the display portion9001, an application can be started. FIG.35Bis a perspective view of a portable information terminal9101. The portable information terminal9101functions as, for example, one or more of a telephone set, a notebook, an information browsing system, and the like. Specifically, the portable information terminal9101can be used as a smartphone. Note that the speaker9003, the connection terminal9006, the sensor9007, and the like, which are not illustrated inFIG.35B, can be positioned in the portable information terminal9101as in the portable information terminal9100illustrated inFIG.35A. The portable information terminal9101can display characters and image information on its plurality of surfaces. For example, three operation buttons9050(also referred to as operation icons, or simply, icons) can be displayed on one surface of the display portion9001. Furthermore, information9051indicated by dashed rectangles can be displayed on another surface of the display portion9001. Examples of the information9051include notification from a social networking service (SNS), display indicating reception of an e-mail or an incoming call, the title of the e-mail, the SNS, or the like, the sender of the e-mail, the SNS, or the like, the date, the time, remaining battery, and the strength of a received signal. Instead of the information9051, the operation buttons9050or the like may be displayed in the position where the information9051is displayed. FIG.35Cis a perspective view of a portable information terminal9102. The portable information terminal9102has a function of displaying information on three or more surfaces of the display portion9001. Here, information9052, information9053, and information9054are displayed on different surfaces. For example, a user of the portable information terminal9102can see the display (here, the information9053) with the portable information terminal9102put in a breast pocket of his/her clothes. Specifically, a caller's phone number, name, or the like of an incoming call is displayed in the position that can be seen from above the portable information terminal9102. Thus, the user can see the display without taking out the portable information terminal9102from the pocket and decide whether to answer the call. FIG.35Dis a perspective view of a watch-type portable information terminal9200. The portable information terminal9200is capable of executing a variety of applications such as mobile phone calls, e-mailing, viewing and editing texts, music reproduction, Internet communication, and computer games. The display surface of the display portion9001is curved, and images can be displayed on the curved display surface. The portable information terminal9200can employ near field communication conformable to a communication standard. For example, hands-free calling can be achieved with mutual communication between the portable information terminal9200and a headset capable of wireless communication. Moreover, the portable information terminal9200includes the connection terminal9006, and data can be directly transmitted to and received from another information terminal via a connector. Charging through the connection terminal9006is also possible. Note that the charging operation may be performed by wireless power feeding without using the connection terminal9006. FIGS.35E,35F, and35Gare perspective views of a foldable portable information terminal9201that is opened, that is shifted from the opened state to the folded state or from the folded state to the opened state, and that is folded, respectively. The portable information terminal9201is highly portable when folded. When the portable information terminal9201is opened, a seamless large display region provides high browsability. The display portion9001of the portable information terminal9201is supported by three housings9000joined together by hinges9055. By folding the portable information terminal9201at a connection portion between two housings9000with the hinges9055, the portable information terminal9201can be reversibly changed in shape from the opened state to the folded state. For example, the portable information terminal9201can be bent with a radius of curvature of greater than or equal to 1 mm and less than or equal to 150 mm. The electronic devices described in this embodiment each include the display portion for displaying some kinds of information. However, a semiconductor device according to one embodiment of the present invention can also be used for an electronic device that does not include a display portion. Furthermore, the display portions of the electronic devices described in this embodiment may also be non-flexible and can display images on a flat surface without limitation to a flexible mode capable of displaying images on a curved display surface or a foldable mode. The structures described in this embodiment can be used in appropriate combination with any of the structures described in the other embodiments. This application is based on Japanese Patent Application serial no. 2014-218938 filed with Japan Patent Office on Oct. 28, 2014, the entire contents of which are hereby incorporated by reference. | 206,586 |
11862455 | DETAILED DESCRIPTION Hereinafter, exemplary embodiments of the present disclosure will be described in detail with reference to the accompanying drawings. The following embodiments are provided by way of example so as to fully convey the spirit of the present disclosure to those skilled in the art to which the present disclosure pertains. Accordingly, the present disclosure is not limited to the embodiments disclosed herein and can also be implemented in different forms. In the drawings, widths, lengths, thicknesses, and the like of elements can be exaggerated for clarity and descriptive purposes. When an element is referred to as being “disposed above” or “disposed on” another element, it can be directly “disposed above” or “disposed on” the other element, or intervening elements can be present. Throughout the specification, like reference numerals denote like elements having the same or similar functions. A light emitting diode according to an exemplary embodiment includes: (i) a first conductivity type semiconductor layer; (ii) a mesa disposed on the first conductivity type semiconductor layer, and including an active layer and a second conductivity type semiconductor layer; (iii) a transparent conductive oxide layer disposed on the mesa and electrically connected to the second conductivity type semiconductor layer; (iv) a dielectric layer covering the conductive oxide layer, and including a plurality of openings exposing the conductive oxide layer, the dielectric layer having a lower refractive index than those of the second conductivity type semiconductor layer and the conductive oxide layer; (v) a metal reflection layer disposed on the dielectric layer, and connecting to the conductive oxide layer through the openings of the dielectric layer; (vi) a lower insulation layer covering the mesa and the metal reflection layer, and including a first opening exposing the first conductivity type semiconductor layer and a second opening exposing the metal reflection layer; (vii) a first pad metal layer disposed on the lower insulation layer, and electrically connected to the first conductivity type semiconductor layer through the first opening; (viii) a second pad metal layer disposed on the lower insulation layer, and electrically connected to the metal reflection layer through the second opening; and (ix) an upper insulation layer covering the first pad metal layer and the second pad metal layer, and including a first opening exposing the first pad metal layer and a second opening exposing the second pad metal layer, in which the dielectric layer has a thickness in a range of about 4 to about 13 times greater than that of the second conductivity type semiconductor layer. In some embodiments, the dielectric layer may have a thickness in a range of about 200 nm to about 1000 nm, and specifically, may have a thickness in a range of about 300 nm to about 800 nm. High light output and low forward voltage may be achieved within the thickness range. In some embodiments, the conductive oxide layer may have a thickness within a range of about 3 nm to about 50 nm, and specifically, may have a thickness in a range of about 6 nm to about 30 nm. Favorable ohmic contact resistance may be obtained within the thickness range, and light loss due to light absorption may be reduced. The dielectric layer may cover side surfaces of the mesa, and partially cover the first conductivity type semiconductor layer around the mesa. The lower insulation layer may cover an edge of the dielectric layer. The first opening of the lower insulation layer may expose the first conductivity type semiconductor layer along a periphery of the mesa, and the first pad metal layer may have an outer contact portion that contacts the first conductivity type semiconductor layer along the periphery of the mesa. The first pad metal layer contacts the first conductivity type semiconductor layer along the periphery of the mesa, so that current spreading capability of the light emitting diode may be improved. The mesa may include an indent portion that exposes the first conductivity type semiconductor layer, and the first opening of the lower insulation layer may further expose the first conductivity type semiconductor layer in the indent portion. Furthermore, the first pad metal layer may further include an inner contact portion that contacts the first conductivity type semiconductor layer in the indent portion. Since the first pad metal layer contacts the first conductivity type semiconductor layer at the periphery of the mesa and inside the mesa, current spreading capability of the light emitting diode may be further enhanced. Furthermore, the inner contact portion may be connected to the outer contact portion, but the inventive concepts are not limited thereto, the inner contact portion and the outer contact portion may be separated from each other. In some exemplary embodiments, the mesa may have a via hole exposing the first conductivity type semiconductor layer through the second conductivity type semiconductor layer and the active layer, in which the first opening of the lower insulation layer may expose the first conductivity type semiconductor layer exposed in the via hole, and the first pad metal layer may have an inner contact portion that contacts the first conductivity type semiconductor layer exposed in the via hole. The first pad metal layer may include outer contact portions that contact the first conductivity type semiconductor layer at the outside of the mesa, in which the outer contact portions may be spaced apart from one another. The light emitting diode may further include: a first bump pad connected to the first pad metal layer through the first opening of the upper insulation layer; and a second bump pad connected to the second pad metal layer through the second opening of the upper insulation layer. The first and second bump pads may be used as bonding pads when the light emitting diode is mounted on a circuit board or the like to manufacture a light emitting module. The lower insulation layer may include a plurality of second openings, and the second bump pad may cover an upper portion of at least one second opening of the lower insulation layer. A location and a shape of the first bump pad may be variously modified as long as the first bump pad is insulated from the second pad metal layer, and a location and a shape of the second bump pad may also be variously modified as long as the second bump pad is insulated from the first pad metal layer, The second pad metal layer may be surrounded by the first pad metal layer. As such, a boundary region in which the lower insulation layer is exposed may be formed between the first pad metal layer and the second pad metal layer. The boundary region may be covered by the upper insulation layer. In some exemplary embodiments, the second bump pad may be disposed within an upper region of the second pad metal layer, but the inventive concepts are not limited thereto, the second bump pad may partially overlap with the first pad metal layer. The light emitting diode may further include a substrate disposed on a side of the first conductivity type semiconductor layer. The substrate is configured to transmit light generated in the active layer. A light emitting diode according to another exemplary embodiment includes: (i) a first conductivity type semiconductor layer; (ii) a mesa disposed on the first conductivity type semiconductor layer, and including an active layer and a second conductivity type semiconductor layer; (iii) a transparent conductive oxide layer disposed on the mesa and electrically connected to the second conductivity type semiconductor layer; (iv) a dielectric layer covering the conductive oxide layer, and including a plurality of openings exposing the conductive oxide layer, the dielectric layer having a lower refractive index than those of the second conductivity type semiconductor layer and the conductive oxide layer; (v) a metal reflection layer disposed on the dielectric layer, and connecting to the conductive oxide layer through the openings of the dielectric layer, in which the dielectric layer has a lower refractive index than those of the conductive oxide layer and the second conductivity type semiconductor layer, and has a thickness in a range of about 300 nm to about 800 nm. A thickness of the dielectric layer may be in a range of 4 times or greater than to 13 times or less than a thickness of the second conductivity type semiconductor layer. The conductive oxide layer may be an indium tin oxide (ITO) layer, and the ITO layer may have a thickness in a range of about 6 nm to about 30 nm. In some embodiments, the light emitting diode may further include: a substrate disposed on a side of the first conductivity type semiconductor layer; a first bump pad disposed over the metal reflection layer, and electrically connected to the first conductivity type semiconductor layer; and a second bump pad disposed over the metal reflection layer, and electrically connected to the metal reflection layer. A light emitting diode according to another exemplary embodiment includes: (i) a first conductivity type semiconductor layer; (ii) a mesa disposed on the first conductivity type semiconductor layer, and including an active layer and a second conductivity type semiconductor layer; (iii) a transparent conductive oxide layer disposed on the mesa and electrically connected to the second conductivity type semiconductor layer; (iv) a dielectric layer covering the conductive oxide layer, and including a plurality of openings exposing the conductive oxide layer; (v) a metal reflection layer disposed on the dielectric layer, and connecting to the conductive oxide layer through the openings of the dielectric layer; (vi) a lower insulation layer covering the mesa and the metal reflection layer, and including at least one first opening exposing the first conductivity type semiconductor layer and a second opening exposing the metal reflection layer; (vii) a first pad metal layer disposed on the lower insulation layer, and electrically connected to the first conductivity type semiconductor layer through the at least one first opening; (viii) a second pad metal layer disposed on the lower insulation layer, and electrically connected to the metal reflection layer through the second opening; and (ix) an upper insulation layer covering the first pad metal layer and the second pad metal layer, and including a first opening exposing the first pad metal layer and a second opening exposing the second pad metal layer, in which the openings of the dielectric layer include a narrow and elongated bar-shaped opening adjacent to at least one of the first openings of the lower insulation layer. The bar-shaped opening is arranged to be adjacent to the first opening of the lower insulation layer, and thus, it is possible to prevent the light emitting diode from being damaged by electrical overstress or electrostatic discharge. The dielectric layer may include openings having other shapes in addition to the bar-shaped opening, and the bar-shaped opening may be disposed between the first opening of the lower insulation layer corresponding to the bar-shaped opening and the openings having other shapes. The first opening of the lower insulation layer corresponding to the bar-shaped opening may have an elongated shape in one direction, and the bar-shaped opening of the dielectric layer may be disposed to be flush with the first opening of the lower insulation layer corresponding to the bar-shaped opening. The bar-shaped opening of the dielectric layer may be longer than the first opening of the lower insulation layer corresponding to the bar-shaped opening. As such, it is possible to provide a light emitting diode that is more resistant to electrical overstress and electrostatic discharge than a conventional light emitting diode. The lower insulation layer may have a plurality of first openings exposing the first conductivity type semiconductor layer around the mesa, and the first pad metal layer may have outer contact portions in contact with the first conductivity type semiconductor layer in the plurality of first openings. The dielectric layer may have a plurality of bar-shaped openings adjacent to the plurality of first openings, respectively. The bar-shaped opening of the dielectric layer may be arranged lengthily over the outer contact portions. The light emitting diode may further include a first bump pad; and a second bump pad, in which the first bump pad and the second bump pad may be electrically connected to the first pad metal layer and the second pad metal layer through the first opening and the second opening of the upper insulation layer, respectively, and at least a portion of the bar-shaped opening may be disposed under the first bump pad. A portion of the bar-shaped opening may be disposed under the second bump pad. The light emitting diode may further include a substrate disposed on a side of the first conductivity type semiconductor layer, in which the substrate is configured to transmit light generated in the active layer. The first pad metal layer may have protrusions along one edge of the mesa M, in which the first pad metal layer may have outer contact portions in contact with the first conductivity type semiconductor layer near an edge of the mesa, the outer contact portions may be formed by the protrusions, and a region between the protrusions of edges of the first pad metal layer may be disposed on the conductive oxide layer. A light emitting diode according to another exemplary embodiment includes: (i) a first conductivity type semiconductor layer; (ii) a mesa disposed on the first conductivity type semiconductor layer, and including an active layer and a second conductivity type semiconductor layer; (iii) a transparent conductive oxide layer disposed on the mesa and electrically connected to the second conductivity type semiconductor layer; (iv) a dielectric layer covering the conductive oxide layer, and including a plurality of openings exposing the conductive oxide layer; (v) a metal reflection layer disposed on the dielectric layer, and connecting to the conductive oxide layer through the openings of the dielectric layer; (vi) a lower insulation layer covering the mesa and the metal reflection layer, and including at least one first opening exposing the first conductivity type semiconductor layer and a second opening exposing the metal reflection layer; (vii) a first pad metal layer disposed on the lower insulation layer, and electrically connected to the first conductivity type semiconductor layer through the at least one first opening; (viii) a second pad metal layer disposed on the lower insulation layer, and electrically connected to the metal reflection layer through the second opening; and (ix) an upper insulation layer covering the first pad metal layer and the second pad metal layer, and including a first opening exposing the first pad metal layer and a second opening exposing the second pad metal layer, in which the openings of the dielectric layer include openings that have different sizes from one another, and at least one of the openings in the dielectric layer adjacent to the first opening of the upper insulation layer has a width or a length greater than at least one another opening of the dielectric layer that is disposed farther from the first opening of the upper insulation layer. Since the opening of the dielectric layer adjacent to the region where the first opening of the upper insulation layer, that is, the first pad metal layer contacts the first conductive semiconductor layer is set to be larger than the remaining openings of the dielectric layer, a light emitting diode having strong resistance to electrical overstress or electrostatic discharge may be provided. In some exemplary embodiments, the opening of the dielectric layer having a greater width or length may have a bar shape. In other exemplary embodiments, the opening of the dielectric layer may have a circular or ring shape. The light emitting diode may further include: a first bump pad; and a second bump pad, in which the first bump pad and the second bump pad may be electrically connected to the first pad metal layer and the second pad metal layer through the first opening and the second opening of the upper insulation layer, respectively, and at least a portion of the opening of the dielectric layer having a greater width or length may be disposed under the first bump pad. At least one of the openings of the dielectric layer having a greater width or length may extend from a bottom of the first bump pad to a bottom of the second bump pad. The mesa may have a via hole that exposes the first conductivity type semiconductor layer, in which the first openings of the lower insulation layer may include an opening that exposes the first conductivity type semiconductor layer in the via hole, the first pad metal layer may include an inner contact portion that contacts the first conductivity type semiconductor layer in the via hole, and the opening of the dielectric layer having a greater width or length may be disposed adjacent to the via hole. The opening of the dielectric layer disposed adjacent to the via hole may surround the via hole. The first pad metal layer may include outer contact portions that contact the first conductivity type semiconductor layer at the outside of the mesa, in which the outer contact portions may be spaced apart from one another, and the openings of the dielectric layer having a greater width or length may be disposed adjacent to the outer contact portions, respectively. The dielectric layer may have a lower refractive index than those of the second conductivity type semiconductor layer and the conductive oxide layer, and may have a thickness in a range of about 300 nm to about 800 nm. The conductive oxide layer may also have a thickness in a range of about 3 nm to about 50 nm. The light emitting diode may further include a substrate disposed on a side of the first conductivity type semiconductor layer, in which the substrate may be configured to transmit light generated in the active layer. A light emitting diode according to another exemplary embodiment includes: (i) a first conductivity type semiconductor layer; (ii) a mesa disposed on the first conductivity type semiconductor layer, and including an active layer and a second conductivity type semiconductor layer; (iii) a transparent conductive oxide layer disposed on the mesa and electrically connected to the second conductivity type semiconductor layer; (iv) a dielectric layer covering the conductive oxide layer, and including a plurality of openings exposing the conductive oxide layer; (v) a metal reflection layer disposed on the dielectric layer, and connecting to the conductive oxide layer through the openings of the dielectric layer; (vi) a lower insulation layer covering the mesa and the metal reflection layer, and including at least one first opening exposing the first conductivity type semiconductor layer and a second opening exposing the metal reflection layer; (vii) a first pad metal layer disposed on the lower insulation layer, and electrically connected to the first conductivity type semiconductor layer through the at least one first opening; (viii) a second pad metal layer disposed on the lower insulation layer, and electrically connected to the metal reflection layer through the second opening; and (ix) an upper insulation layer covering the first pad metal layer and the second pad metal layer, and including a first opening exposing the first pad metal layer and a second opening exposing the second pad metal layer, in which the openings of the dielectric layer include openings disposed under the first opening of the upper insulation layer, and, among the openings disposed under the first opening of the upper insulation layer and adjacent to the first opening of the lower insulation layer, a distance of an opening spaced apart from the first opening in the vertical direction is greater than a distance of an opening of the dielectric layer closest to the first opening. The light emitting diode having improved resistance to electrical overstress or electrostatic discharge may be provided by adjusting the distance between the contact portion where the first pad metal layer contacts the first conductivity type semiconductor layer and the openings of the dielectric layer adjacent thereto. Hereinafter, exemplary embodiments of the inventive concepts will be described in detail with reference to the accompanying drawings. FIG.1is a schematic plan view illustrating a light emitting diode according to an exemplary embodiment, andFIG.2is a cross-sectional view taken along the line A-A inFIG.1. Referring toFIG.1andFIG.2, the light emitting diode includes a substrate21, a first conductivity type semiconductor layer23, an active layer25, a second conductivity type semiconductor layer27, a conductive oxide layer28, a dielectric layer29, a metal reflection layer31, a lower insulation layer33, a first pad metal layer35a, a second pad metal layer35b, and an upper insulation layer37. The light emitting diode may further include a first bump pad39aand a second bump pad39b. The substrate21may be selected from any substrates that are suitable for growth of gallium nitride semiconductor layers thereon. The substrate21may include, for example, a sapphire substrate, a gallium nitride substrate, a SiC substrate, and the like, and may be a patterned sapphire substrate. The substrate21may have a rectangular or square shape, as shown in the plan view ofFIG.1, without being limited thereto. A size of the substrate21is not particularly limited and may be selected in various ways. The first conductivity type semiconductor layer23is disposed on the substrate21. The first conductivity type semiconductor layer23may be a gallium nitride semiconductor layer grown on the substrate21and doped with dopants, for example Si. An edge of the first conductivity type semiconductor layer23according to the exemplary embodiment is flush with an edge of the substrate21, as shown inFIG.2. However, the inventive concepts are not limited thereto, and the first conductivity type semiconductor layer23may be located inside a region surrounded by the edge of the substrate21. In this case, a portion of the upper surface of the substrate21may be exposed along a periphery of the first conductivity type semiconductor layer23. A mesa M is disposed on the first conductivity type semiconductor layer23. The mesa M may be disposed within a region surrounded by the first conductivity type semiconductor layer23so that regions near edges of the first conductivity type semiconductor layer23are not covered by the mesa M, but exposed to the outside. The mesa M includes the second conductivity type semiconductor layer27and the active layer25. The active layer25is interposed between the first conductivity type semiconductor layer23and the second conductivity type semiconductor layer27. The active layer25may have a single quantum well structure or a multiple quantum well structure. A location and a thickness of the well layer in the active layer25determine a wavelength of light that is generated. In particular, by controlling the location of the well layer, it is possible to provide an active layer generating ultraviolet light, blue light or green light. The second conductivity type semiconductor layer27may be a gallium nitride-based semiconductor layer doped with a p-type impurity, for example, Mg. A concentration of the p-type impurity of the second conductivity type semiconductor layer27affects a refractive index of the second conductivity type semiconductor layer27. The concentration of the p-type impurity of the second conductivity type semiconductor layer27may be in a range of about 8×10−18to about 4×10−21/cm3. When the concentration of the impurity is lower than 8×10−18/cm−3, effect that increases the refractive index is not obtained. When the concentration of the impurity is higher than 4×10−21/cm3, it is difficult to form a stable ohmic contact. The concentration of the p-type impurity of the second conductivity type semiconductor layer27may not have a constant value, but it may have a concentration profile that varies with thickness within the above range. In particular, it may have a higher impurity concentration on a side thereof closer to the conductive oxide layer28to have a higher refractive index on a surface of the second conductivity type semiconductor layer27. As such, a difference between the refractive index of the second conductivity type semiconductor layer27and that of the conductive oxide layer28may be increased by increasing the refractive index of the second conductivity type semiconductor layer27. The difference in refractive indexes between the second conductivity type semiconductor layers28and the conductive oxide layer28is set to be substantially similar to the difference in refractive indexes between the conductive oxide layer28and the dielectric layer29, and thus, light extraction may be effective. FIG.3illustrates a concentration profile in the second conductivity type semiconductor layer27. As shown inFIG.3, a concentration of a p-type impurity of the second conductivity type semiconductor layer27, for example, a concentration of Mg may include a section that has different gradients of concentration from each other. The concentration thereof may have a profile that the concentration decreases as a measurement point is closer to the active layer25, and increases as the measurement point is closer to the conductive oxide layer28. In particular, the concentration sharply increases as the measurement point approaches the conductive oxide layer28, and it may have a gradient greater than an absolute value of gradient's decrease in concentration near the active layer25. As such, a portion where the refractive index is sharply increased is in contact with the conductive oxide layer28, and thus, light extraction effect may be maximized. Each of the first conductivity type semiconductor layer23and the second conductivity type semiconductor layer27may be composed of a single layer or multiple layers without limiting thereto, or may include super-lattice layers. The first conductivity type semiconductor layer23, the active layer25and the second conductivity type semiconductor layer27may be grown on the substrate21in a chamber by a well-known method, such as metal organic chemical vapor delocation (MOCVD) or Molecular Beam Epitaxy (MBE). As shown inFIG.1, the mesa M may have an indent portion30penetrating therein, and an upper surface of the first conductivity type semiconductor layer23may be exposed by the indent portion30. The indent portion30may be extend from one edge of the mesa M toward the other side opposite to the mesa M. A length of the indent portion30is not particularly limited, but may be ½ of the length of the mesa M or longer than that. Also, although two indent portions30are shown inFIG.1, the number of indent portion30may be one or three or more. Accordingly, as the number of indent portions30increases, the number of inner contact portions35a2of the first pad metal layer35a, which will be described later, increases, thereby improving current spreading capability. The indent portion30has a round shape as a width becomes wider at an end terminal portion thereof. As the shape of the end terminal portion of the indent is formed as described above, the lower insulation layer33may be patterned in a similar shape. In particular, in a case that the lower insulation layer33includes a distributed Bragg reflector, if a width of the distributed Bragg reflector is not widened at the end terminal portion as shown inFIG.1, a severe double step is formed in a side wall of the distributed Bragg reflector, and the pad metal layer35ais likely to be cracked as an inclination angle of the side wall becomes large. Accordingly, an edge of the lower insulation layer33may be formed to have a gentle inclination angle by forming the shape of the end terminal portion of the indent portion30and the shape of the end terminal portion of the first opening33a2of the lower insulation layer33as those in the illustrated exemplary embodiment, thereby improving yield of the light emitting diode. Although the indent portion30is illustrated and described as being formed in the mesa M in the exemplary embodiment, the mesa M may have at least one via hole passing through the second conductivity type semiconductor layer27and the active layer25instead of the indent portion30. The conductive oxide layer28is disposed over the mesa M to contact the second conductivity type semiconductor layer27. The conductive oxide layer28may be disposed over almost an entire region of the mesa M. For example, the conductive oxide layer28may cover 80% or more, and further more than 90% or more of the upper region of the mesa M. The conductive oxide layer28includes an oxide layer that transmits light generated in the active layer25. The conductive oxide layer28may include for example, indium tin oxide (ITO) or ZnO. The conductive oxide layer28is formed to have a thickness sufficient for ohmic contacting with the second conductivity type semiconductor layer27, and, for example, the conductive oxide layer28may be formed to have a thickness in a range of about 3 nm to about nm, specifically, in a range of about 6 nm to about 30 nm. When the thickness of the conductive oxide layer28is too thin, it does not provide sufficient ohmic properties, thereby increasing the forward voltage. When the thickness of the conductive oxide layer28is too thick, light loss due to light absorption occurs, thereby lowering luminous efficiency. The dielectric layer29may cover the conductive oxide layer28, and may further cover side surfaces of the second conductivity type semiconductor layer27, the active layer25, and the first conductivity type semiconductor layer23. An edge of the dielectric layer29may be covered with the lower insulation layer33. Accordingly, the edge of the dielectric layer29is located farther from the edge of the substrate21than the edge of the lower insulation layer33. However, the inventive concepts are not limited thereto, and a portion of the dielectric layer29may be exposed to the outside of the lower insulation layer33. The dielectric layer29has openings29aexposing the conductive oxide layer28. A plurality of openings29amay be disposed over the conductive oxide layer28. The openings29aare used as connection passages so that the metal reflection layer31may be connected to the conductive oxide layer28. The dielectric layer29also exposes the first conductivity type semiconductor layer23around the mesa M and exposes the first conductivity type semiconductor layer23in the indent portion30. The dielectric layer29includes an insulating material that has a lower refractive index than those of the second conductivity type semiconductor layer27and the conductive oxide layer28. The dielectric layer29may include SiO2, for example. A thickness of the dielectric layer29affects the forward voltage and light output of the light emitting diode. The dielectric layer29may have a thickness in a range of about 200 nm to about 1000 nm, and specifically, may have a thickness in a range of about 300 nm to about 800 nm. When the thickness of the dielectric layer29is less than 200 nm, the forward voltage is high and the light output is low, which is not favorable. When the thickness of the dielectric layer29is more than 400 nm, the light output is saturated, and the forward voltage tends to increase again. Thus, it is advantageous that the thickness of the dielectric layer29does not exceed 1000 nm, and, in particular, the thickness thereof may be about 800 nm or less. The thickness of the dielectric layer29may be about 4 times or greater than a thickness of the second conductivity type semiconductor layer27on the active layer25, and may be about 13 times or less than that of the second conductivity type semiconductor layer27. The metal reflection layer31is disposed on the dielectric layer29and is connected to the ohmic contact layer28through the openings29a. The metal reflection layer31may include a reflective metal, and may include Ag or Ni/Ag, for example. The metal reflection layer32may further include a barrier layer to protect a reflective metal material layer, for example, Ni, and may also include an Au layer to prevent oxidation of the metal layer. A Ti layer may further be included under the Au layer to improve the adhesion of the Au layer. The metal reflection layer31is in contact with an upper surface of the dielectric layer29, and thus, the thickness of the dielectric layer29is equal to a distance between the conductive oxide layer28and the metal reflection layer31. Since an ohmic contact is formed with the conductive oxide layer28, and the metal reflection layer31is disposed on the dielectric layer29, ohmic resistance may be prevented from being increased due to solder or the like. Furthermore, since the conductive oxide layer28, the dielectric layer29, and the metal reflection layer31are disposed on the second conductivity type semiconductor layer27, reflectance of light may be improved, thereby improving luminous efficiency. The lower insulation layer33covers the mesa M and the metal reflection layer31. The lower insulation layer33may also cover the first conductivity type semiconductor layer23along a periphery of the mesa M, and may cover the first conductivity type semiconductor layer23in the indent portion30that is inside the mesa M. The lower insulation layer33covers side surfaces of the mesa M in particular. The lower insulation layer33may also cover the dielectric layer29. The lower insulation layer33has first and second openings33a1and33a2exposing the first conductivity type semiconductor layer23and a second opening33bexposing the metal reflection layer31. The first opening33a1exposes the first conductivity type semiconductor layer23along the periphery of the mesa M, and the first opening33a2exposes the first conductivity type semiconductor layer23in the indent portion30. In a case that a via hole is formed instead of the indent portion30, the first opening33a2exposes the first conductivity type semiconductor layer23in the via hole. As shown inFIG.1, the first openings33a1and33a2may be connected to each other. However, the inventive concepts are not limited thereto, and in other embodiments, the first opening33a1and the first opening33a2may be separated from each other. The first opening33a1of the lower insulation layer33is formed to expose all of the peripheral region including the edge of the first conductivity type semiconductor layer23in the illustrated exemplary embodiment. However, the inventive concepts are not limited thereto, and the first opening33a1of the lower insulation layer33may be formed to have a band shape along the periphery of the mesa M. In this case, the edge of the first conductivity type semiconductor layer23may be covered with the lower insulation layer33or may be flush with the edge of the lower insulation layer33. The second opening33bexposes the metal reflection layer31. A plurality of second openings33bmay be formed, and the second openings33bmay be disposed near one edge of the substrate21so as to face the indent portion30. Locations of the second openings33bwill be described later. The lower insulation layer33may include a single layer of SiO2or Si3N4, without being limited thereto. For example, the lower insulation layer33may have a multilayer structure which includes a silicon nitride layer and a silicon oxide layer, and may include a distributed Bragg reflector in which silicon oxide layers and titanium oxide layers are alternately stacked one above another. The first pad metal layer35ais disposed on the lower insulation layer33and is insulated from the mesa M and the metal reflection layer31by the lower insulation layer33. The first pad metal layer35acontacts the first conductivity type semiconductor layer23through the first openings33a1and33a2of the lower insulation layer33, as shown inFIG.2. The first pad metal layer35amay include an outer contact portion35a1that contacts the first conductivity type semiconductor layer23along the periphery of the mesa M and an inner contact portion35a2that contacts the first conductivity type semiconductor layer23in the indent portion30or the via hole. The outer contact portion35a1contacts the first conductivity type semiconductor layer23near the edge of the substrate21along the periphery of the mesa M, and the inner contact portion35a2contacts the first conductivity type semiconductor layer23in a region surrounded by the outer contact portion35a1. The outer contact portion35a1and the inner contact portion35a2may be connected to each other, but the inventive concepts are not limited thereto, and they may be separated from each other. In addition, the outer contact portion35a1may continuously contact the first conductivity type semiconductor layer23along the periphery of the mesa M, but it is not limited thereto, and a plurality of outer contact portions35a1may be disposed to be spaced apart from one another. The second pad metal layer35bis disposed on the upper region of the mesa M on the lower insulation layer33, and is electrically connected to the metal reflection layer31through the second opening33bof the lower insulation layer33. The second pad metal layer35bmay be surrounded by the first pad metal layer35a, and a boundary region35abmay be formed therebetween. The lower insulation layer33is exposed to the boundary region35ab, and the boundary region35abis covered with the upper insulation layer37, which will be described later. The first pad metal layer35aand the second pad metal layer35bmay be formed in the same process and may include substantially the same material. The first and second pad metal layers35aand35bmay include an ohmic reflection layer such as an Al layer, and the ohmic reflection layer may be formed on an adhesive layer such as Ti, Cr, Ni, or the like. Furthermore, a protective layer of a single layer or a multiple layer structure such as Ni, Cr, Au, or the like may be formed on the ohmic reflection layer. The first and second pad metal layers35aand may have multilayer structures of Cr/Al/Ni/Ti/Ni/Ti/Au/Ti, for example. The upper insulation layer37covers the first and second pad metal layers35aand35b. The upper insulation layer37may also cover the first conductivity type semiconductor layer23along the periphery of the mesa M. In the illustrated exemplary embodiment, the upper insulation layer37may expose the first conductivity type semiconductor layer23along the edge of the substrate21. However, the inventive concepts are not limited thereto, and the upper insulation layer37may cover all of the first conductivity type semiconductor layers23, and may be flush with the edge of the substrate21. The upper insulation layer37has a first opening37aexposing the first pad metal layer and a second opening37bexposing the second pad metal layer35b. The first opening37aand the second opening37bmay be disposed in the upper region of the mesa M and may be arranged to face each other. In particular, the first opening37aand the second opening37bmay be disposed close to both side edges of the mesa M. The upper insulation layer37may include a single layer of SiO2or Si3N4, without being limited thereto. For example, the upper insulation layer37may have a multilayer structure which includes a silicon oxide layer and a silicon nitride layer, and may include a distributed Bragg reflector in which silicon oxide layers and titanium oxide layers are alternately stacked one above another. The first bump pad39aelectrically contacts the first pad metal layer35aexposed through the first opening37aof the upper insulation layer37, and the second bump pad39belectrically contacts the second pad metal layer35bexposed through the second opening37b. As shown inFIG.1, the first bump pad39amay be disposed in the first opening37aof the upper insulation layer37, and the second bump pad39bmay be disposed in the second opening37bof the upper insulation layer37. However, the inventive concepts are not limited thereto, and the first bump pad39aand the second bump pad39bmay cover all of the first opening37aand the second opening37bto seal them, respectively. In addition, the second bump pad39bmay cover an upper region of the second opening33bof the lower insulation layer33. The second bump pad39bmay cover all of the second openings33bof the lower insulation layer33, but the inventive concepts are not limited thereto, a portion of the openings33bmay be disposed at the outside of the second bump pad39b. The second bump pad39bmay further be disposed within an upper region of the second pad metal layer35aas shown inFIG.1, but the inventive concepts are not limited thereto, and a portion of the second bump pad39bmay overlap with the first pad metal layer35a. However, the upper insulation layer37may be disposed between the first pad metal layer and the second bump pad39bto insulate them. According to the exemplary embodiment, a reflective structure with the conductive oxide layer28, the dielectric layer29, and the metal reflection layer31is used instead of a conventional ohmic reflection layer. As such, it is possible to prevent a bonding material such as solder from diffusing into the contact region, and to obtain a stable ohmic contact resistance, thereby improving the reliability of the light emitting diode. Furthermore, since the thickness of the dielectric layer29is set to be about 300 nm or more, high light output and low forward voltage may be achieved. FIG.4AandFIG.4Bare graphs showing forward voltage (Vf) and light output (Po) as a function of thicknesses of SiO2with a conductive oxide layer28as ITO and a dielectric layer29as SiO2. A thickness of ITO was 20 nm, and thicknesses of SiO2were changed to 200 nm, 400 nm, 600 nm, and 800 nm. A thickness of the second conductivity type semiconductor layer27was about 65 nm. As shown inFIG.4A, when the thickness of the dielectric layer29was 200 nm, the forward voltage was relatively high, and the lowest value exhibited when the thickness thereof was 400 nm. Also, as the thickness became greater than 400 nm, the forward voltage increased. As shown inFIG.4B, however, the lowest light output exhibited when the thickness of the dielectric layer29was 200 nm, and substantially similar light output exhibited when the thickness of the dielectric layer29was 400 nm or more. FIG.5is a schematic plan view illustrating a light emitting diode according to another exemplary embodiment, andFIG.6is a cross-sectional view taken along the line B-B ofFIG.5. Referring toFIG.5andFIG.6, since the light emitting diode according to the exemplary embodiment is substantially similar to the light emitting diode described with reference toFIGS.1and2, characteristic differences thereof will be mainly explained so as to avoid redundancy hereinafter. First, in the previous exemplary embodiment, the edge of the first conductivity type semiconductor layer23is flush with the edge of the substrate21. An edge of a first conductivity type semiconductor layer23in this embodiment, however, is disposed in a region surrounded by the edge of the substrate21. As such, a region near the edge of the substrate21is exposed to the outside of the first conductivity type semiconductor layer23. In addition, locations of openings29aof the dielectric layer29are adjusted in the exemplary embodiment, which will be described in detail later. In the previous exemplary embodiment, the edge of the lower insulation layer33is located on the first conductivity type semiconductor layer23, but, a lower insulation layer33in this exemplary embodiment covers the edge of the first conductivity type semiconductor layer23, and is flush with the edge of the substrate21, as shown inFIG.6. A first opening33a1of the lower insulation layer33is limitedly disposed on the first conductivity type semiconductor layer23, and is disposed in a ring shape along a periphery of mesa M. Further, a second opening33bof the lower insulation layer33is formed at the outside of a second bump pad39bso as not to overlap with the second bump pad39b. Since the second opening33bare disposed to be spaced apart from the second bump pad39bin the lateral direction, it is possible to prevent solder from diffusing into the light emitting diode while soldering the second bump pad39b. As shown inFIG.6, a first pad metal layer35acovers the first opening33a1of the lower insulation layer33to contact the first conductivity type semiconductor layer23, and thus, an outer contact portion35a1is formed in the first opening33a1. Referring back toFIG.5, the outer contact portion35a1may be connected to an inner contact portion35a2or spaced apart from the inner contact portion35a2, as described in the previous exemplary embodiment. A shape of a second pad metal layer35bin the exemplary embodiment is different from that of the second pad metal layer35in the exemplary embodiment ofFIG.1, and accordingly, a location of a boundary region between the second pad metal layer35band the first pad metal layer35ais also different from that in the exemplary embodiment ofFIG.1. As shown inFIG.5, the second pad metal layer35bextends to a region between the inner contact portion35a2and the outer contact portion35a1. In a case that a plurality of inner contact portions35a2are disposed, a front end of the second pad metal layer35bmay have a concave-convex shape as shown in the drawing. The first pad metal layer35amay be spaced apart from the second pad metal layer35bat regular intervals, and thus, the first pad metal layer35aadjacent to the front end of the second pad metal layer35bmay also have a concave-convex shape. Since the front end of the second pad metal layer35bextends to near the inner contact portions35a2, it is possible to easily separate the second openings33bof the lower insulation layer33from the second bump pad39bin the lateral direction. An upper insulation layer37may cover the lower insulation layer33, and an edge of the upper insulation layer37may be formed to be flush with the edges of the substrate21and the lower insulation layer33. Although the first and second bump pads39aand39bare illustrated and described as being disposed within the first and second openings37aand37bof the upper insulation layer37in the previous exemplary embodiment, the first and second bump pads39aand39bcover and seal first and second openings37aand37bof the upper insulation layer37in the exemplary embodiment. That is, edges of the first and second bump pads39aand39bare located on an upper surface of the upper insulation layer37. As such, the first pad metal layer35aand the second pad metal layer35bmay be prevented from being exposed between the upper insulation layer37and the bump pads39aand39b, and thus, direct diffusion into the first and second pad metal layers35aand35bmay be prevented. Locations of the edges of the first conductivity type semiconductor layer23, the lower insulation layer33, the upper insulation layer37, and the bump pads39aand39bin the exemplary embodiment, are different from those in the exemplary embodiment ofFIG.1, but the drawing herein is for illustrating an exemplary embodiment that can be modified with respect to the embodiment ofFIG.1without being limited thereto. That is, the locations of the edges of the first conductivity type semiconductor layer23, the lower insulation layer33, and the upper insulation layer37in the exemplary embodiment may be the same as those of the embodiment ofFIG.1, and the exemplary embodiment inFIG.1may be modified as that in this exemplary embodiment. The location of the openings29aof a dielectric layer29in the exemplary embodiment are adjusted to enhance resistance to electrical overstress or electrostatic discharge. Although the reflective structure with the conductive oxide layer28, the dielectric layer29and the metal reflection layer31improve the reflectance, the conductive oxide layer28and the metal reflection layer31need to be electrically connected. The openings29ain the dielectric layer29provide a passage through which the metal reflection layer31electrically connects to the conductive oxide layer28. In addition, a plurality of openings29aare widely distributed on the conductive oxide layer28so as to evenly distribute current over a wide region of the conductive oxide layer28. However, a distance between the outer contact portion35a1and the inner contact portion35a2and the openings29awhich are in contact with the first pad metal layer35amay affect characteristics of the light emitting diode against electrical overstress or electrostatic discharge. As a countermeasure against this, the illustrated exemplary embodiment as shown inFIG.5is characterized in that, among the openings29aof the dielectric layer29disposed under the first opening37aof the upper insulation layer37(or under the first bump pad39a), the openings29alocated closest to the inner contact portion35a2are relatively spaced apart therefrom. More particularly, a shortest distance Dv1(FIG.5) between the outer contact portion and the opening29alocated under the first opening37aof the upper insulation layer37is greater than a shortest distance Ds between the outer contact portion35a1and the openings29alocated outside the first openings37aof the upper insulation layer37. Although the distance between the outer contact portion35a1and the opening29ais indicated in the drawing, the same description applies to a distance between the inner contact portion35a2and the opening29a. The distance between the opening29aof the dielectric layer29located under the first bump pad39aelectrically connected to the first conductivity type semiconductor layer23and the contact portions35a1and35a2is greatly affected by electrical overstress and electrostatic discharge. Accordingly, the reliability of the light emitting diode may be improved by separating the openings29aof the dielectric layer29located under the first bump pad39afar away from the contact portions35a1and35a2. The openings29aunder the second bump pad39band those in other locations as well as the openings29aunder the first bump pad39amay also be separated from the contact portions35a1and35a2, but luminous efficiency may be lowered because current may not be widely distributed in this case. Therefore, the electrostatic discharge characteristics may be improved in the illustrated exemplary embodiment by arranging only the openings29alocated under the first bump pad39arelatively far from other openings without deteriorating the current spreading performance. FIG.7is a schematic plan view illustrating a light emitting diode according to another exemplary embodiment. Referring toFIG.7, the light emitting diode according to the exemplary embodiment is substantially similar to the light emitting diode described with reference toFIGS.5and6, but openings of a dielectric layer29include elongated opening29balong with a plurality of openings29ain the exemplary embodiment. When the opening29bis located between an outer contact portion35a1and an inner contact portion35a2and the openings29a, the opening29bforms a closed loop along the outer contact portion35a1and the inner contact portion35a2. Since the openings29badjacent to the outer contact portion35a1and the inner contact portion35a2are lengthily adjacent to the contact portions35a1and35a2, it is possible to prevent a large difference in voltage from occurring at a specific point, and thus a light emitting diode having a strong resistance to electrical overstress or electrostatic discharge may be provided. Although the opening29bin the illustrated exemplary embodiment is shown and described as forming the closed loop, the openings29bthat has a shape having a length larger than a width may be arranged along the contact portions35a1and35a2. In the illustrated exemplary embodiment, it is described that the opening29bis not limitedly disposed under a first bump pad39abut also extends to the outside of the first bump pad39a. In other embodiments, the opening29bmay be limitedly disposed under the first bump pad39a. FIG.8is a schematic plan view illustrating a light emitting diode according to another exemplary embodiment. Referring toFIG.8, the light emitting diode according to the exemplary embodiment is substantially similar to the light emitting diode described with reference toFIG.7, but openings of a dielectric layer29further include an opening29cin the exemplary embodiment. The opening29cmay be disposed in a region surrounded by opening29b, and in particular, may be located outside of a lower region of a second bump pad39b. A portion of the opening29cmay also be located under the first bump pad39b. FIG.9is a schematic plan view illustrating a light emitting diode according to another exemplary embodiment. Referring toFIG.9, the light emitting diode according to the exemplary embodiment is substantially similar to the light emitting diode described with reference toFIG.5, but a mesa M has an elongated shape in one direction, outer contact portions35a1are formed near an edge of the mesa without inner contact portions35a2, and a first pad metal layer35ais formed not to surround a second pad metal layer35b. The mesa M has an elongated shape in one direction, and for example, a length thereof may be more than four times longer and less than seven times longer than a width thereof. When the mesa M is formed to have an elongated shape in one direction, a region where the first pad metal layer35acontacts a first conductivity type semiconductor layer23may be relatively reduced, thereby securing the light emitting area. In some embodiments, one edge of the mesa M may be formed to have recesses or protrusions. A dielectric layer29covers a conductive oxide layer28and covers a side surface of the mesa M. A portion of the dielectric layer29partially covers the first conductivity type semiconductor layer23exposed around the mesa M as described with reference toFIG.5. The dielectric layer29has a plurality of openings29aexposing the conductive oxide layer28, and locations of the openings29aare adjusted to improve resistance to electrical overstress and electrostatic discharge. This will be described later. A metal reflection layer31is disposed on the dielectric layer29and connects to the conductive oxide layer28through the openings29aof the dielectric layer29. In the exemplary embodiment, the conductive oxide layer28and the metal reflection layer31cover most of an upper surface of the mesa M. However, edges of the conductive oxide layer28and the metal reflection layer31are spaced apart from the edge of the mesa M, and in particular, spaced farther from one edge of the mesa M that is adjacent to the outer contact portions35a1. In particular, since the edge of the conductive oxide layer28is spaced farther from the outer contact portions35, it is possible to prevent the occurrence of device failure due to electrical overstress or electrostatic discharge. A lower insulation layer33may cover the dielectric layer29and the metal reflection layer31, and may cover a portion of the first conductivity type semiconductor layer23exposed around the mesa M. The lower insulation layer33exposes the first conductivity type semiconductor layer23in recess regions of the mesa M. Although the lower insulation layer33may cover the first conductivity type semiconductor layer23, it may be formed to expose a region near an edge of the first conductivity type semiconductor layer23as shown inFIG.5. The lower insulation layer33also has a second opening33bexposing the metal reflection layer31. The first pad metal layer35ain the illustrated exemplary embodiment is disposed over the mesa M except for a region where the outer contact portions35a1are formed. However, in the exemplary embodiment ofFIG.5, the first pad metal layer35acovers not only the upper region of the mesa M but also the side surface of the mesa M and a portion of the first conductivity type semiconductor layer23around the mesa M. An edge of the first pad metal layer35amay also be located on the mesa M in a region between the recesses of the mesa M. The first pad metal layer35amay include a region that has a wide width toward one side of the mesa and a region that has a narrow width extending from thereof. The outer contact portions35a1are formed along one edge of the mesa M, and may be formed in the recesses formed at one edge of the mesa M. The outer contact portions35a1may be formed to have an elongated shape along the longitudinal direction of the mesa M. As illustrated in the drawing, the outer contact portions35a1may also be formed by the region having the wide width and the region having the narrow width of the first pad metal layer35a. The first pad metal layer35amay have protrusions along one edge of the mesa M, and the protrusions may form the outer contact portions35a1. A region between the protrusions among the edges of the first pad metal layer35amay be located on the mesa M, and may further be located on the conductive oxide layer28. The second pad metal layer35bmay be disposed in the upper region of the mesa M. The second pad metal layer35bmay extend along the region having the narrow width of the first pad metal layer35a. The second pad metal layer35bmay be electrically connected to the metal reflection layer31through the second openings33bof the lower insulation layer33. The second openings33bof the lower insulation layer33may be disposed under the second bump pad39b, but they may be spaced apart from the second bump pad39bin the lateral direction as illustrated inFIG.9. In the exemplary embodiment, the openings29aof the dielectric layer29are disposed apart from the edges of the mesas M, and in particular, disposed farther apart from the edge of the mesas M adjacent to the outer contact portions35a1. In particular, among the openings29alocated under a first bump pad39a, a distance Dv1of a first set of the opening29athat is disposed closest to the outer contact portion35a1in the vertical direction is greater than a distance Ds of a second set of the opening29athat is disposed closest to the contact portion as illustrated inFIG.9. Further, the second set of the opening29athat is disposed closest to the contact portion35a1is disposed farther from the edge of the mesa M than the opening closest to the edge of the mesa M. Locations of the openings29adisposed under the second bump pad39bas well as those of the openings29adisposed under the first bump pad39amay be adjusted, and locations of a third set of the openings29adisposed under the first bump pad39aand the second bump pad39bmay also be adjusted. More particularly, as shown inFIG.9, a separation distance Dv2of the third set of the opening29athat is disposed apart from the outer contact portion35a1in the vertical direction may be greater than the separation distance Ds of the second set of the opening29athat is disposed closest to the contact portion35a1. The openings29adisposed under the second bump pad39bmay also be disposed in the same manner as illustrated in the drawing. FIG.10is a schematic plan view illustrating a light emitting diode according to another exemplary embodiment. Referring toFIG.10, the light emitting diode according to the exemplary embodiment is substantially similar to the light emitting diode described with reference toFIG.9, but a dielectric layer29has openings29aand129athat have different sizes from each other in the exemplary embodiment, as shown inFIG.10. In the illustrated exemplary embodiment, relatively large openings129aare disposed closer to outer contact portions35a1than relatively small openings29a. In particular, the relatively large openings129ain a lower region of a first bump pad39aare disposed closer to the outer contact portion35a1than the relatively small openings29a. The relatively large openings129amay also be disposed closer to the outer contact portions35a1than the relatively small openings29ain a lower region of the second bump pad39band other regions. The relatively large openings129amay prevent current from being concentrated at a specific point, thereby improving resistance of the light emitting diode to electrical overstress or electrostatic discharge. The openings129ain the illustrated exemplary embodiment are shown as being circular, but their shapes may vary. In particular, the openings129amay have an elongated shape along the longitudinal direction of the mesa M, and for example, may have an ellipse shape or a bar shape. FIG.11is a schematic plan view illustrating a light emitting diode according to another exemplary embodiment. Referring toFIG.11, the light emitting diode according to the exemplary embodiment is substantially similar to the light emitting diode described with reference toFIG.10, but bar-shaped openings129bare adjacent to outer contact portions35a1in the exemplary embodiment. The bar-shaped opening129bmay be disposed under a first bump pad39a, and bar-shaped openings129bmay further be disposed under a second bump pad39band in other regions. The bar-shaped openings129bmay be disposed flush with a first opening33aof a lower insulation layer33or the outer contact portions35a1. The opening129bis disposed between the outer contact portion35a1and openings29ato prevent current from being concentrated at a specific point, thereby improving the light emitting diode's resistance to electrical overstress or electrostatic discharge. End portions of the bar-shaped openings129bmay be formed to have a relatively wide width to facilitate patterning. FIG.12is a schematic plan view illustrating a light emitting diode according to another exemplary embodiment. Referring toFIG.12, the light emitting diode according to the exemplary embodiment is substantially similar to the light emitting diode described with reference toFIG.11, but a single bar-shaped opening129cis formed continuously over outer contact portions35a1. The bar-shaped opening129cis not necessarily a straight line. In particular, a portion of the opening129cdisposed under a first bump pad39amay be disposed farther from the outer contact portion35a1than other portions. FIG.13is a schematic plan view illustrating a light emitting diode according to another exemplary embodiment of the present disclosure, andFIG.14is a cross-sectional view taken along the line C-C ofFIG.13. Referring toFIG.13andFIG.14, the light emitting diode according to the exemplary embodiment is substantially similar to those in the above-described embodiments, but a plurality of light emitting cells C1and C2are formed and t connected in series in the exemplary embodiment. First and second light emitting cells C1and C2are disposed on the substrate21. The first and second light emitting cells C1and C2are separated from each other by an isolation region I exposing the substrate21(seeFIG.14). As such, semiconductor layers of the first light emitting cell C1and the second light emitting cell C2are spaced apart from each other. Each of the first and second light emitting cells C1and C2are disposed to face each other and may have a square or rectangular shape, respectively. In particular, the first and second light emitting cells C1and C2may have elongated rectangular shapes in a direction facing each other. The isolation region I separates the light emitting cells C1and C2from each other. As such, a surface of the substrate21is exposed in the isolation region I through semiconductor layers. The isolation region I is formed using photolithography and etching processes, a photoresist pattern having a gentle inclined surface is formed and the semiconductor layers are etched using the photoresist pattern as a mask, thereby forming relatively gently inclined side surfaces in the isolation region I. The light emitting cells C1and C2face each other with the isolation region I interposed therebetween. Side surfaces of the light emitting cells C1and C2that face each other are defined as inner side surfaces, and side surfaces of the light emitting cells other than the inner side surfaces are defined as outer side surfaces. Therefore, the first conductivity type semiconductor layers23in the first and second light emitting cells C1and C2also include inner and outer side surfaces, respectively. For example, the first conductivity type semiconductor layer23may include one inner side surface and three outer side surfaces. A mesa M is disposed on each of first conductivity type semiconductor layers23. The mesa M may be located within a region surrounded by the side surfaces of the first conductivity type semiconductor layer23, and thus, regions near edges adjacent to the outer side surfaces of the first conductivity type semiconductor layer23are not covered by the mesa M, but are exposed to the outside. In another exemplary embodiment, a side surface of the mesa M and a side surface of the first conductivity type semiconductor layer23on a sidewall of the isolation region I may be continuous with each other. Each mesa M includes a second conductivity type semiconductor layer27and an active layer25. The active layer25is interposed between the first conductivity type semiconductor layer23and the second conductivity type semiconductor layer27. Each mesa M has recesses, first openings33aof a lower insulation layer33are formed in the recesses, which will be described later, and outer contact portions35a1are formed through the first openings33a. A conductive oxide layer28is disposed on each mesa M, and a dielectric layer29covers the conductive oxide layer28and the mesa Mon each of the light emitting cells C1and C2. The conductive oxide layer28is in ohmic contact with the second conductivity type semiconductor layer27. The conductive oxide layer28may be disposed over almost an entire region of the mesa M in an upper region of the mesa M. However, the conductive oxide layer28may be spaced apart from an edge of the mesa M. The dielectric layer29may cover the upper region and side surfaces of the mesa M, and may cover the first conductivity type semiconductor layer exposed around the mesa M. The dielectric layer29also has openings29aand129b, and the bar-shaped openings129bare disposed between the outer contact portions35a1and the openings29a. In the illustrated exemplary embodiment, the bar-shaped openings129bare illustrated and described as an example, but in addition to the bar shape, circular, elliptical or other shape openings having a larger size than that of the openings29amay be disposed, and a single line-shaped opening that continuously stretches out longitudinally may be disposed on each mesa M, as shown inFIGS.13and14. A metal reflection layer31is disposed on the dielectric layer29and connects to the conductive oxide layer28through the openings29aand129bof the dielectric layer29. The metal reflection layer31is disposed in the upper region of the mesa M of each of the light emitting cells C1and C2. The lower insulation layer33covers the mesas M and covers the metal reflection layer31and the dielectric layer29. The lower insulation layer33also covers the first conductivity type semiconductor layer23and the substrate21exposed to the outside of the dielectric layer29. In a case that the substrate21is a patterned sapphire substrate, the lower insulation layer33may be formed along shapes of protrusions on the substrate21. The lower insulation layer33includes the first openings33aexposing the first conductivity type semiconductor layer23in the recesses of each mesa M, and further includes second openings33b1exposing the metal reflection layer31on the second light emitting cell C2and a third opening33b2exposing the metal reflection layer31on the first light emitting cell C1. The first openings33aexpose the first conductivity type semiconductor layer23along outer surfaces of the mesa M, and the third opening33b2exposes the metal reflection layer31on the first light emitting cell C1near the isolation region I. The third openings33b2may generally have an elongated shape along the isolation region I, but they are not necessarily limited thereto, and may have various shapes. The second openings33b1may be located on the second light emitting cell C2, and may be located in a lower region of a second bump pad39b. However, in another exemplary embodiment, the second openings33b1may be disposed to be apart from the second bump pad39bon the second light emitting cell C2in the lateral direction. InFIG.14, the lateral direction corresponds to a vertical direction. A first pad metal layer35a, a second pad metal layer35band a connection metal layer are disposed on the lower insulation layer33. The first pad metal layer35ais disposed on the first light emitting cell C1, and is in ohmic contact with the first conductivity type semiconductor layer23exposed around the mesa M. As shown inFIG.13, the first pad metal layer35amay be in ohmic contact with the first conductivity type semiconductor layer23through the first opening33aof the lower insulation layer33along a periphery of the mesa M to form the outer contact portions35a1. In the drawing, the first pad metal layer35aintermittently contacts the first conductivity type semiconductor layer23in the recesses of the mesa M along the periphery of the mesa M, but is not limited thereto, and may remain contacting the first conductivity type semiconductor layer23. More particularly, the lower insulation layer33may be formed to have the first opening33athat causes the first conductivity type semiconductor layer23to be exposed along the periphery of the mesa M, and the first pad metal layer35amay maintain contact with the first conductivity type semiconductor layer23through the first opening33aof the lower insulation layer33. The bar-shaped openings129bof the dielectric layer29may be flush with the first openings33aof the lower insulation layer33, and thus, may be flush with the outer contact portions35a1. The second pad metal layer35bis disposed on the second light emitting cell C2and is connected to the metal reflection layer31on the second light emitting cell C2through the second opening33b1of the lower insulation layer33. The second pad metal layer35bis disposed on the mesa M, and is insulated from the first conductivity type semiconductor layer23. For example, the second pad metal layer35bmay be separated from side surfaces of the mesa M on the second light emitting cell C2. The connection metal layer35cmay be electrically connected to the metal reflection layer31on the first light emitting cell C1through the third opening33b2of the lower insulation layer33, and may be electrically connected to the first conductivity type semiconductor layer23of the second light emitting cell C2through the first openings33aof the second light emitting cell C2. Accordingly, the first and second light emitting cells C1and C2are connected to each other in series through the connection metal layer35c. The connection metal layer35cmay contact the first conductivity type semiconductor layer23in the recesses of the mesa M along the edge of the second light emitting cell C2to form the outer contact portions35a1. In particular, the connection metal layer35cmay contact the first conductivity type semiconductor layer23continuously or intermittently along the periphery of the mesa M. In addition, the connection metal layer35cmay surround the second pad metal layer35b, and a boundary region35bcmay be formed between the connection metal layer35cand the second pad metal layer35b. Meanwhile, a boundary region35acmay be formed between the connection metal layer35cand the first pad metal layer35a. The boundary regions35acand35bcare covered with an upper insulation layer37which will be described later. The first and second pad metal layers35aand35band the connection metal layer35cmay be formed in the same process and may include substantially the same material. For example, the first and second pad metal layers35aand35band the connection metal layer35cmay include an ohmic reflection layer such as an Al layer, and the ohmic reflection layer may be formed on an adhesive layer such as Ti, Cr, or Ni. Furthermore, a protective layer of a single layer or a multiple layer structure such as Ni, Cr, Au, or the like may be formed on the ohmic reflection layer. The first and second pad metal layers35aand35band the connection metal layer35cmay have multilayer structures of Cr/Al/Ni/Ti/Ni/Ti/Au/Ti, for example. The upper insulation layer37is disposed on the first pad metal layer35a, the second pad metal layer35b, and the connection metal layer35c, and has a first opening37aexposing the first pad metal layer35aand a second opening37bexposing the second pad metal layer35b. The upper insulation layer37also covers the first pad metal layer35aand the connection metal layer35cconnected to the first conductivity type semiconductor layer23in the periphery of the mesa M. As shown inFIG.13, a region between the first pad metal layer and the second connection metal layer35cand an edge of the first conductivity type semiconductor layer23is covered with the upper insulation layer37. In addition, the upper insulation layer37may cover the connection metal layer35con the isolation region I, and may be formed to have irregularities according to a shape of the connection metal layer35c. The upper insulation layer37protects the first and second pad metal layers35aand35band the connection metal layer from external environments such as moisture. The first opening37ais formed within an upper region of the first pad metal layer35a, and thus is separated from the connection metal layer35cand the third opening33b2of the lower insulation layer33. The second opening37bis also disposed limitedly on the second pad metal layer35b, and is separated from the connection metal layer35c. In the exemplary embodiment, the first and second pad metal layers35aand35bexposed through the first and second openings37aand37bof the upper insulation layer37may serve as bonding pads to which the solder is directly bonded. Alternatively, as described with reference toFIGS.1and2, the first and second bump pads39aand39bmay cover the first and second pad metal layers35aand35bexposed through the first and second openings37aand37bof the upper insulation layer37, respectively. The first and second bump pads39aand39bmay be formed in the first and second openings37aand37bof the upper insulation layer37, but the inventive concepts are not limited thereto, and the first and second bump pads39aand39bmay cover and seal the first and second openings37aand37b. FIG.15is a schematic plan view illustrating a light emitting diode according to another exemplary embodiment. Referring toFIG.15, the light emitting diode according to the exemplary embodiment includes six light emitting cells C1, C2, C3, C4, C5, and C6, and the light emitting cells are connected in series. Each of the light emitting cells C1C2, C3, C4, C5, and C6includes a first conductivity type semiconductor layer23and a mesa M as described with reference toFIG.13, and is separated from one another by an isolation region. Each mesa M has a via hole30aexposing the first conductivity type semiconductor layer23, and a lower insulation layer33has a first opening33aexposing the first conductivity type semiconductor layer23in each via hole30a. In addition, the lower insulation layer33has a second opening33bexposing a metal reflection layer31on each light emitting cell. A first pad metal layer35ais disposed on the first light emitting cell C1and forms inner contact portions35a2in the via holes30ain the first light emitting cell C1. A second pad metal layer35bis disposed on the last light emitting cell, that is, the sixth light emitting cell C6, and is connected to the metal reflection layer31through the second opening33b. Connection metal layers35cconnect adjacent light emitting cells in series. The connection metal layers35celectrically connect the metal reflection layer31of the adjacent light emitting cells and the first conductivity type semiconductor layer23. The inner contact portions35a2are formed in the via holes30aof the second, third, fourth, fifth, and sixth light emitting cells C2, C2, C3, C4, C5, and C6by the connection metal layers35c. In the illustrated exemplary embodiment, the inner contact portions35a2are formed instead of outer contact portions35a1, but the outer contact portions35a1may be formed. In the exemplary embodiment, the dielectric layer29includes openings229btogether with openings29a. The openings29aare widely distributed on each mesa M. The openings229bsurround the inner contact portions35a2on each mesa M. The opening229bis disposed between the inner contact portion35a2and the openings29a. More particularly, the opening229bis disposed closer to the inner contact portion35a2than the openings29a. As such, it is possible to prevent device failure due to electrical overstress or electrostatic discharge from occurring in the opening adjacent to the inner contact portion35a2. A first bump pad39ais disposed on the first light emitting cell C1and a second bump pad39bis disposed on the sixth light emitting cell C6. The first, second, third, fourth, fifth, and sixth light emitting cells C1, C2, C2, C3, C4, C5, and C6are connected in series between the first bump pad39aand the second bump pad39b. In the illustrated exemplary embodiment, although the opening229bis illustrated as having a ring shape surrounding the via hole30a, the inventive concepts are not limited thereto. For example, the opening229bmay be formed in a portion of the outer periphery of the via hole30a. However, the opening229bmay have a longer shape than the opening29a. In another exemplary embodiment, openings329bas shown inFIG.16may be formed by connecting the openings of the dielectric layer29surrounding the via holes30aon each mesa M. An exemplary experiment of electrostatic discharge Electrostatic discharge characteristics of the light emitting diode (Comparative Example) in the exemplary embodiment ofFIG.9in which the openings29aare disposed adjacent to the external contacts35a1and those of the light emitting diodes (Examples 1, 2, 3, and 4) in the exemplary embodiments ofFIGS.9through12are compared. Sixteen (16) samples were prepared for each light emitting diode, and voltages from 1 kV to 6 kV were applied three times at 0.3 second intervals to determine whether device defects occurred. The voltage was increased in an increment of 1 kV from 1 kV to 4 kV, and increased in an increment of 0.5 kV from 4 kV to 6 kV. As for the light emitting diodes of the Comparative Example, all of the light emitting diodes were defective due to electrostatic discharge at 4 kV, and, as for the light emitting diodes of Inventive Example 1 ofFIG.9, two device defects occurred at 4 kV and 14 device defects occurred at 4.5 kV. As for the light emitting diodes of Inventive Example 2 ofFIG.10, two device defects occurred at 4.5 kV and 14 device defects occurred at 5 kV, and, as for the light emitting diodes of Inventive Example 3 ofFIG.6, one device defect occurred at 4.5 kV, six device defects occurred at 5 kV, and six device defects occurred at 5.5 kV. As for the light emitting diodes of Inventive Example 4 ofFIG.12, one device defect occurred at 4.5 kV, seven device defects occurred at 5 kV, and eight device defects occurred at 5.5 kV. The above experimental results are shown in Table 1 below. TABLE 1Number of Device Failure(Total 16ea)Applied voltage(kV)12344.555.56Comparative———16exampleInventive———214example 1Inventive———214example 2Inventive————1663example 3Inventive———1——78example 4 Referring to Table 1, it can be seen that the light emitting diodes of Examples 1, 2, 3, and 4 have stronger resistance to electrostatic discharge than that of Comparative Example, and in particular, the light emitting diode of Example 4 (FIG.12) having an elongated bar-shaped opening has the strongest resistance to electrostatic discharge. FIG.17is an exploded perspective view illustrating a lighting apparatus to which a light emitting diode according to an exemplary embodiment is applied. Referring toFIG.17, the lighting apparatus according to the exemplary embodiment includes a diffusive cover1010, a light emitting diode module1020, and a body1030. The body1030may receive the light emitting diode module1020and the diffusive cover1010may be disposed on the body1030to cover an upper surface of the light emitting diode module1020. The body1030may have any shape so long as the body can supply electric power to the light emitting diode module1020while receiving and supporting the light emitting diode module1020. For example, as shown in the drawing, the body1030may include a body case1031, a power supply1033, a power supply case1035, and a power source connection1037. The power supply1033is received in the power supply case1035to be electrically connected to the light emitting diode module1020, and may include at least one IC chip. The IC chip may regulate, change or control electric power supplied to the light emitting diode module1020. The power supply case1035may receive and support the power supply1033, and the power supply case1035having the power supply1033secured therein may be disposed within the body case1031. The power source connection1037is disposed at a lower end of the power supply case1035and is coupled thereto. Accordingly, the power source connection1037is electrically connected to the power supply1033within the power supply case1035and can serve as a passage through which power can be supplied from an external power source to the power supply1033. The light emitting diode module1020includes a substrate1023and a light emitting diode1021disposed on the substrate1023. The light emitting diode module1020may be disposed at an upper portion of the body case1031and electrically connected to the power supply1033. As the substrate1023, any substrate capable of supporting the light emitting diode1021may be used without limitation. For example, the substrate1023may include a printed circuit board having interconnects formed thereon. The substrate1023may have a shape corresponding to a securing portion formed at the upper portion of the body case1031so as to be stably secured to the body case1031. The light emitting diode1021may include at least one of the light emitting diodes according to the exemplary embodiments described above. The diffusive cover1010is disposed on the light emitting diode1021and may be secured to the body case1031to cover the light emitting diode1021. The diffusive cover1010may include a light transmitting material and light orientation of the lighting apparatus may be adjusted through regulation of the shape and optical transmissivity of the diffusive cover1010. Thus, the diffusive cover1010may be modified to have various shapes depending on usage and applications of the lighting apparatus. FIG.18is a cross-sectional view illustrating a display apparatus to which a light emitting diode according to another exemplary embodiment of the present disclosure is applied. The display apparatus according to the exemplary embodiment includes a display panel2110, a backlight unit supplying light to the display panel2110, and a panel guide supporting a lower edge of the display panel2110. The display panel2110is not particularly limited and may be, for example, a liquid crystal panel including a liquid crystal layer. Gate driving PCBs may be further disposed at the periphery of the display panel2110to supply driving signals to a gate line. Here, the gate driving PCBs may be formed on a thin film transistor substrate instead of being formed on separate PCBs. The backlight unit includes a light source module which includes at least one substrate and a plurality of light emitting diodes2160. The backlight unit may further include a bottom cover2180, a reflective sheet2170, a diffusive plate2131, and optical sheets2130. The bottom cover2180may be open at an upper surface thereof to receive the substrate, the light emitting diodes2160, the reflective sheet2170, the diffusive plate2131, and the optical sheets2130. In addition, the bottom cover2180may be coupled to the panel guide. The substrate may be disposed under the reflective sheet2170to be surrounded by the reflective sheet2170. Alternatively, when a reflective material is coated on a surface thereof, the substrate may be disposed on the reflective sheet2170. Further, a plurality of substrates may be arranged flush with one another, without being limited thereto. However, it should be understood that the backlight unit includes a single substrate. The light emitting diodes2160may include at least one of the light emitting diodes according to the exemplary embodiments described above. The light emitting diodes2160may be regularly arranged in a predetermined pattern on the substrate. In addition, a lens2210may be disposed on each of the light emitting diodes2160to improve uniformity of light emitted from the plurality of light emitting diodes2160. The diffusive plate2131and the optical sheets2130are disposed above the light emitting diode2160. Light emitted from the light emitting diodes2160may be supplied in the form of sheet light to the display panel2110through the diffusive plate2131and the optical sheets2130. In this way, the light emitting diodes according to the exemplary embodiments may be applied to direct type displays like the display apparatus according to the exemplary embodiment. FIG.19is a cross-sectional view illustrating a display apparatus to which a light emitting diode according to another exemplary embodiment of the present disclosure is applied. The display apparatus according to the exemplary embodiment includes a display panel3210on which an image is displayed, and a backlight unit disposed at a rear side of the display panel3210and emitting light thereto. Further, the display apparatus includes a frame3240supporting the display panel3210and receiving the backlight unit, and covers3270,3280surrounding the display panel3210. The display panel3210is not particularly limited and may be, for example, a liquid crystal panel including a liquid crystal layer. A gate driving PCB may be further disposed at the periphery of the display panel3210to supply driving signals to a gate line. Here, the gate driving PCB may be formed on a thin film transistor substrate instead of being formed on a separate PCB. The display panel3210is secured by the covers3270,3280disposed at upper and lower sides thereof, and the cover3280disposed at the lower side of the display panel3210may be coupled to the backlight unit. The backlight unit supplying light to the display panel3210includes a lower cover3270partially open at an upper surface thereof, a light source module disposed at one side inside the lower cover3270, and a light guide plate3250disposed flush with the light source module and converting spot light into sheet light. In addition, the backlight unit according to the exemplary embodiment may further include optical sheets3230disposed on the light guide plate3250to spread and collect light, and a reflective sheet3260disposed at a lower side of the light guide plate3250and reflecting light traveling in a downward direction of the light guide plate3250towards the display panel3210. The light source module includes a substrate3220and a plurality of light emitting diodes3110arranged at constant intervals on one surface of the substrate3220. As the substrate3220, any substrate capable of supporting the light emitting diodes3110and being electrically connected thereto may be used without limitation. For example, the substrate3220may include a printed circuit board. The light emitting diodes3110may include at least one of the light emitting diodes according to the exemplary embodiments described above. Light emitted from the light source module enters the light guide plate3250and is supplied to the display panel3210through the optical sheets3230. The light guide plate3250and the optical sheets3230convert spot light emitted from the light emitting diodes3110into sheet light. In this way, the light emitting diodes according to the exemplary embodiments may be applied to edge type displays like the display apparatus according to the exemplary embodiment. FIG.20is a cross-sectional view illustrating a head light to which a light emitting diode according to another exemplary embodiment of the present disclosure is applied. Referring toFIG.20, the headlight according to the exemplary embodiment includes a lamp body4070, a substrate4020, a light emitting diode4010, and a cover lens4050. The headlight may further include a heat dissipation unit4030, a support rack4060, and a connection member4040. The substrate4020is secured by the support rack4060and is disposed above the lamp body4070. As the substrate4020, any member capable of supporting the light emitting diode4010may be used without limitation. For example, the substrate4020may include a substrate having a conductive pattern, such as a printed circuit board. The light emitting diode4010is disposed on the substrate4020and may be supported and secured by the substrate4020. In addition, the light emitting diode4010may be electrically connected to an external power source through the conductive pattern of the substrate4020. Further, the light emitting diode4010may include at least one of the light emitting diodes according to the exemplary embodiments described above. The cover lens4050is disposed on a path of light emitted from the light emitting diode4010. For example, as shown in the drawing, the cover lens4050may be separated from the light emitting diode4010by the connection member4040and may be disposed in a direction of supplying light emitted from the light emitting diode4010. By the cover lens4050, an orientation angle and/or a color of light emitted by the headlight can be adjusted. On the other hand, the connection member4040is disposed to secure the cover lens4050to the substrate4020while surrounding the light emitting diode4010, and thus can act as a light guide that provides a luminous path4045. The connection member4040may include a light reflective material or coated therewith. On the other hand, the heat dissipation unit4030may include heat dissipation fins4031and/or a heat dissipation fan4033to dissipate heat generated upon operation of the light emitting diode4010. In this way, the light emitting diodes according to the exemplary embodiments may be applied to headlights like the headlight according to the exemplary embodiment, particularly, vehicular headlights. Although the various embodiments of the present disclosure have been described above, the present disclosure is not limited to these embodiments, and various modifications can be made. In addition, the elements described in one embodiment can be applied to other embodiments without departing from the technical spirit according to the appended claims of the present disclosure. | 91,540 |
11862456 | DESCRIPTION OF EMBODIMENTS The present inventor has earnestly studied to solve the above-described problems in polished-wafer cleaning, and consequently found that when brush-cleaning is performed with carbonated water in a brush cleaning step, electrification and particle adhesion by brush cleaning are reduced, and cleaning level equivalent to that with SC1 can be achieved. Moreover, an alkaline chemical solution like SC1 is not used but carbonated water is used to clean the wafer on the entire surface of which a polishing agent immediately after polishing still adheres. This makes it possible to reduce defects on the wafer and prevent surface roughness degradation. Further, the inventor has found that carbonated water and ozone water allow treatments at normal temperature and recycling of waste liquids thereof, thereby leading to cost reduction and environmental load reduction. These findings have led to the completion of the present invention. Hereinafter, an example of embodiments according to the present invention will be described with reference to the drawings in detail, but the present invention is not limited thereto. FIG.1is a flowchart showing an outline of the inventive method for cleaning a semiconductor wafer. First, a wafer is prepared with a polishing agent immediately after polishing, the polishing agent adhering on the entire surface of the wafer (Step1). The type of the wafer is not particularly limited, but is here a silicon wafer. Herein, the conditions under which the polishing is performed on the wafer are not particularly limited. As the polishing agent, it is possible to use silica. Particularly, the silica particle size is such that the primary particle diameter is 10 to 35 nm, and the silica concentration is 0.01 to 1.0 mass %. This silica can be removed by a brush cleaning step and a second ozone-water treatment step (particularly cleaning using hydrofluoric acid) to be described below. Next, as in Step2ofFIG.1, the silicon wafer having a polishing agent immediately after polishing adhering on the entire surface is cleaned with ozone water in a first ozone-water treatment step. Thereby, organic matter of the adhering polishing agent is decomposed and removed, and an oxide film is formed. The cleaning method here is not particularly limited, as long as ozone water is used, and can be, for example, brush cleaning or spin cleaning. In this event, the ozone water may be at normal temperature and may have a pH of 7.0 or less. Such a material enables more easy and effective organic matter removal and oxide film formation. Additionally, the lower limit value of the pH of this ozone water is not particularly limited, and can be, for example, 0. Further, the ozone water may have a concentration of 10 ppm or more and 50 ppm or less. With the ozone water concentration of 10 ppm or more, this enables further effective removal of the organic matter, and the wafer quality can be improved more reliably. Meanwhile, with the concentration of 50 ppm or less, it is possible to prevent the formation of excessively thick oxide film. Furthermore, the oxide film formed in this event may have a thickness of 0.8 nm or more and 1.5 nm or less. With the oxide film thickness of 0.8 nm or more, it is possible to more sufficiently remove the organic matter and metal contamination attributable to the polishing agent. Meanwhile, with the thickness of 1.5 nm or less, it is possible to shorten the time for a step of removing the formed oxide film. Next, as in Step3ofFIG.1, brush cleaning (physical cleaning) is performed with carbonated water. By this brush cleaning step, the polishing agent is removed. In this event, the carbonated water may be at normal temperature and may have a pH of 7.0 or less. Such a material enables more reliable reduction of defect generation on the wafer surface and prevention of surface roughness degradation. Additionally, the lower limit value of the pH of this carbonated water is not particularly limited, and can be, for example, 0. Moreover, the carbonated water may have a concentration of 100 ppm or more and 1000 ppm or less. With the carbonated water concentration of 100 ppm or more, further sufficient cleaning effect by the brush cleaning can be obtained. Meanwhile, with the concentration of 1000 ppm or less, bubbling during the cleaning and its adverse influence can be suppressed. Next, as in Step4ofFIG.1, a second ozone-water treatment step is performed which includes: removing the oxide film with hydrofluoric acid to remove metal contamination; and then forming an oxide film again with ozone water. This second ozone-water treatment step is performed one or more times. The upper limit of the number of times the second ozone-water treatment step is performed is not particularly limited. Moreover, since it depends on the extent of the metal contamination, and so forth, the maximum number of the treatments performed cannot be limited. In this event, as in the first ozone-water treatment step, the ozone water may have a concentration of 10 ppm or more and 50 ppm or less. Further, the oxide film thus formed may have a thickness of 0.8 nm or more and 1.5 nm or less. Furthermore, the hydrofluoric acid may have a concentration of 1.0% or less. With the hydrofluoric acid concentration of 1.0% or less, the time for the oxide film removal is not too short, so that it is not difficult to control the time. Additionally, the lower limit of the hydrofluoric acid concentration can be, for example, higher than 0%. Furthermore, the oxide film removal with hydrofluoric acid and the oxide film formation with ozone water may be carried out by spin cleaning or batch cleaning. Such cleaning methods are commonly performed and suitable. The oxide film removal and formation can be carried out individually or plural simultaneously. Furthermore, among waste liquids generated in each of the above steps, waste liquids of the ozone water and the carbonated water can be collected and reused. The re-uses of these waste liquids can lead to further cost reduction and environmental load reduction. Further, a drying step is performed thereafter (Step5). Thus, the cleaning is ended. EXAMPLE Hereinafter, the present invention will be more specifically described with reference to Example and Comparative Examples. However, the present invention is not limited to Example. Example According to the cleaning flow of the present invention as shown inFIG.1, the first ozone-water treatment step was performed with ozone water on a polished silicon wafer which had a polishing agent adhering thereon. Then, the brush cleaning step was performed with carbonated water. Subsequently, the second ozone-water treatment step was performed once by spin cleaning with hydrofluoric acid and ozone water, followed by the drying treatment. These steps were performed under the following conditions.First ozone-water treatment step: ozone water concentration=30 ppm, pH=5.0Brush cleaning step: carbonated water concentration=100 ppm, pH=4.0Second ozone-water treatment step: hydrofluoric acid concentration=1.0 mass %, pH=3.0; ozone water concentration=30 ppm, pH=5.0 Comparative Examples 1, 2 Cleaning was carried out as in Example, except that the brush cleaning step was performed with pure water (Comparative Example 1) or SC1 (Comparative Example 2) according to the cleaning flow as shown inFIG.4. Note that, in Example and Comparative Example 1, among waste liquids generated in the steps, waste liquids of the ozone water, the carbonated water or the pure water were collected and reused. In the wafer evaluation of Example and Comparative Examples 1, 2, particles with diameters of 19 nm or more on the cleaned wafers were measured using a wafer inspection system SP5 manufactured by KLA-Tencor Corporation.FIG.2and Table 1 show the measurement result. Moreover, regarding the haze value, Original Std. Classic Average of DW2 was used.FIG.3and Table 1 show the measurement result. TABLE 1Chemical solutionThe number ofHazeusedparticles(ppb)Comparativepure water32555Example 1ComparativeSC112260Example 2Examplecarbonated10555water As shown inFIG.2and Table 1, in Example, the number of particles was improved in comparison with Comparative Example 1 using pure water in the brush cleaning step. Example achieved the cleaning level equivalent to or higher than that of Comparative Example 2 using SC1. Moreover, as shown inFIG.3and Table 1, the haze (surface roughness) degradation as in Comparative Example 2 using SC1 was not observed in Example. Further, as in the case of pure water in Comparative Example 1, collecting and reusing the waste liquid of carbonated water used in Example successfully led to cost reduction and environmental load reduction. It should be noted that the present invention is not limited to the above-described embodiments. The embodiments are just examples, and any embodiments that substantially have the same feature and demonstrate the same functions and effects as those in the technical concept disclosed in claims of the present invention are included in the technical scope of the present invention. | 9,170 |
11862457 | DETAILED DESCRIPTION OF THE EMBODIMENTS Hereinafter, a wafer cleaning apparatus according to the exemplary embodiment will be described referring toFIGS.1to8. FIG.1is a schematic cross-sectional view for explaining a wafer cleaning apparatus according to some embodiments.FIG.2is a plan view for explaining rotation of a wafer ofFIG.1.FIG.3is a conceptual diagram for explaining the operation of a first rotor unit and a second rotor unit ofFIG.1.FIG.4is a schematic conceptual diagram for explaining an optical system ofFIG.1.FIG.5is a cross-sectional view for explaining a calibration window ofFIG.1.FIG.6is a plan view for explaining the calibration window ofFIG.1.FIG.7is an exemplary cross-sectional view for explaining a first coating layer ofFIG.5.FIG.8is an exemplary cross-sectional view for explaining a second coating layer ofFIG.5. Referring toFIGS.1to8, the wafer cleaning apparatus according to some embodiments includes a housing100, a laser module110, an optical system120, a reflector130, a calibration window140, a transparent window150, a chuck160, a bowl180, a drain guide portion190, and a chemical supply unit200. A wafer W may be disposed on the chuck160. The chuck160may fix the disposed wafer W. The chuck160may be rotatable. As the chuck160rotates, the wafer W fixed on/to the chuck160may also rotate. For example, as shown inFIG.2, the wafer W may rotate in a first rotation direction a1or a second rotation direction a2. The wafer W may include a central region We and an edge region We. In some embodiments, the wafer W may include an exposed portion Wb and a non-exposed portion Wa. The exposed portion Wb may be a region which is irradiated with light in an exposure process of the wafer W, and the non-exposed portion Wa may be a region which is not irradiated with light in the exposure process. For example, an exposure mask (not shown) may be disposed on the wafer W. When light irradiates from the upper part of the exposure mask, the light that has passed through a transmission portion of the exposure mask may irradiate a part of the wafer W to form the exposure portion Wb. The other part of the wafer W that is not irradiated with light by a shielding portion of the exposure mask may form the non-exposed portion Wa. The wafer W including the exposed portion Wb and the non-exposed portion Wa may include, but is not limited to, a photoresist film. In some embodiments, the chuck160may include a grip portion161and a side wall portion163. The grip portion161may fix the wafer W by coming into contact with the side surface of the wafer W. Further, the grip portion161may include a heat insulating material. When the wafer W is heated by the laser module110, the grip portion161may block transfer of heat to prevent thermal damage of other components (e.g., the side wall portion163of the chuck160). The side wall portion163may surround a side surface of a housing100to be described below In some embodiments, the rotating chuck160may be supported by a fixing portion170and a bearing172. The fixing portion170may fix the chuck160on the ground on which the wafer cleaning apparatus according to some embodiments is disposed. The fixing portion170may not rotate. The bearing172may be interposed between the fixing portion170and the chuck160to allow the chuck160to rotate. Accordingly, the chuck160may be configured to be rotatable despite it is supported by the fixing portion170that does not rotate. Although the bearing172is shown as only being interposed between the fixing portion170and the side wall portion163inFIG.1, this is only an example, and if rotation of the chuck160is allowed, the position of the bearing172may be freely changed. In some embodiments, the chuck160may be rotatable by a first rotor unit165and a second rotor unit175. The first rotor unit165may be fixed on/to the chuck160. The second rotor unit175may rotate the first rotor unit165in a magnetic levitation method. For example, the first rotor unit165and the second rotor unit175may each include a magnetic material, and may generate a rotational force, using a magnetic force. As the first rotor unit165rotates, the chuck160and the wafer W may rotate together. Although the first rotor unit165is shown as only being fixed on the side wall portion163of the chuck160inFIG.1, this is only an example. As long as the first rotor unit165is configured to rotate the chuck160, the position of the first rotor unit165may be freely changed. As an example, as shown inFIG.3, the first rotor unit165may include a first magnetic pole region165aand a second magnetic pole region165b, and the second rotor unit175may include a third magnetic pole region175aand a fourth magnetic pole region175b. The first magnetic pole region165aand the second magnetic pole region165bmay be alternately disposed in the first rotor unit165, and the third magnetic pole region175aand the fourth magnetic pole region175bmay be alternately disposed in the second rotor unit175. The first magnetic pole region165aand the second magnetic pole region165bmay have magnetic poles different from each other, and the third magnetic pole region175aand the fourth magnetic pole region175bmay have magnetic poles different from each other. Also, the first magnetic pole region165aand the third magnetic pole region175amay have the same magnetic pole, and the second magnetic pole region165band the fourth magnetic pole region175bhave the same magnetic pole. As an example, the first magnetic pole region165aand the third magnetic pole region175amay be an N-pole, and the second magnetic pole region165band the fourth magnetic pole region175bmay be an S-pole. Each of the first to fourth magnetic pole regions165a,165b,175a, and175bmay be implemented as, but is not limited to, an electromagnet. As the first to fourth magnetic pole regions165a,165b,175a, and175bare alternately disposed, the first rotor unit165may rotate in the first rotation direction a1or the second rotation direction a2. For example, as the first to fourth magnetic pole regions165a,165b,175a, and175bare alternately disposed, there may be a repulsive force between the first magnetic pole region165aand the third magnetic pole region175a, and there may be an attractive force between the first magnetic pole region165aand the fourth magnetic pole region175b. Similarly, there may be an attractive force between the second magnetic pole region165band the third magnetic pole region175a, and there may be a repulsive force between the second magnetic pole region165band the fourth magnetic pole region175b. Accordingly, the first rotor unit165may rotate in a direction in which the first magnetic pole region165aand the third magnetic pole region175aface each other (or a direction in which the second magnetic pole region165band the fourth magnetic pole region175bface each other). Subsequently, the magnetic pole of the first rotor unit165(or the magnetic pole of the second rotor unit175) may be reversed. Accordingly, the rotation of the first rotor unit165may be accelerated and the first rotor unit165may continuously rotate. The chuck160may rotate the wafer W at a predetermined rotation speed. As an example, the rotation speed of the chuck160may range from about 100 rpm to about 300 rpm. If the rotation speed of the chuck160is not enough high, a chemical210provided to the wafer W may not be applied evenly. If the rotation speed of the chuck160is excessively high, the edge region We of the wafer W may be relatively cooled, and the temperature control may not be easy. The housing100may be disposed under the wafer W, e.g., while the wafer W is processed in the wafer cleaning apparatus. For example, the upper surface of the housing100may face the lower surface of the wafer W. The housing100may fix and support a laser module110, an optical system120, a reflector130, a calibration window140, and a transparent window150, which will be described below. For example, the laser module110, the optical system120, the reflector130, the calibration window140, and the transparent window150may be fixed on and supported by the housing100. In some embodiments, the housing100may be spaced apart from the chuck160and the wafer W. Accordingly, the housing100may not rotate, even while the chuck160and the wafer W rotate together. However, this is merely an example, and the housing100may rotate with or separately from the chuck160. The laser module110may irradiate a lower surface of the wafer W with a laser L. For example, the laser module110may be disposed inside the housing100. The laser L irradiated/emitted from the laser module110may penetrate the calibration window140and the transparent window150to be described later, and may reach the wafer W. The laser L that reaches the wafer W may be used to heat the wafer W. In some embodiments, the laser module110may be provided with the laser L from a laser supply unit111. The laser supply unit111may be connected to the outside of the wafer cleaning apparatus according to some embodiments to form a path through which the laser L is supplied. The laser supply unit111may include, but is not limited to, for example, optical fibers. A wavelength of the laser L provided from the laser supply unit111may be, for example, from about 100 nm to about 2000 nm. Preferably, the wavelength of the laser L provided from the laser supply unit111may be from about 400 nm to about 1,600 nm. The laser L provided from the laser supply unit111may have a single wavelength or may have multiple wavelengths. The laser L provided from the laser supply unit111may be a continuous wave (CW) type or a pulse type. A continuous wave type laser may be a laser that is continuously irradiated/emitted without being turned on/off. A pulse-type laser may be a laser that is periodically turned on/off and irradiated/emitted discontinuously. The frequency of the pulse-type laser may be, for example, about 10 MHz to about 1,000 MHz. The laser L irradiated/emitted from the laser module110may penetrate the optical system120. The optical system120may process the profile of the laser supplied from the laser module110and transfer it to the wafer W. For example, the optical system120may modify wavelength configurations and/or distributional configurations of the laser supplied form the laser module110before transferring it to the wafer W. For example, the optical system120may determine intensities of respective directions/angles to which the laser transfers. The laser L processed by the optical system120may heat the wafer W, e.g., the whole area of the wafer W. In some embodiments, the optical system120may include an aspheric lens array. As an example, as shown inFIG.4, the optical system120may include first to third aspherical lenses122,124, and126. Although the optical system120is only shown as including three aspheric lenses122,124, and126inFIG.4, this is merely an example, and the number of aspheric lenses may be variously changed. For example, the optical system120may include more than three aspheric lenses or less than three aspheric lenses. In certain embodiments, a spherical lens may be interposed between the aspherical lenses122,124, and126. The first to third aspherical lenses122,124, and126may process the profile of the laser L through refraction of the laser L. For example, the first to third aspherical lenses122,124, and126may provide a flat-top type laser L (e.g., a top-hot beam of laser) to the wafer W. Gaps between the first and third aspheric lenses122,124, and126may be adjusted to provide the required/proper profile of the laser L. For example, a first gap g1between the first aspherical lens122and the second aspherical lens124, a second gap g2between the second aspherical lens124and the third aspherical lens126or a third gap g3between the third aspheric lens126and the wafer W may be adjusted. The first to third gaps g1, g2, and g3may be determined and fixed at the time of fabricating/manufacturing the wafer cleaning apparatus according to some embodiments, and may also be adjustable depending on the size and type of the wafer W. The reflector130may be disposed inside the housing100. For example, the reflector130may be disposed around the laser module110and/or the optical system120. The reflector130may re-reflect the laser L that is irradiated/emitted from the laser module110and is reflected from the lower surface of the wafer W. Further, the reflector130may also block the laser L from reaching other components (e.g., the side wall portion163of the chuck160). As an example, the reflector130may have a hemispherical shape whose inner surface faces the lower surface of the wafer W. Therefore, the reflector130may improve the efficiency of treatment of the wafer W by the laser L. The hemispherical reflector130may define a hollow region100H. The laser L irradiated/emitted from the laser module110may progress through the hollow region100H to reach the wafer W. The transparent window150may be disposed on the lower surface of the wafer W, e.g., while the wafer W is processed in the wafer cleaning apparatus. For example, the transparent window150may be disposed on the top of the housing100. The laser L irradiated/emitted from the laser module110may penetrate the transparent window150. For example, the transparent window150may be formed of a transparent material through which the laser L may penetrate. For example, the transparent window150may include or be formed of, but is not limited to, quartz. The transparent window150may be disposed adjacent to the wafer W, e.g., while the wafer W is processed in the wafer cleaning apparatus. As a result, the outflow of the laser L penetrating the transparent window150to a region other than the wafer W may be minimized. In some embodiments, the transparent window150may not be in contact with the wafer W. Accordingly, the transparent window150may not rotate, even while the chuck160and the wafer W rotate together. The size of the transparent window150may correspond to the size of the wafer W to heat the whole area of the lower surface of the wafer W. For example, the width/diameter of the transparent window150may be the same as the width/diameter of the wafer W. For example, the transparent window150may be formed/configured to expose the edge region We, as well as the center region Wc, of the wafer W to the laser L. The calibration window140may be disposed inside the housing100. The calibration window140may be interposed between the laser module110and the wafer W, e.g., while the wafer W is processed in the wafer cleaning apparatus. As an example, the calibration window140may be interposed between the reflector130and the transparent window150. The calibration window140may adjust the transmissivity of the laser L irradiated/emitted from the laser module110for each region. For example, as shown inFIGS.5and6, the calibration window140may include a first region I and a second region II different from each other. As an example, the first region I may surround the second region II, e.g., in a plan view. At this time, a first light transmissivity of the first region I may be different from a second light transmissivity of the second region II. As an example, the first light transmissivity of the first region I may be smaller/less than the second light transmissivity of the second region II. As another example, the first light transmissivity of the first region I may be greater than the second light transmissivity of the second region II. Here, the light transmissivity may be a ratio of the laser L passing through the calibration window140to the laser L incident on the calibration window140. For convenience of explanation, a case where the first light transmissivity is smaller than the second light transmissivity will be mainly described below. Therefore, the calibration window140may provide the calibrated laser L to the wafer W. For example, the calibration window140may transmit the calibrated laser L toward the wafer W. As an example, the first light transmissivity of the first region I may be smaller than the second light transmissivity of the second region II. In such a case, an amount of light of the laser L that penetrates the first region I and reaches the edge region We of the wafer W may be smaller than an amount of light of the laser L that penetrates the second region II and reaches the central region We of the wafer W. In some embodiments, the annular (or donut-like) first region I may have a shape that shares a center with the circular second region II. However, the shapes, sizes, numbers, and the like of the first region I and the second region II are merely examples, and are not limited thereto. In some embodiments, an annular (or donut-like) first coating layer144may surround a circular second coating layer146. As an example, as shown inFIG.6, a diameter DM2of the second coating layer146may be from about 200 mm to about 350 mm, a diameter DM1of the first coating layer144may be greater than the diameter DM2of the second coating layer146. Preferably, the diameter DM2of the second coating layer146may be from about 250 mm to about 330 mm, and the diameter DM1of the first coating layer144may be about 400 mm or less. In some embodiments, the calibration window140may include a lens barrel148and a window structure141. The lens barrel148may fix and support the window structure141. For example, the window structure141may be fixed on and supported by the lens barrel148. For example, the lens barrel148may surround the side surfaces of the window structure141. The lens barrel148may have, but is not limited to, for example, a cylindrical shape. The lens barrel148may include or be formed of, but is not limited to, for example, at least one of aluminum (Al) and steel use stainless (SUS). The window structure141may be disposed inside the lens barrel148. As an example, the window structure141may be, but is not limited to, a disk type. A thickness TH11of the window structure141may be appropriately selected as needed. For example, the thickness TH11of the window structure141may be, but is not limited to, from about 1 mm to about 100 mm. Preferably, the thickness TH11of the window structure141may be from about 5 mm to about 50 mm. The size of the window structure141may correspond to the size of the wafer W to heat the whole area of the lower surface of the wafer W. For example, the window structure141may be formed to expose to the edge region We of the wafer W by the laser L. As an example, when a 300 mm wafer W is used, the diameter of the window structure141(e.g., DM1ofFIG.5) may be from about 250 mm to about 400 mm. In some embodiments, the window structure141may include a light projection window142, a first coating layer144, and a second coating layer146. The light projection window142may include a lower surface142S1and an upper surface142S2that are opposite to each other. In some embodiments, the lower surface142S1of the light projection window142may be disposed to face the laser module110, and the upper surface142S2of the light projection window142may be disposed to face the wafer W, e.g., while the wafer W is processed in the wafer cleaning apparatus. The light projection window142may include or be formed of, but is not limited to, for example, at least one of a borosilicate glass (e.g., BK7) and a fused silica glass. The first coating layer144and the second coating layer146may cover the light projection window142. The first coating layer144may cover the light projection window142of the first region I, and the second coating layer146may cover the light projection window142of the second region II. In some embodiments, the first coating layer144and the second coating layer146may extend along the lower surface142S1of the light projection window142. As an example, the first coating layer144may extend along the lower surface142S1of the light projection window142of the first region I, and the second coating layer146may extend along the lower surface142S1of the light projection window142of the second region II. The first coating layer144and the second coating layer146may have light transmissivities different from each other. As an example, the first light transmissivity of the first coating layer144may be smaller than the second light transmissivity of the second coating layer146. As an example, the first light transmissivity may be from about 50% to about 95%, and the second light transmissivity may be from about 95% to about 99.9%. Preferably, the first light transmissivity may be from about 80% to about 95%, and the second light transmissivity may be from about 95% to about 99.9%. A thickness TH21of the first coating layer144and a thickness TH22of the second coating layer146may be appropriately selected to achieve the required light transmissivity. For example, each of the thickness TH21of the first coating layer144and the thickness TH22of the second coating layer146may be, but is not limited to, about 100 nm to about 10,000 nm. Preferably, each of the thickness TH21of the first coating layer144and the thickness TH22of the second coating layer146may be about 500 nm to about 5,000 nm. More preferably, each of the thickness TH21of the first coating layer144and the thickness TH22of the second coating layer146may be about 900 nm to about 1,000 nm. Although only a case where the thickness TH21of the first coating layer144and the thickness TH22of the second coating layer146are the same is shown inFIG.5, this is merely an example. Unlike the shown case inFIG.5, the thickness TH21of the first coating layer144may be greater or smaller than the thickness TH22of the second coating layer146. For example, the thicknesses TH21and TH22may be different from each other. The first coating layer144and the second coating layer146may each include or be formed of, for example, an oxide. As an example, the first coating layer144and the second coating layer146may include or be formed of, but are not limited to, at least one of a silicon oxide and a hafnium oxide. In some embodiments, the first coating layer144may include or be formed of a high-reflection coating (HR coating) material. The high-reflection coating material may provide high reflectivity and low transmissivity, using a constructive interference of Fresnel reflection. For example, as shown inFIG.7, the first coating layer144may include first and second sub-coating layers1441and1442that are alternately stacked on the light projection window142. A refractive index n1of the first sub-coating layer1441may be lower than a refractive index n2of the second sub-coating layer1442. As an example, the first sub-coating layer1441may include or be formed of silicon oxide, and the second sub-coating layer1442may include or be formed of hafnium oxide. Therefore, an example, a first reflected light RW11generated on or reflected from the surface of the second sub-coating layer1442may achieve the constructive interference with a second reflected light RW12generated on or reflected from the surface of the first sub-coating layer1441. The thickness of each of the first and second sub-coating layers1441and1442may be appropriately selected depending on the wavelength λ of the laser L to induce the constructive interference. As an example, the thickness of the second sub-coating layer1442may be ¼λ. In some embodiments, the second coating layer146may include an anti-reflection coating (AR coating) material. The anti-reflection coating material may provide low reflectivity and high transmissivity, using the destructive interference of Fresnel reflection. For example, as shown inFIG.8, the second coating layer146may include third to sixth sub-coating layers1461to1464that are sequentially stacked on the light projection window142. The refractive indexes n21to n24of the third to sixth sub-coating layers1461to1464may decrease in a direction receding from the light projection window142. As an example, the fifth sub-coating layer1463may include or be formed of hafnium oxide, and the sixth sub-coating layer1464may include or be formed of silicon oxide. Therefore, as an example, a third reflected light RW21generated on or reflected from the surface of the sixth sub-coating layer1464may achieve the destructive interference with a fourth reflected light RW22generated on or reflected from the surface of the fifth sub-coating layer1463. The thickness of each of the third to sixth sub-coating layers1461to1464may be appropriately selected depending on the wavelength λ of the laser L to induce the destructive interference. As an example, the thickness of the sixth sub-coating layer1464may be ¼λ. In some embodiments, both the first coating layer144and the second coating layer146may include the anti-reflection coating material. As an example, the first coating layer144may include an anti-reflection coating material having a first light transmissivity, and the second coating layer146may include an anti-reflection coating material having a second light transmissivity greater than the first light transmissivity. AlthoughFIGS.5to8show that the first coating layer144and the second coating layer146are formed on the lower surface142S1of the light projection window142, this is merely an example. Unlike the shown cases in the figures, the first coating layer144and the second coating layer146may be formed on the upper surface142S2of the light projection window142, and may be formed on both the lower surface142S1and the upper surface142S2of the light projection window142. AlthoughFIG.1shows that the calibration window140is in contact with the reflector130and the transparent window150, this is merely an example. Unlike the shown case inFIG.1, the calibration window140may be spaced apart from the reflector130or from the transparent window150in certain embodiments. In some embodiments, the calibration window140may cover the reflector130. For example, the calibration window140may vertically overlap the whole area of the reflector130. In such cases, the hollow region100H may be isolated from the outside by the reflector130and the calibration window140. The reflector130and the calibration window140may prevent the hollow region100H where the laser L progresses from being contaminated by a fume generated from the chemical210to be described below. In some embodiments, the hollow region100H may be provided and/or maintained with vacuum state. The hollow region100H provided with vacuum state may be beneficial for and/or facilitate the progress of the laser L. The chemical supply unit200may be disposed over the chuck160. The chemical supply unit200may supply the chemical210to the upper surface of the wafer W. The chemical210may include various substances for cleaning the wafer W. For example, the chemical210may include, but is not limited to, at least one of phosphoric acid, aqueous ammonia and TMAH (Tetramethylammonium hydroxide). In some embodiments, the chemical210may perform a developing process on the wafer W. For example, the chemical210supplied to the wafer W may remove a portion of photoresist layer disposed on either the exposed portion Wb or the non-exposed portion Wa. As an example, by the exposure process of the wafer W, the solubility of the exposed portion Wb in the chemical210may be increased compared to the solubility of the non-exposed portion Wa in the chemical210. In such a case, the chemical210supplied to the wafer W may remove the exposed portion Wb, and the non-exposed portion Wa may remain to form a photoresist pattern. For example, a positive tone development (PTD) process may be performed. As another example, the exposed portion Wb may be cured by the exposure process of the wafer W. In such a case, the chemical210supplied to the wafer W may remove the unexposed portion Wa, and the cured exposed portion Wb may remain to form a photoresist pattern. For example, a negative tone development (NTD) process may be performed. The chemical supply unit200may be, but is not limited to, for example, a nozzle. Although the chemical210is only shown as being supplied to the center of the wafer W inFIG.1, this is merely an example, and the chemical210may be supplied from the edge of the wafer W in certain embodiments. The chemical supply unit200may provide the chemical210at a predetermined flow rate. As an example, the chemical supply unit200may provide the chemical210at a flow rate of about 0.1 L/min to about 1 L/min. When the flow rate of the chemical210is not sufficiently large/great, the cleaning speed may be slow, and when the flow rate of the chemical210is excessively large/great, heating of the wafer W by the laser L may be slow or may be insufficient. As the wafer W rotates along with the chuck160, the chemical210provided from the chemical supply unit200may spread along the upper surface of the wafer W. Accordingly, the chemical210may clean the entire upper surface of the wafer W. In some embodiments, a first flow F may be applied in the direction toward the upper surface of the wafer W for fixation of the wafer W and uniform spreading of the chemical210. For example, the first flow F may be a gas flow, and the gas flow may be controlled by a pressure difference (e.g., vacuum level difference) of the gas. The first flow F allows the chemical210to move from the central region We of the wafer W to the edge region We of the wafer W. The first flow F may include or be formed of, but is not limited to, an inert gas such as nitrogen (N2) gas. The bowl180may be disposed outside the chuck160to surround the chuck160, e.g., in a plan view. Also, the bowl180may be disposed to be higher than the chuck160and the wafer W. The bowl180may block the outflow of the chemical210and/or the vaporized fume of the chemical210to the outside. The drain guide portion190may guide a drain path of the chemical210and/or the fume. As an example, the chemical210moved to the edge region We of the wafer W by the first flow F and/or centrifugal force generated by the rotation of the wafer W may reach the drain guide portion190via the side wall portion163of the chuck160. The chemical210that has reached the drain guide portion190may be discharged to the outside as a drain chemical210d. In some embodiments, the drain guide portion190may be disposed to be lower than the bowl180. Also, in some embodiments, the drain guide portion190may be spaced apart from the wafer W farther than the chuck160and the housing100, e.g., in a plan view. This configuration may be beneficial to prevent other components (e.g., the chuck160) from being damaged by the drain chemical210d. In some embodiments, a second flow C1and a third flow C2may be applied toward the drain guide portion190. The second flow C1and the third flow C2may be gas flows. As an example, as shown inFIG.1, the second flow C1may be provided between the side wall portion163and the drain guide portion190of the chuck160, and the third flow C2may be provided between the bowl180and the drain guide portion190. The second flow C1and the third flow C2may prevent the chemical210and/or the fume from flowing backward (e.g., toward the wafer W), and may cool the wafer cleaning apparatus according to some embodiments. Each of the second flow C1and the third flow C2may include, but are not limited to, a refrigerant such as nitrogen (N2) gas. In some embodiments, the second flow C1may be directed toward the drain guide portion190via a space between the first rotor unit165and the second rotor unit175. Such a second flow C1may prevent the first rotor unit165and the second rotor unit175including a magnetic material from being excessively heated, by cooling the first rotor unit165and the second rotor unit175. Hereinafter, the effects of the wafer cleaning apparatus according to the exemplary embodiment will be described referring toFIGS.1to9. FIG.9is an exemplary graph showing intensity and temperature of the laser depending on the position of the wafer. For reference, a horizontal axis (x-axis) ofFIG.9indicates a distance from the center of the wafer W, and a vertical axis (y-axis) ofFIG.9indicates intensity (or an amount of light) of the laser L reaching the wafer W and the temperature of the wafer W. Referring toFIG.9, the intensity (or an amount of light) of the laser L reaching the wafer W and the temperature of the wafer W may not be uniform on the entire surface of the wafer W. As an example, the intensity of the laser L and the temperature of the wafer W in the edge region We (e.g., 100 mm to 150 mm) of the wafer W may be higher than the intensity of the laser L and the temperature of the wafer W in the central region We (e.g., —100 mm to 100 mm) of the wafer W. This may be caused by various causes such as the characteristics of the laser L, a significant difference in reflectivity generated on the lower surface of the wafer W, an influence of airflow generated in the outside of the wafer W, and a significant difference in an oil film thickness formed on the upper surface of the wafer W. However, the wafer cleaning apparatus according to some embodiments may minimize the intensity variation of the laser L and the temperature variation of the wafer W, by including the calibration window140. As an example, as described above, the first light transmissivity of the first region I of the calibration window140may be smaller/less than the second light transmissivity of the second region II of the calibration window140. For example, the amount of light of the laser L that penetrates the first region I and reaches the edge region We of the wafer W may be smaller/less than the amount of light of the laser L that penetrates the second region II and reaches the central region We of the wafer W. Accordingly, the temperature variation on the entire surface of the wafer can be improved to provide the wafer cleaning apparatus with improved performance. Hereinafter, a wafer cleaning apparatus according to the exemplary embodiment will be described referring toFIGS.10to18. FIGS.10to12are various plan views for explaining the calibration window of the wafer cleaning apparatus according to some embodiments. For convenience of explanation, repeated parts of contents explained above usingFIGS.1to9will be briefly described or omitted. For example, above descriptions with respect to various components, elements, parts and features may also be applied to corresponding components, elements, parts and features of embodiments illustrated inFIGS.10to12. Referring toFIGS.10to12, in the wafer cleaning apparatus according to some embodiments, the first region I and the second region II are variously formed as needed. For example, as explained above usingFIGS.1to8, the first coating layer144that provides the first region I, and the second coating layer146that provides the second region II may be formed in various ways as needed. Accordingly, the wafer cleaning equipment according to some embodiments may provide various customized calibration windows140, depending on various intensity profiles of the laser L and various temperature profiles of the wafer W. As an example, as shown inFIG.10, the light transmissivity of the calibration window140may gradually change. For example, the light transmissivity of the first region I may gradually decrease in a direction receding from the second region II. Alternatively, for example, the light transmissivity of the first region I may gradually increase in a direction receding from the second region II. Although only a case where the light transmissivity of the first region I gradually changes is explained, this is merely an example. For example, the light transmissivity of the second region II may gradually change, and both the light transmissivity of the first region I and the light transmissivity of the second region II may gradually change. As another example, as shown inFIG.11, the first region I and/or the second region II of the calibration window140may be formed radially. For example, the first region I and the second region II are formed radially and may be disposed alternately. For example, the first region I and the second region II may have a fan shape, and a plurality of fanwise first regions I and a plurality of fanwise second regions II may be alternately arranged in an azimuthal direction as shown inFIG.11. Although the calibration window140is only shown as including four first regions I and four second regions II inFIG.11, this is merely an example, and the number of first regions I and the number of second regions II may be various. For example, the calibration window140may have more than four first regions I and more than four second regions II. In certain embodiments, the calibration window140may have less than four first regions I and less than four second regions II. Also, unlike the shown case inFIG.11, at least a part of the plurality of first regions I and/or at least a part of the plurality of second regions II may be continuously disposed. As still another example, as shown inFIG.12, the calibration window140may include a plurality of second regions II that are spaced apart from each other. The shape and size of each second region II and the number of the second region II are merely examples, and are not limited thereto. For example, at least a part of the second region II may have a form other than a circular shape, e.g., an oval, an ellipse, a rectangle, a triangle, etc. In some embodiments, the calibration window140may also be rotatively disposed on the reflector130. Therefore, the calibration window140may provide various forms for each region. FIG.13is a cross-sectional view for explaining a calibration window of the wafer cleaning apparatus according to some embodiments.FIG.14is a plan view for explaining a calibration window of the wafer cleaning apparatus according to some embodiments. For convenience of explanation, repeated parts of contents explained above usingFIGS.1to12will be briefly explained or omitted. Referring toFIGS.13and14, in the wafer cleaning apparatus according to some embodiments, the calibration window140may include a plurality of window structures141a,141b, and141c. As an example, the calibration window140may include first to third window structures141a,141b, and141cthat are stacked sequentially. The laser irradiated/emitted from the laser module may sequentially penetrate the first to third window structures141a,141b, and141c. Although the calibration window140is only shown as including the three window structures141a,141b, and141cinFIG.13, this is merely an example, and the number of window structures may vary. In some embodiments, the number of stacked window structures141a,141b, and141cmay be about 50 or less. Preferably, the number of stacked window structures141a,141b, and141cmay be about 30 or less. Although the thicknesses of the first to third window structures141a,141b, and141care only shown as being the same as each other inFIG.13, this is merely an example, and if necessary, the thicknesses of each of the first to third window structures141a,141b, and141cmay differ from each other. The first to third window structures141a,141b, and141cmay respectively include light projection windows142a,142b, and142c, first coating layers144a,144b, and144cand second coating layers146a,146b, and146c. In some embodiments, the first coating layers144a,144b, and144cof the respective first to third window structures141a,141b, and141cmay have areas different from each other. For example, as shown inFIG.14, the calibration window140may include first to fourth regions I to IV different from each other. As an example, a first region I may surround a second region II, the second region II may surround a third region III, and the third region III may surround a fourth region IV. At this time, for example, the first coating layer144aof the first window structure141amay cover (e.g., vertically overlap) a light projection window142aof the first region I, the first coating layer144bof the second window structure141bmay cover (e.g., vertically overlap) a light projection window142bof the first and second regions I and II, and the first coating layer144cof the third window structure141cmay cover (e.g., vertically overlap) a light projection window142cof the first to third regions I to III. In such a case, the first to fourth regions I to IV may have light transmissivities different from each other. As an example, the first light transmissivity of the first region I may be smaller/less than the second light transmissivity of the second region II, the second light transmissivity of the second region II may be smaller/less than the third light transmissivity of the third region III, and the third light transmissivity of the third region III may be smaller/less than the fourth light transmissivity of the fourth region IV. In some embodiments, the annular (or donut-like) first to third regions I to III may have a shape that shares a center with the circular fourth region IV. However, the shapes, sizes, and the like of the first to fourth regions I to IV, and the number of regions are merely examples, and are not limited thereto. In some embodiments, as the number of regions of the calibration window140(e.g., first to fourth regions I to IV) increases, the temperature variation on the entire surface of the wafer may be improved more finely. FIG.15is a cross-sectional view for explaining the calibration window of the wafer cleaning apparatus according to some embodiments. For convenience of explanation, repeated parts of contents explained above usingFIGS.1to14will be briefly explained or omitted. Referring toFIG.15, in the wafer cleaning apparatus according to some embodiments, at least some of the plurality of window structures141a,141b, and141dinclude a plurality of first coating layers144a,144band144d. As an example, the plurality of window structures141a,141b, and141dmay include a fourth window structure141d. Each of the window structures141a,141b, and141dmay include light projection windows142a,142band142d, first coating layers144a,144band144d, and second coating layers146a,146band146d. At this time, the fourth window structure141dmay include a plurality of first coating layers144d. Although the fourth window structure141dis only shown as including two first coating layers144dinFIG.15, this is merely an example, and the number of aspheric lenses may vary. Further, if necessary, the first window structure141amay include a plurality of first coating layers144aor the second window structure141bmay include a plurality of first coating layers144b. FIGS.16to18are various cross-sectional views for explaining a wafer cleaning apparatus according to some embodiments. For convenience of explanation, repeated parts of contents explained above usingFIGS.1to15will be briefly explained or omitted. Referring toFIG.16, the wafer cleaning apparatus according to some embodiments does not include a transparent window150. For example, the calibration window140may be disposed adjacent to the wafer W. Accordingly, it is possible to minimize the outflow of the laser L passing through the calibration window140to a region other than the wafer W. For example, the calibration window140ofFIG.16may replace a combined structure of the transparent window150and the calibration window140ofFIG.1. In some embodiments, the calibration window140may not be in contact with the wafer W. Accordingly, the calibration window140may not rotate, even while the chuck160and the wafer W rotate together. Referring toFIG.17, in the wafer cleaning apparatus according to some embodiments, the transparent window150is interposed between the reflector130and the calibration window140. Although the calibration window140is only shown as being in contact with the transparent window150inFIG.17, this is merely an example. Unlike the shown case inFIG.17, the calibration window140may be spaced apart from the transparent window150. In some embodiments, the transparent window150may cover the reflector130. For example, the transparent window150may vertically overlap the whole area of the reflector130. In such a case, the hollow region100H may be isolated from the outside by the reflector130and the transparent window150. The reflector130and the transparent window150may prevent the hollow region100H in which the laser L progresses from being contaminated by the fume generated from the chemical210. In some embodiments, the hollow region100H may be provided in vacuum. The hollow region100H provided in vacuum may facilitate the progress of the laser L. For example, the transparent window150and the reflector130may be airtightly attached. Referring toFIG.18, in the wafer cleaning apparatus according to some embodiments, at least a part of the calibration window140is disposed in the reflector130. For example, the calibration window140may be disposed inside the hollow region100H. In some embodiments, the transparent window150may cover the reflector130. For example, the transparent window150may vertically overlap the whole area of the reflector130. In such a case, the hollow region100H in which the calibration window140is disposed may be isolated from the outside by the reflector130and the transparent window150. Although the calibration window140is only shown as being in contact with the transparent window150inFIG.18, this is merely an example. Unlike the shown case inFIG.18, the calibration window140may be spaced apart from the transparent window150. Hereinafter, a method for cleaning a wafer according to exemplary embodiments will be described referring toFIGS.1to19. FIG.19is a flowchart for explaining the method for cleaning the wafer using the wafer cleaning apparatus according to some embodiments. For convenience of explanation, repeated parts of contents explained above usingFIGS.1to18will be briefly described or omitted. Referring toFIG.19, the method for cleaning the wafer using the wafer cleaning apparatus according to some embodiments may include measurement (S10) of a temperature gradient of the wafer W, provision (S20) of the calibration window140using the measured temperature gradient, and cleaning (S30) of the wafer W using the calibration window140. The measurement (S10) of temperature gradient of the wafer W may be performed by measuring the temperature of the lower surface of the wafer W heated by the laser L in the wafer cleaning apparatus according to some embodiments. The measurement of the temperature of the lower surface of the wafer W may include, but is not limited to, for example, usage of a pyrometer and/or a charged-coupled device (CCD) camera. Accordingly, as an example, a graph as shown inFIG.9may be provided. The provision (S20) of the calibration window140may be performed by adjusting the transmissivity of the calibration window140to the laser L for each region based on the measured temperature gradient. As an example, when a graph as shown inFIG.9is provided, the calibration window140including the first region I having the first light transmissivity and the second region II having the second light transmissivity greater than the first light transmissivity may be provided. The cleaning (S30) of the wafer W may be performed by utilizing the wafer cleaning apparatus described above referring toFIGS.1to18. This will be described more specifically below in the description ofFIG.20. Accordingly, a method for cleaning a wafer with improved performance may be provided. Hereinafter, the method for fabricating the semiconductor device according to an exemplary embodiment will be described referring toFIGS.1to20. FIG.20is a flowchart for explaining a method for fabricating a semiconductor device using the wafer cleaning apparatus according to some embodiments. For convenience of explanation, repeated parts of contents explained above usingFIGS.1to19will be briefly explained or omitted. Referring toFIG.20, the method for fabricating the semiconductor device using the wafer cleaning apparatus according to some embodiments includes disposition (S40) of the wafer W on the chuck160, heating (S42) of the wafer W by irradiating/emitting the laser L, and supplying (S44) of the chemical210to the wafer W. The disposition (S40) of the wafer W on the chuck160may be performed by fixing the wafer W to the grip portion161of the chuck160. As the chuck160rotates, the wafer W fixed on/to the chuck160may also rotate. In some embodiments, the wafer W may be a wafer subjected to the exposure process. For example, the wafer W may include an exposed portion Wb and a non-exposed portion Wa. The wafer W may include, but is not limited to, a photoresist film. The heating (S42) of the wafer W may be performed by irradiating the lower surface of the wafer W with the laser L. The irradiation/radiation of the laser L to the lower surface of the wafer W may be performed using the laser module110. As described above usingFIGS.1to8, the laser L irradiated/emitted from the laser module110may penetrate the optical system120and the calibration window140, and reach the lower surface of the wafer W. The supplying (S44) of the chemical210to the wafer W may be performed, using the chemical supply unit200. The chemical210supplied from the chemical supply unit200may be provided to the upper surface of the wafer W. As a result, the wafer W may be cleaned. In some embodiments, the cleaning of the wafer W may be performed by a puddle method that utilizes the surface tension of the chemical210. In some embodiments, the chemical210supplied to the wafer W may remove either the exposed portion Wb or the unexposed portion Wa. As an example, the chemical210supplied to the wafer W may remove the exposed portion Wb, and the non-exposed portion Wa may remain to form a photoresist pattern. As another example, the chemical210supplied to the wafer W may remove the non-exposed portion Wa, and the exposed portion Wb may remain to form a photoresist pattern. Accordingly, a developing process of the wafer W may be performed to fabricate a semiconductor device including a predetermined pattern. While the present inventive concept has been particularly shown and described with reference to exemplary embodiments thereof, it will be understood by those of ordinary skill in the art that various changes in form and details may be made therein without departing from the spirit and scope of the present inventive concept as defined by the following claims. It is therefore desired that the present embodiments be considered in all respects as illustrative and not restrictive, reference being made to the appended claims rather than the foregoing description to indicate the scope of the invention. | 50,712 |
11862458 | Several of the figures are included as schematics. It is to be understood that the figures are for illustrative purposes, and are not to be considered of scale unless specifically stated to be of scale. Additionally, as schematics, the figures are provided to aid comprehension and may not include all aspects or information compared to realistic representations, and may include exaggerated material for illustrative purposes. In the appended figures, similar components and/or features may have the same reference label. Further, various components of the same type may be distinguished by following the reference label by a letter that distinguishes among the similar components. If only the first reference label is used in the specification, the description is applicable to any one of the similar components having the same first reference label irrespective of the letter. DETAILED DESCRIPTION Amorphous silicon may be used in semiconductor device manufacturing for a number of structures and processes, including as a sacrificial material, for example as a dummy gate material, or as a trench fill material. In gap filling operations, some processing may utilize flowable films formed under process conditions to limit conformality of deposition, which may allow the deposited material to better fill features on the substrate. Flowable silicon material may be characterized by relatively high amounts of hydrogen, and may be less dense than other formed films. Consequently, subsequent treatment operations may be performed to cure the produced films. Conventional technology may utilize a UV curing process to remove hydrogen and process the film. However, UV curing may result in significant film shrinkage, which may cause stress on features as well as produce voids within the structure. As feature sizes continue to shrink, flowable films may be challenged for narrow features, which may be further characterized by higher aspect ratios. For example, pinching of the feature may more readily occur due to deposition on sidewalls of the feature, which in small feature sizes may further restrict flow further into the feature, and may produce voids. Additionally, for processes in which conversion of the amorphous silicon may be performed, expansion of the sidewall materials during conversion may further restrict access within the feature. The present technology may overcome these limitations by performing a directional treatment of material formed in the feature that may not be performed on material deposited on the sidewalls. Additionally, the present technology may perform a selective etch and/or modification of the formed film during a curing operation that is capable of removing the lower quality material on the sidewalls, while maintaining denser material within the feature. This may limit or prevent sidewall coverage during trench fill, allowing improved fill operations to be performed. Additionally, conversion operations may be performed subsequent curing, which may further reduce flow restriction within the feature. After describing general aspects of a chamber according to some embodiments of the present technology in which plasma processing operations discussed below may be performed, specific methodology may be discussed. It is to be understood that the present technology is not intended to be limited to the specific films, chambers, or processing discussed, as the techniques described may be used to improve a number of film formation processes, and may be applicable to a variety of processing chambers and operations. FIG.1shows a cross-sectional view of an exemplary processing chamber100according to some embodiments of the present technology. The figure may illustrate an overview of a system incorporating one or more aspects of the present technology, and/or which may perform one or more deposition or other processing operations according to embodiments of the present technology. Additional details of chamber100or methods performed may be described further below. Chamber100may be utilized to form film layers according to some embodiments of the present technology, although it is to be understood that the methods may similarly be performed in any chamber within which film formation may occur. The processing chamber100may include a chamber body102, a substrate support104disposed inside the chamber body102, and a lid assembly106coupled with the chamber body102and enclosing the substrate support104in a processing volume120. A substrate103may be provided to the processing volume120through an opening126, which may be conventionally sealed for processing using a slit valve or door. The substrate103may be seated on a surface105of the substrate support during processing. The substrate support104may be rotatable, as indicated by the arrow145, along an axis147, where a shaft144of the substrate support104may be located. Alternatively, the substrate support104may be lifted up to rotate as necessary during a deposition process. A plasma profile modulator111may be disposed in the processing chamber100to control plasma distribution across the substrate103disposed on the substrate support104. The plasma profile modulator111may include a first electrode108that may be disposed adjacent to the chamber body102, and may separate the chamber body102from other components of the lid assembly106. The first electrode108may be part of the lid assembly106, or may be a separate sidewall electrode. The first electrode108may be an annular or ring-like member, and may be a ring electrode. The first electrode108may be a continuous loop around a circumference of the processing chamber100surrounding the processing volume120, or may be discontinuous at selected locations if desired. The first electrode108may also be a perforated electrode, such as a perforated ring or a mesh electrode, or may be a plate electrode, such as, for example, a secondary gas distributor. One or more isolators110a,110b, which may be a dielectric material such as a ceramic or metal oxide, for example aluminum oxide and/or aluminum nitride, may contact the first electrode108and separate the first electrode108electrically and thermally from a gas distributor112and from the chamber body102. The gas distributor112may define apertures118for distributing process precursors into the processing volume120. The gas distributor112may be coupled with a first source of electric power142, such as an RF generator, RF power source, DC power source, pulsed DC power source, pulsed RF power source, or any other power source that may be coupled with the processing chamber. In some embodiments, the first source of electric power142may be an RF power source. The gas distributor112may be a conductive gas distributor or a non-conductive gas distributor. The gas distributor112may also be formed of conductive and non-conductive components. For example, a body of the gas distributor112may be conductive while a face plate of the gas distributor112may be non-conductive. The gas distributor112may be powered, such as by the first source of electric power142as shown inFIG.1, or the gas distributor112may be coupled with ground in some embodiments. The first electrode108may be coupled with a first tuning circuit128that may control a ground pathway of the processing chamber100. The first tuning circuit128may include a first electronic sensor130and a first electronic controller134. The first electronic controller134may be or include a variable capacitor or other circuit elements. The first tuning circuit128may be or include one or more inductors132. The first tuning circuit128may be any circuit that enables variable or controllable impedance under the plasma conditions present in the processing volume120during processing. In some embodiments as illustrated, the first tuning circuit128may include a first circuit leg and a second circuit leg coupled in parallel between ground and the first electronic sensor130. The first circuit leg may include a first inductor132A. The second circuit leg may include a second inductor132B coupled in series with the first electronic controller134. The second inductor132B may be disposed between the first electronic controller134and a node connecting both the first and second circuit legs to the first electronic sensor130. The first electronic sensor130may be a voltage or current sensor and may be coupled with the first electronic controller134, which may afford a degree of closed-loop control of plasma conditions inside the processing volume120. A second electrode122may be coupled with the substrate support104. The second electrode122may be embedded within the substrate support104or coupled with a surface of the substrate support104. The second electrode122may be a plate, a perforated plate, a mesh, a wire screen, or any other distributed arrangement of conductive elements. The second electrode122may be a tuning electrode, and may be coupled with a second tuning circuit136by a conduit146, for example a cable having a selected resistance, such as 50 ohms, for example, disposed in the shaft144of the substrate support104. The second tuning circuit136may have a second electronic sensor138and a second electronic controller140, which may be a second variable capacitor. The second electronic sensor138may be a voltage or current sensor, and may be coupled with the second electronic controller140to provide further control over plasma conditions in the processing volume120. A third electrode124, which may be a bias electrode and/or an electrostatic chucking electrode, may be coupled with the substrate support104. The third electrode may be coupled with a second source of electric power150through a filter148, which may be an impedance matching circuit. The second source of electric power150may be DC power, pulsed DC power, RF bias power, a pulsed RF source or bias power, or a combination of these or other power sources. In some embodiments, the second source of electric power150may be an RF bias power. The lid assembly106and substrate support104ofFIG.1may be used with any processing chamber for plasma or thermal processing. In operation, the processing chamber100may afford real-time control of plasma conditions in the processing volume120. The substrate103may be disposed on the substrate support104, and process gases may be flowed through the lid assembly106using an inlet114according to any desired flow plan. Inlet114may include delivery from a remote plasma source unit116, which may be fluidly coupled with the chamber, as well as a bypass117for process gas delivery that may not flow through the remote plasma source unit116in some embodiments. Gases may exit the processing chamber100through an outlet152. Electric power may be coupled with the gas distributor112to establish a plasma in the processing volume120. The substrate may be subjected to an electrical bias using the third electrode124in some embodiments. Upon energizing a plasma in the processing volume120, a potential difference may be established between the plasma and the first electrode108. A potential difference may also be established between the plasma and the second electrode122. The electronic controllers134,140may then be used to adjust the flow properties of the ground paths represented by the two tuning circuits128and136. A set point may be delivered to the first tuning circuit128and the second tuning circuit136to provide independent control of deposition rate and of plasma density uniformity from center to edge. In embodiments where the electronic controllers may both be variable capacitors, the electronic sensors may adjust the variable capacitors to maximize deposition rate and minimize thickness non-uniformity independently. Each of the tuning circuits128,136may have a variable impedance that may be adjusted using the respective electronic controllers134,140. Where the electronic controllers134,140are variable capacitors, the capacitance range of each of the variable capacitors, and the inductances of the first inductor132A and the second inductor132B, may be chosen to provide an impedance range. This range may depend on the frequency and voltage characteristics of the plasma, which may have a minimum in the capacitance range of each variable capacitor. Hence, when the capacitance of the first electronic controller134is at a minimum or maximum, impedance of the first tuning circuit128may be high, resulting in a plasma shape that has a minimum aerial or lateral coverage over the substrate support. When the capacitance of the first electronic controller134approaches a value that minimizes the impedance of the first tuning circuit128, the aerial coverage of the plasma may grow to a maximum, effectively covering the entire working area of the substrate support104. As the capacitance of the first electronic controller134deviates from the minimum impedance setting, the plasma shape may shrink from the chamber walls and aerial coverage of the substrate support may decline. The second electronic controller140may have a similar effect, increasing and decreasing aerial coverage of the plasma over the substrate support as the capacitance of the second electronic controller140may be changed. The electronic sensors130,138may be used to tune the respective circuits128,136in a closed loop. A set point for current or voltage, depending on the type of sensor used, may be installed in each sensor, and the sensor may be provided with control software that determines an adjustment to each respective electronic controller134,140to minimize deviation from the set point. Consequently, a plasma shape may be selected and dynamically controlled during processing. It is to be understood that, while the foregoing discussion is based on electronic controllers134,140, which may be variable capacitors, any electronic component with adjustable characteristic may be used to provide tuning circuits128and136with adjustable impedance. Processing chamber100may be utilized in some embodiments of the present technology for processing methods that may include formation, treatment, etching, or conversion of materials for semiconductor structures. It is to be understood that the chamber described is not to be considered limiting, and any chamber that may be configured to perform operations as described may be similarly used.FIG.2shows exemplary operations in a processing method200according to some embodiments of the present technology. The method may be performed in a variety of processing chambers and on one or more mainframes or tools, including processing chamber100described above. Method200may include a number of optional operations, which may or may not be specifically associated with some embodiments of methods according to the present technology. For example, many of the operations are described in order to provide a broader scope of the structural formation, but are not critical to the technology, or may be performed by alternative methodology as would be readily appreciated. Method200may describe operations shown schematically inFIGS.3A-3C, the illustrations of which will be described in conjunction with the operations of method200. It is to be understood that the figures illustrate only partial schematic views, and a substrate may contain any number of additional materials and features having a variety of characteristics and aspects as illustrated in the figures. Method200may include additional operations prior to initiation of the listed operations. For example, additional processing operations may include forming structures on a semiconductor substrate, which may include both forming and removing material. For example, transistor structures, memory structures, or any other structures may be formed. Prior processing operations may be performed in the chamber in which method200may be performed, or processing may be performed in one or more other processing chambers prior to delivering the substrate into the semiconductor processing chamber or chambers in which method200may be performed. Regardless, method200may optionally include delivering a semiconductor substrate to a processing region of a semiconductor processing chamber, such as processing chamber100described above, or other chambers that may include components as described above. The substrate may be deposited on a substrate support, which may be a pedestal such as substrate support104, and which may reside in a processing region of the chamber, such as processing volume120described above. A substrate on which several operations have been performed may be substrate305of a structure300, which may show a partial view of a substrate on which semiconductor processing may be performed. It is to be understood that structure300may show only a few top layers during processing to illustrate aspects of the present technology. The substrate305may include a material in which one or more features310may be formed. Substrate305may be any number of materials used in semiconductor processing. The substrate material may be or include silicon, germanium, dielectric materials including silicon oxide or silicon nitride, metal materials, or any number of combinations of these materials, which may be the substrate305, or materials formed in structure300. Features310may be characterized by any shape or configuration according to the present technology. In some embodiments, the features may be or include a trench structure or aperture formed within the substrate305. Although the features310may be characterized by any shapes or sizes, in some embodiments the features310may be characterized by higher aspect ratios, or a ratio of a depth of the feature to a width across the feature. For example, in some embodiments features310may be characterized by aspect ratios greater than or about 5:1, and may be characterized by aspect ratios greater than or about 10:1, greater than or about 15:1, greater than or about 20:1, greater than or about 25:1, greater than or about 30:1, greater than or about 40:1, greater than or about 50:1, or greater. Additionally, the features may be characterized by narrow widths or diameters across the feature including between two sidewalls, such as a dimension less than or about 20 nm, and may be characterized by a width across the feature of less than or about 15 nm, less than or about 12 nm, less than or about 10 nm, less than or about 9 nm, less than or about 8 nm, less than or about 7 nm, less than or about 6 nm, less than or about 5 nm, or less. In some embodiments, method200may include optional treatment operations, such as a pretreatment, that may be performed to prepare a surface of substrate305for deposition. Once prepared, method200may include delivering one or more precursors to a processing region of the semiconductor processing chamber housing the structure300. The precursors may include one or more silicon-containing precursors, as well as one or more diluents or carrier gases such as an inert gas or other gas delivered with the silicon-containing precursor. A plasma may be formed of the deposition precursors including the silicon-containing precursor at operation205. The plasma may be formed within the processing region, which may allow deposition materials to deposit on the substrate. For example, in some embodiments a capacitively-coupled plasma may be formed within the processing region by applying plasma power to the faceplate as previously described. A silicon-containing material may be deposited on the substrate at operation210from plasma effluents of the silicon-containing precursor. The material may be a flowable silicon-containing material in some embodiments, which may be or include amorphous silicon. The deposited materials may at least partially flow into the features on the substrate to provide a bottom-up type of gap fill. As illustrated inFIG.3A, material315may be deposited on the substrate305, and may flow into trenches or features310. As illustrated, the deposited material315may flow into the bottom of the feature, although an amount of material may remain on the sidewalls of the substrate as illustrated with material317, as well as material on top of, or between, features, as illustrated with material319. Although the amount deposited may be relatively small, the remaining material on the sidewalls may limit subsequent flow. Additionally, if a conventional conversion were performed of the deposited material, such as a conversion to silicon nitride for example, the conversion would involve an expansion of the film. For reduced dimension features, the residual material formed on the sidewalls may be converted and expand outward towards an opposite sidewall. This may cause the feature to be pinched off, which may form voids within the feature. The power applied during deposition may be a lower power plasma, which may limit dissociation, and which may maintain an amount of hydrogen incorporation in the deposited materials. This incorporated hydrogen may contribute to the flowability of the materials deposited. Additionally, unlike conventional technologies, the present technology may incorporate a bias process, which may produce a treatment to the deposited film during the deposition operations. The process may include utilizing a source power, such as coupled with the faceplate or showerhead as previously described, as well as utilizing a bias power, such as applied through the substrate support as discussed above. The source power may be used to perform a controlled dissociation of the silicon-containing precursor, which may limit dissociation and allow longer material chains to be formed. When these materials contact the substrate, the longer chain silicon-containing materials may have increased flowability, which may improve bottom-up fill. The source power may be pulsed, and the duty cycle may be reduced, which may further reduce the effective plasma power in some embodiments. For example, the source power may be applied at any higher frequency, such as greater than or about 10 MHz, greater than or about 13 MHz, greater than or about 15 MHz, greater than or about 20 MHz, or higher. The plasma power source may deliver a plasma power to the faceplate of less than or about 300 W, and may deliver a power of less than or about 250 W, less than or about 200 W, less than or about 150 W, less than or about 100 W, less than or about 50 W, or less. Additionally, the source power may be pulsed at a pulsing frequency of 20 kHz or less, such as less than or about 15 kHz, less than or about 12 kHz, less than or about 10 kHz, less than or about 8 kHz, or less. Additionally, the pulsing duty cycle may be applied at less than or about 50%, and may be applied at less than or about 40%, less than or about 30%, less than or about 20%, less than or about 10%, less than or about 5%, less than or about 1% or less. This may limit the silicon precursor dissociation, and improve long-chain formation. In some embodiments, to facilitate dissociation and deposition, the deposition precursors may include one or more inert gases, such as argon and/or helium, which may help improve dissociation. Additionally, in some embodiments the deposition precursors may include diatomic hydrogen, which may be flowed to facilitate a treatment process during the deposition, and which may be aided by the bias power provision. For example, hydrogen may be delivered with the silicon-containing precursor at a flow rate ratio of the hydrogen to the silicon-containing precursor of greater than or about 0.5:1, and may be delivered at a flow rate ratio of greater than or about 1:1, greater than or about 1.5:1, greater than or about 2:1, greater than or about 2.5:1, greater than or about 3.0:1, greater than or about 3.5:1, greater than or about 4.0:1, or more. The hydrogen may also be dissociated in the plasma generated, and may be further activated by utilizing a bias power delivery. For example, in some embodiments, a bias power source may be operated at a lower frequency than the source power, and may be operated at less than or about 10 MHz, less than or about 5 MHz, less than or about 2 MHz, or less. The power supply may be operated at a power of less than or about 500 W, and may be operated at less than or about 450 W, less than or about 400 W, less than or about 350 W, or less. The bias power may create an amount of directionality of effluent movement, and may allow lighter hydrogen radicals to further dissociate argon and/or helium, which may be directed more specifically downward at the structure. The lower frequency power may also impart additional energy to the ions as they travel in more straight-line paths down to the substrate. These hydrogen and inert gas radical species may transfer energy to materials along surfaces normal to the direction of travel, such as material along the bottom of features and along the top of features, such as material315and319. The energy may help release excess hydrogen, which may densify the film in these locations. As illustrated inFIG.3B, while the material317along the sidewalls may not be impacted, or may have limited changes, the material315and319may be densified, which may improve the quality of the materials. Consequently, in some embodiments, material along the top and bottom of the structure may be characterized by a higher quality, which may include an increased density, over material that may have deposited along sidewalls of the features. However, by utilizing a bias power, the deposition plasma may be characterized by an increased power, which may further dissociate the silicon-containing precursor and reduce flowability. Accordingly, to limit this effect, the bias power may also be pulsed at a pulsing frequency of less than or about 10 kHz, and may be pulsed at a frequency of less than or about 5 kHz, less than or about 1 kHz, less than or about 500 Hz, less than or about 100 Hz, less than or about 50 Hz, less than or about 10 Hz, or less. Additionally, the duty cycle may be operated at less than or about 50%, and may be operated at less than or about 40%, less than or about 30%, less than or about 20%, less than or about 10%, less than or about 5%, or about 1%, which may further reduce the impact of the bias power. By operating the bias power at very low pulsing frequency and duty cycle, the bias power may be utilized to increase film quality at the top of the structure and at the bottom of the feature, while limiting an impact on any other deposition characteristics. Additionally, by utilizing a low power, the hydrogen may not be energized sufficiently to cause etching of the deposited material, or lead to sputtering of the material based on bombardment of the inert gas effluents. Subsequent an amount of deposition, in some embodiments of the present technology an etching and/or modifying process may be performed that is configured to etch back the formed material selectively and modifying the remaining material. This process may be performed in the same chamber as the deposition, and may be performed in a cyclic process to fill the feature. In some embodiments the silicon-containing precursor flow may be halted and the processing region may be purged. The flow of inert gases, such as argon and/or helium, may also be halted. Subsequent a purge, a hydrogen-containing precursor may be flowed into the processing region of the processing chamber. In some embodiments, the modification process may only include a hydrogen-containing precursor, which may be diatomic hydrogen in some embodiments. A modification plasma may be formed at operation215, which may also be a capacitively-coupled plasma formed within the processing region, although in some embodiments an inductively-coupled plasma may similarly be applied. Similarly to the deposition process, during the etching operation, an additional power source may be engaged and coupled with the substrate support as previously described to provide a bias to the plasma generated above the substrate. Accordingly, the etch process may also include both source power and bias power. This may draw plasma effluents to the substrate, which may bombard the film and cause densification of the deposited materials, especially the materials that have already been at least partially improved by the treatment performed during deposition. Although any hydrogen-containing material may be used, in some embodiments diatomic hydrogen may be used as the hydrogen-containing precursor to produce the etching plasma. The hydrogen radicals and ions may readily penetrate the materials formed within the trench, and may release incorporated hydrogen from the film causing densification. The bias power applied may be relatively low to limit sputtering of the produced film as well as to limit any potential damage to the structure. Additionally, by adjusting the source power and the bias power applied, an etching operation may be performed, which may reduce sidewall coverage of the deposited material while limiting an effect on the previously treated materials. Diatomic hydrogen, or any other hydrogen-containing material, may be utilized to generate a plasma within the processing region by delivering power to the faceplate from the plasma power source. The plasma power in some embodiments may be greater than a plasma power used during the deposition, both from the source power and the bias power. For example, the plasma source power delivered may be greater than or about 100 W, and may be greater than or about 200 W, greater than or about 300 W, greater than or about 400 W, greater than or about 500 W, or more. By increasing the plasma power during the treatment plasma formation, a greater amount of plasma effluents may be generated. However, as plasma power increases, the amount of material etched from the bottom of the structure may also increase. Accordingly, in some embodiments the plasma source power may be maintained at less than or about 500 W, and may be maintained at less than or about 400 W, less than or about 300 W, or less. Additionally, aspects of the bias power may also be adjusted. For example, in some treatment operations the bias power may be higher than the plasma source power, which may provide enough power to the plasma to ensure etching of lower quality materials occurs, such as materials along the sidewalls that may not have been treated during the deposition operation. Applying greater bias power may increase an ability of the hydrogen to etch deposited materials. While the bias power during deposition may be reduced to limit an etching effect, during the modification operation a bias power, which may be at any of the frequencies noted above, may be increased to greater than or about 500 W, and may be increased to greater than or about 800 W, greater than or about 1000 W, greater than or about 1200 W, greater than or about 1400 W, greater than or about 1600 W, greater than or about 1800 W, or more. However, because the bias power may impart directionality, the bias power may be pulsed as discussed below, which may provide etching of the lower quality material, while maintaining the material previously treated, and which may modify and/or densify the material. The plasma effluents may then etch the flowable film at operation220, and may remove the flowable film from the sidewalls of the trench. Simultaneously, and beneficially, plasma effluents delivered more directionally may penetrate the remaining film formed at the bottom of the feature, and may reduce hydrogen incorporation to densify the film at optional operation225. As illustrated inFIG.3C, material317may be removed from sidewalls and overhang regions of the substrate305, which may maintain the deposited material at bottom regions of the feature and along the top region of the structure. As an added benefit, the densified material319at the top of the structure may also protect the underlying material from damage by limiting any impact on the materials. The process may also provide a reduced hydrogen incorporation in the remaining material, such as a hydrogen incorporation of less than or about 40 at. %, and may provide a reduced hydrogen incorporation of less than or about 35 at. %, less than or about 30 at. %, less than or about 25 at. %, less than or about 20 at. %, less than or about 15 at. %, less than or about 10 at. %, less than or about 5 at. %, or less. Additional adjustments may be made to further increase etching of deposited material along sidewalls of the features by adjusting one or more characteristics of the plasma power or bias power being supplied. For example, in some embodiments both the plasma power source and bias power source may be operated in a continuous wave mode. Additionally, one or both of the power sources may be operated in a pulsed mode. In some embodiments, the source power may be operated in a continuous wave mode while the bias power is operated in a pulsed mode. A pulsing frequency for the bias power may be any of the pulsing frequencies discussed previously. The duty cycle of the bias power may be less than or about 75%, and the bias power may be operated at a duty cycle of less than or about 70%, less than or about 60%, less than or about 50%, less than or about 40%, less than or about 30%, less than or about 20%, less than or about 10%, less than or about 5%, or less. By operating the bias power for a reduced duty cycle, such as an on-time duty of less than or about 50%, a greater amount of time per cycle may be performing a more isotropic etch within the feature, such as during the off time, which may better remove material from the sidewalls. Additional power configurations may also include an amount of synchronization of the source power and the bias power in a master/slave relationship. For example, both power supplies may be operated in a pulsing orientation, and the bias power may be synchronized to engage after the source power has been engaged at each pulse. A level-to-level pulsing scheme may also be applied. For example, during the on duty of the bias power, the source power may be operated at a first plasma power. During the remainder of the cycle where the bias power is off, the source power may be operated at a second plasma power, which may be greater than the first plasma power. This may both increase isotropic etching by removing the bias-induced directionality, and may also increase etching characteristics of the isotropic etch. The deposition and etch processes may be repeated any number of times in cycles to fill a feature in embodiments of the present technology, which may fill a feature with amorphous silicon. Additionally, in some embodiments where the silicon may be sought to be converted within the feature, the cycling may also include a conversion operation. By converting during each cycle, penetration issues through the feature may be fully resolved. Also, by performing a conversion operation subsequent to the curing and etching/modification, deposited material may be removed from the sidewalls prior to conversion, which may limit film expansion laterally within the trench or feature between sidewalls as previously described. The conversion may be performed in a different chamber from the deposition and treatment, although in some embodiments two or more, including all operations, may be performed within a single processing chamber. This may reduce queue times over conventional processes. Method200may also optionally include conversion of the amorphous silicon to another material. For example, subsequent to the etching and densifying, one or more conversion precursors may be delivered to the processing region of the chamber. For example, a nitrogen-containing precursor, an oxygen-containing precursor, and/or a carbon-containing precursor may be delivered to the processing region of the chamber, along with any carrier or diluent gases. A plasma may be formed of the conversion precursor, which may then contact the amorphous silicon material within the feature. At optional operation230, plasma effluents of the conversion precursor may interact with the amorphous silicon material within the trench, and convert the material to silicon nitride, silicon oxide, silicon carbide, silicon oxynitride, silicon oxycarbide, silicon carbon nitride, or silicon oxycarbonitride, along with any other materials that may be used to convert amorphous silicon films. The plasma power may be similar to powers previously stated, and may be from about 100 W up to about 1,000 W or more for a capacitively-coupled system, as well as up to 10 kW or more for an inductively-coupled plasma system, for example, although any type of conversion may also be performed. Although the deposition may be formed to several nanometers or more, by performing an etch process as previously described, the thickness of densified material may be controlled to be at a thickness of less than or about 500 Å, and may be less than or about 450 Å, less than or about 400 Å, less than or about 350 Å, less than or about 300 Å, less than or about 250 Å, less than or about 200 Å, less than or about 150 Å, less than or about 100 Å, less than or about 50 Å, or less. By controlling the thickness of the deposited material, conversion through the entire thickness may be performed more readily, and penetration issues common in conventional processes may be resolved. After a conversion of deposited material, the process may then be fully repeated to continue to produce the converted material up through the feature. Any number of precursors may be used with the present technology with regard to the deposition precursors used during any of the formation operations. Silicon-containing precursors that may be used during any silicon formation, silicon oxide formation, or silicon nitride formation may include, but are not limited to, silane (SiH4), disilane (Si2H6), trisilane, or other organosilanes including cyclohexasilanes, silicon tetrafluoride (SiF4), silicon tetrachloride (SiCl4), dichlorosilane (SiH2Cl2), tetraethyl orthosilicate (TEOS), as well as any other silicon-containing precursors that may be used in silicon-containing film formation. By utilizing higher order silanes, longer material chains may be produced, which may increase flowability in some embodiments. The silicon-containing material may be nitrogen-free, oxygen-free, and/or carbon-free in some embodiments. Oxygen-containing precursors used in any operation as described throughout the present technology may include O2, N2O, NO2, O3, H2O, as well as any other oxygen-containing precursors that may be used in silicon oxide film formation, or other film formation. Nitrogen-containing precursors used in any operation may include Na, N2O, NO2, NH3, N2H2, as well as any other nitrogen-containing precursor that may be used in silicon nitride film formation. Carbon-containing precursors may be or include any carbon-containing material, such as any hydrocarbon, or any other precursor including carbon. In any of the operations one or more additional precursors may be included, such as inert precursors, which may include Ar, He, Xe, Kr, or other materials such as nitrogen, ammonia, hydrogen, or other precursors. Temperature and pressure may also impact operations of the present technology. For example, in some embodiments to facilitate film flow, the process may be performed at a temperature below or about 20° C., and may be performed at a temperature less than or about 0° C., less than or about −20° C., less than or about −50° C., less than or about −75° C., less than or about −100° C., or lower. The temperature may be maintained in any of these ranges throughout the method, including during the treatment and etching, as well as the conversion. Pressure within the chamber may be kept relatively low for any of the processes as well, such as at a chamber pressure of less than or about 20 Torr, and pressure may be maintained at less than or about 15 Torr, less than or about 10 Torr, less than or about 5 Torr, less than or about 3 Torr, less than or about 2 Torr, less than or about 1 Torr, less than or about 0.1 Torr, or less. By performing processes according to some embodiments of the present technology, improved fill of narrow features utilizing silicon-containing materials may be produced. In the preceding description, for the purposes of explanation, numerous details have been set forth in order to provide an understanding of various embodiments of the present technology. It will be apparent to one skilled in the art, however, that certain embodiments may be practiced without some of these details, or with additional details. Having disclosed several embodiments, it will be recognized by those of skill in the art that various modifications, alternative constructions, and equivalents may be used without departing from the spirit of the embodiments. Additionally, a number of well-known processes and elements have not been described in order to avoid unnecessarily obscuring the present technology. Accordingly, the above description should not be taken as limiting the scope of the technology. Additionally, methods or processes may be described as sequential or in steps, but it is to be understood that the operations may be performed concurrently, or in different orders than listed. Where a range of values is provided, it is understood that each intervening value, to the smallest fraction of the unit of the lower limit, unless the context clearly dictates otherwise, between the upper and lower limits of that range is also specifically disclosed. Any narrower range between any stated values or unstated intervening values in a stated range and any other stated or intervening value in that stated range is encompassed. The upper and lower limits of those smaller ranges may independently be included or excluded in the range, and each range where either, neither, or both limits are included in the smaller ranges is also encompassed within the technology, subject to any specifically excluded limit in the stated range. Where the stated range includes one or both of the limits, ranges excluding either or both of those included limits are also included. As used herein and in the appended claims, the singular forms “a”, “an”, and “the” include plural references unless the context clearly dictates otherwise. Thus, for example, reference to “a precursor” includes a plurality of such precursors, and reference to “the layer” includes reference to one or more layers and equivalents thereof known to those skilled in the art, and so forth. Also, the words “comprise(s)”, “comprising”, “contain(s)”, “containing”, “include(s)”, and “including”, when used in this specification and in the following claims, are intended to specify the presence of stated features, integers, components, or operations, but they do not preclude the presence or addition of one or more other features, integers, components, operations, acts, or groups. | 43,054 |
11862459 | DETAILED DESCRIPTION Certain embodiments of the invention relate to methods of making a III-nitride semiconductor device. This III-nitride material may e.g. be GaN, InGaN (Indium Gallium nitride), or AlGaN (Aluminum Gallium nitride). The method may comprise forming a plurality of semiconductor seeds over a substrate. The substrate may be any suitable material for growing III-nitride seeds or nanowires, for example a GaN, silicon, SiC, sapphire or AlN wafer which may optionally contain one or more buffer layers, such as a GaN buffer layer on a silicon substrate. For homogeneous fabrication of GaN wafers and arrays the basic atomic information the substrate material provides to the process is a uniform crystal orientation to all seeds and a competitive surface for selective nucleation of GaN. Such a surface may be provided through thin films, such as graphene, ALD-fabricated oxides and LPCVD-fabricated AlN. In various embodiments, the seeds are continuously grown to nanowires. In various embodiments, a semiconductor volume element is grown on each seed or nanowire. In a planarizing step, a plurality of discrete templates, or base elements, having a substantially planar upper surface, are formed. After planarizing, a step of c-plane surface repair growth may also be performed. Subsequent steps may include forming a device, such as an electronic component, in or on each of the plurality of base elements. As will be discussed, the planarizing step is most appropriately also called a reformation-step. It's our understanding that the large-scale homogeneity seen in the reformation step discussed herein is enabled by homogeneous crystal structure of the dislocation-free crystal templates used. Hitherto, the only known way to provide such an array of dislocation-free templates is through selective NW-growth. Furthermore, a fundamental level it is understood that the dislocation-free nature of the array is dependent on combination of the aperture dimension of the opening in the mask and the specific epitaxial growth conditions. NW growth conditions are no magic bullet but has been shown to provide such dislocation-free crystals. Since the generation of dislocation-free crystals is the prominent task of the NW growth step and, for the purpose of this application, any epitaxial conditions that provides such monocrystalline templates are considered to be NW-conditions. Different embodiments will now be discussed with reference to the drawings. It shall be noted that reference is made to certain examples of devices and methods, where materials and process parameters of working embodiments are given. This does not, as such, mean that certain steps or features may be of a different character or art without departing from the general scope of the solutions proposed herein, and which fall within the scope of the appended claims. In addition, more details related to e.g. nanowire growth in III-nitride materials are available to the skilled person in e.g. the above-referenced prior application. FIG.1schematically illustrates method step of the production of a III-nitride semiconductor device. In a step a) a base substrate101of e.g. sapphire is provided. In a step b) one or more layers102of e.g. GaN are formed on the base substrate101. Together, the layers101and102form a substrate. In a step c) a mask layer103of e.g. SiNxmay be formed on top of the substrate. In a subsequent step d), holes104are provided in the mask layer103, e.g. by means of EBL (electron beam lithography). The holes may be very narrow, e.g. with a diameter of 50-150 nm, or 60-100 nm. The pitch between the holes104may e.g. be in the order of 200-2000 nm, and is selected dependent on inter alia the electronic devices to be formed on the templates which are to be created on the substrate, and may also depend on the material of the III-nitride. In a step e) growth of a first III-nitride material is performed or at least initiated. Step e) indicates the initial growth, in the form of substantially pyramidal seeds105, protruding from the holes104. In a subsequent step f), which need not be included in all embodiments, as will be explained, the seeds105are grown into nanowires106, by continued growth of the III-nitride material of the seeds105, e.g. by CVD or VPE in a nanowire growth step, wherein a nitrogen source flow and a metal-organic source flow are present. In an embodiment including growth of nanowires as in step f), the process from d) to f) is typically continuous. In one embodiment, the seed105and subsequently grown nanowires106comprise GaN. By growth from holes104, which represent a very small portion of the substrate surface, a large majority of any dislocations in the substrate III-nitride102are filtered out. In addition, dislocations close to the edge of a hole104tend to bend off towards one side of the grown nanowire106. Nanowires of GaN are thus grown, normally in a hexagonal shape with6equivalent and smooth m-plane facets, where dislocations are seen to terminate towards the SiNxmask. The result is entirely or substantially dislocation free seeds105or nanowires106of GaN, e.g. to a degree of at least 90% or at least 99% of the seeds105or nanowires106being dislocation free. A nitride semiconductor nanowire106as discussed herein is in this context defined as an essentially rod-shaped structure with a diameter less than 1 micron, such as 50-100 nm and a length up to several μm. The method of growing nitride semiconductor nanowires according to one non-limiting embodiment of the invention utilizes a CVD based selective area growth technique. A nitrogen source and a metal-organic source are present during the nanowire growth step and at least the nitrogen source flow rate is continuous during the nanowire growth step. The V/III-ratio utilized for nanowire growth is significantly lower than the V/III-ratios commonly associated with the growth of nitride based semiconductor, as also outlined in the referenced earlier US application. For an embodiment of GaN, processing according to g) ofFIG.1may continue. Here, a GaN volume element107is grown on each nanowire106. This step of forming the volume element107on the nanowires106may be carried out by CVD or VPE in a volume element growth step, wherein the nitrogen source flow and the metal-organic source flow are present. Preferably, the molar V/III-ratio during the volume element107growth step is higher than the molar V/III-ratio during the nanowire growth step. The volume element107grows to comprise a discreet insulating or semi-insulating GaN pyramid formed around each GaN nanowire106. In an alternative embodiment, processing according to step g) ofFIG.1may be performed from the seed stage of e), without fully growing nanowires106, as indicated by the vertical arrow in the drawing between steps e) and g). Also this step of growing a GaN volume element107on seeds105may be carried out by CVD or VPE in a volume element growth step, wherein the nitrogen source flow and the metal-organic source flow are present. Preferably, the molar V/III-ratio during the volume element107growth step is higher than the molar V/III-ratio during the seed growth step. The volume element107grows to comprises a discrete insulating or semi-insulating GaN pyramid formed around each GaN seed105. Further details related to volume growth may also be obtained e.g. from the referenced US application by the instant inventor. The process also includes a planarizing step. This may be carried out either after a nanowire growth step f), or alternatively after a volume element107growth step g), as indicated inFIG.1. In one embodiment, in which a GaN growth of nanowires106, and potentially also a GaN volume element107, is subjected to planarizing to obtain a flat c-plane mesa108as shown in h), the inventors have discovered the surprising effect that, by carefully selecting process parameters, the planarization can be performed without, or at least without any significant, desorption of GaN. In such an embodiment, the planarization is instead obtained by controlled atomic redistribution of the nanostructure, i.e. the nanowire106when planarizing from f) to h), or the volume element107when planarizing from g) to h). Such a step may be carried out by providing a high, or even very high, flow of Nitrogen-containing material, typically NH3, while throttling, or preferably completely omitting, supply of additional flow of Ga source material. In other words, no or substantially no new Ga atoms are supplied. In one embodiment, the flow of NH3may e.g. be in the order of 5-20, in certain embodiments within 9-10 slm, while the Ga source is completely shut off. The process temperature may be maintained as held in a receding volume growth step, or be elevated, e.g. in the range of 1000-1200 degrees Celsius for GaN (the range going down to 700 for InGaN growth and up to 1500 for AlGaN growth). The inventors have found that the research results indicate that by selecting suitable process conditions, Ga atoms may break their crystal bond, without actually being completely desorbed and leave the GaN crystal surface. Instead, single Ga atoms may still be physically attached, even if the chemical bond is broken, herein referred to as physisorbed. Such a physisorbed Ga atom may travel on the surface of the GaN device, and reattach at another place. More specifically, given the right conditions, such as exemplified, a cone of a volume growth or element107may grow in the normal direction to the slanting s-plane, such that vertical m-planes underneath, and the planar top c-plane, increase. By providing the high NH3flow, or back pressure, while the temperature is optimally elevated, sufficient mobility of physisorbed Ga atoms is obtained, while excessive dissociation is avoided, such that the described atomic redistribution may be obtained. The process temperature at the planarizing step should preferably still be kept below a certain upper level, for the purpose of avoiding a three phase system where liquid Ga may form droplets on the surface of the GaN device. Exemplary test results are depicted inFIG.2, whereFIG.2Ashows a substantially cone-shaped or pyramidal GaN device as created by volume growth107.FIG.2Billustrates the transformation of a device ofFIG.2A, when subjected to planarization by atomic redistribution, as described. Evidently, the m-planes and the c-plane have increased, while the s-plane has decreased. The result is, inter alia, that an enlarged c-plane has been obtained, usable for providing e.g. epitaxial layers or other provision of contacts etc. Still, the decreased or even eliminated degree of dislocations in the GaN surface as obtained by mask growth, is maintained. In other words, the average amount of dislocations per surface area unit is substantially lower, ideally nil, as compared to an epitaxially grown continuous GaN surface, such as layer102. Furthermore, the increase of the c-plane in the planarization step can be obtained in situ, without removal of the substrate from the machine after nanowire and potential volume growth, and without involvement of other material, such as etchants. This way, process speed and reliability may be improved. Test results have also shown that in one embodiments, atomic reconstruction may be carried out under circumstances such that mobile physisorbed Ga atoms will rather attach on the m-plane than on the c-plane. In such an embodiment, the results of the in crystal reconstruction involves the effect that a wider c-plane may be, which is usable for component configuration, than for a pure etching or polishing process. In one embodiment, the suggested process is applied for an InGaN device. In such a process, steps a) to d) are also included. In one variant, the substrate layer102may also include an InGaN layer, on which a seed105and subsequently a nanowire106is grown of InGaN. Volume growth of InGaN is then carried out, on the InGaN nanowire106, in step g). In an alternative embodiment, which has provided more reliable lab results, the process from a) to e) is the same as for GaN, i.e. with GaN seed growth on a GaN substrate layer102. However, the GaN growth is stopped at the seed stage, preferably when the seed105is only a small pyramid, preferably with no m-plane over the mask level. After that, volume growth of InGaN is applied onto the GaN seed105, to the state of a pyramid volume as in g). By starting with GaN growth, a lower level of dislocations may potentially be provided in the seed105. In addition, by providing volume growth of InGaN already on the small seed105of GaN, rather than on a GaN nanowire, the risk for dislocation errors in the volume growth is minimized. In the planarizing step from g) to h) of an InGaN volume107at an elevated temperature, a high degree of dissociation is normally involved, and may be dominating over any atomic redistribution.FIG.3Aillustrates an InGaN volume device107, and although this is only a top view, its pyramidal shape is evident.FIG.3Bshows such volume device after planarizing, e.g. at a temperature in the range of 1100-1200 degrees Celsius, with a high NH3flow of 5-10 slm and absent any additional provision of In or Ga during the planarizing step. Also in this case, the planarization is obtained without providing any etchants, and c-plane increase is also obtained without any minimization of the width of the devices. As can be seen, though, a pattern of trenches may occur in the c-plane surface, potentially caused by the different boiling temperature of In and Ga. In a preferred embodiment, a repair step of providing additional InGaN growth may therefore be carried out, after planarization. When doing so, pyramidal growth will again occur, as during the preceding volume growth step from e) to g). However, only a limited number of atomic layers are required, and after that, further epitaxial growth may be carried out to form electrical components, e.g. red and green light-emitting diodes.FIG.3Cshows a slanted image of such a device300, where the planarized InGaN body308forms the base part, additional InGaN repair layers309are provided thereon, and epitaxial component layers310are formed on the repair layers309. AlsoFIG.4illustrates the process of manufacturing a light emitting diode on an InGaN device as described with reference to the preceding description and drawings, starting from a GaN seed. In the middle lower picture ofFIG.4, the side view of device300also clearly shows the layers308,309, and310. In one embodiment, the general growth process incorporating planarization is employed for the production of AlGaN devices. One such device500is shown in a side cross-section view inFIG.5. The high degree of reactivity of Al with other materials presents a hurdle for growing AlGaN from mask holes, since the Al may grow on the mask too. For this reason, the inventors have come up with a new way of manufacturing planar AlGaN templates, on which to provide further epitaxial growth for component production. Referring back toFIG.1, the process steps from a) to f) are carried out with GaN, for the beneficial reasons already referred to with regard to elimination or minimization of dislocations. (The process may alternatively be halted already at the seed level of e), dependent inter alia on hole size and on how large GaN planar mesas are desired.) After a plurality of GaN nanowires106(or seeds105) have been grown to contain desired volume, a planarizing step is carried out at h). In other words, there is preferably no volume step g) involved in the AlGaN process. The result after atomic distribution as described above for GaN, will be a flat mesa508with a relatively small diameter, e.g. compared to the hole, since there is much less material in the growth when no volume growth step has been carried out. As an example, for a mask hole104size of 60-100 nm, the planarized GaN mesa structure508may have a width of 200-300 nm, i.e. in the range of only e.g. 2-5 times the mask hole size. In addition, the flat GaN structure will be configured, by atomic redistribution, to be very thin, e.g. with a GaN thickness t1in the range of 30-100 nm. In a subsequent process step, AlGaN growth is begun. As noted, layers may then grow on all parts of the substrate and on all facets of the flat GaN mesas. More importantly, AlGaN growth is deliberately continued until a layer509having a relatively large thickness t2, compared to t1. The reason for this is that any plastic deformation, as caused by the lattice mismatch between GaN and AlGaN, will occur in the GaN layer508rather than in the AlGaN layer509. So, rather than a thin AlGaN layer509stretching to adapt to the crystal structure of the GaN mesa layer508, a relatively thick AlGaN layer509will compress or contract the GaN layer508, in the region of the interface between the materials. The growth of AlGaN layer509shall preferably be carried out at a comparatively low temperature, for AlGaN growth, which will help retain template shape at subsequent higher temperatures when adding layers over layer509. The result is a substantially or entirely dislocation free AlGaN layer, on which further epitaxial layers510, contacts or other component structures may be built. In various embodiments, incorporating any one of the above-referenced embodiments and materials, the process may involve epitaxially growing a semiconductor displacing layer on the planarized volume element such that an upper surface of the displacing layer is located above the upper tip of the nanowire or seed, and the upper surface of the displacing layer forms the upper surface of each of the base elements, or alternatively that planarizing is halted at a stage where said tip is still below the upper c-plane layer of the planarized device. Referring back toFIG.1, in one aspect of the invention, a planarizing step is carried out to reform and merge or unite adjacent nanowire of volume growths. This is schematically illustrated through step i) ofFIG.1. This may be carried out either after a nanowire growth step f) or after a volume element107growth step g), and can be seen as a continued planarizing step via stage h). The result is a continuous planar semiconductor layer or film109, obtained from a plurality of separate growths. This process is referred to herein as coalescing. As an example, a planar GaN layer may be obtained by coalescing. In one embodiment, GaN nanowire growth may be obtained using standard precursors TMG, TEG, NH3 and nitrogen and hydrogen carrier gases, on a patterned substrate, with a thin mask layer103—silicon nitride, silicon dioxide or similar. Openings104in the mask can be done by the standard lithographic techniques like nanoimprint or electron beam lithography, and developed using dry etching techniques like ICP-RIE and wet chemical etching. The spacing between the openings104can be adjusted during nanoimprint or EBL—typical values are 400, 600, 1000 or 2000 nm. The opening diameter is defined in the nanoimprint or EBL lithographic process, with typical values between 50-400 nm, depending on the used lithography technology. By means of suitable process steps, e.g. as described with reference to steps a) to e) above, a GaN seed105may be grown. Dependent on selected process parameters, the seed may evolve to nanowires106as in step f) or to volume elements107as in step g). Alternatively, the volume elements10/may be created by radial volume growth on nanowires106grown in step f). In one embodiment volume GaN growth or GaN nanowires are subjected to a coalescing/planarization step, in which a cohesive c-plane planar layer is obtained as shown inFIG.1i). In such an embodiment, the coalescing step may be carried out under a nitrogen-sustaining background condition using, for example, ammonia, while throttling or completely omitting column-III element-containing gas precursor as described above with reference toFIG.1. FIG.6Ashows volume growth structures as described in steps a-g. The semiconductor structure having a plurality of individual volume growths (or nanowires) may be subjected to a subsequent coalescing step for merging the individual structures. The coalescing step may e.g. involve processing of the substrate at a temperature in the range of 1000-1200 degrees Celsius, with a high NH3 flow of 1-10 slm and absent any additional provision of Ga. FIG.6Bshows a flat c-plane GaN surface after the coalescing step, in which it is observable that the individual growth structures flatten out and coalesce together.FIG.6Cshows a zoom out overview of larger area with uniformly coalesced GaN planar film. In the drawn figure aboveFIGS.6Band C, it is indicated that the reformation has progressed such that the top of each nanowire is exposed to the planar coalesced surface. It should be noted, though, that in other embodiments planarization may be obtained by reformation only of the volume growth, such that a seed or nanowire grown prior to, and encapsulated by, the volume growth is not exposed. A variant of the embodiment described with reference toFIGS.6A-Bmay be to continue volume growth as shown inFIG.6Auntil the individual growths merge to some degree, at least at the base close to the mask surface. In such an embodiment, the subsequent coalescing step will nevertheless cause reformation of the grown structures, so as to form a cohesive flat surface extending over the individual growth positions. For individual growths from a patterned mask103, the orientation of the nanowires or volume growths can be such that the side facets can be oriented in any of two in-plane orientations, i.e. in [1-100] or [−12-10]. While it would seem that merging of individual adjacent nanowires or volume growths would benefit from such adjacent growths having facing facets, the inventors have found that the flat c-plane GaN surface after the coalescing step can be formed in any of those two orientations. For example, in the planar semiconductor structure obtained inFIG.6B, the originating nanowires are facing in [−12-1-0] with respect to each. The reformation process with mobile physisorbed atoms is consequently a suitable process for producing a cohesive planar semiconductor III-Nitride layer or film109. In one embodiment, a planar III-N film110can further be grown on the coalesced film109. An example is shown inFIG.6Dby means of a SEM top view of a 500 nm thick planar GaN layer110that has been grown on the coalesced film109, whileFIG.6Eshows a cross-section SEM image of the structure. In accordance with one aspect, the inventors have found out that by controlling the coalescing step growth conditions it was possible to grow a coalesced planar layer from groups of two or more structures to form a larger platelet or mesa, e.g. compared to single structure mesas as inFIG.2B. An example of such a structure is shown inFIG.7A, which shows a triplet structure consisting of three volume growth structures, which have been coalesced into one planar platelet701.FIG.7Bshows a variant, where five growths have been merged into one planar platelet703. The ability to, in this way, form separate planar layers, designed in shape and size, gives the opportunity not only to fabricate wafers with separate insulated devices but also to provide the wafer with pre-deployed vias already at the wafer fabrication step. In one embodiment, a substrate may e.g. be configured with a mask103having a predetermined pattern of openings104, distributed such that growth through the openings and subsequent coalescing will result in a desired shape of a planar semiconductor structure. In such embodiments, the volume GaN growth or GaN nanowires could be subjected to a radial volume enlargement growth step in order to make the decrease the gaps in between neighbouring nanowires or volume growth structures, but it is not necessary to for the purpose of obtaining the flat c-plane GaN surface. FIG.7Cillustrates, by way of a schematic example, a part of a substrate709provided with a mask having openings. In this embodiment, the openings are provided in an ordered manner, such that a first subset710of the openings form one pattern, and a second subset712of the openings form another pattern. After growth of semiconductor structures through the openings, e.g. in accordance with the preceding description, nanowires and/or volume elements will extend from the substrate surface through the openings710,712. In a step of coalescing, preferably carried out in situ in the same machine as used for growing and without intermediate removal of the substrate, the grown structures are subjected to operating conditions in which atoms are mobilized but kept attached, physisorbed, at the surface of the respective growth. In selected suitable conditions, as exemplified above for the steps of reformation and coalescing, the individual growths will flatten out, and closely adjacent growths will merge into a common planar layer. By arranging the openings in a manner such that certain growths will merge and certain will not, planar layers711,713that are cohesive but also separate from each other may be formed. Such planar layers711and713may also assume a large variety of sizes and shapes. This provides a freedom of production that has hitherto not been available in the art of preparing planar III-N structures. The coalescing step, as described brings a non-obvious advantage over, traditional, epitaxial methods of re-growth, such as ELO (Epitaxial-lateral overgrowth). Epitaxial regrowth is made under active growth-conditions with supersaturation as driving force. Crystallization from the gas phase reduces the free energy of the system, resulting in forced conditions where dislocations and defects can be formed, especially when non-aligned crystal growth fronts meet and coalesce, as in epitaxial regrowth and epitaxial overgrowth. In contrast, the reformation occurring during e coalescing step is carried out near thermal equilibrium. During the planarization and coalescing step as described herein, no, or little additional column-III element is added to the epitaxial crystal. The epitaxial system is in a zero net-volume growth state but with conditions allowing for high surface mobility of physisorbed material. When dissociation- and chemisorption-rates are kept comparable, each physisorbed molecule is, ideally, free to repeatedly move, chemisorb and dissociate until it finds the lowest-energy crystal position to occupy. Dislocations in the crystal structure, as well as most defects results in a higher free energy, whereas the total binding energy to the crystal will be lower than in the case of the ideal crystal. All in all, making the planarization and coalescing step is much less prone to produce or comprise such crystal faults. In one embodiment, the volume III-nitride growth is carried out with In or Al to obtain a flat c-plane InGaN or AlGaN surface. As a more specific example, a coalescing process applied for InGaN growth is described. In such a process steps a to d are included. Depending on step d array design coalesced planar InGaN layer or coalesced InGaN structure consisting of groups of two or more nanowires or volume growth structures could be grown, e.g. through steps e-g or e-f-g. By supplying In-precursor flow simultaneously with Ga-precursor flow during volume-growth ternary InGaN may be formed in step g) from e) or f). When the volume growth is subjected to the coalescing step i), both gallium and indium atoms are free to move, chemisorb and dissociate until they find low energy crystal positions. A planar InGaN coalesced layer is thus formed. An exemplary InGaN coalesced layer is given inFIG.8A, in which a cohesive InGaN layer made from a plurality of merged individual growths of InGaN can be seen. In a preferred embodiment a repair planar InGaN growth can be carried out after the coalescing step, as described above with reference toFIG.4. When doing so a planar InGaN growth will occur, on top of the coalesced layer. Since it is typically difficult to avoid defect formation and material degradation with higher indium, the method proposed herein provides an alternative growth technique where crystal faults are less prone to form. A planar InGaN layer, obtained by the proposed coalescing method, with reduced dislocation density will provide a very good substrate for optoelectronic device applications. It could be also directly used in typical CVD or VPE growth of III-nitride optoelectronic devices. FIG.8Bshows an alternative embodiment of volume III-nitride growth with In or Al, developed to obtain a flat c-plane InGaN or AlGaN surface formed from a group of three openings in SiNxmask. The structure ofFIG.8Bis similar to the structure ofFIG.7A, in that a limited number (three in this example) of ordered growths are coalesced into a via. The structure ofFIG.8Bhas not, yet, been provided with a repair layer, as evidenced by the surface structure which is characteristic for a transformed InGaN structure. In order to obtain the structure ofFIG.8B, a mask structure as shown in d) is selected, where the number, order and spacing of openings104are carefully selected. In step e) groups of two or more nanowires or volume growth structures could be formed. By introducing additional indium precursor flow during volume growth indium content in the volume growth g) can be added. When the volume growth is subjected to a coalescing step i) nanostructures or volume growth are coalesced, i.e. merged and made to form an increased c-plane surface. In one preferred embodiment, a smoothening InGaN growth layer can be grown out after the coalescing step, in a surface repair step. The embodiments ofFIGS.7Aand B and8B illustrate examples of a semiconductor structure comprising a substrate, a mask provided on a surface of the substrate, the mask having a plurality of openings provided in an ordered manner along the substrate surface, wherein a cohesive planar via of a III-N material extends over a plurality of openings in a substrate mask. The planar via is formed by merged individual semiconductor structures grown through different openings. The openings may be provided at equidistant positions along a path along the substrate surface. The coalescing step may be carried out in situ in a subsequent step to individual semiconductor growth, wherein atomic reformation is carried out at an increased temperature with a high back pressure of nitrogen, without or with substantially no additional source of column III semiconductor material. The solutions outlined above, for providing flat structures of III-N semiconductor material, such as e.g. GaN and InGaN, in the form of platelets or even coherent flat layers is a great and also unexpected achievement. It is now 100 years since the so-called Czochralski process was invented, according to which a solid crystal is slowly pulled up from a melt. This is still the basis for growth of Si ingots. Other, similar, techniques used for fabrication of conventional semiconductors, such as Ge, GaAs, GaP and InP, are the Bridgman technique and the float zone process. These technologies all have in common the use of a liquid/solid growth front, with a minutely controlled growth rate and temperature gradient, ΔT, and initiated from a dislocation-free crystal seed. In these growth processes, ΔT will determine the growth rate, with a high ΔT forcing fast condensation of the crystal. In the Czochralski process the “Perfect Si Crystal” conditions are met when the growth rate is sufficiently fast as to avoid creation of Si crystal vacancies, but sufficiently slow, or unforced as to avoid incorporation of interstitial Si. In Czochralski growth, a low ΔT gives a low driving force for precipitation and the system is said to be close to thermodynamic equilibrium. In thermodynamic equilibrium, the atoms have the same probability for precipitation into the crystal from the liquid phase as for dissociation from the crystal phase to the liquid. In this case other factors will determine where the atoms go in the end. It is easy to realize that interstitial incorporation of atoms, or inclusions of vacancies represent a smaller decrease in free energy for the system than incorporation of adatoms at their respective lattice sites. With reference toFIG.9A, the Czochralski process is a transition between liquid phase and the crystal phase, represented by the double-headed arrow. However, as seen from the diagram, a phase boundary between solid and liquid GaN emerges only at pressures above 6 GPa. This makes liquid phase epitaxy of GaN an immense challenge with GaN semiconductor wafers instead predominantly fabricated on foreign substrates, by metal organic vapor phase epitaxy (MOVPE). In order to improve the crystal quality of GaN grown on sapphire and Si, epitaxial lateral overgrowth (ELO) has been developed in order to reduce dislocation density and provide higher quality substrates, and early results did show much promise and lately it has been adopted for nanowires. In various embodiments of the solutions proposed herein, though, the epitaxial physics of a peculiar epitaxial regime is explored, which is denoted crystal reformation herein. This crystal reformation may be carried out as a step of planarization of a III-nitride material grown on a seed at a mask opening, as outlined for several different embodiments above. The planarization of the III-nitride material serves to form a plurality of discrete base elements having a substantially planar upper surface. Crystal reformation is performed near equilibrium conditions and supersaturation is not created by addition of material. In contrast to MOCVD growth in general, it's not required to supply the III-V nitride crystal growth front with column III-material in order to drive the phase transition. One significant aspect of equilibrium growth and the described method is reversibility of the phase transition, i.e. the ability to reverse the propagation of the growth front, going forwards or backwards, by changing the thermal bias. In our case the thermal bias, driving the reformation, is supplied by the difference in surface energy of the crystal facets: Net atomic dissociation at one crystal facet takes place simultaneously with net precipitation, or crystallization, at another facet. In this sense the epitaxial growth front comprises all involved facets but local growth rates may be both positive or negative. In various embodiments, a supply of NH3is kept in order to avoid degradation of the crystal surface, and the temperature is elevated, as exemplified for various embodiments. In yet another embodiment for GaN, the elevated temperature may be in the range of 900° C. and 1200° C., or between 700° C. and 1000° C. In one embodiment the elevated temperature is above the sublimation temperature of the crystal material. During the reformation, the inventors have observed the surprising effect that a substantial portion of the crystal is transferred from one facet to another. FIG.9Billustrates a calculated Ga—N phase diagram at atmospheric pressure. Here it may be noted that the Gas+GaN regime, where the reformation step would be positioned, marked by dashed lines, requires an excess of atomic nitrogen and that Ga would be in liquid form. Furthermore,FIG.9Cshows the known Ga—N binary phase diagram according to Subvolume F ‘Ga—Gd—Hf—Zr’ of Volume 5 ‘Phase Equilibria, Crystallographic and Thermodynamic Data of Binary Alloys’ of Landolt-Börnstein-Group IV Physical Chemistry. As noted therein, “An experimentally determined phase diagram is not available”. This goes to show that hitherto there is in fact not sufficient experimental data to draw the phase-diagram for N>50%, The phase diagram corresponding to the reformation-conditions is not available. Although the environmental conditions suggest Ga to be in liquid phase, as the data suggest an additional condition of a low desorption—rate of the Ga atoms within the process window. The solutions proposed herein, for providing planar III-N materials by reformation, consequently form a new solution with beneficial, unexpected results, obtained by processes carried out in an untrodden territory of physics. The shape-transformation is most likely driven by the surface energies of the facets. Growth on higher order facets are favored, such that formation of lower order facets and the 0001 c-plane is strongly favored, as can be anticipated from published work on kinetic Wulff crystal shapes in GaN. The kinetic Wulff model aims to predict the shape of a small crystal based on the relative surface energy ratios of the facets. The inventors propose to complement this model with an atomic picture, which may be associated with the embodiments described herein: 1. Each atom that dissociates from the crystal may stay in a physisorbed state or desorb to the gas-phase. Since the volume of the crystal remains intact, it may be concluded that desorption can be discounted and the atoms remain physisorbed until they are incorporated to the crystal again. 2. The probabilities for going into a physisorbed state and into a crystal-bound state are both high, but with a higher incorporation probability at the side facets and a higher desorption probability at the top facet (since the crystal height decreases). With high sticking and dissociation probabilities the atoms may alter freely between physisorbed states and crystal bound states. Formation of dislocations, point-defects, vacancies and interstitials usually results in a weaker bonding to the crystal and smaller decrease in free energy of the system than the positioning on a “perfect lattice site”. Since the atoms can move freely between crystal-bound states, the atoms will typically end up at the positions with higher binding energy, and there will thus be a barrier to form a defect or dislocation, as compared to bonding at a “perfect site”. 3. The physisorbed atoms are preferably column-III atoms, most common species being Gallium, Indium, and Aluminium. The natural state for these materials at the conditions used is liquid form (Room pressure melting T: Ga 30° C.; In 157° C.; Al 660° C., all having boiling Ts above 2000° C.). Their vapor pressures are all low, below 1 pascal at 1000° C., explaining the low loss of material through evaporation, although some evaporation-loss will be expected. 4. The physisorbed column III atoms can have rather high diffusion rates and diffusion lengths on the order of 1 μm for Ga and 10 μm for In. A good physical description is the physisorbed atoms forming a two-dimensional cloud on the surface which will retain a constant concentration within the limits of diffusion lengths which in various embodiment is larger than the dimensions of the template structures. The cloud is supplied by dissociation of column III atoms from the crystal lattice and the reformation rate will be given by the relative differences in atomic dissociation rate and sticking rate to the respective facets. As long as the reformation-rate is sufficient low for the surface-diffusive state of column-III material to retain a relatively constant, conformal concentration of column-III material and the dimensions of structure is of similar, or less, length than the diffusion-length, then the supply of III-material will not be diffusion-limited but crystal incorporation is only governed by the activation energy of the crystal binding. This is what usually is referred to equilibrium conditions. 5. In a preferred embodiment, the background flow of NH3will be sufficiently high when it provides a supply of nitrogen, e.g. through pyrolysis of NH3, which is sufficient to provide a reservoir of nitrogen for III-material atoms to combine with during the reformation, at which a substantially planar upper surface is formed on a template facet. Pure nitrogen, N2, is inert at the used temperatures but the moderate activation energy for pyrolysis of NH3supplies us with enough atomic nitrogen to allow us to work with a phase transition touching on the right end side of the diagram inFIG.9C. However, nitrogen sources with even lower cracking temperatures would allow for reformation at lower temperatures and possibly better control over incorporation of crystal nitrogen vacancies. As noted, the planar upper surface will be formed and increased by redistribution of column III material, e.g. Ga or In, caused by favored growth on other template facets. At such a supply level, the nitrogen supply will not be diffusion limited, thereby fulfilling the condition for equilibrium growth with regards to the column V-element. Increasing the flow above this level may inhibit surface diffusion of column-III material productive flow of NH3. It's more likely that atomic nitrogen supply is limited by low pyrolysis-rate of NH3. Therefore the reformation step can be a very good candidate for use of alternative nitrogen sources where more efficient pyrolysis can be achieved. There are several such sources, examples being hydrazine, methylated hydrazine, such as dimethyl hydrazine, tertiarybutylhydrazine, tertiarybutylamine and also nitrogen-plasma, although reactivity of nitrogen radicals could decrease diffusion lengths appreciably. Although using a gas phase environment, crystal reformation stands in closer relation to the original liquid phase epitaxy methods that have been the centennial state of the art of high-purity bulk-grown semiconductor wafers. The thermodynamics involved also suggest that the conditions for reformation can be made uniquely preservative, allowing for minimal introduction of new dislocations during the coalescence. Being a new epitaxial regime, this will, as is the case for all new epitaxy methods, require further understanding of the physics involved in order to avoid introduction of new crystal defects. The approach, detailed herein, relies on a combination of epitaxial growth, low temperature optical characterization and the implementation of a physical growth-model. The nanostructures proposed herein are preferably all based on GaN nanowire seeds, or pyramidal seeds but other compositions of nitride material, including In and Ga can be used. The suggested embodiments are different, mainly due to specific challenges in context of materials and structures grown. Growing high Al composition AlGaN on GaN or high In-composition InGaN on GaN introduce crystal lattice mismatch, therefore the GaN seeds and templates are kept small in size to more easily accommodate strain without introducing new misfit dislocations. It may be even better but more challenging to incorporate In or Al, already during nanowire growth. Also, it may be preferable to use an AlGaN NW or grow and reform an AlGaN template directly. This is currently challenging due to the low diffusion-length of Al atoms but maybe preferably long term when such working conditions can be developed. With that said we should distinguish practical differences between GaN, InGaN and AlGaN methodology from fundamental preferences. All embodiments described may work may work for any combination of nitride material, as ternary nitride NW growth and reformation are further developed. A great advantage is the elimination of substrate dislocations through the nanowire or seed growth, giving fully dislocation-free platelets. This gives a second similarity to the Czochralski process, since it generates high quality crystals not only due to the well-controlled equilibrium-proximity, but also since it generates its own dislocation free seed. The reformation of whole arrays of nanostructures, such as nanowire-based structures, provides additional structural advantages which will now be discussed. Nanowire-based structures provide vertical m-planes, [10-10]. These planes provide surfaces for efficient lateral coalescence of material rearranged from the top of the nanowire structures. As previously outlined, it has been noted that physisorbed column III atoms may form a two-dimensional cloud on the surface, when the nanowire-based structure is subjected to an elevated temperature in a Nitrogen-rich environment as exemplified, which cloud will retain a constant concentration within the limits of diffusion lengths of the physisorbed atoms. This may result in reformation, at which a C plane, directed upwards from the nanowire structures, tends to increase while III-nitride material instead grows on the m-planes. In various embodiments the coalesced layer will thus be formed by formation of material in between the nanowire structures and, depending on process parameters such as temperature, and chosen length and spacing between the nanowire structures, the reformation will form a thin coalesced layer. More specifically, the reformation will cause growth between the nanowire structures adjacent upper portions of the nanowire structures. The result will be a coalesced layer which is thinner than the remaining length of the nanowire structures, leaving an appreciable lower part of the nanostructures un-coalesced. An example associated with this embodiment will now be described with reference toFIGS.10and11. FIG.10schematically illustrates method step of the production of a III-nitride semiconductor device, corresponding to the process described with reference toFIG.1. InFIG.10Aa base substrate101of e.g. sapphire is provided with one or more buffer layers102of e.g. GaN. Together, the layers101and102form a substrate, with a substrate surface1021. InFIG.10Ba mask layer103of e.g. SiNxhas been formed on top of the substrate, which mask layer comprises apertures or holes104. The holes may be very narrow, e.g. with a diameter of 50-200 nm, or e.g. 60-100 nm. The pitch between the holes104may e.g. be in the order of 200-2000 nm, e.g. 400-1000 nm, and is selected dependent on inter alia the electronic devices to be formed on the templates which are to be created on the substrate, and may also depend on the material of the III-nitride. FIG.10Cillustrates how nanowires106have been grown on the substrate surface1021of the buffer layer102through the holes104, e.g. by CVD or VPE in a nanowire growth step, wherein a nitrogen source flow and a metal-organic source flow are present. In one embodiment, the nanowires106comprise GaN. FIG.10Dillustrates the result of a volume growth step to provide a volume element, carried out after nanowire growth, as previously discussed herein. In the drawings, a different pattern is indicated for the nanowires106than the volume element107, but is should be noted that this only serves the purpose of clearly showing the different elements. The nanowires106and the volume element107may be provided in the same material, or different materials, as previously outlined. For the embodiment at hand, the volume growth step is optional, but may be advantageous. As a result of the processes ending atFIG.10C or10D, a nanowire structure1010is formed, which comprises a nanowire106and optionally a volume element107provided onto the nanowire106. It is a noted advantage that the nanowire structures are close to each other, with a pitch and width that results in a spacing between the nanowire structures which is substantially smaller than the length of the nanowire structures1010. However, growing relatively narrow nanowires106will increase the positive effect of minimizing threading dislocations, which means that it may be more advantageous to provide a volume element107onto the nanowires106may be more beneficial than growing thicker nanowires106. In one embodiment, the nanowire structures1010are grown to have a height which is at least 3 times a width of said spacing. In another embodiment, the nanowire structures are epitaxially grown to have a height which is at least 4, 5 or 6 times a width of said spacing. FIG.11illustrates a coalesced device formed after a planarizing step, carried out on a device including nanowire structures1010as shown in e.g.FIG.10CorFIG.10D. By carrying out the step of reformation on extended nanowire structures1010, with a suitably small distance between each other compared to the length of the nanowire structures1010, coalescence will appear at an upper part1012of the nanowire structures1010to form a coherent planar layer1020, having an upper first surface1022, and a backside surface1023. As noted, the growth of the layer1020is carried out at an elevated temperature in a nitrogen-rich environment without, or substantially without, providing further column III material. Instead, due to distinctive different surface energies of the crystal planes, column III atoms are released from primarily the top portions of the nanowire structures1010, so as to form and increase a C plane. Under suitable process parameters, as exemplified, such released column III material will attain a physisorbed and will further crystallize with nitrogen atoms to form a column III-nitride layer1016on the vertical M planes. This reformation will subsequently lead to coalescing of the M planes of adjacent nanowire structures1010to form the coherent layer1020. Due at least in part to the larger length of the nanowire structures1010than the distance between the nanowire structures1010, as given by the pitch and width of the nanowire structures1010, coalescence into a coherent layer1020will take place primarily or only at an upper part1012of the nanowire structures1010. A lower part1014of the nanostructures may thus remain un-coalesced, and free of solid material, or at least not occupied by material redistributed by coalescence from the nanowire structures1010. Since column III material grown1016on the M planes at coalescence is taken from the top of the nanowire structures1010, the resulting height of the nanowire structure is smaller after reformation. The coalesced layer1020will hence be formed by formation of material in between the nanowire structures1010and forms a thin layer1020. The depth of the coalescence1016, which basically defines the thickness of the coalesced layer1020, depends inter alia on chosen length of and spacing between the nanowire structures1010. In various embodiments the coalesced layer1020may have a depth between 100 nm and 500 nm, but dependent on dimensions and process parameters this may be decreased to a range between 10 and 100 nm, leaving the lower part1014of the nanostructures un-coalesced. In various embodiments the coalesced portion1016may be in the range of half the resulting length of the nanowire structures1010, such that the upper portion1012is between 20-70% of the resulting length of the nanowire structures1010after coalescence. As discussed earlier, the reformation method provides better conditions for formation of a continuous layer with low generation of dislocations at the coalescing interfaces. In addition, reformation allows a thinner continuous layer to be realized than the nanostructures being epitaxial overgrown, through ELO, since planarization through ELO must be achieved by adding material on pyramidal and lateral surfaces of the nanostructures. It's also easy to see that similar nanostructures grown without a nanowire, mainly terminated by pyramidal −s-planes and c-planes, lack the prolonged vertical m-plane facets, enabling efficient lateral reformation. FIG.12shows an embodiment in which a subsequent layer1030is provided on top of the planarized and coalesced layer1020. This layer1030may serve to provide a c-plane surface repair growth if required, or simply to provide thickening of the coalesced layer1020. This step may be performed at a lower temperature than the planarizing step. In various embodiments, the surface repair growth may be performed by providing a supply of column III material, preferably the same column III material as in the planarized second III nitride material, and may result in additional layers of pyramidal growth. In preferred embodiment, the repair layer thus created may only include one or a few atom layers, such that there will be no substantial decrease of the planarized template surface. Further layers may be grown on top of a repair layer. Subsequent steps may include forming a device, such as an electronic component, in or on the planarized and coalesced plurality of base elements, on top of the subsequent layer1030, e.g. by further epitaxial growth. FIG.13Ashows an embodiment provided by Flip-chip technology, in which the epitaxial stack is separated from the base substrate layer101, while leaving layers from the growth-substrate102, such as a GaN buffer layer. from the growth-substrate102the stack may also. FIG.13Bshows another embodiment provided by Flip-chip technology, in which the epitaxial stack is entirely separated from the substrate101,102, and also the mask layer103. FIG.14illustrates a beneficial effect rendered by the embodiments described with reference particularly toFIGS.10-13. As already noted, by growth from mask holes104, which represent a very small portion of the substrate surface, a large majority of any dislocations, such as threading dislocations1400illustrated in the drawing, in the substrate III-nitride102are filtered out by means of the mask layer103. In addition, it has been noted that threading dislocations close to the edge of a hole104tend to bend off towards one side of the grown nanowire106, or to the side edge of the mask hole104. An explanation for this may be that strain generated by threading dislocations in the grown material tend to be released by growth of the nanowires106, since the material in the nanowire106is substantially free to relax in three dimensions, as compared to the III-nitride material in the planar grown buffer layer. Both a thicker mask layer and longer nanowires may therefore provide an advantageous suppression or elimination of threading dislocations. More particularly, coalescing the nanowire structures1010at only an upper part, leaving a lower part of the nanowire structures1010separated, further minimizes the risk for threading dislocations to appear in the resulting coalesced layer1020, and hence in any further grown layers1030. The embodiments outlined with reference toFIGS.10-14may be provided with features of production and structure according to any of the other embodiments outlined herein, unless contradictory. As an example, devices with two or more separate coalesced surfaces, as described with reference toFIG.7and b, may also be generated by means of coalesced layers as indicated inFIG.11. Various embodiment of a device as shown inFIGS.11-14may be provided by means of a mask103of a spacing of e.g. 150-1000 nm, such as 700 nm, between mask holes104with an aperture of 50-300 nm, where larger apertures may be used with larger spacing. such as 200 nm. The nanowires106may be grown on a III-nitride buffer layer102, such as GaN. Nanowires106may be grown to a height of e.g. 400-1000 nm, or even several μm. A nanowire structure1010may be provided with a narrow spacing, e.g. in the range of 50-200 nm, as determined by the aperture pitch and the width of the nanowire structures1010. This may be obtained by growing nanowires106very close to each other. In another embodiment, nanowires106are grown with a substantially longer pitch, and are subsequently widened in a subsequent epitaxial growth step to be provided with a volume element, as exemplified inFIG.10D. Where the spacing is shorter than the height of the nanowire structures, the tendency to form a thin coalesced layer1020may increase. Dimensions and process parameters may be configured dependent on e.g. desired thickness of the coalesced layer1020, or the size of the uncoalesced portion104. In one exemplary embodiment, a dielectric mask103with a pitch of 700 nm between holes104with an aperture of 200 nm is provided on a GaN buffer layer102. Nanowires106are epitaxially grown through the mask holes104, and are subsequently epitaxially provided with a volume element107, to a height and width of the nanowire structures in the range of 600 nm. The spacing between adjacent nanowire structures1010are thus in the order of about 100 nm, which means that the height is in the order of 5 times the size of the spacing. A reformation step carried out without or substantially without addition of Ga atoms, as described, results in redisposition of Ga atoms from primarily S planes at the top of the nanowire structures1010onto M planes, at an upper part1012of the nanowire structures, and may result in adjoining106of adjacent nanowire structures1010into a coalesced coherent layer1020, with a thickness of 200-400 nm, leaving up to 300 nm or more of uncoalesced lower parts of the nanowire structures1010. As discussed earlier, the reformation method provides better conditions for formation of a continuous layer with low generation of dislocations at the coalescing interfaces. In addition, reformation allows a thinner continuous layer to be realized than the nanostructures being epitaxial overgrown, through ELO, since planarization through ELO must be achieved by adding material on pyramidal and lateral surfaces of the nanostructures. It's also easy to see that similar nanostructures grown without a nanowire, mainly terminated by pyramidal s-planes and c-planes lack the prolonged vertical m-plane facets, which enable efficient lateral reformation. In various embodiments a substrate has a growth surface, such as provided by a planar GaN buffer-layer on Si, SiC, or Sapphire substrate, and a dielectric layer deposited on the growth-surface. Through an array of apertures in the dielectric layer, III-N nanowire structures are monolithically connected to the growth substrate by epitaxial growth. Upper parts of the nanostructures are laterally coalesced to form an appreciably continuous, planar layer of a III-N semiconductor crystal, in level with the upper ends of the NW cores. Subsequent planar layers may be epitaxial grown on the reformed layer. Threading dislocations from the growth substrate or threading dislocations generated by the epitaxial hetero-interface formed between the III-N nanostructure and the growth substrate, are terminated at the interface between the nanostructure and the dielectric layer, or at a lower, un-coalesced part of the nanostructures. Other III-nitride semiconductors share the challenges of equilibrium growth of wafer material with GaN. Wafer fabrication of these materials is further challenged by a wide variation of crystal lattice dimensions, non-overlapping windows of thermal stability and material solubility. However, the realization of semiconductor growth-wafers of AlGaN, InGaN, AlInGaN, InN, and AlN of high crystal quality is highly attractive, for realization of more energy efficient and higher performance components and circuits in several areas of applications, some of them being of RF and power electronics, UV-LEDs, red/green LEDs. The examples below focus on AlGaN wafer fabrication, a material highly relevant for realizing efficient UV-LEDs and high voltage power devices. Various embodiments, as exemplified e.g. with reference toFIGS.10-14, work well to illustrate certain advantages, achieved through improved mechanisms for relaxation of crystal strain and eliminating parts of the strain that is otherwise built up in conventional planar semiconductor growth and, which, inevitably results in plastic deformation of the crystal through dislocation-formation when a critical layer thickness is reached. The generic nature of the invention makes it possible to utilize the described methodology for other industrially relevant mismatched semiconductor systems, such as generic III-V semiconductors grown on Si, for integration of optical and high speed functionality with Si CMOS, but the experimental findings behind this invention have been made in work with III-nitride material and is, correspondingly, as such described: III-N substrates (and III-V substrates) of different choice of composition, such as the binary, ternary and quaternary nitrides, given by the chemical formulas AlxGa1-xN, InzGa1-zN, where 0≤x≤1 and 0≤y≤1, and AlxInyGa1-x-yN, where 0≤x≤1, 0≤y≤1 and 0≤1−x−y≤1. In table 1, crystal properties of some nitride semiconductors and available growth-wafers are given. There are no obvious matches between the materials, also in-between the nitride semiconductors the heterostructure growth will result in plastic deformation, unless thin layers and moderate composition-changes are used. TABLE 1LatticeThermal expansionLatticeLatticemismatchcoefficientconstantconstantto(aa, ×10 −Material(c, Å)(a, Å)GaN (%)6K−1)GaN5.183.190%5.59AlN4.983.11−3%4.15Al0.2Ga0.8N5.143.174−1%5.302InN5.693.5311%?Si5.43 (cubic)17%2.56Al2O3−16%7.5(Sapphire)SiC—6H3.07−3%4.2 We have found that the structure, comprising a reformed planar layer monolithically connected by an array of pillars to a growth-substrate, such as exemplified by the embodiments ofFIGS.11-14, allow for a freedom of strain accommodation, as shown inFIG.15. Table 2 provides data associated with the diagrams ofFIG.15. TABLE 2peak 1peak 2acacpeak 1FWHMFWHM(c-plane)(c-plane)Descriptionθ (Deg)(arcsec)peak 2(arcsec)peak 1peak 2NW + reformation17.2224417.345.2045.169NW + reformation +17.24258.617.333515.725.1985.1711 μm top layerNW + reformation +17.1633717.282485.2225.1864 μm top layer InFIG.15, the diagram shows x-ray diffraction measurements of three different samples fabricated on growth substrates comprising an approximately 4 μm thick planar GaN buffer-layer102on a 600 μm thick sapphire wafer101, similar to what was described with reference toFIGS.1and10. All samples include a planar coherent layer1020, coalesced from nanowire structures at upper ends, spaced from a growth substrate surface1021similar to the examples of e.g.FIGS.11and12, i.e. where bottom ends of the nanowire structures adjacent to the growth substrate101are preferably uncoalesced and thus spaced apart. The three samples differ in that sample A, i.e. the first row in Table 2, comprise reformed nanowires to form a reformed or coalesced layer1020, but without any additionally grown layers1030. The reformed layer1020is approximately 0.3 μm thick. Sample B, corresponding to the second row in Table 2, has an additional 1 μm thick planar GaN layer1030epitaxially grown on the structure of sample A, while sample C, corresponding to the third row in Table 2, has an 4 μm thick planar GaN layer1030grown on the structure of sample A. The diagram ofFIG.15shows the (0002) diffraction peaks in the regime of the GaN crystal diffraction peak. A fully relaxed GaN crystal, at room temperature, corresponds to a diffraction angle of 17.28°. The planar GaN buffer layer102on the sapphire wafer101(peak 1, i.e. the dominant peak to the left in the respective curve) dominates the spectra of sample A and B, while staying fairly constant in position and linewidth, at 17.22-17.24° and 2.48-2.59 nm. The slight deviation from unstrained GaN (17.28°) is expected; a lower angle corresponds to larger lattice constant and the lattice mismatch between GaN and the sapphire substrate101which results in tensile strain of the GaN buffer layer102. In sample C, the GaN buffer layer102peak (peak1) has shifted appreciably towards a larger lattice constant, as evidenced to the peak 1 shifted to 17.16°, which means a larger lattice constant. Also, the linewidth has increased, indicating a non-uniform strain field, or bow in the buffer layer102. The reason behind the additional tensile strain in the GaN buffer layer102in sample C is revealed by peak 2 (i.e. the rightmost peak or shoulder in the respective curve), which origins from the combined reformed layer1020and additional planar, epitaxial, layers1030grown on top of the reformed layer1020(sample B: 1 μm GaN and sample C; 4 μm GaN). Samples A and B exhibit the peak 2 as a shoulder around 17.33-17.34°, indicating a thin compressed GaN layer. When we increase the thickness of the epitaxially grown GaN layer1030to 4 μm, comparable to the GaN buffer layer102in the growth substrate, the diffraction peak 2 of 17.28° shows the top layer, meaning the combined coalesced coherent layer1020and additionally grown layer1030. The location of this diffraction peak 2 at or close to 17.28° indicates that the combined layers1020and1030are essentially relaxed, unstrained. In the right columns of Table 2, related toFIG.15, the XRD measurements are converted to lattice spacing (lattice constant=ac). These values show that the difference in lattice spacing between the GaN buffer layer102and the GaN top layer1020and1030remains just below ˜0.7% for the three samples, while GaN top layer lattice goes from ˜0.35% to ˜0% compression when increasing the layer thickness. Quite surprisingly, the lattice relaxation of the top layer seems to be accommodated by the introduction of a corresponding level of tensile strain in the already strained GaN buffer layer102, going from ˜0.35% to ˜0.7% expansion. This not only shows that the structure can accommodate a lattice mismatch of at least 0.7% but also that the strain (and corresponding likelihood of plastic deformation) is distributed downwards, into the growth substrate101,102, allowing the top-layer1020,1030to relax to a high degree. Furthermore, it is easy to accommodate for the 0.7% lattice mismatch between the top layer and the growth substrate GaN buffer layer by incorporating Al into the top layer. Using Vegard's law and knowing that AlN has a 3% lattice mismatch to GaN we approximate a 0.7% lattice mismatch to correspond to 23% of Al. An Al23Ga77N top layer1030would allow the crystal lattice of the GaN buffer layer102to approach the nominal lattice spacing or constant of fully relaxed GaN, eliminating internal strain between the top layer and the buffer layer. And, even further, we have seen that the reformed structure can accommodate at least 0.7% lattice mismatch between the growth substrate (GaN buffer layer102) and the top planar layer1030grown on the reformed structure1020. It's reasonable to assume that the sign of the strain plays little role and that we can allow the introduction of an additional lattice mismatch of 0.7% from the relaxed structure comprising an Al23Ga77N top layer1030and a GaN buffer layer102. Using Vegard's law again, we aim at a 1.4% lattice mismatch as compared to a GaN top layer, giving that we can expect to be able to grow AlGaN with at least 47% Al without introduction of misfit dislocations in the top layer1030. The nitride semiconductors are typically wurtzite crystal structure and are anisotropic with different lateral constant (aa) and vertical lattice constant (ac). The lattice spacings extracted from the XRD measurements inFIG.15are in the vertical c-direction (ac). It would be prudent to corroborate the above findings and argumentation. To do this we go back to the top GaN layer1020,1030and the GaN buffer layer102, in order to understand how exactly a crystal mismatch between two layers of identical material is introduced. This is not obvious, in light of the whole reformed structure and the two GaN layers on top1020,1030and bottom102forms a singular monolithically grown crystal plainly composed of GaN/GaN homojunctions. A mechanism that is often forgotten in GaN layer on layer growth, is thermal expansion. This is understandable, since it mainly provides a challenge in the nucleation and initial growth for fabrication of GaN buffer layers on Si, and to much less extent on Sapphire and SiC, in order to avoid cracks and control thermally induced bow of the substrate101. Thermal mismatch is fairly irrelevant in layer on layer growth on existing GaN buffer layers102. In the reformation process, i.e. during coalescence to form a coherent layer1020from a nanowire structure, thermal mismatch plays a unique role, and opportunity, distinctly different from to the challenges it provides in buffer layer102growth. The basis for this is that coalescence by reformation is a fully lateral process. The reformation and growth temperatures of GaN are typically 1000° C. above room temperature (RT). The same temperature may be applied during coalescence to form layer1020and growing the growth layer1030, but with different flow of source material. In an alternative embodiment, a first elevated temperature applied during coalescence, or reformation, to form layer1020may be higher than a second elevated temperature when growing the growth layer1030. Since the sapphire substrate101thickness used inFIG.15is 600 μm, while the GaN buffer layer102on top of the sapphire substrate101, which forms the growth substrate surface, is around 4 μm, we can assume the combined substrate101,102to expand according to the sapphire thermal expansion coefficients. In Table 3, the thermal expansion along the GaN lateral direction is given. The embodiments outlined herein may relate to the fabrication of a semiconductor device having a planar III-N semiconductor layer, including coalescence at an elevated temperature T. Coalescence is preferably carried out above the sublimation temperature of the nanostructure1010III-N material, which may vary dependent on pressure. The temperature T may e.g. be in the range of 700-1500° C., or 800-1200° C., or 900-1100° C. The temperature T is elevated above room temperature RT, which may be in the range of 18-22° C., and exemplified as 21° C. in the example in Table 3. Thermal expansion affects the amount the distance between the mask apertures104will change when heating up the sample, and consequently the spacing between the NWs106. Specifically, since the substrate comprises a comparatively thin buffer layer102, of a III-N material, provided on a comparatively thick wafer of a different material, the thermal expansion of the wafer101will dominate the overall thermal expansion of the substrate. The buffer layer102may have a thickness in the order of 0.1-5% of the thickness of the wafer101, or 0.5-2%, in various embodiments. In at least such embodiments, the overall thermal expansion coefficient of the substrate will substantially be the same as for the wafer material. Hence, the thermal expansion of the wafer101, from RT to T, affects built-in crystal strain in the buffer layer102and causes an increase in said crystal lattice spacing at the growth surface, as caused by the heating, to deviate from a corresponding increase of a relaxed crystal of the buffer material. Since the GaN lateral expansion coefficient is lower than Sapphire, it will require a higher number of GaN monolayers, or periods of the atomic lattice, in the lateral direction to close the gap by coalescence between the nanowires106,107at growth temperature than at room temperature. Hence, the number of lattice cells spanning the distance between adjacent apertures104are different at the growth surface compared to the number of lattice cells spanning the corresponding distance at the coalesced planar layer1020. When the sample is cooled down, the substrate, and most importantly the sapphire material of the wafer101, will shrink and the lattice of the reformed layer1020will be laterally compressed with respect to the sapphire with a change in lattice spacing of approximately 0.3% (0.28%). TABLE 3substratespacingspacingGaN expansionexpansionatatΔa/afrom 294RT1273Kfrom 1273K toSubstrate typeto 1273K(nm)(nm)294KGaN on sapphire0.89%10001008.90890.28%GaN on silicon0.44%10001004.4251−0.16%GaN on SiC0.59%10001005.9091−0.10% This shows that, with the coalescing reformation process, the choice of growth substrate101, in particular the thermal expansion coefficients, matters profoundly for growth of layers with different lattice size. With AlGaN, which is a smaller crystal than the GaN buffer layer102, a substrate101like sapphire with a larger expansion coefficient than the intended AlGaN top layer1030allows growth of layers that are highly mismatched to said growth substrate surface material. If we want to grow InGaN as a top layer1030, where the lattice size increases with increased In concentration, a substrate101like Si is preferable, since it has a much lower expansion coefficient than GaN and InGaN, meaning that at high temperature a smaller amount of periods of the atomic lattice in the lateral direction will fill up the space between the nanowires than at RT, resulting in a strain-accommodated lateral expansion of the crystal lattice in the top layer1030at RT with respect to the growth surface material, also referred to herein as the buffer layer material, i.e. the uppermost layer of the buffer layer102. Consequently, the embodiments above may comprise a continuous or coherent layer1020,1030of a crystal lattice size that is larger than the crystal lattice size of a layer102of the growth substrate101,102comprising the growth surface1021, and where the growth substrate101,102has an overall lower expansion coefficient than the continuous layer1020,1030, such as a GaN buffer layer on Si or SiC. The embodiments may also comprise a continuous or coherent layer1020,1030of a crystal lattice size that is smaller than the crystal lattice size of a layer102of the growth substrate101,102comprising the growth surface1021, and where the growth substrate101,102has an overall higher expansion coefficient than the continuous layer1020, such as a GaN buffer layer on sapphire. In the above embodiments the transition to the composition of the top continuous layer1030can be made by growing a layer1030of the intended composition on the reformed coalesced layer1020. When larger compositional changes and changes in lattice spacing are intended, it may be advantageous to use the radial growth step to grow a radial layer107of the intended composition on the nanowires106, or a radial layer107approaching the intended composition, so that already the coalesced, reformed layer1020approaches the intended lattice spacing. It's also possible to start the compositional transition at the NW106growth-step. There are several less common alternative substrate101materials that have been used for GaN buffer layer102growth. Two examples which can enhance the required difference in thermal expansion coefficient are NdGaO3with a lateral thermal expansion coefficient of 11.9*10-6/K and ZnO, with a lateral thermal expansion coefficient of 2.9*10-6/K. Various nanostructures and processes for preparing III-nitride semiconductor devices have been provided above, which devices are suitable for further processing to carry or incorporate semiconductor electronic devices, such as Schottky diode, p-n diode, MOSFET, JFET, HEMT etc. The planar substrate layer obtained by coalescing of individual growths from mask openings is substantially fully relaxed, as compared to a traditionally grown layer on a mismatched substrate, while microscopic and macroscopic strain may be induced by other environmental conditions, such as differences in the thermal expansion properties and high fabrication temperature, interface and surface energies and dopants or impurities. Further details on embodiments for fabrication of various such electronic devices can be found e.g. in the referenced patent application. | 75,233 |
11862460 | MODES FOR CARRYING OUT THE INVENTION In the following, some embodiments and features of a SiC structure, a method of producing the same, and a semiconductor device of the present disclosure will be described. SiC Laminate Production Method According to First Embodiment In the implementation of a method of producing a SiC laminate according to a first embodiment of the present invention, a single-crystal hexagonal SiC wafer is prepared as a substrate. As to single-crystal SiC wafers, 4H-SiC or 6H-SiC wafers are commercially available. In this embodiment, a 4H-SiC wafer with a band gap (Eg) of 3.2 eV, which is suitable for manufacturing high-voltage power semiconductor devices, is used. In carrying out the method, there is no restriction on the resistivity of the 4H-SiC wafer. Nevertheless, when the SiC laminate is used as a substrate of a power MOSFET, it is desirable to use a wafer doped with donor impurities (nitrogen, phosphorus, etc.) at a high concentration and exhibiting a resistivity of 20 mΩ·cm or less to reduce the specific on-resistance (Ron). It is also desirable that the surface of the 4H-SiC wafer be substantially parallel to the (0001) plane having Si polarity. However, if microfabrication is difficult in the off process or the seed process, for the reasons described later, it is desirable to use a SiC wafer (vicinal SiC wafer) the surface of which is inclined in a specific direction selected from the <11-20> or <1-100> directions at an angle in the range of 0.5 to 8 degrees with respect to a close-packed plane. (Off Process, Seed Process) This embodiment describes a method of producing a SiC laminate having a main surface in which a lattice-matched (coherent) heterointerface linearly traverses a 4H-SiC wafer from one end to the other, and 3C-SiC and 4H-SiC surfaces alternate in stripes. In order to form this structure, as illustrated in the cross-sectional view ofFIG.12(b), a plurality of trenches (TR) each having a positively inclined plane (1if) and a negatively inclined plane (1ib) as sidewalls are arranged in parallel across the surface of the 4H-SiC wafer. Such methods as machining, chemical etching, and laser processing can be used to form the trenches (TR); however, considering the reproducibility of the shape of the inclined planes and the degree of freedom of arrangement, a processing method that uses photolithography and dry etching is most desirable and simple. In this process, first, as illustrated inFIG.12(a), a plurality of linear photoresist (LPR) patterns are formed on the surface of the 4H-SiC wafer. The cross-section of each LPR pattern is T-shaped with a flange having a width of Wh as it is necessary to form an inclined plane in a dry etching process (described later). A method for forming a T-shaped LPR pattern is described in Patent Document 9 (JP 2000-214593 A) and the like, and therefore a detailed description thereof is omitted herein. However, it is to be noted that the thickness of the photoresist is 0.5 μm or more and 5 μm or less, more preferably 0.7 μm or more and 2 μm or less. If the thickness of the photoresist is less than 0.5 μm, a portion that is to be a seed plane is partially etched in the dry etching process (described later) and loses its smoothness, which may result in multinucleation of 3C-SiC. When multinucleation occurs, a twin boundary (TB) is formed in a 3C-SiC layer. On the other hand, if the thickness of the photoresist is more than 5 μm, the accuracy of the line width and flange shape of the LPR patterns decreases. As a result, the boundary between a 3C-SiC surface and a 4H-SiC surface formed by a lateral epitaxy process (described later) meanders, generating an incoherent interface. To achieve the effects of the present invention, the LPR patterns need to be linearly continuous from one end to the other end of the wafer surface. In addition, the direction in which the LPR patterns extend (division direction), the spacing between adjacent LPR patterns (space width), and the minimum line width of the LPR patterns (line width) are important factors for achieving the effects of the present invention. Considering that a plane inclined in the [11-20] direction is used in general step-controlled epitaxy, it is desirable that the division direction be within 2 degrees with respect to the [1-100] direction, which is perpendicular to the [11-20] direction, and within 0.5 degrees for the best result. This is because the more the orthogonality of the division direction with respect to the inclination direction is compromised, the more discontinuities occur in the coherent heterointerface. Accordingly, all LPR patterns are positioned and processed so as to be parallel to the [1-100] direction. A second orientation flat formed on the periphery of a commercially available wafer can be used as a reference for positioning the LPR patterns. The line width is desirably 100 nm or less, more desirably 1 nm or less. If the line width is more than 100 nm, the width of a seed plane (1p) increases, which may cause multinucleation of two-dimensional nuclei (2e) of 3C-SiC due to the high degree of supersaturation, and a 3C-SiC layer (2) may contain a twin boundary (TB). Meanwhile, the space width is desirably 1 μm or more and 1 mm or less, and 10 μm or more and 500 μm or less for the best result. The reasons for this are as follows: A trench (TR) is formed at a location corresponding to the space width by dry etching (described later), and the side walls of the trench (TR) correspond to inclined planes (1if,1ib). If the space width is less than 1 μm, it is difficult to provide a sufficient height difference (d) and depression angle (θp) to the inclined planes formed by dry etching (described later), resulting in incomplete step-controlled epitaxy. On the other hand, when the space width is more than 1 mm, the area ratio of a 3C-SiC surface (2S) obtained by this method decreases relative to the area of the main surface (S), and the current capacity per unit area of a semiconductor device decreases. After forming the LPR patterns as described above, dry reactive ion etching (RIE) is performed to etch SiC exposed at a location corresponding to the space width, thereby forming a trench (TR). With this, a positively inclined plane (1if) and a negatively inclined plane (1ib) can be obtained as the sidewalls of the trench (TR). It is desirable to use an etching gas that contains fluorine such as SF6, NF3, BF3, and CF4to etch SiC by the RIE process. In particular, if CF4is used as the dry etching gas and mixed with O2such that the flow rate of O2is a quarter of that of CF4, the etching rate of SiC can be maximized. It is desirable to use a parallel-plate radio frequency (RF) etching system in carrying out the RIE process. In addition, the power input to the RF etching system is preferably 200 W or less, more desirably in the range of 75 W to 150 W, and the gas pressure is preferably 13.8 Pa or more, more desirably in the range of 30 Pa to 50 Pa. If the input power exceeds 200 W, plasma irradiation induces crystal defects on the surface of SiC crystal, which may result in incomplete step-controlled epitaxy in the lateral epitaxy process (described later). Meanwhile, if the input power is less than 75 W, the straight motion of ions is impaired, making it difficult to adjust the depression angle (θp) of the inclined planes. Similarly, if the gas pressure is below 13.8 Pa, the kinetic energy of the ions that form a plasma increases, and crystal defects are more likely to occur on the surface of SiC crystal. If the gas pressure is above 50 Pa, residues from etching may adhere to part of the inclined planes, which may also result in incomplete step-controlled epitaxy in the lateral epitaxy process (described later). The SiC surface exposed at an opening between adjacent LPR patterns is etched and removed by the above RIE process to a predetermined depth of 1 nm or more and 10 μm or less. When the etching depth is less than 1 nm, the step density exposed on the inclined planes (1if,1ib) becomes very small, resulting in incomplete step-controlled epitaxy in the lateral epitaxy process (described later). On the other hand, when the etching depth exceeds 10 μm, the LPR patterns are lost during the dry etching. This not only impairs the controllability of the depression angle (θp) but also decreases the smoothness of the seed plane (1p), and a twin boundary (TB) is formed in the 3C-SiC layer. In the RIE process of this embodiment, the etching depth changes around under the flange of each LPR pattern. Therefore, the depression angle (θp) of the inclined planes (1if,1ib) can be controlled by the width (Wh) of the flange of the LPR pattern and the depth of the trench (TR) (i.e., the height difference (d) of the inclined planes). Specifically, since the height difference (d) corresponds to the product of the width (Wh) and the tangent of the depression angle (θp), if the height difference (d) is adjusted in the range of 0.009 to 3.27 times the width (Wh) by changing the time of the RIE process, a depression angle (θp) of 0.5 to 73 degrees can be obtained. For example, by adjusting the time of the RIE process so that the width (Wh) is 0.5 μm and the height difference (d) is 35 nm, a depression angle (θp) of 4 degrees can be obtained. Furthermore, since different values can be selected for the width (Wh) in the positive inclination direction (If) and the negative inclination direction (Ib), the depression angle of the positively inclined plane and the depression angle of the negatively inclined plane can be arbitrarily changed. Note, however, that the depression angle (θp) of less than 0.5 degrees is not desirable because the step density exposed on the inclined planes becomes extremely low, and an increase in the degree of supersaturation causes multinucleation of 3C-SiC. Meanwhile, when the depression angle (θp) is 73 degrees or more, the substantial step interval becomes one molecule or less in size, and step-controlled epitaxy does not occur. Therefore, the depression angle (θp) is desirably within the range of 1 to 15 degrees. It is more desirable that the depression angle (θp) be in the range of 2 to 8 degrees to achieve epitaxial growth with excellent reproducibility. Incidentally, since the depression angle (θp) corresponds to the inclination angle (θ) where the coherent heterointerface and the main surface intersect, the optimum range of the inclination angle (θ) is determined by the depression angle (θp). After the desired shape of the inclined planes is obtained as described above, any residual photoresist on the surface of the 4H-SiC wafer is removed using an oxygen ashing system. The photoresist can be completely removed by treatment at 100 W for 15 minutes or more. In addition, sulfuric acid-hydrogen peroxide mixture (SPM) cleaning and rinsing with pure water are each performed for 5 minutes to completely remove metal impurities, dust, and the like from the surface of the 4H-SiC wafer. If this cleaning is insufficient, dust and impurities cause incomplete step-controlled epitaxy in the lateral epitaxy process, which increases the defect density in epitaxial films and decreases the smoothness of the coherent heterointerface. The off process and the seed process have been described in detail above. If it is difficult to achieve a line width of 100 nm or less, by using a vicinal wafer having a surface inclined from a CPP at an initial inclination angle (θf) of 0.5 to 8 degrees in the [11-20] direction, i.e., a specific direction of the inclined surface, a seed plane with a width of substantially less than 1 nm can be obtained. For example, the cross-sectional view ofFIG.13illustrates that a substantial seed plane is confined to the upper end of the negatively inclined plane (1ib) (where the CPP corresponds to the tangent line) as the wafer surface is inclined from the CPP in the positive inclination direction (If), and the ridge portion (1r) also functions as part of the positively inclined plane (1if). Additionally, the widths of terraces adjacent to both ends of the seed plane (1P) are asymmetrical, and the stabilization of the wider terrace is prioritized in a surface structure stabilization process (described later). As a result, the close-packed structure of the 3C-SiC surface (2S) is uniquely defined as either CCP1 or CCP2. Note that the depression angle of the inclined plane with respect to the ridge portion (1r) obtained in the above process needs to be 0.5 degrees or more than the initial inclination angle (θf) to obtain an effective negatively inclined plane (1ib). This is because otherwise the inclined plane would have a depression angle (θp) of less than 0.5 degrees or negative degrees with respect to the seed plane (1P). (Surface Structure Stabilization Process) Prior to the lateral epitaxy process (described later), it is desirable to stabilize the surface energy of the seed plane (1P) by a surface stabilization process as set forth in claim7of the present invention to uniformize the close-packed structure. Described below are treatment conditions for the surface structure stabilization process. The 4H-SiC wafer that has undergone the off process is placed in a hydrogen treatment vessel and exposed to a hydrogen gas atmosphere of 700 hPa to 1100 hPa. At this time, the purity of hydrogen gas is desirably 99.99% or higher, more desirably 99.9999% or higher. If the purity of hydrogen is less than 99.99%, residual oxygen and water vapor components oxidize and etch the surface of the 4H-SiC wafer, making step-controlled epitaxy difficult. Next, the temperature in the hydrogen treatment vessel is raised from 300° C. to 600° C. and maintained for 1 hour or more. The longer the temperature is maintained, the more the stabilization of the surface structure is ensured; however, the lower the productivity. In order to achieve both the productivity improvement and stabilization of the surface structure of the seed plane, the substrate temperature is desirably at 450° C. to 550° C., and the hydrogen pressure is desirably at 900 hPa to 1000 hPa. If the treatment temperature is above 550° C., or if the hydrogen pressure is less than 900 hPa, the SiC surface is etched with hydrogen and its smoothness is decreased. Meanwhile, if the hydrogen pressure is higher than 1000 hPa, the inside of the treatment vessel has a positive pressure with respect to the atmosphere, which is undesirable from a safety standpoint because of the risk of hydrogen gas leakage. (Nucleation Process, Lateral Epitaxy Process) After the off process or the surface structure stabilization process described above, step-controlled epitaxy is performed as the lateral epitaxy process. The lateral epitaxy process of this embodiment may employ a commercially available SiC epitaxial growth apparatus, and a combination of hydrocarbon gas and any one or more of silane-based gas, silane chloride-based gas, and organosilane-based gas can be used as the source gas. In general SiC epitaxial growth, a mixed gas of monosilane and propane, a mixed gas of dichlorosilane and acetylene, or a mixed gas of silicon tetrachloride and methane is used. In particular, when the embodiment is implemented by using a mixed gas of monosilane and propane, step-controlled epitaxy with excellent reproducibility is achieved. In this embodiment, epitaxial growth of SiC is performed as follows: the 4H-SiC wafer is placed on a graphite susceptor coated with SiC, which is then placed in a quartz reaction vessel, and the wafer is heated to a predetermined temperature by induction heating of the susceptor from outside the reaction vessel. The wafer is maintained at a constant temperature in the range of 1400° C. to 1700° C. during epitaxial growth, and thereby SiC single crystal is epitaxially grown. A wafer temperature of 1500° C. to 1650° C. is particularly desirable to obtain a high-quality single-crystal SiC layer. It is more desirable to maintain the wafer at a constant temperature of 1550° C. to 1650° C. to achieve step-controlled epitaxy realizing both the extension of a seed plane and two-dimensional nucleation of 3C-SiC on the surface of the seed plane. In the epitaxial growth, steps move at a growth rate of 171 μm/hour in both the positive inclination direction (If) and the negative inclination direction (Ib) by, for example, setting the temperature of the wafer to 1650° C., the flow rate of hydrogen to 5 slm, the flow rate of monosilane to 50 sccm, the flow rate of propane to 13 sccm, and the pressure in the reaction vessel to 300 hPa. As a result, when the depression angle (θp) is 4 degrees, epitaxial growth proceeds at a growth rate of 12 μm/hour in the [0001] direction. For adjusting the resistivity of the epitaxially grown layer, if one or more gases selected from N2, PH3, B2H5, trimethylaluminum (TMA), and AlCl3are mixed in the source gases in an arbitrary amount in the epitaxial growth process, the epitaxial layer of SiC can be doped with donor impurities (N, P) or acceptor impurities (B, Al). For example, in the case of forming a drift layer of a MOSFET with a breakdown voltage (Vb) of 600 V, 5 sccm of N2is mixed in the source gases and epitaxial growth is performed for 50 minutes. With this, it is possible to obtain an epitaxially grown layer of 10 μm thick with a donor concentration of 3×1015cm−3at room temperature. When the depression angle (θp) is 4 degrees, the 3C-SiC surface formed by this epitaxial growth has a width of 143 μm in the [11-20] direction. (Structure of SiC Laminate) Through the epitaxial growth process described above, it is possible to obtain a SiC laminate in which a coherent heterointerface of 4H-SiC and 3C-SiC is formed parallel to a close-packed plane (CPP). On the main surface of the SiC laminate, a segment of the coherent heterointerface is exposed as a straight line parallel to the [1-100] direction, and the 4H-SiC surface and the 3C-SiC surface are clearly demarcated. Furthermore, since the [1-10] direction of 3C-SiC coincides with the [1-100] direction of 4H-SiC, and their CPPs are parallel to one another, all {1-11} planes of 3C-SiC are perfectly matched to a combination of three-fold symmetry planes selected from the {0-33-4} planes of 4H-SiC. Thus, it is possible to produce a SiC laminate that does not contain a twin boundary with no scattering and trapping at the heterointerface. SiC Laminate Production Method According to Second Embodiment In the implementation of a method of producing a SiC laminate according to a second embodiment of the present invention, a single-crystal hexagonal SiC wafer is prepared as a substrate. As to single-crystal SiC wafers, 4H-SiC or 6H-SiC wafers are commercially available. In this embodiment, a 4H-SiC wafer with a band gap (Eg) of 3.2 eV, which is suitable for manufacturing high-voltage power semiconductor devices, is used. In carrying out the method, there is no restriction on the resistivity of the wafer. Nevertheless, when the SiC laminate is used as a substrate of a power MOSFET, it is desirable to use a wafer doped with donor impurities at a high concentration so that the resistivity is 20 mΩ·cm or less. It is also desirable that the surface of the 4H-SiC wafer be substantially parallel to the (0001) plane having Si polarity. However, if microfabrication is difficult in the off process or the seed process, it is desirable to use a SiC wafer (vicinal SiC wafer) the surface of which is inclined in a specific direction selected from the <11-20> or <1-100> directions at an angle in the range of 0.5 to 8 degrees with respect to a CPP. (Off Process, Seed Process) This embodiment describes a method of producing a SiC laminate in which the periphery of a 3C-SiC surface on the main surface is surrounded by a 4H-SiC surface via a coherent heterointerface. For this purpose, rotationally symmetric inclined planes are formed on the surface of a 4H-SiC wafer. In forming the inclined planes, first, a Si oxide film (OX) is formed on the surface of the 4H-SiC wafer. Thermal oxidation in oxygen and steam, chemical vapor deposition (CVD) using silane and oxygen as precursor gasses, and sputtering can be used to form the Si oxide film. In this embodiment, the Si oxide film (OX) is used as a protective film for forming an inclined plane, and therefore it is important that the film has a uniform film thickness distribution and a high density. Accordingly, it is most desirable to form the Si oxide film (OX) by thermal oxidation in an oxygen atmosphere containing water vapor. It is also desirable that the Si oxide film (OX) be formed to have a thickness of 1 μm or more. If the thickness of the Si oxide film is less than 1 μm, the Si oxide film (OX) is lost during a polishing process (described later), making it difficult to obtain a desired inclined plane. However, SiC has a lower oxidation rate than Si, and the thermal oxidation process takes longer as the thickness of the Si oxide film (OX) increases. In the case of forming a Si oxide film (OX) with a thickness exceeding 1 μm on a 4H-SiC wafer by thermal oxidation in a relatively short time, a Si layer with a thickness of 0.4 μm or more is deposited on the 4H-SiC wafer prior to the thermal oxidation. By this way, a Si oxide film (OX) that is about 2.5 times or more thicker than the deposited Si layer can be obtained within 3 hours. Next, as illustrated inFIG.14(a), a photoresist is applied to the 4H-SiC wafer coated with the Si oxide film (OX), and a plurality of circular photoresist (CPR) patterns are formed at regular intervals by using photolithography. The photolithography is performed in the same manner as in a general Si integrated circuit manufacturing process, and therefore a detailed description thereof is omitted herein. Note, however, that the CPR patterns desirably have a diameter of 100 nm or less. This is because the diameter of each CPR pattern corresponds to the width of a seed plane (1p) formed in the subsequent process, and if it exceeds 100 nm, the frequency of two-dimensional nucleation increases on the seed plane (1p). As a result, a 3C-SiC layer is more likely to contain a twin boundary (TB) due to multinucleation. In the SiC laminate of this embodiment, the minimum spacing (space width) between adjacent CPR patterns is important to determine the area ratio of the surface of a 3C-SiC layer and the surface of a 4H-SiC layer. In order to obtain a practical SiC laminate surface, the space width is desirably in the range of 100 nm to 1 mm. A sufficient 4H-SiC surface area cannot be secured if the spacing between CPR patterns is less than 100 nm because, in this embodiment, the space width corresponds to twice the length of an inclined plane formed in the subsequent process. On the other hand, if the spacing between CPR patterns is more than 1 mm, it becomes difficult to provide the inclined plane with a sufficient height difference relative to its length, making it difficult to ensure a depression angle (θp) of 0.5 degrees or more for the inclined plane. After forming the CPR patterns, the 4H-SiC wafer is immersed in a hydrofluoric acid (HF) solution with a concentration of 5% for 10 minutes to transfer the shape of the CPR patterns to the Si oxide film (OX). Then, the CPR patterns are removed using an oxygen ashing system as in the first embodiment of the SiC laminate production method to obtain a 4H-SiC surface partially covered with a circular oxide film as illustrated inFIG.14(b). Next, the surface of the 4H-SiC wafer is brought into contact with a polishing cloth impregnated with a diamond slurry having a pH of 5.5 or less to apply mechanical polishing thereto. The diamond slurry is continuously supplied to the polishing cloth at a flow rate of 400 cc or more per minute during the polishing. Preferably, the polishing cloth is attached to a flat turntable and the turntable is rotated at 30 rpm or higher. In addition, the pressure applied to the 4H-SiC wafer is adjusted so that the polishing rate is in the range of 0.2 μm/hour to 10 μm/hour. If the polishing rate exceeds 10 μm/hour, the surface smoothness of the inclined plane obtained by polishing is impaired. Meanwhile, if the polishing rate is less than 0.2 μm/hour, the machining of the inclined plane takes time, and sufficient productivity cannot be achieved. With the above polishing treatment, a dent is formed where the 4H-SiC surface is not covered with the Si oxide film (OX), and an inclined plane (1is) is obtained on the side surface of the dent. As a result, as illustrated in the plan view ofFIG.14(c), a truncated cone is formed with a portion covered with the Si oxide film (OX) as a ridge portion (1r). The depression angle (θp) of the inclined plane (1is) with respect to the ridge portion (1r) of the truncated cone is determined by the height difference (d) of the inclined plane and the spacing between adjacent CPR patterns. Therefore, a depression angle (θp) of 0.5 to 73 degrees can be achieved by precisely controlling the polishing time. Note that a depression angle (θp) of less than 0.5 degrees is not desirable because the step density exposed on the inclined plane becomes extremely low, and an increase in the degree of supersaturation causes multinucleation of 3C-SiC. Meanwhile, when the depression angle (θp) is more than 73 degrees, the substantial step interval becomes one molecule or less in size, and step-controlled epitaxy does not occur. The depression angle (θp) is desirably within the range of 1 to 15 degrees. It is further desirable that the depression angle (θp) be in the range of 2 to 8 degrees to achieve epitaxial growth with excellent reproducibility. Incidentally, since the depression angle (θp) corresponds to the inclination angle (θ) where the coherent heterointerface and the main surface intersect, the optimum range of the inclination angle (θ) is determined by the depression angle (θp). After the truncated cone is obtained in a desired shape, the 4H-SiC wafer is immersed in an HF solution with a concentration of 5% for 10 minutes to remove the Si oxide film (OX) on the top of the truncated cone. This provides a truncated cone-shaped 4H-SiC surface as illustrated in the plan view ofFIG.14(d)orFIG.8. Subsequently, SPM cleaning and rinsing with pure water are performed for 5 minutes or longer to remove dust and impurities from the surface. If this treatment is insufficient, it may cause incomplete step-controlled epitaxy (described later), resulting in the formation of a twin boundary (TB) in the 3C-SiC layer and an incoherent heterointerface. The details of the off process and the seed process have been described above. If it is difficult to obtain a ridge portion (1r) with a diameter of 100 nm or less, a seed plane (1P) with a width of substantially 1 nm or less can be obtained by using a vicinal wafer. The range of the initial inclination angle (θf) of the vicinal wafer and the reason for it have already been described above in the first embodiment of the SiC laminate production method. A substantial seed plane is confined to the end of the ridge portion (1r) (where the CPP corresponds to the tangent line) as the wafer surface is inclined in a specific direction, and the ridge portion (1r) functions as part of the inclined plane. In addition, the widths of terraces adjacent to both ends of the seed plane are asymmetrical, and the stabilization of the wider terrace is prioritized, promoting the effects of the surface structure stabilization process described below. Consequently, the close-packed structure of the surface of the 3C-SiC layer is uniquely defined as either CCP1 or CCP2. As a result, according to the embodiment, the 3C-SiC surface (2S) exposed on the main surface has a uniform shape. (Surface Structure Stabilization Process) After the off process described above, the surface structure stabilization process is performed in the same manner as in the first embodiment of the SiC laminate production method. This minimizes the surface energy of the seed plane (1p), and thereby the CCP structure can be uniquely defined. (Nucleation Process, Lateral Epitaxy Process) After the off process or the surface structure stabilization process described above, epitaxial growth is carried out as in the first embodiment of the SiC laminate production method. In the course of the epitaxial growth, the ridge portion (1r) epitaxially grows in the lateral direction, which extends the seed plane (1p). This extension of the seed plane increases the degree of supersaturation in the center of the seed plane, generating a two-dimensional nucleus (2e) of 3C-SiC. The generated two-dimensional nucleus (2e) of 3C-SiC forms a specific CCP structure reflecting the close-packed structure of the surface of the seed plane. The two-dimensional nucleus of 3C-SiC further grows laterally to form a new seed plane (2P), which extends the coherent heterointerface (3) and suppresses the formation of a twin boundary (TB) in the 3C-SiC layer (2). (Structure of SiC Laminate) The CCP structure of 3C-SiC mononucleated on the seed plane has side surfaces including {110}, {11-2} and {−1-12} planes. Under the epitaxial growth conditions of this embodiment, the epitaxial growth rate of 3C-SiC is higher in the <110> directions than in other crystal orientations. Therefore, as illustrated inFIG.14(e), the surface of the seed plane made of 3C-SiC has a triangular shape with sides parallel to the {11-2} planes. A layered structure of 4H-SiC is exposed on the inclined plane (1is) around the 3C-SiC surface (2S). Under the epitaxial growth conditions of the embodiment, the epitaxial growth rate of 4H-SiC is maximum in the <110> directions compared to other crystalline plane orientations of 4H-SiC. Accordingly, the inclined plane is a six-fold symmetry plane oriented in the {11-20} plane direction. Hence, the coherent heterointerface between the 3C-SiC layer and the 4H-SiC layer has a triangular segment (3S) exposed on the main surface, separating the 3C-SiC surface (2S) and the surrounding inclined plane (1is) made of 4H-SiC. In the manner as described above, it is possible to obtain a SiC laminate that is free from scattering and trapping of carriers at the interface and does not involve the formation of a twin boundary. [Embodiments of Power MOSFET and SBD] Described below are embodiments of a power MOSFET and an SBD using a SiC laminate produced by the SiC laminate production method according to the first and second embodiments. (Device Manufacturing Process) Using an n-type 4H-SiC substrate with a resistivity of 20 mΩ·cm or less, a SiC laminate having a 3C-SiC layer and a 4H-SiC layer is produced by the SiC laminate production method according to the first and second embodiments. Note that nitrogen doping is performed intentionally in the lateral epitaxy process to obtain an 8 μm thick epitaxially grown layer that contains nitrogen at a concentration of 1×1016/cm3as a drift layer. Next, aluminum ions are implanted so that the ions penetrate from the 3C-SiC layer (2) to the underlying 4H-SiC layer (1) to provide an acceptor-doped region (P-well) with a concentration of 3×1017/cm3as illustrated inFIG.15(structure according to the first embodiment of the SiC laminate production method) orFIG.16(structure according to the second embodiment of the SiC laminate production method). In addition, to reduce the source contact resistance, nitrogen ions and phosphorus ions are implanted into a portion around the surface of the p-well to provide a donor-doped region (n+region) with a concentration of 1×1021/cm3or more. After the ion implantation, heat treatment is performed at 1600° C. to 1700° C. for 45 minutes to electrically activate the implanted ions. After that, thermal oxidation is performed at 1120° C. for 60 minutes in a dry oxygen atmosphere to form a gate oxide film (Gox) with a thickness of 50 nm on the main surface. An opening is formed in a portion of the gate oxide film (Gox), and a Ni electrode is connected to the n+region as a source electrode (Source). A gate electrode (Gate) made of polycrystalline Si is provided on the gate oxide film (Gox) that covers the p-well from the n+region. In this process, the gate is formed in a length of 0.8 μm to 3 μm. Then, a drain electrode (Drain) is provided over the entire back surface of the SiC laminate. Further, a metal with a high work function such as Pt, Au, W is deposited on the surface of the 4H-SiC layer by sputtering or vapor deposition to form an anode (An), thereby forming a Schottky barrier diode (SBD) as a freewheeling diode. (Device Characteristics) In the n-type MOSFET formed by the above process, a gate electrode (Gate) is formed only on the 3C-SiC layer, and the interface state density (DA) at the MOS interface is less than 5×1011/cm2/eV. At a gate voltage of 3.2 V or higher, an n-channel (Nch) is formed by an inversion layer and the MOSFET becomes conductive. At a gate voltage of 5 V, the channel mobility is higher than 340 cm2/V/sec at 300 K and exceeds 240 cm2/V/sec at 500 K. Therefore, the channel resistance (Rch) is less than 1.3 mΩ·cm at a temperature of 500 K or less, which reduces the conduction loss of the MOSFET. The lower part of the p-well, where a region with the maximum electric field intensity is formed, is located in the 4H-SiC layer having a band gap (Eg) of 3.2 eV. Accordingly, when the applied voltage between the source and the drain is 600 V and the gate voltage is 0 V, the leakage current density between the drain and the source is less than 1.3×10−9 A/cm2. Meanwhile, when the gate voltage is 5 V, the density of current flowing between the source and the drain exceeds 730 A/cm2in the temperature range of 500 K or less. Thus, it is possible to obtain a low-loss MOSFET in which power loss due to leakage current is sufficiently reduced. On the surface of the 4H-SiC layer, the anode (An) of the SBD is connected to the source. When the drain potential of the MOSFET drops with respect to the source potential, the SBD becomes conductive as a freewheeling diode and matches the drain potential with the source potential. Since the anode (An) is formed on the 4H-SiC surface with a high band gap, the SBD maintains a breakdown voltage (Vb) equal to or higher than that of the MOSFET. There is also almost no accumulation of electric charge as the SBD is a unipolar device. In addition, the threshold voltage at which it becomes conductive is lower than the threshold voltage at which the pn junction in the MOSFET becomes conductive, and therefore, the pn junction in the MOSFET does not become conductive under any circumstances. This prevents the recombination of minority carriers around the p-well, thereby improving the long-term reliability of the MOSFET. Furthermore, the time required for the SBD to become conductive (reverse recovery time) is 8 n seconds or less. Thus, according to the embodiments of the present invention, the semiconductor device has the effect of suppressing the switching loss of the MOSFET. [Embodiments of CMOS Circuit] Described below is an embodiment of a CMOS circuit using a SiC laminate of the present invention. In the following embodiment, using an n-type 4H-SiC wafer with a resistivity of 150 Ω·cm or higher, a layered structure having a 3C-SiC layer and a 4H-SiC layer is formed by the SiC laminate production method according to the first embodiment. Note that intentional doping of impurities is not performed in the lateral epitaxy process, and an epitaxially grown layer has a donor concentration of 1×1015/cm3or less. The epitaxially grown layer formed has a thickness of 5 μm to 10 μm. (Manufacturing Process for Device and Circuit) Aluminum ions are implanted in part of the 3C-SiC layer and nitrogen ions are implanted in part of the 4H-SiC layer to form a p-well and an n-well as illustrated inFIG.17. An n-channel MOSFET (NMOSFET) is formed in the p-well region, while a p-channel MOSFET (PMOSFET) is formed in the n-well region. Aluminum concentration and nitrogen concentration are 3×1017/cm3in the respective regions. Nitrogen ions and phosphorus ions are implanted near the surface of a portion of the p-well, and aluminum ions are implanted near the surface of a portion of the n-well to provide a high-concentration donor-doped region (n+) and a high-concentration acceptor-doped region (p+) for connection with electrodes. The donor concentration of the n+region is 1×1021/cm3or more, and the acceptor concentration of the p+region is 5×1018/cm3or more. After the above ion implantation, heat treatment is performed at 1600° C. to 1700° C. for at least 45 minutes to electrically activate the implanted ions. After that, thermal oxidation is performed at 1120° C. for 10 minutes in a dry oxygen atmosphere to form a gate oxide film (Gox) with a thickness of 20 nm on the SiC laminate. In addition, a field oxide film (Fox) with a thickness of 3 μm or more is provided between the n-well and the p-well by the CVD method to electrically isolate the devices from each other. Then, a gate electrode (Gate) made of polycrystalline Si is provided on the gate oxide film (Gox) and used as an input terminal. In this process, the gate is formed in a length of 40 nm to 1 μm. Thereafter, an opening is formed in a portion of the gate oxide film (Gox), and Ni electrodes are connected to the n+region and the p+region to be used as a source electrode (Source) and a drain electrode (Drain). In the last step, the drain of the NMOSFET formed on the p-well and the drain of the PMOSFET formed on the n-well are connected together to form a CMOS circuit using this as an output terminal. (Device Characteristics) In the CMOS circuit formed by the above process, the source of the NMOSFET region is grounded to the ground potential, and the source of the PMOSFET region is connected to a constant voltage (Vdd) between 3.3 V and 45.2 V. The PMOSFET and the NMOSFET alternately become conductive depending on the voltage applied to the gate, and accordingly the potential of the drain changes between the ground potential and the voltage Vdd. The NMOSFET is located in the 3C-SiC layer with an interface state density of less than 5×1011/cm2/eV with respect to electrons. The PMOSFET is located in the 4H-SiC layer with an interface state density of less than 4×1012/cm2/eV with respect to holes. As a result, the on-resistance (Ron) of the NMOSFET is 1.3 mΩ·cm or less, and the on-resistance of the PMOSFET is 3.2 mΩ·cm or less. Thus, the delay time required to invert the output of the CMOS circuit can be 5 n seconds or less. Furthermore, the CMOS circuit of this embodiment has a low subthreshold leakage current and can reduce the standby power loss to 3% or less compared to a Si CMOS circuit having a structure similar to that of this embodiment. Since the temperature at which SiC becomes an intrinsic semiconductor is higher than 700° C. due to its wide band gap (Eg), the CMOS circuit of the embodiment is operable in the temperature range exceeding 220° C. Therefore, when the source of the NMOSFET is connected to a capacitor, a non-volatile memory can be constructed because of the low leakage current. EXAMPLES (Off Process, Seed Process) Commercially available single-crystal 4H-SiC wafers (W1, W2, W3, W4, W5) were prepared. The wafers were 6 inches in diameter and had a surface inclined 1 degree in the [11-20] direction from the (0001) plane (Si plane). Each wafer was provided with a first orientation flat (OF1) parallel to the (1-100) plane and a second orientation flat (OF2) parallel to the (11-20) plane. An image reversal photoresist (AZ5214E) was applied to a thickness of 2 μm on the surfaces of the wafers W1 to W4. Next, 240 linear photoresist (LPR) patterns were defined by exposure with a reduction stepper (Nikon NSR-1505G5D) that utilized a g-line mercury lamp (wavelength 436 nm) as its light source. At this time, the angles of the wafers W1, W2, and W4 were adjusted such that the LPR patterns were deflected by 0.5 degrees or less relative to the OF2, and the angle of the wafer W3 was adjusted such that the LPR patterns were deflected counterclockwise by 8 degrees from the OF2. The LPR patterns on the 4H-SiC wafers W1, W3, and W4 were formed to be continuous from the OF1 side to the other side, while the LPR patterns on the wafer W2 were provided with 1 mm unexposed portions (discontinuous portions) at 10 mm intervals in a <1-100> direction by adjusting the step size of the stepper. The spacing (space width) between adjacent LPR patterns was 30 μm, and the minimum width of the LPR patterns was 1.3 μm. The photoresist was developed by a reverse bake at 180° C. for 5 minutes and overall exposure to the g-line of the mercury lamp to obtain LPR patterns each having an inversely tapered cross section with a flange width of 0.5 μm. Dry etching was performed on the wafers W1 to W4 using a parallel plate RF dry etching system. In this process, CF4gas and O2gas were introduced into the dry etching system at flow rates of 40 sccm and 10 sccm, respectively, and plasma was generated by applying 100 W RF power at 13.56 MHz while the pressure was maintained at 40 Pa. By 25 seconds of the dry etching, SiC exposed at a location corresponding to the space width of the resist patterns was etched to a depth of 35 nm and removed. Inclined planes were formed on the SiC surface covered by the flanges of the resist patterns, and their inclination angle was 4 degrees. After that, ashing was performed for 15 minutes with oxygen plasma generated at an input power of 100 W using an asher to completely remove the LPR patterns. This was followed by 5 minutes of SPM cleaning and 3 minutes of rinsing with pure water to remove resist residues, fine particles, and metal contaminants from the surface. (Surface Structure Stabilization Process) The wafers W1, W2, W3, and W5 were vertically fixed to a quartz boat, and the boat was placed in a horizontal quartz vessel. Then, the air in the quartz vessel was replaced with nitrogen gas, and the pressure was maintained at 970 hPa as hydrogen gas was introduced into the quartz vessel at a flow rate of 3 slm. Note that the hydrogen introduced was purified through a purification system using a permeable membrane made of platinum-palladium to ensure its purity of 99.999999% or higher. The flow rate and pressure of the hydrogen gas were adjusted by a method generally used for thermal diffusion and thermal oxidation of Si, and therefore a detailed description thereof is omitted herein. Next, the entire quartz vessel was heated to 500° C. by energizing a resistance heater surrounding the outside of the quartz vessel and controlling the current value. After the temperature of the reaction vessel reached 500° C., the temperature was maintained for 5 hours, and then the power supply to the heater was turned off. The supply of hydrogen was stopped after the temperature of the quartz vessel dropped to 100° C. or less. The SiC wafers placed on the boat were taken out after the atmosphere inside the quartz vessel was replaced with nitrogen gas. (Epitaxial Growth Process) Epitaxial growth was performed on the wafers W1 to W5 under the same conditions using a SiC epitaxial growth system (NuFlare Technology, Inc. EPIREVO S6). In the epitaxial growth, each of the wafers was placed face up on a graphite susceptor coated with polycrystalline SiC in a reactor. Then, while the wafers were rotated at 800 rpm, 5 slm of hydrogen was introduced to maintain the pressure at 300 hPa and the wafer temperature was raised to 1650° C. Immediately after the wafer temperature reached 1650° C., additional monosilane gas and propane gas were fed into the reactor at flow rates of 50 sccm and 13 sccm, respectively, and epitaxial growth was carried out for 3 minutes while the pressure was maintained at 300 hPa. After that, the supply of monosilane gas and propane gas was stopped. When the wafer temperature reached 700° C. or lower, the supply of hydrogen gas was stopped, and the wafers were taken out from the reactor. Fourier transform infrared spectroscopy (FT-IR) confirmed that an epitaxially grown SiC layer had a thickness of 0.6 μm. In addition, Hall effect measurement indicated that the epitaxially grown layer had an n-type conductivity, and the carrier concentration at room temperature was 7×1015/cm3. Layered Structure) After the epitaxial growth, the crystal structure of SiC exposed on the wafer surface and its orientation or direction were observed by electron backscatter diffraction (EBSD). As a result of the observation, 3C-SiC and 4H-SiC were found on the surfaces of the wafers W1, W2, W3 and W4, while only 4H-SiC was found on the surface of the wafer W5. This indicates that, when a seed plane is formed by the SiC laminate production method according to an embodiment of the present invention, 3C-SiC is formed on the top of the seed plane, and step-controlled epitaxy occurs on the inclined planes. Through the EBSD analysis for the wafers W1, W3, and W4, it was detected that the 3C-SiC surface had a width of 18 μm in the [11-20] direction, while the 4H-SiC surface had a width of 13 μm. From this, it was found that the 3C-SiC two-dimensionally nucleated on the seed plane grew in a direction parallel to a close-packed plane by step-controlled epitaxy. On the other hand, the EBSD analysis for the wafer W2 showed that the 3C-SiC surface had a discontinuity in the [110] direction, and the 4H-SiC surface appeared at the discontinuity of 3C-SiC. The boundary between 3C-SiC and 4H-SiC found here is not perpendicular to the inclination direction, indicating that the boundary includes an incoherent interface. (Carrier Lifetime) On the wafers W1 to W4, the time taken for excess carriers to disappear at the boundary between the 3C-SiC surface and the 4H-SiC surface was measured by the microwave photoconductive decay (μ-PCD) method. In the μ-PCD method, a laser beam with a wavelength of 355 nm was focused to a diameter of 1 μm and adjusted such that its center was located on the boundary between the 3C-SiC surface and the 4H-SiC surface. The lifetime of carriers generated by the excitation of laser light was then measured based on the decay time of reflected microwave intensity. Since 3C-SiC has an electron affinity about 1 eV higher than that of 4H-SiC, electrons generated by laser light excitation diffuse toward the 3C-SiC side, and holes diffuse toward the 4H-SiC side. As a result, the electrons and holes are spatially separated, which extends the lifetime of carriers. However, if the interface between 3C-SiC and 4H-SiC includes an incoherent interface that causes carrier recombination, the carrier lifetime is reduced according to the density. Table 1 shows the carrier lifetime measured by the μ-PCD method together with production conditions and results of the EBSD analysis for each wafer. It is clear from the table that the carrier lifetime is significantly longer on the wafers (W1, W3, W4) with continuous inclined planes. On the wafer W2 where inclined planes have a discontinuity, an incoherent interface is generated at the discontinuity, which promotes the recombination of electrons and holes, resulting in a shorter carrier lifetime. In addition, the more the division direction maintained an orthogonal relationship to the inclination direction, the more the recombination of carriers was suppressed, extending the carrier lifetime. In view of the foregoing, it has been proven that the SiC laminate of the present invention suppresses the trapping and recombination of carriers in a semiconductor device and improves the characteristics of the semiconductor device. TABLE 1SurfaceInterfaceCarrierStructurebetweenLifetimeWaferInclinedStabilization3C—SiC and(×10−9No.PlaneProcess4H—SiCsec.)W1ContinuousPerformedCoherent2032W2DiscontinuousPerformedCoherent and74incoherentW3Continuous withPerformedCoherent776deviated divisiondirectionW4ContinuousNot performedCoherent1811W5PositivePerformedNo interfaceinclination only Pole figures were observed by X-ray diffraction on the wafers W1, W3, and W4. The results showed that the (111) plane of the 3C-SiC layer and the (0001) plane of the 4H-SiC layer were exactly parallel and that three-fold symmetry planes selected from the {11-2} planes of the 3C-SiC layer and the {11-20} planes of the 4H-SiC layer were exactly parallel. This indicates that three-fold symmetry planes selected from the {−1-11} planes of 3C-SiC and the {0-33-4} planes of 4H-SiC are exactly parallel, and the 3C-SiC layer does not contain a twin boundary. On the other hand, in the pole figure of the wafer W2, there was found a portion where the (111) pole of 3C-SiC and the (0001) pole of 4H-SiC had different angles. From this, it can be seen that the interface between 3C-SiC and 4H-SiC formed on the wafer W2 contains an incoherent interface. Meanwhile, in the pole figure of the wafer W4, the (−1-11) planes of discrete 3C-SiC layers were not always parallel and were found to have a rotational relationship of 120 degrees. Thus, it was found that the 3C-SiC layers have a twinning relationship. That is, the surface structure stabilization process of the present invention is necessary to equalize the close-packed structure of all 3C-SiC layers. As described above, it is possible to obtain a laminate of hexagonal SiC and 3C-SiC by performing step-controlled epitaxy after forming a seed plane. In addition, by providing no discontinuity to inclined planes adjacent to the seed plane, the continuity of the crystal lattice is maintained at the interface between hexagonal SiC and 3C-SiC, and only a coherent heterointerface can be obtained. Furthermore, it has been found that stabilizing the surface structure of seed planes prior to step-controlled epitaxy prevents a twin boundary from occurring even when 3C-SiC layers extending from different seed planes meet each other. (MOS Interface Characteristics) All the above wafers were thermally oxidized at 1120° C. for 60 minutes in a dry oxygen atmosphere to form a Si oxide film with a thickness of 50 nm on the main surface. Then, Ni electrodes with a diameter of 1 μm were deposited on the Si oxide film. The Ni electrodes were arranged in a grid with a spacing of 1 μm. In the wafers W1, W3, and W4, a 3C-SiC surface with a width of 2.3 μm and a 4H-SiC surface with a width of 2 μm are both present on the main surface. Therefore, it is possible to select an electrode (E3C) located only on the surface of the 3C-SiC layer or an electrode (E4H) located only on the surface of the 4H-SiC layer. Next, the conductance method was used to measure the MOS interface state density around the conduction bands of the electrodes E3Cand E4Hon each wafer. After measuring the interface state density, the dielectric breakdown field strength of the Si oxide film was measured as the voltage applied to the electrodes was continuously increased from 0 V to 60 V at room temperature. Table 2 shows the interface state density and dielectric breakdown field strength for each of the electrodes E3Cand E4Hon each wafer. TABLE 2MOS Interface State DensityDielectric Breakdown FieldWafer(×1012cm−2/eV)Strength (MV/cm)No.E3CE4HE3CE4HW10.342.711.810.2W20.842.85.36.4W30.331.011.911.3W40.580.29.19.1W517.411.5 As can be seen in Table 2, the state density of the MOS interface formed in 3C-SiC is reduced to 1/30 or less of that of 4H-SiC. That is, the channel resistance decreases in an n-channel MOSFET manufactured in a 3C-SiC layer according to an embodiment of the present invention, and it is possible to obtain a semiconductor device with significantly reduced power loss. The effect of reducing the interface state density is particularly pronounced in the wafers (W1, W3) having seed planes subjected to the surface structure stabilization process. Furthermore, since the wafers W1, W3, and W4 do not has an incoherent interface at the interface between 3C-SiC and 4H-SiC, the electric field distribution is uniform at the MOS interface, and the high dielectric breakdown field strength is achieved on the 3C-SiC surface and the 4H-SiC surface. This clearly indicates that the SiC laminate of the present invention is effective in improving the long-term reliability of semiconductor devices. Although specific embodiments of the invention have been described and illustrated, it is to be understood that the invention is not limited to the embodiments disclosed herein. Various changes, modifications, and alterations may be made within the scope of the invention as defined in the appended claims. For example, the polytype of hexagonal SiC is not limited to 4H-SiC. 6H-SiC or 15R-SiC may also be used to obtain a coherent heterointerface with a 3C-SiC layer, and a low-loss semiconductor device can be achieved. In addition, the shape of the seed plane is not limited to a straight line with a trapezoidal cross section or a truncated cone. As long as the inclined plane is at a depression angle of 0.5 degrees or more and less than 73 degrees with respect to the seed plane and has no discontinuity, the same results as in the embodiments can be obtained regardless of the shape of the seed plane. The temperature, pressure, and gas flow rate in the lateral epitaxy process are also not limited to those described in the above embodiments and examples, and optimal conditions can be appropriately adjusted as necessary. INDUSTRIAL APPLICABILITY The SiC laminate of the present invention can be used as a substrate for power semiconductor devices, such as MOSFETs, insulated-gate bipolar transistors (IGBTs), bipolar transistors, p-n diodes, and SBDs, high-speed logic circuits with CMOS, and microelectromechanical systems (MEMS) devices. Furthermore, taking advantage of the features of the coherent heterointerface where different band gaps and electron affinities meet, the SiC laminate can also be used as a substrate for high-frequency devices, such as heterojunction bipolar transistors (HBTs) and high-electron-mobility transistors (HEMTs), and high-efficiency solar cells. LIST OF REFERENCE SIGNS 1Hexagonal SiC layer1S Hexagonal SiC surface1i,1is,1iu,1iv,1iwInclined plane1ifPositively inclined plane1ibNegatively inclined plane1pSeed plane on hexagonal SiC layer1pb,1pfPartial inclined plane1rRidge portion1vValley portion1prDiscontinuous ridge portion1pvDiscontinuous valley portion1N Crystal lattice plane having three-fold symmetry relationship selected from {0-33-n} planes of hexagonal SiC23C-SiC layer2S 3C-SiC surface2pSeed plane on 3C-SiC layer2eTwo-dimensional nucleus of 3C-SiC2N {−1-11} plane of 3C-SiC3Coherent heterointerface3S Segment of coherent heterointerface on main surface3J Segment of incoherent interface on main surfaceS Main surfaceCPP Close-packed plane of crystal latticeθ Inclination angleθf Initial inclination angle of vicinal waferθp Depression angle of inclined plane with respect to seed planeIf Positive inclination directionIb Negative inclination directionIx Division directionL Minimum length of inclined plane projected onto close-packed plane of crystal lattice in inclination directionWe Critical widthte Thickness of two-dimensional nucleus of 3C-SiC formed on seed planed Height difference of inclined planeOX Si oxide filmLPR Linear photoresist patternCPR Circular photoresist patternTR Trench on SiC surfaceWh Width of flange of linear photoresist patternNMOSFET N-channel field effect MOS transistorNch Channel region of NMOSFETPMOSFET P-channel field-effect MOS transistorPch Channel region of PMOSFETGox Gate oxide filmFox Field oxide filmAn Anode of SBDP-well Acceptor-doped regionN-well Donor-doped region | 55,785 |
11862461 | DETAILED DESCRIPTION With reference to the accompanying drawings, the following further describes exemplary implementations disclosed in the disclosure in detail. Although the accompanying drawings illustrate the exemplary implementations of the disclosure, it should be understood that the disclosure can be implemented in multiple forms, and should not be limited by the particular implementations described here. On the contrary, the purpose of providing these implementations is to more thoroughly understand the disclosure, and the scope of the disclosure is fully conveyed to persons skilled in the art. In the following description, numerous specific details are given in order to provide a more thorough understanding of the disclosure. However, it is apparent to persons skilled in the art that the disclosure may be implemented without one or more of these details. In other examples, in order to avoid confusion with the disclosure, some technical features well known in the art are not described. That is, all the features of the actual embodiments are not described herein, and well-known functions and structures are not described in detail. In the accompanying drawings, for clarity, the dimensions of layers, areas, elements and their relative dimensions may be exaggerated. The same reference numerals are used to denote the same components throughout the disclosure. It should be understood that when an element or layer is referred to as being “on”, “adjacent to”, “connected to” or “coupled to” another element or layer, it can be directly on, adjacent to, connected to or coupled to the another element or layer, or intervening elements or layers may be present. In contrast, when an element is referred to as being “directly on”, “directly adjacent to”, “directly connected to” or “directly coupled to” another element or layer, there are no intervening elements or layers. It should be understood that though the terms, first, second, third, etc., are used to describe the elements, components, areas, layers and/or sections, those elements, components, areas, layers and/or sections should not be limited by these terms. The terms are merely used to distinguish one element, component, area, layer or section from another element, component, area, layer or section. Thus, a first element, component, area, layer or section, which is discussed below, may be referred to as a second element, component, area, layer or section, without departing from the scope of the disclosure. Moreover, when a second element, component, area, layer or section is discussed, it does not mean that a first element, component, area, layer or section is necessarily present in the disclosure. The terms used herein are for the purpose of describing particular embodiments only and is not intended to limit the disclosure. As used herein, the singular forms “a”, “an” and “the/said” are intended to include the plural forms as well, unless the context clearly indicates otherwise. It should be further understood that the terms “consisting of” and/or “include”, when used in this description, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof. As used herein, the term “and/or” includes any and all combinations of the associated listed items. The embodiments of the disclosure provide a method for forming a semiconductor structure, as shown inFIG.1A, including S101to S103. At S101, a base is provided, in which the base includes a first doped area and a second doped area, and an isolation structure is provided between the first doped area and the second doped area. With reference toFIG.1B, a base100includes a first doped area101and a second doped area102, and an isolation structure104is provided between the first doped area101and the second doped area102. In some embodiments, the isolation structure is formed on a substrate, and the substrate on which the isolation structure is formed is doped, to form the first doped area on one side of the isolation structure and to form the second doped area on another side of the isolation structure to form the base. This operation may include S201to S210, as shown inFIG.2A. The operations of forming the base are described below with reference toFIG.2BtoFIG.2H. At S201, a substrate103is provided, as shown inFIG.2B; the isolation structure104is formed in the substrate103, in which the isolation structure104divides the substrate103into a first substrate105and a second substrate106spaced apart from each other, i.e., the isolation structure104is provided between the first substrate105and the second substrate106, as shown inFIG.2C. In some embodiments, the substrate may be a silicon substrate, a silicon on insulator substrate and the like. The substrate may also include other semiconductor elements, or include semiconductor compounds such as silicon carbide (SiC), gallium arsenide (GaAs), gallium phosphide (GaP), indium phosphide (InP), indium arsenide (InAs) or indium antimonide (InSb), or include other semiconductor alloys such as gallium arsenide phosphide (GaAsP), aluminum indium arsenide (AlInAs), aluminum gallium arsenide (AlGaAs), gallium indium arsenide (GaInAs), gallium indium phosphide (GaInP), and/or gallium indium arsenide phosphide (GaInAsP), or a combination thereof. The isolation structure may include a Shallow Trench Isolation (STI) structure or a Local Oxidation of Silicon (LOCOS) isolation structure, which is not limited here. The material of the isolation structure may include one or more of oxide of silicon, such as silicon oxide or silicon oxynitride. The isolation structure can be formed by a Chemical Vapor Deposition (CVD) process, a Physical Vapor Deposition (PVD) process, an Atomic Layer Deposition (ALD) process or the like. At S202, a patterned first mask layer is formed on the first substrate and the second substrate, in which the patterned first mask layer exposes a surface of the second substrate. With reference toFIG.2D, a patterned first mask layer107is formed on the first substrate105and the second substrate106. The patterned first mask layer107exposes the second substrate106. In some embodiments, the material of the patterned first mask layer107may include oxide of silicon, oxide of nitrogen or carbide such as silicon oxide, silicon nitride, silicon carbide, or silicon oxynitride. In addition, the patterned first mask layer107can be formed by any of deposition processes such as chemical vapor deposition, physical vapor deposition and atomic layer deposition, and the patterned first mask layer107can be formed by photolithography, dry or wet etching. At S203, a germanium-silicon substrate is formed on the surface of the second substrate through epitaxial growth or deposition. With reference toFIG.2D, a germanium-silicon substrate108is formed on the surface of the second substrate106through epitaxial growth or deposition. During implementation, the germanium-silicon substrate108may also be formed on the patterned first mask layer107, and the deposition process may be chemical vapor deposition. Forming the germanium-silicon substrate108on the second substrate106can effectively increase the migration rate of a hole, thereby improving the turn-on speed of the device. At S204, the germanium-silicon substrate on the patterned first mask layer is removed. With reference toFIG.2E, the germanium-silicon substrate108on the first substrate105and the patterned first mask layer107are removed to expose a surface of the first substrate105. In some embodiments, the removal can be performed through dry etching or wet etching. The gas used in dry etching may be one of trifluoromethane (CHF3), carbon tetrafluoride (CF4), difluoromethane (CH2F2), hydrobromic acid (HBr), chlorine (Cl2), or sulfur hexafluoride (SF6) or a combination thereof. In wet etching, hot phosphoric acid or hydrofluoric acid can be used as an etching solution. At S205, a patterned second mask layer is formed on the first substrate on which the isolation structure is formed and the germanium-silicon substrate, in which the patterned second mask layer exposes a surface of the first substrate. With reference toFIG.2F, a patterned second mask layer109is formed on the first substrate105on which the isolation structure104is formed and the germanium-silicon substrate108, in which the patterned second mask layer109exposes the surface of the first substrate105. In some embodiments, the material of the second mask layer may include silicon nitride, silicon carbide, or silicon oxynitride. In addition, the second mask layer can be formed by any of deposition processes such as chemical vapor deposition, physical vapor deposition and atomic layer deposition, and the patterned second mask layer109can be formed by photolithography, dry or wet etching. At S206, first ion implantation is performed on the first substrate by using the patterned second mask layer as a mask, to form the first doped area. With reference toFIG.2FandFIG.2G, first ion implantation is performed on the first substrate105by using the patterned second mask layer109as a mask, to form the first doped area101. Arrow A indicates performing first ion implantation on the first substrate105. In some embodiments, the first doped area101may be an N-type doped first substrate, and corresponding implanted first ions may be group VA ions, such as phosphorus, arsenic, and antimony. In some embodiments, ion implantation can also be achieved through processes such as thermal diffusion and plasma doping. After the ion implantation, a high temperature annealing process may also be included to repair lattice damage caused by the ion implantation. At S207, the patterned second mask layer is removed. With reference toFIG.2G, the patterned second mask layer109is removed to expose a surface of the germanium-silicon substrate108. In some embodiments, the patterned second mask layer109can be removed through a dry or wet etching process, etc. For an etching solution or gas used, reference may be made to the patterned first mask layer107, which is not repeated here. At S208, a patterned third mask layer is formed on the first substrate on which the isolation structure and the first doped area are formed and the germanium-silicon substrate, in which the third mask layer exposes a surface of the germanium-silicon substrate. With reference toFIG.2G, a patterned third mask layer110is formed on the first substrate105on which the isolation structure104and the first doped area101are formed and the germanium-silicon substrate108, in which the patterned third mask layer110exposes a surface of the germanium-silicon substrate108. In some embodiments, the material of the third mask layer may include oxide of silicon, oxide of nitrogen or carbide such as silicon oxide, silicon nitride, silicon carbide, or silicon oxynitride. In addition, the third mask layer can be formed by any of deposition processes such as chemical vapor deposition, physical vapor deposition and atomic layer deposition, and the patterned third mask layer110can be formed by photolithography, dry or wet etching. At S209, second ion implantation is performed on the germanium-silicon substrate and the second substrate in contact with a lower surface of the germanium-silicon substrate by using the patterned third mask layer as a mask, to form the second doped area. With reference to bothFIG.2GandFIG.2H, arrow B indicates performing second ion implantation on the second substrate106and the germanium-silicon substrate108. Second ion implantation is performed on the germanium-silicon substrate108and the second substrate106in contact with a lower surface of the germanium-silicon substrate108by using the patterned third mask layer110as a mask, to form the second doped area102. That is, the substrate corresponding to the first doped area may be the first substrate, and the substrate corresponding to the second doped area may be the second substrate and the germanium-silicon substrate formed on the second substrate. In some embodiments, the second doped area may be a P-type doped second substrate and a P-type doped germanium-silicon substrate, and corresponding implanted second ions may be group IIIA ions such as boron and indium. In some embodiments, an implantation process for the second ions can refer to the first ion implantation process, which is not repeated here. Different doped areas in the embodiments of the disclosure may adopt the same or different ion implantation processes. For example, when the base includes two different doped areas, the first doped area may adopt a thermal diffusion process, and the second doped area may adopt an ion implantation process, which is not limited here. At S210, the patterned third mask layer is removed. With reference toFIG.2H, the patterned third mask layer110is removed. In some embodiments, the patterned third mask layer110can be removed through a dry or wet etching technology, etc. For an etching solution or gas used, reference may be made to the patterned first mask layer, which is not repeated here. In some embodiments, N-type ion implantation can also be performed in a P-type doped base, i.e., a formed P well, to form the first doped area101to form a PN junction. In addition, P-type ion implantation can also be performed in an N-type doped base, that is, a formed N well, to form the second doped area102to form a PN junction. At S102, nitridation treatment is performed on the first doped area and the second doped area. With reference toFIG.2I, arrow C indicates performing nitridation treatment on the first doped area101and the second doped area102, so that nitrogen ions enter the first doped area101and the second doped area102, to form a first doped area101asubjected to nitridation treatment and a second doped area102asubjected to nitridation treatment. In the embodiments of the disclosure, nitridation treatment may be performed on the first doped area101and the second doped area102through a plasma nitridation process, rapid thermal nitridation or vertical furnace tube nitridation. In some embodiments, nitridation treatment may be performed on the first doped area and the second doped area by using a decouple plasma nitridation process. A reaction gas for the nitridation treatment includes nitrogen, and an auxiliary gas for the nitridation treatment includes helium. A ratio of a flow rate of the nitrogen to a flow rate of the helium ranges from 1:5 to 1:2. The flow rate of the helium may be 300 to 500 standard milliliters per minute (sccm), and the flow rate of the nitrogen may be 100 to 300 sccm. In the process of the nitridation treatment, it is ensured that a concentration of the nitrogen is greater than 5×1015/cubic centimeter (cm3), and the pressure ranges from 5 mtorr to 50 mtorr. The power of the plasma device may range from 300 watts (W) to 1500 W. In this way, ultra-low energy doping can be efficiently realized, which is more conducive to reducing an oxidation rate of the second doped area, and moreover, the problem of interface defects can be alleviated. In some embodiments, the reaction gas for the nitridation treatment includes nitrogen, and the auxiliary gas for the nitridation treatment includes helium. The ratio of the flow rate of the nitrogen to the flow rate of the helium ranges from 1:5 to 1:2. In this way, the second doped area and the first doped area can have nitrogen ions with sufficient volume concentration, thereby reducing the growth velocity of the second gate oxide layer, and also reducing adverse effects of excessive volume concentration of the nitrogen ions on the electrical properties of a subsequently formed device. In some embodiments, a reaction temperature for the nitridation treatment ranges from 90 degrees Celsius (° C.) to 100° C., and a reaction time for the nitridation treatment ranges from 90 seconds (s) to 110 s. The gas flow rate of nitrogen serving as the reaction gas needs to be moderate. If the gas flow rate of nitrogen is too small, the volume concentration of nitrogen ions entering the second doped area is too low, thus the inhibitory effect on the formation of the second gate oxide layer is not significant enough, and it is difficult to reduce the growth velocity of the second gate oxide layer. If the gas flow rate of nitrogen is too large, the volume concentration of nitrogen ions entering the surface of the second doped area is too high, which is likely to adversely affect the electrical properties of the subsequently formed device. Therefore, in this embodiment, the gas flow rate of nitrogen may range from 30 milliliters per minute (ml/min) to 150 ml/min. In this way, the second doped area and the first doped area can have nitrogen ions with sufficient volume concentration, thereby reducing the growth velocity of the second gate oxide layer, and also reducing adverse effects of excessive volume concentration of nitrogen ions on the electrical properties of a subsequently formed device. In this way, the nitrogen ions enter the first doped area and the second doped area through the nitridation treatment, and the nitrogen ions have an inhibitory effect on the formation of the second gate oxide layer, and reduce the growth velocity of the second gate oxide layer, thereby reducing the difference between the thickness of the first gate oxide layer and the thickness of the second gate oxide layer. In some embodiments, a high-temperature annealing process may also be included after the nitridation treatment is finished, for stabilizing nitrogen doping and repairing plasma damage in a medium caused by the nitridation treatment. In the embodiments of the disclosure, the nitridation treatment is performed on the first doped area and the second doped area, and oxidation treatment is performed on the first doped area and the second doped area subjected to the nitridation treatment, to form the first gate oxide layer and the second gate oxide layer respectively. In this way, in the process of nitridation treatment, nitrogen ions doped on the germanium-silicon substrate can prevent formation of Ge—O bond, thereby decreasing a difference between the thickness of the first gate oxide layer and the thickness of the second gate oxide layer, and reducing the effect on the electrical parameters of a semiconductor device, such as threshold voltage and capacitance. At S103, oxidation treatment is performed on the first doped area and the second doped area subjected to the nitridation treatment, to form a first gate oxide layer and a second gate oxide layer respectively. With reference toFIG.2J, oxidation treatment is performed on the first doped area101aand the second doped area102asubjected to the nitridation treatment, to form a first gate oxide layer111and a second gate oxide layer112respectively. In the embodiments of the disclosure, the first gate oxide layer and the second gate oxide layer may be silicon oxide. The oxidation treatment may be a suitable oxidation process such as ozone oxidation treatment, thermal oxidation treatment, In-Situ Stream Generation (ISSG) oxidation treatment, wet oxygen oxidation treatment, and high pressure oxidation treatment, which is not limited in the embodiments of the disclosure. In some embodiments, oxidation treatment may be performed, through ozone oxidation treatment, on the first doped area and the second doped area subjected to the nitridation treatment, to form the first gate oxide layer and the second gate oxide layer respectively. In this way, the oxidation rate can be better controlled, thereby facilitating obtaining a uniform gate oxygen thickness, and providing a better prerequisite for device performance adjustment. In some embodiments, the ozone oxidation may use a wet oxidation process, and an oxidant for the wet oxidation process is ozone. The flow rate of the ozone ranges from 8 to 12 L/min. The temperature for the wet oxidation process ranges from 20° C. to 30° C. In an embodiment, the first substrate corresponding to the first doped area is a silicon substrate, and the substrate corresponding to the second doped area is a silicon substrate and the germanium-silicon substrate formed on the silicon substrate. Taking this embodiment an example, a reaction of formula (1) occurs when the first gate oxide layer is formed by performing nitridation treatment on the first doped area and using ozone as the oxidant in the wet oxidation process, and a reaction of formula (2) occurs when the second gate oxide layer is formed by performing nitridation treatment on the second doped area and using ozone as the oxidant in the wet oxidation process. Si→SiNx+O3+DIW→SiONx(1) SiGe→SiGeNx+O3+DIW→SiONx(2) Formula (1) includes two arrows, the first arrow indicates a process of performing nitridation treatment on the silicon substrate to generate SiNx, and the second arrow indicates performing ozone oxidation treatment on the silicon substrate in which SiNxhas been generated. During the ozone oxidation treatment, an appropriate amount of Deionized Water (DIW) is added, and SiNxreacts with ozone and DIW to generate SiONx. Formula (2) also includes two arrows, the first arrow indicates a process of performing nitridation treatment on the germanium-silicon substrate in the second doped area to generate SiGeNx, and the second arrow indicates performing ozone oxidation treatment on the germanium-silicon substrate in which SiGeNxhas been generated. An appropriate amount of deionized water is also added. In the process of the ozone oxidation treatment, N ions inhibit the formation of Ge—O bonds, and SiGeNxreacts with ozone and DIW to generate SiONx, thereby reducing the rate of generating the second gate oxide layer. That is, when gate oxide layers are formed by performing nitridation treatment on the first doped area and the second doped area and using ozone as an oxidant in the wet oxidation process, the gate oxide layers formed on the first doped area and the second doped area are the same, for example, both may be SiONx, thereby reducing the difference between the thickness of the first gate oxide layer and the thickness of the second gate oxide layer, and improving the consistency of the gate oxide thicknesses of the first doped area and the second doped area. Furthermore, by introducing ozone into deionized water, the ozone concentration can be saturated to ensure the stability of the concentration, thereby facilitating further improving the uniformity of the thickness of the gate oxide layer formed. In some embodiments, a thickness of the first gate oxide layer may range from 10.5 angstroms to 11 angstroms (Å), a thickness of the second gate oxide layer may be greater than the thickness of the first gate oxide layer, and a difference between the thickness of the second gate oxide layer and the thickness of the first gate oxide layer may be less than 1.5 Å. With reference toFIG.2J, that is, d1ranges from 10.5 Å to 11 Å, and a difference between d2and d1is less than 1.5 Å. In some embodiments, oxidation treatment can also be performed, through an ISSG process, on the first doped area and the second doped area subjected to the nitridation treatment, to form the first gate oxide layer and the second gate oxide layer respectively. In this way, the first gate oxide layer and the second gate oxide layer having advantages of good coverage capability, good uniformity and good compactness can be formed, which is beneficial to improve the performance of the device and ameliorate the problem of device mismatch. In some embodiments, the reaction gas for the ISSG process may be oxygen and hydrogen, and the reaction temperature for the ISSG process may range from 850° C. to 950° C. ISSG treatment is performed on the first doped area and the second doped area subjected to the nitridation treatment for 15 s to 20 s, to form the first gate oxide layer and the second gate oxide layer respectively. In some embodiments, the reaction gas for the ISSG process may further include one of a mixed gas of N2O and H2or a mixed gas of N2O, O2and H2. In some embodiments, after S103, the method may further include S104to S106. With reference toFIG.3A, S104to S106are explained below in conjunction withFIG.3BtoFIG.3E. At S104, a first gate structure is formed on the first gate oxide layer, and a second gate structure is formed on the second gate oxide layer. With reference toFIG.3B, a first gate structure113is formed on the first gate oxide layer111, and a second gate structure114is formed on the second gate oxide layer112. In some embodiments, the first gate structure includes a first gate oxide layer, a first high-k dielectric layer, a first work function layer, a first cover layer, and a polysilicon layer. The second gate structure includes a second gate oxide layer, a second high-k dielectric layer, a second work function layer, a second cover layer, and a polysilicon layer. Correspondingly, the operation of forming the first gate structure and the second gate structure may include the following operations. At S1041, a first high-k dielectric layer, a first work function layer, and a first cover layer are successively deposited on the first gate oxide layer to form a first stack structure. With reference toFIG.3C, a first high-k dielectric layer115, a first work function layer116, and a first cover layer117are successively deposited on the first gate oxide layer111to form a first stack structure118. In the embodiments of the disclosure, the first high-k dielectric layer may be formed through a CVD, PVD or ALD process, etc. The first high-k dielectric layer may include at least one of a hafnium silicon oxide (HfSiO) layer, a hafnium silicon oxynitride (HfSiON) layer, a hafnium tantalum oxide (HfTaO) layer, a hafnium titanium oxide (HfTiO) layer, a hafnium zirconium oxide (HfZrO) layer, a zirconium oxide (ZrO2) layer or an aluminum oxide (Al2O3) layer. The first work function layer may include a lanthanum sesquioxide (La2O3) layer, and may be configured to adjust a threshold voltage. The first cover layer may be a metal layer such as a titanium nitride (TiN) layer or a tantalum nitride (TaN) layer, and can improve polysilicon depletion. At S1042, a second high-k dielectric layer, a second work function layer, and a second cover layer are successively deposited on the second gate oxide layer to form a second stack structure. With reference toFIG.3C, a second high-k dielectric layer119, a second work function layer120, and a second cover layer121are successively deposited on the second gate oxide layer112to form a second stack structure122. During implementation, the second high-k dielectric layer may be the same as or different from the first high-k dielectric layer. The second work function layer may include an aluminum sesquioxide (Al2O3) layer, and may be configured to adjust the threshold voltage. The second cover layer may be the same as or different from the first cover layer. At S1043, a polysilicon layer is formed on the first stack structure and the second stack structure to form the first gate structure and the second gate structure. With reference toFIG.3D, a polysilicon layer123is formed on the first stack structure118and the second stack structure122to form the first gate structure113and the second gate structure114. At S105, a P-type extension area is formed in the first doped area subjected to nitridation treatment, and an N-type extension area is formed in the second doped area subjected to nitridation treatment. With reference toFIG.3E, a P-type extension area124is formed in the first doped area101asubjected to nitridation treatment, and an N-type extension area125is formed in the second doped area102asubjected to nitridation treatment. Here, the N-type extension area includes halo ion implantation and Lightly Doped Drain (LDD), the P-type extension area also includes halo ion implantation and LDD, and the difference lies in that the doped ions of the N-type extension area are different from the doped ions of the P-type extension area. During implementation, during the halo ion implantation, the ion implantation direction may not be perpendicular to the first doped area and the second doped area, but may have a certain angle to form a bag-like doped area. In this way, lateral extension of depletion areas of a source and a drain can be reduced, to avoid a source/drain punch-through phenomenon. The extension areas form an impurity concentration gradient between the source/drain and a channel, thereby reducing a peak electric field near the drain and improving the hot carrier effect. At S106, sidewall structures are formed on two sides of the first gate structure and two sides of the second gate structure. With reference toFIG.3E, sidewall structures126are formed on two sides of the first gate structure113and two sides of the second gate structure114. The material of the sidewall structures126may be nitride, such as silicon nitride or silicon oxynitride. In embodiments of the disclosure, a method for forming a semiconductor structure includes: a base is provided, in which the base includes a first doped area and a second doped area, and an isolation structure is provided between the first doped area and the second doped area; nitridation treatment is performed on the first doped area and the second doped area; and oxidation treatment is performed on the first doped area and the second doped area subjected to the nitridation treatment, to form a first gate oxide layer and a second gate oxide layer respectively. In this way, by performing nitridation treatment on the first doped area and the second doped area, and performing oxidation treatment on the first doped area and the second doped area subjected to the nitridation treatment, a first gate oxide layer and a second gate oxide layer are formed respectively. In this way, on the one hand, the nitrogen ions formed by the nitridation treatment may reduce the oxidation rate of the second doped area, thereby inhibiting the formation of the second gate oxide layer. Therefore, the difference between the thickness of the first gate oxide layer and the thickness of the second gate oxide layer can be reduced, to reduce the effect on the electrical parameters of the semiconductor device, such as threshold voltage and capacitance, and provide a good basis for adjusting the semiconductor device. On the other hand, the process flow of the method is simple and controllable. The embodiments of the disclosure provide a semiconductor structure, and the semiconductor structure is formed by the method in the foregoing embodiments. The features disclosed in the method or semiconductor structure embodiments provided in the disclosure may be combined arbitrarily without conflict to obtain new method embodiments or semiconductor structure embodiments. The descriptions of the semiconductor structure embodiments above are similar to the descriptions of the method embodiments above, and have similar beneficial effects to the method embodiments. For technical details not disclosed in the semiconductor embodiments of the disclosure, please refer to the descriptions of the method embodiments of the disclosure for understanding. The foregoing descriptions are merely exemplary embodiments of the disclosure, and are not intended to limit the scope of protection of the disclosure. Any modification, equivalent replacement, improvement and the like made within the spirit and principle of the disclosure shall fall within the scope of protection of the disclosure. Therefore, the scope of protection of the disclosure shall be subject to the scope of protection of the claims. | 31,898 |
11862462 | DETAILED DESCRIPTION FIG.1shows a first working example of an apparatus1according to the invention for the continuous vapor deposition of silicon on substrates. This apparatus1comprises a reaction chamber2, a measuring unit3, a control unit4, a circulation conduit5, a gas scrubber6and a recovery unit7. The reaction chamber2has an inlet opening8through which substrates to be coated can be introduced into the reaction chamber2. Furthermore, there is an outlet opening9on the side of the reaction chamber2opposite the inlet opening8, via which outlet opening9silicon-coated substrates can be discharged from the reaction chamber2. Transport of the substrates into the reaction chamber2and out again is effected by a transport device10. As indicated by an arrow inFIG.1, the transport device10has a transport direction for the substrates from the inlet opening8to the outlet opening9. The transport device10can be configured as a conveyor belt. As an alternative, the transport device10can also have a plurality of transport rollers, or be configured as sliding rail transport. As shown inFIG.1, two substrates can in each case be introduced in an upright position into the reaction chamber2by the transport device10. Here, the substrates are arranged parallel to one another, so that the sides to be coated of the substrates are opposite one another. Furthermore, the reaction chamber2has a temperature of 1100° C. in the present working example. To introduce a gaseous silicon precursor compound and a process gas, two gas inlets11,12, via which the gaseous silicon precursor compound and the process gas can be introduced separately from one another into the reaction chamber, are arranged on the reaction chamber2in the region of the inlet opening8. In the present working example, high-purity hydrogen is used as process gas. The formation of parasitic deposits in the gas inlets11,12can be prevented by separate introduction of the gaseous silicon precursor compound and the process gas. Furthermore, the gas inlets11,12are each connected to a fluid feed conduit13,14through which the silicon precursor compound and the process gas can be fed to the gas inlets11,12. In the present working example, silicon tetrachloride is used as silicon precursor compound. Since silicon tetrachloride has a boiling point of 57.6° C. and is thus liquid at room temperature, a vaporizer15is arranged on the fluid feed conduit13. Liquid silicon tetrachloride is brought into the gaseous state by the vaporizer15before it is introduced into the reaction chamber2. In order to be able to discharge the excess of the gas mixture composed of the excess silicon precursor compound, the silicon-based intermediate and the process gas from the reaction chamber2after the substrates have been coated with silicon, the reaction chamber2has a gas outlet16in the region of the outlet opening9. The gas outlet16is connected to the circulation conduit5which serves for recirculation of at least one of the constituents of the excess of the gaseous mixture, selected from among the silicon precursor compound, the silicon-based intermediate and/or the process gas, into the reaction chamber2. Furthermore, the circulation conduit5is connected to the fluid feed conduit13. In the present working example, the gas scrubber6, the recovery unit7and the measuring unit3are arranged on the circulation conduit5and are connected to one another via the continuous circulation conduit5, in fact from the side of the gas outlet16to the side of the fluid feed conduit13. The gas scrubber6serves to concentrate the discharged excess of the gaseous mixture from the reaction chamber by bringing the discharged gaseous excess into contact with a scrubbing liquid in the gas scrubber6, as a result of which valuable constituents of the excess can be taken up in the scrubbing liquid. The constituents going over can be solid, liquid or gaseous materials. As scrubbing liquid, it is possible to use, for example, chlorosilane. The purified excess of the gaseous mixture can be conveyed via the circulation conduit5into the recovery unit7. In the present working example, the recovery unit7is configured as distillative separation apparatus. It serves to separate the silicon precursor compound and/or the silicon-based intermediate from the process gas. In addition, the recovery unit7makes it possible to separate undesirable by-products of the chemical vapor deposition from the circulation conduit5. The measuring unit3is arranged on the circulation conduit5in order to determine a molar ratio of the silicon-based intermediate and the silicon precursor compound. In the present example, the measuring unit3is configured as infrared spectrometer which measures a concentration of the silicon-based intermediate and the silicon precursor compound in the gas stream of the circulation conduit5and in this way determines the molar ratio of the silicon-based intermediate and the silicon precursor compound. However, as an alternative, the measuring unit3can also be configured as Coriolis mass flow meter. However, the invention is not restricted thereto. In order to regulate the introduction of the silicon precursor compound into the reaction chamber2, a control unit4, which can be configured, for example, as gas flow regulator, is arranged on the fluid feed conduit13. The control unit4additionally serves to control the molar ratio of the silicon-based intermediate to the silicon precursor compound in the reaction chamber2during introduction. For this purpose, the control unit4is connected to the measuring unit3. A molar ratio of the silicon-based intermediate to the silicon precursor compound in the excess of the gaseous mixture in the circulation conduit5as determined by the measuring unit3is transmitted to the control unit4. In order to maintain a desired molar ratio of the silicon-based intermediate to the silicon precursor compound of from 0.2:0.8 to 0.5:0.5, preferably from 0.3:0.7 to 0.5:0.5, particularly preferably 0.5:0.5, in the process gas in the reaction chamber2, the control unit4controls the amount of silicon precursor compound fed via the fluid feed conduit13and the gas inlet12into the reaction chamber on the basis of the molar ratio of the silicon-based intermediate to the silicon precursor compound in the excess of the gaseous mixture in the circulation conduit5determined by the measuring unit3. In the present working example, the control unit4and the measuring unit3are electrically conductively connected to one another, as a result of which the values measured by the measuring unit3are automatically transmitted to the control unit4. However, it is also within the scope of the invention for a user of the apparatus1to read off the molar ratio determined by the measuring unit3and provide it manually to the control unit4. FIG.2shows a second working example of an apparatus1according to the invention for the continuous vapor deposition of silicon on substrates. The apparatus1has a structure which is largely identical to the configuration described inFIG.1, for which reason further details will not be discussed first. In order to regulate the introduction of the silicon precursor compound and of the process gas into the reaction chamber2, the control unit4is arranged on the fluid feed conduit13,14. The control unit4serves firstly to control the molar ratio of the silicon-based intermediate to the silicon precursor compound in the reaction camber2during introduction and secondly to set a total amount of the silicon precursor compound and the silicon-based intermediate in step (c) in a molar ratio of from 1 to 10 mol %, preferably from 2 to 7 mol %, particularly preferably from 3 to 6 mol %, in the process gas. In this working example, too, the control unit4is connected to the measuring unit3. It is also within the scope of the invention for the excess process gas and/or the silicon-based intermediate and/or the silicon precursor compound to be discharged from the apparatus. In this present working example, the gas scrubber has, for this purpose, a gas outlet17with a discharge conduit18through which the excess process gas is discharged. However, the invention is not restricted thereto. Furthermore, the distillative separation apparatus can also have a gas outlet with a discharge conduit. FIG.3shows a third working example of an apparatus1according to the invention for the continuous vapor deposition of silicon on substrates. This apparatus1, too, has a structure which is largely identical to the configuration described inFIG.1, for which reason further details will not be discussed first. Downstream of the recovery unit7, the circulation conduit5is split up into three separate subconduits51,52,53for the process gas, the silicon-based intermediate and the silicon precursor compound. It is within the scope of the invention for more than three separate subconduits to be located downstream of the recovery unit, especially in order to recirculate other gases, for example hydrogen chloride, separately. The respective mass or volume flows are determined by separate measuring units31,32,33which are arranged on the subconduits51,52,53downstream of the recovery unit7. The molar ratio of the silicon-based intermediate to the silicon precursor compound can be derived therefrom. As can be seen fromFIG.3, the recovered process gas is then fed to the fluid feed conduit14, the silicon-based intermediate and the silicon precursor compound are the fluid feed conduit13. | 9,525 |
11862463 | DETAILED DESCRIPTION A dieelectric composition is disclosed as is a method of forming a dielectric composition and its use. In one embodiment, the dielectric composition is operable for use in integrated circuit structures as a dielectric layer on a device layer such as a dielectric layer as a mask (e.g., a hardmask) on an interconnect layer (e.g., metal line or other contact point) to allow the selective formation of openings to the interconnect layer. The dielectric composition is operable to fill tight pitch features (e.g., pitch feature of 30 nanometers or less) and demonstrates relatively high etch selectivity compared to other hardmask materials such as silicon nitride or silicon carbide. In one embodiment, the dielectric composition includes metal oxide particles having a diameter of five nanometers (nm) or less that are capped with an organic ligand at at least a one to one (1:1) ratio. Suitable metals for the metal oxide particles include but are not limited to hafnium, zirconium, titanium, aluminum and tin. The metal oxide particles can be synthesized by a variety of methods, such as sol gel hydrolysis-condensation using metal alkoxide precursors and reduction of metal halides. Equations 1-3 below show representative ways to synthesize metal oxide particles. Equation 1 shows a condensation between a metal halide of, for example, hafnium, zirconium, titanium, aluminum, or tin (with X representing a halide (e.g., chloride, iodide) and a metal alkoxide (formed, for example, by the reaction of metal halides with alcohols). The condensation produces a metal oxide and an alkyl halide. One example would be the reaction of titanium isopropoxide and titanium chloride. Equation 2 describes another condensation operation leading to metal oxides. Equation 2 describes an ether elimination process involving condensation of two metal alkoxides under elimination of an organic ether. Equation 3 is a further condensation process using an ester elimination process involving the reaction of metal carboxylates and metal alkoxides. M-X+R-O-M→M-O-M+R—X Equation 1: M-OR+RO-M→M-O-M+R—O—R Equation 2: M-O—C(O)R′+R—O-M→M-O-M+RO—(C(O)R Equation 3: A metal oxide particle process such as described above is used to form metal oxide particles that, in one embodiment, have a diameter of five nanometers or less. To control agglomeration and limit the particle size of the metal oxide particles, the particles are end capped with organic ligands. End capping of oxide particles may be done by, for example, an esterification reaction or by a ligand exchange after synthesis and purification. The capping of the metal oxides with an organic ligand inhibits the agglomeration of the metal oxide particles allowing particle sizes of five nanometers or less that are suitable for tight pitch feature applications. Representative dimensions of openings or gaps that can be filled with the dielectric composition include gaps having a diameter or width on the order of 10 nm to 15 nm with a 10:1 aspect ratio (depth:diameter (width)). A representation of the dielectric composition is illustrated InFIG.1.FIG.1shows metal atoms (M) bond to oxide atoms (O) with organic ligands bound to exterior oxygen atoms. In one embodiment, the capping ligands are X-type ligands as both the ligand and the nanoparticle core contribute electrons to the chemical bond. In the representation shown inFIG.1, the capping ligands have a carbonyl group, —C(O)R, where R is a C1-C10 chain that may be saturated (e.g., an alkyl), be unsaturated, branched (e.g., an isoalkyl) contain an aromatic moiety and/or be substituted (e.g., carbon atoms substituted with oxygen atoms) contain an aromatic moiety. Suitable molecules for capping ligands include carboxylic acids that can react with the metal oxide nanoparticles through an esterification reaction. Representative carboxylic acids include, but not limited to, methacrylic acid, benzoic acid, 4-vinylbenzoic acid, isobutyric acid, pivalic acid and acetic acid. One example of forming hafnium nanoparticles is as follows. First, a hafnium alkoxide (e.g., hafnium isopropoxide) undergoes an acide-catalyzed hydrolysis reaction where the hafnium is hydroxylated. The hydroxylated hafniums can condense to form a Hf—O—Hf crosslined network. As the hydrolysis/condensation reaction occurs, an esterification reaction will occur on the shell of the formed nanoparticles, where carboxylic acid fuctional groups replace the isopropoxide ligands from the hafnium starting material. Such end capping prevents further condensation reactions from taking place at that particular site, and ultimately controls the size of the nanoparticles. In another embodiment, the esterification reaction may occur with a first carboxylic acid (e.g., oleic acid) and then that first carboxylic acid may be replaced on the surface of nanoparticle clusters with a carboxylic acid by ligand exchange by exposure of the clusters to an excess of the second carboxylic acid. Such end capping may include monodentate ligand binding or bidentate ligand binding. Hafnium oxide nanoparticles capped with carboxylate ligands have shown greater than a 50:1 etch selectivity to oxide, nitride and typical ILD materials on blanket films. Using spin-coating and thermal cure, lab tests have demonstrated the ability of this material to fill 25 nm gaps without voiding. The hafnium oxide nanoparticles can withstand an oxygen-based plasma etch to remove a carbon-based trench wall, leaving the cured nanoparticles behind. The cured hafnium oxide film has demonstrated low leakage and can be considered as a leave-behind material. FIGS.2-9show a process of utilizing the dielectric composition described above as a hardmask in an integrated circuit process operation. Specifically,FIGS.2-9describe a process using the dielectric composition as a hardmask to selectively form openings or vias to an underlying metal layer either by ultimately selectively removing the dielectric composition or another dielectric material formed on the metal layer. Referring toFIG.2,FIG.2shows substrate105that is for example a semiconductor substrate as a bulk semiconductor substrate (e.g., bulk silicon substrate) or a silicon on insulator (SOI) substrate. Formed on substrate105is device layer110of, for example, transistor devices (e.g., hundreds of thousands to millions of transistor devices) and possibly other devices (e.g., capacitors resistors, etc.). Disposed on device layer110is dielectric layer111such as an initial interlayer dielectric (ILD0) of silicon dioxide or a material having a dielectric constant less than silicon dioxide (a low-k material). Formed in ILD0 are contacts to ones of devices in device layer110(not shown) and interconnect or metal layer112that is, for example, a series of metal lines or traces (e.g., copper traces) between device contacts that form circuits and transmit power throughout a substrate area. In one embodiment, metal layers112have a pitch, P2, that is, for example, 10 nanometers (nm) to 30 nm. In the absence of extreme ultraviolet (EUV) lithography, one option for defining openings or vias to metal lines or traces having a pitch on the order of 10 nm to 30 nm is through self-aligned double patterning (SADP) techniques.FIGS.2-6illustrate an example of an SADP process. Referring again toFIG.2, overlying metal layer112on substrate110is hardmask layer115of, for example, silicon nitride, silicon carbide, or a dielectric composition such as described above including metal oxide particles including a metal selected from hafnium, zirconium, titanium, aluminum or tin. In one embodiment, hardmask layer115has a thickness on the order of 30-100 nm. In one embodiment, to form a dielectric composition of metal oxide particles, metal oxide particles would be synthesized and capped as described above. The capped particles are then dispersed in a casting solvent. A representative casting solvent is propylene glycol methyl ether acetate (PGMEA), cyclohexanone, 2-heptanone. From the casting solvent, such composition may be deposited, for example, by spin-coating. After deposition, a high temperature anneal such as an anneal temperature of 400° C. or greater for 30 minutes is used to decompose the organic ligands and solvent and convert the metal oxide into a dense film in which the nanoparticles further agglomerate. Ultraviolet or electron beam radiation may alternatively be used to decompose the ligands and solvent and form a dense film. Overlying hardmask layer115in the structure ofFIG.2is a dielectric layer that has an etch selectivity relative to bottom hardmask layer115. An etch selectivity in this context means that a material of dielectric layer120may be etched or removed at a different rate with a particular etchant than a material of bottom hardmask layer115. In one embodiment, dielectric layer120is a buffer oxide (e.g., silicon dioxide) deposited to a thickness on the order of 30-100 nm. Disposed on dielectric layer120is dielectric layer125of a material having an etch selectivity relative to dielectric layer120. One suitable material for dielectric layer125, where dielectric layer120is an oxide, is silicon nitride or silicon carbide. Dielectric layer125has a representative thickness on the order of 30-100 nm. FIG.2shows the structure of the structure following the deposition of a pattern on the structure.FIG.2shows, for example, pattern130of a photoresist deposited and patterned using mask135. Photoresist pattern130on dielectric layer120has a pitch, P1, on the order of 60 nanometers or more. In one embodiment, pattern130is formed with a width, W, and depth (into the page) for a desired contact opening. In this embodiment, the contact opening will be made to individual areas of lines or traces of underlying metal layer112. Accordingly, in one embodiment, the patterned photoresist has a, W, equivalent to or less than a width of the metal lines. FIG.3shows the structure ofFIG.2following an etch of dielectric layer125and the introduction and patterning of a spacer layer. In one embodiment, a material for dielectric layer125of silicon nitride may be etched anisotropically with, for example, phosphoric acid (H3PO4) to transpose pattern130into the dielectric layer. The etch proceeds through dielectric layer125and can be stopped on dielectric layer120due to a different etch rate (e.g., dielectric layer120of silicon dioxide having a slower etch rate with phosphoric acid than silicon nitride). Following the etching of dielectric layer125, pattern130is removed and a spacer layer is conformally deposited on the structure of patterned dielectric layer125. Spacer layer140is formed on dielectric layer120and on the sidewalls and superior surface of dielectric layer125. In one embodiment, spacer layer140is a dielectric material that may be etched selectively relative to dielectric layer125(e.g., an oxide). An example material for spacer layer140is silicon-oxide based. Once deposited, spacer layer140is then anisotropically etched to expose a superior surface of dielectric layer125creating the side wall spacer image of space layer140on patterned dielectric layer125. FIG.4shows the structure ofFIG.3following a deposition of dielectric layer145on the structure. Dielectric layer145is, for example, a dielectric material that may be selectively etched relative to spacer layer140and dielectric layer145. Where dielectric layer125is silicon nitride and spacer layer is is an oxide, dielectric layer145may be silicon carbide. Following a deposition of dielectric layer145, a superior surface of the structure is planarized with, for example, a chemical mechanical polish. FIG.5shows the structure ofFIG.4following the selective removal of spacer layer140. A spacer layer of140of an oxide may be selectively removed relative to dielectric layer125of silicon nitride and dielectric layer145of silicon carbide using a potassium hydroxide etchant. The removal of spacer layer140creates a mask structure on dielectric layer120consisting of alternate bodies of dielectric layer125and dielectric layer145.FIG.5also shows the structure following an etch of dielectric layer120using the mask of dielectric layer125and dielectric layer145. Dielectric layer120is patterned to have a pitch P2 that is, in one embodiment, 50 percent of pitch P1. FIG.6shows the structure ofFIG.5following a removal of dielectric layer125and dielectric layer145and the patterning of hardmask layer115using the pattern of dielectric layer120.FIG.6shows hardmask layer115disposed on dielectric layer111(ILD0) over or patterned on metal lines112. FIG.7shows the structure ofFIG.6following a deposition of a dielectric material on the substrate. Dielectric material150is a material having an etch selectivity relative to hardmask layer115. In one embodiment where hardmask layer115is a traditional hardmask such as silicon nitride or silicon dioxide, dielectric layer150is, for example, a dielectric composition of a metal oxide including a metal selected from hafnium, zirconium, titanium, aluminum or tin. Where hardmask layer115is a dielectric composition comprising a metal oxide of, for example, hafnium, zirconium, titanium, aluminum or tin, in another embodiment, dielectric material150may also be a metal oxide of one of the noted materials that has a different etch rate (different selectivity) for a particular etchant relative to a material of hardmask layer115. For example, where hardmask layer115is made up of, for example, hafnium oxide particles, dielectric material150is made up of, for example, titanium oxide particles. A dielectric material of metal oxide particles such as described above offer the ability to fill openings having a diameter of, for example, 30 nm or less without voiding. In one embodiment, dielectric material150may be introduced by spin-coating and then cured to form film. FIG.8shows a structure ofFIG.7following a deposition of a second ILD layer on the structure (ILD1). In one embodiment, a suitable dielectric material for dielectric layer160is, for example, silicon dioxide or a low-k material. FIG.9shows the structure ofFIG.8following the formation of an opening or via through dielectric layer160to the layer defined by hardmask layer115and dielectric material150. To form opening or via165through dielectric layer160of for example, silicon dioxide, a suitable etchant is potassium hydroxide (KOH). The etch through dielectric layer160exposes both dielectric material150and hardmask layer115. In this embodiment, the opening has a diameter or width, W2, greater than a diameter or width, W1, of patterned hardmask layer115. Hardmask layer115is disposed on a metal line of metal layer112to the exclusion of dielectric material150. In this embodiment, it is desired to subsequently only remove hardmask layer115and expose the metal line of metal layer112leaving dielectric material150intact. FIG.10shows the structure ofFIG.9following the removal of dielectric layer115to expose a metal line of metal layer112. Where dielectric layer115is a traditional hardmask material such as silicon nitride, and dielectric material150is a dielectric composition of agglomerated metal oxide particles such as hafnium, zirconium, titanium, aluminum or tin oxide nanoparticles the dielectric composition of agglomerated metal oxide nanoparticles formed as described above is highly resistant to conventional hardmask etch conditions. Thus, dielectric layer115may be selectively removed and dielectric material150retained. Following the exposure of the metal layer112in opening or via165, the opening or via may be filled with a metal as a contact to another layer of the integrated circuit device as is known in the art.FIG.11shows metal170such as copper deposited in opening165and contacting a metal line of metal layer112. The above embodiment described the use of a dielectric composition including a dielectric material including agglomerated metal oxide nanoparticles with a metal such as hafnium, zirconium, titanium, aluminum or tin that has good fillability into openings such as having diameters or widths on the order of 10 nm to 30 nm and is highly etch resistant to conventional hardmask etch conditions thus providing the ability to form narrow conductive vias (narrow trenches) without voiding. In the above embodiment, a description of landing a via on a correct metal using a hardmask layer of two contrasting hardmask materials was presented.FIGS.12-14show another embodiment of a process where three contrasting hardmask materials are used. In one embodiment, the three contrasting hardmask materials may include one, two or three dielectric compositions such as described above including metal oxides including a metal such as hafnium, zirconium, titanium, aluminum or tin. FIG.12shows a portion of a substrate such as a portion of a silicon wafer including substrate205on which device layer210is formed. Overlying device layer is dielectric layer211as an ILD0 (e.g., SiO2 or a low-k material) and metal layer212therein including a number of metal lines or traces having a representative pitch on the order of 30 nm or less. Disposed on dielectric layer211is a hardmask layer including three different patterned hardmask materials, where one, two or all three of the different materials are a dielectric of metal oxide nanoparticles such as described above, (e.g., hafnium, zirconium, titanium, aluminum or tin nanoparticles). Where the hardmask layer includes more than one material of such nanoparticles, the more than one materials are different from one another in the sense that the metal cation is different. Hardmask materials of metal oxide nanoparticles may be deposited by spin coating followed by a cure to form a film. Where less than the three different patterned hardmask materials are metal oxide nanoparticles such as described above, the other(s) are, for example, a traditional hardmask material such as silicon nitride or silicon carbide. The hardmask layer of three different patterned hardmask materials may be formed according to double patterning techniques as known in the art. In the embodiment ofFIG.12, disposed on the lines of metal layer212are one of hardmask material215and hardmask material255with hardmask material250disposed there between. Disposed on the hardmask layer is dielectric layer260(e.g., SiO2 or a low-k material). FIG.13shows the structure ofFIG.12following the forming of an opening or via through dielectric layer260to expose a portion of the hardmask layer. In this embodiment, via265has a diameter that is greater than a pitch of the traces of metal layer212or is aligned over line2120A and line2120B of metal layer212.FIG.14shows the structure ofFIG.13following the opening of a via to line2120A of metal layer212. In one embodiment, the opening is formed by etching dielectric material255selectively relative to dielectric material215and relative to dielectric material250. In one embodiment, dielectric material215and dielectric material250are each a film of metal oxide nanoparticles such as described above and dielectric material255is a conventional dielectric material such as silicon nitride or silicon carbide.FIG.14shows that dielectric material215and dielectric material250are resistant to etching by conventional hardmask etchants. FIG.15illustrates interposer300that includes one or more embodiments. Interposer300is an intervening substrate used to bridge a first substrate302to second substrate304. First substrate302may be, for instance, an integrated circuit die. Second substrate304may be, for instance, a memory module, a computer motherboard, or another integrated circuit die. Generally, the purpose of interposer300is to spread a connection to a wider pitch or to reroute a connection to a different connection. For example, interposer300may couple an integrated circuit die to ball grid array (BGA)306that can subsequently be coupled to second substrate304. In some embodiments, first and second substrates302/304are attached to opposing sides of interposer300. In other embodiments, first and second substrates302/304are attached to the same side of interposer300. In further embodiments, three or more substrates are interconnected by way of interposer300. Interposer300may be formed of an epoxy resin, a fiberglass-reinforced epoxy resin, a ceramic material, or a polymer material such as polyimide. In further implementations, the interposer may be formed of alternate rigid or flexible materials that may include the same materials described above for use in a semiconductor substrate, such as silicon, germanium, and other group III-V and group IV materials. The interposer may include metal interconnects308and vias310, including but not limited to through-silicon vias (TSVs)312. Interposer300may further include embedded devices314, including both passive and active devices. Such devices include, but are not limited to, capacitors, decoupling capacitors, resistors, inductors, fuses, diodes, transformers, sensors, and electrostatic discharge (ESD) devices. More complex devices such as radio-frequency (RF) devices, power amplifiers, power management devices, antennas, arrays, sensors, and MEMS devices may also be formed on interposer300. In accordance with embodiments, apparatuses or processes disclosed herein may be used in the fabrication of interposer300. FIG.16illustrates computing device400in accordance with one embodiment. Computing device400may include a number of components. In one embodiment, these components are attached to one or more motherboards. In an alternate embodiment, these components are fabricated onto a single system-on-a-chip (SoC) die rather than a motherboard. The components in computing device400include, but are not limited to, integrated circuit die402and at least one communication chip408. In some implementations communication chip408is fabricated as part of integrated circuit die402. Integrated circuit die402may include CPU404as well as on-die memory406, often used as cache memory, that can be provided by technologies such as embedded DRAM (eDRAM) or spin-transfer torque memory (STTM or STTM-RAM). Computing device400may include other components that may or may not be physically and electrically coupled to the motherboard or fabricated within an SoC die. These other components include, but are not limited to, volatile memory410(e.g., DRAM), non-volatile memory412(e.g., ROM or flash memory), graphics processing unit414(GPU), digital signal processor416, crypto processor442(a specialized processor that executes cryptographic algorithms within hardware), chipset420, antenna422, display or a touchscreen display424, touchscreen controller426, battery428or other power source, a power amplifier (not shown), global positioning system (GPS) device444, compass430, motion coprocessor or sensors432(that may include an accelerometer, a gyroscope, and a compass), speaker434, camera436, user input devices438(such as a keyboard, mouse, stylus, and touchpad), and mass storage device440(such as hard disk drive, compact disk (CD), digital versatile disk (DVD), and so forth). Communications chip408enables wireless communications for the transfer of data to and from computing device400. The term “wireless” and its derivatives may be used to describe circuits, devices, systems, methods, techniques, communications channels, etc., that may communicate data through the use of modulated electromagnetic radiation through a non-solid medium. The term does not imply that the associated devices do not contain any wires, although in some embodiments they might not. Communication chip408may implement any of a number of wireless standards or protocols, including but not limited to Wi-Fi (IEEE 802.11 family), WiMAX (IEEE 802.16 family), IEEE 802.20, long term evolution (LTE), Ev-DO, HSPA+, HSDPA+, HSUPA+, EDGE, GSM, GPRS, CDMA, TDMA, DECT, Bluetooth, derivatives thereof, as well as any other wireless protocols that are designated as 3G, 4G, 5G, and beyond. Computing device400may include a plurality of communication chips408. For instance, a first communication chip may be dedicated to shorter range wireless communications such as Wi-Fi and Bluetooth and a second communication chip may be dedicated to longer range wireless communications such as GPS, EDGE, GPRS, CDMA, WiMAX, LTE, Ev-DO, and others. Processor404of computing device400includes one or more devices, such as transistors or metal interconnects, that are formed where connections to a devices or interconnects are formed utilizing hardmask materials including metal oxide nanoparticles describes in accordance with embodiments presented above. The term “processor” may refer to any device or portion of a device that processes electronic data from registers and/or memory to transform that electronic data into other electronic data that may be stored in registers and/or memory. Communication chip408may also include one or more devices, such as transistors or metal interconnects, that are formed where connections to adevices or interconnects are formed utilizing hardmask materials including metal oxide nanoparticles describes in accordance with embodiments presented above. In further embodiments, another component housed within computing device400may contain one or more devices, such as transistors or metal interconnects, that are formed where connections to adevices or interconnects are formed utilizing hardmask materials including metal oxide nanoparticles describes in accordance with implementations presented above. In various embodiments, computing device400may be a laptop computer, a netbook computer, a notebook computer, an ultrabook computer, a smartphone, a tablet, a personal digital assistant (PDA), an ultra mobile PC, a mobile phone, a desktop computer, a server, a printer, a scanner, a monitor, a set-top box, an entertainment control unit, a digital camera, a portable music player, or a digital video recorder. In further implementations, computing device400may be any other electronic device that processes data. EXAMPLES Example 1 is a dielectric composition including a metal oxide particle including a diameter of 5 nanometers or less capped with an organic ligand at at least a 1:1 ratio. In Example 2, the metal oxide particles of the dielectric composition of Example 1 include a metal selected from hafnium, zirconium, titanium, aluminum and tin. In Example 3, the organic ligand of the dielectric composition of Example 1 or 2 includes a carbonyl group, C(O). In Example 4, the organic ligand of the dielectric composition of Example 3 includes the formula, —C(O)R, wherein R is C1-C10. In Example 5, the dielectric composition of Example 1 further includes a casting solvent, wherein the metal oxide particles are dispersed in the casting solvent. Example 6 is a method including synthesizing metal oxide particles including a diameter of 5 nanometers or less; and capping the metal oxide particles with an organic ligand at at least a 1:1 ratio. In Example 7, synthesizing of the method of Example 6 includes a sol gel synthesis. In Example 8, synthesizing of the method of Example 6 includes reducing a metal halide. In Example 9, the metal oxide particles of any of the methods of Examples 6-8 include a metal selected from hafnium, zirconium, titanium, aluminum and tin. In Example 10, the organic ligand of any of the methods of Examples 6-8 includes a carbonyl group, C(O). In Example 11, the organic ligand of the method of Example 10 includes the formula, —C(O)R, wherein R is C1-C5. In Example 12, the methods of any of Examples 6-11 further includes dispersing the capped metal oxide particles in a casting solvent. In Example 13, the method of Example 12 further includes depositing the dispersed capped metal oxide particles on a semiconductor substrate and thermally curing to a metal oxide film on the semiconductor substrate. Example 14 is a method including forming an interconnect layer on a semiconductor substrate; forming a first hardmask material and a different second hardmask material on the interconnect layer, wherein at least one of the first hardmask material and the second hardmask material is formed over an area of interconnect layer target for a via landing and at least one of the first hardmask material and the second hardmask material include a metal oxide including a metal selected from hafnium, zirconium, titanium, aluminum and tin; forming a dielectric layer on the first hardmask material and the second hardmask material; and forming an opening to the interconnect layer through the dielectric layer and selectively through one of the first hardmask material and the second hardmask material. In Example 15, the first hardmask material of the method of Example 14 includes the metal oxide and forming an opening to the interconnect layer includes forming an opening through the second hardmask material. In Example 16, forming at least one of the first hardmask material and the second hardmask material on the interconnect layer of the method of Example 14 includes depositing a solvent dispersion including capped metal oxide particles including a diameter of 5 nanometers or less and curing the deposited dispersion. In Example 17, forming the first hardmask material and the second hardmask material of any of the methods of Examples 14-16 includes sequentially depositing the first hardmask material and the second hardmask material. In Example 18, the first hardmask material of the method of Example 17 includes the metal oxide and forming the first hardmask material follows forming the second hardmask material. In Example 19, after forming the second hardmask material, the method of Example 18 includes forming at least one opening in the second hardmask material to the interconnect and forming the first hardmask material includes forming the first hardmask material in the at least one opening. In Example 20, the at least one opening of the method of Example 19 includes at least two openings separated by a pitch of 30 nanometers or less. The above description of illustrated implementations, including what is described in the Abstract, is not intended to be exhaustive or to limit the invention to the precise forms disclosed. While specific implementations of, and examples for, the invention are described herein for illustrative purposes, various equivalent modifications are possible within the scope, as those skilled in the relevant art will recognize. These modifications may be made in light of the above detailed description. The terms used in the following claims should not be construed to limit the invention to the specific implementations disclosed in the specification and the claims. Rather, the scope of the invention is to be determined entirely by the following claims, which are to be construed in accordance with established doctrines of claim interpretation. | 30,963 |
11862464 | DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, the method for manufacturing a pillar-shaped semiconductor device according to embodiments of the present invention is described with reference to drawings. First Embodiment Hereinafter, a method for manufacturing a pillar-shaped semiconductor device having SGTs according to the first embodiment of the present invention is described with reference toFIGS.1AAto1YYC. In the figures, figures suffixed with A are plan views, figures suffixed with B are cross-sectional structural views taken along lines X-X′ in the corresponding figures suffixed with A, and figures suffixed with C are cross-sectional structural views taken along lines Y-Y′ in the corresponding figures suffixed with A. As shown inFIGS.1AA to1AC, an N layer2is formed on a P layer substrate1by an epitaxial crystal growth method. Then, an N+layer3and P+layers4,5are formed on a surface layer of the N layer2by an ion implantation method. Then, an i layer (intrinsic Si layer)6is formed. Then, a mask material layer7consisting of, for example, a SiO2layer, an aluminum oxide (Al2O3, hereinafter referred as AlO) layer and a SiO2layer is formed. Also, the i layer6may be formed by N-type or P-type Si, which contains a small amount of donor or acceptor impurity. Then, a silicon nitride (SiN) layer8is deposited. Then, a mask material layer9consisting of a SiO2layer is deposited. Then, a mask material layer10consisting of a SiN layer is deposited. Next, as shown inFIGS.1BA to1BC, the mask material layer10is etched with a lithographically formed band-like resist layer (not shown) extended in Y direction in planar view as a mask. A band-like mask material layer10aextended in the Y direction in planar view is thus formed. Here, the band-like mask material layer10amay be subjected to an isotropic etching such that the width of the band-like mask material layer10ais formed to become smaller than the width of the resist layer. Thus, it may be possible to form a band-like mask material layer10ahaving a width smaller than the smallest width of a resist layer which can be formed lithographically. Then, the mask material layer9is etched, for example by RIE (Reactive Ion Etching), with the band-like mask material layer10aas an etching mask, to form a band-like mask material layer9a. While the band-like mask material layer10aformed by the isotropic etching has a trapezoidal cross section with its bottom width being wider than its top width, the mask material layer9ais etched by RIE, and thus has a rectangular cross section. This rectangular cross section leads an enhanced precision of etching pattern, which is etched with the band-like mask9aas a mask. Next, as shown inFIGS.1CA to1CC, the mask material layer8is etched, for example by RIE method with the band-like mask material layer9aas a mask to form a band-like mask material layer8a. The band-like mask material layer10amay be removed prior to the etching of the mask material layer8or may remain. Next, as shown inFIGS.1DA to1DC, a SiGe layer12and a SiO2layer13are entirely formed over the mask material layer7(first material layer), the band-like mask material layer8a(second band-like material layer) and the layer9a(first band-like material layer) by ALD (Atomic Layered Deposition) method. In this case, a cross section of the SiGe layer12(second material layer) provides a round part R1at its top. It is desirable to form the round part R1to be positioned above the band-like mask material layer8a. Next, as shown inFIGS.1EA to1EC, the entire area is covered with a SiO2layer (not shown) for example by Flow CVD (Flow Chemical Vapor Deposition) method, and then the SiO2layer13(third material layer) and the SiGe layer12are polished by CMP (Chemical Mechanical Polishing) such that their upper surface positions come to the upper surface position of the band-like mask material layer9ato form a SiO2layer13aand SiGe layers12a,12b. In this case, it is desirable that the top side surfaces of the SiGe layers12a,12bare vertical. For this purpose, it is desirable that the round part R1of the top of the SiGe layer12inFIG.1DBhas been removed during the polishing process of the SiO2layer13and the SiGe layer12. Next, as shown inFIGS.1FA to1FC, each of the top of the SiGe layers12a,12bis etched with the SiO2layer13and the band-like mask material layer9aas a mask to form recesses14a,14b(first recess). It is desirable that the bottom positions of the recesses14a,14bcome to the lower position of the mask material layer9aand that the round part R1of the top of the SiGe layers12a,12bhas been etched. During the polishing process of the SiO2layer and the SiGe layer12, the round part R1of the top of the SiGe layer12inFIG.1DBis removed, and thus the recesses14a,14bhaving vertical peripheral side surfaces are formed. Next, as shown inFIGS.1GA to1GC, the entire area is covered with a SiN layer (not shown), and the SiN layer is entirely polished by CMP method such that its upper surface position comes to the upper surface position of the mask material layer9a. Thus, SiN layers15a,15b(third band-like material layer) having the same shape as the shape of the top of the SiGe layers12a,12bin planar view are formed at each side of the band-like mask material layers8a,9a. Then, as shown inFIGS.1HA to1HC, the SiO2layer13is removed. Next, as shown inFIGS.1IA to1IC, the SiGe layers12a,12bare etched with the band-like mask material layers9a,15a,15bas a mask to form band-like SiGe layers12aa,12ab(fourth band-like material layer). In this case, the band-like SiGe layer12aaand the band-like SiGe layer12abhave the same width in planar view. Next, as shown inFIGS.1JA to1JC, a SiN layer16by ALD method and a SiO2layer13bby FCVD method are formed to cover the entire area. In this case, similar toFIG.1DB, a round part R2provided at the top of the SiN layer16(fourth material layer) is desirably positioned above the band-like mask material layer9a. Next, the SiO2layer13b(fifth material layer) and the SiN layer16are polished such that their upper surface positions come to the same position as the upper surface of the mask material layer9a. Then, by performing processes similar to those ofFIGS.1EA and1FC, recesses14A,14B (second recess) are formed above band-like SiN layers16A,16B, and between band-like mask material layers15a,15band a SiO2layer13ba, as shown inFIGS.1KA to1KC. As shown inFIGS.1LA to1LC, band-like SiN layers16a,16bin contact with each side surface of the band-like SiGe layers12aa,12ab, and band-like mask material layers17a,17b(fifth band-like material layer) in contact with each side surface of the band-like mask material layers15a,15bare formed. Next, a SiGe layer (not shown) is formed by ALD method to cover the entire area. Then, a SiO2layer (not shown) is formed to cover the entire area. Then, the SiO2layer and the SiGe layer are polished such that their upper surface positions come to the same position as the upper surface of the band-like mask material layer9a. Then, by performing processes similar to those ofFIGS.1EA to1IC, band-like SiGe layers18a,18bin contact with each side surface of the band-like mask material layers16a,16b(sixth band-like material layer), and band-like mask material layers19a,19bin contact with each side surface of the band-like mask material layers17a,17bare formed, as shown inFIGS.1MA to1MC. Next, a SiN layer (not shown) is formed by ALD method to cover the entire area. Then, a SiO2layer (not shown) is formed to cover the entire area. Then, the SiO2layer and the SiN layer are polished such that their upper surface positions come to the same position as the upper surface of the band-like mask material layer9a. Then, by performing processes similar to those ofFIGS.1EA to1IC, band-like mask material layers20a,20bin contact with each side surface of the band-like mask material layers18a,18b, and band-like mask material layers21a,21bin contact with each side surface of the band-like mask material layers19a,19bare formed, as shown inFIGS.1NA to1NC. Next, the band-like mask material layers15a,15b,19a,19band the band-like SiGe layers12aa,12ab,18a,18bare removed by etching. Thus, as shown inFIGS.1OA to1OC, band-like mask material layers8a,16a,16b,20a,20band the mask material layers9a,17a,17b,21a,21bon the band-like mask material layers8a,16a,16b,20a,20bare formed on the mask material layer7. Next, the entire area is covered with a SiO2layer (not shown). Then, as shown inFIGS.1PA to1PC, the SiO2layer is polished by CMP method such that its upper surface position comes to the upper surface position of the band-like mask material layer9ato form a SiO2layer22. Then, a SiN layer24and a SiGe layer (not shown) are entirely formed. Then, a band-like mask material layer26(eighth band-like material layer) of SiN layer extended in X direction is formed. Then, the SiGe layer is etched by lithography and RIE method with the formed band-like mask material layer26as a mask to form a band-like SiGe layer25(ninth band-like material layer) extended in X direction. Next, by performing processes similar to those ofFIGS.1CA to1IC(processes similar toFIGS.1CA to1ICare performed as processes for forming sixth material layer, seventh material layer, third recess, tenth band-like material layer, and eleventh band-like material layer), band-like mask material layers28a,28b(seventh band-like material layer) of SiN layer in contact with each side surface of the band-like SiGe layer25and band-like mask material layers27a,27b(seventh band-like material layer) consisting of SiO2layer, AlO layer, SiO2layer in contact with each side surface of the band-like mask material layer26are formed, as shown inFIGS.1QA to1QC. Next, as shown inFIGS.1RA to1RC, the band-like mask material layer26and the band-like SiGe layer25are removed to form band-like mask material layers28a,28band band-like mask material layers27a,27bon the band-like mask material layers28a,28b, extended in X direction in planar view, on the SiN layer24. Next, as shown inFIGS.1SA to1SC, the SiN layer24, the band-like mask material layers9a,17a,17b,21a,21b,8a,16a,16b,20a,20b, and the SiO2layer22are etched with the band-like mask material layers27a,27b,28a,28bas a mask. Thus, a band-like SiN layer24a, and in planar view, square-shaped mask material layers21aa,21ab,17aa,17ab,9aa, and square-shaped mask material layer20aa,20ab,16aa,16ab,8aalocated under the square-shaped mask material layers21aa,21ab,17aa,17ab,9aaare formed under the band-like mask material layers27a,28a. Similarly, a band-like SiN layer24b, and in planar view, square-shaped mask material layers21ba,21bb,17ba,17bb,9ab, and square-shaped mask material layer20ba(not shown),20bb(not shown),16ba(not shown),16bb(not shown),8ablocated under the square-shaped mask material layers21ba,21bb,17ba,17bb,9abare formed under the band-like mask material layers27b,28b. Also, at the same time, a SiO2layer22ais formed under the band-like SiN layer24aand between the square-shaped mask material layers21aa,21ab,17aa,17ab,9aa,20aa,20ab,16aa,16ab,8aa. Similarly, a SiO2layer22b(not shown) is formed under the band-like SiN layer24band between the square-shaped mask material layers21ba,21bb,17ba,17bb,9ab,20ba,20bb,16ba,16bb,8ab. Next, as shown inFIGS.1TA to1TC, the band-like mask material layers27a,27b,28a,28b, the band-like SiN layers24a,24band the SiO2layers22a,22bare removed. Thus, in planar view, square-shaped mask material layers21aa,21ab,21ba,21bb,17aa,17ab,17ba,17bb,9aa,9aband square-shaped mask material layers20aa,20ab,20ba,20bb,16aa,16ab,16ba,16bb,8aa,8abare formed on the mask material layer7. Next, the mask material layer7is etched by RIE method with the mask material layers21aa,21ab,21ba,21bb,17aa,17ab,17ba,17bb,9aa,9aband the mask material layers20aa,20ab,20ba,20bb,16aa,16ab,16ba,16bb,8aa,8abas a mask. Then, the mask material layers21aa,21ab,21ba,21bb,17aa,17ab,17ba,17bb,9aa,9aband the material layers20aa,20ab,20ba,20bb,16aa,16ba,16bb,16ab,8aa,8abare removed. Thus, as shown inFIGS.1UA to1UC, mask material layers7a,7b,7c,7d,7e,7f,7g,7h,7i,7j(first mask material layer) are formed on the i layer6. For example, before the RIE etching of the mask material layer7, either or both of the square-shaped mask material layers21aa,21ab,21ba,21bb,17aa,17ab,17ba,17bb,9aa,9aband the square-shaped mask material layers20aa,20ab,20ba,20bb,16aa,16ab,16ba,16bb,8aa,8abare slightly etched isotropically. This makes mask material layers7ato7jcircular shape in planar view. Next, as shown inFIGS.1VA to1VC, the i layer6is etched with the mask material layers7ato7jas a mask to form Si pillars6a,6b,6c,6d,6e,6f,6g,6h,6i,6j(three-dimensionally-shaped semiconductor layer) on the N+layer3and the P+layer4. Next, a SiO2layer (not shown) is deposited by FCVD method, and then polished by CMP method such that its surface position comes to the top position of the mask material layers7ato7j. Then, the mask material layers7b,7iand the Si pillars6b,6iare removed by lithography and RIE etching method. Then, the SiO2layer formed by the FCVD method is removed. Thus, as shown inFIGS.1WA to1WC, the Si pillars6a,6c,6d,6e,6f,6g,6h,6jare formed on the N+layer3and the P+layers4,5. Next, as shownFIGS.1XA to1XC, mask material layers30a,30b,30c,30dsurrounding side surfaces of the mask material layers7ato7j(the mask material layers7b,7iare absent) and mask material layers31a,31b,31c,31d(not shown) surrounding side surfaces of the Si pillars6ato6j(the Si pillars6b,6iare absent) are formed. Then, a SiO2layer (not shown) is deposited over the entire area by FCVD method, and then polished by CMP method such that its surface position comes to the top position of the mask material layers7ato7j(mask material layers7b,7iare absent). Then, on the smoothed face, in planar view, a band-like mask material layer33aof, for example, SiO2layer, linked to the Si pillars6a,6c,6d,6e, and a band-like mask material layer33bof, for example, SiO2layer, linked to the Si pillars6f,6g,6h,6jare formed. Then, the SiO2layer, the N+layer3, the P+layers4,5, the N layer2, and the P layer1are etched by RIE with the mask material layers30a,30b,30c,30d,7ato7j,33a, and33bas a mask. Thus, N layer2a, N+layers3a,3band a P+layer4aare formed under the Si pillars6a,6c,6d,6eand on the P layer1. Similarly, an N layer2b, N+layers3c(not shown),3d(not shown) and a P+layer5aare formed under the Si pillars6f,6g,6h,6jand on the P layer1. Then, a SiO2layer32ais formed under the mask material layer33aand between the Si pillars6aand6c. Similarly, a SiO2layer32b(not shown) is formed under the mask material layer33band between the Si pillars6hand6j. Next, as shown inFIGS.1YA to1YC, the mask material layers33a,33b, the SiO2layers32a,32b, and the mask material layers30a,30b,30c,30d,31a,31b,31c,31dare removed. Next, as shown inFIGS.1ZA to1ZC, a SiO2layer34is formed on the periphery of the N+layers3a,3b,3c,3d, the P+layer4a,5a, and the N layer2a,2band on the P layer substrate1. Then, a HfO2layer (not shown), a TiN layer (not shown), and a SiO2layer (not shown) are formed over the entire area by ALD method. In this case, the TiN layers between the Si pillars6c,6d, and6eare desirably in contact with each other at their side surfaces. Similarly, the TiN layers between the Si Pillars6f,6g, and6hare desirably in contact with each other at their side surfaces. Then, the HfO2layer, the TiN layer and the SiO2layer are polished by CMP method such that their upper surface positions come to the upper surface position of the mask material layers7ato7j. Then, the SiO2layer is etch-backed by RIE method. Then, the TiN layer and the HfO2layer are etched with the SiO2layer as a mask such that their upper surface positions come to the upper positions of the Si pillars6ato6j. Then, a SiN layer (not shown) is formed over the entire area by CVD method. Then, the SiN layer is polished by CMP method such that its upper surface position comes to the upper surface position of the mask material layers7ato7j. Thus, SiN layers37a,37b,37c,37d(not shown) having equal width in planar view are formed on the periphery of the top of the Si pillars6ato6j. Then, mask material layers38a,38b,38c,38drespectively contacting the Si pillars6a,6d,6g,6jin planar view are formed on the mask material layers7ato7j. Then, the SiO2layer and the TiN layer on the periphery of the mask material layers37a,37b,37c,37din planar view are etched with the mask material layers7ato7j,37a,37b,37c,37d,38a,38b,38c,38das a mask. Thus, a TiN layer40alinked to the periphery of the Si pillar6a, a TiN layer40blinked to the periphery of the Si pillars6c,6d,6e, a TiN layer40clinked to the periphery of the Si pillars6f,6g,6h, and a TiN layer40d(not shown) linked to the periphery of the Si pillar6jare formed. Then, the mask material layers38ato38d,37ato37d, and7ato7jare removed. Next, as shown in FIGS.1XXA to1XXC, the entire area is covered with a SiO2layer (not shown) and then the SiO2layer is polished by CMP method such that its upper surface position comes to the upper surface position of the top of the Si pillars6ato6j. Then, an upper portion of the SiO2layer is etched by RIE method until its upper surface position comes to the top position of the TiN layers40ato40d. Then, a SiN layer42is formed on the periphery of the top of the Si pillars6ato6j. Then, after the top of the Si pillar6c,6his covered with a SiO2layer (not shown), an N+layer43acontaining donor impurities is formed around the top of the Si pillar6aby selective epitaxial crystal growth method. At the same time, an N+layer43ccovering the top of the Si pillar6d, an N+layer43d(not shown) covering the top of the Si pillar6e, an N+layer43e(not shown) covering the top of the Si pillar6f, an N+layer43f(not shown) covering the top of the Si pillar6g, and an N+layer43h(not shown) covering the top of the Si pillar6jare formed. Then, the SiO2layer covering the top of the Si pillars6c,6his removed. Then, a SiO2layer (not shown) is formed over the Si pillars6a,6d,6e,6f,6g,6j. Then, P+layers43b,43gcontaining acceptor impurities are formed around the top of the Si pillars6c,6hby selective epitaxial crystal growth method. Then, the donor impurities in the N+layers43a,43c,43d,43e,43f,43hare diffused into the top of the Si pillars6a,6d,6e,6f,6g,6jby heat treatment to form N+layers44a,44c,44d,44e(not shown),44f(not shown),44h(not shown). At the same time, the acceptor impurities are diffused from the P+layers43b,43gto form P+layers44b,44g. Next, as shown in FIGS.1YYA to1YYC, a SiO2layer46having a flat upper surface is formed over the entire area. Then, a connection line metal layer C1is formed via a contact hole47aformed on the interface between the N+layer3aand the P+layer4aand on the TiN layer40b. At the same time, a connection line metal layer C2(not shown) is formed via a contact hole47bformed on the interface between the N+layer3dand the P+layer5aand on the TiN layer40b. A SiO2layer48having a flat upper surface is formed over the entire area. Then, a word line metal layer WL is formed via contact holes49a,49bformed on the TiN layer40a,40d. A SiO2layer50having a flat upper surface is formed over the entire area. Then, a ground line metal layer Vss1is formed via contact holes51a,51bformed on the N+layers43c,43d. At the same time, a ground line metal layer Vss2is formed via contact holes51c,51dformed on the N+layers43e,43f. Then, a SiO2layer52having a flat upper surface is formed over the entire area. Then, a supply line metal layer Vdd is formed via contact holes53a,53bformed on the P+layers43b,43g. Then, a SiO2layer54having a flat upper surface is formed over the entire area. Then, a bit output line metal layer BL and a reverse bit output line metal layer RBL are formed via contact holes55a,55bformed on the N+layer43a,43h. Thus, a SRAM cell circuit is formed on the P layer substrate1. According to the manufacturing method of the first embodiment, following features are provided. 1. In this embodiment, as shown inFIGS.1VA to1VC, ten Si pillars6ato6jare formed in one SRAM cell area. In these pillars, lithography is only used to form band-like SiN layer8afor forming Si pillars (6c,6h) in a row in X direction. Other eight Si pillars (6ato6jexcluding6c,6h) are formed by band-like SiGe layers12aa,12ab,18a,18band band-like SiN layer16a,16b,20a,20bformed by ALD method. Band-like SiGe layers12a,12bare formed by ALD method, and on the band-like SiGe layers12a,12b, band-like mask material layers15a,15b, having a shape in which the shape of top part of the band-like SiGe layers12a,12bremains as it is, are formed. In ALD method, a material layer can be deposited in each monoatomic or monomolecular layer in controlled manner. Thus, a thickness of band-like SiGe layers12a,12bin planar view can be thin with high precision, depending on design requirement. This makes it possible to narrow distances between Si pillars7ato7jwith high precision without constraints of lithography. Thus, high integration of SRAM cell can be provided. Also, when distance between only the Si pillars6c,6hand the Si pillars6b,6d,6g,6iin X direction are to be formed with high precision and as being the narrowest, only the band-like SiGe layers12aa,12ab, and the band-like mask material layers15a,15bmay be formed by the manufacturing method provided in the present invention. 2. Similarly, band-like SiN layers16A,16B are formed by ALD method, and on the band-like SiN layers16A,16B, band-like mask material layers17a,17b, having a shape in which the shape of top part of the band-like SiN layers16A,16B remains as it is, are formed. Thus, diameters of the Si pillars7ato7jin planar view can be reduced with high precision, without constraints of lithography. This makes it possible to design cells without limitation for high integration of cells due to lithography. Thus, high precision and high integration of SRAM cell can be provided. 3. As high integration of cell proceeds, it is required that both diameters of Si pillar6ato6jin planar view and distances between the Si pillars6ato6jare made to be high precision and high density. For this purpose, in this embodiment, as shown inFIGS.1DA to10C, both band-like SiGe layers12aa,12ab,18a,18band band-like SiN layers16a,16b,20a,20bon each side of band-like SiN layer8acan be formed with high precision and narrow, in a cross-section in X direction. High precision of the thickness of the band-like SiN layers16a,16b,20a,20bleads to high precision of the diameter of the Si pillar6ato6j. Then, high precision of the thickness of the band-like SiGe layers12aa,12ab,18a,18bleads to high precision of the distance between the Si pillars6ato6j. Thus, high precision and high integration of SRAM cell can be provided. 4. When SiGe layers12a,12band SiN layers16A,16B are etched by RIE method, portions of band-like mask material layers15a,15b,17a,17bwhere etching ion is impacted are etched, although the etching rate is low. When the band-like mask material layers15a,15b,17a,17bhave a trapezoidal shape having a bottom side longer than a top side, for example, a portion of the bottom side of the band-like mask material layers15a,15b,17a,17bis etched during etching. Thus, end positions of mask layer of the band-like mask material layers15a,15b,17a,17bare changed over etching time in planar view. This makes it difficult to form the band-like SiGe layers12aa,12aband the band-like SiN layers16a,16brectangular in cross-sectional view. On the other hand, in this embodiment, SiGe layers12a,12band SiN layers16A,16B having a same thickness in vertical direction are formed on each side of the band-like SiN layer8aand band-like mask material layer9a. Then, band-like mask material layers15a,15b,17a,17b, having a shape in which the shape of top part of SiGe layers12a,12band the SiN layers16A,16B remains as it is, are formed. Thus, band-like mask material layers15a,15b,17a,17bhaving a rectangular cross-section are formed. Furthermore, SiGe layers12a,12band SiN layers16A,16B are etched with the band-like mask material layers15a,15b,17a,17bhaving a rectangular cross-section as a mask to form band-like SiGe layer12aa,12aband band-like SiN layer16a,16bhaving a rectangular cross-section. Thus, high precision and high integration of SRAM cell can be provided. 5. For example, as shown inFIGS.1EA to1IC, in band-like mask material layers15a,15bwhich are an etching mask for band-like SiGe layers12aa,12ab, SiGe layer12is deposited over band-like SiN layer8aand band-like mask material layer9aby ALD method. Then, a SiO2layer (not shown) is deposited. Then, the SiO2layer and the SiGe layer12are polished by CMP method such that their upper surface positions come to the upper surface position of the band-like mask material layer9a. Upper round parts R1of SiGe layer12are removed by this polishing. By removing the upper round part R1, shapes of recesses14a,14bare formed so as to conform with shapes of side surfaces of the band-like mask material layer9aand SiO2layer13on each side of SiGe layer12a,12b, and to conform with shapes of band-like SiGe layers12a,12bhaving equal width in vertical direction. Thus, cross-sectional shapes of the recesses14a,14bare formed substantially rectangular. Thus, overall cross-sectional shapes of band-like mask material layers15a,15bare made to be substantially rectangular with their width remaining equal in vertical direction. This indicate that band-like SiGe layers12aa,12ab, which are formed by etching SiGe layer12aby RIE method with the band-like mask material layers15a,15bas a mask, can be formed with high precision both in planar view and cross-sectional view. Similarly, band-like SiN layer16a,16b,20a,20band band-like SiGe layer18a,18bcan be formed with high precision. 6. In this embodiment, as shown inFIGS.1ZA to1ZC, each of gate TiN layers40b,40crespectively linked to the periphery of Si pillars7c,7d,7eand Si pillars7f,7g,7hcontacts at side surface between the Si pillars7c,7dand7e, and between the Si pillars7f,7gand7h. On the other hand, gate TiN layers40a,40dare formed independently at Si pillars6a,6j. The fact that each of the gate TiN layers40b,40crespectively linked to the periphery of Si pillars7c,7d,7eand Si pillars7f,7g,7hcontacts at side surface between Si pillars7c,7dand7eand between Si pillars7f,7gand7hindicates that it is possible to reduce a distance between Si pillars7c,7dand7eand between Si pillars7f,7gand7hto such a length corresponding to twice of a sum of a thickness of a gate HfO2layer35and a thickness of gate TiN layers40b,40c. Then, as shown inFIGS.1WA to1WC, by removing Si pillars7b,7i, gate TiN layers40a,40dcan be formed to be separated from the gate TiN layers40b,40c. This can be done, as shown inFIGS.1WA to1WC, by forming Si pillars6ato6jat high density in planar view, followed by removing Si pillars7b,7ito form areas having no Si pillar in planar view. Thus, contact holes47a,47bcan be formed on the areas of the removed Si pillars7b,7iin planar view. Thus, SRAM cell can be provided at high density. This embodiment can be applied not only to the SRAM cell, but also to a circuit having a plurality of Si pillars in which gate conductor layers are connected with each other, and one or more Si pillars having gate conductor layers adjacent thereto and separated. 7. In this embodiment, as described inFIGS.1PA to1SC, band-like mask material layers27a,27b,28a,28bextended in X direction are formed to be orthogonal to band-like mask material layers8a,16a.16b,20a,20bextended in Y direction by a method similar to the method for forming the band-like mask material layers8a,16a.16b,20a,20b. This makes it possible to form Si pillars6ato6jwith high precision and at high density both in X and Y directions. Also, in the description of the embodiment, the band-like mask material layers28a,28bare formed after forming the band-like mask material layers8a,16a,16b,20a,20b. On the other hand, it may be also possible to form Si pillars6ato6jwith high precision and at high density by a process in which the band-like mask material layers8a,16a,16b,20a,20bare formed after forming the band-like mask material layers28a,28b. Further, in designing, when there is enough room in Y direction, the band-like mask material layers27a,27b,28a,28bmay be directly formed by lithography and RIE etching method after entirely forming a mask material layer, without using this method. Also, when there is enough room in X direction, the band-like mask material layers8a,16a,16b,20a,20bor the band-like mask material layers9a,17a,17b,21a,21bmay be directly formed by lithography and RIE etching method after entirely forming a mask material layer, without using this method. 8. In this embodiment, as shown inFIGS.10A to10C, five band-like SiN layers8a,16a,16b,20a,20bextended in Y direction in planar view are formed. On the other hand, by changing the material of the band-like SiN layer8afrom SiN to SiGe, and changing the material of the band-like SiGe material layer12aa,12abto SiN, two band-like SiN layers extended parallel to Y direction in planar view can be formed. Si pillars can be thus formed at high density at positions of these two band-like SiN layers in planar view. This makes it possible to form three, four, five or more band-like SiN layers extended in Y direction in planar view depending on the material of the band-like material layer consisting of the band-like SiN layer8awhich is formed first and the band-like mask material layer9a, the material of the band-like SiN layer and the band-like mask material layer formed parallelly on each side of this band-like material layer, in planar view, and times repeated for forming the band-like SiN layer or the band-like SiGe layer. Si pillars at high density can be thus formed at positions of these band-like SiN layers in a plane. Second Embodiment Hereinafter, a method for manufacturing a pillar-shaped semiconductor device having SGTs according to the second embodiment of the present invention is described with reference toFIGS.2AA to2DC. In the figures, figures suffixed with A are plan views, figures suffixed with B are cross-sectional structural views taken along lines X-X′ in the corresponding figures suffixed with A, and figures suffixed with C are cross-sectional structural views taken along lines Y-Y′ in the corresponding figures suffixed with A. Processes similar to those shown inFIGS.1AA to1LCare performed. In these processes, the arrangement of N+layer3and P+layer4inFIGS.1AA to1ACis different in planar view, and as shown inFIGS.2AA to2AC, band-like N+layers3A,3B are formed at each side of a P+layer4A. Then, SiGe layers12Aa,12Ab wider than the band-like SiGe layers12aa,12abare formed at each side of the band-like SiN layer8ahaving a band-like mask material layer9aon its top, in planar view. Also, band-like mask material layers15A,15B are respectively formed on top of the SiGe layers12Aa,12Ab. Then, band-like SiN layers16A,16B having width the same as that of the band-like SiN layer8a, respectively having band-like mask material layers17A,17B on its top, are formed at each side of the band-like SiGe layers12Aa,12Ab. Then, processes the same asFIGS.1NA to1TCare performed. As shown inFIGS.2BA to2BC, square-shaped SiN layers8Aa,8Ab,16Aa,16Ab (not shown),16Ba,16Bb (not shown) respectively having square-shaped mask material layers9Aa,9Ab,17Aa,17Ab,17Ba,17Bb on its top in planar view are thereby formed on a mask material layer7. Then, same processes as shown inFIGS.1UA to1VCare performed. Thus, as shown inFIGS.2CA to2CC, Si pillars61a,61c,61d,61fare formed on N+layer3A,3B. At the same time, Si pillars61b,61eare formed on P+layer4A. Then, same processes as shown inFIGS.1XAto1YYC are performed. Thus, as shown inFIGS.2DA to2DC, N layer2A, N+layers3Aa,3Ba and P+layer4Aa are formed under Si pillars61a,61b,61c. Similarly, N layer2B, N+layers3Ba (not shown),3Bb (not shown) and P+layer4Ba are formed under Si pillars61d,61e,61f. Then, SiO2layer33is formed surrounding lower part of the Si pillars61ato61f. Then, a HfO2layer63, which is a gate insulating layer, is formed surrounding the Si pillars61ato61f. Then, gate TiN layers65a,65b,65c,65d(not shown), and SiO2layer41are formed surrounding the HfO2layer63. Then, SiN layer42is formed on the periphery of the top of the Si pillars61ato61f. Then, N+layers67a,67c,67d,67f, and P+layers67b,67eare formed on the top of the Si pillars61ato61fby selective epitaxial crystal growth method. Then, heat treatment is applied to form N+layers66a,66c,66d(not shown),66f(not shown), and P+layers66b,66eon the top of the Si pillars61ato61f. Then, after the SiO2layer46is formed entirely, the N+layer3Aa, the P+layer4Aa, and the gate TiN layer65care connected by a metal layer (not shown) via a contact hole69aformed on the interface between the N+layer3Aa and the P+layer4Aa and on the gate TiN layer65c. At the same time, the N+layer3Bb, the P+layer4Ba, and the gate TiN layer65bare connected by a metal layer (not shown) via a contact hole69bformed on the interface between the N+layer3Bb and the P+layer4Ba and on the gate TiN layer65b. Then, after the SiO2layer48is formed entirely, the gate TiN layers65a,65dand a word line metal layer WL are connected via a contact hole70aformed on the gate TiN layer65aand a contact hole70bformed on the gate TiN layer65d. Then, after the SiO2layer50is formed entirely, the P+layers67b,67eand a supply line metal layer Vdd are connected via contact holes71a,71bformed on the P+layers67b,67e. Then, after the SiO2layer52is formed entirely, the N+layer67aand a ground line metal layer Vss1are connected via a contact hole73a. At the same time, the N+layer67fand a ground line metal layer Vss2are connected via a contact hole73b. Then, after the SiO2layer54is formed entirely, the N+layer67cand a bit line metal layer BL are connected via a contact hole74a. At the same time, the N+layer67dand a reverse bit line metal layer RBL are connected via a contact hole74b. Thus, a SRAM cell is formed on a P layer substrate1. According to the manufacturing method of this embodiment, following features are provided. 1. In the first embodiment, five band-like SiN layers8a,16a,16b,20a,20bare formed on a mask material layer7as shown inFIGS.1NA to1NC. On the other hand, in this embodiment, a SRAM cell can be formed by forming three band-like SiN layers8a,16A,16B as shown inFIGS.2AA to2AC. This makes it possible to simplify the processes. 2. In the first embodiment, as shown inFIGS.1VA to1VC, the process for removing the Si pillars6b,6iformed in the SRAM cell was necessary. On the other hand, in the present invention, such process for removing Si pillars is unnecessary. This makes it possible to simplify the processes. Third Embodiment Hereinafter, a method for manufacturing a pillar-shaped semiconductor device having SGTs according to the third embodiment of the present invention is described with reference toFIGS.3AA to3FC. In the figures, figures suffixed with A are plan views, figures suffixed with B are cross-sectional structural views taken along lines X-X′ in the corresponding figures suffixed with A, and figures suffixed with C are cross-sectional structural views taken along lines Y-Y′ in the corresponding figures suffixed with A. As shown inFIGS.3AA to3AC, at first, a band-like SiGe layer80(second band-like material layer) is formed with a band-like mask material layer81(first band-like material layer) as an etching mask, instead of a band-like SiN layer8aand a mask material layer9ashown inFIGS.1CA to1CC. Then, processes similar to those shown inFIGS.1DA to1MCare performed. Thus, as shown inFIGS.3BA to3BC, on each side of the band-like SiGe layer80having the band-like mask material layer81on its top, band-like SiN layers82a,82b(fourth band-like material layer) having band-like mask material layer layers83a,83b(third band-like material layer of equal width on their top are formed. Then, on each side of the band-like SiN layers82a,82b, band-like SiN layers84a,84bhaving band-like mask material layers85a,85bof equal width on their top are formed. Then, on each side of the band-like SiGe layers84a,84b, band-like SiN layers86a,86bhaving band-like mask material layers87a,87bon their top are formed. Then, processes similar to those shown inFIGS.1NA to1TCare performed. Thus, as shownFIGS.3CA to3CC, in planar view, square-shaped SiN layers90a,90b,90c,90d,90e(not shown),90f(not shown),90g,90h(not shown) having square-shaped mask material layers91a,91b,91c,91d,91e,91f,91g,91h(first mask material layer) on their top are formed on a mask material layer7. Then, same processes as shown inFIGS.1UA to1VCare performed. Thus, as shown inFIGS.3DA to3DC, Si pillars93a,93b,93c,93d,93e,93f,93g,93h(three-dimensionally-shaped semiconductor layer) having mask material layers92a,92b,92c,92d,92e,92f,92g,92hon their top are formed on N+layer3cand P+layers4c,4d. Then, as shown inFIGS.3EA to3EC, mask material layers92b,92gand Si pillars93b,93gare removed. Then, same processes as shown inFIGS.1ZAto1YYC are performed. Thus, as shown inFIGS.3FA to3FC, N layer2ca, N+layers3ca,3cband P+layer4caare formed under Si pillars93a,93c,93d. Similarly, N layer2cb, N+layers3da(not shown),3dband P+layer4cb(not shown) are formed under Si pillars93e,93f,93h. Then, a HfO2layer95, which is a gate insulating layer, is formed surrounding the Si pillars93ato93h. Then, gate TiN layers96a,96b,96c,96d(not shown) are formed surrounding the HfO2layer95. Then, N+layers98a,98c,98d(not shown),98f(not shown) are formed on the top of the Si pillars93a,93d,93e,93h, and N+layers97a,97c,97d(not shown),97e(not shown) are formed on the top of the Si pillars93a,93d,93e,93h. Also, P+layers98b,98e(not shown) are formed on the top of the Si pillars93c,93f, and P+layers97b,97e(not shown) are formed on the top. Then, the N+layer3ca, the P+layer4ca, and the gate TiN layer96care connected by a metal layer (not shown) via a contact hole99aformed on the interface between the N+layer3caand the P+layer4caand on the gate TiN layer96c. At the same time, the N+layer3db, the P+layer4cb, and the gate TiN layer96bare connected by a metal layer (not shown) via a contact hole99bformed on the interface between the N+layer3dband the P+layer4cband on the gate TiN layer96b. Then, the gate TiN layers96a,96dand a word line metal layer WL are connected via a contact hole101aformed on the gate TiN layer96aand a contact hole101bformed on the gate TiN layer96d. Then, the P+layers98b,98eand a supply line metal layer Vdd are connected via contact holes102a,102bformed on the P+layers98b,98e. Then, the N+layer98cand a ground line metal layer Vss1are connected via a contact hole103a. At the same time, the N+layer98dand a ground line metal layer Vss2are connected via a contact hole103b. Then, the N+layer98aand a reverse bit line metal layer RBL are connected via a contact hole104A. At the same time, the N+layer98fand a bit line metal layer BL are connected via a contact hole104B. Thus, a SRAM cell is formed on a P layer substrate1. According to the manufacturing method of this embodiment, following features are provided. 3. In the first embodiment, five band-like SiN layers8a,16a,16b,20a,20bare formed on a mask material layer7as shown inFIGS.1NA to1NC. On the other hand, in this embodiment, four band-like SiN layers82a,82b,86a,86bmay be formed to form a SRAM cell as shown inFIGS.3BA to3BC. This makes it possible to simplify the processes. 4. In this embodiment, similar to the first embodiment, each of gate TiN layers96b,96c, which are respectively linked to periphery of Si pillars93c,93dand Si pillars93e,93f, contacts at side surface between the Si pillars93cand93dand between the Si pillars93eand93f. On the other hand, gate TiN layers96a,96dare formed independently at the Si pillars93a,93h. Thus, the fact that each of the gate TiN layers96b,96ccontacts at side surface between the Si pillars93cand93dand between Si pillars93eand93findicates that it is possible to reduce a distance between Si pillars93cand93dand between Si pillars93eand93fto such a length corresponding to twice of a sum of a thickness of gate HfO2layer95and a thickness of gate TiN layers96b,96c. Thus, high integration of SRAM cell can be provided. Fourth Embodiment Hereinafter, a method for manufacturing a pillar-shaped semiconductor device having SGTs according to the fourth embodiment of the present invention is described with reference toFIGS.4AA to4BC. In the figures, figures suffixed with A are plan views, figures suffixed with B are cross-sectional structural views taken along lines X-X′ in the corresponding figures suffixed with A, and figures suffixed with C are cross-sectional structural views taken along lines Y-Y′ in the corresponding figures suffixed with A. Processes ofFIGS.1AA to1RCare performed. Then, as shown inFIGS.4AA to4AC, band-like mask material layers27a,28ain an area on a SiN layer16ainFIGS.1RA to1RCare removed in planar view by lithography and RIE etching to form band-like mask material layers28A,28B having band-like mask material layers27A,27B on their top. At the same time, band-like mask material layers27b,28bon a SiN layer16bare removed in planar view to form band-like mask material layers28C,28D (not shown) having band-like mask material layers27C,27D on their top. Next, by performing processes shown inFIGS.1SA to1TC, square-shaped mask material layers21aa,21ab,21ba,21bb,17ab,17ba,9aa,9aband square-shaped mask material layer20aa,20ab,20ba(not shown),20bb,16ab,16ba(not shown),8aa,8abare formed on a mask material layer7in planar view, as shown4B. In this case, SiN layers16aa,16bband mask material layers17aa,17bbinFIGS.1SA to1SCare absent. Then, by performing processes ofFIGS.1XAto1YYC, a SRAM cell having a structure the same as that of the first embodiment is formed on a P layer substrate1. According to the manufacturing method of this embodiment, following features are provided. In the first embodiment, Si pillars6b,6iand mask material layers7b,7iare removed after the Si pillars6b,6iand mask material layers7b,7iare formed. In such a case, the Si pillars6b,6ihaving a height in vertical direction must be removed by etching in controlled manner such that the end point of the etching comes to the same as the bottom of other Si pillars6a,6c,6d,6e,6f,6g,6h,6j. On the other hand, in this embodiment, only mask material layers27a,27b,28a,28bon the upper most surface shown inFIGS.1RA to1RCof the first embodiment may be etched. In this case, the end point of etching is a mask material layer7, which is an etching stopper, and thus there is no problem of controllability for the end point of etching, as in the first embodiment. Fifth Embodiment Hereinafter, a method for manufacturing a pillar-shaped semiconductor device having SGTs according to the fifth embodiment of the present invention is described with reference toFIGS.5AA to5FC. In the figures, figures suffixed with A are plan views, figures suffixed with B are cross-sectional structural views taken along lines X-X′ in the corresponding figures suffixed with A, and figures suffixed with C are cross-sectional structural views taken along lines Y-Y′ in the corresponding figures suffixed with A. As shown inFIGS.5AA to5AC, a band-like SiN layer101aand a band-like SiN layer101b(seventh band-like material layer, twelfth band-like material layer, sixteenth band-like material layer) respectively having a band-like mask material layer100aand a band-like mask material layer100b(sixth band-like material layer, eleventh band-like material layer, fifteenth band-like material layer) on its top are extended in Y direction to be formed on a mask material layer7. The band-like SiN layer101ais formed on an N+layer3A in planar view. Also, the band-like SiN layer101bis formed on an N+layer3B in planar view. These N+layers3A,3B are formed in band-shape at each side of a band-like P+layer4A in planar view. Then, processes ofFIGS.1DA to1ICare performed. As shown inFIGS.5BA to5BC, band-like mask material layers102aa,102ab, and band-like SiGe layers103aa,103abare thus formed at each side of the band-like mask material layer100aand the band-like SiN layer101a. Similarly, band-like mask material layers102ba,102bb(eighth band-like material layer, thirteenth band-like material layer, seventeenth band-like material layer), and band-like SiGe layers103ba,103bb(ninth band-like material layer, fourteenth band-like material layer, eighteenth band-like material layer) are formed at each side of the band-like mask material layer100band the band-like SiN layer101b. Next, entire area is covered with a SiN layer (not shown). Then, as shown inFIGS.5CA to5CC, the SiN layer is polished by CMP method such that its upper surface position comes to the same as the mask material layers100a,100bto form band-like SiN layers104a,104b,104c. Next, as shown inFIGS.5DA to5DC, a resist layer105having an opening end outside of the SiN layer104a, in planar view is formed. Then, the SiN layer104ais etched with the resist layer105, the band-like mask material layers102ab,102baas a mask, such that its upper surface position comes to a bottom position of the band-like mask material layers102ab,102ba, to form a recess106. Next, the resist layer105is removed. Then, the recess106is filled using CVD method and CMP method to form a band-like mask material layer108(twentieth band-like material layer) which upper surface position is the same as the upper surface position of the band-like mask material layers102ab,102ba. Then, as shown inFIGS.5EA to5EC, the SiN layer104is etched and removed, with the mask material layers100a,100b,102aa,102ab,102ba,102bbas a mask. Next, as shown inFIGS.5FA to5FC, the band-like mask material layers102aa,102ab,102ba,102bbare removed. Then, the SiGe layers103aa,103ab,103ba,103bbare removed. Thus, band-like SiN layers101a,101b,104ahaving the mask material layers100a,100b,108on their top are formed on the mask material layer7. Then, by performing the processes fromFIGS.2BA to2DC, a SRAM cell circuit consisting of six Si pillars61ato61fin one cell area, which is the same as the second embodiment, is formed. According to the manufacturing method of this embodiment, following features are provided. In the second embodiment, the band-like SiN layer8ais formed first, and then, two band-like SiN layers16A,16B are formed at outsides of this band-like SiN layer8a. In this case, precision of position in X direction of the band-like SiN layers16A,16B to the band-like SiN layer8ais affected by precision of two times of ALD film deposition and RIE etching for forming the band-like SiGe layers12Aa,12Ab and the band-like SiN layers16A,16B. On the other hand, in this embodiment, the band-like SiN layers101a,101bon each side are formed first, then the band-like SiGe layers103aa,103ab,103ba,103bbare formed, and after that, the central band-like SiN layer104ais formed. In this case, precision of position in X direction of the band-like SiN layers101a,101bto the band-like SiN layer104ais only affected by precision of one ALD film deposition and RIE etching for forming the band-like SiGe layers103aa,103ab,103ba,103bb. Thus, high precision of SRAM cell can be provided. In the description of the embodiment, the band-like mask material layers102aa,102ab,102ba,102bb, and the band-like SiGe layers103aa,103ab,103ba,103bbare removed, to leave the band-like mask material layers100a,100b,108, and SiN layers101a,101b,104a. On the other hand, the band-like mask material layers102aa,102ab,102ba,102bb, and the band-like SiGe layers103aa,103ab,103ba,103bbmay be left, and the band-like mask material layers100a,100b,108, and SiN layers101a,101b,104amay be removed. In this case, the band-like mask material layers102aa,102ab,102ba,102bb, and the band-like SiGe layers103aa,103ab,103ba,103bbbecome a mask material layer when forming the Si pillars. This also makes it possible to provide high precision of SRAM cell. This embodiment is described using an example of forming the band-like SiN layer104aand the band-like mask material layer108between the band-like SiGe layers103ab,103ba, as shown inFIGS.5BA to5EC. On the other hand, if a band-like mask material layer (not shown) and a band-like SiN layer (not shown) are formed by processes the same as shown inFIGS.1JA to1LCafter forming the band-like SiGe layers103aa,103ab,103ba,103bb, five band-like mask material layers (not shown) and band-like SiN layers (not shown) extended in Y direction in planar view, the same as inFIGS.1NA to1NC, can be formed. Thus, a SRAM cell consisting of eight SGTs which is the same as the first embodiment can be formed. In this method, each of forming processes of the band-like mask material layer and the band-like SiN layer can be reduced by one compared to the first embodiment. This makes it possible to simplify the processes. Sixth Embodiment Hereinafter, a method for manufacturing a pillar-shaped semiconductor device having SGTs according to the sixth embodiment of the present invention is described with reference toFIGS.6A to6C.FIG.6Ais a plan view,FIG.6Bis a cross-sectional structural view taken along line X-X′ ofFIG.6A, andFIG.6Cis a cross-sectional structural view taken along line Y-Y′ ofFIG.6A. Processes ofFIGS.1AA to1ECare performed. In the processes, Si layers110a,110bare formed instead of the SiGe layers12a,12b. Then, an amorphous SiOC layer111is formed instead of the SiO2layer13. Then, heat treatment in an atmosphere containing oxygen is performed to oxidize the top of the Si layers110a,110bto form band-like SiO2layers112a,112bwhich are mask material layers. The band-like mask material layers can be thus formed by oxidation treatment. According to the manufacturing method of this embodiment, following features are provided. In the first embodiment, after forming the recesses14a,14b, the process of polishing the entirely deposited SiN layer by CMP method is necessary. On the other hand, in this embodiment, the band-like SiO2layers112a,112bwhich are mask material layers can be formed only by the oxidation treatment. This makes it possible to simplify the processes. Seventh Embodiment Hereinafter, a method for manufacturing a pillar-shaped semiconductor device having SGTs according to the seventh embodiment of the present invention is described with reference toFIGS.7A to7C.FIG.7Ais a plan view,FIG.7Bis a cross-sectional structural view taken along line X-X′ ofFIG.7A, andFIG.7Cis a cross-sectional structural view taken along line Y-Y′ ofFIG.7A. Processes ofFIGS.1AA to1ECare performed. Then, band-like SiGe nitride layers114a,114bare formed on top of the SiGe layer12aby nitrogen ion implantation. These band-like SiGe nitride layers114a,114bare used as mask material layers. According to the manufacturing method of this embodiment, following features are provided. In the first embodiment, after forming the recesses14a,14b, the process of polishing the entirely deposited SiN layer by CMP method is necessary. On the other hand, in this embodiment, the band-like SiGe nitride layers114a,114bwhich are the mask material layers can be formed only by ion implantation of nitrogen ion. This makes it possible to simplify the processes. Eighth Embodiment Hereinafter, a method for manufacturing a three-dimensional semiconductor device according to the eighth embodiment of the present invention is described with reference toFIGS.8AA to8EC. In the figures, figures suffixed with A are plan views, figures suffixed with B are cross-sectional structural views taken along lines X-X′ in the corresponding figures suffixed with A, and figures suffixed with C are cross-sectional structural views taken along lines Y-Y′ in the corresponding figures suffixed with A. As shown inFIGS.8AA to8AC, a SiGe layer120a(fourth material layer) is formed for example on a SiO2substrate1aby ALD method. Then, a Si layer121a(first semiconductor layer), a SiGe layer120b(fourth material layer), a Si layer121b(first semiconductor layer), and a SiGe layer120care formed from below in order by epitaxial crystal growth method. Support material layers (not shown) are formed at each end in Y direction of SiGe layers120a(eighth material layer),120b(eighth material layer),120c, and Si layers121a,121b,120c. Then, a mask material layer122is formed on the SiGe layer120c. Then, processes the same asFIGS.1AA to1LCare performed to form a band-like SiN layer124having a band-like mask material layer125on its top, band-like SiGe layers126a,126brespectively having band-like mask material layers127a,127bon its top, formed at each side of the band-like mask material layer125and the band-like SiN layer124, and band-like SiN layers128a,128brespectively having mask material layers129a,129bon its top, at each side of the band-like SiGe layers126a,126band the band-like mask material layers127a,127b, on the mask material layer122. Next, as shown inFIGS.8BA to8BC, entire area is covered with a SiO2layer (not shown), and the SiO2layer is polished by CMP method such that its upper surface position comes to the upper surface position of the band-like mask material layer125to form a SiO2layer130. Then, a mask material layer131which each end in Y direction in planar view corresponds to ends of the support material layer is formed. Next, the SiO2layer130, the band-like mask material layers125,127a,127b,129a,129b, the SiN layer124,128a,128b, and the band-like SiGe layers126a,126bare etched, with the mask material layer131as a mask. Then, the mask material layer131is removed. Then, the remaining SiO2layer130, mask material layers127a,127b, SiGe layers126a,126bare removed. Then, as shown inFIGS.8CA to8CC, the mask material layer122, the SiGe layers120a,120b,120c, and Si layers121a,121bare etched with the mask material layers125,129a,129b, SiN layers124,128a,128bas a mask to form SiGe layers120aa,120ba,120ca, Si layers121aa,121ba, and a mask material layer122aunder the SiN layer128a. At the same time, SiGe layers120ab,120bb,120cb, Si layers121ab,121bb, and a mask material layer122bare formed under the SiN layer124. At the same time, SiGe layers120ac,120bc,120cc, Si layers121ac,121bc, and a mask material layer122care formed under the SiN layer128b. Next, as shown inFIGS.8DA to8DC, the mask material layers125,129a,129b, the SiN layers124,128a,128b, and the SiGe layers120aa,120ab,120ac,120ba,120bb,129bc,120ca,120cb,120ccare etched. This makes it possible to form band-like Si layers121aa,121ab,121ac,121ba,121bb,121bcsupported by the support material layer located at each end in Y direction. Next, as shown inFIGS.8EA to8EC, gate HfO2layers130aa,130ab,130ac,130ba,130bb,130bcare formed surrounding the band-like Si layers121aa,121ab,121ac,121ba,121bb,121bc. Then, a gate TiN layer132is formed surrounding the gate HfO2layers130aa,130ab,130ac,130ba,130bb,130bc. Then, the support material layer at each end of the band-like Si layers121aa,121ab,121ac,121ba,121bb,121bcis removed. Then, an N+layer (not shown) or a P+layer (not shown), which becomes source or drain, is formed at each end of the band-like Si layers121aa,121ab,121ac,121ba,121bb,121bc. Thus, a circuit using GAA (Gate All Around) transistor (refer to N. Loubt, et al.: “Stacked Nanosheet Gate-All-Around Transistor to Enable Scaling Beyond FinFET” 2017 Symposium on VLSI Technology of Technical Papers, pp. T230, 231 (2017)) in which the band-like Si layers121aa,121ab,121ac,121ba,121bb,121bcare channels is formed. According to the manufacturing method of this embodiment, following features are provided. According to this embodiment, space between the band-like Si layers121ab,121bb, and the band-like Si layers121aa,121ba, the band-like Si layers121ac,121bcin planar view can be made narrower. For example, if the band-like Si layers121aa,121baare channels of N channel GAA transistor, and the band-like Si layers121ab,121bb, the band-like Si layers121ac,121bcare channels of P channel GAA transistor, a high-density inverter circuit can be formed. Similarly, if the band-like Si layers121aa,121ab,121acin the lower stage are being channels of N channel GAA transistor, and the band-like Si layers121ba,121bb,121bcin the upper stage are being channels of the P channel GAA transistor, a high-density inverter circuit can also be formed. Also, not only the circuit where the GAA transistors are formed vertically in two stages and horizontally in three rows as in this embodiment, a circuit at high-density can also be provided in a circuit where the GAA transistors are formed vertically in one stage and three or more stages, and horizontally in two rows and four rows. Ninth Embodiment Hereinafter, a method for manufacturing a three-dimensional semiconductor device according to the ninth embodiment of the present invention is described with reference toFIGS.9AA to9CC. In the figures, figures suffixed with A are plan views, figures suffixed with B are cross-sectional structural views taken along lines X-X′ in the corresponding figures suffixed with A, and figures suffixed with C are cross-sectional structural views taken along lines Y-Y′ in the corresponding figures suffixed with A. After performing a process shown inFIGS.1AA to1AC, a SiGe layer (not shown) and a mask material layer (not shown) are entirely formed on a mask material layer7. Then, as shown inFIGS.9AA to9AC, two band-like mask material layers133a,133bextended in Y direction in planar view are formed by lithography and RIE etching methods. Then, the SiGe layer are etched by RIE etching with the band-like mask material layers133a,133bas a mask to form band-like SiGe layers134a,134bextended in Y direction. Next, a SiN layer (not shown) is entirely formed by ALD method. Then, processes shown inFIGS.1DA to1ICare performed to form band-like mask material layers135aa,135ab,135ba,135bbformed at each side of the band-like mask material layers133a,133b, and band-like SiN layers136aa,136ab,136ba,136bbunder the band-like mask material layers135aa,135ab,135ba,135bband in contact with each side surface of the band-like SiGe layers134a,134b, as shown inFIGS.9BA to9BC. The band-like mask material layers135aband the band-like mask material layer135baare formed as being separated. Similarly, the band-like SiN layer136aband the band-like SiN layer136baare formed as being separated. Next, as shown inFIGS.9CA to9CC, the band-like mask material layers133a,133b, and the band-like SiGe layers134a,134bare removed. Thus, the band-like mask material layers135aa,135ab,135ba,135bband the band-like SiN layers136aa,136ab,136ba,136bbextended in Y direction in planar view are formed on a mask material layer7. Then, by performing processes ofFIGS.3CA to3FC, a SRAM cell the same asFIGS.3FA to3FCis formed. According to the manufacturing method of this embodiment, following features are provided. In the third embodiment, a process for forming band-like material layer is repeated three times on each side of the band-like SiGe layer80to form band-like SiN layers82a,82b,86a,86band band-like SiGe layer84a,84b. On the other hand, in this embodiment, band-like SiN layers136aa,136ab,136ba,136bbare formed in a single process for forming band-like material layer, on each side of the simultaneously formed band-like SiGe layers134a,134b. This makes it possible to simplify the processes. In planar view, distance between two SiN layers136a,136bis separated more than that inFIGS.9AA and9AB, and a band-like SiGe layer and a band-like mask material layer on this band-like SiGe layer are formed (materials are different from that ofFIGS.1IA to1LC) at each side of the band-like SiN layers136aa,136ab, and the band-like SiN layers136ba,136bbby a method similar the one inFIGS.1IA to1LC. Then, a band-like SiN layer and a band-like mask material layer on this band-like SiN layer are formed between the band-like SiGe layers using a method similar to the one shown inFIGS.5BA to5EC. This makes it possible to form five band-like SiN layers extended in Y direction in planar view, and band-like mask material layers on this SiN layers similar to the first embodiment. A SRAM cell the same as the first embodiment is thus formed. In the first embodiment, a process for forming band-like materials is repeated four times on each side of a band-like SiN layer8a, on the other hand, in this method, the process is repeated for two times to form a SRAM cell. This makes it possible to simplify the processes. In addition, in the first embodiment to the seventh embodiment according to the present invention, one SGT is formed at one semiconductor pillar, but the present invention can also be applied to any circuit formation in which two or more SGTs are formed. Also, in the first embodiment, a mask material layer7is formed of a SiO2layer, an aluminum oxide (Al2O3, hereinafter referred as AlO) layer, and a SiO2layer. Then, a Silicon nitride (SiN) layer8is deposited. Then, a mask material layer9consisting of a SiO2layer is deposited. Then, a mask material layer10consisting of a SiN layer is deposited. For these mask material layers7,9,10, and SiN layer8, other material layers consisting of single or multiple layers including organic or inorganic materials may be used, as long as the materials are suitable for the purpose of the present invention. This is also applicable to other embodiments according to the present invention. Also, in the first embodiment, a SiGe layer12is formed entirely over the band-like mask material layers7,8a,9aby ALD method, as shown inFIGS.1DA to1DC. For this SiGe layer12, other material layers consisting of single or multiple layers including organic or inorganic materials may be used, as long as the materials are suitable for the purpose of the present invention. This is also applicable to band-like SiGe layers18a,18b. In addition, base materials for band-like SiGe layers12aa,12aband for band-like SiGe layers18a,18bmay not be the same. This is also applicable to other embodiments according to the present invention. Also, for band-like mask material layers15a,15b,17a,17b,19a,19b,21a,21band band-like mask material layers16a,16b,20a,20bin the first embodiment, other material layers consisting of single or multiple layers including organic or inorganic materials may be used, as long as the materials are suitable for the purpose of the present invention. This is also applicable to other embodiments according to the present invention. Also, in the first embodiment, band-like mask material layers9a,15a,15b,17a,17b,19a,19b,21a,21bare formed such that each upper surface and bottom position comes to be same, but the each upper surface and bottom position may be different in vertical direction, as long as they are suitable for the purpose of the present invention. This is also applicable to other embodiments according to the present invention. Also, in the first embodiment, a thickness and a shape of band-like mask material layers9a,15a,15b,17a,17b,19a,19b,21a,21bmay be changed by CMP polishing, RIE etching, and cleaning. This change causes no problem when the change is within a range suitable for the purpose of the present invention. This is also applicable to other embodiments according to the present invention. Also, in the first embodiment, for a SiO2layer22, a SiN layer24, band-like SiGe layer25, a band-like mask material layer26of SiN layer, and band-like mask material layers27a,27b,28a,28bshown inFIGS.1QA to1SC, other material layers consisting of single or multiple layers including organic or inorganic materials may be used, as long as the materials are suitable for the purpose of the present invention. This is also applicable to other embodiments according to the present invention. Also, in the first embodiment, Si pillars7b,6iare removed. In this manner, any of formed Si pillars6ato6jmay be removed by lithography and etching depending on a circuit design. In a circuit other than the SRAM cell circuit, once formed Si pillars may also be removed depending on a circuit design. Also, as in the fourth embodiment, any area of band-like mask material layers27a,27b,28a,28bin planar view may be etched so as to not form any of Si pillars6ato6j. A method provided by the embodiments can be applied to any circuit formation other than SRAM cells. This is also applicable to other embodiments according to the present invention. Also, in the first embodiment, TiN layers40a,40b,40c,40dare used as a gate metal layer, as shown inFIGS.1ZA to1ZC. For the TiN layers40a,40b,40c,40d, other material layers consisting of single or multiple layers may be used, as long as the materials are suitable for the purpose of the present invention. The TiN layers40a,40b,40c,40dmay be formed of a metal layer of single or multiple layers having at least desired work function. Outside of this, a W layer, for example, may be formed. In this case, the W layer serves as a metal line layer for linking gate metal layers. Any metal layers of single or multiple layers other than the W layer may be used. This is also applicable to other embodiments according to the present invention. Then, in the description of the embodiment, the example of forming the SRAM cell is used. For example, in a microprocessor circuit, a SRAM circuit and a logic circuit are formed on a same chip. In forming this logic circuit, a method of not forming unnecessary Si pillar can be used by the method described inFIGS.1WA to1WCandFIGS.4AA to4AC. Also, the SRAM circuit and the logic circuit may be formed by methods of different embodiments. This is also applicable to other circuit formation. In addition, in the sixth embodiment, the amorphous SiOC layer111is formed instead of the SiO2layer13in the first embodiment. Then, heat treatment in an atmosphere containing oxygen is performed to oxidize the top of the Si layers110a,110bto form the band-like SiO2layers112a,112bwhich are mask material layers. The amorphous SiOC layer111, Si layers110a110bmay be other material layers as long as they are suitable for the purpose of the present invention. In addition, in the seventh embodiment, the band-like SiGe nitride layers114a,114bare formed on top of the SiGe layer12aby nitrogen ion implantation. The nitrogen ion implantation and the SiGe layer12amay be other atom ion implantation, or a material layer alternative to the SiGe layer as long as a mask material layer is formed. In addition, in the first embodiment, circular mask material layers7ato7jin planar view are formed. The shape of the mask material layers7ato7jmay be elliptic. This is also applicable to other embodiments according to the present invention. In the first embodiment, although HfO2layer35is used as a gate insulating layer and TiN layers40a,40b,40c,40dare used as gate material layers, other material layers consisting of single or multiple layers may be used. This is also applicable to other embodiments according to the present invention. Also, in the first embodiment, N+layers43a,43c,43d,43e,43f,43hand P+layers43b,43gare formed by using selective epitaxial crystal growth method as shown in FIGS.1XXA to1XXC. Then, N+layers44a,44c,44d,44e,44f,44hand P+layers44b,44gare formed on top of Si pillars6ato6jby heat diffusion. Since the N+layers43a,43c,43d,43e,43f,43hand P+layers43b,43gformed by selective epitaxial crystal growth method are single crystal layer, the layers become source or drain of SGT, even when the N+layers44a,44c,44d,44e,44f,44hand P+layers44b,44gformed on top of the Si pillars6ato6jby heat diffusion do not exist. Similarly, the N+layer or the P+layer formed by epitaxial crystal growth method, surrounding periphery of the Si pillars6ato6j, may be source or drain, instead of the N+layers3a,3b,3c,3dand the P+layers4a,5apresent at the bottom of the Si pillars6ato6j, which are source or drain. This is also applicable to other embodiments according to the present invention. Also, in the first embodiment, N+layers43a,43c,43d,43e,43f,43hand P+layers43b,43gshown in FIGS.1XXA to1XXC are formed by selective epitaxial crystal growth method. These N+layers43a,43c,43d,43e,43f,43hand P+layers43b,43gmay also be formed by performing usual epitaxial crystal growth method and then lithography and etching. This is also applicable to other embodiments according to the present invention. Also, in the first embodiment, SGTs are formed on a P layer substrate1, but SOI (Silicon On Insulator) substrate may be used instead of the P layer substrate1. Alternatively, any substrate of other materials may be used as long as it can serve as a substrate. This is also applicable to other embodiments according to the present invention. Also, in the first embodiment, a SGT is described in which N+layers44a,44c,44d,44f,44hand P+layers44b,44g, and N+layers3a,3b,3c,3dand P+layers4a,5ahaving conductivities of same polarity are used above and below Si pillars6ato6jto configure source and drain, but the present invention may also be applicable to a tunnel-type SGT having source and drain of different polarities. This is also applicable to other embodiments according to the present invention. Also, in each embodiment described above, examples, in which Si (silicon) is used as a semiconductor region such as a channel, source, and drain, are described. However, the technical ideas of the present invention may not be limited to this, and may also be applicable to any three-dimensional semiconductor devices using semiconductor materials containing Si, such as SiGe, or semiconductor materials other than Si. Also, in the first embodiment, Si pillars6ato6jare formed of a single Si layer, but channels of SGTs may be formed by laminating semiconductor layers consisting of different semiconductor base materials in vertical direction. This is also applicable to other embodiments according to the present invention. Also, in a vertical-type NAND type flash memory circuit, a semiconductor pillar is made to be a channel, and multiple stage of memory cells configured by a tunnel oxide layer, a charge accumulation layer, an interlayer insulating layer, and a control conductor layer surrounding the semiconductor pillar are formed in a vertical direction. At the semiconductor pillars on each end of these memory cells, a source line impurity layer which corresponds to a source and a bit line impurity layer which corresponds to a drain exist. In addition, for one memory cell, when there are other memory cells on each side of the one memory cell, if one of the other memory cells is a source, then the other one serves as a drain. Thus, the vertical-type NAND type flash memory circuit is a type of SGT circuits. Therefore, the present invention may be applicable to the NAND type flash memory circuit. In the present invention, various embodiments and modification will be possible without departing from the broader sprit and scope of the present invention. Also, the foregoing embodiments are intended to illustrate one example of the present invention and not intended to limit the scope of the present invention. The foregoing examples and variations may be arbitrarily combined. Furthermore, if necessary, even if a part of constituent features of the foregoing embodiments is removed, it will be within the technical idea of the present invention. | 71,237 |
11862465 | DETAILED DESCRIPTION It is to be understood that the following disclosure provides many different embodiments, or examples, for implementing different features of the invention. Specific embodiments or examples of components and arrangements are described below to simplify the present disclosure. These are, of course, merely examples and are not intended to be limiting. For example, dimensions of elements are not limited to the disclosed range or values, but may depend upon process conditions and/or desired properties of the device. Moreover, the formation of a first feature over or on a second feature in the description that follows may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features may be formed interposing the first and second features, such that the first and second features may not be in direct contact. Various features may be arbitrarily drawn in different scales for simplicity and clarity. Further, spatially relative terms, such as “beneath,” “below,” “lower,” “above,” “upper” and the like, may be used herein for ease of description to describe one element or feature's relationship to another element(s) or feature(s) as illustrated in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The apparatus may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein may likewise be interpreted accordingly. In addition, the term “being made of” may mean either “comprising” or “consisting of.” In the present disclosure, a phrase “one of A, B and C” means “A, B and/or C” (A, B, C, A and B, A and C, B and C, or A, B and C), and does not mean one element from A, one element from B and one element from C, unless otherwise described. FIGS.1(a),1(b),2(a),2(b),3(a),3(b),4(a),4(b),5(a),5(b),6(a),6(b),7(a),7(b),8(a), and8(b) show various views illustrating various stages of a sequential manufacturing operation of a semiconductor device according to an embodiment of the present disclosure. It is understood that additional operations may be provided before, during, and after the operations shown byFIGS.1(a)-8(b), and some of the operations described below can be replaced or eliminated for additional embodiments of the method. The order of the operations/processes may be interchangeable. FIGS.1(a) and1(b)show a fragmentary diagrammatic top view and a cross-sectional view of a semiconductor device, in portion or entirety, at a fabrication operation, according to an embodiment of the present disclosure.FIGS.1(a) and1(b)show an operation of a photolithographic and etching method using a mask M over a substrate100. Depending on the device or integrated circuit (IC) being fabricated on the substrate100, the substrate100can be made of various materials for proper functioning of the device or IC. In some embodiments, the substrate100includes a single crystalline semiconductor layer on at least its surface portion. The substrate100may include a single crystalline semiconductor material such as, but not limited to Si, Ge, SiGe, SiC, InSb, InP, InAs, InAlAs, InGaAs, GaAs, GaP, GaSb, GaSbP, and GaAsSb. In some embodiments, the substrate100is made of crystalline silicon. In some embodiments, the substrate100is a semiconductor-on-insulator substrate fabricated using separation by implantation of oxygen (SIMOX), wafer bonding, and/or other suitable methods, such as a silicon-on-insulator (SOI) substrate, a silicon germanium-on-insulator (SGOI) substrate, or a germanium-on-insulator (GOI) substrate. InFIGS.1(a) and1(b), an underlying layer110is formed over the substrate100. Depending on the type and structure, the underlying layer can be made of the materials for proper functioning of a device made by patterning the underlying layer110. In some embodiments, the underlying layer110is formed of a semiconductor material such as, but not limited to Si, SiGe and Ge. Bandgap adjustment in the semiconductor material of the underlying layer110is optionally performed to tune the carrier concentration in the underlying layer110, and this is achieved using an ion implantation method, in some embodiments. Alternately, the underlying layer110is made of a conducting material including one or more of Co, Ni, W, Ti, Ta, Cu, Al, TiN and TaN for forming wiring lines of a circuitry or a device. The structure of the material in the underlying layer110is crystalline, polycrystalline, nanostructured, or two-dimensional sheet, in some embodiments. Also, in some embodiments, the underlying layer110is a portion of an integrated circuit (IC) chip, a system on chip (SoC), or portion thereof, that includes various passive and active microelectronic devices, such as resistors, multilayered capacitors, coil inductors, fuses, diodes, metal-oxide-semiconductor FETs (MOSFETs), complementary MOS (CMOS) transistors, FinFET, gate-all-around (GAA) FET and other suitable components, or combinations thereof. In other embodiments, the underlying layer110is one or more layers of a dielectric material, such as SiO2, Si3N4, SiON, SiCN, or SiOCN. InFIGS.1(a) and1(b), a hard mask layer120is formed over the substrate100and on the underlying layer110. In some embodiments, the hard mask layer120is formed of a material such as, but not limited to, silicon oxide, silicon nitride, silicon carbide, or other suitable hard mask material, or combinations thereof. The hard mask layer120is formed by a deposition process, such as chemical vapor deposition (CVD), including low pressure CVD (LPCVD) and plasma enhanced CVD (PECVD), physical vapor deposition (PVD), atomic layer deposition (ALD), or other suitable process. On the hard mask layer120, a photoresist layer130is formed by spin coating or self-assembly, in some embodiments. The photoresist layer130is a positive resist (a type of photoresist in which the portion of the photoresist that is exposed to light becomes soluble in the photoresist developer and the unexposed portion of the photoresist remains insoluble in the photoresist developer) or a negative photoresist (a type of photoresist in which the portion of the photoresist that is exposed to light becomes insoluble in the photoresist developer and the unexposed portion of the photoresist is dissolved by the photoresist developer). In some embodiments, operations of pre-exposure baking, exposure, post-exposure baking, and development are carried on at the photoresist layer130. The operation of exposure uses an electromagnetic wave or energetic particles having a wavelength of any value that can change the chemical structure of the photoresist layer130. The exposure source includes high-pressure mercury lamp with a wavelength of about 436 nm (g-line) and a wavelength of about 365 nm (i-line), deep UV (DUV) with wavelengths of about 248 nm (KrF laser) and about 193 nm (ArF laser), and extreme UV (EUV) with a wavelength in a range from about 10 nm to about 15 nm, e-beam, and X-ray. The electromagnetic wave or energetic particle passes through transparent portions or openings of the mask M and reaches the photoresist layer130in some embodiments. In some embodiments, EUV is not included. In some embodiments, maskless photolithography is used and the electromagnetic wave or energetic particles form a pattern by controlled optical or electromagnetic system (in case of e-beam) on the photoresist layer130without using a mask, and in this method, the precision of patterning relies solely on the electro-magnetic optics instead of the mask. In some embodiments, other techniques are used to form a pattern on the photoresist layer130, and the techniques include cyclotron photolithography, atomic force microscopic (AFM) cantilever writing or positron beam photolithography. FIGS.2(a) and2(b)show the structure after the operation of development of the photoresist layer130is performed. Depending on the material of the photoresist layer, the exposed and developed region of the photoresist layer can either be removed by dissolution to show the desired pattern, or remain as the desired patterns. The patterned photoresist layers130′ are formed on the hard mask layer120, duplicating the pattern provided by the shape of the mask M inFIGS.1(a) and1(b). FIGS.3(a) and3(b)show that an etching operation is performed on the hard mask layer120using the developed photoresist layer130′ as an etching mask, to form patterned hard mask layer120′.FIGS.4(a) and4(b)show the structure after the patterned photoresist layer130′ is removed. In some embodiments, the patterned photoresist layer130′ is removed by a plasma ashing operation or a wet removal process. FIGS.5(a) and5(b)show an operation of directional etching of the patterned hard mask layer120′ from a right to left direction (i.e. in x-direction). The directional etching or surface directional etching process (also referred to as a horizontal directional etching process) is performed to modify a horizontal profile of the patterned hard mask layer120′ so as to reduce an edge-to-edge or end-to-end (EE) distance within a feature in the patterned hard mask layer120′. The directional etching method increases the gap between the left and right vertical patterns inFIG.5(a)by an extended gap region having a width of d (FIG.6(a)). Also, the directional etching method narrows the left pattern of the patterned hard mask layer120′ by reducing a portion having a width of d (FIG.6(a)). For a narrow feature, such as the right pattern inFIG.5(a), it can be selectively and completely removed without and with minimal effect to the other portions of the patterned hard mask layer120′ adjacent to this removed narrow feature. The surface directional etching process is a selective dry etching process that selectively etches the patterned hard mask layer120′ relative to substrate100. The selective dry etching process directs an etching species or energetic species in a substantially horizontal direction relative to a horizontal surface of substrate100, thereby achieving horizontal etching of patterned hard mask layer120′. In this disclosure, the substantially horizontal direction generally refers to a situation where the etching species or energetic species are directed towards a horizontal surface of substrate100at an angle of about 0° to about 20° relative to the horizontal surface in the x-y plane substantially parallel to the horizontal surface of the substrate. In some embodiments, the angle is less than or equal to about 10°. Depending on the desired horizontal etching, the angle can be tuned to different values. In some embodiments, the angle can be adjusted so that the etching species or energetic species are along the x axis, y axis, or z axis. In some embodiments, the surface directional etching process is a plasma etching process tuned to cause plasma to flow in an in-plane direction, such as along they axis, over substrate100, such that horizontal profile of gap between the left and right patterns inFIG.5(a)are modified in they axis direction. Various etching parameters can be tuned to generate etching species (radicals) that travel in a horizontal direction, such as etchant composition, etching temperature, etching time, etching pressure, radio frequency (RF) bias voltage, RF bias power, etchant flow rate, wafer tilting, other suitable etching parameters, or combinations thereof. In some embodiments, RF bias voltage is tuned to achieve an electric field that causes etching species to flow substantially horizontally along an in-plane direction (for example, in they axis direction) relative to a surface over substrate100. In some embodiments, the etching species are tuned to have a profile of momenta of the energetic species such as the momenta of the etching species or energetic species along a frontline are not the same, i.e. the momentum of an etching or energetic species on the top path is different from the momentum of an etching or energetic species on the bottom path. In some embodiments, the momentum of an etching or energetic species on the top path is different from the momentum of an etching or energetic species in the middle path above the bottom path, and the momentum of the etching or energetic species on the top path is the same as or different from the momentum of an etching or energetic species on the bottom path. Any combinations can be achieved by adjustment of the electromagnetic control to tune the energies of the etching or energetic species along the etching front. FIGS.6(a) and6(b)show the outcome of the patterned hard mask layer120′ after the directional etching operation performed inFIGS.5(a) and5(b).FIGS.9(a) and9(b)show the expected and desired final pattern of the underlying layer110′, when the directional etching on the hard mask layer120″ is well-controlled. In contrast,FIGS.6(a) and6(b)show the case where the directional etching is not appropriately controlled. The width of the left pattern of the patterned hard mask layer120′ is reduced by a distance d while the right thinner hard mask pattern of the patterned hard mask layer120′ inFIGS.5(a) and5(b), which is expected to be smaller and non-zero after the directional etching operation performed inFIGS.5(a) and5(b), is undesirably and completely removed after the directional etching operation. Therefore, a new strategy or method may apply directional etching to make a narrow hard mask pattern narrower to achieve a fine dimension by etching through the narrowed and patterned hard mask layer120′ smaller than the smallest value achieved by photolithography. FIGS.7(a) and7(b)show the operation using the directionally etched hard mask layer120″ for etching the underlying layer110′. In some embodiments, the underlying layer110′ is etched to form a pattern based on the directionally etched hard mask layer120″. FIGS.8(a) and8(b)show an operation of removing the directionally etched hard mask layer120″. InFIGS.8(a) and8(b), the patterned underlying layer110′ remains. FIGS.9(a) and9(b)show the expected and desired final pattern of the underlying layer110′ which is not equal to the final outcome of the patterned underlying layer110′ shown inFIGS.8(a) and8(b). In particular, the desired right narrower pattern inFIGS.9(a) and9(b)is undesirably and completely removed inFIGS.8(a) and8(b). A new strategy or method may achieve a fine line pattern that has a pattern width or EE distance smaller than the smallest dimension achieved by a photolithographic and etching method. FIGS.10(a)-21(b)show various views illustrating various stages of a sequential manufacturing operation of a semiconductor device according to an embodiment of the present disclosure. It is understood that additional operations may be provided before, during, and after the operations shown byFIGS.10(a)-21(b), and some of the operations described below can be replaced or eliminated for additional embodiments of the method. The order of the operations/processes may be interchangeable. Materials, configurations, layouts, dimensions, processes and/or operations same as or similar to those described with respect toFIGS.1(a)-9(b)may be employed in the following embodiments and the detailed explanation may be omitted. FIGS.10(a)-20(b)show operations of forming a fine line pattern that has a dimension smaller than the smallest dimension achieved by a photolithographic and etching method. FIGS.10(a) and10(b)show a fragmentary diagrammatic top view and a cross-sectional view of a semiconductor device, in portion or entirety, at various fabrication operations, according to an embodiment of the present disclosure.FIGS.10(a) and10(b)show an operation of a photolithographic and etching method using a mask M over a substrate100. Depending on the device or integrated circuit (IC) being fabricated on the substrate100, the substrate100can be made of various materials for proper functioning of the device or IC. In some embodiments, the substrate100includes a single crystalline semiconductor layer on at least its surface portion. The substrate100may include a single crystalline semiconductor material such as, but not limited to Si, Ge, SiGe, SiC, InSb, InP, InAs, InAlAs, InGaAs, GaAs, GaP, GaSb, GaSbP, and GaAsSb. In some embodiments, the substrate100is made of crystalline silicon. In some embodiments, the substrate100is a semiconductor-on-insulator substrate fabricated using separation by implantation of oxygen (SIMOX), wafer bonding, and/or other suitable methods, such as a silicon-on-insulator (SOI) substrate, a silicon germanium-on-insulator (SGOI) substrate, or a germanium-on-insulator (GOI) substrate. InFIGS.10(a) and10(b), an underlying layer110is formed over the substrate100. Depending on the type and structure, the underlying layer can be made of materials for proper functioning of a device made by patterning the underlying layer110. In some embodiments, the underlying layer110is formed of a semiconductor material such as, but not limited to Si, SiGe and Ge. Bandgap adjustment in the semiconductor material of the underlying layer110is optionally performed to tune the carrier concentration in the underlying layer110, and this is achieved using an ion implantation method, in some embodiments. Alternately, the underlying layer110is made of a conducting material including one or more of Co, Ni, W, Ti, Ta, Cu, Al, TiN and TaN for forming wiring lines of a circuitry or a device. The structure of the material in the underlying layer110is crystalline, polycrystalline, nanostructured, and two-dimensional sheet, in some embodiments. Also, in some embodiments, the underlying layer110is a portion of an integrated circuit (IC) chip, a system on chip (SoC), or portion thereof, that includes various passive and active microelectronic devices, such as resistors, multilayered capacitors, coil inductors, fuses, diodes, metal-oxide-semiconductor FETs (MOSFETs), complementary MOS (CMOS) transistors, FinFET, gate-all-around (GAA) FET and other suitable components, or combinations thereof. In other embodiments, the underlying layer110is one or more layers of dielectric material, such as SiO2, Si3N4, SiON, SiCN, or SiOCN. InFIGS.10(a) and10(b), a hard mask layer120is formed over the substrate100and on the underlying layer110. In some embodiments, the hard mask layer120is formed of a material such as, but not limited to, silicon oxide, silicon nitride, silicon carbide, or other suitable hard mask material, or combinations thereof. The hard mask layer120is formed by a deposition process such as chemical vapor deposition (CVD), including low pressure CVD (LPCVD) and plasma enhanced CVD (PECVD), physical vapor deposition (PVD), atomic layer deposition (ALD), or other suitable process. On the hard mask layer120, a photoresist layer130is formed by spin coating or self-assembly, in some embodiments. The photoresist layer130is a positive resist (a type of photoresist in which the portion of the photoresist that is exposed to light becomes soluble in the photoresist developer and the unexposed portion of the photoresist remains insoluble in the photoresist developer) or a negative photoresist (a type of photoresist in which the portion of the photoresist that is exposed to light becomes insoluble in the photoresist developer and the unexposed portion of the photoresist is dissolved by the photoresist developer). In some embodiments, operations of pre-exposure baking, exposure, post-exposure baking, and development are carried out on the photoresist layer130. The operation of exposure uses an electromagnetic wave having a wavelength of any value that can change the chemical structure of the photoresist layer130or energetic particles. The exposure source includes high-pressure mercury lamp with a wavelength of about 436 nm g-line and a wavelength of about 365 nm i-line), UV, deep UV (DUV) with wavelengths of about 248 nm (KrF laser) and about 193 nm (ArF laser), and extreme UV (EUV) with a wavelength in a range from about 10 nm to about 15 nm, e-beam, and X-ray. The electromagnetic wave or energetic particle passes through transparent portions or openings of the mask M and reaches the photoresist layer130in some embodiments. In some embodiments, maskless photolithography is used and electromagnetic wave of energetic particles form a pattern by controlled optical or electromagnetic system (in case of e-beam) on the photoresist layer130without using a mask, and in this method, the precision of patterning relies solely on the electro-magnetic optics instead of a mask. In some embodiments, other techniques are used to form a pattern on the photoresist layer130, and the techniques include cyclotron photolithography, atomic force microscopic (AFM) cantilever writing or positron beam photolithography. FIGS.11(a) and11(b)show the structure after the operation of development of the photoresist layer130is performed. Depending on the material of the photoresist layer130, the exposed and developed region of the photoresist layer can either be removed by dissolution to show the desired pattern or remain as desired patterns. The patterned photoresist layers130′ are formed on the hard mask layer120, duplicating the pattern provided by the shape of the mask M inFIGS.10(a) and10(b). FIGS.12(a) and12(b)show an etching operation performed on the hard mask layer120using the developed photoresist layer130′ as an etching mask, to form patterned hard mask layer120′.FIGS.13(a) and13(b)show the structure of the patterned photoresist layer130′ on the patterned hard mask layer120′ is removed. In some embodiments, the patterned photoresist layer130′ is removed by a plasma ashing operation or a wet removal process. The remaining patterned hard mask layer120′ has a width or edge-to-edge or end-to-end length (in short “EE”) of wM. This value of EE, wM, is further reduced in the following operations. FIGS.14(a) and14(b)show an operation of forming a blanket layer of a spacer material140over the substrate100, covering the patterned hard mask layer120′. In some embodiments, the spacer material layer140is formed of one or more of insulating materials, such as SiO2, Al2O3, HfO2or silicon oxynitride and the spacer material layer140is selectively etchable relative to the hard mask layer120. FIGS.15(a) and15(b)show an operation of anisotropic etching300to remove the spacer material layer140on the substrate100. In some embodiments, the spacer material layer140is etched to remove the spacer material from horizontal surfaces while the vertical sections of the spacer material140remain. In some embodiments, such an etching process is performed using a reactive ion etch (RIE) employing CF4, CHF3, and/or CH2F2-containing plasma in the case of SiO2spacer material. The etching chemistry may be selective to the material comprising the spacer material layer140. In some embodiments, single anisotropic etching is performed. In other embodiments, multiple anisotropic etching is performed. FIGS.16(a) and16(b)show the outcome of the anisotropic etching inFIGS.15(a) and15(b). The patterned spacer material layer140′ contact sidewalls of the patterned hard mask layer120′ while the horizontal sections of the spacer material layer140are substantially removed. FIGS.17(a) and17(b)show an operation of a directional etching200from the right-to-left direction to remove the right vertical section of the spacer material layer140′ contacting the right sidewalls of the patterned hard mask layer120′. The purpose of the directional etching is to expose the surface of the right sidewalls of the patterned hard mask layer120′. In some embodiments, such an etching process is performed using a reactive ion etch (RIE) employing CF4, CHF3, and/or CH2F2-containing plasma in the case of SiO2spacer material. The etching chemistry may be selective to the material comprising the spacer material layer140. In some embodiments, single anisotropic etching is performed. In other embodiments, multiple anisotropic etching is performed. The etching operation ofFIGS.17(a) and17(b)is directional etching or surface directional etching process (also referred to as a horizontal directional etching process) performed to eventually modify a horizontal profile of the hard mask features of patterned hard mask layer120′ so as to reduce an edge-to-edge or end-to-end (EE) distance within a feature in the patterned hard mask layer120′ when combined with the etching operation ofFIGS.18(a) and18(b). The directional etching method inFIGS.17(a) and17(b)increases the gap between the left and right vertical patterns inFIG.17(a)by removing the right spacer material layer140′ (the outcome of the etching operation ofFIGS.17(a) and17(b)is shown inFIGS.18(a) and18(b)). The surface directional etching process is a selective dry etching process that selectively etches the spacer material layer140′. The selective dry etching process directs an etching species or energetic species in a substantially horizontal direction relative to a horizontal surface of substrate100, thereby achieving horizontal etching of the spacer material layer140′. In this disclosure, the substantially horizontal direction generally refers to the etching species or energetic species being directed towards a horizontal surface of substrate100at an angle of about 0° to about 20° relative to the horizontal surface in the x-y plane (substantially parallel to the horizontal surface of the substrate). In some embodiments, the angle is less than or equal to about 10°. Depending on desired horizontal etching, the angle can be tuned to different values. In some embodiments, the angle can be adjusted so that the etching species or energetic species are along the x axis, y axis, or z axis. In some embodiments, the surface directional etching process is a plasma etching process tuned to cause plasma to flow in an in-plane direction, such as along they axis, over substrate100, such that horizontal profile of gap between the left and right patterns inFIG.17(a)are modified in they axis direction. Various etching parameters can be tuned to generate etching species (radicals) that travel in a horizontal direction, such as etchant composition, etching temperature, etching time, etching pressure, radio frequency (RF) bias voltage, RF bias power, etchant flow rate, wafer tilting, other suitable etching parameters, or combinations thereof. In some embodiments, RF bias voltage is tuned to achieve an electric field that causes etching species to flow substantially horizontally along an in-plane direction (for example, in they axis direction) relative to a surface over substrate100. In some embodiments, the etching species are tuned to have a profile of momenta of the energetic species such as the momenta of the etching species or energetic species along a frontline are not the same, i.e. the momentum of an etching or energetic species on the top path is different from the momentum of an etching or energetic species on the bottom path. In some embodiments, the momentum of an etching or energetic species on the top path is different from the momentum of an etching or energetic species in the middle path above the bottom path, and the momentum of the etching or energetic species on the top path is the same as or different from the momentum of an etching or energetic species on the bottom path. Any combinations can be achieved by adjustment of the electromagnetic control to tune the energies of the etching or energetic species along the etching front. After the directional etching of the spacer material layer140′, another directional etching operation210targeting the exposed sidewall surface of the patterned hard mask layer120′ is shown inFIGS.18(a) and18(b).FIGS.18(a) and18(b)show that the energetic species of the directional etching method are aimed at the right sidewall surface of the hard mask layer120′. The etchant targets the hard mask layer120′ instead of the spacer material layer140′. The etchant source gas includes a fluorine containing gas without oxygen, in some embodiments. In another embodiment, the etchant source gas also includes argon. The etching operation ofFIGS.18(a) and18(b)is directional etching or surface directional etching process (also referred to as a horizontal directional etching process) performed to directly modify a horizontal profile of the hard mask features of patterned hard mask layer120′ so as to reduce an edge-to-edge or end-to-end (EE) distance within a feature in the patterned hard mask layer120′. The directional etching method inFIGS.18(a) and18(b)removes the right vertical portion of the120′ while the spacer material layer140″ remains (the outcome of the etching operation ofFIGS.18(a) and18(b)is shown inFIGS.19(a) and19(b)). The surface directional etching process is a selective dry etching process that selectively etches the hard mask layer120′. The selective dry etching process directs an etching species or energetic species in a substantially horizontal direction relative to a horizontal surface of substrate100, thereby achieving horizontal etching of the hard mask layer120′. In this disclosure, the substantially horizontal direction generally refers to the etching species or energetic species being directed towards a horizontal surface of substrate100at an angle of about 0° to about 20° relative to the horizontal surface in the x-y plane (substantially parallel to the horizontal surface of the substrate). In some embodiments, the angle is less than or equal to about 10°. Depending on desired horizontal etching, the angle can be tuned to different values. In some embodiments, the angle can be adjusted so that the etching species or energetic species are along the x axis, y axis, or z axis. In some embodiments, the surface directional etching process is a plasma etching process tuned to cause plasma to flow in an in-plane direction, such as along they axis, over substrate100. Various etching parameters can be tuned to generate etching species (radicals) that travel in a horizontal direction, such as etchant composition, etching temperature, etching time, etching pressure, radio frequency (RF) bias voltage, RF bias power, etchant flow rate, wafer tilting, other suitable etching parameters, or combinations thereof. In some embodiments, RF bias voltage is tuned to achieve an electric field that causes etching species to flow substantially horizontally along an in-plane direction (for example, in they axis direction) relative to a surface over substrate100. In some embodiments, the etching species are tuned to have a profile of momenta of the energetic species such as the momenta of the etching species or energetic species along a frontline are not the same, i.e. the momentum of an etching or energetic species on the top path is different from the momentum of an etching or energetic species on the bottom path. In some embodiments, the momentum of an etching or energetic species on the top path is different from the momentum of an etching or energetic species in the middle path above the bottom path, and the momentum of the etching or energetic species on the top path is the same as or different from the momentum of an etching or energetic species on the bottom path. Any combinations can be achieved by adjustment of the electromagnetic control to tune the energies of the etching or energetic species along the etching front. The etching parameter such as degree of etching direction is controlled to the same for both operations inFIGS.17(a) and17(b)andFIGS.18(a) and18(b), in some embodiments. In other embodiments, the etching parameter such as degree of etching direction is controlled to be different for both operations inFIGS.17(a) and17(b)andFIGS.18(a) and18(b). FIGS.19(a) and19(b)show the outcome of the directional etching performed inFIGS.18(a) and18(b).FIGS.19(a) and19(b)show that the left pattern of the patterned hard mask layer120′ is narrowed while the right pattern of the patterned hard mask layer120′ is completely removed, while the spacer material layer140′ after this directional etching operation of the exposed hard mask layer120′ remains, forming patterned spacer material layer140″ with opposite sidewalls exposed. FIGS.20(a) and20(b)show an operation of etching using the patterned spacer material layer140″. In some embodiments, the etching is performed by anisotropic etching methods. After the underlying layer110is patterned, the patterned spacer material layers140″ are removed by dry and/or wet etching (FIGS.21(a) and21(b)). The right pattern of the patterned underlying layer110′ has a dimension of the patterned spacer material layer140″, and has an EE length smaller than the smallest value achieved by other photolithographic and etching methods. The width of the patterned spacer material layer140″ can be adjusted by adjusting a thickness of the blanket layer140of the spacer material. In some embodiments, the thickness of the blanket layer140of the spacer material is in a range from about 5 nm to about 20 nm and the width wMof the patterned spacer material layer140″ (labelled inFIG.19(b)) is in a range from about 3 nm to about 18 nm, in some embodiments. In some embodiments, the width wMis in a range of 0.5 nm to 5 nm. Additional steps can be provided before, during, and after the operations ofFIGS.10(a),10(b),11(a),11(b),12(a),12(b),13(a),13(b),14(a),14(b),15(a),15(b),16(a),16(b),17(a),17(b),18(a),18(b),19(a),19(b),20(a),20(b),21(a), and21(b), and some of the operations described can be removed, replaced, or eliminated for additional embodiments. Combinations of any of the operations in this disclosure can be performed for other possible embodiments in this disclosure. FIGS.22(a),22(b),23(a),23(b),24(a),24(b),25(a),25(b),26(a),26(b),27(a),27(b),28(a),28(b),29(a),29(b),30(a), and30(b) show various views illustrating various stages of a sequential manufacturing operation of a semiconductor device according to an embodiment of the present disclosure. It is understood that additional operations may be provided before, during, and after the operations shown byFIGS.22(a)-30(b), and some of the operations described below can be replaced or eliminated for additional embodiments of the method. The order of the operations/processes may be interchangeable. FIGS.22(a),22(b),23(a),23(b),24(a),24(b),25(a),25(b),26(a),26(b),27(a),27(b),28(a),28(b),29(a),29(b),30(a), and30(b) show operations of forming a patterned underlying layer having a dimension or EE length smaller than the smallest dimension achieved by photolithographic and etching methods, without using the spacer material layer140and the operations applied to the spacer material layer140inFIGS.14(a),14(b),15(a),15(b),16(a),16(b),17(a),17(b),18(a),18(b),19(a),19(b),20(a), and20(b). FIGS.22(a) and22(b)show a fragmentary diagrammatic top view and a cross-sectional view of a semiconductor device, in portion or entirety, at a fabrication operation, according to an embodiment of the present disclosure.FIGS.22(a) and22(b)show an operation of a photolithographic and etching method using a mask M over a substrate100. Depending on the device or integrated circuit (IC) being fabricated on the substrate100, the substrate100can be made of various materials for proper functioning of the device or IC. In some embodiments, the substrate100includes a single crystalline semiconductor layer on at least its surface portion. The substrate100may include a single crystalline semiconductor material such as, but not limited to Si, Ge, SiGe, SiC, InSb, InP, InAs, InAlAs, InGaAs, GaAs, GaP, GaSb, GaSbP, and GaAsSb. In some embodiments, the substrate100is made of crystalline silicon. In some embodiments, the substrate100is a semiconductor-on-insulator substrate fabricated using separation by implantation of oxygen (SIMOX), wafer bonding, and/or other suitable methods, such as a silicon-on-insulator (SOI) substrate, a silicon germanium-on-insulator (SGOI) substrate, or a germanium-on-insulator (GOI) substrate. InFIGS.22(a) and22(b), an underlying layer110is formed over the substrate100. Depending on the type and structure, the underlying layer can be made of materials for proper functioning of a device made by patterning the underlying layer110. In some embodiments, the underlying layer110is formed of a semiconductor material such as, but not limited to Si, SiGe and Ge. Bandgap adjustment in the semiconductor material of the underlying layer110is optionally performed to tune the carrier concentration in the underlying layer110, and this is achieved using an ion implantation method, in some embodiments. Alternately, the underlying layer110is made of a conducting material including one or more of Co, Ni, W, Ti, Ta, Cu, Al, TiN and TaN for forming wiring lines of a circuitry or a device. The structure of the material in the underlying layer is crystalline, polycrystalline, nanostructured, and two-dimensional sheet, in some embodiments. Also, in some embodiments, the underlying layer110is a portion of an integrated circuit (IC) chip, a system on chip (SoC), or portion thereof, that includes various passive and active microelectronic devices, such as resistors, multilayered capacitors, coil inductors, fuses, diodes, metal-oxide-semiconductor FETs (MOSFETs), complementary MOS (CMOS) transistors, FinFET, gate-all-around (GAA) FET and other suitable components, or combinations thereof. In other embodiments, the underlying layer110is one or more layers of dielectric material, such as SiO2, Si3N4, SiON, SiCN, or SiOCN. InFIGS.22(a) and22(b), a hard mask layer120is formed over the substrate100and on the underlying layer110. In some embodiments, the hard mask layer120is formed of a material such as, but not limited to, silicon oxide, silicon nitride, silicon carbide, or other suitable hard mask material, or combinations thereof. The hard mask layer120is formed by a deposition process such as chemical vapor deposition (CVD), including low pressure CVD (LPCVD) and plasma enhanced CVD (PECVD), physical vapor deposition (PVD), atomic layer deposition (ALD), or other suitable process. On the hard mask layer120, a photoresist layer130is formed by spin coating or self-assembly, in some embodiments. The photoresist layer130is a positive resist (a type of photoresist in which the portion of the photoresist that is exposed to light becomes soluble in the photoresist developer and the unexposed portion of the photoresist remains insoluble in the photoresist developer) or a negative photoresist (a type of photoresist in which the portion of the photoresist that is exposed to light becomes insoluble in the photoresist developer and the unexposed portion of the photoresist is dissolved by the photoresist developer). In some embodiments, operations of pre-exposure baking, exposure, post-exposure baking, and development are carried out at the photoresist layer130. The operation of exposure uses an electromagnetic wave having a wavelength of any value that can change the chemical structure of the photoresist layer130or energetic particles. The exposure source includes high-pressure mercury lamp with a wavelength of about 436 nm g-line and a wavelength of about 365 nm i-line), deep UV (DUV) with wavelengths of about 248 nm (KrF laser) and about 193 nm (ArF laser), and extreme UV (EUV) with a wavelength in a range from about 10 nm to about 15 nm, e-beam, and X-ray. The electromagnetic wave or energetic particle passes through transparent portions or openings of the mask M and reaches the photoresist layer130in some embodiments. In some embodiments, maskless photolithography is used and electromagnetic wave of energetic particles form a pattern by controlling an optical or electromagnetic system (in case of e-beam) on the photoresist layer130without using a mask, and in this method, the precision of the patterning relies solely on the electromagnetic optics instead of the mask. In some embodiments, other techniques are used to form a pattern on the photoresist layer130, and the techniques include cyclotron photolithography, atomic force microscopic (AFM) cantilever writing or positron beam photolithography. FIGS.23(a) and23(b)show the structure, after the operation of development of the photoresist layer130is performed. Depending on the material of the photoresist layer, the exposed and developed region of the photoresist layer can be either removed by dissolution to show the desired pattern or remain as desired patterns. The patterned photoresist layers130′ are formed on the hard mask layer120, duplicating the pattern provided by the shape of the mask M inFIGS.22(a) and22(b). FIGS.24(a) and24(b)show an etching operation performed on the hard mask layer120using the developed photoresist layer130′ as an etching mask, to form patterned hard mask layer120′.FIGS.25(a) and25(b)show the patterned photoresist layer130′ is removed. In some embodiments, the patterned photoresist layer130′ is removed by a plasma ashing operation or a wet removal process. FIGS.26(a) and26(b)show an operation of directional ion implantation applied to an exposed sidewall surface of the patterned hard mask layer120′. The energetic species400includes arsenic (As75), phosphorus (P31) or boron (B11) ions and are aimed at the sidewall surface of the patterned hard mask layer120′, and the species400undergo diffusion and interaction with the atoms for a diffusion length from the sidewall surface of the patterned hard mask layer120′. The ion implantation dose is in a range of 1015to 5×1016cm−2with an implantation energy of 30 to 100 keV. The energetic species400would eventually stabilize in the patterned hard mask layer120′ within a region defined by this diffusion length, which is a very thin layer under the sidewall surface of the patterned hard mask layer120′.FIGS.27(a)and27(b) show the outcome of the directional ion implantation. The thick black lines inFIGS.27(a) and27(b)indicate the regions that undergo substantial ion implantation, forming a hardened hard mask layer150. FIGS.28(a) and28(b)show an operation of directional etching200targeting the patterned hard mask layer120′ that has not undergone the directional ion implantation.FIGS.28(a) and28(b)show that the energetic species of the directional etching method are aimed at the left sidewall surfaces of the hard mask layer120′. The etchant targets the hard mask layer120′ instead of the ion-implanted hardened hard mask layer150. The etchant source gas includes a fluorine containing gas without oxygen, in some embodiments. In another embodiment, the etchant source gas also includes argon. The etching operation ofFIGS.28(a) and28(b)is directional etching or surface directional etching process (also referred to as a horizontal directional etching process) performed to directly modify a horizontal profile of the hard mask features of patterned hard mask layer120′ so as to reduce an edge-to-edge or end-to-end (EE) distance within a feature in the patterned hard mask layer120′. The directional etching method inFIGS.28(a) and28(b)removes the right vertical portion of the patterned hard mask layer120′ (FIGS.28(a) and29(a)) while the hardened hard mask layer150remains (the outcome of the etching operation ofFIGS.28(a) and28(b)is shown inFIGS.29(a) and29(b)). The surface directional etching process is a selective dry etching process that selectively etches the hard mask layer120′. The selective dry etching process directs an etching species or energetic species in a substantially horizontal direction relative to a horizontal surface of substrate100, thereby achieving horizontal etching of the hard mask layer120′. In this disclosure, the substantially horizontal direction generally refers to the etching species or energetic species being directed towards a horizontal surface of substrate100at an angle of about 0° to about 20° relative to the horizontal surface in the x-y plane (substantially parallel to the horizontal surface of the substrate). In some embodiments, the angle is less than or equal to about 10°. Depending on desired horizontal etching, the angle can be tuned to different values. In some embodiments, the angle can be adjusted so that the etching species or energetic species are along the x axis, y axis, or z axis. In some embodiments, the surface directional etching process is a plasma etching process tuned to cause plasma to flow in an in-plane direction, such as along they axis, over substrate100. Various etching parameters can be tuned to generate etching species (radicals) that travel in a horizontal direction, such as etchant composition, etching temperature, etching time, etching pressure, radio frequency (RF) bias voltage, RF bias power, etchant flow rate, wafer tilting, other suitable etching parameters, or combinations thereof. In some embodiments, RF bias voltage is tuned to achieve an electric field that causes etching species to flow substantially horizontally along an in-plane direction (for example, in they axis direction) relative to a surface over substrate100. In some embodiments, the etching species are tuned to have a profile of momenta of the energetic species such as the momenta of the etching species or energetic species along a frontline are not the same, i.e. the momentum of an etching or energetic species on the top path is different from the momentum of an etching or energetic species on the bottom path. In some embodiments, the momentum of an etching or energetic species on the top path is different from the momentum of an etching or energetic species in the middle path above the bottom path, and the momentum of the etching or energetic species on the top path is the same as or different from the momentum of an etching or energetic species on the bottom path. Any combinations can be achieved by adjustment of the electromagnetic control to tune the energies of the etching or energetic species along the etching front. FIGS.29(a) and29(b)show the remaining hardened patterned hard mask layer150ofFIGS.28(a) and28(b)have an EE length of wHsmaller than the smallest dimension achieved by photolithographic and etching methods used for anisotropic etching of the underlying layer110, thereby forming patterned underlying layer110′ having the same EE length as the hardened hard mask layer150.FIGS.30(a) and30(b)show the patterned underlying layer with the line width of wHsmaller than the smallest dimension achieved by photolithographic and etching method. Additional steps can be provided before, during, and after the operations ofFIGS.22(a),22(b),23(a),23(b),24(a),24(b),25(a),25(b),26(a),26(b),27(a),27(b),28(a),28(b),29(a),29(b),30(a), and30(b), and some of the operations described can be removed, replaced, or eliminated for additional embodiments. Combinations of any of the operations in this disclosure can be performed for other possible embodiments in this disclosure. FIGS.31,32, and33show various views illustrating various stages of a sequential manufacturing operation of a semiconductor device according to an embodiment of the present disclosure. It is understood that additional operations may be provided before, during, and after the operations shown byFIGS.31-33, and some of the operations described below can be replaced or eliminated for additional embodiments of the method. The order of the operations/processes may be interchangeable. FIG.31shows the patterned hard mask layer120′ having top, middle, and bottom gaps formed by photolithographic and etching methods such as the operations ofFIGS.22(a),22(b),23(a),23(b),24(a),24(b),25(a), and25(b), or the operations ofFIGS.10(a),10(b),11(a),11(b),12(a),12(b),13(a),13(b), or the operations of1(a),1(b),2(a),2(b),3(a),3(b),4(a), and4(b). The arrows indicate the direction of the energetic species directed at the left and right sidewalls of the patterned hard mask layer120′. As shown inFIG.31, the patterned hard mask layer120′ is formed by operations as set forth above. The patterned hard mask layer120′ has grooves (the grooves expose the underlying layer110) facing other grooves in the x direction, respectively. InFIG.31, the top groove g1is formed of two portions, i.e. a left groove and a right groove. The middle groove g2is formed of two portions, i.e. a left groove and a right groove. The bottom groove g3is formed of two portions, i.e. a left groove and a right groove. As shown inFIG.31, the distances of separation (width/gap) between adjacent left and right grooves of top, middle, and bottom grooves g1, g2, and g3are not uniform, i.e. the distances between the left and right grooves along x direction at the bottom groove g3and at the top groove g1are larger than the distance between the left and right grooves along x direction in the middle groove g2. In the present embodiment, two directional ion implantation operations31-L and31-R are performed from the right side (R) and the left side (L) as shown inFIG.31. The implanted depths are generally uniform among the grooves. For example, for the smallest “gap” portion of the patterned hard mask layer120′ in the middle groove g2between the left and right grooves along x axis, the implanted ions are distributed in the entirety of the “gap” portion, and the entire middle portion of hard mask120′ between the left and right grooves along x axis becomes a hardened portion. In contrast, for the long distance “gap” portions at the bottom groove g3and at the top groove g1, the peak of the dopant concentration locates in the middle region of the “gap” portion, while end portions of the bottom “gap” portion have less dopant. Accordingly, only the middle region of the “gap” portion is hardened, while the end portions are not. After the implantation, when the etching operation is performed, the hardened portions are not etched, forming substantially uniform end-to-end patterns.FIG.33shows the uniform pattern ends with uniform separation between the left and right grooves of top groove g1′, middle groove g2′, and bottom groove g3′. FIG.32shows an on-going process of applying the energetic species during the bi-directional etching. In particular, applying energetic particles to the top portions of the patterned hard mask layer120′ between the left and right grooves of the top groove g1. The momenta of the energetic species from the left side and from the right side do not enable the species from the left side and the species from the right side to meet each other in the middle gap portion of the patterned hard mask layer120′, and the energetic species reach the border of the gap portion and do not stay in the end portions, causing that the end portions are not hardened and a narrower region (FIGS.32and33) in the top portion of the patterned hard mask layer120′ between the top left and right grooves of top groove g1is not etched by the directional etching (FIG.33). In some embodiments, the method inFIG.32is used to produce a very fine line pattern of the patterned hard mask layer120′ which remains after the directional etching, facilitating etching of the underlying layer110to form a fine line pattern in the underlying layer110to have an EE length smaller than the smallest dimension achieved by the photolithographic and etching methods of the hard mask layer120′. FIG.32shows that in the middle groove g2of the patterned hard mask layer120′, the directional etching species from the left side meet the species from the right side, causing complete overlapping of momenta of the energetic species in the entire gap portion between the left and right grooves along x axis from the species from the right and the species from the left. The momenta cancellation renders the middle gap portion of the patterned hard mask layer120′ between the left and right grooves of the middle groove g2not etched.FIG.33shows that the middle portion of the patterned hard mask layer120′ between the left and right grooves of the middle groove g2, after the directional etching operation ofFIGS.31and32, has an unchanged dimension. FIG.32shows that in the bottom portion of the patterned hard mask layer120′ between the bottom left and right grooves of the bottom groove g3, the energetic species only diffuse into a border of the gap portion of the patterned hard mask layer120′ between end portions and do not stay in the end portions, leaving end portions not hardened by ion implantation by the species.FIG.33shows that, after the directional etching, the left and right end portions of the bottom portion of the patterned hard mask layer120′ are etched while the middle gap portion is not etched, i.e. a situation like the top gap portion between the left and right grooves of the top groove g1of the patterned hard mask layer120′. Therefore,FIGS.31,32, and33provide a demonstration of a method not just for forming a fine line pattern having a dimension or EE length smaller than the smallest dimension achieved by another photolithographic or etching methods, but also for making the line pattern even, i.e. the distances between the grooves along x axis are about the same. In some embodiments, the momenta of the energetic species of the directional etch process from the left side inFIG.31and the momenta of the energetic species of the directional etch process from the right side inFIG.31are controlled to be the same. In some embodiments, the momenta of the energetic species of the directional etch process from the left side inFIG.31are controlled to be different from the momenta of the energetic species of the directional etch process from the right side inFIG.31, achieving different etching rates at the left and right sides. In some embodiments, the momenta of the energetic species of the directional etch process from the left side inFIG.31is controlled to be smaller than the momenta of the energetic species of the directional etch process from the right side inFIG.31, so as to reduce the etching rate on the left side for achieving a final structure having a central axis positioned closer to the left side. This application can be used for evenly etching a tilted substrate to form an even pattern without extensive adjustment of a tilted substrate. FIGS.34,35,36,37,38, and39show cross-sectional views of a semiconductor device, at various fabrication operations, according to an embodiment of the present disclosure.FIG.34shows a structure having a substrate100, a hard mask layer500formed on the substrate100, a bit line (BL)510formed on the hard mask layer500, a metal line (ML)520formed on the BL layer510, and a patterned photoresist layer530formed on the ML layer520, according to some embodiments of the present disclosure. The substrate100is formed of the above mentioned materials. The hard mask layer500includes a silicon nitride layer, according to some embodiments of the present disclosure. The BL layer510is formed of a material including WSi, WN, WSi, and polysilicon, according to some embodiments of the present disclosure. The ML layer520is formed of a material including W and Al, according to some embodiments of the present disclosure. FIG.35shows an operation of anisotropic etching performed to etch the ML layer520, forming patterned ML layer520′. During this operation, a top portion of the photoresist layer530is also etched, according to some embodiments of the present disclosure.FIG.36shows an operation of removal of the photoresist layer530.FIG.37shows an operation of anisotropic etching of the BL layer510, forming patterned BL layer510′, according to some embodiments of the present disclosure. FIG.38shows an operation of ion implantation softening of the patterned ML layer520′, forming softened ML layer520″. The softening of the ML layer520′ is achieved by ion implantation effected by bombarding the surface of the ML layer520′ with at least one of the following ions: nitrogen, oxygen, carbon, boron, aluminum, magnesium, silicon, titanium, yttrium, nickel, fluoride, chloride, and any of the inert gases of helium, neon, argon, krypton, xenon, according to some embodiments of the present disclosure. The ion-implantation parameters include a time duration from a few seconds to about one hour, a dose ranging from about 1×1014to about 1×1018, an energy level from about 10 keV to about 5000 keV, and a current density from about 0.1 μA/cm2to about 10 μA/cm2. The implantation depth is controlled to render the ML layer520′ softened.FIG.39shows an operation of removal of the softened ML layer520″ using a mild etch. In further steps, the BL layer510′ is used as a mask to etch the hard mask layer500. With this process shown inFIGS.34-39, the softened ML layer520″ can be efficiently removed. Additional steps can be provided before, during, and after the operations ofFIGS.31,32, and33, and some of the operations described can be removed, replaced, or eliminated for additional embodiments. Combinations of any of the operations in this disclosure can be performed for other possible embodiments in this disclosure. The present disclosure describes an exemplary method of manufacturing a semiconductor device. The method includes operations of forming a first hard mask over an underlying layer on a substrate by a photolithographic and etching method, forming a sidewall spacer pattern having a first sidewall portion and a second sidewall portion on opposing sides of the first hard mask, etching the first sidewall portion, etching the first hard mask and leaving the second sidewall portion bridging a gap of the etched first hard mask, and processing the underlying layer through the second hard mask. In one or more of the foregoing or following embodiments, in the etching the first hard mask, the first hard mask is fully removed. In one or more of the foregoing or following embodiments, in the etching the first hard mask, the first hard mask is only partially removed. In one or more of the foregoing or following embodiments, the etching the first sidewall portion of the sidewall spacer pattern is performed by directional etching. In one or more of the foregoing or following embodiments, the etching the first hard mask is performed by directional etching. In one or more of the foregoing or following embodiments, the first hard mask has a first width and the second hard mask has a second width smaller than the first width. In one or more of the foregoing or following embodiments, the second width has a value in a range from 0.5 nm to 5 nm. In one or more of the foregoing or following embodiments, the sidewall spacer pattern is formed of a material including silicon nitride. The present disclosure describes another exemplary method of manufacturing a semiconductor device. The method includes operations of forming a first hard mask over a device layer on a substrate by a photolithographic and etching method, hardening a sidewall portion of the first hard mask, etching a portion of the first hard mask contacting the hardened sidewall portion so as to result in a second hard mask comprising the hardened sidewall portion bridging a gap in the etched first hard mask, and processing the device layer through the second hard mask. In one or more of the foregoing or following embodiments, the first hard mask contacting a mid-portion of the hardened sidewall portion, after the etching the portion of the first hard mask, is removed. In one or more of the foregoing or following embodiments, the hardening is performed by directional implantation. In one or more of the foregoing or following embodiments, the etching the portion of the first hard mask contacting the hardened sidewall portion is performed by directional etching. In one or more of the foregoing or following embodiments, the first hard mask has a first width and the second hard mask has a second width smaller than the first width. The present disclosure describes another exemplary method of manufacturing a semiconductor device. The method includes operations of forming a first hard mask over a device layer on a substrate by a photolithographic and etching method, performing a directional etching process to etch opposite side portions of a portion of the first hard mask between two gaps from two opposite directions, and processing the underlying layer through the etched first hard mask. In one or more of the foregoing or following embodiments, the portion of the first hard mask between the two gaps is narrowed to a width or end-to-end distance less than the smallest dimension achieved by the photolithographic and etching method. In one or more of the foregoing or following embodiments, the portion of the first hard mask between the two gaps is not etched by the directional etching. In one or more of the foregoing or following embodiments, the portion of the first hard mask between the two gaps is narrowed. In one or more of the foregoing or following embodiments, momenta of energetic species of the directional etching from the two opposite directions are controlled. In one or more of the foregoing or following embodiments, momenta of energetic species of the directional etching from a left direction of the two opposite direction is controlled to be different from momenta of energetic species of the directional etching from a right direction of the two opposite direction. In one or more of the foregoing or following embodiments, the momenta of the energetic species of the directional etching from the left direction is controlled to be smaller than the momenta of the energetic species of the directional etching from the right direction. The foregoing outlines features of several embodiments or examples so that those skilled in the art may better understand the aspects of the present disclosure. Those skilled in the art should appreciate that they may readily use the present disclosure as a basis for designing or modifying other processes and structures for carrying out the same purposes and/or achieving the same advantages of the embodiments or examples introduced herein. Those skilled in the art should also realize that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and that they may make various changes, substitutions, and alterations herein without departing from the spirit and scope of the present disclosure. | 62,412 |
11862466 | Identical components or components with the same function are denoted with the same reference numbers in the figures. The figures are not true to scale. DETAILED DESCRIPTION OF THE INVENTION FIG.1ashows a basic schematic representation, not true to scale, of two substrates1,2to be bonded. A first substrate1and a second substrate2are pretreated in a first optional process step. The pretreatment can comprise cleaning of the substrates free from chemical and/or physical impurities, for example from particles. Furthermore, an oxide present can be removed in particular wet-chemically and/or dry-chemically, in particular in a suitable vacuum installation with substrate processing.FIG.1ashows a first process step of an exemplary method according to the invention. For greater clarity, substrate holders, vacuum chamber, grippers, pre- and post-processing devices of the substrate-processing device, together with control, energy and media supply, are not represented in the figures. FIG.1bshows a basic schematic representation, not true to scale, of substrates1,2after an amorphisation of the surfaces to be bonded. First substrate1is provided in a device according to the invention (not represented) with a first thin amorphised layer1aand second substrate2is provided in the device according to the invention (not represented) with a second thin amorphised layer2a.FIG.1bis a second process step of an exemplary method. Alternatively, it would be feasible to dispense with one of the two amorphized layers1a,2a. FIG.1cshows a basic schematic representation, not true to scale, of the alignment of substrates1,2to be bonded. First substrate1with first amorphous layer1ais aligned relative to second substrate2with second amorphous layer2ain such a way that amorphous layers1a,2alie on mutually facing surfaces1o,2oof amorphous layers1o,2o. An alignment device is thereby expressly disclosed, but is represented only symbolically with movement direction arrows P.FIG.1cis a third process step of an exemplary method according to the invention. FIG.1dshows a substrate stack3bonded with a prebond in a basic schematic representation not true to scale, which substrate stack has arisen from the two substrates1and2to be bonded. Amorphous layers1aand2ahave been joined together by means of the prebond.FIG.1dshows a fourth process step. FIG.1eshows an effect according to the invention of radiation5on amorphous layers1aand/or2aof substrate stack3, which has been formed from substrates1,2. A radiation source4generates radiation5. The arrows symbolise a relative movement between radiation source4and substrate stack3. In particular, radiation5can scan over substrate stack3in a grid-like manner. In another embodiment, the movement trajectory of the relative movement of a regulation and/or control can be stored, in particular in a control computer not represented, and implemented as a prescribed procedure. Optimum path curves for the minimised thermal loading of substrate regions with temperature-sensitive zones can thus be produced. The modelling and/or calculation of the trajectory can take place based on simulations such as FEM or coupled thermal-mechanical modelling. Thus, all the parameters mentioned earlier can be used for establishing and/or adapting the irradiation time, irradiation location and irradiation path and irradiation intensity of the radiation.FIG.1eshows a fifth process step. FIG.1fshows the heat-treated substrate stack according to the invention in a basic schematic representation, wherein the representation is not true to scale. In the fifth process step carried out according to the invention, the entire bonding interface or the entire amorphous phase has been transformed into a crystalline phase. The substrate stack is thus permanently bonded inseparably. FIG.2shows a basic schematic representation of three substrates1,2,6, which are bonded with the method according to the invention in another embodiment, wherein the representation is not true to scale. A first substrate1and a second substrate2each receive at least one amorphous layer1a,2a. A third substrate6, with which the substrate material does not have to be transparent for the radiation, has two amorphous layers6a. After the joining of substrates1and2to substrate6, a phase transformation according to the invention on both sides simultaneously or offset in time can produce a substrate stack (not represented) comprising more than two substrates. A substrate stack comprising three substrates, preferably comprising four substrates, particularly preferably comprising more than five substrates can expediently be produced using the disclosed method. The following diagram descriptions show, based on calculated data, the absorption and refractive-index behaviour of amorphous and crystalline silicon. The two diagrams are to be regarded as an illustrative example for all other materials, which in certain wavelength ranges exhibit the same behaviour as silicon. FIG.3shows two calculated absorption spectra for amorphous (dotted lines8) and crystalline (continuous line9) Si. The diagram shows absorption index ε as a function of the particle energy, in particular photon energy in eV. Continuous line9represents the absorption behaviour of Si in the crystalline phase as a function of the particle energy. Dotted line8represents the absorption behaviour of Si in the amorphous phase as a function of the particle energy. In particle energy range A between approx. 1.8 eV and 3.0 eV, it can be seen that the amorphous phase has an absorption capacity that is higher by the factor 0.2-18 than the crystalline phase. Particles having a particle energy between 1.8 eV and 3.0 eV are scarcely absorbed by the crystalline phase, but very much so by the amorphous phase. The disclosed method thus utilises ranges of the spectrum in which the absorption of the amorphous phase is greater, in particular at least 1.1 times greater, preferably 2 times greater, still more preferably more than 5 times greater, most preferably more than 10 times greater, with utmost preference more than 20 times greater than the absorption of the crystalline phase. FIG.4shows two calculated refractive index graphs10,11for amorphous (dotted line10) and crystalline (continuous line11) Si. The diagram shows refractive index n as a function of particle energy eV, in particular photon energy. In particle energy range A between approx. 1.8 eV and 3.0 eV, it can be seen that refractive indices n of amorphous and crystalline Si are very similar. All physical processes that are based solely on the refractive index are therefore very similar in this particle energy range A for amorphous and crystalline silicon. The same considerations apply to crystalline material mixtures with amorphised phases, insofar as the amorphous phase can be transformed residue-free into a crystalline phase. FIG.5ashows an enlarged substrate stack3(not true to scale) of two substrates1,2with corresponding amorphous layers1a,2a. Individual atoms a1, a2can be seen, from which the crystalline phases of substrates1a,2aand the amorphous phases of amorphous layers1a,2aare built up. Atoms a1of the crystalline phases of substrates1,2are ordered, atoms a2of amorphous phases1a,2aare disordered. FIG.5bshows enlarged substrate stack3(not true to scale) of substrates1,2with corresponding amorphous layers1a,2a, which are treated with radiation5. Radiation5penetrates essentially unhindered through crystalline substrate2, but is then absorbed by amorphous layers1a,2a. The areas which radiation5has already struck are already crystallised. FIG.5cshows enlarged substrate stack3(not true to scale) of two substrates1,2bonded together almost perfectly without corresponding amorphous layers1a,2a. A dislocation7at the right-hand edge of the figure can be seen. Represented dislocation7is an edge dislocation. It has been marked at its lower end with a symbol known to the person skilled in the art, and additionally outlined with a dashed line. Edge dislocation7represents an additional row of atoms introduced between the otherwise perfect lattice. The distortion of the lattice atoms arising near dislocation7can be seen. Such defects are known to the person skilled in the art in the field. It is explicitly mentioned that such defects may arise with the method according to the invention, but do not have to arise. LIST OF REFERENCE NUMBERS 1First substrate1aFirst amorphous layer of a first substrate1oBonding surface of the first layer2Second substrate2aSecond amorphous layer of a second substrate2oBonding surface of the second layer3Substrate stack4Radiation source of the radiation5Radiation6Third substrate6aAmorphous layer of the third substrate7Dislocation8,9Absorption spectrum10,11Refractive index grapha1, a2AtomsA Particle energy rangeε Absorption indexn Refractive indexP Movement arrows | 8,886 |
11862467 | DETAILED DESCRIPTION OF THE DISCLOSURE The following disclosure provides many different embodiments, or examples, for implementing different features of the invention. Specific examples of components and arrangements are described below to simplify the present disclosure. These are, of course, merely examples and are not intended to be limiting. For example, the formation of a first feature over or on a second feature in the description that follows may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features may be formed between the first and second features, such that the first and second features may not be in direct contact. In addition, the present disclosure may repeat reference numerals and/or letters in the various examples. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed. Also, the components disclosed herein may be arranged, combined, or configured in ways different from the exemplary embodiments shown herein without departing from the scope of the present disclosure. It is understood that those skilled in the art will be able to devise various equivalents that, although not explicitly described herein, embody the principles of the present invention. Further, spatially relative terms, such as “beneath,” “below,” “lower,” “above,” “upper” and the like, may be used herein for ease of description to describe one element or feature's relationship to another element(s) or feature(s) as illustrated in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The apparatus may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein may likewise be interpreted accordingly. The fins may be patterned by any suitable method. For example, the fins may be patterned using one or more photolithography processes, including double-patterning or multi-patterning processes. Generally, double-patterning or multi-patterning processes combine photolithography and self-aligned processes, allowing patterns to be created that have, for example, pitches smaller than what is otherwise obtainable using a single, direct photolithography process. For example, in one embodiment, a sacrificial layer is formed over a substrate and patterned using a photolithography process. Spacers are formed alongside the patterned sacrificial layer using a self-aligned process. The sacrificial layer is then removed, and the remaining spacers may then be used to pattern the fins. Multi-gate devices have been introduced in an effort to improve gate control by increasing gate-Channel coupling, reduce OFF-state current, and reduce short-channel effects (SCEs). One such multi-gate device that has been introduced is the fin field-effect transistor (FinFET). The FinFET gets its name from the fin-like structure which extends from a substrate on which it is formed, and which is used to form the FET channel. FinFETs are compatible with conventional complementary metal-oxide-semiconductor (CMOS) processes and their three-dimensional structure allows them to be aggressively scaled while maintaining gate control and mitigating SCEs. However, ion implantation of dopants through fins of FinFET devices, as done in current fabrication methods, may result in a non-uniform doping profile, which among other issues can cause non-linearity of capacitance of the device. Thus, existing techniques have not proved entirely satisfactory in all respects. A semiconductor device may perform various digital and analog functions. Some semiconductor device may have analog-rich circuit design, such as image signal processor (ISP). Analog-rich circuit design requires high linearity capacitor through voltage biasing. However, it is hard to provide such high linearity capacitor in fin-based devices. In a typical process for manufacturing a semiconductor device, doped regions or well regions in a substrate are all formed by implanting ions into the substrate from a surface on which devices are formed and driving-in the ions to form the doped regions and well regions by anneal. However, it is found that the well region may have non-uniform doping profile from the shallow implantation regions to the deep implantation regions after annealing. For example, when the implantation is performed after the fins are formed on the substrate, such non-uniformity becomes more obvious due to such non-planar structure. Since the dopant concentration shows Gaussian distribution with respect to different levels of depth in the target to be implanted, the longer path the ionized dopants have to travel in the target, the more evident the Gaussian distribution can be observed. Such dopant concentration distribution undermines the uniformity of the dopant concentration at predetermined regions through the fin structure and thus reduces the device performance. Given the above discussion, a fin-based device with a uniformly doped region is desired in achieving improved linearity in capacitance and enhanced device performance. Examples of devices that can benefit from one or more embodiments of the present invention are semiconductor devices. Such a device may include a P-type metal-oxide-semiconductor FinFET device or an N-type metal-oxide-semiconductor FinFET device. The FinFET device may be a dual-gate device, tri-gate device, bulk device, silicon-on-insulator (SOI) device, and/or other configuration. One of ordinary skill may recognize other examples of semiconductor devices that may benefit from aspects of the present disclosure. For example, some embodiments as described herein may also be applied to gate-all-around (GAA) devices, Omega-gate (Ω-gate) devices, or Pi-gate (Π-gate) devices. With reference toFIG.1andFIGS.2to9, a method100and a semiconductor structure200are collectively described below. It is understood that parts of the method100and/or the semiconductor structure200may be fabricated by a well-known complementary metal-oxide-semiconductor (CMOS) technology process flow, and thus some processes are only briefly described herein. Further, the semiconductor structure200may include various other devices and features, such as additional transistors, bipolar junction transistors, resistors, capacitors, diodes, fuses, etc., but is simplified for a better understanding of the inventive concepts of the present disclosure. Further, in some embodiments, the semiconductor structure200includes a plurality of semiconductor devices (e.g., transistors), which may be interconnected. The semiconductor structure200may be an intermediate device fabricated during processing of an integrated circuit, or portion thereof, that may comprise static random access memory (SRAM) and/or other logic circuits, passive components such as resistors, capacitors, and inductors, and active components such as P-channel field-effect transistors (PFETs), N-channel FETs (NFETs), metal-oxide-semiconductor field-effect transistors (MOSFETs), complementary metal-oxide-semiconductor (CMOS) transistors, bipolar transistors, high voltage transistors, high frequency transistors, other memory cells, and/or combinations thereof. Moreover, it is noted that the process steps of the method100, including any descriptions given with reference toFIGS.2-9, are merely exemplary and are not intended to be limiting beyond what is specifically recited in the claims that follow. FIG.1is a flow chart of a method100for manufacturing a semiconductor structure according to various aspects of the present disclosure. In the present embodiment, the method100is for manufacturing a semiconductor structure that includes a fin structure. The method100includes a number of operations (102,104,106,108,110,112,114and116). The method for manufacturing the semiconductor structure100will be further described according to one or more embodiments. It should be noted that the operations of the method for manufacturing the semiconductor structure100may be rearranged or otherwise modified within the scope of the various aspects. It should further be noted that additional processes may be provided before, during, and after the method100, and that some other processes may only be briefly described herein. Thus, other implementations are possible within the scope of the various aspects described herein. FIGS.2-9illustrate diagrammatic cross-sectional side views of one embodiment of a semiconductor structure200at various stages of fabrication, according to the method100ofFIG.1. In some embodiments, a semiconductor structure200includes any fin-based device, including double-gate field effect transistor, tri-gate field effect transistor (TGFET), multi-gate field-effect transistor (MuGFET). The semiconductor structure200may be included in a microprocessor, memory cell, and/or other integrated circuit device.FIGS.2-9have been simplified for the sake of clarity to better understand the inventive concepts of the present disclosure. Additional features can be added in the semiconductor structure200, and some of the features described below can be replaced or eliminated in other embodiments of the semiconductor structure200. The method100begins at operation102where a substrate210is provided or received. In some embodiments, the substrate210includes a silicon substrate (e.g., wafer). The substrate210may be silicon in a crystalline structure. In other embodiments, the substrate210may include other elementary semiconductors such as germanium in a crystalline structure, a compound semiconductor, such as silicon germanium, silicon carbide, gallium arsenic, gallium phosphide, indium phosphide, indium arsenide, and/or indium antimonide; or combinations thereof. In some embodiments, the substrate210includes a silicon-on-insulator (SOI) substrate. The SOI substrate may be fabricated using separation by implantation of oxygen (SIMOX), wafer bonding, and/or other suitable methods. The substrate210may further include various doped regions and other suitable features. In some embodiments, the substrate210can include isolation structures (i.e., shallow trench isolation (STI) structures) (not shown) interposing regions accommodating different devices. In some embodiments, an anti-punch through (APT) dopant implantation process may be performed to form an APT region (not shown) in the substrate210, The APT region may be an n-type APT region or a p-type APT region. By way of example, a p-type dopant implanted into the p-type APT region may include boron, aluminum, gallium, indium, or other p-type acceptor material; and an n-type dopant implanted via the ion implantation process into the n-type APT region may include arsenic, phosphorous, antimony, or other n-type donor material. It will be understood that the APT dopant implantation steps may be performed in any order, for example, the n-type APT region may be implanted before or after the p-type APT region. Further, when performing the APT dopant implantation, for the p-type APT region, a patterned resist layer can be formed to protect the n-type ATP region. Similarly, another patterned resist layer can be formed to protect the p-type ATP region when performing the APT dopant implantation for the n-type APT region. After the ion implantation processes, the patterned resist layers may be removed, for example, by way of a solvent, resist stripper, asking, or other suitable technique. Additionally, in various embodiments, an APT implant may have a high dopant concentration, for example, of between about 1×10 cm−3and 1×1019cm−3. In some embodiments, a dielectric layer may be formed over the substrate210and serve as a pad layer. The dielectric pad layer can be formed by any suitable process to any suitable thickness. In some embodiments, the dielectric pad layer includes silicon oxide and is formed by a CVD or a thermal oxidation process. The thermal oxidation process may be a dry or a wet process. In various examples, the silicon oxide can be formed by physical vapor deposition (PVD), atomic layer deposition (ALD), high density plasma. CVD (HDPCVD), other suitable methods, and/or combinations thereof. The CVD process, for example, may use chemicals including hexachlorodisilane (HCD or Si2Cl6), dichlorosilane (DCS or SiH2C12), bis(tertiarybutylamino) silane (BTBAS or C8H22N2Si) and disilane (DS or Si2H6). A mask layer is then formed over the dielectric pad layer. In some embodiments, the mask layer includes silicon nitride and is formed by a CVD process. The mask layer may be a stop/hard mask layer. The mask layer can be formed by any suitable process to any suitable thickness. The mask layer may include a material such as silicon nitride, silicon oxide, silicon oxynitride, silicon carbide, silicon carbon nitride, other suitable material, or combinations thereof. In various examples, the silicon nitride can be formed by physical vapor deposition (PVD), atomic layer deposition (ALD), high density plasma CVD (HDPCVD), other suitable methods, and/or combinations thereof. The CVD process, for example, may use chemicals including hexachlorodisilane (HCD or Si2Cl6), dichlorosilane (DCS or SiH2C12), bis(tertiarybutylamino) silane (BTBAS or C8H22N2Si) and disilane (DS or Si2H6). A photoresist layer may be formed over the mask layer. The photoresist layer is formed by any suitable process to any suitable thickness. At operation104, a fin structure212is formed over the substrate210. In an embodiment, the fin structure212is a silicon fin (Si-fin). The layer of silicon may be a silicon layer of an SOI substrate. The fin structure212may have a height ranging from about 20 nm to about 100 nm. In sine embodiments, the height ranges from about 50 nm to about 70 nm. The fin structure212may be formed by any suitable process, such as a photolithography and etching process. In some embodiments, the fin structure212is formed by exposing the photoresist layer to a pattern, performing a post-exposure bake process, and developing the photoresist layer to for a masking element. The photoresist layer patterning may include processing steps of photoresist coating, soft baking, mask aligning, exposing pattern, post-exposure baking, developing photoresist, and hard baking. The patterning may also be implemented or replaced by other proper methods, such as maskless photolithography, electron-beam writing, ion-beam writing, and molecular imprint. In some embodiments, the masking element may be transferred to the mask layer and the dielectric pad layer. Such that a patterned mask is obtained. In some embodiments, the patterned mask layer is used in an etching process to etch the substrate210. Accordingly, the fin structure212is formed over the substrate210, as shown inFIG.2. The etching process uses the patterned mask layer to define the area to be etched and to protect other regions of the FinFET device. The etching process may include a wet etching process, a dry etching process, or a combination thereof. In some embodiments, the fin structure212may be formed by an etching process using a reactive ion etch (RIE) and/or other suitable process. In one example, a hydrofluoric acid (HF) or buffered HF may be used to etch the dielectric pad layer to expose the substrate210according to the pattern defined by the mask layer. In one example, a dry etching process used to etch the substrate210includes a chemistry including fluorine-containing gas. In a further example, the chemistry of the dry etch includes CF4, SF6, or NF3. Alternatively, the fin structure212is formed by a double-patterning lithography (DPL) process. DPI, is a method of constructing a pattern on a substrate210by dividing the pattern into two interleaved patterns. DPL allows enhanced feature (e.g., fin) density. Various DPL methodologies may be used, including, double exposure (e.g., using two mask sets), forming spacers adjacent features and removing the features to provide a pattern of spacers, resist freezing, and/or other suitable processes. It is understood that multiple parallel fin structures may be formed in a similar manner. The method100then proceeds to operation106where an insulation material220is deposited over the fin structure212. The insulation material220may be deposited such that it covers the fin structure212. In one embodiment, the insulation material220includes silicon oxide. The silicon oxide can be deposited by a CVD process. In various examples, the silicon oxide can be formed by physical vapor deposition (PVD), atomic layer deposition (ALD), high density plasma CVD (HDPCVD), other suitable methods, and/or combinations thereof. The silicon oxide may be alternatively formed by a high aspect ratio process (HARP). In various embodiments, an optional thermal oxide trench liner may be grown to improve the trench interface. The CVD process, for example, may use chemicals including hexachlorodisilane (HCD or Si2Cl6), dichlorosilane (DCS or SiH2Cl2), bistTertiarybutylamino) silane (BTBAS or C8H22N2Si) and disilane (DS or Si2H6). A planarizing process may be performed such that the top surface of the insulation material220is planarized. In some embodiments, the top of the fin structure212may be exposed. The planarizing process includes a chemical mechanical polishing (CMP) process applied to the FinFET device to remove excessive portions of the insulation material. Referring toFIG.3, in some embodiments, top surface of the fin structure212can be aligned with a top surface of the insulation material220, but the disclosure is not limited thereto. The method100continues with operation108where a multi-implantation300is applied to the fin structures212and the insulation material220, using suitable dopants, such as p-type dopants (e.g., boron or indium) and/or n-type dopants (e.g., arsenic or phosphorous). In some embodiments, the multi-implantation300can be referred to a plurality of ions implantation cycles performed in-situ. In some embodiments, an in-situ multi-implantation comprises performing the plurality of ion implantation cycles in a vacuum chamber without releasing the vacuum. In some embodiments, each of the ion implantation cycles is conducted with an implantation energy from about 10 KeV to about 70 KeV, but the disclosure is not limited thereto. In some embodiments, each of the ion implantation is conducted with an implantation dose from about 1E15 atm/cm2to about 5E15 atm/cm2, but the disclosure is not limited thereto. In some embodiments, the implantation dose in each ion implantation can be the same. In some alternative embodiments, the implantation dose may be increased or decreased stepwise. The dopants used in each of the ion implantation cycles include any suitable dopants, such as p-type dopants (e.g., boron or indium) and/or n-type dopants (e.g., arsenic or phosphorous). In some embodiments, each of the ion implantation cycles may be conducted at a constant temperature. For example, each implantation may be conducted at room temperature. In some alternative embodiments, the implantation cycles may be conducted in a stepwise increased or decreased temperature. Each of the ion implantation cycles may be performed with a tilt angle with respect to the vertical axis, in a range from about 5° to about 70°. For example in some embodiments, the tilt angle is from about 15° to about 50°, but the disclosure is not limited thereto. In some embodiments, the tilt angle in each ion implantation can be the same. In some alternative embodiments, the tilt angle may be increased or decreased stepwise. In some embodiments, the multi-implantation300includes at least two ion implantation cycles. In some embodiments, the two ion implantation cycles may be performed with substantially identical energy. In other embodiments, the multi-implantation300includes four ion implantation cycles with substantially identical energy. For example, each of the four ion implantation cycles is applied with an implantation energy of about 20 KeV, but the disclosure is not limited thereto. In some embodiment, the multi-implantation300may include two ion implantation cycles with stepwise increased or decreased energy. For example, the applied energy at the first ion implantation is from about 40 KeV to about 70 KeV such that a first implanted region in the fin structure is formed; and the applied energy at the second ion implantation is from about 10 KeV to about 40 KeV such that a second implanted region is formed. For example, the applied energy at the first ion implantation is from about 40 KeV to about 70 KeV at room temperature with a tilt angle from about 15° to about 50°; and the applied energy at the second ion implantation is from about 10 KeV to about 40 KeV at room temperature with a tilt angle from about 15° to about 50°. For example, the applied energy at the first ion implantation is from about 40 KeV to about 70 KeV at room temperature with a tilt angle from about 15° to about 30°; and the applied energy at the second ion implantation is from about 10 KeV to about 40 KeV at room temperature with a tilt angle from about 30° to about 50°. In some embodiments, the first implantation region in the fin structure is deeper than the second implantation region. For example, the first implantation region is located at a depth (from top to bottom) of about 30% to about 50% of the fin structure212and the second implantation region is located at a depth of about 30% or less of the fin structure212. For example, in a multi-implantation300including three ion implantation cycles, the applied energy at the first ion implantation is from about 40 KeV to about 70 KeV, such that a first implanted region300A is formed, as shown inFIG.4. The applied energy at the second ion implantation t is from about 20 KeV to about 40 KeV, such that a second implanted region300B is formed, as shown inFIG.5. The applied energy at the third ion implantation is from about 10 KeV to about 20 KeV, such that a third implantation region300C is formed, as shown inFIG.6. For example, the applied energy at the first ion implantation is from about 40 KeV to about 70 KeV at room temperature with a tilt angle from about 15° to about 50°; the applied energy at the second ion implantation is from about 20 KeV to about 40 KeV at room temperature with a tilt angle from about 15° to about 50°; and the applied energy at the third ion implantation is from about 10 KeV to about 20 KeV at room temperature with a tilt angle from about 15 to about 50°. For example, the applied energy at the first ion implantation is from about 40 KeV to about 70 KeV at room temperature with a tilt angle from about 5° to about 20°; the applied energy at the second ion implantation is from about 25 KeV to about 40 KeV at room temperature with a tilt angle from about 20° to about 40°; and the applied energy at the second ion implantation is from about 10 KeV to about 20 KeV at room temperature with a tilt angle from about 40° to about 70°. In some embodiments, the first implanted region300A as shown inFIG.4is located at a depth (from top to bottom) of about 35% to about 50% of the fin structure212, the second implantation region300B is located at a depth of about 15% to about 35% of the fin structure212and the third implantation region300C is located at a depth of about 15% or less of the fin structure212. The method100then proceeds to operation110where a well anneal is performed at a temperature above approximately 1000° C. In one embodiment, the well anneal may be performed between about 1000° C. to about 1100° C. In some examples, the well anneal may be performed for a duration of few seconds, such as about 10 s. While some examples of annealing temperature and duration have been given, these examples are merely exemplary and are not meant to be limiting in any way. Other annealing temperatures and/or durations may also be used in accordance with various process conditions and/or device requirements, as known in the art. Consequently, a well region214is formed in each of the fin structure212as shown inFIG.7. As discussed above, the dopant concentration shows Gaussian distribution with respect to different levels of depth in the target to be implanted. Applying implantation several times with substantially identical energy or different energy levels provides the fin structure212with uniform doping profile after annealing. At operation112, at least a portion of the insulation material220is removed to expose a portion of the fin structure212. In one embodiment, the at least a portion of the insulation material may be removed by an etching process, which includes etching back the insulation material such that the sidewalk of the fin structure212are exposed, as shown inFIG.8. It should be noted that during the multi-implantation300, a portion of the insulating material230may be damaged. However, those portions damaged by the multi-implantation300may be removed at operation112. Consequently, adverse impact to the remained insulation material can be mitigated. At operation114, in which a gate structure is formed over a portion of the fin structure212. The gate structure includes a gate dielectric layer410and a gate electrode420. In an embodiment, the gate dielectric layer410may include silicon oxide. The silicon oxide may include a thickness ranging from about 1 to about 3 nm. In other embodiments, the gate dielectric layer410may optionally include other dielectric materials such as, silicon nitride, silicon oxynitride, dielectric with a high dielectric constant (high k), and/or combinations thereof. Examples of high k materials include hafnium silicate, hafnium oxide, zirconiwn oxide, aluminum oxide, hafnium dioxide-alumina (HfO2—Al2O3) alloy, and/or combinations thereof. The gate dielectric layer may be formed using processes such as, photolithography patterning, oxidation, deposition, etching, and/or other suitable processes. The gate electrode420may include polysili con, silicon-germanium, a metal including metal compounds such as, Mo, Cu, W, Ti, Ta, TaN, NiSi, CoSi, and/or other suitable conductive materials known in the art. The gate electrode420may be formed using processes such as, physical vapor deposition (PVD), chemical vapor deposition (CVD), plasma-enhanced chemical vapor deposition (PECVD), atmospheric pressure chemical vapor deposition (APCVD), low-pressure CVD (LPCVD), high density plasma CVD (HD CVD), atomic layer CVD (ALCVD), and/or other suitable processes which may be followed, for example, by photolithography and/or etching processes. In some embodiments, the method100may continue to provide steps of fabricating other features of semiconductor elements, including, for example, forming contact, interconnect structures, and/or other suitable processes and features. In one embodiment, the protection layer may be removed. In other embodiments, the protection layer may remain over the fin structure in the final device. Additional steps can be provided before, during, and after the method100, and some of the steps described can be replaced or eliminated for other embodiments of the method. The discussion that follows illustrates various embodiments of a semiconductor structure that can be fabricated according to the method100ofFIG.1. FIGS.10-19illustrate diagrammatic cross-sectional side views of one embodiment of a semiconductor structure200at various stages of fabrication, according to the method100ofFIG.1. It should be noted that similar elements inFIGS.2-9andFIGS.10-19are designated by the same numerals, and can include similar materials, therefore those details are omitted in the interest of brevity. In some embodiments, a semiconductor structure200includes any fin-based device, including double-gate field effect transistor, tri-gate field effect transistor (TGFET), multi-gate field-effect transistor (MuGFET).FIG.20illustrates a perspective view of one embodiment of a fin-based device. The semiconductor structure200may be included in a microprocessor, memory cell, and/or other integrated circuit device.FIGS.10-19have been simplified for the sake of clarity to better understand the inventive concepts of the present disclosure. Additional features can be added in the semiconductor structure200, and some of the features described below can be replaced or eliminated in other embodiments of the semiconductor structure200. Referring toFIG.10, at operation102, a substrate (e.g., wafer)210is provided or received, and a fin structure212(including a plurality of fins each having first and second sidewalls) is formed over the substrate210at operation104. The substrate210is a bulk silicon substrate. Alternatively, the substrate210comprises an elementary semiconductor, such as silicon or germanium in a crystalline structure. As mentioned above, the substrate210may have an anti-punch-through (APT) layer. In some embodiments, the APT layer may be a semiconductor layer comprising APT dopants suitable for preventing source/drain punch through in n-type devices. For example, the APT layer may comprise silicon carbon boron (SiCB), silicon boron (SiB), and the like. In embodiments when the APT layer comprises SiCB, the carbon atoms may prevent (or at least reduce) the diffusion of APT dopants (e.g., boron) into surrounding device layers. In such embodiments, an atomic concentration of C in APT layer may be about 0.5% to about 1%. Furthermore, the APT layer may have a thickness of about 3 nm to about 10 nm. In one embodiment, the APT layer may be formed before the fin structure212is formed on the substrate210. The fin structure212is formed on the substrate210by any suitable process, such as a photolithography and etching process. The fin structure212includes one or more fins each having first and second sidewalls. In an embodiment, the fin structure212includes silicon. In other embodiments, the fin structure212may optionally include germanium. In an embodiment, the fin structure208may be disposed on the insulator layer. The fin structure212may have a depth ranging from about 20 nm to about 100 nm. In one embodiment, the depth ranges from about 50 nm to about 70 nm. At operation106, with further reference toFIG.11, deposited over the substrate210(and over the fin structure212) is an insulation material220. The insulation material220is deposited such that the insulation material220surrounds and isolates the fins from each other. The insulation material220may include an insulating material such as silicon oxide, silicon nitride, silicon oxynitride, low k materials, air gap, other suitable material, or combinations thereof. The insulation material220may have a multi-layer structure, for example, a thermal oxide liner layer with silicon nitride formed over the substrate. The top surface of the insulation material220may be planarized with a planarizing process. In one embodiment, the top portion of the fin structure may be exposed. As shown in an example ofFIG.12, in some embodiments, a sacrificial layer230may be formed on the top of each fin structure212; or formed on the top of each fin structure212or also onto the insulation material220as shown inFIG.12. The sacrificial layer230may be a silicon oxide layer, which is used to protect the fin structure212against any damages (such as crystal damage) generated due to the following multi-implantation processes, so as to ensure high device performance. The thickness of the sacrificial layer230is from about 40 Å to about 80 Å, but the disclosure is not limited thereto. In on example, the thickness of the sacrificial oxide230is about 60 Å, but the embodiments are not limited thereto. In some comparative approaches, when the thickness of the sacrificial layer230is less than 40 Å, it may not be thick enough to protect the fin structure212. In other comparative approaches, when the thickness of the sacrificial layer230is greater than 80 Å, it may too thick to block the following multi-implantation. With further reference toFIG.13, a multi-implantation300is applied to the fin structures212and the insulation material220at operation108. The multi-implantation300can be referred to a plurality of ions implantation cycles performed in-situ. In some embodiment, implantation energy of each of the ion implantation cycles is from about 10 KeV to about 70 KeV, but the disclosure is not limited thereto. In some embodiments, an implantation dose of each of the ion implantation cycles is from about 1E15 atm/cm2to about 5E15 atm/cm2, but the disclosure is not limited thereto. The implantation dose in each ion implantation may be the same. In some embodiments, the implantation dose may be increased or decreased stepwise. The dopants used in each of the ion implantation cycles include any suitable dopants, such as p-type dopants (e.g., boron or indium) and/or n-type dopants (e.g., arsenic or phosphorous). In some embodiments, each of the ion implantation cycles may be conducted in a constant temperature. For example, each implantation may be conducted at room temperature. Each ion implantation may be a tilt implantation, which is performed at a tilt angle θ with respect to the vertical axis from about 5° to about 70°. For example in some embodiments, the tilt angle θ is from about 15° to about 50°, but the disclosure is not limited thereto. In some embodiments, the multi-implantation300may include at least two ion implantation cycles applied with substantially identical energy. In some embodiments, the multi-implantation300may include four ion implantation cycles applied with substantially identical energy. In some embodiments, the multi-implantation300may include two ion implantation cycles with stepwise increased or decreased energy. For example, the multi-implantation300may include three ion implantation cycles, the applied energy at the first ion implantation is from about 40 KeV to about 70 KeV, such that a first implanted region300A is formed, as shown inFIG.13. The applied implantation energy at the second ion implantation is from 20 KeV to 40 KeV, such that a second implanted region300B is formed, as shown inFIG.14. The applied implantation energy at the third ion implantation is from about 10 KeV to about 20 KeV, such that a third implanted region300C is formed, as shown inFIG.15. The method100then proceeds to operation110where a well anneal is performed at a temperature above approximately 1000° C., In one embodiment, the well anneal may be performed between about 1000° C. to about 1100° C. In some examples, the well anneal may be performed for a duration of few seconds, such as about 10 s. While some examples of annealing temperature and duration have been given, these examples are merely exemplary and are not meant to be limiting in any way. Other annealing temperatures and/or durations may also be used in accordance with various process conditions and/or device requirements, as known in the art. Consequently, a well region214is formed in each of the fin structure212, as shown inFIG.16. In some embodiments, the sacrificial layer230can be removed after annealing. As discussed above, the dopant concentration shows Gaussian distribution with respect to different levels of depth in the target to be implanted. Applying implantation several times with substantially identical energy or different energy levels provides the fin structure212with uniform doping profile after annealing. At operation112, a portion of the insulation material230is removed. With further reference toFIG.17, the sidewalls of the fin structure212are exposed by removing at least a portion of the insulation material220. In one embodiment, the top of the fin structure212may also be exposed by removing the sacrificial oxide230. With further reference toFIGS.18to20, a gate structure400is formed over a portion of the fin structure212. The gate structure400includes a gate dielectric layer410and a gate electrode420. The gate dielectric layer410is formed along sidewalls and over a top of the fin structure212, and the gate electrode420is formed over the gate dielectric layer410. Source/drain regions500and600are formed in opposite sides of the fin structure212with respect to the gate structure400. Referring toFIG.20, accordingly, the semiconductor structure200includes a fin structure212, a gate dielectric layer410covering a portion of the fin structure210, a gate electrode420over the gate dielectric layer410, a source/drain regions500and600formed in opposite sides of the fin structure212with respect to the gate structure400. As mentioned above, the multi-implantation300improves the uniformity of the dopant concentration in the fin structure212. In some embodiments, the dopant concentration at the sidewalk of the fin structure212is substantially identical to that at the top of the fin structure212. With the multi-implantation300, the resulting semiconductor structure200of the present invention has linearity in capacitance less than about 5% as applied with a gate voltage from −3V to 3V. In one embodiment, the resulting semiconductor structure has linearity of capacitance less than 3% as applied with a gate voltage from −3V to 3V. The improved linearity in capacitance improves the device performance.FIG.21shows that, compared to semiconductor structures200with a tin structure undergoing one implantation (see lines B and C), the semiconductor structure of the present invention has smooth capacitance density (see line A) as the gate voltage increases. In the present disclosure, a method of manufacturing a semiconductor structure comprises providing a substrate; forming a plurality of fin structures over the substrate; forming an insulation material in a plurality of gaps between the fin structures; forming a sacrificial layer on the fin structures and the insulation material; applying a plurality of ion implantation cycles to the fin structures; and removing at least a portion of the insulation material to expose at least a top portion of each fin structure, wherein applying the plurality of ion implantation cycles comprises applying different implantation energies. In some embodiments, a method of manufacturing a semiconductor structure comprises providing a substrate; forming a plurality of tin structures over the substrate; forming an insulation material in a plurality of gaps between the fin structures; forming a sacrificial layer on the fin structures and the insulation material; applying a plurality of ion implantation cycles to the fin structures in-situ with stepwise increased or decreased energy and in a stepwise increased or decreased temperature; and removing at least a portion of the insulation material to expose at least a top portion of each fin structure, wherein applying the plurality of ion implantation cycles comprises: performing a first ion implantation with a first implantation energy to form a first implanted region of the fin structures; performing a second ion implantation with a second implantation energy to form a second implanted region of the tin structures; and performing a third ion implantation with a third implantation energy to form a third implanted region of the fin structures. In some embodiments, a method of manufacturing a semiconductor structure, comprises providing a substrate; forming a plurality of fin structures over the substrate; forming an insulation material in a plurality of gaps between the fin structures; forming a sacrificial layer on the fin structures and the insulation material; applying a first ion implantation to the fin structures with a first implantation energy to form a first implanted region of the fin structures; applying a second ion implantation to the fin structures with a second implantation energy to form a second implanted region of the fin structures; applying a third ion implantation to the fin structures with a third implantation energy to form a third implanted region of the fin structures; and removing at least a portion of the insulation material to expose at least a top surface of each fin structure, wherein the first implantation energy is greater than the second implantation energy, and the second implantation energy is greater than the third implantation energy, and wherein each of the plurality of ion-implantation cycles is applied with a tilt angle with respect to the vertical axis from about 5° to about 70°. The foregoing outlines features of several embodiments so that those skilled in the art may better understand the aspects of the present disclosure. Those skilled in the art should appreciate that they may readily use the present disclosure as a basis for designing or modifying other processes and structures for carrying out the same purposes and/or achieving the same advantages of the embodiments introduced herein. Those skilled in the art should also realize that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and that they may make various changes, substitutions, and alterations herein without departing from the spirit and scope of the present disclosure. | 41,324 |
11862468 | DETAILED DESCRIPTION The following disclosure provides many different embodiments, or examples, for implementing different features of the invention. Specific examples of components and arrangements are described below to simplify the present disclosure. These are, of course, merely examples and are not intended to be limiting. For example, the formation of a first feature over or on a second feature in the description that follows may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features may be formed between the first and second features, such that the first and second features may not be in direct contact. In addition, the present disclosure may repeat reference numerals and/or letters in the various examples. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed. Further, spatially relative terms, such as “beneath,” “below,” “lower,” “above,” “upper” and the like, may be used herein for ease of description to describe one element or feature's relationship to another element(s) or feature(s) as illustrated in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The apparatus may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein may likewise be interpreted accordingly. In accordance with some embodiments, an annealing process is performed to repair defects in a replacement gate stack. One or more sacrificial layers are formed to protect the gate dielectric layer of the gate stack during annealing. The sacrificial layers include a layer of silicon formed with a slow deposition process, which allows the sacrificial layer to be formed with a high degree of conformality. Forming the sacrificial layer with a high degree of conformality allows the sacrificial layer to be removed while avoiding damage to underlying fins, particularly when the underlying fins are close together. FIG.1illustrates an example of simplified Fin Field-Effect Transistors (FinFETs) in a three-dimensional view, in accordance with some embodiments. Some other features of the FinFETs (discussed below) are omitted for illustration clarity. The illustrated FinFETs may be electrically coupled in a manner to operate as, for example, one transistor or multiple transistors, such as four transistors. The FinFETs include fins62extending from a substrate50. Shallow trench isolation (STI) regions66are disposed over the substrate50, and the fins62protrude above and from between neighboring STI regions66. Although the STI regions66are described/illustrated as being separate from the substrate50, as used herein the term “substrate” may be used to refer to just the semiconductor substrate or a semiconductor substrate inclusive of isolation regions. Additionally, although the fins62are illustrated as being a single, continuous material of the substrate50, the fins62and/or the substrate50may include a single material or a plurality of materials. In this context, the fins62refers to the portions extending above and from between the neighboring STI regions66. Gate structures110are over channel regions of the fins62. The gate structures110include gate dielectrics112and gate electrodes114. The gate dielectrics112are along sidewalls and over top surfaces of the fins62, and the gate electrodes114are over the gate dielectrics112. Source/drain regions92are disposed in opposite sides of the fins62with respect to the gate dielectrics112and gate electrodes114. Gate spacers94separate the source/drain regions92from the gate structures110. In embodiments where multiple transistors are formed, the source/drain regions92may be shared between various transistors. In embodiments where one transistor is formed from multiple fins62, neighboring source/drain regions92may be electrically coupled, such as through coalescing the source/drain regions92by epitaxial growth, or through coupling the source/drain regions92with a same source/drain contact. One or more inter-layer dielectric (ILD) layer(s) (discussed further below) are over the source/drain regions92and/or gate electrodes114, through which contacts (discussed further below) to the source/drain regions92and the gate electrodes114are formed. FIG.1further illustrates several reference cross-sections. Cross-section A-A is along a longitudinal axis of a fin62and in a direction of, for example, a current flow between the source/drain regions92of a FinFET. Cross-section B-B is perpendicular to cross-section A-A and is along a longitudinal axis of a gate electrode114. Cross-section C-C is perpendicular to cross-section A-A and extends through source/drain regions92of the FinFETs. Subsequent figures refer to these reference cross-sections for clarity. Some embodiments discussed herein are discussed in the context of FinFETs formed using a gate-last process. In other embodiments, a gate-first process may be used. Also, some embodiments contemplate aspects used in planar devices, such as planar FETs. FIGS.2through9are cross-sectional views of intermediate stages in the manufacturing of FinFETs, in accordance with some embodiments.FIGS.2through9illustrate reference cross-section A-A illustrated inFIG.1, except for multiple fins/FinFETs. InFIG.2, a substrate50is provided. The substrate50may be a semiconductor substrate, such as a bulk semiconductor, a semiconductor-on-insulator (SOI) substrate, or the like, which may be doped (e.g., with a p-type or an n-type dopant) or undoped. The substrate50may be a wafer, such as a silicon wafer. Generally, an SOI substrate is a layer of a semiconductor material formed on an insulator layer. The insulator layer may be, for example, a buried oxide (BOX) layer, a silicon oxide layer, or the like. The insulator layer is provided on a substrate, typically a silicon or glass substrate. Other substrates, such as a multi-layered or gradient substrate may also be used. In some embodiments, the semiconductor material of the substrate50may include silicon; germanium; a compound semiconductor including silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, and/or indium antimonide; an alloy semiconductor including silicon-germanium, gallium arsenide phosphide, aluminum indium arsenide, aluminum gallium arsenide, gallium indium arsenide, gallium indium phosphide, and/or gallium indium arsenide phosphide; or combinations thereof. The substrate50has an n-type region50N and a p-type region50P. The n-type region50N can be for forming n-type devices, such as NMOS transistors, e.g., n-type FinFETs. The p-type region50P can be for forming p-type devices, such as PMOS transistors, e.g., p-type FinFETs. The n-type region50N may be physically separated from the p-type region50P, and any number of device features (e.g., other active devices, doped regions, isolation structures, etc.) may be disposed between the n-type region50N and the p-type region50P. One or more dielectric layers52are formed on the substrate50. The dielectric layers52will be used to pattern the substrate50. In the illustrated embodiment, the dielectric layers52include a first dielectric layer52A over the substrate50, a second dielectric layer52B over the first dielectric layer52A, and a third dielectric layer52C over the second dielectric layer52B. The first dielectric layer52A may be referred to as a pad layer, may be formed of an oxide such as silicon oxide, and may be formed by performing a thermal oxidation on a surface layer of the substrate50. The second dielectric layer52B may be a mask layer, such as a hard mask layer, may be formed of a nitride such as silicon nitride, and may be formed by deposition such as by plasma-enhanced chemical vapor deposition (PECVD), atomic layer deposition (ALD), or the like. The third dielectric layer52C may be formed of silicon oxide (such as a tetraethylorthosilicate (TEOS) oxide), a nitrogen-free anti-reflective Coating (NFARC), silicon carbide, silicon oxynitride, or the like. Mandrels54are formed over the dielectric layers52, e.g., on the third dielectric layer52C. The mandrels54can be formed by depositing and patterning a mandrel layer. The mandrel layer is formed of a material that has a high etching selectivity from the etching of the underlying layer(s), e.g., the dielectric layers52. The mandrel layer may be formed of a material such as amorphous silicon, polysilicon, silicon nitride, silicon oxide, the like, or combinations thereof, and may be formed using a process such as a chemical vapor deposition (CVD), PECVD, or the like. The mandrel layer is then patterned using suitable photolithography and etching techniques to form the mandrels54. The mandrels54can be separated by a spacing distance D1in the range of about 10 nm to about 15 nm. Each of the mandrels54can have a width W1in the range of about 10 nm to about 15 nm. The mandrels54will be used to pattern spacers over the substrate50. The spacing distance D1and the width W1of the mandrels54determines the spacing distance between the subsequently patterned spacers. InFIG.3, a spacer layer56is formed over the mandrels54and the dielectric layers52. After formation, the spacer layer56extends along the top surfaces of the mandrels54, the sidewalls of the mandrels54, and the top surface of the third dielectric layer52C. The spacer layer56is formed of a material that has a high etching selectivity from the etching of the underlying layer(s), e.g., the dielectric layers52. The spacer layer56may be formed from silicon nitride, aluminum oxide, aluminum nitride, tantalum nitride, titanium nitride, titanium oxide, the like, or combinations thereof, and may be formed using a process such as ALD, CVD, or the like. The spacer layer56has a high degree of conformality, with the thickness T1of its vertical portions being equal to or slightly less than the thickness T2of its horizontal portions. For example, the thickness T1can be from about 80% to about 100% of the thickness T2. The thickness T1can be in the range of about 5 nm to about 20 nm and the thickness T2can be in the range of about 5 nm to about 24 nm. The spacer layer56will be patterned to form spacers over the substrate50. The thickness T1of the vertical portions of the spacer layer56determines the width of the subsequently patterned spacers. InFIG.4, the spacer layer56is patterned to form spacers58. A suitable etching process is performed to remove the horizontal portions of the spacer layer56. The etching process selectively etches the horizontal portions of the spacer layer56at a greater rate than the mandrels54and the vertical portions of the spacer layer56. For example, when the spacer layer56is formed of silicon nitride, the etching process can be an anisotropic dry etch performed with methane (CH4), chlorine (Cl2), nitrogen (N2), or the like. After the etching process, the spacers58comprise the remaining vertical portions of the spacer layer56. The mandrels54can optionally be removed with the horizontal portions of the spacer layer56, or can be removed in subsequent processing. In some embodiments, the mandrels54are removed after the spacers58are formed, and can be removed by a suitable etching processes that selectively etches the mandrels54at a greater rate than the spacers58. As shown inFIG.4, the spacers58have a width W2and are separated by a spacing distance D2. As noted above, the spacing distance D1and the width W1(seeFIG.2) of the mandrels54determines the spacing distance D2between the spacers58, and the thickness T1(seeFIG.3) of the vertical portions of the spacer layer56determines the width W2of the spacers58. Because selective etching process are used to form the spacers58, the thickness T1of the vertical portions of the spacer layer56decreases by a small amount when forming the spacers58. For example, the spacing distance D2between the spacers58can be up to about 300% large than the width W1of the mandrels54, and the width W2of the spacers58can be up to about 30% smaller than the thickness T1of the spacer layer56. The spacing distance D2between the spacers58can be in the range of about 10 nm to about 30 nm, and the width W2of the spacers58can be in the range of about 3.5 nm to about 20 nm. The spacers58will be used to pattern fins in the substrate50. The spacing distance D2and the width W2of the spacers58determines the spacing distance and the width of the subsequently patterned fins. InFIG.5, fins62are formed in the substrate50. The fins62are semiconductor strips. The fins62can be formed in the substrate50by patterning trenches60in the dielectric layers52using the spacers58as an etching mask, and then transferring the pattern of the trenches60from the dielectric layers52to the substrate50. The trenches60may be formed by any acceptable etch process, such as a reactive ion etch (RIE), neutral beam etch (NBE), the like, or a combination thereof. The etch may be anisotropic. The spacers58may be consumed by the etching process, or may be removed after the etching process. In some embodiments, a cleaning process, such as a wet etch, may be performed to remove any residual material of the spacers58. The dielectric layers52can optionally be removed with the spacers58, or can be removed in subsequent processing. As shown inFIG.5, the fins62have a width W3and are separated by a spacing distance D3. As noted above, the width W2(seeFIG.4) of the spacers58determines the width W3of the fins62, and the spacing distance D2(seeFIG.4) between the spacers58determines the spacing distance D3between the fins62. Although an anisotropic etching process is used to form the fins62, such a process may not be perfectly anisotropic. As such, the spacing distance D3between the fins62can be up to about 20% smaller than the spacing distance D2between the spacers58, and the width W3of the fins62can be up to about 150% larger than the width W2of the spacers58. The spacing distance D3between the fins62and the width W3of the fins62are both small, which allows the integration density of the resulting semiconductor devices to be improved. However, as the spacing distance D3between the fins62decreases, the uniformity of the spacing distance D3between the fins62degrades. When the uniformity of the spacing distance D3between the fins62is poor, a subsequently performed etching process (discussed further below) may need to be performed with a large amount of over-etching, which increases the risk of damage to the fins62and can decrease manufacturing yield. Thus, in accordance with some embodiments, the spacing distance D3between the fins62and the width W3of the fins62are selected to strike a balance between integration density and manufacturing yield. In some embodiments, the width W1of the mandrels54(seeFIG.2) is constrained to be in the range of about 10 nm to about 15 nm, which allows the spacing distance D3between the fins62to be in the range of about 8 nm to about 30 nm, and the width W3of the fins62to be in the range of about 3.5 nm to about 30 nm. Such a spacing distance D3between the fins62allows the spacing distance D3to have a relative standard deviation in the range of about 0.6% to about 0.95%. Forming the fins62with a width W3and a spacing distance D3in these ranges allows a subsequently performed etching process (discussed further below) to be performed with less over-etching, which decreases the risk of damage to the fins62and can increase manufacturing yield. Forming the fins62with a width W3and a spacing distance D3outside of these ranges may not allow a subsequently performed etching process (discussed further below) to be performed with less over-etching, which may increase the risk of damage to the fins62and may decrease manufacturing yield. InFIG.6, an insulation material64is formed over the substrate50and in the trenches60(SeeFIG.5) between neighboring fins62. The insulation material64may be an oxide, such as silicon oxide, a nitride, the like, or a combination thereof, and may be formed by a high density plasma chemical vapor deposition (HDP-CVD), a flowable CVD (FCVD) (e.g., a CVD-based material deposition in a remote plasma system and post curing to make it convert to another material, such as an oxide), the like, or a combination thereof. Other insulation materials formed by any acceptable process may be used. In the illustrated embodiment, the insulation material64is silicon oxide formed by a FCVD process. An anneal process may be performed once the insulation material is formed. In an embodiment, the insulation material64is formed such that excess insulation material64covers the fins62and the dielectric layers52(if present). Although the insulation material64is illustrated as a single layer, some embodiments may utilize multiple layers. For example, in some embodiments a liner may first be formed along a surface of the substrate50and sidewalls of the fins62. Thereafter, a fill material, such as those discussed above may be formed over the liner. InFIG.7, a removal process is applied to the insulation material64to remove excess insulation material64over the fins62. In some embodiments, a planarization process such as a chemical mechanical polish (CMP), an etch-back process, combinations thereof, or the like may be utilized. The planarization process exposes the fins62such that top surfaces of the fins62and the insulation material64are coplanar after the planarization process is complete. In embodiments in which the dielectric layers52(seeFIG.6) remain on the fins62, the planarization process may remove the dielectric layers52such that top surfaces of the fins62and the insulation material64are coplanar after the planarization process is complete. In another embodiment, the planarization process may expose the dielectric layers52such that top surfaces of the third dielectric layer52C and the insulation material64are coplanar after the planarization process is complete. InFIG.8, the insulation material64is recessed to form STI regions66. The insulation material64is recessed such that upper portions of fins62in the n-type region50N and in the p-type region50P protrude above and from between neighboring STI regions66. The exposed portions of the fins62include what will be channel regions of the resulting FinFETs. Further, the top surfaces of the STI regions66may have a flat surface as illustrated, a convex surface, a concave surface (such as dishing), or a combination thereof. The top surfaces of the STI regions66may be formed flat, convex, and/or concave by an appropriate etch. The STI regions66may be recessed using an acceptable etching process, such as one that is selective to the material of the insulation material64(e.g., selectively etches the material of the insulation material64at a greater rate than the material of the fins62). For example, an oxide removal using, for example, dilute hydrofluoric (dHF) acid may be used. The process described with respect toFIGS.2through8is just one example of how the fins62may be formed. In some embodiments, the fins may be formed by an epitaxial growth process. For example, a dielectric layer can be formed over a top surface of the substrate50, and trenches can be etched through the dielectric layer to expose the underlying substrate50. Homoepitaxial structures can be epitaxially grown in the trenches, and the dielectric layer can be recessed such that the homoepitaxial structures protrude from the dielectric layer to form fins. Additionally, in some embodiments, heteroepitaxial structures can be used for the fins62. For example, the fins62inFIG.7can be recessed, and a material different from the fins62may be epitaxially grown over the recessed fins62. In such embodiments, the fins62comprise the recessed material as well as the epitaxially grown material disposed over the recessed material. In an even further embodiment, a dielectric layer can be formed over a top surface of the substrate50, and trenches can be etched through the dielectric layer. Heteroepitaxial structures can then be epitaxially grown in the trenches using a material different from the substrate50, and the dielectric layer can be recessed such that the heteroepitaxial structures protrude from the dielectric layer to form the fins62. In some embodiments where homoepitaxial or heteroepitaxial structures are epitaxially grown, the epitaxially grown materials may be in situ doped during growth, which may obviate prior and subsequent implantations although in situ and implantation doping may be used together. Still further, it may be advantageous to epitaxially grow a material in n-type region50N (e.g., an NMOS region) different from the material in p-type region50P (e.g., a PMOS region). In various embodiments, upper portions of the fins62may be formed from silicon-germanium (SixGe1-x, where x can be in the range of 0 to 1), silicon carbide, pure or substantially pure germanium, a III-V compound semiconductor, a II-VI compound semiconductor, or the like. For example, the available materials for forming III-V compound semiconductor include, but are not limited to, indium arsenide, aluminum arsenide, gallium arsenide, indium phosphide, gallium nitride, indium gallium arsenide, indium aluminum arsenide, gallium antimonide, aluminum antimonide, aluminum phosphide, gallium phosphide, and the like. Further, appropriate wells may be formed in the fins62and/or the substrate50. In some embodiments, a p-type well may be formed in the n-type region50N, and a n-type well may be formed in the p-type region50P. In some embodiments, a p-type well or a n-type well are formed in both the n-type region50N and the p-type region50P. In the embodiments with different well types, the different implant steps for the n-type region50N and the p-type region50P may be achieved using a photoresist and/or other masks. For example, a photoresist may be formed over the fins62and the STI regions66in the n-type region50N. The photoresist is patterned to expose the p-type region50P of the substrate50. The photoresist can be formed by using a spin-on technique and can be patterned using acceptable photolithography techniques. Once the photoresist is patterned, an n-type impurity implant is performed in the p-type region50P, and the photoresist may act as a mask to substantially prevent n-type impurities from being implanted into the n-type region50N. The n-type impurities may be phosphorus, arsenic, antimony, or the like implanted in the region to a concentration of up to about 1018cm−3, such as in the range of about 1016cm−3to about 1018cm−3. After the implant, the photoresist is removed, such as by an acceptable ashing process. Following the implanting of the p-type region50P, a photoresist is formed over the fins62and the STI regions66in the p-type region50P. The photoresist is patterned to expose the n-type region50N of the substrate50. The photoresist can be formed by using a spin-on technique and can be patterned using acceptable photolithography techniques. Once the photoresist is patterned, a p-type impurity implant may be performed in the n-type region50N, and the photoresist may act as a mask to substantially prevent p-type impurities from being implanted into the p-type region50P. The p-type impurities may be boron, boron fluoride, indium, or the like implanted in the region to a concentration of up to about 1018cm−3, such as in the range of about 1016cm−3to about 1018cm−3. After the implant, the photoresist may be removed, such as by an acceptable ashing process. After the implants of the n-type region50N and the p-type region50P, an anneal may be performed to repair implant damage and to activate the p-type and/or n-type impurities that were implanted. In some embodiments, the grown materials of epitaxial fins may be in situ doped during growth, which may obviate the implantations, although in situ and implantation doping may be used together. InFIG.9, a dummy dielectric layer70is formed on the fins62. The dummy dielectric layer70may be, for example, silicon oxide, silicon nitride, a combination thereof, or the like, and may be deposited or thermally grown according to acceptable techniques. A dummy gate layer72is formed over the dummy dielectric layer70, and a mask layer74is formed over the dummy gate layer72. The dummy gate layer72may be deposited over the dummy dielectric layer70and then planarized, such as by a CMP. The mask layer74may be deposited over the dummy gate layer72. The dummy gate layer72may be a conductive or non-conductive material and may be selected from a group including amorphous silicon, polycrystalline-silicon (polysilicon), poly-crystalline silicon-germanium (poly-SiGe), metallic nitrides, metallic silicides, metallic oxides, and metals. The dummy gate layer72may be deposited by physical vapor deposition (PVD), CVD, sputter deposition, or other techniques for depositing the selected material. The dummy gate layer72may be made of other materials that have a high etching selectivity from the etching of isolation regions, e.g., the STI regions66and/or the dummy dielectric layer70. The mask layer74may include one or more layers of, for example, silicon nitride, silicon oxynitride, or the like. In this example, a single dummy gate layer72and a single mask layer74are formed across the n-type region50N and the p-type region50P. In the illustrated example, the dummy dielectric layer70covers the fins62and the STI regions66, and extends over the STI regions66and between the dummy gate layer72and the STI regions66. In another embodiment, the dummy dielectric layer70covers only the fins62. FIGS.10A through22Bare cross-sectional views of intermediate stages in the manufacturing of FinFETs, in accordance with some embodiments.FIGS.10A,11A,12A,13A,14A,15A,16A,17A,18A,19A,20A,21A, and22Aare illustrated along reference cross-section A-A illustrated inFIG.1, except two fins62are shown.FIGS.10B,11B,12B,13B,14B,15B,16B,17B,18B,19B,20B,21B, and22Bare illustrated along reference cross-section B-B illustrated inFIG.1.FIGS.12C and12Dare illustrated along reference cross-section C-C illustrated inFIG.1, except two fins62are shown.FIGS.10A through22Billustrate features in either of the n-type region50N and the p-type region50P. For example, the structures illustrated inFIGS.10A through22Bmay be applicable to both the n-type region50N and the p-type region50P. Differences (if any) in the structures of the n-type region50N and the p-type region50P are described in the text accompanying each figure. InFIGS.10A and10B, the mask layer74(seeFIG.9) is patterned using acceptable photolithography and etching techniques to form masks84. The pattern of the masks84then may be transferred to the dummy gate layer72to form dummy gates82. In some embodiments, the pattern of the masks84may also be transferred to the dummy dielectric layer70by an acceptable etching technique to form dummy dielectrics80. The dummy gates82cover respective channel regions68of the fins62. The pattern of the masks84may be used to physically separate each of the dummy gates82from adjacent dummy gates. The dummy gates82may also have a lengthwise direction substantially perpendicular to the lengthwise direction of the fins62. InFIGS.11A and11B, gate spacers94are formed on exposed surfaces of the dummy gates82, the masks84, and/or the fins62. The gate spacers94may be formed by conformally forming an insulating material and subsequently etching the insulating material. The insulating material of the gate spacers94may be silicon nitride, silicon carbonitride, silicon oxycarbonitride, a combination thereof, or the like, and may be formed by thermal oxidation, deposition, a combination thereof, or the like. In some embodiments, the gate spacers94are formed from a multi-layered insulating material, and include multiple layers. For example, the gate spacers94may include multiple layers of silicon carbonitride, may include multiple layers of silicon oxycarbonitride, or may include a layer of silicon oxide disposed between two layers of silicon nitride. The etching of the gate spacers94can be anisotropic. After etching, the gate spacers94can have straight sidewalls or curved sidewalls. Before or during the formation of the gate spacers94, implants for lightly doped source/drain (LDD) regions may be performed. In the embodiments with different device types, similar to the implants discussed above inFIG.8, a mask, such as a photoresist, may be formed over the n-type region50N, while exposing the p-type region50P, and appropriate type (e.g., p-type) impurities may be implanted into the exposed fins62in the p-type region50P. The mask may then be removed. Subsequently, a mask, such as a photoresist, may be formed over the p-type region50P while exposing the n-type region50N, and appropriate type impurities (e.g., n-type) may be implanted into the exposed fins62in the n-type region50N. The mask may then be removed. The n-type impurities may be the any of the n-type impurities previously discussed, and the p-type impurities may be the any of the p-type impurities previously discussed. The lightly doped source/drain regions may have a concentration of impurities in the range of about 1015cm−3to about 1019cm−3. An anneal may be used to repair implant damage and to activate the implanted impurities. It is noted that the above disclosure generally describes a process of forming spacers and LDD regions. Other processes and sequences may be used. For example, fewer or additional spacers may be utilized, different sequence of steps may be utilized, spacers may be formed and removed, and/or the like. Furthermore, the n-type and p-type devices may be formed using different structures and steps. InFIGS.12A and12Bepitaxial source/drain regions92are formed in the fins62. The epitaxial source/drain regions92are formed in the fins62such that each of the dummy gates82is disposed between respective neighboring pairs of the epitaxial source/drain regions92. In some embodiments the epitaxial source/drain regions92may extend into, and may also penetrate through, the fins62. In some embodiments, the gate spacers94are used to separate the epitaxial source/drain regions92from the dummy gates82by an appropriate lateral distance so that the epitaxial source/drain regions92do not short out subsequently formed gates of the resulting FinFETs. A material of the epitaxial source/drain regions92may be selected to exert stress in the channel regions68, thereby improving performance. The epitaxial source/drain regions92in the n-type region50N may be formed by masking the p-type region50P and etching source/drain regions of the fins62in the n-type region50N to form recesses in the fins62. Then, the epitaxial source/drain regions92in the n-type region50N are epitaxially grown in the recesses. The epitaxial source/drain regions92may include any acceptable material, such as appropriate for n-type FinFETs. For example, if the fins62are silicon, the epitaxial source/drain regions92in the n-type region50N may include materials exerting a tensile strain in the channel regions68, such as silicon, silicon carbide, phosphorous doped silicon carbide, silicon phosphide, or the like. The epitaxial source/drain regions92in the n-type region50N may have surfaces raised from respective surfaces of the fins62and may have facets. The epitaxial source/drain regions92in the p-type region50P may be formed by masking the n-type region50N and etching source/drain regions of the fins62in the p-type region50P to form recesses in the fins62. Then, the epitaxial source/drain regions92in the p-type region50P are epitaxially grown in the recesses. The epitaxial source/drain regions92may include any acceptable material, such as appropriate for p-type FinFETs. For example, if the fins62are silicon, the epitaxial source/drain regions92in the p-type region50P may comprise materials exerting a compressive strain in the channel regions68, such as silicon-germanium, boron doped silicon-germanium, germanium, germanium tin, or the like. The epitaxial source/drain regions92in the p-type region50P may have surfaces raised from respective surfaces of the fins62and may have facets. The epitaxial source/drain regions92and/or the fins62may be implanted with dopants to form source/drain regions, similar to the process previously discussed for forming lightly-doped source/drain regions, followed by an anneal. The source/drain regions may have an impurity concentration in the range of about 1019cm−3to about 1021cm−3. The n-type and/or p-type impurities for source/drain regions may be any of the impurities previously discussed. In some embodiments, the epitaxial source/drain regions92may be in situ doped during growth. As a result of the epitaxy processes used to form the epitaxial source/drain regions92in the n-type region50N and the p-type region50P, upper surfaces of the epitaxial source/drain regions have facets which expand laterally outward beyond sidewalls of the fins62. In some embodiments, these facets cause adjacent epitaxial source/drain regions92of a same FinFET to merge as illustrated byFIG.12C. In other embodiments, adjacent epitaxial source/drain regions92remain separated after the epitaxy process is completed as illustrated byFIG.12D. In the illustrated embodiments, gate spacers94are formed covering portions of the sidewalls of the fins62that extend above the STI regions66thereby blocking the epitaxial growth. In another embodiment, the spacer etch used to form the gate spacers94may be adjusted to remove the spacer material to allow the epitaxially grown regions to extend to the surface of the STI regions66. InFIGS.13A and13B, a first ILD layer98is deposited over the masks84(if present) or the dummy gates82, the epitaxial source/drain regions92, and the gate spacers94. The first ILD layer98may be formed of a dielectric material, and may be deposited by any suitable method, such as CVD, PECVD, or FCVD. Dielectric materials may include phospho-silicate glass (PSG), boro-silicate glass (BSG), boron-doped phospho-silicate glass (BPSG), undoped silicate glass (USG), or the like. Other insulation materials formed by any acceptable process may be used. In some embodiments, a contact etch stop layer (CESL)96is disposed between the first ILD layer98and the epitaxial source/drain regions92, the masks84(if present) or the dummy gates82, and the gate spacers94. The CESL96may be formed of a dielectric material, such as, silicon nitride, silicon oxide, silicon oxynitride, or the like, that has a high etching selectivity from the etching of the first ILD layer98. InFIGS.14A and14B, a planarization process, such as a CMP, may be performed to level the top surface of first ILD layer98with the top surfaces of the masks84(if present) or the dummy gates82. The planarization process may also remove the masks84on the dummy gates82, and portions of the gate spacers94along sidewalls of the masks84. The planarization process can also remove portions of the CESL96over the dummy gates82and the gate spacers94. After the planarization process, top surfaces of the dummy gates82, the gate spacers94, and the first ILD layer98are coplanar. Accordingly, the top surfaces of the dummy gates82are exposed through the first ILD layer98. In some embodiments, the masks84may remain, in which case the planarization process levels the top surface of the first ILD layer98with the top surfaces of of the masks84. InFIGS.15A and15B, the masks84(if present) and the dummy gates82are removed in one or more etching step(s), so that recesses100are formed. Portions of the dummy dielectrics80in the recesses100may also be removed. In some embodiments, only the dummy gates82are removed and the dummy dielectrics80remain and are exposed by the recesses100. In some embodiments, the dummy dielectrics80are removed from recesses100in a first region of a die (e.g., a core logic region) and remain in recesses100in a second region of the die (e.g., an input/output region). In some embodiments, the dummy gates82are removed by a wet etch process that selectively etches the dummy gates82at a greater rate than the first ILD layer98, the gate spacers94, or the dummy dielectrics80. For example, the dummy gates82can be removed by a wet etch performed with ammonium hydroxide (NH4OH) and deionized water. The recesses100expose and/or overly the channel regions68of one or more fins62. Each of the channel regions68is disposed between neighboring pairs of the epitaxial source/drain regions92. During the removal, the dummy dielectrics80may be used as etch stop layers when the dummy gates82are etched. The dummy dielectrics80may then be optionally removed after the removal of the dummy gates82. In some embodiments, the dummy dielectrics80are removed by a wet etch process that selectively etches the dummy dielectrics80at a greater rate than the first ILD layer98or the gate spacers94. For example, the dummy dielectrics80can be removed by a dry etch performed with fluorine. As noted above, the spacing distance D3between the fins62and the width W3of the fins62are both small, which allows the integration density of the resulting semiconductor devices to be improved. However, when the fins62have a small width W3, bending of the fins62can occur during formation of the recesses100, e.g., during removal of the dummy gates82or the dummy dielectrics80. For example, removing the dummy gates82can relax stresses in the material of the fins62, which can allow bending to occur. Likewise, when the dummy gates82and the dummy dielectrics80are removed by a wet etch, the viscosity of the wet etchants can exert lateral forces that bend the fins62. In some embodiments, adjacent ones of the fins62, such as the fins62of a same FinFET (e.g., a FinFET with merged epitaxial source/drain regions92, seeFIG.12C) can bend towards one another. As such, lower portions of the fins62(e.g., below the top surfaces of the STI regions66) can be separated by the original spacing distance D3, but upper portions of the fins62(e.g., above the top surfaces of the STI regions66) can have a spacing distance that continually decreases along a direction extending away from the substrate50. The spacing distance of the upper portions of the fins62can decrease from the original spacing distance D3to a reduced spacing distance D4. The reduced spacing distance D4can be up to about 60% less than the original spacing distance D3, such as in the range of about 3.2 nm to about 30 nm. After the fins62are bent, the sidewalls of the upper portions of the fins62form angles θ1with the sidewalls of the lower portions of the fins62. The angles θ1can be up to about 7 degrees. InFIGS.16A and16B, a gate dielectric layer102is formed. The gate dielectric layer102includes one or more layers deposited in the recesses100, such as on the top surfaces and the sidewalls of the fins62and on sidewalls of the gate spacers94. The gate dielectric layer102may also be formed on the top surface of the first ILD layer98. In some embodiments, the gate dielectric layer102comprises one or more dielectric layers, such as one or more layers of silicon oxide, silicon nitride, metal oxide, metal silicate, or the like. For example, in some embodiments, the gate dielectric layer102include an interfacial layer of silicon oxide formed by thermal or chemical oxidation and an overlying high-k dielectric material, such as a metal oxide or a silicate of hafnium, aluminum, zirconium, lanthanum, manganese, barium, titanium, lead, and combinations thereof. The gate dielectric layer102may include a dielectric layer having a k value greater than about 7.0. The formation methods of the gate dielectric layer102may include Molecular-Beam Deposition (MBD), ALD, PECVD, and the like. In embodiments where portions of the dummy dielectrics80remains in the recesses100, the gate dielectric layer102include a material of the dummy dielectrics80(e.g., silicon oxide). The gate dielectric layer102can include defects104(each of which is illustrated with an “X”) after deposition. Some of the defects104are interfacial defects located at the interface of the gate dielectric layer102and the fins62. Some of the defects104are oxygen vacancy defects in the material(s) of the gate dielectric layer102, such as in the high-k layer when the gate dielectric layer102includes a high-k layer of a metal oxide, or in the interfacial layer when the gate dielectric layer102includes an interfacial layer of silicon oxide. Oxygen vacancy defects can be caused by, e.g., insufficient oxidation during formation of the material(s) of the gate dielectric layer102. The defects104will be repaired in a subsequent annealing process (discussed further below). InFIGS.17A and17B, one or more sacrificial layers are formed on the gate dielectric layer102. As discussed further below, the sacrificial layers will be used to protect the gate dielectric layer102during an annealing process used to repair the defects104(seeFIGS.16A and16B). In some embodiments, the sacrificial layers include a first sacrificial layer106A and a second sacrificial layer106B. The first sacrificial layer106A is in direct physical contact with the gate dielectric layer102and the second sacrificial layer106B is in direct physical contact with the first sacrificial layer106A. The first sacrificial layer106A is formed of a material that has a high etching selectivity from the etching of the gate dielectric layer102, and the second sacrificial layer106B is formed of a material that has a high etching selectivity from the etching of the first sacrificial layer106A. The sacrificial layer106A may be formed of TiN, silicon-doped TiN (TiSiN), TaN, or the like, and may be formed by a deposition process such as ALD or CVD. The sacrificial layer106B may be formed of amorphous silicon, polysilicon, silicon nitride, the like, or combinations thereof, and may be formed by a deposition process such as CVD or ALD. In some embodiments, the sacrificial layers106A,106B are formed by different deposition processes. As noted above, the initial spacing distance D3(seeFIG.15A) between the fins62is small, and bending of the fins62can occur when the recesses100are formed, which further decreases the spacing distance D4(seeFIG.15A). The risk of pinch-off during deposition of the sacrificial layers106A,106B is thus high. Specifically, the risk of pinch-off is high when CVD is used to deposit the sacrificial layers106A,106B. As discussed further below, the sacrificial layer106B is deposited with a CVD process that helps avoid or reduce the risk of pinch-off caused by the small spacing distance of the fins62. In some embodiments, the sacrificial layer106A is a layer of TiSiN deposited with ALD. Depositing the sacrificial layer106A with ALD allows it to have a high degree of conformality, with the thickness T3of its vertical portions being similar to the thickness T4of its horizontal portions. Depositing the sacrificial layer106A with ALD also allows it to have a small thickness. The thickness T3and the thickness T4can each be in the range of about 0.5 nm to about 2.5 nm. In some embodiments, the sacrificial layer106B is a layer of amorphous silicon deposited with a self-inhibiting CVD process, which has a slow deposition rate. The self-inhibiting CVD process is performed by placing the substrate50in a deposition chamber, dispensing a self-limiting source precursor into the deposition chamber, and then dispensing a self-reacting source precursor into the deposition chamber. The recesses100(e.g., the surfaces of the gate dielectric layer102) are exposed to the self-limiting source precursor and then the self-reacting source precursor. The self-limiting source precursor and the self-reacting source precursor both react to form the material (e.g., silicon) of the sacrificial layer106B. The self-reacting source precursor can react with itself in a CVD process to form the material (e.g., silicon) of the sacrificial layer106B. Acceptable self-reacting source precursors for silicon include binary silicon-hydrogen compound silanes such as silane (SiH4), disilane (Si2H6), and the like. The self-limiting source precursor can be used to deposit a highly conformal layer of the material (e.g., silicon) of the sacrificial layer106B, and can react with the self-reacting source precursor in a CVD process, but cannot react with itself in the CVD process. Acceptable self-limiting source precursors for silicon include aminosilanes, such as dimethylaminosilane (SiH3[N(CH3)2], DMAS), ethylmethylaminosilane (SiH3[N(CH3C2H5)], EMAS), diethylaminosilane (SiH3[N(C2H5)2], DEAS), ethylisopropylaminosilane (SiH3[N(C2H5C3H7)], EIPAS), diisopropylaminosilane (SiH3[N(C3H7)2], DIPAS), and the like. A first pulse of the self-inhibiting CVD process is performed by dispensing the self-limiting source precursor into the deposition chamber. The self-limiting source precursor can be dispensed at a flow rate the range of about 50 sccm to about 1000 sccm and for a duration in the range of about 20 seconds to about 180 seconds. No self-reacting source precursor is dispensed during the dispensing of the self-limiting source precursor. The self-limiting source precursor is then purged from the deposition chamber. The self-limiting source precursor (e.g., an aminosilane) includes SiH3groups, which readily react with dangling bonds at the surface of the sacrificial layer106A to form a conformal initial layer of amorphous silicon during the first pulse. The SiH3groups in an aminosilane are bonded to nitrogen atoms. Although silanes also include SiH3groups, SiH3groups in silanes are bonded to other hydrogen atoms. SiH3groups can break away from nitrogen atoms (e.g., in an aminosilane) more easily than from hydrogen atoms (e.g., in a silane). Thus, dispensing the self-limiting source precursor in the first pulse may allow more SiH3groups to react with dangling bonds at the surface of the sacrificial layer106A, increasing the conformality of the initial layer. Because the self-limiting source precursor cannot react with itself, the initial layer can be very thin, such as one monolayer thick. A second pulse of the self-inhibiting CVD process is then performed by dispensing the self-reacting source precursor into the deposition chamber. The self-reacting source precursor can be dispensed at a flow rate the range of about 20 sccm to about 1000 sccm and for a duration in the range of about 10 minutes to about 50 minutes. The duration of the second pulse can be longer than the duration of the first pulse, such as from about 3.3% to about 150% longer than the first pulse. No self-limiting source precursor is dispensed during the dispensing of the self-reacting source precursor. The self-reacting source precursor (e.g., a silane) also includes SiH3groups, which readily bond to the initial layer of amorphous silicon during the second pulse. Accordingly, a main layer of amorphous silicon is formed along the initial layer of amorphous silicon, creating an amorphous silicon layer with a high degree of conformality. The self-reacting source precursor repeatedly reacts with previously formed SiH3groups. The sacrificial layer106B can thus be formed by dispensed the self-reacting source precursor until the sacrificial layer106B is a desired thickness. During the self-inhibiting CVD process, the deposition chamber can be maintained at a temperature in the range of about 300° C. to about 500° C. and at a pressure in the range of about 0.1 Torr to about 20 Torr. The deposition rate of the self-inhibiting CVD process can be controlled by controlling the temperature of the chamber during the first pulse and the second pulse. Specifically, performing deposition at a low temperature allows the self-inhibiting CVD process to have a low deposition rate. The deposition rate of the self-inhibiting CVD process can be in the range of about 0.5 Å/minute to about 2 Å/minute. Depositing the sacrificial layer106B at a slow deposition rate also allows it to have a high degree of conformality, with the thickness T5of its vertical portions being equal to or slightly less than the thickness T6of its horizontal portions. For example, the thickness T5can be up to about 20% less than the thickness T6. Forming the sacrificial layer106B with a high degree of conformality helps avoid pinch-off of the sacrificial layer106B at the apexes of the fins62during deposition. By avoiding pinch-off, a subsequently performed etching process for removing the sacrificial layer106B can be performed with less over-etching, which decreases the risk of damage to the fins62or the gate dielectric layer102. Performing the self-inhibiting CVD process at a temperature in the range described above allows the deposition rate to be sufficiently slow to avoid pinch-off. Performing the self-inhibiting CVD process at a temperature that is outside of the range described above may not allow the deposition rate to be sufficiently slow to avoid pinch-off. The thickness of the sacrificial layer106B can be controlled by controlling the deposition rate and the duration of the self-inhibiting CVD process. When the deposition rate is controlled to be in the range described above and the second pulse is performed for a duration in the range described above, the sacrificial layer106B can have a small thickness. The thickness T5can be in the range of about 12 nm to about 35 nm and the thickness T6can be in the range of about 15 nm to about 35 nm. Forming the sacrificial layer106B with a small thickness also helps avoid pinch-off at the apexes of the fins62during deposition. By avoiding pinch-off, a subsequently performed etching process for removing the sacrificial layer106B can be performed with less over-etching, which decreases the risk of damage to the fins62or the gate dielectric layer102. Performing the second pulse for a duration in the range described above allows the thickness of the sacrificial layer106B to be sufficiently small to avoid pinch-off. Performing the second pulse for a duration outside of the range described above may not allow the thickness of the sacrificial layer106B to be sufficiently small to avoid pinch-off. The thickness of the sacrificial layer106B is greater than the thickness of the sacrificial layer106A. Further, as noted above, the sacrificial layers106A,106B are formed of different materials. Notably, the material of the sacrificial layer106B (e.g., amorphous silicon) acts as a better oxygen barrier than the material of the sacrificial layer106A (e.g., TiSiN). The sacrificial layer106B can thus act as an additional protection layer during subsequent processing, as compared to only forming the sacrificial layer106A. After depositing the sacrificial layer106B, the gate dielectric layer102is thermally treated to repair the defects104. The thermal treatment can include annealing the gate dielectric layer102. The anneal can be performed at a temperature in the range of about 600° C. to about 1100° C. and for a duration of up to about 1 minute. The anneal can be performed in an atmosphere of oxygen, nitrogen, argon, or the like, or can be performed in a vacuum. The thermal treatment may passivate oxygen vacancies in the gate dielectric layer102(such as with trace oxygen from the sacrificial layer106A) and rearrange oxygen at the interface of the gate dielectric layer102and each of the fins62, thus repairing the defects104. Repairing the defects104can help improve the performance and reliability of the resulting FinFETs, such as by reducing charge build-up and scattering effects that can decrease current mobility in the channel regions68. During the thermal treatment, the gate dielectric layer102is covered by the sacrificial layers106A,106B. The sacrificial layers106A,106B helps prevent undesirable modification of the material(s) of the gate dielectric layer102during the thermal treatment, such as undesirable thermal oxidation that may occur if the gate dielectric layer102were exposed during the thermal treatment. Because the sacrificial layer106B is thicker than the sacrificial layer106A and is formed of a material that acts as a better oxygen barrier than the material of the sacrificial layer106A, undesirable modification of the material(s) of the gate dielectric layer102may be further reduced as compared to only forming the sacrificial layer106A. As such, the material properties (e.g., relative permittivity) of the gate dielectric layer102can be similar before and after the thermal treatment. InFIGS.18A and18B, the sacrificial layers106A,106B are removed to expose the gate dielectric layer102. The sacrificial layers106A,106B may be removed by acceptable etch process(es) that selectively etch the sacrificial layers106A,106B at a greater rate than the gate dielectric layer102. The etch process(es) can include an anisotropic etch followed by an isotropic etch. Because the sacrificial layers106A,106B both have a high degree of conformality and a small thickness, the etch process(es) can be performed for a short duration and with a small amount of over-etching. For example, the sacrificial layer106B (e.g., amorphous silicon) can be removed by a dry etch performed with fluorine for a duration in the range of about 10 seconds to about 120 seconds, and the sacrificial layer106A (e.g., TiSiN) can then be removed by a wet etch performed with ammonium hydroxide (NH4OH) for a duration in the range of about 30 seconds to about 180 seconds. Reducing the amount of over-etching when removing the sacrificial layers106A,106B can avoid or reduce damage to the gate dielectric layer102and/or the fins62. Performing the etch process for a duration in the range described above allows damage to the gate dielectric layer102and/or the fins62from over-etching to be avoided. Performing the etch process for a duration outside of the range described above may not allow damage to the gate dielectric layer102and/or the fins62from over-etching to be avoided. InFIGS.19A and19B, a gate electrode layer108is formed on the gate dielectric layer102. The gate electrode layer108is deposited on the gate dielectric layer102and fills the remaining portions of the recesses100. The gate electrode layer108may include a metal-containing material such as titanium nitride, titanium oxide, tantalum nitride, tantalum carbide, cobalt, ruthenium, aluminum, tungsten, combinations thereof, or multi-layers thereof. For example, although a single gate electrode layer108is illustrated, the gate electrode layer108may comprise any number of liner layers, any number of work function tuning layers, and a fill material. InFIGS.20A and20B, a planarization process, such as a CMP, is performed to remove the excess portions of the material(s) of the gate dielectric layer102and the material(s) of the gate electrode layer108, which excess portions are over the top surfaces of the first ILD layer98and the gate spacers94. The remaining portions of the material(s) of the gate dielectric layer102in the recesses100form gate dielectrics112for replacement gates of the resulting FinFETs. The remaining portions of the material(s) of the gate electrode layer108in the recesses100form gate electrodes114for the replacement gates of the resulting FinFETs. The gate dielectrics112and the gate electrodes114may be collectively referred to as gate structures110or “gate stacks.” The gate structures110extend along sidewalls of the channel regions68of the fins62. The formation of the gate dielectrics112in the n-type region50N and the p-type region50P may occur simultaneously such that the gate dielectrics112in each region are formed from the same materials, and the formation of the gate electrodes114may occur simultaneously such that the gate electrodes114in each region are formed from the same materials. In some embodiments, the gate dielectrics112in each region may be formed by distinct processes, such that the gate dielectrics112may be different materials, and/or the gate electrodes114in each region may be formed by distinct processes, such that the gate electrodes114may be different materials. Various masking steps may be used to mask and expose appropriate regions when using distinct processes. For example, the gate dielectrics112and the gate electrodes114in the n-type region50N may be formed by masking the p-type region50P and performing the process described with respect toFIGS.16A through20Bin the n-type region50N. Likewise, the gate dielectrics112and the gate electrodes114in the p-type region50P may be formed by masking the n-type region50N and performing the process described with respect toFIGS.16A through20Bin the p-type region50P. In other words, the process described with respect toFIGS.16A through20Bcan be performed multiple times, e.g., once in the n-type region50N and once in the p-type region50P. InFIGS.21A and21B, a second ILD layer118is deposited over the first ILD layer98. In some embodiments, the second ILD layer118is a flowable film formed by a flowable CVD method. In some embodiments, the second ILD layer118is formed of a dielectric material such as PSG, BSG, BPSG, USG, or the like, and may be deposited by any suitable method, such as CVD and PECVD. In some embodiments, an etch stop layer is formed between the first ILD layer98and the second ILD layer118. In some embodiments, gate masks116are formed over respective gate stacks (including a gate dielectric112and a corresponding gate electrode114). The gate masks116are disposed between opposing pairs of the gate spacers94. In some embodiments, forming the gate masks116includes recessing the gate dielectrics112and the gate electrodes114so that recesses are formed between opposing pairs of the gate spacers94. One or more layers of dielectric material, such as silicon nitride, silicon oxynitride, or the like, are filled in the recesses, and a planarization process is performed to remove excess portions of the dielectric material extending over the first ILD layer98. The gate masks116comprise the remaining portions of the dielectric material in the recesses. Subsequently formed gate contacts penetrate through the second ILD layer118and the gate masks116to contact the top surfaces of the recessed gate electrodes114. InFIGS.22A and22B, source/drain contacts122and gate contacts124are formed, respectively, to the epitaxial source/drain regions92and the gate electrodes114. Openings for the source/drain contacts122are formed through the second ILD layer118, the first ILD layer98, and the CESL96. Openings for the gate contacts124are formed through the second ILD layer118and the gate masks116. The openings may be formed using acceptable photolithography and etching techniques. A liner, such as a diffusion barrier layer, an adhesion layer, or the like, and a conductive material are formed in the openings. The liner may include titanium, titanium nitride, tantalum, tantalum nitride, or the like. The conductive material may be copper, a copper alloy, silver, gold, tungsten, cobalt, aluminum, nickel, or the like. A planarization process, such as a CMP, may be performed to remove excess material from a surface of the second ILD layer118. The remaining liner and conductive material form the source/drain contacts122and the gate contacts124in the openings. An anneal process may be performed to form a silicide at the interface between the epitaxial source/drain regions92and the source/drain contacts122. The source/drain contacts122are physically and electrically coupled to the epitaxial source/drain regions92, and the gate contacts124are physically and electrically coupled to the gate electrodes114. The source/drain contacts122and the gate contacts124may be formed in different processes, or may be formed in the same process. Although shown as being formed in the same cross-sections, it should be appreciated that each of the source/drain contacts122and the gate contacts124may be formed in different cross-sections, which may avoid shorting of the contacts. Embodiments may achieve advantages. Forming the fins62(seeFIG.5) with the spacing distance D3and the width W3discussed above allows for a good balance between integration density and manufacturing yield of the FinFETs. Protecting the gate dielectric layer102with the sacrificial layers106A,106B (seeFIGS.17A and17B) while annealing the gate dielectric layer102allows defects104in the resulting gate stack to be cured without undesirable modification of the material(s) of the gate dielectric layer102. Depositing the sacrificial layer106B with a self-inhibiting CVD process performed with a self-limiting source precursor, such as an aminosilane, allows the sacrificial layer106B to deposited with a high degree of conformality. Over-etching during removal of the sacrificial layers106A,106B may thus be avoided, which can be particularly advantageous when the fins62are close together, such as when the fins62are formed with a small initial spacing distance D3, or when bending of the fins62occurs during processing. In an embodiment, a method includes: depositing a gate dielectric layer on a first fin and a second fin, the first fin and the second fin extending away from a substrate in a first direction, a distance between the first fin and the second fin decreasing along the first direction; depositing a sacrificial layer on the gate dielectric layer by exposing the gate dielectric layer to a self-limiting source precursor and a self-reacting source precursor, the self-limiting source precursor reacting to form an initial layer of a material of the sacrificial layer, the self-reacting source precursor reacting to form a main layer of the material of the sacrificial layer; annealing the gate dielectric layer while the sacrificial layer covers the gate dielectric layer; after annealing the gate dielectric layer, removing the sacrificial layer; and after removing the sacrificial layer, forming a gate electrode layer on the gate dielectric layer. In some embodiments of the method, the self-reacting source precursor is a silane and the self-limiting source precursor is an aminosilane. In some embodiments of the method, the silane is a binary silicon-hydrogen compound silane, and the aminosilane is dimethylaminosilane, ethylmethylaminosilane, diethylaminosilane, ethylisopropylaminosilane, or diisopropylaminosilane. In some embodiments of the method, exposing the gate dielectric layer to the self-limiting source precursor and the self-reacting source precursor includes: placing the substrate in a deposition chamber; dispensing the self-limiting source precursor into the deposition chamber for a first duration; purging the self-limiting source precursor from the deposition chamber; and dispensing the self-reacting source precursor into the deposition chamber for a second duration, the second duration being greater than the first duration. In some embodiments of the method, the first duration is in a range of 20 seconds to 180 seconds, and the second duration is in a range of 10 minutes to 50 minutes. In some embodiments of the method, the gate dielectric layer is exposed to the self-reacting source precursor and the self-limiting source precursor at a temperature in a range of 300° C. to 500° C. In some embodiments of the method, the sacrificial layer is a silicon layer, the silicon layer having a first thickness along top surfaces of the first fin and the second fin, the silicon layer having a second thickness along sidewalls of the first fin and the second fin, the second thickness being up to 20% less than the first thickness. In some embodiments of the method, the first thickness is in a range of 12 nm to 35 nm and the second thickness is in a range of 15 nm to 35 nm. In some embodiments of the method, upper portions of the first fin and the second fin are separated by a first distance and lower portions of the first fin and the second fin are separated by a second distance, the first distance being in a range of 3.2 nm to 30 nm, the second distance being in a range of 8 nm to 30 nm. In some embodiments, the method further includes: growing an epitaxial source/drain region in the first fin and the second fin, the gate dielectric layer and the gate electrode layer disposed adjacent the epitaxial source/drain region. In some embodiments of the method, removing the sacrificial layer includes etching the sacrificial layer with a dry etch performed with fluorine for a duration in a range of 10 seconds to 120 seconds. In an embodiment, a method includes: forming a first fin and a second fin extending from a substrate; forming a dummy dielectric on upper portions of the first fin and the second fin; growing an epitaxial source/drain region in the first fin and the second fin, the epitaxial source/drain region adjacent the dummy dielectric; removing the dummy dielectric from the first fin and the second fin, upper portions of the first fin and the second fin bending towards one another during the removing the dummy dielectric; depositing a gate dielectric layer on the upper portions of the first fin and the second fin; depositing a sacrificial layer on the gate dielectric layer, horizontal portions of the sacrificial layer having a first thickness, vertical portions of the sacrificial layer having a second thickness, the second thickness being up to 20% less than the first thickness; after depositing the sacrificial layer, annealing the gate dielectric layer; after annealing the gate dielectric layer, removing the sacrificial layer; and after removing the sacrificial layer, forming a gate electrode layer on the gate dielectric layer. In some embodiments of the method, forming the first fin and the second fin includes: forming a mandrel over the substrate, the mandrel having a first width in a range of 10 nm to 15 nm; forming a first spacer and a second spacer adjacent the mandrel; removing the mandrel; and etching the first fin and the second fin in the substrate using the first spacer and the second spacer as an etching mask. In some embodiments of the method, depositing the sacrificial layer includes: performing a chemical vapor deposition process using a first precursor and a second precursor, the first precursor being a self-limiting source precursor for a material of the sacrificial layer, the second precursor being a self-reacting source precursor for the material of the sacrificial layer, where the self-reacting source precursor reacts with itself in the chemical vapor deposition process to form the material of the sacrificial layer, where the self-limiting source precursor does not react with itself in the chemical vapor deposition process. In some embodiments of the method, the first precursor is an aminosilane and the second precursor is a silane, the first precursor dispensed in a first pulse for a first duration during the chemical vapor deposition process, the second precursor dispensed in a second pulse for a second duration during the chemical vapor deposition process, the second duration being greater than the first duration. In some embodiments, the method further includes: forming an isolation region around lower portions of the first fin and the second fin, the upper portions of the first fin and the second fin disposed above the isolation region, where after removing the dummy dielectric, sidewalls of the upper portions of the first fin and the second fin form angles with sidewalls of the lower portions of the first fin and the second fin, the angles being up to 7 degrees. In some embodiments, the method further includes: forming an isolation region around lower portions of the first fin and the second fin, the upper portions of the first fin and the second fin disposed above the isolation region, where after removing the dummy dielectric, the upper portions of the first fin and the second fin are separated by a first distance and the lower portions of the first fin and the second fin are separated by a second distance, the first distance being up to 60% less than the second distance. In some embodiments of the method, annealing the gate dielectric layer repairs defects in the gate dielectric layer. In an embodiment, a method includes: forming a dummy dielectric on a first fin and a second fin, the first fin and the second fin extending away from a substrate in a first direction; growing an epitaxial source/drain region in the first fin and the second fin, the epitaxial source/drain region adjacent the dummy dielectric; removing the dummy dielectric to form a recess exposing the first fin and the second fin, a distance between the first fin and the second fin being constant along the first direction before the removing, the distance between the first fin and the second fin decreasing along the first direction after the removing; depositing a gate dielectric layer in the recess; depositing a sacrificial layer on the gate dielectric layer by exposing the gate dielectric layer to a self-limiting source precursor and a self-reacting source precursor, the self-limiting source precursor reacting to form an initial layer of a material of the sacrificial layer, the self-reacting source precursor reacting to form a main layer of the material of the sacrificial layer, where the self-reacting source precursor reacts with itself, where the self-limiting source precursor does not react with itself; repairing defects in the gate dielectric layer while the sacrificial layer covers the gate dielectric layer; removing the sacrificial layer from the gate dielectric layer; and forming a gate electrode layer on the gate dielectric layer. In some embodiments of the method, after removing the dummy dielectric, sidewalls of upper portions of the first fin and the second fin form angles with sidewalls of lower portions of the first fin and the second fin, the angles being up to 7 degrees. The foregoing outlines features of several embodiments so that those skilled in the art may better understand the aspects of the present disclosure. Those skilled in the art should appreciate that they may readily use the present disclosure as a basis for designing or modifying other processes and structures for carrying out the same purposes and/or achieving the same advantages of the embodiments introduced herein. Those skilled in the art should also realize that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and that they may make various changes, substitutions, and alterations herein without departing from the spirit and scope of the present disclosure. | 70,839 |
11862469 | DETAILED DESCRIPTION The following disclosure provides many different embodiments, or examples, for implementing different features of the provided subject matter. Specific examples of components and arrangements are described below to simplify the present disclosure. These are, of course, merely examples and are not intended to be limiting. For example, the formation of a second feature over or on a first feature in the description that follows may include embodiments in which the second and first features are formed in direct contact, and may also include embodiments in which additional features may be formed between the second and first features, such that the second and first features may not be in direct contact. In addition, the present disclosure may repeat reference numerals and/or letters in the various examples. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed. Further, spatially relative terms, such as “beneath”, “below”, “lower”, “on”, “above”, “upper” and the like, may be used herein for ease of description to describe one element or feature's relationship to another element(s) or feature(s) as illustrated in the FIGS. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the FIGS. The apparatus may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein may likewise be interpreted accordingly. Other features and processes may also be included. For example, testing structures may be included to aid in the verification testing of the 3D packaging or 3DIC devices. The testing structures may include, for example, test pads formed in a redistribution layer or on a substrate that allows the testing of the 3D packaging or 3DIC, the use of probes and/or probe cards, and the like. The verification testing may be performed on intermediate structures as well as the final structure. Additionally, the structures and methods disclosed herein may be used in conjunction with testing methodologies that incorporate intermediate verification of known good dies to increase the yield and decrease costs. FIG.1AtoFIG.1Fare schematic cross-sectional views illustrating a method of manufacturing a package structure according to a first embodiment of the disclosure. Referring toFIG.1A, a carrier10is provided. The carrier10may be a glass carrier, a ceramic carrier, or the like. A de-bonding layer11is formed on the carrier10by, for example, a spin coating method. In some embodiments, the de-bonding layer11may be formed of an adhesive such as an Ultra-Violet (UV) glue, a Light-to-Heat Conversion (LTHC) glue, or the like, or other types of adhesives. The de-bonding layer11is decomposable under the heat of light to thereby release the carrier10from the overlying structures that will be formed in subsequent steps. A redistribution layer (RDL) structure12is formed over the carrier10and the de-bonding layer11. In some embodiments, the RDL structure12includes a plurality of polymer layers PM1, PM2, PM3 and PM4 and a plurality of redistribution layers RDL1, RDL2, RDL3 and RDL4 stacked alternately. The number of the polymer layers or the redistribution layers is not limited by the disclosure. In some embodiments, the RDL structure12comprises at least three RDL layers. In some embodiments, the RDL structure12is free of substrate. In some embodiments, the redistribution layer RDL1 penetrates through the polymer layer PM1, and the bottom surface of the redistribution layer RDL1 and the bottom surface of the polymer layer PM1 are substantially level with each other, and are in contact with the de-bonding layer11. The redistribution layer RDL2 penetrates through the polymer layer PM2 and is electrically connected to the redistribution layer RDL1. The redistribution layer RDL3 penetrates through the polymer layer PM3 and is electrically connected to the redistribution layer RDL2. The redistribution layer RDL4 penetrates through the polymer layer PM4 and is electrically connected to the redistribution layer RDL3. In some embodiments, the redistribution layer RDL4 is also referred as pads, and is located in a region for collecting to a die in the subsequently processes. In some embodiments, the redistribution layer RDL4 protrudes from the top surface of the polymer layer PM4 and exposed, that is, the top surface of the redistribution layer RDL4 is higher than the top surface of the polymer layer PM4, but the disclosure is not limited thereto. In some other embodiments, the top surface of the redistribution layer may be substantially level with the top surface of the polymer layer PM4. In some embodiments, the redistribution layers RDL1, RDL2, RDL3 and RDL4 respectively includes a plurality of vias V and a plurality of traces T connected to each other. The vias V penetrates through the polymer layers PM1, PM2, PM3 and PM4 to connect the traces T of the redistribution layers RDL1, RDL1, RDL3 and RDL4, and the traces T are respectively located on the polymer layers PM1, PM2, PM3 and PM4, and are respectively extending on the top surface of the polymer layers PM1, PM2, PM3 and PM4. Referring to the enlarged view of the via V and the trace T inFIG.1A, in some embodiments, the cross-section shape of the via V is inverted trapezoid, but the disclosure is not limited thereto. In some embodiments, the base angle θ of the via V is an obtuse angle, and the width W20of top surface of the via V is larger than the width W10of the bottom surface of the via V. In some embodiments, the top surface of the via V has a larger area than the bottom surface of the via V. In some other embodiments, the cross-section shape of the via V may be square or rectangle, and the base angle θ of the via V is a right angle. In some embodiments, the polymer layers PM1, PM2, PM3 and PM4 respectively includes a photo-sensitive material such as polybenzoxazole (PBO), polyimide (PI), benzocyclobutene (BCB), a combination thereof or the like. The forming methods of the polymer layers PM1, PM2, PM3 and PM4 include suitable fabrication techniques such as spin coating, chemical vapor deposition (CVD), plasma-enhanced chemical vapor deposition (PECVD), lamination or the like. In some embodiments, the redistribution layers RDL1, RDL2, RDL3 and RDL4 respectively includes conductive materials. The conductive material includes metal such as copper, nickel, titanium, a combination thereof or the like, and is formed by an electroplating process. In some embodiments, the redistribution layers RDL1, RDL2, RDL3 and RDL4 respectively includes a seed layer (not shown) and a metal layer formed thereon (not shown). The seed layer may be a metal seed layer such as a copper seed layer. In some embodiments, the seed layer includes a first metal layer such as a titanium layer and a second metal layer such as a copper layer over the first metal layer. The metal layer may be copper or other suitable metals. Referring toFIG.1B, a die17is placed over and electrically connected to the RDL structure12. Specifically, the die17is connected to the redistribution layer RDL4 of the RDL structure12though a plurality of conductive bumps18. The die17may be an application-specific integrated circuit (ASIC) chip, an analog chip, a sensor chip, a wireless and radio frequency chip, a voltage regulator chip or a memory chips. The number of the die17shown inFIG.1Bis merely for illustration, and the disclosure is not limited thereto. In some embodiments, two or more dies17may be mounted onto the RDL structure12, and the two or more dies17may be the same types of dies or the different types of dies. In some embodiments, the die17includes a substrate13, a plurality of pads14, a passivation layer15and a plurality of connectors16. The pads14may be a part of an interconnection structure (not shown) and electrically connected to the integrated circuit devices (not shown) of the die17. The passivation layer15covers a portion of the pads14. The passivation layer15includes an insulating material such as silicon oxide, silicon nitride, polymer, or a combination thereof. A portion of the pads14is exposed by the passivation layer15and serves as an external connection of the die17. The connectors16are contacted with and electrically connected to the pads14not covered by the passivation layer15. The connector16includes solder bumps, gold bumps, copper bumps, copper posts, copper pillars, or the like. The die17has a first surface17a(that is, the top surface) and a second surface17b(that is, the bottom surface) opposite to each other. In some embodiments, the first surface17ais a surface of the substrate13away from the connectors16. The second surface17bis an active surface17bof the die17facing the top surface of the RDL structure12, in some embodiments, the second surface17bincludes a portion of the surface of the connectors16and a portion of the surface of the passivation layer15. That is to say, the RDL structure12is located at a front-side (a side close to the connectors16) of the die17. In some embodiments, the top surface of the via V of the RDL structure12is relatively closer to the second surface17bof the die17than the bottom surface of the via V, and the bottom surface of the via V of the RDL structure12is relatively farther away from the second surface17bof the die17than the top surface of the via V. In other word, in some embodiments, the top surface of the via V with a larger area is relatively closer to the active surface17bof the die17than the bottom surface of the via V. Still referring toFIG.1B, the conductive bumps18are located between the connectors16of the die17and the redistribution layer RDL4 of the RDL structure12. In some embodiments, the conductive bumps18further covers a portion of sidewalls of the connector16and a portion of sidewalls of the RDL4. In some embodiments, the conductive bumps18are solder bumps, silver balls, copper balls, or any other suitable metallic balls. In some embodiments, a soldering flux (not shown) may be applied onto the conductive bumps18for better adhesion. In some embodiments, after the die17is connected to the RDL structure12, an underfill layer19is formed to fill the space between the die17and the RDL structure12, so as to cover the active surface17bof the die17and a portion of the top surface of the polymer layer PM4, and surrounds the connectors16, the conductive bumps18and the redistribution layer RDL4. In some embodiments, the underfill layer19further covers a portion of sidewalls of the die17. In some embodiments, the underfill layer19includes polymer such as epoxy. Referring toFIG.1C, an encapsulant20is then formed on the RDL structure12to encapsulate the sidewalls of the die17, the first surface17aof the die17and the sidewalls of the underfill layer19. In some embodiments, the encapsulant20includes a molding compound, a molding underfill, a resin such as epoxy, a combination thereof, or the like. In some other embodiments, the encapsulant20includes a photo-sensitive material such as PBO, polyimide, BCB, a combination thereof, or the like, which may be easily patterned by exposure and development processes or laser drilling process. In alternative embodiments, the encapsulant20includes nitride such as silicon nitride, oxide such as silicon oxide, phosphosilicate glass (PSG), borosilicate glass (BSG), boron-doped phosphosilicate glass (BPSG), a combination thereof, or the like. The encapsulant20is formed by a suitable fabrication technique such as spin-coating, lamination, deposition, or similar processes. In some embodiments, the top surface of the encapsulant20is higher than or over the first surface17aof the die17, such that the first surface17aof the die17is encapsulated by the encapsulant20. However, the present disclosure is not limited thereto. Referring toFIG.1D, in some embodiments, a protection layer21is then formed over the die17and the encapsulant20. In other words, the protection layer21is a backside film formed at the backside (opposite to the front-side) of the die17. In some embodiments, the protection layer21completely covers the top surface of the encapsulant20. In some embodiments, the protection layer21is referred as a warpage control layer, and preferably provides a sufficient degree of rigidity to the underlying structure, so as to control the warpage of the underlying structure. The protection layer21may comprise a single-layer structure or a multi-layer structure. In some embodiments, the protection layer21includes an inorganic material, an organic material, or a combination thereof. The inorganic material includes silicon nitride, a low temperature nitride such as aluminum nitride, gallium nitride, aluminum gallium nitride or the like, or a combination thereof. The organic dielectric material includes a polymer such as PBO, PI, BCB, ajinomoto buildup film (ABF), solder resist film (SR), or the like, or a combination thereof. However, the present disclosure is not limited thereto, the protection layer21may include any kind of materials, as long as it provides a sufficient degree of rigidity to the underlying structure against warpage and twisting. The protection layer21is formed by a suitable fabrication technique such as spin-coating, lamination, chemical vapor deposition (CVD), plasma-enhanced chemical vapor deposition (PECVD) or the like, for example. In some embodiments, the thickness T1of the protection layer21ranges from 5 μm to 100 μm. Referring toFIG.1E, the de-bonding layer11is decomposed under the heat of light, and the carrier10is then released from the overlying structure. In some embodiments, before the carrier10is released, a frame tape (not shown) is attached to the protection layer21, and the frame tape is removed after the carrier10is released. Thereafter, the redistribution layer RDL1 is exposed for electrical connection in the subsequent process. In some embodiments, the redistribution layer RDL1 includes a redistribution layer RDL1a and a redistribution layer RDL1b. The redistribution layer RDL1a is also referred as under-ball metallurgy (UBM) layer for ball mounting. The redistribution layer RDL1b may be micro bump for connecting to an integrated passive device (IPD)24in the subsequent process. Referring toFIG.1EandFIG.1F, a plurality of connectors23are formed on and electrically connected to the redistribution layer RDL1a of the RDL structure12. In some embodiments, the connectors23are referred as conductive terminals. In some embodiments, the connectors23are, for example, solder balls or ball grid array (BGA) balls. In some embodiments, the material of the connector23includes copper, aluminum, lead-free alloys (e.g., gold, tin, silver, aluminum, or copper alloys) or lead alloys (e.g., lead-tin alloys). In some embodiments, the connectors23are placed on the redistribution layer RDL1a by a ball mounting process. Still referring toFIG.1F, in some embodiments, an integrated passive device (IPD)24including a plurality of pads25is electrically connected to the redistribution layer RDL1b through a plurality of conductive bumps26therebetween. The IPD24may be a capacitor, a resistor, an inductor or the like, or a combination thereof. The IPD24is optionally connected to the RDL structure12, and the number of the IPD24is not limited to that is shown inFIG.1F, but may be adjusted according to the design of the product. An underfill layer27is formed to fill the space between the IPD24and the RDL structure12. The underfill layer27covers a portion of the surface of the IPD24and a portion of the bottom surface of the RDL structure12, and surrounds the pads15of the IPD24and the conductive bumps26. The material of the underfill layer27is similar to that of the underfill layer19, which is not described again. Still referring toFIG.1F, a package structure50ais thus completed. The package structure50aincludes the die17, the encapsulant20, the RDL structure12, the connectors23, the IPD24and the protection layer21. The connectors23and the IPD24are electrically connected to the die17through the RDL structure12. The protection layer21is formed for controlling the warpage of the package structure50a, that is, the protection layer21provides a sufficient degree of rigidity to the package structure50aagainst warpage and twisting. Thereafter, the package structure50amay be connected to other package components such as a printed circuit board (PCB), a flex PCB, or the like through the connectors23. In the package structure50a, the encapsulant20encapsulates the sidewalls and the first surface17aof the die17. However, the present disclosure is not limited thereto. Referring toFIG.2A, processes similar to those ofFIGS.1A to1Care performed, in some embodiments, after the encapsulant20is formed as shown inFIG.1C, a grinding or polishing process such as a chemical mechanical polishing (CMP) process is performed to remove a portion of the encapsulant20, such that the first surface17aof the die17is exposed, and an encapsulant20aencapsulating the sidewalls of the die17is formed. In some embodiments, the top surface of the encapsulant20ais substantially coplanar with the first surface17aof the die17. Referring toFIG.2B, after the encapsulant20ais formed, processes similar to those ofFIG.1DtoFIG.1Fare performed subsequently, so as to form a package structure50b. The package structure50bdiffers from the package structure50ain that the top surface of the encapsulant20ais substantially level with the first surface17aof the die17, and the protection layer21is in contact with the top surface of the encapsulant20aand the first surface17aof the die17. In some embodiments, the protection layer21completely covers the top surface of the encapsulant20aand the first surface17aof the die17. The other structural characteristics of the package structure50bare similar to those of the package structure50a, which is not described again. FIG.3AtoFIG.3Hare schematic cross-sectional views illustrating a method of manufacturing a package structure according to a second embodiment of the disclosure. The second embodiments differs from the first embodiment in that, a plurality of through integrated fan-out vias (TIVs)28are formed aside the die17. Referring toFIG.3A, similar to the processes ofFIGS.2A and2B, a RDL structure12including polymer layers PM1, PM2, PM3, PM4 and redistribution layers RDL1, RDL2, RDL3, RDL4 is formed over a carrier10. In some embodiments, the redistribution layer RDL4 includes a redistribution layer RDL4a and a redistribution layer RDL4b. The redistribution layer RDL4b is located aside and around the redistribution layer RDL4a. A die17is placed on and electrically connected to the redistribution layer RDL4a through a plurality of conductive bumps18. An underfill layer19is formed to fill the space between the die17and the RDL structure12. The structural characteristics of the die17, the RDL structure12, the conductive bumps18and the underfill layer19are similar to those of the first embodiments, which will not be described again. A plurality of TIVs28are formed on and electrically connected to the redistribution layer RDL4b. In some embodiments, the TIVs28include copper, nickel, solder, alloys thereof, or the like. In some embodiments, the TIV28includes a seed layer and a conductive layer formed thereon (not shown). The seed layer is, for example, a titanium or/and copper composited layer. The conductive layer is, for example, a copper layer. An exemplary forming method of the TIVs28includes forming a photoresist layer such as a dry film resist over the carrier10. Thereafter, openings are formed in the photoresist layer, the openings exposes a portion of the top surface of the redistribution layer RDL4b, and the TIVs28are then formed in the openings by electroplating. In some other embodiments, the TIVs28further include a barrier layer (not shown) under the seed layer to prevent metal diffusion. The material of the barrier layer includes, for instance, metal nitride such as titanium nitride, tantalum nitride, or a combination thereof. Still referring toFIG.3A, the die17is located between and surrounded by the TIVs28, that is, the TIVs28are aside or around the die17. In some embodiments, the top surface of the TIV28is higher than the first surface17aof the die17, but the disclosure is not limited thereto. In some other embodiments, the top surface of the TIV28is substantially level with the first surface17aof the die17. Referring toFIG.3B, an encapsulant20is formed over the RDL structure12, so as to encapsulate the sidewalls of the TIVs28, the sidewalls and a portion of a surface of the RDL4b, the sidewalls of the underfill layer19, the sidewalls and the first surface17aof the die17. The material of the encapsulant20is substantially the same as that of the first embodiment. The encapsulant20may be formed by forming an encapsulant material layer over the carrier10. The encapsulant material layer encapsulates the top surfaces and sidewalls of the die17and the TIVs28. Thereafter, a grinding or polishing process is performed to remove a portion of the encapsulant material layer, such that the top surfaces of the TIVs28are exposed. In some embodiments, the top surfaces of the TIVs28and the top surface of the encapsulant20are substantially coplanar and higher than or over the first surface17aof the die17, but the present disclosure is not limited thereto. Referring toFIG.3BandFIG.3C, a protection layer21is then formed over the die17, the encapsulant20and the TIVs28. In some embodiments, the protection layer21is referred as a warpage control layer. The material and the forming method of the protection layer21are similar to those of the first embodiments. Referring toFIG.3CandFIG.3D, a portion of the protection layer21is removed to form a plurality of openings29. The removal method includes exposure and development processes, laser drilling process, photolithography and etching processes, or a combination thereof. The opening29penetrates through the protection layer21to expose a portion of the top surface of the TIV28. The opening29is also referred as a recess. Still referring toFIG.3D, thereafter, a plurality of caps30are formed in the openings29and on the TIVs28. In some embodiments, the caps30are formed for protecting the TIVs28from oxidation or pollution. The cap30includes metal, organic material, or a combination thereof. In some embodiments, the cap30includes solder, solder paste adhesive or a combination thereof, and the cap30may be formed by dropping solder balls in the openings29and then a reflow process is performed. In some other embodiments, the cap30includes an organic material, such as an organic solderability preservative (OSP), and the cap30is referred as an OSP layer, such as a copper OSP layer. In some embodiments, the OSP layer includes benzotriazole, benzimidazoles, or combinations and derivatives thereof. In some embodiments, the OSP layer is formed by coating, and the OSP coating is applied by immersing the surfaces of the TIVs28exposed in the openings29in an OSP solution, or spaying an OSP solution on the surfaces of the TIVs28exposed in the openings29. The OSP solution may contain alkylimidazole, benzotriazole, rosin, rosin esters, or benzimidazole compounds. Alternatively, the OSP coating is made with phenylimidazole or other imidazole compounds including 2-arylimidazole as the active ingredient. In some embodiments, the cap30is formed within the opening29, and the top surface of the cap30is lower than the top surface of the protection layer21, but the disclosure is not limited thereto. In some other embodiments, the cap30may filled up the opening29and protrudes from the top surface of the protection layer21. The cross-section shape of the cap30may be inverted trapezoid, inverted trapezoid with a arced base, square, rectangle, semicircular, or any other shape, as long as the cap30covers the TIV28to protect the TIV28from oxidation. Referring toFIG.3EandFIG.3F, processes similar toFIG.1EandFIG.1Fare performed, so as to form a package structure50c. The de-bonding layer11is decomposed under the heat of light, and the carrier10is then released from the overlying structure. Thereafter, a plurality of connectors23are formed on and electrically connected to the redistribution layer RDL1a of the RDL structure12. An IPD24is electrically connected to the redistribution layer RDL1b through a plurality of conductive bumps26. Referring toFIG.3F, the package structure50cis thus completed. The package structure50cincludes the die17, the encapsulant20, the TIVs28, the RDL structure12, the connectors23, the IPD24and the protection layer21. The protection layer21covers and contacts with the top surface of the encapsulant20, and a portion of the top surface of the TIVs28. The protection layer21has a plurality of openings29exposing the TIVs28, and a plurality of caps30are located in the openings29to protect the TIVs28from oxidation or pollution. That is to say, a portion of the top surface of the TIV28is covered by the protection layer21, and another portion of the top surface of the TIV28is covered by the cap30. Referring toFIG.3GandFIG.3H, in some embodiments, the package structure50cis further connected to a package structure60to form a package-on-package (PoP) device70a. Referring toFIG.3G, the package structure60is provided. The package structure60may be any kind of package structures according to the functional demand of the PoP device70a. In some embodiments, the package structure60includes a package body61and a plurality of connectors62attached to the package body61. In some embodiments, the connectors62are referred as conductive terminals. The material and the forming method of the connector62are similar to those of the connector23of the package structure50c. In some embodiments, the connectors62are located at the positions corresponding to the positons of the openings29of the package structure50c. Referring toFIG.3GandFIG.3H, a reflow process is performed at least on the connectors62, so that a connector62ais formed to connect the package structure50cand the package structure60. The connectors62aare in electrical contact with the TIVs28. In some embodiments in which the cap30is formed of solder, solder paste adhesive or a combination thereof, the cap30is melted and fused with the connector62during the reflow process, that is, the connector62ais formed of the connector62and the cap30. In some embodiments in which the cap30is an OSP layer, before the reflow process is performed, a cleaning process is performed to remove the cap30, that is, the connector62ais formed of the connector62. Referring toFIG.3H, in some embodiments, an underfill layer63is further formed to fill the space between the package structure50cand the package structure60and surround the connectors62a. The PoP device70aincluding the package structure50cand the package structure60is thus completed, and the package structure50cand the package structure60are connected through the connectors62a. The PoP device70aas shown inFIG.3His just for illustration, and the disclosure is not limited thereto. Referring toFIG.3B,FIG.4AandFIG.4B, in some other embodiments, after the encapsulant20is formed as shown inFIG.3B, the grinding or polishing process is performed, such that the top surfaces of the TIVs28and the first surface17aof the die17are exposed, and an encapsulant20ais formed. In some embodiments in which the TIVs28are formed with a top surface higher than the first surface17aof the die17, a portion of the encapsulant20and a portion of the TIVs28are removed during the grinding or polishing process. In some embodiments in which the TIVs28are formed with a top surface substantially level with the first surface17aof the die17, a portion of the encapsulant20is removed during the grinding or polishing process. In some embodiments, the top surfaces of the TIVs28, the top surface of the encapsulant20aand the first surface17aof the die are substantially coplanar with each other. In other words, the protection layer21is in contact with the first surface17aof the die17, the top surface of the TIVs28, and the top surface of the encapsulant20a. In some embodiments, the protection layer21completely covers the first surface17aof the die17, the top surface of the TIVs28, and the top surface of the encapsulant20a. Referring toFIG.4B, a package structure50dis then formed through the processes similar to those ofFIG.3CtoFIG.3F. Referring toFIG.3FandFIG.4B, the package structure50ddiffers from the package structure50cin that the top surfaces of the TIVs28, the top surface of the encapsulant20aand the first surface17aof the die17are coplanar with each other, and the protection layer21is in contact with the first surface17aof the die17. Other structural characteristics of the package structure50dare similar to those of the package structure50c. Similarly, the package structure50dmay further connected to other package structures to form a PoP device. Referring toFIG.4BandFIG.4C, processes similar to those ofFIG.3GtoFIG.3Hare performed, such that the package structure50dis connected to a package structure60, and a PoP device70bis formed. FIG.5AtoFIG.5Bare schematic cross-sectional views illustrating a method of manufacturing a package structure according to a third embodiment of the disclosure. The third embodiment differs from the foregoing embodiments in that a protection layer121is formed at the back side of the die17. In some embodiments, the protection layer121acts as a warpage control layer and a heat spreader. Referring toFIG.2AandFIG.5A, in some embodiments, after the encapsulant20ais formed aside the die17, the top surface of the encapsulant20aand the first surface17aof the die17form a surface31. A protection layer121is attached to the surface31through an adhesive layer32. The adhesive layer32is in contact with the die17and the encapsulant20a. In some embodiments, the protection layer121is a plate or a sheet, and acts as a warpage control layer for preventing or reducing the warpage of the underlying structure, and also act as a heat spreader conducting heat away from the die17. In some embodiments, the adhesive layer32may also help to conduct heat away from the die17. The protection layer121may include single material or composite material, and may be a single-layer structure or a multi-layer structure. In some embodiments, the protection layer121includes a thermally conductive material, and has a thermal conductivity greater than the die17and the encapsulant20a. In some embodiments, the protection layer121includes a conductive material and is floating, that is to say, the protection layer121is not electrically connected to any other layers. In some embodiments, the protection layer121includes a rigid metal (such as copper, steel, or a combination thereof), a ceramic material, a silicon containing material, diamond, or a combination thereof. In some embodiments, the protection layer121is a copper layer, a steel layer, or a diamond film. In some other embodiments, the protection layer121includes a composite material composed of a matrix material and fillers. In some embodiments, the matrix material includes graphite, graphene, a polymer or a combination thereof. The fillers include diamond, oxide such as aluminum oxide or silicon oxide, carbide such as silicon carbide, or a combination thereof. However, the material of the protection layer121is not limited to those described above, the protection layer121may include any material, as long as the protection layer121preferably provides a sufficient degree of rigidity to present or reduce the warpage of the underlying structure and also effectively conducts heat away from the die17. In some embodiments, the adhesive layer32includes a die attach film (DAF), a thermal interface material (TIM), or a combination thereof. In some embodiments, the material of the adhesive layer32is also thermally conductive, and has a thermal conductivity greater than the die17and the encapsulant20a. In some embodiments, the thermal conductivity of the adhesive layer32and the thermal conductivity of the protection layer121may be the same or different. In some embodiments, the thermal conductivity of the adhesive layer32may be greater or less than the thermal conductivity of the protection layer121. Still referring toFIG.5A, in some embodiments, the thickness T2of the protection layer121ranges from 30 μm to 400 μm. The thickness T2of the protection layer121is dependent on the material thereof. In some embodiments in which the protection layer121is a diamond film, the thickness T2of the protection layer121may be less than 30 μm. In some embodiments, the width W1of the protection layer121is substantially the same as the width W2of the surface31. The first surface17aof the die17and the top surface of the encapsulant20aare covered by the protection layer121. In some embodiments, the first surface17aof the die17and the top surface of the encapsulant20aare completely covered by the protection layer121. In some other embodiments, the width W1of the protection layer121is less than the width W2of the surface31, and greater than the width W3of the die17. That is, the first surface17aof the die17and a portion of the top surface of the encapsulant20aare covered by the protection layer121. In yet alternative embodiments, the width W1of the protection layer121may be substantially the same as or slightly less than the width W3of the first surface17aof the die17, thus the first surface17aof the die17is covered or partially covered by the protection layer121. That is to say, the thickness T2and the width W1of the protection layer121may be adjusted, as long as the protection layer121provides the properties necessary to achieve the objectives of the present disclosure. Referring toFIG.5AandFIG.5B, thereafter, processes similar to those ofFIG.1EtoFIG.1Fare performed, such that the carrier10is released with the de-bonding layer11decomposed under the heat of light. Thereafter, a plurality of connectors23are electrically connected to the redistribution layer RDL1a of the RDL structure12. An IPD24is electrically connected to the redistribution layer RDL1b through a plurality of conductive bumps26. Referring toFIG.5B, a package structure50eis thus completed. The package structure50eincludes the die17, the encapsulant20a, the RDL structure12, the connectors23, the IPD24, and the protection layer121. In some embodiments, the protection layer121is used for controlling the warpage of the package structure50eand for spreading the heat of the die17. The other structural characteristics are similar to those of the package structure50b. FIG.6AtoFIG.6Dare schematic cross-sectional views illustrating a method of manufacturing a package structure according to a fourth embodiment of the disclosure. The forth embodiment differs from the third embodiment in that a plurality of TIVs28are formed aside the die17. Referring toFIG.6A, after the TIVs28and the encapsulant20ais formed aside the die17(as shown inFIG.4A), a protection layer121is attached to the die17and the encapsulant20athrough an adhesive layer32. In some embodiments, the protection layer121covers the first surface17aof the die17and a portion of the top surface of the encapsulant20a. The TIVs28are not covered by the protection layer121, and exposed. In some other embodiments, the protection layer121only covers or partially covers the first surface17aof the die17, and does not cover the top surface of the encapsulant20aand the TIV28. The material of the protection layer121and the material of the adhesive layer32are substantially the same as those of the third embodiment. Referring toFIG.6AandFIG.6B, a plurality of caps30are formed on the TIVs28to at least cover the top surfaces of the TIVs28. In some embodiments, the top surface of the TIV28is completely covered by the cap30. In some embodiments, the top surface of the TIV28and a portion of the top surface of the encapsulant20aare covered by the cap30. The material, forming method and the properties of the cap30are similar to those of the second embodiment. In some embodiments, the cross-section shape of the cap30may be semicircular, arc-shaped, square, rectangle, trapezoid, or a combination thereof. The cap30may be any shape, as long as the TIV28is covered and protected from oxidation or pollution. Still referring toFIG.6AandFIG.6B, the carrier10is released with the de-bonding layer11decomposed under the heat of light. Thereafter, a plurality of connectors23are electrically connected to the redistribution layer RDL1a of the RDL structure12. An IPD24is electrically connected to the redistribution layer RDL1b through a plurality of conductive bumps26. Referring toFIG.6B, a package structure50fis thus completed. The package structure50fincludes the die17, the encapsulant20a, the TIVs28, the RDL structure12, the connectors23, the IPD24and the protection layer121. The TIVs28are covered by the caps30. In some embodiments, the TIVs28are covered to be protected from oxidation or pollution. In some embodiments, the protection layer121is used for controlling the warpage of the package structure50fand spreading the heat of the die17. The package structure50fmay further coupled to other package structures to form a PoP device. Referring toFIG.6CandFIG.6D, in some embodiments, a package structure60including a package body61and a plurality of connectors62is provided, thereafter a reflow process is performed, such that a connector62ais formed to connect the package structure50fand the package structure60. Similar to the second embodiments, the connector62amay be formed of the connector62or formed of the connector62and the cap30, the forming method of the connector62ais similar to that of the second embodiment as shown inFIG.3GtoFIG.3H. Thereafter, an underfill layer63is formed to fill the space between the package structure50fand the package structure60, and a PoP device70cis thus completed. In the second and the fourth embodiments, as shown inFIG.3H,FIG.4CandFIG.6D, the package structure50c/50d/50fis connected to the package structure60, so as to form a PoP device70a/70b/70c, however, the number of the package structures that may be coupled to the package structure50c/50d/50fis not limited thereto. In some other embodiments, more than one package structures are connected to the package structure50c/50d/50f, and IPDs may also be coupled to the package structure50c/50d/50f. For the sake of brevity, the package structure50cis taken for example. Referring toFIG.7, in some embodiments, a PoP device70dcomprising a package structure50c, a package structure61and a package structure64is formed. The package structure50cincludes a plurality of TIVs28. The TIVs28includes a plurality of TIVs28aand a plurality of TIVs28b. The TIVs28aare aside and around the die17. The TIVs28bare aside the TIVs28aand relatively farther away from the die17than the TIVs28a, that is to say, no die is surrounded by the TIVs28b, but the disclosure is not limited thereto. Still referring toFIG.7, the package structure61is electrically coupled to the package structure50cthrough the connectors62a. A package structure64is electrically coupled to the package structure50cthough the connectors65by a similar method as described in the processes ofFIG.3GtoFIG.3H. The package structure61and the package structure64may be the same types or different types of package structures. The package structure61is connected to the TIVs28aof the package structure50c, and the package structure64is connected to the TIVs28bof the package structure50c. Referring toFIG.8, in some embodiments, besides the package structure61and the package structure64are coupled to the package structure50c, an IPD66is further electrically coupled to the package structure50cthrough a plurality of connectors67, and a PoP device70eis thus completed. The IPD66may be a capacitor, a resistor, an inductor or the like, or a combination thereof. In some embodiments, the TIVs28includes a plurality of TIVs28cbetween the TIVs28aand the TIVs28b. The package structure61is connected to the TIVs28a. In some embodiments, the package structure64is connected to the TIVs28b. The IPD66is connected to the TIVs28c. The IPD66is located between the package structure61and the package structure64, but the disclosure is not limited thereto. In the present disclosure, a protection layer is formed at the backside of the die. In some embodiments, the protection layer acts as a warpage control layer to control warpage of the package structure. In some embodiments, the protection layer also acts as a heat spreader of the die. In accordance with some embodiments of the disclosure, a package structure includes a die, a TIV, an encapsulant, a RDL structure, an underfill layer, a protection layer, and a cap. The TIV is aside the die. The encapsulant laterally encapsulates the die and the TIV. The RDL structure is electrically connected to the die. The underfill layer is disposed between the die and the RDL structure and laterally encapsulated by the encapsulant. The protection layer is overlying the die and the encapsulant. The cap covers a top surface of the TIV and laterally aside the protection layer. A top surface of the cap is higher than a top surface of the encapsulant and lower than a top surface of the protection layer. In accordance with some embodiments of the disclosure, a package structure includes a RDL structure, a die, a TIV, an encapsulant, a warpage controlling layer and a cap. The die is electrically bonded to the RDL structure through a plurality of conductive bumps. The TIV is aside the die and landing on a top conductive RDL of the RDL structure. The encapsulant encapsulates sidewalls of the die, the TIV and the top conductive RDL. The warpage controlling layer covers the die and the encapsulant. The cap is laterally aside the warpage controlling layer and covers the TIV. A top surface of the cap is located at a level height between a top surface of the encapsulant and a top surface of the warpage controlling layer. In accordance with some embodiments of the disclosure, a method of forming a package structure includes the following processes. A first package structure is formed by the following processes: forming a RDL structure; electrically bonding a die to the RDL structure; forming a TIV on the RDL structure and laterally aside the die; forming an encapsulant to laterally encapsulate the TIV and the die; forming a protection layer over the encapsulant and the die; and forming a cap on the TIV and laterally aside the protection layer. The cap is removed from the first package structure, and the first package structure is connected to the second package structure. The foregoing outlines features of several embodiments so that those skilled in the art may better understand the aspects of the disclosure. Those skilled in the art should appreciate that they may readily use the disclosure as a basis for designing or modifying other processes and structures for carrying out the same purposes and/or achieving the same advantages of the embodiments introduced herein. Those skilled in the art should also realize that such equivalent constructions do not depart from the spirit and scope of the disclosure, and that they may make various changes, substitutions, and alterations herein without departing from the spirit and scope of the disclosure. | 43,701 |
11862470 | DESCRIPTION OF EMBODIMENTS Although embodiments of the present invention are hereunder specifically described, it should not be construed that the present invention is limited to the following embodiments, and the present invention can be carried out by making various changes within the scope of a gist thereof. In this specification, the expression “to” is used as an expression including numerical values or physical property values before and after the expression. Silica Particle Silica particles according to the present embodiment satisfies the following formula (1) where a d value measured by wide-angle X-ray scattering is y Å. y≥4.2 (1) When the d value of the silica particles is 4.2 Å or more, formation of a membered ring is promoted with sharing oxygen of a SiO4tetrahedron, a membered ring size becomes large and a strain becomes small, the silica particles are hardly elastically deformed, mechanical strength is excellent, and polishing characteristics of a polishing composition are excellent. The d value of the silica particles is calculated based on a first sharp diffraction peak (FSDP) measured by wide-angle X-ray scattering using copper Kα1 line (wavelength λ of Kα1 line=1.5405 Å). That is, a scattering vector q (q=4π·sin θ/λ) is calculated based on a scattering angle 2θ indicating a maximum intensity of an observed halo pattern, and the scattering vector q is used to calculate the d value using the following formula (5) representing a Bragg's law (λ=2d·sin θ). In the case of amorphous silica, the d value represents an interval between surfaces aligned through voids. d=2π/q(5) Specifically, a parallel beam X-ray diffraction equipment is used, and a recessed portion of a non-reflective sample plate formed of silicon is filled with a silica sol containing the silica particles and attached to the equipment. The silica sol on the non-reflective sample plate is irradiated with a parallel beam of copper Kα1 line (wavelength λ, of Kα1 line=1.5405 Å) at an irradiation angle of 0.1°, and 2θ scanning (20 range is from 5° to 50°) is performed to obtain an X-ray scattering pattern. A scattering angle 2θ indicating the maximum intensity of the obtained halo pattern is recorded, the scattering vector q (q=4π·sin θ/λ) is calculated, and the d value is calculated by using the scattering vector q and the above equation (5) representing a Bragg's law (λ=2d·sin θ). The d value of the silica particles satisfies the following formula (1), preferably satisfies the following formula (1′), more preferably satisfies the following formula (1″), and still more preferably satisfies the following formula (1″′), since the membered ring size is large, the number of defects is small, the mechanical strength of the silica particles is excellent, and the polishing characteristics of the polishing composition are excellent. y≥4.2 (1) y≥4.5 (1′) y≥4.7 (1″) y≥4.8 (1″′) The d value of the silica particles preferably satisfies the following formula (3), more preferably satisfies the following formula (3′), and still more preferably satisfies the following formula (3″), since the silica particles form a membered ring having a small strain with maintaining an amorphous state. y≤6.0 (3) y≤5.8 (3′) y≤5.7 (3″) The d value of the silica particles can be set in a desired range by adjusting conditions of a hydrolysis reaction and a condensation reaction of alkoxysilane and conditions of a subsequent treatment. Specific examples thereof include a method in which a silica sol obtained by a hydrolysis reaction and a condensation reaction of alkoxysilane is subjected to a pressurized heat treatment; a method in which a hydrolysis reaction and a condensation reaction are separately performed; and a method in which a reaction accelerator is added in a hydrolysis reaction and a condensation reaction; etc. Among these methods, the method is preferred in which a silica sol obtained by a hydrolysis reaction and a condensation reaction of alkoxysilane is subjected to a pressurized heat treatment, since the d value can be precisely controlled. It is preferable that a silica particle satisfies the following formulae (1) and (2) where a density of silanol groups on a surface measured by the Sears method is an x surface silanol group number/nm2and the d value measured by the wide-angle X-ray scattering is y Å. When the following formula (1) and the following formula (2) are satisfied, the formation of the membered ring is promoted with sharing oxygen of a SiO4tetrahedron, the number of defects of the silica particles is small, the mechanical strength of the silica particles is excellent, and the polishing characteristics of the polishing composition are excellent, and also the silica particles have appropriate surface repulsion, and dispersion stability of the silica sol is excellent. y≥4.2 (1) y≥−0.2x+5.4 (2) It is more preferable that a silica particle satisfies following formulae (3) and (4). When the following formula (3) and the following formula (4) are satisfied, the membered ring size is large, the strain is small, the mechanical strength of the silica particles is excellent, and the polishing characteristics of the polishing composition are excellent, and also the silica particles have appropriate surface repulsion, and aggregation of the silica sol can be prevented. y≤6.0 (3) y≤−0.2x+7.0 (4) A density of silanol groups on the surfaces of the silica particles is measured by the Sears method. Specifically, measurement and calculation are performed under the following conditions. The silica sol corresponding to 1.5 g of silica particles is collected, and pure water is added thereto to adjust a liquid amount to be 90 mL. A hydrochloric acid aqueous solution of 0.1 mol/L is added until a pH reaches 3.6 in an environment of 25° C., 30 g of sodium chloride is added, sodium chloride is completely dissolved with gradually adding pure water, and finally, pure water is added until a total amount of a test solution reaches 150 mL to obtain the test solution. The obtained test solution is placed in an automatic titration device, and a sodium hydroxide aqueous solution of 0.1 mol/L is added dropwise thereto to measure a titration amount A (mL) of the sodium hydroxide aqueous solution of 0.1 mol/L required for the pH to be changed from 4.0 to 9.0. A consumption amount V (mL) of the sodium hydroxide aqueous solution of 0.1 mol/L required for the pH to be changed from 4.0 to 9.0 per 1.5 g of the silica particles is calculated using the following formula (6), and a density p (number/nm2) of silanol groups on the surfaces of the silica particles is calculated using the following formula (7). V=(A×f×100×1.5)/(W×C) (6)A: titration amount (mL) of sodium hydroxide aqueous solution of 0.1 mol/L required for pH to be changed from 4.0 to 9.0 per 1.5 g of silica particlesf: titer of used sodium hydroxide aqueous solution of 0.1 mol/LC: concentration (mass %) of silica particles in silica solW: collection amount (g) of silica sol ρ(B×NA)/(1018×M×SBET) (7)B: sodium hydroxide amount (mol) required for pH to be changed from 4.0 to 9.0 per 1.5 g of silica particles calculated based on VNA: Avogadro number (number/mol)M: silica particle amount (1.5 g)SBET: specific surface area (m2/g) of silica particles measured at time of calculation of average primary particle size A method of measuring and calculating the density of silanol groups on a surface of the silica particles is referred to “G. W. Sears, Jr., Analytical Chemistry, Vol. 28, No. 12, pp. 1981-1983 (1956).”, “Shinichi Haba, Development of Polishing Agent for Semiconductor Integrated Circuit Process, Kochi University of Technology Doctoral Dissertation, pp. 39-45, March 2004”, “Japanese Patent No. 5967118”, and “Japanese Patent No. 6047395”. The d value and the density of silanol groups on the surfaces of the silica particles may be set to desired ranges by adjusting conditions of the hydrolysis reaction and the condensation reaction of alkoxysilane and conditions of a subsequent treatment. Specific examples thereof include a method in which a silica sol obtained by a hydrolysis reaction and a condensation reaction of alkoxysilane is subjected to a pressurized heat treatment; a method in which a reaction accelerator is added in a hydrolysis reaction and a condensation reaction; etc. Among these methods, the method is preferred in which a silica sol obtained by a hydrolysis reaction and a condensation reaction of alkoxysilane is subjected to a pressurized heat treatment, since the d value and the density of silanol groups on the surface can be precisely controlled. The hydrolysis reaction and the condensation reaction are methods in which alkoxysilane is hydrolyzed in a presence of a catalyst such as an acid or a base, and the resulting silanol group is dehydrated and condensed to grow particles with forming a siloxane bond, thereby obtaining silica particles. At this time, the silanol group disappears with a progress of the condensation reaction, but for example, the silanol group density inside or on the surfaces of the silica particles may be adjusted by setting conditions such as alkoxysilane, solvent or dispersion medium, catalyst composition, reaction temperature, reaction time during the hydrolysis reaction and the condensation reaction. A silica particle preferably satisfies the following formula (8), more preferably satisfies the following formula (8′), and still more preferably satisfies the following formula (8″), since the silica particles have the appropriate surface repulsion and dispersion stability of the silica sol is excellent. x≥0.1 (8) x≥0.5 (8′) x≥1 (8″) A silica particle preferably satisfies the following formula (9), more preferably satisfies the following formula (9′), and still more preferably satisfies the following formula (9″), since the silica particles have the appropriate surface repulsion and the aggregation of the silica particles can be prevented. x≤10 (9) x≤7.5 (9′) x≤7 (9″) A silica particle preferably satisfies the following formula (2), more preferably satisfies the following formula (2′), and still more preferably satisfies the following formula (2″), since the membered ring size is large, the strain is small, the mechanical strength of the silica particles is excellent, and the polishing characteristics of the polishing composition are excellent. y≥−0.2x+5.4 (2) y≥−0.2x+5.5 (2′) y≥−0.2x+5.6 (2″) A silica particle preferably satisfies the following formula (4), and more preferably satisfies the following formula (4′), since the membered ring is formed with a small strain while the amorphous state is maintained. y≤−0.2x+7.0 (4) y≤−0.2x+6.9 (4′) The average primary particle size of the silica particles is preferably 5 nm or more, and more preferably 10 nm or more, and is preferably 100 nm or less, and more preferably 60 nm or less. When the average primary particle size of the silica particles is 5 nm or more, the storage stability of the silica sol is excellent. When the average primary particle size of the silica particles is 100 nm or less, surface roughness and flaws of an object to be polished typified by a silicon wafer can be reduced, and sedimentation of the silica particles can be prevented. The average primary particle size of the silica particles is measured by the BET method. Specifically, the specific surface area of the silica particles is measured using an automatic measurement device of a specific surface area, and the average primary particle size is calculated using the following formula (10). Average primary particle size (nm)=6000/(specific surface area (m2/g)×density (g/cm3)) (10) The average primary particle size of the silica particles can be set to a desired range by known conditions and methods. An average secondary particle size of the silica particles is preferably 10 nm or more, and more preferably 20 nm or more, and is preferably 200 nm or less, and more preferably 100 nm or less. When the average secondary particle size of the silica particles is 10 nm or more, removability of particles and the like in washing after polishing is excellent, and the storage stability of the silica sol is excellent. When the average secondary particle size of the silica particles is 200 nm or less, the surface roughness and the flaws of the object to be polished typified by a silicon wafer during polishing can be reduced, the removability of particles and the like in washing after polishing is excellent, and the sedimentation of the silica particles can be prevented. The average secondary particle size of the silica particles is measured by the DLS method. Specifically, measurement is performed using a dynamic light scattering particle size measuring device. The average secondary particle size of the silica particles can be set to a desired range by known conditions and methods. Coefficient of variation (cv) of the silica particles is preferably 15 or more, more preferably 20 or more, and still more preferably 25 or more, and is preferably 50 or less, more preferably 40 or less, and still more preferably 35 or less. When the coefficient of variation (cv) of the silica particles is 15 or more, a polishing rate for the object to be polished typified by a silicon wafer is excellent, and productivity of the silicon wafer is excellent. When the coefficient of variation (cv) of the silica particles is 50 or less, the surface roughness and flaws of the object to be polished typified by a silicon wafer during polishing can be reduced, and the removability of particles and the like in washing after polishing is excellent. The coefficient of variation (cv) of the silica particles is a value calculated by measuring the average secondary particle size of the silica particles using the dynamic light scattering particle size measuring device and using the following formula (11), and is a value serving as an index of a uniform particle size. cv=(standard deviation (nm)/average secondary particle size (nm))×100 (11) An association ratio of the silica particles is preferably 1.0 or more, and more preferably 1.1 or more, and is preferably 4.0 or less, and more preferably 3.0 or less. When the association ratio of the silica particles is 1.0 or more, the polishing rate for the object to be polished typified by a silicon wafer is excellent, and the productivity of the silicon wafer is excellent. When the association ratio of the silica particles is 4.0 or less, the surface roughness and flaws of the object to be polished typified by a silicon wafer during polishing can be reduced, and aggregation of the silica particles can be prevented. The association ratio of the silica particles is calculated using the following formula (12) based on the average primary particle size measured by the measuring method described above and the average secondary particle size measured by the measuring method described above. Association ratio=average secondary particle size/average primary particle size (12) A content of metal impurity of the silica particles is preferably 5 ppm or less, and more preferably 2 ppm or less. In the present specification, ppm means ppm by mass. In polishing of a silicon wafer of a semiconductor device, the metal impurity adhere to and contaminate a surface of the object to be polished, which adversely affects wafer characteristics, and the metal impurity diffuses into the wafer to deteriorate quality. Therefore, performance of the semiconductor device manufactured by such wafers is significantly reduced. When the metal impurity is present in the silica particles, a coordination interaction occurs between a surface silanol group exhibiting acidity and the metal impurity, chemical properties (acidity and the like) of the surface silanol group are changed, a three-dimensional environment (ease of aggregation of the silica particles and the like) of the surfaces of the silica particles is changed, and the polishing rate is affected. The content of the metal impurity of the silica particles is measured by high-frequency inductively coupled plasma mass spectrometry (ICP-MS). Specifically, a silica sol containing 0.4 g of silica particles is accurately weighed, and sulfuric acid and hydrofluoric acid are added thereto. The mixture is heated, dissolved, and evaporated, and pure water is added to the remaining sulfuric acid droplets so that a total amount is accurately 10 g to prepare a test solution. The test solution is measured using a high-frequency inductively coupled plasma mass spectrometer. A target metal is sodium, potassium, iron, aluminum, calcium, magnesium, zinc, cobalt, chromium, copper, manganese, lead, titanium, silver, or nickel. A total content of these metals is defined as the content of the metal impurity. The content of the metal impurity of the silica particles may be 5 ppm or less by performing the hydrolysis reaction and the condensation reaction using alkoxysilane as a main raw material to obtain the silica particles. In a method of deionization of alkali silicate such as water glass, sodium or the like derived from the raw material remains, and thus it is extremely difficult to set the content of the metal impurity of the silica particles to 5 ppm or less. Examples of a shape of the silica particles include a spherical shape, a chain shape, a cocoon shape (also referred to as a bump shape or a peanut shape), an irregular shape (for example, a wart shape, a bent shape, or a branched shape), etc. Among these shapes of the silica particles, in a case where it is desired to reduce the surface roughness or flaws of the object to be polished typified by a silicon wafer during polishing, a spherical shape is preferred, and in a case where it is desired to further increase the polishing rate for the object to be polished typified by a silicon wafer, an irregular shape is preferred. The silica particles according to the present embodiment preferably have no pores due to the excellent mechanical strength and storage stability. The presence or absence of pores in the silica particles is confirmed by the BET multipoint analysis using an adsorption isotherm using nitrogen as an adsorption gas. The silica particles according to the present embodiment preferably contain an alkoxysilane condensate as a main component, and more preferably contain a tetraalkoxysilane condensate as a main component due to the excellent mechanical strength and storage stability. The main component is defined as being 50 mass % or more of total components of the silica particles. Examples of the tetraalkoxysilane condensate include condensates such as tetramethoxysilane, tetraethoxysilane, tetrapropoxysilane, tetraisopropoxysilane, etc. These tetraalkoxysilane condensates may be used alone or in combination of two or more kinds thereof. Among these tetraalkoxysilane condensates, a tetramethoxysilane condensate and a tetraethoxysilane condensate are preferred, and a tetramethoxysilane condensate is more preferred, since the hydrolysis reaction is fast, an unreacted material hardly remains, productivity is excellent, and a stable silica sol can be easily obtained. In order to obtain silica particles containing an alkoxysilane condensate as a main component, it is preferable to use alkoxysilane as a main raw material. In order to obtain silica particles containing a tetraalkoxysilane condensate as a main component, it is preferable to use tetraalkoxysilane as a main raw material. The main raw material is defined as being 50 mass % or more of total raw materials of the silica particles. Method for Producing Silica Particles Examples of a method for producing silica particles include a method by thermal decomposition of silicon tetrachloride, a method by deionization of alkali silicate such as water glass, a method by a hydrolysis reaction and a condensation reaction of alkoxysilane, etc. Among these methods for producing silica particles, a method by a hydrolysis reaction and a condensation reaction of alkoxysilane is preferred, and a method by a hydrolysis reaction and a condensation reaction of tetraalkoxysilane is more preferred, since the content of the metal impurity can be reduced and the shape of the silica particles can be easily controlled. Examples of tetraalkoxysilane include tetramethoxysilane, tetraethoxysilane, tetrapropoxysilane, tetraisopropoxysilane, etc. These tetraalkoxysilanes may be used alone or in combination of two or more kinds thereof. Among these tetraalkoxysilanes, tetramethoxysilane and tetraethoxysilane are preferred, and tetramethoxysilane is more preferred, since the hydrolysis reaction is fast, the unreacted material hardly remains, the productivity is excellent, and the stable silica sol can be easily obtained. As the raw material of the silica particles, a raw material other than tetraalkoxysilane, such as a low condensation product of tetraalkoxysilane, may be used. Due to excellent reactivity, among the total raw materials of the silica particles, it is preferable that an amount of tetraalkoxysilane is 50% by mass or more and an amount of the raw materials other than tetraalkoxysilane is 50% by mass or less, and it is more preferable that the amount of tetraalkoxysilane is 90% by mass or more and the amount of the raw materials other than tetraalkoxysilane is 10% by mass or less. Examples of the solvent or dispersion medium used in the hydrolysis reaction and the condensation reaction include water, methanol, ethanol, propanol, isopropanol, ethylene glycol, etc. These solvents or dispersion media may be used alone or in combination of two or more. Among these solvents and dispersion media, water and alcohol are preferred, and water and methanol are more preferred, since those used in the hydrolysis reaction and the condensation reaction are the same as those produced as a by-product, and are excellent in convenience in production. The hydrolysis reaction and the condensation reaction may be performed in the presence of a catalyst or in the absence of a catalyst. It is preferable in the presence of a catalyst since the hydrolysis reaction and the condensation reaction can be promoted. Examples of the catalyst include acid catalysts such as hydrochloric acid, sulfuric acid, nitric acid, phosphoric acid, acetic acid, formic acid, and citric acid; and alkali catalysts such as ethylenediamine, diethylenetriamine, triethylenetetramine, ammonia, urea, ethanolamine, tetramethyl ammonium hydroxide, etc. Among these catalysts, an alkali catalyst is preferred since catalytic action is excellent and a particle shape is easy to be controlled, and an alkali catalyst is preferred and ammonia is more preferred since mixing of the metal impurity can be prevented, volatility is high, and removability after the condensation reaction is excellent. In order to increase a degree of condensation of the silica particles, in the method for producing silica particles according to the present embodiment, it is preferable to perform a pressurized heat treatment on the obtained silica particles after completion of the hydrolysis reaction and the condensation reaction of alkoxysilane. A pressure of the pressurized heat treatment is preferably 0.10 MPa or more, and more preferably 0.14 MPa or more, and is preferably 2.3 MPa or less, and more preferably 1.0 MPa or less. When the pressure of the pressurized heat treatment is 0.10 MPa or more, the degree of condensation of the silica particles can be increased. When the pressure of the pressurized heat treatment is 2.3 MPa or less, the silica particles can be produced without greatly changing the average primary particle size, the average secondary particle size, the coefficient of variation (cv), and the association ratio, and dispersion stability of the silica sol is excellent. A temperature of the pressurized heat treatment is preferably 100° C. or more, and more preferably 110° C. or more, and is preferably 220° C. or less, and more preferably 180° C. or less. When the temperature of the pressurized heat treatment is 100° C. or more, the degree of condensation of the silica particles can be increased. When the temperature of the pressurized heat treatment is 220° C. or less, the silica particles can be produced without greatly changing the average primary particle size, the average secondary particle size, the coefficient of variation (cv), and the association ratio, and the dispersion stability of the silica sol is excellent. A time of the pressurized heat treatment is preferably 0.25 hours or more, and more preferably 0.5 hours or more, and is preferably 6 hours or less, and more preferably 4 hours or less. When the time of the pressurized heat treatment is 0.25 hours or more, the degree of condensation of the silica particles can be increased. When the time of the pressurized heat treatment is 6 hours or less, the silica particles can be produced without greatly changing the average primary particle size, the average secondary particle size, the coefficient of variation (cv), and the association ratio, and the dispersion stability of the silica sol is excellent. The pressurized heat treatment may be performed in air or in a solvent or a dispersion medium, and is preferably performed in a solvent or a dispersion medium since the dispersion stability of the silica sol is excellent, and is more preferably performed in an aqueous dispersion since the d value and the density of silanol groups on the surface can be precisely controlled without greatly changing the average primary particle size, the average secondary particle size, the coefficient of variation (cv), and the association ratio. The pressurized heat treatment may be performed immediately after the completion of the hydrolysis reaction and the condensation reaction, or may be performed after removing unnecessary components among the components in a reaction liquid after the hydrolysis reaction and the condensation reaction, and adding necessary components. The pressurized heat treatment is preferably performed after removing unnecessary components among the components in the reaction liquid after the hydrolysis reaction and the condensation reaction, and adding necessary components, and more preferably performed after removing an organic compound and adding water, since an operation pressure can be kept low. When the pressurized heat treatment is performed in an aqueous dispersion, a pH is preferably 6.0 or more, and more preferably 6.5 or more, and is preferably 8.0 or less, and more preferably 7.8 or less. In a case where the pH is 6.0 or more when the pressurized heat treatment is performed in an aqueous dispersion, gelation of the silica sol can be prevented. In a case where the pH is 8.0 or less when the pressurized heat treatment is performed in an aqueous dispersion, structural destruction due to dissolution is prevented, the d value and the density of silanol groups on the surface can be precisely controlled without greatly changing the average primary particle size, the average secondary particle size, the coefficient of variation (cv), and the association ratio, the aggregation of the silica particles can be suppressed, and the dispersion stability of the silica sol is excellent. Silica Sol The silica sol according to the present embodiment preferably contains the silica particles according to the present embodiment and a solvent or a dispersion medium. Examples of the solvent or dispersion medium of the silica sol include water, methanol, ethanol, propanol, isopropanol, ethylene glycol, etc. These solvents or dispersion media of the silica sol may be used alone or in combination of two or more kinds thereof. Among these solvents or dispersion media of the silica sol, water and alcohol are preferred, and water is more preferred due to excellent affinity with the silica particles. A content of the silica particles in the silica sol is preferably 3 mass % or more, more preferably 4 mass % or more, and still more preferably 5 mass % or more, and is preferably 50 mass % or less, more preferably 40 mass % or less, and still more preferably 30 mass % or less, with respect to a total amount of the silica sol. When the content of the silica particles in the silica sol is 3 mass % or more, the polishing rate for the object to be polished typified by a silicon wafer is excellent. When the content of the silica particles in the silica sol is 50 mass % or less, the aggregation of the silica particles in the silica sol or the polishing composition can be prevented, and the storage stability of the silica sol or the polishing composition is excellent. A content of the solvent or the dispersion medium in the silica sol is preferably 50 mass % or more, more preferably 60 mass % or more, and still more preferably 70 mass % or more, and is preferably 97 mass % or less, more preferably 96 mass % or less, and still more preferably 95 mass % or less, with respect to the total amount of the silica sol. When the content of the solvent or the dispersion medium in the silica sol is 50 mass % or more, the aggregation of the silica particles in the silica sol or the polishing composition can be prevented, and the storage stability of the silica sol or the polishing composition is excellent. When the content of the solvent and the dispersion medium in the silica sol is 97 mass % or less, the polishing rate for the object to be polished typified by a silicon wafer is excellent. The content of the silica particles, the solvent, or the dispersion medium in the silica sol can be set to a desired range by removing unnecessary components from the components in the reaction liquid after the completion of the hydrolysis reaction and the condensation reaction, and adding necessary components. The silica sol according to the present embodiment may contain, in addition to the silica particles and the solvent or the dispersion medium, other components such as an oxidizing agent, a preservative, an antifungal agent, a pH adjusting agent, a pH buffering agent, a surfactant, a chelating agent, and an antimicrobial and biocide, if necessary, as long as the performance of the silica sol is not impaired. In particular, it is preferable that the silica sol contains an antimicrobial and biocide due to the excellent storage stability. Examples of the antimicrobial and biocide include hydrogen peroxide, ammonia, quaternary ammonium hydroxide, quaternary ammonium salt, ethylenediamine, glutaraldehyde, methyl p-hydroxybenzoate, sodium chlorite, etc. These antimicrobial and biocides may be used alone or in combination of two or more kinds thereof. Among these antimicrobial and biocides, hydrogen peroxide is preferred due to the excellent affinity with the silica sol. The biocide include those generally referred to as bactericides. A content of the antimicrobial and biocide in the silica sol is preferably 0.0001 mass % or more, and more preferably 0.001 mass % or more, and is preferably 10 mass % or less, and more preferably 1 mass % or less, with respect to the total amount of the silica sol. When the content of the antimicrobial and biocide in the silica sol is 0.0001 mass % or more, the storage stability of the silica sol is excellent. When the content of the antimicrobial and biocide in the silica sol is 10 mass % or less, the original performance of the silica sol is not impaired. A pH of the silica sol is preferably 6.0 or more, and more preferably 6.5 or more, and is preferably 8.0 or less, and more preferably 7.8 or less. When the pH of the silica sol is 6.0 or more, long-term storage stability of the silica sol is excellent. When the pH of the silica sol is 8.0 or less, the aggregation of the silica particles can be prevented, and the dispersion stability of the silica sol is excellent. The pH of the silica sol can be set to a desired range by adding a pH adjusting agent. Method for Producing Silica Sol The silica sol according to the present embodiment may be produced by using a reaction solution after the completion of the hydrolysis reaction and the condensation reaction as it is, or by removing unnecessary components from the components in the reaction solution after the completion of the hydrolysis reaction and the condensation reaction, and adding necessary components. In production of the silica sol, a filtration step may be included in order to remove coarse particles or avoid aggregation due to fine particles. Examples of a filtration method include natural filtration under normal pressure, filtration under reduced pressure, filtration under pressure, centrifugal filtration, etc. Filtration may be performed at any timing and any number of times, but is preferably performed immediately before preparation of the polishing composition due to excellent storage stability and polishing characteristics of the polishing composition. Polishing Composition The polishing composition according to the present embodiment contains the silica sol according to the present embodiment, and preferably further contains a water-soluble polymer. The water-soluble polymer enhances wettability of the polishing composition with respect to the object to be polished typified by a silicon wafer. The water-soluble polymer is preferably a polymer having a functional group having high hydrophilicity, affinity between the functional group having high hydrophilicity and the silanol group in the surfaces of the silica particles is high, and the silica particles and the water-soluble polymer are stably dispersed in the vicinity in the polishing composition. Therefore, when the object to be polished typified by a silicon wafer is polished, the effects of the silica particles and the water-soluble polymer synergistically function. Examples of the water-soluble polymer include a cellulose derivative, polyvinyl alcohol, polyvinylpyrrolidone, a copolymer having a polyvinylpyrrolidone skeleton, a polymer having a polyoxyalkylene structure, etc. Examples of the cellulose derivative include hydroxyethyl cellulose, hydroxyethylcellulose which has been subjected to a hydrolysis treatment, hydroxypropylcellulose, hydroxyethylmethyl cellulose, hydroxypropylmethyl cellulose, methyl cellulose, ethyl cellulose, ethylhydroxyethyl cellulose, carboxymethyl cellulose, etc. Examples of the copolymer having a polyvinylpyrrolidone skeleton include graft copolymers of polyvinyl alcohol and polyvinylpyrrolidone, etc. Examples of the polymer having a polyoxyalkylene structure include polyoxyethylene, polyoxypropylene, a copolymer of ethylene oxide and propylene oxide, etc. These water-soluble polymers may be used alone or in combination of two or more kinds thereof. Among these water-soluble polymers, cellulose derivatives are preferred, and hydroxyethyl cellulose is more preferred, since the affinity with the silanol groups in the surfaces of the silica particles is high and good hydrophilicity to the surface of the object to be polished is imparted by acting synergistically. A mass average molecular weight of the water-soluble polymer is preferably 1000 or more, more preferably 5000 or more, and still more preferably 10000 or more, and is preferably 3000000 or less, more preferably 2000000 or less, and still more preferably 1000000 or less. When the mass average molecular weight of the water-soluble polymer is 1000 or more, hydrophilicity of the polishing composition is improved. When the mass average molecular weight of the water-soluble polymer is 3000000 or less, the affinity with the silica sol is excellent, and the polishing rate for the object to be polished typified by a silicon wafer is excellent. The mass average molecular weight of the water-soluble polymer is measured by size exclusion chromatography under conditions that a NaCl solution of 0.1 mol/L in terms of polyethylene oxide is used as a mobile phase. A content of the water-soluble polymer in the polishing composition is preferably 0.02 mass % or more, and more preferably 0.05 mass % or more, and is preferably 10 mass % or less, and more preferably 5 mass % or less, with respect to the total amount of the polishing composition. When the content of the water-soluble polymer in the polishing composition is 0.02 mass % or more, the hydrophilicity of the polishing composition is improved. When the content of the water-soluble polymer in the polishing composition is 10 mass % or less, the aggregation of the silica particles during preparation of the polishing composition can be prevented. The polishing composition according to the present embodiment may contain, in addition to the silica sol and the water-soluble polymer, other components such as a basic compound, a polishing accelerator, a surfactant, a hydrophilic compound, a preservative, an antifungal agent, a pH adjusting agent, a pH buffer, a surfactant, a chelating agent, and an antimicrobial and biocide, if necessary, as long as the performance of the polishing composition is not impaired. In particular, the basic compound is preferably contained in the polishing composition since chemical polishing (chemical etching) can be performed by imparting a chemical action to the surface of the object to be polished typified by a silicon wafer, and the polishing rate for the object to be polished typified by a silicon wafer can be improved by a synergistic effect with the silanol groups on the surfaces of the silica particles. Examples of the basic compound include an organic basic compound, an alkali metal hydroxide, an alkali metal hydrogen carbonate, an alkali metal carbonate, ammonia, etc. These basic compounds may be used alone or in combination of two or more kinds thereof. Among these basic compounds, ammonia, tetramethylammonium hydroxide, tetraethylammonium hydroxide, ammonium hydrogen carbonate, and ammonium carbonate are preferred, ammonia, tetramethylammonium hydroxide, and tetraethylammonium hydroxide are more preferred, and ammonia is still more preferred, since water solubility is high and affinity between the silica particles and the water-soluble polymers is excellent. A content of the basic compound in the polishing composition is preferably 0.001 mass % or more, and more preferably 0.01 mass % or more, and is preferably 5 mass % or less, and more preferably 3 mass % or less, with respect to the total amount of the polishing composition. When the content of the basic compound in the polishing composition is 0.001 mass % or more, the polishing rate for the object to be polished typified by a silicon wafer can be improved. When the content of the basic compound in the polishing composition is 5 mass % or less, the stability of the polishing composition is excellent. A pH of the polishing composition is preferably 8.0 or more, and more preferably 9.0 or more, and is preferably 12.0 or less, and more preferably 11.0 or less. When the pH of the polishing composition is 8.0 or more, the aggregation of the silica particles in the polishing composition can be prevented, and the dispersion stability of the polishing composition is excellent. When the pH of the polishing composition is 12.0 or less, dissolution of the silica particles can be prevented, and the stability of the polishing composition is excellent. The pH of the polishing composition can be set to a desired range by adding the pH adjusting agent. The polishing composition according to the present embodiment can be obtained by mixing the silica sol according to the present embodiment and, if necessary, a water-soluble polymer and other components. Considering storage and transportation, the polishing composition may be prepared at a high concentration once and diluted with water or the like immediately before polishing. Use The silica particles according to the present embodiment, the silica particles obtained by the production method according to the present embodiment, the silica sol according to the present embodiment, and the polishing composition according to the present embodiment can be suitably used for polishing applications, for example, can be used for polishing of a semiconductor material such as a silicon wafer, polishing of an electronic material such as a hard disk substrate, polishing (chemical mechanical polishing) in a planarization step in producing an integrated circuit, polishing of a synthetic quartz glass substrate used for a photomask or liquid crystal, polishing of a magnetic disk substrate, and the like, and among them, can be particularly suitably used for polishing of a silicon wafer or chemical mechanical polishing. Polishing Method A polishing method according to the present embodiment is preferably a method of polishing using the polishing composition according to the present embodiment. Specific examples of the polishing method include a method in which a surface of a silicon wafer is pressed against a polishing pad, the polishing composition according to the present embodiment is dropped onto the polishing pad, and the surface of the silicon wafer is polished. Method for Producing Semiconductor Wafer A method for producing a semiconductor wafer according to the present embodiment is a method including a step of polishing using the polishing composition according to the present embodiment, and a specific polishing method is as described above. Examples of the semiconductor wafer include a silicon wafer, a compound semiconductor wafer, etc. Method for Producing Semiconductor Device A method for producing a semiconductor device according to the present embodiment is a method including a step of polishing using the polishing composition according to the present embodiment, and a specific polishing method is as described above. EXAMPLES Hereinafter, the present invention will be described more specifically with reference to Examples. However, the present invention is not limited to the description of the following Examples as long as its gist is observed. Measurement of Average Primary Particle Size A silica sol containing silica particles obtained in Examples and Comparative Examples was freeze-dried, and a specific surface area of the silica particles was measured using an automatic specific surface area measurement device “FlowSorb II” (model name, manufactured by Shimadzu Corporation). Using the following formula (10) and setting a density to 2.2 g/cm3, an average primary particle size was calculated. Average primary particle size (nm)=6000/(specific surface area (m2/g)×density (g/cm3)) (10) Measurement of Average Secondary Particle Size and Coefficient of Variation For the silica sol containing the silica particles obtained in Examples and Comparative Examples, the average secondary particle size of the silica particles was measured using a dynamic light scattering particle size measuring device “Zetasizar Nano ZS” (model name, manufactured by Malvern Instruments Ltd.), and coefficient of variation (cv) was calculated using the following formula (11). cv=(standard deviation (nm)/average secondary particle size (nm))×100 (11) Calculation of Association Ratio An association ratio was calculated based on the measured average primary particle size and the average secondary particle size using the following formula (12). Association ratio=average secondary particle size/average primary particle size (12) Measurement of d Value Using an X-ray diffraction equipment (model name “RINT-Ultima III”, manufactured by Rigaku Corporation), the silica sol containing silica particles obtained in Examples and Comparative Examples was filled into a recessed portion of a non-reflective sample plate formed of silicon, and attached to the device. A copper X-ray tube having an output of 1.5 kW was applied at 40 kV and 30 mA. On an X-ray incident side, a multilayer mirror and a Soller slit having an opening angle of 5° were provided for collimating, compression, and monochromatization of X-rays, and on an X-ray receiving side, a long parallel slit having an opening angle of 0.114° and a scintillation counter were provided. The silica sol on the non-reflective sample plate is irradiated with a parallel beam of copper Kα1 line (wavelength λ of Kα1 line=1.5405 Å) at an irradiation angle of 0.1°, and 2θ scanning (20 range is from 5° to 50°) was performed to obtain an X-ray scattering pattern. A scattering angle 20 indicating a maximum intensity of the obtained halo pattern was recorded, the scattering vector q (q=4π·sin θ/λ) was calculated, and the d value was calculated by using the scattering vector q and the following formula (5) representing a Bragg's law (λ=2d·sin θ). d=2π/q(5) Measurement of Density of Silanol Groups on Surface An amount of the silica sol containing the silica particles obtained in Examples and Comparative Examples, corresponding to 1.5 g of the silica particles, was collected in a 200 mL tall beaker, and pure water was added thereto to adjust a liquid amount to 90 mL. A pH electrode was inserted into a tall beaker under an environment of 25°, and a test solution was stirred for 5 minutes by a magnetic stirrer. While stirring with the magnetic stirrer was continued, a hydrochloric acid aqueous solution of 0.1 mol/L was added until a pH reached 3.6. The pH electrode was removed from the tall beaker, 30 g of sodium chloride was added in a state in which stirring with the magnetic stirrer was continued, and the sodium chloride was completely dissolved with gradually adding pure water. Pure water was added until a total amount of the test solution finally reached 150 mL, and the test solution was stirred for 5 minutes by the magnetic stirrer to obtain a test solution. The tall beaker containing the obtained test solution was set in an automatic titration device “COM-1600” (manufactured by Hiranuma Sangyo Co., Ltd.), and the pH electrode and a burette attached to the device were inserted into the tall beaker. While the test solution was stirred with the magnetic stirrer, a sodium hydroxide aqueous solution of 0.1 mol/L was added dropwise through a burette, and a titration amount A (mL) of the sodium hydroxide aqueous solution of 0.1 mol/L required for the pH to be changed from 4.0 to 9.0 was measured. A consumption amount V (mL) of the sodium hydroxide aqueous solution of 0.1 mol/L required for the pH to be changed from 4.0 to 9.0 per 1.5 g of the silica particles was calculated using the following formula (6), and a density p (number/nm2) of silanol groups on the surfaces of the silica particles was calculated using the following formula (7). V=(A×f×100×1.5)/(W×C) (6)A: titration amount (mL) of sodium hydroxide aqueous solution of 0.1 mol/L required for pH to be changed from 4.0 to 9.0 per 1.5 g of silica particlesf: titer of used sodium hydroxide aqueous solution of 0.1 mol/LC: concentration (mass %) of silica particles in silica solW: collection amount (g) of silica sol ρ=(B×NA)/(1018×M×SBET) (7)B: sodium hydroxide amount (mol) required for pH to be changed from 4.0 to 9.0 per 1.5 g of silica particles calculated based on VNA: Avogadro number (number/mol)M: silica particle amount (1.5 g)SBET: specific surface area (m2/g) of silica particles measured at time of calculation of average primary particle size Measurement of Content of Metal Impurity A silica sol containing 0.4 g of silica particles obtained in Comparative Example 1 was accurately weighed, sulfuric acid and hydrofluoric acid were added thereto, the mixture was heated, dissolved, and evaporated, pure water was added to the remaining sulfuric acid droplets so that a total amount is accurately 10 g to prepare a test solution, and a content of metal impurity was measured using a high frequency inductively coupled plasma mass spectrometer “ELEMENT 2” (model name, manufactured by Thermo Fisher Scientific Inc.). The content of the metal impurity in the silica particles was 1.1 ppm for sodium, 0.140 ppm for potassium, 0.015 ppm for iron, 0.135 ppm for aluminum, 0.075 ppm for calcium, 0.07 ppm for zinc, and less than 0.005 ppm for all of magnesium, cobalt, chromium, copper, manganese, lead, titanium, silver, and nickel. From this, it is considered that the content of the metal impurity in each of the silica particles of Examples 1 to 7 and Comparative Examples 2 and 3 is 5 ppm or less. Storage Stability With respect to the silica particles obtained in Examples and Comparative Examples, after a lapse of one year from the purchase or production, the presence or absence of precipitation of the silica particles was confirmed with a naked eye, and the storage stability was evaluated. When the precipitated silica particles were not observed with the naked eye, the storage stability was determined to be good and indicated by “A” in a table. When there are both of a case where precipitated silica particles are confirmed and a case where precipitated silica particles are not confirmed, it is determined that the storage stability is medium, and the result was shown as “B” in the table. A case where a large amount of silica particles settle out is indicated by “C” in the table as having no storage stability. Comparative Example 1 Tetramethoxysilane and methanol were mixed at a volume ratio of 3:1 to prepare a raw material solution. A reaction solvent in which methanol, pure water, and ammonia were mixed in advance was charged into a reaction tank equipped with a thermometer, a stirrer, a supply pipe, and a distillation line. A concentration of water in the reaction solvent was 15 mass %, and a concentration of ammonia in the reaction solvent was 1 mass %. With maintaining a temperature of the reaction solvent at 20° C., the reaction solvent and a raw material solution were set to 9.2:1 (volume ratio), and the raw material solution was added dropwise to the reaction tank for 25 minutes at a uniform rate to obtain a silica sol. The obtained silica sol was subjected to removal of methanol and ammonia by increasing the temperature with adjusting the liquid amount by adding pure water so that the content of silica particles was about 20 mass %, thereby obtaining a silica sol having a content of silica particles of about 20 mass %. The evaluation results of the obtained silica particles are shown in Table 1. Examples 1 to 7 and Comparative Example 2 and 3 A silica sol obtained in Comparative Example 1 was subjected to a pressurized heat treatment under conditions shown in Table 1 to obtain a silica sol having a content of silica particles of about 20 mass %. The evaluation results of the silica particles contained in the obtained silica sol are shown in Table 1. In the table, “-” representing physical properties of particles of Comparative Examples 2 and 3 means that measurement was not possible due to significant particle aggregation. Comparative Example 4 A commercially available silica sol (trade name “PL-3”, manufactured by Fuso Chemical Co., Ltd.) was used as it was. The evaluation results of the silica particles contained in the silica sol are shown in Table 1. TABLE 1Physical properties of particlesDensity(x)Coef-[number/ficientnm2] ofAverageAverageofAs-Evalua-Pressurized heatdsilanolprimarysecondaryvari-so-tion ontreatment conditionsvaluegroupsparticleparticleationcia-resultTemperaturePressureTime(y)on−0.2x +−0.2x +sizesize(cv)tionStorage[° C.][MPa][hour]pH[Å]surface5.47.0[nm][nm](%)ratiostabilityExample 11200.2017.54.776.84.045.6435.865.229.81.8AExample 21400.3617.54.616.54.15.736.663.426.41.7AExample 31600.6217.54.775.34.345.9437.361.926.71.7AExample 41801.0017.54.881.85.046.6438.460.926.81.6AExample 52001.5617.54.851.75.066.6638.861.225.01.7AExample 62001.5637.54.741.75.066.6639.661.624.71.6AExample 72001.5657.55.471.65.086.6837.063.126.71.6AComparative————4.077.43.925.5234.966.126.51.9AExample 1Comparative1600.62111.2————————CExample 2Comparative1600.6213.0————————CExample 3Comparative————4.105.54.35.936.171.228.62.0BExample 4 As can be seen from Table 1, in contrast to Comparative Example 1 in which the pressurized heat treatment was not performed or Comparative Example 4 in which it is unknown whether the pressurized heat treatment was performed, the silica particles in the silica sol obtained in Examples 1 to 7 in which the pressurized heat treatment was performed had almost no change in an average primary particle size, an average secondary particle size, coefficient of variation (cv), and an association ratio, a d value was improved, and formula (1) was established. Establishment of formula (1) represents formation of a large membered ring than the commercially available silica particles as in Comparative Example 4, and means that formation of the membered ring by sharing oxygen of a SiO4tetrahedron is promoted and the number of defects of the silica particles is small. This means that the number of four-membered rings is small, so that it is expected that the mechanical strength of the silica particles is excellent, the polishing characteristics of the polishing composition are excellent since the strain is small and elastic deformation is difficult. Since the pressurized heat treatment is performed, it is considered that a content of an alkoxy group or a silanol group is reduced, and it is expected that the number of reactive sites is small and the storage stability of the silica sol is excellent. Since it is generally considered that a true specific gravity of a silica mineral is decreased as the d value is increased, it is expected that the silica particles are stable and hardly precipitated. In Comparative Example 2 in which the treatment was performed under alkaline conditions and Comparative Example 3 in which the treatment was performed under acidic conditions, although the pressure heat treatment was performed, the silica particles were significantly aggregated, a large amount of the silica particles were precipitated, and the d value and the density of silanol groups on the surface could not be measured. In Comparative Example 4, which is a commercially available silica sol, there were observed a case where precipitation of silica particles occurred and a case where the precipitation of silica particles did not occur, and the storage stability was moderate. In Comparative Example 1 in which the pressurized heat treatment was not performed, although the precipitated silica particles were not confirmed with the naked eye in the current evaluation, it is considered that a content of alkoxy group or silanol group is larger than those in Examples 1 to 7, and it is considered that the number of reactive sites is large, and the precipitation of the silica particles occurs in the case of further long-term storage. Furthermore, in Comparative Example 1 and Comparative Example 4, the d value was low, and formula (1) was not established. When the formula (1) is not established, it is considered that a large membered ring is not formed, formation of the membered ring by sharing oxygen of a SiO4tetrahedron is not promoted, and the number of defects of the silica particles is large. Since this means that the number of four-membered rings is large, it is expected that the mechanical strength of the silica particles is inferior and the polishing characteristics of the polishing composition are inferior due to a large strain and easy elastic deformation. Although the present invention has been described in detail with reference to the specific embodiments, it is obvious to those skilled in the art that various changes and modifications may be made without departing from the gist and the scope of the present invention. This application is based on Japanese Patent Application No. 2019-029142 filed on Feb. 21, 2019 and Japanese Patent Application No. 2019-029143 filed on Feb. 21, 2019, and the contents of which are incorporated herein by reference. INDUSTRIAL APPLICABILITY The silica particles according to the present invention, the silica particles obtained by the production method according to the present invention, the silica sol according to the present invention, and the polishing composition according to the present invention can be suitably used for polishing applications, for example, can be used for polishing of a semiconductor material such as a silicon wafer, polishing of an electronic material such as a hard disk substrate, polishing (chemical mechanical polishing) in a planarization step in producing an integrated circuit, polishing of a synthetic quartz glass substrate used for a photomask or liquid crystal, polishing of a magnetic disk substrate, and the like, and among them, can be particularly suitably used for polishing of a silicon wafer or chemical mechanical polishing. | 56,749 |
11862471 | DETAILED DESCRIPTION A manufacturing method for a semiconductor device according to an embodiment includes: performing first etching for forming a recess in a layer to be processed using a reactive ion etching method; performing a first treatment of supplying a silylation agent to the recess after the performing the first etching; and performing second etching of etching a bottom surface of the recess using a reactive ion etching method after the performing the first treatment. Embodiments of the present invention will be described below with reference to the drawings. In the following description, the identical or similar members are given the identical reference numerals, and description of the members once described will sometimes be omitted as appropriate. In the present description, the term “up” or “down” is sometimes used for convenience. The term “up” or “down” is, for example, a term indicating a relative positional relationship in the drawings. The term “up” or “down” is not a term defining a positional relationship with respect to gravity. Qualitative analysis and quantitative analysis of the chemical composition of the members constituting the semiconductor device in the present description can be carried out by, for example, secondary ion mass spectrometry (SIMS) and energy dispersive X-ray spectroscopy (EDX). In addition, for measuring the thickness of the members constituting the semiconductor device and the distance between the members, for example, a transmission electron microscope (TEM) or a scanning electron microscope (SEM). The manufacturing method for a semiconductor device according to an embodiment will be described below with reference to the drawings. First Embodiment A manufacturing method for a semiconductor device according to a first embodiment includes: performing first etching for forming a recess in a layer to be processed using a reactive ion etching method; performing a first treatment of supplying a silylation agent to the recess after the performing the first etching; and performing second etching of etching a bottom surface of the recess using a reactive ion etching method after the performing the first treatment. FIG.1is a schematic cross-sectional view of a semiconductor device manufactured by the manufacturing method for a semiconductor device according to the first embodiment. The semiconductor device manufactured by the manufacturing method for a semiconductor device according to the first embodiment is a nonvolatile memory100in which memory cells are three-dimensionally disposed.FIG.1is a cross-sectional view of a memory cell array of the nonvolatile memory100. The nonvolatile memory100includes a silicon substrate10, a channel layer11, a plurality of interlayer insulating layers12, a gate insulating layer13, a plurality of word lines WL, and a plurality of bit lines BL. The nonvolatile memory100includes a plurality of three-dimensionally disposed memory cells MC. The region enclosed by a dotted line inFIG.1corresponds to one of the memory cells MC. The channel layer11extends in the normal direction of the surface of the silicon substrate10. The channel layer11is electrically connected to the silicon substrate10. The channel layer11functions as a channel region of a transistor of the memory cell MC. The channel layer11is a semiconductor. The channel layer11is, for example, polycrystalline silicon. The word lines WL are stacked in the normal direction of the surface of the silicon substrate10. The word line WL functions as a gate electrode of a transistor of the memory cell MC. The word line WL is, for example, a plate-like conductor. The word line WL is tungsten (W), for example. The channel layer11penetrates the plurality of word lines WL. The interlayer insulating layer12is provided between the word line WL and the word line WL. The interlayer insulating layer12electrically separates the word line WL from the word line WL. The bit line BL extends in a direction parallel to the surface of the silicon substrate10. The bit line BL is electrically connected to the channel layer11. The gate insulating layer13is provided between the channel layer11and the word line WL. The gate insulating layer13includes, for example, a tunnel insulating film, a charge storage film, and a block insulating film that are not illustrated. The tunnel insulating film is a silicon oxide film, for example. The charge storage film is a silicon nitride film, for example. The block insulating film is an aluminum oxide film, for example. The memory cell MC stores data by the charge stored in the charge storage film of the gate insulating layer13. The threshold voltage of the transistor of the memory cell MC varies depending on the amount of the charge stored in the charge storage film. Data stored in the memory cell MC is read by monitoring the current flowing between the word line WL and the bit line BL, which varies depending on the threshold voltage of the transistor. FIG.2is a schematic view of an example of the reactive ion etching device used in the manufacturing method for a semiconductor device according to the first embodiment. The reactive ion etching device (RIE device) inFIG.2is a two-frequency capacitively coupled plasma device (CCP device). The RIE device includes, for example, a chamber20, a holder22, a first high-frequency power source24, a second high-frequency power source26, a first gas supply port30a, a second gas supply port30b, and a third gas supply port30c. The holder22is provided in the chamber20. The holder22mounts a semiconductor substrate W, for example. The holder22is, for example, an electrostatic chuck. The first high-frequency power source24has a function of applying high-frequency power to the chamber20. Plasma is generated in the chamber20by the first high-frequency power source24. The high-frequency power applied by the first high-frequency power source24is, for example, equal to or more than 50 W and equal to or less than 5000 W. The frequency applied by the first high-frequency power source24is, for example, equal to or more than 20 MHz and equal to or less than 200 MHz. The second high-frequency power source26has a function of applying high-frequency power to the holder22. By applying high-frequency power to the holder22, the energy of ions colliding with the semiconductor substrate W is controlled. The high-frequency power applied to the holder22is, for example, equal to or more than 100 W and equal to or less than 10000 W. The frequency applied to the holder22is lower than the frequency applied to the chamber20by the first high-frequency power source24. The frequency applied to the holder22is, for example, equal to or more than 0.1 MHz and equal to or less than 10 MHz. The semiconductor substrate W is anisotropically etched using plasma generated in the chamber20. Next, an example of the manufacturing method of the semiconductor device according to the first embodiment will be described. FIGS.3A to3D,4A to4D,5A to5D, and6A to6Care schematic views showing the manufacturing method for a semiconductor device of the first embodiment.FIGS.3A to6Ccorrespond to a portion including one channel layer11inFIG.1. First, a stacked body40is formed on the silicon substrate10(FIG.3A). The stacked body40is an insulating layer. The stacked body40is an example of the layer to be processed. The stacked body40includes a structure in which silicon oxide films40aand silicon nitride films40bare alternately stacked. The silicon oxide film40ais an example of a first film. The silicon nitride film40bis an example of a second film. The silicon oxide film40aand the silicon nitride film40bare formed by, for example, the chemical vapor deposition method (CVD method). The interlayer insulating layer12eventually replaces a part of the silicon oxide film40a. Next, a carbon layer42having a hole pattern42ais formed on the stacked body40(FIG.3B). The carbon layer42is an example of a mask layer. The carbon layer42is formed by, for example, a sputtering method. The hole pattern42ais formed using, for example, the lithography method and the RIE method. As the mask layer, for example, a resist layer, an insulating layer, or a metal layer can also be used. Next, the silicon substrate10is introduced into the chamber20of a RIE device. In the chamber20of the RIE device, the first etching is performed using the carbon layer42as a mask. A memory hole MH is formed in the stacked body40by the first etching (FIG.3C). The memory hole MH is an example of the recess. In the first etching, the memory hole MH does not penetrate the stacked body40. In the first etching, the etching is stopped in the middle of the stacked body40. The first etching amount of the stacked body40in the first etching is indicated by E1inFIG.3C. In the first etching, the first etching gas is supplied from the first gas supply port30ainto the chamber20, for example. The first etching is performed using the first etching gas. Next, the first treatment of supplying trimethylsilyldimethylamine (TMSDMA) to the memory hole MH is performed (FIG.3D). Trimethylsilyldimethylamine is an example of the silylation agent. The first treatment is performed using the RIE device, for example. The first treatment is performed in the chamber20identical to that for the first etching, for example. For example, after the first etching is performed, the first etching and the first treatment are continuously performed without releasing the silicon substrate10into the atmosphere. The first treatment is performed by, for example, supplying TMSDMA into the chamber20from the second gas supply port30bof the RIE device. In the first treatment, TMSDMA is supplied as a gas to the memory hole MH. By the first treatment, a protective film44ais formed on a sidewall of the memory hole MH. The protective film44acontains carbon. Next, in the chamber20of the RIE device, the second etching is performed using the carbon layer42as a mask. At least a bottom surface of the memory hole MH is etched by the second etching (FIG.4A). The memory hole MH becomes further deeper than that immediately after the first etching. In the second etching, the memory hole MH does not penetrate the stacked body40. In the second etching, the etching is stopped in the middle of the stacked body40. The second etching amount of the stacked body40in the second etching is indicated by E2inFIG.4A. For example, the first etching amount E1of the stacked body40in the first etching is larger than the second etching amount E2of the stacked body40in the second etching. The first etching amount E1may be equal to or smaller than the second etching amount E2. In the second etching, the second etching gas is supplied from the first gas supply port30ainto the chamber20, for example. The second etching is performed using the second etching gas. Next, a second treatment of supplying TMSDMA to the memory hole MH is performed (FIG.4B). TMSDMA is an example of the silylation agent. The second treatment is performed using the RIE device, for example. The second treatment is performed in the chamber20identical to that for the second etching, for example. For example, after the second etching is performed, the second etching and the second treatment are continuously performed without releasing the silicon substrate10into the atmosphere. The second treatment is performed by supplying TMSDMA into the chamber20from the second gas supply port30bof the RIE device. TMSDMA is supplied as a gas to the memory hole MH. By the second treatment, a protective film44bis formed on the sidewall of the memory hole MH. The protective film44bcontains carbon. Next, in the chamber20of the RIE device, third etching is performed using the carbon layer42as a mask. At least a bottom surface of the memory hole MH is etched by the third etching (FIG.4C). The memory hole MH becomes further deeper than that immediately after the second etching. In the third etching, the memory hole MH does not penetrate the stacked body40. In the third etching, the etching is stopped in the middle of the stacked body40. In the third etching, the third etching gas is supplied from the first gas supply port30ainto the chamber20, for example. The third etching is performed using the third etching gas. Next, a third treatment of supplying TMSDMA to the memory hole MH is performed (FIG.4D). TMSDMA is an example of the silylation agent. The third treatment is performed using the RIE device, for example. The third treatment is performed in the chamber20identical to that for the third etching, for example. For example, after the third etching is performed, the third etching and the third treatment are continuously performed without releasing the silicon substrate10into the atmosphere. The third treatment is performed by, for example, supplying TMSDMA into the chamber20from the second gas supply port30bof the RIE device. TMSDMA is supplied as a gas to the memory hole MH. By the third treatment, a protective film44cis formed on the sidewall of the memory hole MH. The protective film44ccontains carbon. Next, in the chamber20of the RIE device, fourth etching is performed using the carbon layer42as a mask. At least a bottom surface of the memory hole MH is etched by the fourth etching (FIG.5A). The memory hole MH becomes further deeper than that immediately after the third etching. In the fourth etching, the memory hole MH penetrates the stacked body40and reaches the silicon substrate10. In the fourth etching, the fourth etching gas is supplied from the first gas supply port30ainto the chamber20, for example. The fourth etching is performed using the fourth etching gas. The aspect ratio of the memory hole MH penetrating the stacked body40is equal to or more than30, for example. After the fourth etching, the silicon substrate10is taken out from the chamber20of the RIE device. The first etching gas, the second etching gas, the third etching gas, and the fourth etching gas contain, for example, carbon and fluorine. The first etching gas, the second etching gas, the third etching gas, and the fourth etching gas contain, for example, oxygen. The first etching gas, the second etching gas, the third etching gas, and the fourth etching gas contain, for example, hydrogen. The first etching gas, the second etching gas, the third etching gas, and the fourth etching gas contain, for example, CxHyFz (x is an integer of equal to or more than 1, y is an integer of equal to or more than 0, and z is an integer of equal to or more than 1). The first etching gas, the second etching gas, the third etching gas, and the fourth etching gas contain, for example, C4F6, C4F8, and CH2F2. The first etching gas, the second etching gas, the third etching gas, and the fourth etching gas contain, for example, oxygen gas. The first etching gas, the second etching gas, the third etching gas, and the fourth etching gas are, for example, mixed gases of C4F6, C4F8, and CH2F2, and oxygen gas. The first etching gas, the second etching gas, the third etching gas, and the fourth etching gas are, for example, the identical gas. For example, at least one of the first etching gas, the second etching gas, the third etching gas, and the fourth etching gas is different from the other gases. The silylation agent is a chemical that realizes silylation. Silylation means substituting active hydrogen on the substance with a trisubstituted silyl group (—SiR3). The silylation agent contains silicon. The silylation agent contains, for example, carbon and hydrogen. The silylation agent contains, for example, a methyl group, an alkyl group, or a phenyl group. The silylation agent contains, for example, an amino group. The silylation agent has, for example, a structure of (R3)—Si—N(R2). The silylation agent is, for example, trimethylsilyldimethylamine (TMSDMA), bistertiarybutylaminosilane (BTBAS), bis(dimethylamino)dimethylsilane (BDMADMS), or phenyldimethylsilyldimethylamine. The silylation agent contains, for example, a methoxy group. The silylation agent has, for example, a structure of R—Si—(O(Me))x. The silylation agent has, for example, a structure of CH3—(CH2)z-Si—(O-Me)3. The silylation agent is, for example, trimethylmethoxysilane (TMSOME), dimethylmethoxysilane (DMDMS), methyltrimethoxysilane (MTMS), or methoxydimethylphenylsilane. The silylation agents used in the first treatment, the second treatment, and the third treatment are identical, for example. Moreover, in the silylation agents used in the first treatment, the second treatment, and the third treatment, for example, the silylation agent used in at least one treatment is different from the silylation agents used in the other treatments. Next, the carbon layer42, the protective film44a, the protective film44b, and the protective film44care removed (FIG.5B). The removal of the carbon layer42, the protective film44a, the protective film44b, and the protective film44cis performed using, for example, a different device or a different condition from that for the first to fourth etching. The removal of the carbon layer42, the protective film44a, the protective film44b, and the protective film44cis performed using, for example, a different gas from that for the first to fourth etching. The removal of the carbon layer42, the protective film44a, the protective film44b, and the protective film44cis performed by, for example, asking treatment using oxygen plasma. Next, a stacked insulating layer46is formed in the memory hole MH (FIG.5C). The stacked insulating layer46has a stacked structure of a silicon oxide film, a silicon nitride film, and an aluminum oxide film, for example. The stacked insulating layer46eventually becomes the gate insulating layer13. Next, a polycrystalline silicon layer48is formed in the memory hole MH (FIG.5D). The polycrystalline silicon layer48eventually becomes the channel layer11. Next, the silicon nitride film40bis selectively removed (FIG.6A). Next, a first tungsten layer50is formed in the region from which the silicon nitride film40bhas been removed (FIG.6B). The first tungsten layer50eventually becomes the word line WL. Next, a second tungsten layer52is formed on the polycrystalline silicon layer48(FIG.6C). The second tungsten layer52eventually becomes the bit line BL. The nonvolatile memory100shown inFIG.1is manufactured by the above manufacturing method. Next, functions and effects of the semiconductor device and the manufacturing method of the semiconductor device of the first embodiment will be described. In the nonvolatile memory100in which the memory cells are three-dimensionally disposed, in order to increase the capacity of the memory, for example, the hole diameter of the memory hole is reduced and the number of stacked word lines WL is increased. When the hole diameter of the memory hole is reduced and the number of stacked word lines WL is increased, it is necessary to form a memory hole having a high aspect ratio (depth of memory hole/hole diameter of memory hole). An increase in the aspect ratio of the memory hole causes a problem that the memory hole has a bowing shape. The bowing shape of the memory hole is caused by the hole diameter widening in the middle of etching for forming the memory hole. As a cause of the hole diameter widening in the middle of etching, it is conceivable that a part of the protective film formed on the sidewall of the memory hole disappears during etching. In etching of the memory hole, a substance derived from the plasma etching gas adheres to the sidewall, and a protective film is formed on the sidewall. Forming the protective film on the sidewall of the memory hole prevents etching of the sidewall, and suppresses the hole diameter from widening. When the protective film on the sidewall of the memory hole disappears, etching of the sidewall of the memory hole progresses, and the hole diameter of the memory hole widens. The protective film formed on the sidewall of the memory hole is, for example, a fluorocarbon film containing carbon and fluorine. The thickness of the protective film formed on the sidewall of the memory hole is determined by the balance between the amount of the substance adhering to the sidewall and the etching amount of the substance adhering to the sidewall. For example, on the sidewall of a shallow portion of the memory hole, the plasma etching gas easily reaches, and the amount of the substance adhering to the sidewall increases. On the other hand, in the shallow portion of the memory hole, the amount of obliquely incident ions is large, and the time of being exposed to etching becomes long. For this reason, the etching amount of the substance adhering to the sidewall also increases. There is a risk that the etching amount exceeds the amount of the substance adhering to the sidewall, the protective film on the sidewall disappears, and the hole diameter of the memory hole widens. For example, on the sidewall of a deep portion of the memory hole, the plasma etching gas hardly reaches, and the amount of the substance adhering to the sidewall decreases. Therefore, when the etching amount exceeds the amount of the substance adhering to the sidewall, there is a risk that the protective film on the sidewall disappears and the hole diameter of the memory hole widens. In the manufacturing method for a semiconductor device according to the first embodiment, when the memory hole MH is formed, etching of the stacked body40, which is a layer to be processed, and treatment using the silylation agent are alternately performed. By the treatment using the silylation agent, the protective film is formed on the sidewall of the memory hole. By the treatment using the silylation agent, a new protective film is formed also in a portion where the protective film formed at the time of etching disappears. Therefore, it is considered that the shape of the memory hole can be suppressed from becoming a bowing shape. FIGS.7A to7Care explanatory views of the function of the manufacturing method for a semiconductor device of the first embodiment. As shown inFIG.7A, a hydroxyl group (—OH) exists on the surfaces of the silicon oxide film40aand the silicon nitride film40bexposed on the sidewall of the memory hole MH. As shown inFIG.7B, in the manufacturing method for the nonvolatile memory100of the first embodiment, TMSDMA, which is a silylation agent, is supplied to the surface of the sidewall of the memory hole MH in the first treatment, the second treatment, and the third treatment. As shown inFIG.7C, the Si—N bond of TMSDMA supplied to the surface of the sidewall of the memory hole MH is broken, and a trimethylsilyl group is bonded to the surface of the sidewall. The trimethylsilyl group is bonded to the surface of the sidewall of the memory hole MH by a silylation reaction. The protective film44a, the protective film44b, and the protective film44cformed by the first treatment, the second treatment, and the third treatment include, for example, trimethylsilyl groups formed by the silylation reaction. The silylation reaction is highly reactive and easily occurs even at a low temperature. For the silylation reaction, it is not necessary to bring the material into plasma and form ions and radicals. Since the silylation reaction is highly reactive, the protective film is easily formed even in the deep portion of the memory hole MH. When the surface of the sidewall is completely covered with the trimethylsilyl group, the silylation reaction ends. Therefore, the formation of the protective film is a self-limiting process. Therefore, it is considered that the protective film44a, the protective film44b, and the protective film44cformed on the sidewall by the first treatment, the second treatment, and the third treatment are formed to have uniform thicknesses. It is considered that formation of the protective film44a, the protective film44b, and the protective film44csuppresses etching of the sidewall, and can suppress the shape of the memory hole MH from becoming a bowing shape. In the manufacturing method for the nonvolatile memory100of the first embodiment, the first etching, the first treatment, the second etching, the second treatment, the third etching, the third treatment, and the fourth etching are continuously performed in the identical chamber20of the identical RIE device. Therefore, the manufacturing time of the nonvolatile memory100is shortened, and an increase in the manufacturing cost of the nonvolatile memory100can be suppressed. The first to fourth etching gases preferably contain oxygen. The first to fourth etching gases preferably contain oxygen gas. When oxygen or oxygen gas is contained in the first to fourth etching gases, the surface of the silicon nitride film40bon the sidewall of the memory hole MH is oxidized. Therefore, the surface state of the silicon oxide film40aexposed to the sidewall resembles the surface state of the silicon nitride film40b. Therefore, the silylation reaction on the surface of the silicon oxide film40aand the silylation reaction on the surface of the silicon nitride film40bprogress similarly. Therefore, the protective film44a, the protective film44b, and the protective film44cbecome uniform films. Hence, the silicon nitride film40bon the sidewall is suppressed from being selectively etched with respect to the silicon oxide film40aon the sidewall. The first to fourth etching gases preferably contain hydrogen. When the first to fourth etching gases contain hydrogen, the etching rate of the silicon nitride film40bincreases. Therefore, the etching time of the first to fourth etching can be shortened. The first etching amount E1of the stacked body40in the first etching is preferably larger than the second etching amount E2of the stacked body40in the second etching. If the silylation reaction in the deep portion of the memory hole MH is suppressed, there is a risk that the protective film44bin the deep portion of the memory hole MH becomes thin. By making the second etching amount E2smaller than the first etching amount E1, etching of the sidewall in the second etching is suppressed. This can suppress the shape of the memory hole MH from becoming a bowing shape. The first etching amount E1may be equal to or smaller than the second etching amount E2. In the first to fourth etching, the high-frequency power applied to the holder22on which the stacked body40is mounted is preferably equal to or more than 500 W, more preferably equal to or more than 750 W, and yet more preferably equal to or more than 1000 W. As the high-frequency power applied to the holder22becomes high, the energy of ions colliding with the stacked body40in the first to fourth etching becomes high. Therefore, it becomes easy to form the memory hole MH having a high aspect ratio. As described above, according to the manufacturing method for a semiconductor device of the first embodiment, it is possible to suppress the shape of the memory hole from becoming a bowing shape, and to form the memory hole with high process accuracy. Second Embodiment The manufacturing method for a semiconductor device of the second embodiment is different from the manufacturing method of the first embodiment in that the first to third treatments are performed by a device different from the RIE device that performs the first to fourth etching processes. Hereinafter, part of description of the contents overlapping the first embodiment may be omitted. In the manufacturing method for a semiconductor device of the second embodiment, the first to third treatments are performed using a wet etching device. For example, after the first etching shown inFIG.3C, the silicon substrate10is taken out from the chamber20of the RIE device. Next, the first treatment is performed using the wet etching device. For example, TMSDMA is applied to the surface of the silicon substrate10. For example, the silicon substrate10is immersed in TMSDMA. In the first treatment, TMSDMA is supplied as a liquid to the memory hole MH. After the first treatment, the silicon substrate10is introduced into the chamber20of the RIE device, and the second etching is performed. Thereafter, the second treatment is performed using the wet etching device, the third etching is performed using the RIE device, the third treatment is performed using the wet etching device, and the fourth etching is performed using the RIE device. As described above, according to the manufacturing method for a semiconductor device of the second embodiment, similarly to the first embodiment, it is possible to suppress the shape of the memory hole from becoming a bowing shape, and to form the memory hole with high process accuracy. Third Embodiment The manufacturing method for a semiconductor device of the third embodiment is different from the manufacturing method of the first or second embodiment in that the treatment time of the first treatment and the treatment time of the second treatment are different. Hereinafter, part of description of the contents overlapping the first or second embodiment may be omitted. In the manufacturing method for a semiconductor device of the third embodiment, for example, the treatment time of the second treatment is longer than the treatment time of the first treatment. The treatment time of the second treatment of forming the protective film44bin the deep portion of the memory hole MH is made longer than the treatment time of the first treatment. By lengthening the treatment time of the second treatment, for example, the uniformity of the protective film44bis improved. In the manufacturing method for a semiconductor device of the third embodiment, for example, the treatment time of the second treatment is shorter than the treatment time of the first treatment. In the deep portion of the memory hole MH, the memory hole diameter sometimes becomes small due to a forward tapered shape of the memory hole MH. By shortening the treatment time of the second treatment, the protective film44battached to a portion having a small memory hole diameter is thinned. By thinning the protective film44b, for example, it is possible to suppress reduction in the etching rate of the stacked body40in the third etching. As described above, according to the manufacturing method for a semiconductor device of the third embodiment, similarly to the first or second embodiment, it is possible to suppress the shape of the memory hole from becoming a bowing shape, and to form the memory hole with high process accuracy. Fourth Embodiment The manufacturing method for a semiconductor device of the fourth embodiment is different from the manufacturing method of the first embodiment in that water is supplied to the recess after the first etching before the first treatment. Hereinafter, part of description of the contents overlapping the first embodiment may be omitted. In the manufacturing method for a semiconductor device of the fourth embodiment, for example, water is supplied to the memory hole MH formed in the stacked body40after the first etching before the first treatment. For example, after the first etching shown inFIG.3C, water is supplied from the third gas supply port30cinto the chamber20. Water is supplied as a gas into the chamber20. Water vapor is supplied into the chamber20. Next, the first treatment shown inFIG.3Dis performed. By supplying water to the memory hole MH after the first etching, for example, the area density and uniformity of the hydroxyl group (—OH) on the surface of the sidewall of the memory hole MH are increased. Therefore, the formation of the protective film44ain the first treatment is promoted. Therefore, for example, the uniformity of the protective film44ais improved. Furthermore, for example, the treatment time of the first treatment can be shortened. For example, water may be supplied to the memory holes MH formed in the stacked body40between the second etching and the second treatment and between the third etching and the third treatment. As described above, according to the manufacturing method for a semiconductor device of the fourth embodiment, similarly to the first embodiment, it is possible to suppress the shape of the memory hole from becoming a bowing shape, and to form the memory hole with high process accuracy. Fifth Embodiment The manufacturing method for a semiconductor device of the fifth embodiment is different from the manufacturing method of the first embodiment in that oxygen is supplied to the recess after the first etching before the first treatment. Hereinafter, part of description of the contents overlapping the first embodiment may be omitted. In the manufacturing method for a semiconductor device of the fifth embodiment, for example, oxygen is supplied to the memory hole MH formed in the stacked body40after the first etching before the first treatment. For example, after the first etching shown inFIG.3C, oxygen gas is supplied from the third gas supply port30cinto the chamber20. High-frequency power is applied, and the oxygen gas becomes oxygen plasma in the chamber20. Next, the first treatment shown inFIG.3Dis performed. After the first etching, by supplying oxygen plasma to the memory hole MH, for example, oxidation of the surface of the silicon nitride film40bon the sidewall of the memory hole MH progresses. Therefore, the surface state of the silicon oxide film40aexposed to the sidewall resembles the surface state of the silicon nitride film40b. Therefore, the silylation reaction on the surface of the silicon oxide film40ain the first treatment and the silylation reaction on the surface of the silicon nitride film40bprogress similarly. Therefore, the uniformity of the protective film44ais improved. Hence, the silicon nitride film40bon the sidewall is suppressed from being selectively etched with respect to the silicon oxide film40aon the sidewall. For example, oxygen may be supplied to the memory holes MH formed in the stacked body40between the second etching and the second treatment and between the third etching and the third treatment. As described above, according to the manufacturing method for a semiconductor device of the fifth embodiment, similarly to the first embodiment, it is possible to suppress the shape of the memory hole from becoming a bowing shape, and to form the memory hole with high process accuracy. Sixth Embodiment The manufacturing method for a semiconductor device of the sixth embodiment is different from the manufacturing method of the first to fifth embodiments in that the layer to be processed is a single layer. Hereinafter, part of description of the contents overlapping the first to fifth embodiment may be omitted. In the manufacturing method for a semiconductor device of the sixth embodiment, the layer to be processed is a single layer. In other words, there is no stacked structure in which the layer to be processed is formed of two or more types of different films. The layer to be processed is, for example, an insulating layer of a single layer. The insulating layer is, for example, an oxide layer, a nitride layer, or an oxynitride layer. The layer to be processed is, for example, a metal layer of a single layer. The layer to be processed is, for example, a semiconductor layer of a single layer. The semiconductor layer is, for example, a silicon layer of a single crystal or polycrystalline. In the manufacturing method for a semiconductor device of the sixth embodiment, the pattern of the recess to be formed is, for example, a hole pattern or a groove pattern. As described above, according to the manufacturing method for a semiconductor device of the sixth embodiment, by a function similar to that in the first to fifth embodiments, it is possible to suppress the shape of the memory hole from becoming a bowing shape, and to form the memory hole with high process accuracy. In the first to fifth embodiments, the case where the etching is performed four times and the treatment of supplying the silylation agent between the etching is performed three times has been described by way of example. However, the number of times of etching is not limited to four and the number of times of the treatment of supplying the silylation agent is not limited to three. The number of times of etching may be any number as long as it is equal to or more than two, and the number of times of treatment of supplying the silylation agent may be any number as long as it is equal to or more than one. In the first to fifth embodiments, the case where the semiconductor device is a nonvolatile memory has been described by way of example. However, the semiconductor device is not limited to a nonvolatile memory. In the first embodiment, the case where the first film of the layer to be processed is a silicon oxide film and the second film is a silicon nitride film has been described by way of example. However, the first film and the second film are not limited to a combination of a silicon oxide film and a silicon nitride film as long as they are different films. For example, a combination of an insulating film and a semiconductor film, or a combination of an insulating film and a metal film may be adopted. While certain embodiments have been described, these embodiments have been presented by way of example only, and are not intended to limit the scope of the inventions. Indeed, the manufacturing method for a semiconductor device described herein may be embodied in a variety of other forms; furthermore, various omissions, substitutions and changes in the form of the devices and methods described herein may be made without departing from the spirit of the inventions. The accompanying claims and their equivalents are intended to cover such forms or modifications as would fall within the scope and spirit of the inventions. | 37,945 |
11862472 | Aspects of the present disclosure will be described with reference to the accompanying drawings. DETAILED DESCRIPTION Although specific configurations and arrangements are discussed, it should be understood that this is done for illustrative purposes only. As such, other configurations and arrangements can be used without departing from the scope of the present disclosure. Also, the present disclosure can also be employed in a variety of other applications. Functional and structural features as described in the present disclosures can be combined, adjusted, and modified with one another and in ways not specifically depicted in the drawings, such that these combinations, adjustments, and modifications are within the scope of the present discloses. In general, terminology may be understood at least in part from usage in context. For example, the term “one or more” as used herein, depending at least in part upon context, may be used to describe any feature, structure, or characteristic in a singular sense or may be used to describe combinations of features, structures or characteristics in a plural sense. Similarly, terms, such as “a,” “an,” or “the,” again, may be understood to convey a singular usage or to convey a plural usage, depending at least in part upon context. In addition, the term “based on” may be understood as not necessarily intended to convey an exclusive set of factors and may, instead, allow for existence of additional factors not necessarily expressly described, again, depending at least in part on context. It should be readily understood that the meaning of “on,” “above,” and “over” in the present disclosure should be interpreted in the broadest manner such that “on” not only means “directly on” something but also includes the meaning of “on” something with an intermediate feature or a layer therebetween, and that “above” or “over” not only means the meaning of “above” or “over” something but can also include the meaning it is “above” or “over” something with no intermediate feature or layer therebetween (i.e., directly on something). Further, spatially relative terms, such as “beneath,” “below,” “lower,” “above,” “upper,” and the like, may be used herein for ease of description to describe one element or feature's relationship to another element(s) or feature(s) as illustrated in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The apparatus may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein may likewise be interpreted accordingly. As used herein, the term “layer” refers to a material portion including a region with a thickness. A layer can extend over the entirety of an underlying or overlying structure or may have an extent less than the extent of an underlying or overlying structure. Further, a layer can be a region of a homogeneous or inhomogeneous continuous structure that has a thickness less than the thickness of the continuous structure. For example, a layer can be located between any pair of horizontal planes between, or at, a top surface and a bottom surface of the continuous structure. A layer can extend horizontally, vertically, and/or along a tapered surface. A substrate can be a layer, can include one or more layers therein, and/or can have one or more layer thereupon, thereabove, and/or therebelow. A layer can include multiple layers. For example, an interconnect layer can include one or more conductor and contact layers (in which interconnect lines and/or via contacts are formed) and one or more dielectric layers. In fabricating 3D memory devices, such as 3D NAND memory devices, the top surface of a topographic dielectric layer (e.g., a silicon oxide layer) needs to be planarized by CMP. For example, after forming the staircase structure at the side of an elevated stack structure, a dielectric layer, such as a tetraethyl orthosilicate (TEOS) silicon oxide layer, is deposited to cover the staircase structure as well as other areas of the stack structure (e.g., the core array region) and the down area outside and below the elevated stack structure. Due to the height variances of different regions covered by the deposited dielectric layer, protrusion(s) and step height(s) may appear in the topography of the dielectric layer, which need to be removed by CMP prior to subsequent processes applied to the stack structure, for example, forming channel structures through the stack structure. Conventionally, a high selectivity slurry (HSS) in combination with a stop layer are used in CMP for polishing the above-mentioned topographic dielectric layer covering a staircase structure. The high selectivity slurry used for polishing dielectric layers has a high selectivity of silicon oxide over silicon nitride, such that a silicon nitride layer can cover the top surface of the stack structure in the core array region as the CMP stop layer to control the endpoint of the CMP process. However, the same silicon nitride layer also covers and protects the topographic dielectric layer outside the stack structure during the CMP. As a result, the step height remains between the down area outside the stack structure and the core array region in the stack structure, which requires additional etching and CMP processes to eliminate it. In practice, a residual step height can even remain in several subsequent processes to cause defects, which affects the production yield. Moreover, since the layout of structures along different directions (e.g., the word line direction and bit line direction) is different, the different loadings for CMP in different directions may also cause dishing on the top surface of the dielectric layer after CMP in one direction due to over-polishing. The dishing can trap various kinds of residuals in the subsequent deposition processes, which are difficult to remove and also cause defects in the final product. Besides the various issues caused by the residual step height and dishing after CMP, the removal of the protrusion in the dielectric layer right above the staircase structure during the CMP process introduces additional issues to the conventional CMP process as well. Because the protrusion is also covered by the silicon nitride CMP stop layer, which has a high CMP selectivity over silicon oxide (e.g., ˜12), the removal rate is significantly reduced when polishing the protrusion, thereby reducing the throughput and increasing the production cost. To address the aforementioned issues, the present disclosure introduces a solution in which the conventional CMP process using a high selectivity slurry and a CMP stop layer is replaced with an improved CMP process using an auto-stop slurry (ASS) without any CMP stop layer in polishing dielectric layers, such as the above-mentioned topographic dielectric layer covering the staircase structure in fabricating 3D memory devices. Different from the high selectivity slurry, the endpoint of a CMP process using an auto-stop slurry does not rely on the CMP selectivity over the stop layer, but rather the pressure sensitivity of the slurry as the CMP contact area changes during the process when the surface flatness changes. That is, the surface features remaining on the topography of the dielectric layer can prevent the stop of the CMP process using the auto-stop slurry. As a result, both the residual step height and dishing can be prevented by the CMP process disclosed herein, thereby avoiding the need for extra CMP processes to remove the step height as well as reducing the defects caused by the step height and dishing in later processes. Furthermore, by eliminating the CMP stop layer, the removal rate of the CMP process, in particular when removing protrusions, can be increased to improve the throughput and reduce the cost. Although the CMP process using an auto-stop slurry is described herein with respect to a dielectric layer covering a staircase structure in a 3D memory device, consistent with the scope of the present disclosure, the CMP process disclosed herein can be applied to any suitable topographic dielectric layers (e.g., having surface features like protrusions, recesses, step heights, etc.) in any suitable semiconductor devices including but not limited to, logic devices (e.g., central processing unit (CPU), graphics processing unit (GPU), and application processor (AP)), volatile memory devices (e.g., dynamic random-access memory (DRAM) and static random-access memory (SRAM)), non-volatile memory devices (e.g., NAND Flash memory, NOR Flash memory), or any combinations thereof in a 2D, 2.5D, or 3D architecture. For example,FIG.1illustrates a plan view of an exemplary wafer100having a plurality of 3D memory device chips104, according to some aspects of the present disclosure. Wafer100can include multiple shots102each including four dies, such as four 3D memory device chips104, separated by scribe lines106. As shown inFIG.1, each 3D memory device chip104can include a stack structure108, such as a memory stack having interleaved conductive layers (e.g., gate lines/word lines) and dielectric layers (e.g., gate-to-gate dielectrics), which is elevated from the surrounding down area. In some implementations, stack structure108includes a staircase structure110on one or more sides of stack structure108. Staircase structure110can have a sloped profile elevating from the surrounding down area outside stack structure108to the inner area within stack structure108. Based on the different elevations of the structures therein, 3D memory device chip104can be separated into three regions: a core array region (dot pattern fill), a staircase region (diagonal pattern fill), and a peripheral region (no fill). As shown inFIG.1, in some implementations, stack structure108is in both the core array region and the staircase region, and staircase structure110of stack structure108is in the staircase region on the side(s) of stack structure108. Memory cell arrays can be formed in the core array region, for example, in the form of arrays of NAND memory strings each extending vertically through stack structures108. In some implementations, the peripheral region is the surrounding down area outside stack structure108. For example, scribe lines106may be in the peripheral region. Other protection, testing, or measurement structures, such as seal rings, testing pads, alignment marks, etc., can be in the peripheral region as well. As described below in detail, in certain stages of fabricating 3D memory device chips104, the different elevations of the structures in the peripheral region, staircase region, and core array region can cause the formation of a topographic dielectric layer over the peripheral region, staircase region, and core array region, which needs to be planarized (polished), for example, using CMP, to become a planar dielectric layer. For example, the structures in the peripheral region, such as scribe lines106, may have the lowest elevation, the part of stack structure108in the core array region may have the highest elevation, and staircase structure110in the staircase region may have a gradually increased elevation from the peripheral region to the core array region. The elevation differences can be cause various surface features in the topography of a deposited dielectric layer, such as protrusions, recesses, and step heights. The layout of the structures in the peripheral region can be different along different directions as well. For example, as shown inFIG.1, the thickness of scribe lines106along the x-direction (e.g., the word line direction of 3D memory device chips104) may be greater than the thickness of scribe lines106along the y-direction (e.g., the bit line direction of 3D memory device chips104) perpendicular to the x-direction. As described above, the uneven layout of structures in the x- and y-directions can cause uneven loadings for a CMP process. For example, the same CMP condition may be suitable for patterns in one direction while causing over-polishing for patterns in another direction due to the different loadings between the two directions. FIGS.2A-2Hillustrate an exemplary fabrication process for forming a 3D memory device, according to some aspects of the present disclosure.FIG.5is a flowchart of an exemplary method500for forming a 3D memory device, according to some aspects of the present disclosure.FIGS.2A-2H and5will be described together. It is understood that the operations shown in method500are not exhaustive and that other operations can be performed as well before, after, or between any of the illustrated operations. Further, some of the operations may be performed simultaneously, or in a different order than shown inFIG.5. In some implementations, the 3D memory device formed by the exemplary fabrication process depicted inFIGS.2A-2H and5is an example of 3D memory device chips104inFIG.1, and the exemplary fabrication process includes an example of a polishing process, e.g., CMP using an auto-stop slurry, for polishing a dielectric layer that covers the peripheral region, staircase region, and core array region, as described above with respect toFIG.1. It is understood that the exemplary polishing process may be applied to the fabrication processes for any other suitable semiconductor devices that involve polishing a dielectric layer that is over both an elevated semiconductor structure and a down area outside and below the elevated semiconductor structure. Referring toFIG.5, method500starts at operation502, in which a stack structure is formed in a staircase region and a core array region. The stack structure can include a plurality of interleaved first material layers and second material layers. Edges of the interleaved first material layers and second material layers can define a staircase structure on a side of the stack structure in the staircase region. In some implementations, the first material layers include silicon oxide, and the second material layers include silicon nitride. As illustrated inFIG.2A, a stack structure202(e.g., one example of stack structure108inFIG.1) including a plurality pairs of first material layers206and second material layers204is formed above a substrate200. That is, stack structure202includes vertically interleaved first and second material layers206and204, according to some implementations. First material layers206and the second material layers204can be alternatingly deposited above substrate200to form stack structure202using one or more thin film deposition processes including, but not limited to, chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), or any combination thereof. It is noted that x, y, and z axes are included inFIGS.2A-2Hto help illustrating the spatial relationship of the components in the 3D memory device. Like inFIG.1, x and y axes are included inFIGS.2A-2Hto illustrate two perpendicular lateral directions in the wafer plane: the x-direction is the word line direction of the 3D memory device, and the y-direction is the bit line direction of 3D memory device. Substrate200of the 3D memory device includes two lateral surfaces extending laterally in the x-y plane: a top surface on the front side of the wafer on which the 3D memory device can be formed, and a bottom surface on the backside opposite to the front side of the wafer. The z-axis is perpendicular to both the x and y axes. As used herein, whether one component (e.g., a layer or a device) is “on,” “above,” or “below” another component (e.g., a layer or a device) of the 3D memory device is determined relative to substrate200of the 3D memory device in the z-direction (the vertical direction perpendicular to the x-y plane) when substrate200is positioned in the lowest plane of the 3D memory device in the z-direction. The same notion for describing the spatial relationships is applied throughout the present disclosure. In some implementations, stack structure202is a dielectric stack in which first material layers206include first dielectric layers, and second material layers204(a.k.a. sacrificial layers) include second dielectric layers different from the first dielectric layers. The dielectric layers can include dielectric materials including, but not limited to, silicon oxide, silicon nitride, silicon oxynitride, high dielectric constant (high-k) dielectrics, or any combination thereof. For example, first material layers206may include silicon oxide, and second material layers204may include silicon nitride. In some implementations, stack structure202is a memory stack in which first material layers206include dielectric layers, and second material layers204include conductive layers. The conductive layers can include conductive materials including, but not limited to, tungsten (W), cobalt (Co), copper (Cu), aluminum (Al), polycrystalline silicon (polysilicon), doped silicon, silicides, or any combination thereof. For example, first material layers206may include silicon oxide, and second material layers204may include metals (e.g., W) or polysilicon. As illustrated inFIG.2A, a staircase structure208(e.g., one example of staircase structure110inFIG.1) having a terraced slope-like shape is formed on one side of stack structure202for purposes such as word line fan-out. In other words, the edges of interleaved first material layers206and second material layers204can define staircase structure208on the side of stack structure202. It is understood that in some examples, additionally or alternatively, staircase structure208may be formed in the intermediate (e.g., the center) of stack structure202. Each stair (a.k.a. level) of staircase structure208can include one or more pairs of first and second material layers206and204. That is, the height of each stair can be equal to the total thickness of one or more pairs of first and second material layers206and204. Staircase structure208can be formed by a so-called trim-etch process, which, in each cycle, trims (e.g., etching incrementally and inwardly, often from all directions) a patterned photoresist layer, followed by etching the exposed portions of interleaved first material layers206and second material layers204of stack structure202using the trimmed photoresist layer as an etch mask to form one stair of staircase structure208. The process can be repeated until all the stairs of staircase structure208are formed. As illustrated inFIG.2A, the 3D memory device can include a core array region201, a peripheral region205, and a staircase region203laterally between core array region201and peripheral region205. Core array region201, peripheral region205, and staircase region203may be examples of the core array region, peripheral region, and staircase region in FIG.1, respectively. In some implementations, stack structure202is formed in both core array region201and staircase region203, and staircase structure208is formed on the side of stack structure202in staircase region203. In some implementations, a scribe line (not shown) is formed in peripheral region205outside stack structure202. At the fabrication stage inFIG.2A, the structure in core array region201(e.g., part of stack structure202) can have the highest height (the elevation relative to substrate200), the structure in peripheral region205(e.g., the scribe line) can have the lowest height, and the structure in staircase structure (e.g., staircase structure208) can have a terraced slope with a gradually increased height from peripheral region205to core array region201, which is formed by the trim-etch process. That is, the formation of elevated stack structure202and sloped staircase structure208can cause uneven height distribution among core array region201, peripheral region205, and staircase region203. As the number of levels of stack structure202continues increasing to increase the memory cell density, the height changes among core array region201, peripheral region205, and staircase region203can become more drastic. As a result, following the formation of staircase structure208(i.e., the sloped side of stack structure202), a planar dielectric layer needs to be formed over core array region201, peripheral region205, and staircase region203in order to provide insulation as well as padding with a flat top surface for subsequent processes. Method500proceeds to operation504, as illustrated inFIG.5, in which a dielectric layer is formed over the staircase region and a peripheral region outside the stack structure. The dielectric layer can include a protrusion from the stack structure. The protrusion can be right above the staircase structure. In some implementations as shown inFIG.6, to form the dielectric layer, at operation602, the dielectric layer is deposited over the peripheral region, the staircase region, and the core array region; at operation604, part of the dielectric layer over the core array region is removed to expose a top surface of the stack structure in the core array region, such that a top surface of the dielectric layer over the peripheral region is above the top surface of the stack structure in the core array region. In some implementations, the top surface of the dielectric layer over the staircase region also protrudes from the peripheral region and the core array region after removing the part of the dielectric layer over the core array region. That is, the topography of the dielectric layer can include a protrusion right above the sloped side of the stack structure, and a step height above the top surface of the stack structure. As illustrated inFIG.2B, a dielectric layer210is deposited over peripheral region205, core array region201, and staircase region203between peripheral region205and core array region201. Dielectric layer210can include dielectric materials including, but not limited to, silicon oxide, silicon nitride, silicon oxynitride, or any combination thereof. For example, dielectric layer210may include TEOS silicon oxide. Dielectric layer210can be deposited using one or more thin film deposition processes including, but not limited to ALD, CVD, PVD, or any combination thereof. The thickness of dielectric layer210after deposition is controlled, for example, by controlling the deposition rate and/or time, such that the top surface of dielectric layer210is not lower than the top surface of stack structure202in core array region201, according to some implementations. As shown inFIG.2B, the topography of dielectric layer210after deposition can generally follow the height profile of the structures in peripheral region205, core array region201, and staircase region203. That is, the top surface of dielectric layer210is elevated from peripheral region205through staircase region203to core array region201after deposition, according to some implementation. In some implementations, to ensure full coverage of dielectric layer210over staircase structure208, which protects second material layers204(e.g., silicon nitride, polysilicon, or metals) in later processes, the top surface of dielectric layer210over peripheral region205is higher than the top surface of stack structure202in core array region201, as shown inFIG.2B. As illustrated inFIG.2C, part of dielectric layer210that is over core array region201is removed to expose the top surface of stack structure202in core array region201, for example, the topmost second material layer204. In some implementations, dielectric layer210includes silicon oxide, and each second material layer204(including the exposed topmost second material layer204) includes silicon nitride. To remove the part of dielectric layer210over core array region201, an etch mask (e.g., a photoresist layer, not shown) can be first patterned using lithography to cover the rest of dielectric layer210(e.g., the parts over peripheral and staircase regions205and203) and expose only the part that is over core array region201. An etching process, including dry etching and/or wet etching such as reactive ion etching (RIE), can be used to etch the part of dielectric layer210over core array region201, which is not covered by the etch mask, until reaching the top surface of stack structure202in core array region201(e.g., the topmost second material layer204). The etching process can create the topographic dielectric layer210, as shown inFIG.2C. The topography of dielectric layer210after etching can include a protrusion212right above staircase structure208in staircase region203. In other words, the top surface of dielectric layer210over staircase region203protrudes from peripheral region205and stack structure202in core array region201after removing the part of dielectric layer210over core array region201, according to some implementation. In some implementations, the slope of protrusion212follows the sloped profile of staircase structure208due to the conformal coating of dielectric layer210over staircase structure208using CVD or ALD. For example, the size of protrusion212in the x-y plane (i.e., the lateral cross-section area) may gradually increase towards substrate200. The topography of dielectric layer210after etching can also include a step height (SH) between the part of the top surface of dielectric layer210that is over peripheral region205and the exposed top surface of stack structure202in core array region201. For example, as shown inFIG.2C, the step height may be above the exposed top surface of stack structure202in core array region201, meaning that the part of the top surface of dielectric layer210over peripheral region205is higher than the top surface of stack structure202in core array region201(e.g., the topmost second material layer204). As described above, the step height can ensure full coverage of dielectric layer210over staircase structure208, which protects second material layers204(e.g., silicon nitride, polysilicon, or metals) in later processes. As described above, the surface features (e.g., protrusion212and the step height) of topographic dielectric layer210need to be removed by a polishing process, such as CMP, to have a planar top surface of dielectric layer210that is flush with the top surface of stack structure202on which other structures can be formed in subsequent processes. Different from the conventional polishing process that requires a stop layer (e.g., a silicon nitride layer) formed directly on dielectric layer210and a high selectivity slurry, a stop layer-free polishing process can be applied using an auto-stop slurry as described below in detail. Method500proceeds to operation506, as illustrated inFIG.5, in which the dielectric layer is polished using an auto-stop slurry to remove the protrusion of the dielectric layer. In some implementations, the dielectric layer is polished using the auto-stop slurry until the protrusion and the step height of the topography of the dielectric layer are flattened. The auto-stop slurry can include an abrasive, an additive, and an inhibitor sensitive to pressure. In some implementations as shown inFIG.6, to polish the dielectric layer, at operation606, the auto-stop slurry is applied directly onto the top surfaces of the dielectric layer over the staircase region and the peripheral region as well as the top surface of the stack structure in the core array region; at operation608, a down force is applied to the auto-stop slurry to polish the dielectric layer. For example, the down force may be applied constantly at a same value. In some implementations, to apply the down force to the auto-stop slurry, the down force is applied to the auto-stop slurry directly on the top surface of the dielectric layer to remove the protruded dielectric layer (protrusion), and the down force is further continuously applied to the auto-stop slurry directly on the top surface of the dielectric layer until the top surface of the dielectric layer is flush with the top surface of the stack structure in the core array region. As illustrated inFIG.2D, protrusion212(shown inFIG.2C) of dielectric layer210is removed by polishing topographic dielectric layer210using an auto-stop slurry in a CMP process. The step height can be reduced as well. That is, the top surface of dielectric layer210over peripheral region205can be lowered by polishing dielectric layer210using the auto-stop slurry. As illustrated inFIG.2E, dielectric layer210is continuously polished until the step height is removed, i.e., when the top surface of dielectric layer210over peripheral region205and staircase region203is planar and flush with the top surface of stack structure201in core array region201. In other words, protrusion212and the step height of the topography of dielectric layer210are flattened after polishing, as shown inFIG.2E, according to some implementations. Different from the conventional CMP process for polishing dielectric layer210, which first forms a CMP stop layer (e.g., a silicon nitride layer) directly on dielectric layer210prior to polishing, the CMP process disclosed herein is applied directly to dielectric layer210without a stop layer formed thereon, i.e., being a stop layer-free CMP process or an auto-stop CMP process in the presence of an auto-stop slurry, according to some implementations. The term “auto-stop” disclosed herein refers to that once the up areas on a topographic dielectric layer have been removed by a polishing process (e.g., CMP) such that they are in the same plane as the down areas, the removal rate (RR) across the planar top surface of the dielectric becomes zero to essentially stop the polishing process. Thus, polishing beyond the endpoint (i.e., over-polishing) does not continue thinning the dielectric layer. The endpoint detection and maintenance are thus not per se critical to obtain a planar dielectric layer of the desired thickness. An auto-stop slurry can include an abrasive, an additive, and an inhibitor sensitive to pressure. By adding the inhibitor that is sensitive to pressure to the additive, the inhibitor that adheres to the surface of abrasives can cause a higher removal rate to a topographic surface, but a lower removal rate to a planar (flat or blanket) surface. Thus, as the surface features of the topography being flatten, the removal rate decreases and eventually becomes zero to essentially stop the polishing process. In some implementations in which the dielectric layer includes silicon oxide, the abrasive (a.k.a. polishing agent) is ceria (cerium oxide, CeO2)-based abrasive. It is understood that in some examples, the abrasive may include other metal oxide materials, such as zinc oxide (ZrO2), thorium oxide (ThO2), titanium oxide (TiO2), iron oxide (Fe2O3), aluminum oxide (Al2O3), etc. The abrasives can be suspended in an aqueous solution (commonly a colloid), such as alkaline or any other suitable solution, with various additives for different purposes, such as rust prevention, metal protection, pH control, stop layer passivation, and so on. For example, in a high selectivity slurry, additives (e.g., surfactants) may have a high silicon nitride selectivity over silicon oxide (e.g., greater than 10) to be more easily adhere to a silicon nitride layer than a silicon oxide layer to passivate the silicon nitride stop layer. In an auto-stop slurry, an inhibitor sensitive to pressure (a.k.a. self-stop agent) can be added, such that the slurry can react sensitively to the polishing pressure. In some implementations, the inhibitor includes benzotriazole (C6H5N3, a.k.a. BTA), hydrogen phthalate salt, or polyalkylamine, for example, polyethyleneimine (a.k.a. PEI). For example,FIGS.3A and3Billustrate the polishing mechanism of an exemplary auto-stop slurry, according to some aspects of the present disclosure. The auto-stop slurry may include an abrasive302(e.g., ceria particles), a pressure-sensitive inhibitor304, and other additives (not shown). The auto-stop slurry may be applied directly onto a dielectric layer300(e.g., a silicon oxide layer) without any stop layer (e.g., a silicon nitride layer) therebetween. A down force (DF) then may be applied to the auto-stop slurry to generate a pressure P, which is defined by the down force and the contact area between the CMP pad and the polishing surface of dielectric layer300in contact with the CMP pad. InFIG.3A, when pressure Pais relatively high, inhibitors304between abrasives302and dielectric layer300may be pushed away from abrasives302by high-pressure Pa, resulting in a high removal rate of dielectric layer300. In contrast, inFIG.3Bwhen pressure Pb is relatively low, inhibitors304adhere back to abrasives302to prevent abrasives302from contacting dielectric layer300, resulting in a low removal rate of dielectric layer300. That is, by adding an inhibitor sensitive to pressure to the auto-stop slurry, the removal rate of the CMP process can be self-adjusted based on the pressure applied to the auto-stop slurry. In some implementations, when the down force is applied constantly at the same value, the removal rate of the CMP process is affected only by the contact area, for example, the topography of the dielectric layer.FIG.4illustrates an exemplary polishing process using an auto-stop slurry, according to some aspects of the present disclosure. At stage (1) inFIG.4, an auto-stop slurry (not shown) may be applied between a topographic dielectric layer400and a CMP pad404. The topography of dielectric layer400may include protrusions402and step heights (SH). A down force (DF) may then be applied to the auto-stop slurry through CMP pad404to generate a pressure P1to start polishing topographic dielectric layer400. Continuing to stage (2), the polishing of topographic dielectric layer400may change the topography of dielectric layer400, for example, by removing parts of protrusions402and reducing the step heights, resulting in an increase of the contact area between CMP pad404and dielectric layer400. The same down force may be constantly applied between stage (1) and (2). Thus, pressure P2at stage (2) may decrease due to the increase of the contact area from stage (1). As described above, the decrease of the pressure may cause a decrease of the removal rate from stage (1). Continuing to stage (3), when the topography of dielectric layer400is flatten by removing protrusions402and the step heights (i.e., when topographic dielectric layer400becomes planar dielectric layer400), the auto-stop slurry may be formulated based on current pressure P3with the same down force, such that the removal rate of polishing becomes zero to essentially stop the polishing automatically. Referring back toFIGS.2C-2E, similarly, the removal rate of polishing may decrease as protrusion212of dielectric layer210being removed due to the increase of the polishing contact area. By adjusting the composition of the auto-stop slurry, for example, the type and/or weight concentration of the pressure-sensitive inhibitor, the removal rate of the polishing may become zero, i.e., essentially stopping the polishing, when the top surface of dielectric layer210becomes planar and flush with the top surface of stack structure202, as shown inFIG.2E. In some implementations, the auto-stop slurry also exhibits the CMP stopping behavior as a high selectivity slurry as well, for example, by adding the high selectivity additive, such as surfactants, into the auto-stop slurry. The auto-stop slurry with high selectivity additive can thus be applied directly onto the top surface of dielectric layer210over peripheral and staircase regions205and203as well as onto the top surface of stack structure202, i.e., the topmost second material layer204. As a result, the polishing not only stops at the planar top surface of dielectric layer210(e.g., a silicon oxide layer), but also stops at the second material layer204(e.g., a silicon nitride layer), which functions as a CMP stop layer. In some implementations, the down force is constantly applied at the same value through the polishing process, and the polishing time is controlled to be sufficient to reach the endpoint at which the removal rate becomes zero. It is understood that excess polishing time beyond the endpoint would not further thin the planar dielectric layer210to cause over-polishing due to the auto-stop nature of the auto-stop slurry. By utilizing the auto-stop nature of the auto-stop slurry in the polishing process, the various issues involved in the conventional dielectric layer polishing process as described above can be overcome. Regarding the residual step height, since any residual step height (e.g., shown inFIG.2D) prior to the polishing endpoint (e.g., shown inFIG.2E) would cause the removal rate higher than zero, the polishing can continue until reaching the endpoint, i.e., when all the surface features, including residual step height, were removed from the topography of dielectric layer210. As described above, the auto-stop nature of the auto-stop slurry would also prevent over-polishing, such that the dishing due to unbalanced loadings along different directions can be avoided as well. Moreover, as the CMP stop layer does not form on dielectric layer210, including protrusion212, the removal of dielectric layer210, in particular, protrusion212, the throughput of the polishing process can be increased with a reduction of the manufacturing cost. The improvement of the surface flatness of dielectric layer210after polishing can also avoid potential defects in subsequent processes. For illustrative purposes only without limiting the applications of the polishing process disclosed herein, exemplary processes in fabricating the 3D memory after the polishing process are described below. As illustrated inFIG.2F, the topmost second material layer204(e.g., a silicon nitride layer) is removed, followed by polishing dielectric layer210, such that the top surface of dielectric layer210(e.g., a silicon oxide layer) is flush with the top surface of stack structure202, i.e., the topmost first material layer206(e.g., a silicon oxide layer). The prior polishing process may damage the top surface of the topmost second material layer204, which serves as the CMP stop layer protecting stack structure202during the polishing process. Thus, in some implementations, to avoid any defects on the topmost second material layer204, an etching process, such as a wet etching process selective to silicon nitride over silicon oxide, is applied to selectively remove the topmost second material layer204without etching dielectric layer210and first material layers206. Another polishing process, such as a CMP process with a much shorter duration, can then be applied to planarize dielectric layer210to be flush with the exposed topmost first material layer206. The polishing process can use the auto-stop slurry as well. As a result, a damage-free, planar silicon oxide layer (including dielectric layer210and the topmost first material layer206) can be formed over peripheral region205, staircase region203, and core array region201. Compared with the conventional polishing process, no additional operations may be needed to remove the residual step height (e.g., etching part of dielectric layer210over peripheral region205) or fill up the dishing (depositing another buffer layer on dielectric layer210) caused by the prior polishing process in order to form the damage-free, planar silicon oxide layer, as shown inFIG.2F. As illustrated inFIG.2G, an array of NAND memory strings213are formed in core array region201. Each NAND memory string213can extend vertically through stack structure202into substrate200. In some implementations, the fabrication process to form NAND memory string213includes forming a channel hole through stack structure202using dry etching/and or wet etching, such as deep RIE (DRIE), followed by filling the channel hole with a plurality of layers, such as a memory film and a semiconductor channel, using thin film deposition processes. For example, the memory film may be a composite dielectric layer, such as a combination of multiple dielectric layers including, but not limited to, a blocking layer, a storage layer, and a tunneling layer. The memory film and semiconductor channel can be formed by sequentially depositing a plurality of layers, such as a silicon oxide layer, a silicon nitride layer, a silicon oxide layer, and a polysilicon layer using one or more thin film deposition processes including, but not limited to ALD, CVD, PVD, or any combination thereof. The remaining space of the channel hole may be filled with a capping layer by depositing silicon oxide into the channel hole. In some implementations, a channel plug is formed in the top portion of the channel hole, for example, by etching back the semiconductor channel using dry etching and/or wet etching to form a recess and filling the recess with polysilicon using one or more thin film deposition processes including, but not limited to ALD, CVD, PVD, or any combination thereof. In the fabrication process to form NAND memory string213, a damage-free, planar silicon oxide layer (including dielectric layer210and the topmost first material layer206) can avoid any residual, such as polysilicon residual trapped by the dishing, which may occur after the conventional polishing process described above. As illustrated inFIG.2H, in some implementations in which second material layers204include dielectric layers, such as silicon nitride, a so-called gate replacement process is performed to replace second material layers204with third material layers214including conductive materials, such as W. For example, a slit may be etched through stack structure202using wet etching and/or dry etching, such as DRIE, which may serve as the passageways for the gate replacement process. The replacement of second material layers204with third material layers214can be performed by wet etching second material layers204(e.g., silicon nitride) selective to first material layers206(e.g., silicon oxide) and filling the resulting lateral recesses with third material layers214(e.g., W). Third material layers214can be deposited using one or more thin film deposition processes including, but not limited to ALD, CVD, PVD, or any combination thereof. As illustrated inFIG.2H, in some implementations, a source contact structure216is formed through stack structure202in core array region201. Source contact structure216can be formed by sequentially depositing one or more dielectric layers (e.g., silicon oxide, as a spacer) and one or more conductive layers (e.g., W and polysilicon, as a contact) into the slit using one or more thin film deposition processes including, but not limited to ALD, CVD, PVD, or any combination thereof. Again, in the fabrication process to form source contact structure216, a damage-free, planar silicon oxide layer (including dielectric layer210and the topmost first material layer206) can avoid any residual, such as W residual or polysilicon residual trapped by the dishing, which may occur after the conventional polishing process described above. Although the CMP process using an auto-stop slurry is described above with respect to a dielectric layer covering a staircase structure in a 3D memory device, consistent with the scope of the present disclosure, the CMP process disclosed herein can be applied to any suitable topographic dielectric layers (e.g., having surface features like protrusions, recesses, step heights, etc.) in any suitable semiconductor devices including but not limited to, any suitable logic devices, volatile memory devices, non-volatile memory devices, or any combinations thereof. For example, a dielectric layer (e.g., dielectric layer210) may be deposited over a semiconductor structure (e.g., stack structure202), and an area (e.g., peripheral region205) outside and below the semiconductor structure. The semiconductor structure may be any elevated semiconductor structure relative to the outside down area. A side of the semiconductor structure may be sloped (e.g., staircase structure208). Part of the dielectric layer may then be removed to expose a planar top surface of the semiconductor structure, such that a topography of the dielectric layer includes a protrusion (e.g., protrusion212) right above the sloped side of the semiconductor structure, and a step height above the top surface of the semiconductor structure. The step height may be between the part of the dielectric layer right above the area and the top surface of the semiconductor structure. The dielectric layer may then be polished using an auto-stop slurry until the protrusion and the step height of the topography of the dielectric layer are flattened. To polish the dielectric layer, the auto-stop slurry may be applied directly onto a top surface of the dielectric layer and the top surface of the semiconductor structure, and a down force to the auto-stop slurry directly on the top surfaces of the dielectric layer and the semiconductor structure until the top surface of the dielectric layer is planar and flush with the top surface of the semiconductor structure. The removal rate of the polishing may decrease as the protrusion of the dielectric layer being polished and become zero when the protrusion and the step height of the topography of the dielectric layer are flattened. According to one aspect of the present disclosure, a method for forming a 3D memory device is disclosed. A stack structure is formed in a staircase region and a core array region. The stack structure includes a plurality of interleaved first material layers and second material layers. Edges of the interleaved first material layers and second material layers define a staircase structure on a side of the stack structure in the staircase region. A dielectric layer is formed over the staircase region and a peripheral region outside the stack structure. The dielectric layer includes a protrusion from the stack structure. The dielectric layer is polished using an auto-stop slurry to remove the protrusion of the dielectric layer. In some implementations, to form the dielectric layer, the dielectric layer is deposited over the peripheral region, the staircase region, and the core array region, and part of the dielectric layer over the core array region is removed to expose a top surface of the stack structure in the core array region, such that a top surface of the dielectric layer over the peripheral region is above the top surface of the stack structure in the core array region. In some implementations, the top surface of the dielectric layer over the peripheral region is lowered by polishing the dielectric layer using the auto-stop slurry. In some implementations, the top surface of the dielectric layer over the peripheral region becomes flush with the top surface of the stack structure in the core array region by polishing the dielectric layer using the auto-stop slurry. In some implementations, to polish the dielectric layer, the auto-stop slurry is applied directly onto a top surface of the dielectric layer over the staircase region and a top surface of the dielectric layer over the peripheral region, and a down force is applied to the auto-stop slurry directly on the top surfaces of the dielectric layer over the staircase region and the peripheral region. In some implementations, the down force is applied constantly at a same value. In some implementations, a removal rate of the polishing becomes zero when the top surfaces of the dielectric layer over the staircase region and peripheral region become flush with a top surface of the stack structure in the core array region. In some implementations, the protrusion is right above the staircase structure. In some implementations, a slope of the protrusion of the dielectric layer follows a profile of the staircase structure. In some implementations, a removal rate of the polishing decreases as the protrusion of the dielectric layer being removed. In some implementations, a scribe line is in the peripheral region. In some implementations, the first material layers include silicon oxide, the second material layers include silicon nitride, and the dielectric layer includes silicon oxide. In some implementations, the auto-stop slurry includes a ceria-based abrasive, an additive selective to silicon nitride over silicon oxide, and an inhibitor sensitive to pressure. According to another aspect of the present disclosure, a method for forming 3D memory device is disclosed. A dielectric layer is formed over a peripheral region, a core array region, and a staircase region between the peripheral region and the core array region, such that a top surface of the dielectric layer is elevated from the peripheral region through the staircase region to the core array region. Part of the dielectric layer over the core array region is removed. An auto-stop slurry is applied directly onto the top surface of the dielectric layer. A down force is applied to the auto-stop slurry directly on the top surface of the dielectric layer to polish the dielectric layer. In some implementations, the auto-stop slurry includes an abrasive, an additive, and an inhibitor sensitive to pressure. In some implementations, a stack structure includes a plurality of interleaved first material layers and second material layers and is in the core array region and the staircase region, edges of the interleaved first material layers and second material layers define a staircase structure on a side of the stack structure in the staircase region, and the top surface of the dielectric layer over the staircase region protrudes from the peripheral region and the core array region after removing the part of the dielectric layer over the core array region. In some implementations, to apply the down force to the auto-stop slurry, the down force is applied to the auto-stop slurry directly on the top surface of the dielectric layer to remove the protruded dielectric layer. In some implementations, a removal rate of the dielectric layer decreases as the protruded dielectric layer being removed. In some implementations, to apply the down force to the auto-stop slurry, the down force is further continuously applied to the auto-stop slurry directly on the top surface of the dielectric layer until the top surface of the dielectric layer is flush with a top surface of the stack structure in the core array region. In some implementations, a removal rate of the dielectric layer becomes zero when the top surface of the dielectric layer becomes flush with the top surface of the stack structure in the core array region. In some implementations, the down force is applied constantly at a same value. In some implementations, a scribe line is in the peripheral region. According to still another aspect of the present disclosure, a method for forming a semiconductor device is disclosed. A dielectric layer is deposited over a semiconductor structure and an area outside and below the semiconductor structure. A side of the semiconductor structure is sloped. Part of the dielectric layer is removed to expose a planar top surface of the semiconductor structure, such that a topography of the dielectric layer includes a protrusion right above the sloped side of the semiconductor structure, and a step height above the top surface of the semiconductor structure. The dielectric layer is polished using an auto-stop slurry until the protrusion and the step height of the topography of the dielectric layer are flattened. In some implementations, to polish the dielectric layer, the auto-stop slurry is applied directly onto a top surface of the dielectric layer and the top surface of the semiconductor structure, and a down force is applied to the auto-stop slurry directly on the top surfaces of the dielectric layer and the semiconductor structure until the top surface of the dielectric layer is planar and flush with the top surface of the semiconductor structure. In some implementations, the down force is applied constantly at a same value. In some implementations, the auto-stop slurry includes an abrasive, an additive, and an inhibitor sensitive to pressure. In some implementations, the step height is between part of the dielectric layer right above the area and the top surface of the semiconductor structure. In some implementations, a removal rate of the polishing decreases as the protrusion of the dielectric layer being polished and becomes zero when the protrusion and the step height of the topography of the dielectric layer are flattened. The foregoing description of the specific implementations can be readily modified and/or adapted for various applications. Therefore, such adaptations and modifications are intended to be within the meaning and range of equivalents of the disclosed implementations, based on the teaching and guidance presented herein. The breadth and scope of the present disclosure should not be limited by any of the above-described exemplary implementations, but should be defined only in accordance with the following claims and their equivalents. | 53,238 |
11862473 | DETAILED DESCRIPTION Stimuli responsive polymers (SRPs) may be used in semiconductor fabrication processes for sacrificial bracing of high aspect ratio (HAR) structures. Low ceiling temperature SRPs can be spontaneously removed when exposed to stimuli such as mildly elevated temperatures or acidic vapors, avoiding aggressive wet or dry removal chemistries that may harm the substrate surface. These SRPs can also be used for surface protection from airborne molecular contaminants and queue-time extension. As indicated above, in many embodiments, the SRPs are low ceiling temperature (Tc) polymers. Tcis the equilibrium temperature between a polymer and its monomers. As used herein, the term low Tcrefers to Tcvalues below a removal temperature. In some embodiments, the Tcis below room temperature, such that the polymers are thermodynamically unstable at room temperature. Instead, the low Tcpolymer is kinetically trapped to allow prolonged storage at room temperature. In some examples, the stable storage period is on the order of months or years. Low Tcpolymers will rapidly de-polymerize to its monomer constituents if an end-group or main chain bond is broken. Thus, the polymer de-polymerizes in response to stimuli such as ultraviolet (UV) light, heat, or an acidic/basic catalyst or compound. The monomer products are volatile and leave or can be easily removed from the surface and chamber. While in some embodiments, the Tcis below room temperature, in the context of semiconductor processing, low Tcmay also refer to ceiling temperatures that are higher than room temperature. For example, removal temperatures of up to 400° C. may be used, meaning that the ceiling temperature is below 400° C., with the polymer kinetically trapped below the ceiling temperature. In some embodiments of the methods described herein, removing an SRP includes controlled degradation by diffusing a compound, or a reactant that reacts to form a compound, only to a top portion of the SRP. The top portion is then degraded and removed, leaving the remaining SRP intact. The exposure and removal cycles are repeated. In some embodiments of the methods described herein, removing SRPs includes exposure to two reactants that react to form an acid or base that can trigger the degradation of the SRP. The exposure occurs sequentially to provide more precise top down control. A first reactant may be provided in gaseous form and diffuses into the SRP. Pressure, temperature, flow rate, and exposure time may be controlled to modulate the depth of diffusion. The first reactant is then purged, and the second reactant is provided in gaseous form to diffuse into the SRP. Pressure, temperature, flow rate, and exposure time may be controlled to modulate the depth of diffusion. A reaction occurs only to the depth and extent that the first and second reactants are both present in the SRP. Thus, all or only a portion of the SRP is degraded and removed in a cycle. The methods described above allow removal of the SRP at lower temperatures than using heat by itself as a stimulus. This can be advantageous for avoiding the formation of non-volatile carbonaceous species (char). Further, the methods allowed controlled removal without adding non-volatile catalysts, dyes, or other additives to the film. Eliminating low volatility additives and char results in a significant reduction or elimination of residues upon SRP removal. Examples of processes that involve the use of sacrificial SRPs are described below with reference toFIGS.1A and1B, with further details of the removal process provided with reference toFIGS.2-7. Turning toFIG.1A, an example of a method for bracing HAR structures using an SRP is shown. First at an operation101, a substrate including HAR structures with a solvent is provided. HAR structures are structures having high aspect ratios (ARs), e.g., at least 8, 10, 20, 30, 40, or 80. The substrate may be provided, for example, after a wet etch or cleaning operation and have solvent associated with the prior operation. In some embodiments, the solvent in operation101may be a transitional solvent if the prior solvent is not chemically compatible with the SRP solution. Next in an operation103, the solvent is displaced with a solution that includes a stimuli responsive polymer (SRP). The substrate is then dried in an operation105. The SRP solidifies as the liquid portion solution is removed and the SRP fills the HAR structures. A mechanical brace forms in the HAR structures to prevent collapse of the structures due to capillary forces that are generated during solvent drying. The fill may include one or more additional components, Such additional components may include stabilizers, surfactants, and/or plasticizers. The substrate is then exposed to a stimulus to degrade all of or only the top portion of the SRP in an operation107. As described further below, operation107may involve controlled exposure to a compound or to two reactants that react to form a compound that degrades the SRP. The stimulus is any compound that scissions bonds of the SRP to degrade it. In some embodiments, the compound is a relatively strong add or base. Volatile monomers or fragments from the degraded polymer can then be removed from the structure in an operation109. If SRP is still present, operations107and109are repeated one or more times to remove all the SRP in an operation111. The amount of SRP removed in each repetition may be the same or different. The number of repetitions is such that bracing remaining after each cycle of operation107and109can withstand the capillary forces without collapsing.FIGS.2A and2B, which show HAR structures having SRP films of thickness Ttotal, illustrate schematically the difference between too few and enough cycles.FIG.2Ashows a side cross-sectional view of an example of a HAR structure in which too much of the SRP is removed in a single removal. The high aspect ratio features collapse. InFIG.2B, by contrast, the structure remains intact. SRPs may also be used in the semiconductor fabrication processes for transient protection of a sensitive surface of substrate. This in turn can extend available queue time between fabrication steps. During semiconductor fabrication, many surfaces are sensitive to airborne molecular contaminants (AMCs) in the surrounding environment. Queue time can lead to exposure to the AMCs and unwanted interactions such as oxidation, corrosion, and halogenation.FIG.1Bshows an example of a method for protection of a sensitive surface of a substrate. At operation121, a substrate including an environmentally sensitive surface is provided. The surface may be a planar surface or include one or more pillars, holes, and trenches, including HAR structures. Examples of substrate surfaces that can be sensitive to environmental queue time effects include silicon, silicon germanium, and germanium structures such as fins and nanowires, metal surfaces including but not limited to copper, cobalt, titanium, titanium nitride, tungsten or molybdenum, and/or other structures and materials. The surface is then coated with a solution including an SRP in an operation123. The substrate is then dried in an operation125, forming a protective coating including SRP on the sensitive substrate. The substrate can then be stored in ambient conditions in an operation127. When ready for further processing, the substrate is exposed to a stimulus that degrades all or a top portion of the SRP in an operation129. As described further below, operation129may involve controlled exposure to a compound or to two reactants that react to form a compound that degrades the SRP. The stimulus is any compound that scissions bonds of the SRP to degrade it. In some embodiments, the compound is a relatively strong add or base. Volatile monomers or fragments from the degraded polymer can then be removed from the structure in an operation131. If SRP is still present, operations129and131are repeated one or more times to fully remove the SRP in an operation133. The amount of removed in each repetition may be the same or different. FIGS.1A and15are flow diagrams showing certain operations in examples semiconductor fabrication processes that use SRPs, though the methods described herein are not limited to particular applications but may be used with any application in which SRPs are removed from any surface. The thickness of an SRP film before any removal may be expressed as a total thickness (Ttotal). If the thickness varies across a surface, Ttotalis the maximum thickness. In certain embodiments of the methods described herein, an amount of SRP that is removed at any one removal operation is less than Ttotal, i.e., the SRP is removed portion by portion in multiple removal cycles. In other embodiments, all of the SRP may be removed in a cycle. In some embodiments, the SRP is directly exposed to pulses of a vapor phase compound (e.g., a base or acid) that can degrade the SRP. For example, hydrogen bromide (HBr), hydrogen chloride (HCl), hydrogen fluoride (HF), hydrogen iodide (HI), nitric acid (HNO3), formic acid (CH2O2), acetic acid (CH3COOH), formonitrile (HCN), or ammonia (NH3), various methyl or ethyl amines gas or vapor may be used. In some examples, when HBr vapor is used, the substrate is maintained at a pressure in a range from 5 mT to 5000 mT and a temperature in a range from 0° C. to 100° C. In some examples, the substrate is maintained at a pressure in a range from 750 mT to 1500 mT and a temperature in a range from 35° C. to ° C. In some examples, the temperature of the substrate is maintained at a pressure of 1000 mT and a temperature of 60° C. The amount of acidic vapor or vapor of other compound is controlled to limit the diffusion.FIG.3is a process flow diagram showing an example of a method of controlled exposure to a compound to degrade the SRP. A substrate is provided with SRP film in an operation301. Examples of apparatus that the substrate may be provided to are described below with reference to Figure S. In some embodiments, operation301involves providing the substrate to a processing chamber. In other embodiments, the substrate is in the chamber from a previous processing operation. The SRP may be provided in a variety of forms—for example, in a gap between features of a structure or as blanket film on all or part of a substrate. A compound is pulsed into the chamber in an operation303. The partial pressure of the vapor and/or the pulse time can be controlled to control the overall exposure to the vapor and the diffusion depth. The chamber can be purged in an operation305, Purging can involve evacuating the chamber and/or flowing inert gas to be swept out through the chamber. Such a gas may be, for example, continuously flowing including during operation303or may be itself pulsed into the chamber. During operation305volatilized monomer or SRP fragment may be pumped or purged out of the chamber. Operations303and305are repeated until the SRP is removed in an operation307. As indicated above, in some embodiments, the SRP is exposed to reactants sequentially in each cycle. This can provide additional control over the process and may be implemented in various ways. In some embodiments, diffusion of both reactants is tightly controlled. This can provide additional control over removal process as the film will only degrade to a depth where both reactants are present. Thus, if one of the two reactants diffuses more than targeted, diffusion of the other reactant can still control the amount of film removed.FIG.4shows an example of a process flow that may be used in accordance with embodiments. A substrate is provided with SRP film in an operation401, as described above with respect to operation301inFIG.3. At this stage, prior to removal, the SRP film has a thickness Ttotal. A first reactant is pulsed into the chamber in an operation403. The substrate temperature and the partial pressure of the vapor and/or the pulse time can be controlled to control the overall exposure to the vapor and the diffusion depth. As a result of operation403, the first reactant diffuses through a top portion of the SRP film. The chamber can be purged in an operation405. Purging can involve evacuating the chamber and/or flowing inert gas to be swept out through the chamber. Such a gas may be, for example, continuously flowing including during operation403or may be itself pulsed into the chamber. A second reactant is then pulsed in operation407. Like in operation403, the substrate temperature and partial pressure of the vapor and/or pulse time can be controlled to limit the diffusion depth. The first reactant and the second reactant react to form a compound that itself reacts with the SRP to scission its bonds. The SRP is degraded to the depth that both reactants diffused. The chamber can be purged in an operation409as described above. During operation409volatilized monomer or SRP fragment may be pumped or purged out of the chamber. Operations403-409are repeated until the SRP is removed in an operation411. In some embodiments, operation411may not be performed. For example, in a surface protection application where bracing HAR features is not a concern, a single cycle may be sufficient to remove the SRP. In such cases, the reactants may be diffused throughout the entire thickness of the film in operations403and407. In the example ofFIG.4, the target diffusion depth of each reactant may be the same or different.FIG.5shows examples of different embodiments, First, at501, a sequence of side cross-sectional views of a HAR structure filled with SRP is shown. The sequence shows two cycles of SRP removal according in an example of a method according toFIG.4in which each reactant is targeted to diffuse to the same depth. A first pulse of reactant1(R1) results in diffusion to a depth D1followed by a first pulse of reactant2(R2) that results in diffusion to D1. The reactants react, forming a compound that degrades the SRP to D1. The degraded SRP is removed leaving the gap unfilled to D1. The cycle repeats removing SRP to a depth D2. The cycles can continue until the SRP is removed. At503, another sequence of side cross-sectional views of a HAR gap filled with SRP is shown. The sequence shows two cycles of SRP removal according in an example of a method according toFIG.4in which each reactant is targeted to diffuse to a depth beyond the diffusion depth of the previous reactant pulse. A first pulse of reactant1(R1) results in diffusion to a depth D1followed by a first pulse of reactant2(R2) that results in diffusion to D2. The reactants react, forming a compound that degrades the SRP to D1, and leaves unreacted reactant R2to a depth D2. The degraded SRP is removed leaving the gap unfilled to D1with unreacted reactant R2present in the SRP to D2. The next reactant pulse R1is done to a target depth D3. The reactants react, forming a compound that degrades the SRP to D2, and leaves unreacted reactant R1to a depth D3. The degraded SRP is removed leaving the gap unfilled to D2with unreacted reactant R1present in the SRP to D3. The next reactant pulse R2is done to a target depth D4. The reactants react, forming a compound that degrades the SRP to D3, and leaves unreacted reactant R2to a depth D4. The cycles can continue until the SRP is removed. As can be seen by comparing sequence503to sequence501, allowing each pulse of reactant to diffuse further into the SRP than the previous reactant pulse can reduce the number of cycles, though each pulse may take longer. In some embodiments, the SRP is exposed to a first reactant, which is allowed to diffuse throughout all of or a first portion of the SRP, followed by multiple pulses of the second reactant, each of which results in diffusion of the second reactant and SRP degradation in only a top portion of the SRP.FIG.6shows an example of a process flow that may be used in accordance with embodiments. A substrate is provided with SRP film in an operation601, as described above with respect to operation301inFIG.3. A first reactant is pulsed into the chamber in an operation603. The substrate temperature and partial pressure of the vapor and/or the pulse time can be controlled to control the overall exposure to the vapor and the diffusion depth. As a result of operation603, the first reactant diffuses through the SRP film to a target diffusion depth. In some embodiments, the target diffusion depth may be the entire depth of the SRP film, i.e., Ttotal. In other embodiments, it may be less than the entire depth, e.g., half Ttotal, one quarter of the Ttotal, etc. The chamber can be purged in an operation605. Purging can involve evacuating the chamber and/or flowing inert gas to be swept out through the chamber. Such a gas may be, for example, continuously flowing including during operation603or may be itself pulsed into the chamber. A second reactant is then pulsed in operation607. In operation607, the target diffusion depth is less than that for the first reactant in operation603. For example, if the first reactant diffused throughout the entire depth or half the entire depth in operation603, the target diffusion depth in operation607may be one-fifth or one-fourth of the depth. The first reactant and the second reactant react to form a compound that itself reacts with the SRP to scissions its bonds. The SRP is degraded only to the depth that the second reactant diffused. Thus, the second reactant diffusion depth controls the overall removal rate. The chamber can be purged in an operation609as described above. During operation609volatilized monomer or SRP fragment may be pumped or purged out of the chamber. In an operation611, operations607and609are repeated until the first reactant is consumed. In embodiments in which the first reactant diffuses through the entire film, the SRP may be completely removed after operation611. In other embodiments, in an operation613, operations603-611may be repeated one or more times until the SRP is completely removed. FIG.7shows examples of different embodiments according to the method described inFIG.6. First, at701, a sequence of side cross-sectional views of a HAR structure filled with SRP is shown. The sequence shows multiple cycles of SRP removal according in an example of a method according toFIG.6in which the first reactant is targeted to diffuse to entire depth of the SRP. A first pulse of reactant2(R2) results in diffusion to a depth D1, The reactants react, forming a compound that degrades the SRP to D1. The degraded SRP is removed leaving the gap unfilled to D1, The R2-removal cycle repeats removing SRP to a depth D2, The cycles can continue until the SRP is removed. At703, another sequence of side cross-sectional views of a HAR structure filled with SRP is shown. The sequence shows multiple cycles of SRP removal according in an example of a method according toFIG.6in which the first reactant is targeted to diffuse to half the depth of the SRP. A first pulse of reactant2(R2) results in diffusion to a depth D1. The reactants react, forming a compound that degrades the SRP to D1. The degraded SRP is removed leaving the gap unfilled to D1. The R2—removal cycle repeats removing SRP to a depth D2. The cycles can continue until the SRP is removed from half the gap depth. Reactant1is then pulsed again to diffuse to the bottom of the gap. The R2—removal cycles can then be repeated (not shown) until the film is completely removed. Stimulus Compounds and Reactants Examples of compounds that may be used to degrade SRPs includes adds (e.g., having a pKa of less than 7, and in some embodiments less than 4, or less than 2) and bases (e.g., having a pKb of less than 7, and in some embodiments, less than 4 or less than 2). Examples of reactants which can be pulsed to in an alternate fashion to produce compounds which are effective to scission SRPs include SO2(sulfur dioxide) and water (H2O) which react to form sulfurous acid (H2SO3), nitrogen dioxide (NO2) and water to form nitric acid (HNO3), carbon dioxide (CO2) and water to form carbonic acid (H2CO3), and ammonia (NH3) and water to form ammonium hydroxide (NH4OH). Other oxides may react with water or another reactant to form acids or bases. In some embodiments, reactants that form hydrogen bonds (e.g., H2O or NH3) may be used as the first reactant in a scheme such as shown inFIGS.6and7. This is because hydrogen bonding may be useful for having the reactant adsorb in the film once diffused. According to various embodiments, the reaction may be catalyzed or uncatalyzed. In some embodiments, a catalyst (e.g., a thermally activated catalyst) may be provided in the SRP, delivered with a reactant, or introduced as a separate pulse. However, in many embodiments, the reaction is uncatalyzed such that SRP is provided free of catalysts. This can facilitate SRP removal. In some embodiments, the reaction is byproduct-free. SRPs Example of SRPs are provided below. However, the methods described herein may be used with any SRPs. In some embodiments, the SRPs are copolymers including poly(aldehydes). In particular embodiments, they may be self-immolative polymers as described in U.S. Patent Publication No. 2018/0155483, which was published on Jun. 7, 2018 and which is hereby incorporated herein by reference in its entirety. Examples of copolymers in that reference include those of Formula I: wherein R is substituted or unsubstituted C1-C20alkyl, C1-C20alkoxyl, C2-C20alkenyl, C2-C20alkynyl, C6-C10heteroaryl, C3-C10cycloalkyl, C3-C10cycloalkenyl, C3-C10heterocycloalkyl, or C3-C10heterocycloalkenyl; and, when substituted, R is substituted with C1-C20alkyl, C1-C20alkoxy, C2-C20alkenyl, C2-C20alkynyl, C6-C10aryl, C6-C10heteroaryl, aldehyde, amino, sulfonic acid, sulfinic acid, fluoroacid, phosphoric acid, ether, halide, hydroxy, ketone, nitro, cyano, azido, silyl, sulfonyl, sulfinyl, or thiol. In particular embodiments, the SRPs are cyclic copolymers of the phthalaldehyde monomer with a second aldehyde such as ethanal, propanal, or butanal. Examples of such copolymers are given in U.S. Patent Publication No. 2018/015548 as Formula II: Specific examples in U.S. Patent Publication No. 2018/015548 include copolymers of PHA and one or more of acetaldehyde, propanal, butanal, pentanal, hexanal, heptanal, octanal, nonanal, decanal, undecanal, propenal, butenal, pentenal, hexenal, heptanal, octenal, nonenal, decenal, undecenal, and any combination thereof. The SRPs may also be any appropriate linear or cyclic copolymer including the pure phthalaldehyde homopolymer. It also may be a homopolymer of poly(phthalaldehyde) derivatives such as poly(4,5-dichlorophthalaldehyde). Apparatus The removal processes described may be implemented in a chamber which may be part of a substrate processing system. The substrate processing system may further include one or more additional substrate processing tools used to process substrates including deposition of SRPs and upstream and downstream processing. Referring now toFIG.8, a substrate processing system800includes one or more substrate processing tools802(substrate processing tools802aand802bare shown for illustration purposes) and substrate buffer830or other substrate storage. Each of the substrate processing tools802aand802bincludes a plurality of processing chambers804a,804b,804c, etc. (collectively processing chambers804). For example only, each of the processing chambers804may be configured to perform a substrate treatment. In some examples, the substrates may be loaded into one of the processing chambers804, processed, and then moved to one or more other ones of the processing chambers804and/or removed from the substrate processing tool800(e.g., if all perform the same treatment). Substrates to be processed are loaded into the substrate processing tools802aand802bvia ports of a loading station of an atmosphere-to-vacuum (ATV) transfer module808. In some examples, the ATV transfer module708includes an equipment front end module (EFEM). The substrates are then transferred into one or more of the processing chambers804, For example, a transfer robot812is arranged to transfer substrates from loading stations816to load locks820. A vacuum transfer robot824of a vacuum transfer module828is arranged to transfer substrates from the load locks820to the various processing chambers804. After processing in one or more of the substrate processing tools802aand802b, the substrates may be transported outside of a vacuum environment. For example, the substrates may be moved to a location for storage (such as the substrate buffer830). In other examples, the substrates may be moved directly from the substrate processing tool to another substrate processing tool for further processing or from the storage buffer830to another substrate processing tool for further processing. Exposure of the substrate to ambient conditions may cause defects or otherwise adversely impact downstream processing. A sacrificial protective layer including an SRP can be added to the substrate prior to exposure to ambient conditions. In some examples, the sacrificial protective layer is applied in the substrate processing tool prior to transferring the substrate to the substrate buffer for storage or to another substrate processing tool. In other examples, the sacrificial protective layer is applied in another processing chamber (not associated with the substrate processing tool). Prior to performing another treatment on the substrate, the sacrificial protective layer is removed as described herein. For example, the substrate may be transferred to the substrate processing tool802bafter a period of storage in the storage buffer830or after processing in the substrate processing tool802a. The sacrificial protective layer may be removed in one of the processing chambers in the substrate processing tool802b, or another processing chamber (not associated with the substrate processing tool802b). In some embodiments, the sacrificial protective layer is removed in a load lock820. In some examples, the sacrificial protective layer is applied by a processing chamber in the same substrate processing tool (that performed substrate treatment) prior to exposure to ambient conditions. Since the substrate processing tool operates at vacuum, exposure of the substrate to ambient conditions is prevented. In some examples, the sacrificial layer is deposited after a wet clean process. In this case, oxides and residues may be removed by the wet clean process and the sacrificial layer is deposited in sequence prior to drying the wafer or immediately after drying the wafer. In some examples, this process is not done under vacuum and is done without any exposure of the dry pristine surface to the ambient. In other examples, the substrate is transported from the substrate processing tool to another processing chamber located outside of the substrate processing tool that adds the sacrificial protective layer. Using this approach limits or reduces the period of exposure of the substrate to ambient conditions. Exposure is limited to a brief period of transport from the substrate processing tool to the processing chamber where the sacrificial protective layer is applied. Storage of the substrate may be performed for longer periods without additional exposure to ambient conditions. Subsequently, the sacrificial protective layer may be removed prior to further processing. In some examples, the sacrificial protective layer is removed in another substrate processing tool under vacuum conditions prior to substrate treatment in processing chambers of the same substrate processing tool. In other examples, the substrate is transported to a processing chamber that removes the sacrificial protective layer and then to the substrate processing tool for further processing. This approach also limits exposure to ambient conditions between the processing chamber and the substrate processing tool or other environment. In one example, the sacrificial protective layer is formed immediately after etch, deposition, or other process by exposing the substrate to a small molecule vapor that condenses on the surface to form a film. This can be performed directly inside the tool in which the etch or deposition occurred (e.g., substrate processing tool802a) and may occur in the same processing chamber in which the etch or deposition occurred. The substrate is then taken to the next tool for processing (e.g., substrate processing tool802b). Once the substrate is again no longer exposed to ambient conditions (for example by bringing the substrate under vacuum or an atmosphere purged with an inert gas), vacuum and compounds, and in some cases, other stimuli, as described above are applied to induce the film to degrade and be removed from the substrate. This may take place inside of a processing chamber as described above (e.g., process chamber804aof substrate processing chamber802b). In various embodiments, a system controller is employed to control process conditions during processing including during the SRP removal. The controller will typically include one or more memory devices and one or more processors. A processor may include a CPU or computer, analog and/or digital input/output connections, stepper motor controller boards, etc. The controller may control all the activities of a removal apparatus. The system controller executes system control software, including sets of instructions for controlling the timing, mixture of gases, chamber pressure, chamber temperature, wafer temperature, wafer chuck or pedestal position, plasma power, and other parameters of a particular process. Other computer programs stored on memory devices associated with the controller may be employed in some embodiments. Typically, there will be a user interface associated with the controller. The user interface may include a display screen, graphical software displays of the apparatus and/or process conditions, and user input devices such as pointing devices, keyboards, touch screens, microphones, etc. System control logic may be configured in any suitable way. In general, the logic can be designed or configured in hardware and/or software. The instructions for controlling the drive circuitry may be hard coded or provided as software. The instructions may be provided by “programming.” Such programming is understood to include logic of any form, including hard coded logic in digital signal processors, application-specific integrated circuits, and other devices which have specific algorithms implemented as hardware. Programming is also understood to include software or firmware instructions that may be executed on a general purpose processor. System control software may be coded in any suitable computer readable programming language. The computer program code for controlling the reactant pulses and purge gas flows and other processes in a process sequence can be written in any conventional computer readable programming language: for example, assembly language, C, C++, Pascal, Fortran, or others. Compiled object code or script is executed by the processor to perform the tasks identified in the program. Also as indicated, the program code may be hard coded. The controller parameters relate to process conditions, such as, for example, process gas composition and flow rates, temperature, pressure, substrate temperature, and plasma power. These parameters are provided to the user in the form of a recipe and may be entered utilizing the user interface. Signals for monitoring the process may be provided by analog and/or digital input connections of the system controller. The signals for controlling the process are output on the analog and digital output connections of the system. The system software may be designed or configured in many ways. For example, various chamber component subroutines or control objects may be written to control operation of the chamber components necessary to carry out the deposition processes in accordance with the disclosed embodiments. Examples of programs or sections of programs for this purpose include substrate positioning code, process gas control code, pressure control code, and heater control code. In some implementations, a controller is part of a system, which may be part of the above-described examples. Such systems can include semiconductor processing equipment, including a processing tool or tools, chamber or chambers, a platform or platforms for processing, and/or specific processing components (a wafer pedestal, a gas flow system, etc.). These systems may be integrated with electronics for controlling their operation before, during, and after processing of a semiconductor wafer or substrate. The electronics may be referred to as the “controller,” which may control various components or subparts of the system or systems. The controller, depending on the processing requirements and/or the type of system, may be programmed to control any of the processes disclosed herein, including the delivery of processing gases, temperature settings (e.g., heating and/or cooling), pressure settings, vacuum settings, power settings, flow rate settings, fluid delivery settings, positional and operation settings, wafer transfers into and out of a tool and other transfer tools and/or load locks connected to or interfaced with a specific system. Broadly speaking, the controller may be defined as electronics having various integrated circuits, logic, memory, and/or software that receive instructions, issue instructions, control operation, enable cleaning operations, enable endpoint measurements, and the like. The integrated circuits may include chips in the form of firmware that store program instructions, digital signal processors (DSPs), chips defined as application specific integrated circuits (ASICs), and/or one or more microprocessors, or microcontrollers that execute program instructions (e.g., software). Program instructions may be instructions communicated to the controller in the form of various individual settings (or program files), defining operational parameters for carrying out a particular process on or for a semiconductor wafer or to a system. The operational parameters may, in some embodiments, be part of a recipe defined by process engineers to accomplish one or more processing steps during the fabrication of one or more layers, materials, metals, oxides, silicon, silicon dioxide, surfaces, circuits, and/or dies of a wafer. The controller, in some implementations, may be a part of or coupled to a computer that is integrated with, coupled to the system, otherwise networked to the system, or a combination thereof. For example, the controller may be in the “cloud” or all or a part of a fab host computer system, which can allow for remote access of the wafer processing. The computer may enable remote access to the system to monitor current progress of fabrication operations, examine a history of past fabrication operations, examine trends or performance metrics from a plurality of fabrication operations, to change parameters of current processing, to set processing steps to follow a current processing, or to start a new process. In some examples, a remote computer (e.g. a server) can provide process recipes to a system over a network, which may include a local network or the internet. The remote computer may include a user interface that enables entry or programming of parameters and/or settings, which are then communicated to the system from the remote computer. In some examples, the controller receives instructions in the form of data, which specify parameters for each of the processing steps to be performed during one or more operations. The parameters may be specific to the type of process to be performed and the type of tool that the controller is configured to interface with or control, Thus, as described above, the controller may be distributed, such as by comprising one or more discrete controllers that are networked together and working towards a common purpose, such as the processes and controls described herein. An example of a distributed controller for such purposes would be one or more integrated circuits on a chamber in communication with one or more integrated circuits located remotely (such as at the platform level or as part of a remote computer) that combine to control a process on the chamber. Without limitation, example systems may include a plasma etch chamber or module, a deposition chamber or module, a spin-rinse chamber or module, a metal plating chamber or module, a clean chamber or module, a bevel edge etch chamber or module, a PVD chamber or module, a CVD chamber or module, an ALD chamber or module, an atomic layer etch (ALE) chamber or module, an ion implantation chamber or module, a track chamber or module, and any other semiconductor processing systems that may be associated or used in the fabrication and/or manufacturing of semiconductor wafers. As noted above, depending on the process step or steps to be performed by the tool, the controller might communicate with one or more of other tool circuits or modules, other tool components, cluster tools, other tool interfaces, adjacent tools, neighboring tools, tools located throughout a factory, a main computer, another controller, or tools used in material transport that bring containers of wafers to and from tool locations and/or load ports in a semiconductor manufacturing factory. The controller may include various programs. A substrate positioning program may include program code for controlling chamber components that are used to load the substrate onto a pedestal or chuck and to control the spacing between the substrate and other parts of the chamber such as a gas inlet and/or target. A process gas control program may include code for controlling gas composition, flow rates, pulse times, and optionally for flowing gas into the chamber. A pressure control program may include code for controlling the pressure in the chamber by regulating, e.g., a throttle valve in the exhaust system of the chamber. A heater control program may include code for controlling the current to a heating unit that is used to heat the substrate. Alternatively, the heater control program may control delivery of a heat transfer gas such as helium to the wafer chuck. A plasma power program may control plasma power. Examples of chamber sensors that may be monitored during removal include mass flow controllers, pressure sensors such as manometers, and thermocouples located in the pedestal or chuck. Appropriately programmed feedback and control algorithms may be used with data from these sensors to maintain desired process conditions. The foregoing describes implementation of disclosed embodiments in a single or multi-chamber semiconductor processing tool. The apparatus and process described herein may be used in conjunction with lithographic patterning tools or processes, for example, for the fabrication or manufacture of semiconductor devices, displays, LEDs, photovoltaic panels, and the like. Typically, though not necessarily, such tools/processes will be used or conducted together in a common fabrication facility, Lithographic patterning of a film typically comprises some or all of the following steps, each step provided with a number of possible tools: (1) application of photoresist on a workpiece, i.e., substrate, using a spin-on or spray-on tool; (2) curing of photoresist using a hot plate or furnace or UV curing tool; (3) exposing the photoresist to visible or UV or x-ray light with a tool such as a wafer stepper; (4) developing the resist so as to selectively remove resist and thereby pattern it using a tool such as a wet bench; (5) transferring the resist pattern into an underlying film or workpiece by using a dry or plasma-assisted etching tool; and (6) removing the resist using a tool such as an RF or microwave plasma resist stripper. Although the foregoing embodiments have been described in some detail for purposes of clarity of understanding, it will be apparent that certain changes and modifications may be practiced within the scope of the appended claims. It should be noted that there are many alternative ways of implementing the processes, systems, and apparatus of the present embodiments. Accordingly, the present embodiments are to be considered as illustrative and not restrictive, and the embodiments are not to be limited to the details given herein. | 40,585 |
11862474 | DETAILED DESCRIPTION In the following detailed description, reference is made to the accompanying drawings, which form a part of the description. In the drawings, similar symbols typically identify similar components, unless context dictates otherwise. Furthermore, unless otherwise noted, the description of each successive drawing may reference features from one or more of the previous drawings to provide clearer context and a more substantive explanation of the current exemplary embodiment. Still, the exemplary embodiments described in the detailed description, drawings, and claims are not meant to be limiting. Other embodiments may be utilized, and other changes may be made, without departing from the spirit or scope of the subject matter presented herein. It will be readily understood that the aspects of the present disclosure, as generally described herein and illustrated in the drawings, may be arranged, substituted, combined, separated, and designed in a wide variety of different configurations, all of which are explicitly contemplated herein. Hereinafter, exemplary embodiments of a substrate processing apparatus and a substrate processing method according to the present disclosure will be described in detail with reference to the accompanying drawings. The substrate processing apparatus and the substrate processing method of the present disclosure are not limited to the exemplary embodiments to be described below. Further, it should be noted that the drawings are schematic and relations in sizes of individual components and ratios of the individual components may sometimes be different from actual values. Even between the drawings, there may exist parts having different dimensional relationships or different ratios. <Outline of Substrate Processing System> FIG.1is a diagram illustrating a schematic configuration of a substrate processing system1(an example of a substrate processing apparatus) according to an exemplary embodiment. In the following, in order to clarify positional relationships, the X-axis, Y-axis and Z-axis which are orthogonal to each other will be defined, and the positive Z-axis direction will be regarded as a vertically upward direction. The substrate processing system1includes a carry-in/out station2and a processing station3. The carry-in/out station2and the processing station3are provided adjacent to each other. The substrate processing system1is configured to perform an etching processing on a semiconductor wafer W (hereinafter, simply referred to as “wafer W”). Films formed on the wafer W (an example of a substrate) on which the etching processing is to be performed are titanium nitride and tungsten. Further, a processing liquid for the etching processing is dilute sulfuric acid prepared by diluting sulfuric acid with pure water, for example, DIW (DeIonized Water). The dilute sulfuric acid has a predetermined concentration in which a ratio between the sulfuric acid and the pure water ranges from 1:1 to 20:1. Further, the processing liquid may be SPM (an aqueous solution of sulfuric acid and hydrogen peroxide). The carry-in/out station2is provided with a carrier placing section11and a transfer section12. In the carrier placing section11, a plurality of carriers C is placed to accommodate a plurality of substrates (semiconductor wafers W (hereinafter, referred to as “wafers W”) in the present exemplary embodiment) horizontally. The transfer section12is provided adjacent to the carrier placing section11, and provided with a substrate transfer device13and a delivery unit14. The substrate transfer device13is provided with a wafer holding mechanism configured to hold the wafer W. Further, the substrate transfer device13is movable horizontally and vertically and pivotable around a vertical axis, and transfers the wafers W between the carriers C and the delivery unit14by using the wafer holding mechanism. The processing station3is provided adjacent to the transfer section12. The processing station3is provided with a transfer section15and a plurality of processing units16. The processing units16are arranged at both sides of the transfer section15 The transfer section15is provided with a substrate transfer device17therein. The substrate transfer device17is provided with a wafer holding mechanism configured to hold the wafer W. Further, the substrate transfer device17is movable horizontally and vertically and pivotable around a vertical axis. The substrate transfer device17transfers the wafers W between the delivery unit14and the processing units16by using the wafer holding mechanism. The processing units16perform a predetermined substrate processing on the wafers W transferred by the substrate transfer device17. Further, the substrate processing system1is provided with a control device4. The control device4is, for example, a computer, and includes a controller18and a storage19. The storage19stores a program that controls various processings performed in the substrate processing system1. The controller18controls the operations of the substrate processing system1by reading and executing the program stored in the storage19. Details of the control device4will be elaborated later. Further, the program may be recorded in a computer-readable recording medium, and installed from the recording medium to the storage19of the control device4. The computer-readable recording medium may be, for example, a hard disc (HD), a flexible disc (FD), a compact disc (CD), a magneto optical disc (MO), or a memory card. In the substrate processing system1configured as described above, the substrate transfer device13of the carry-in/out station2first takes out a wafer W from a carrier C placed in the carrier placing section11, and then places the taken wafer W on the delivery unit14. The wafer W placed on the delivery unit14is taken out from the delivery unit14by the substrate transfer device17of the processing station3and carried into a processing unit16. The wafer W carried into the processing unit16is processed by the processing unit16, and then, carried out from the processing unit16and placed on the delivery unit14by the substrate transfer device17. After the processing of placing the wafer W on the delivery unit14, the wafer W returns to the carrier C of the carrier placing section11by the substrate transfer device13. <Configuration of Processing Unit> Now, a configuration of the processing unit16will be described with reference toFIG.2.FIG.2is a schematic diagram illustrating a specific configuration example of the processing unit16according to the exemplary embodiment. As depicted inFIG.2, the processing unit16includes a chamber20, a substrate processing unit30, a liquid supply40, a recovery cup50, and a temperature sensor60. The chamber20accommodates therein the substrate processing unit30, the liquid supply40, and the recovery cup50. A FFU (Fan Filter Unit)21is provided at a ceiling of the chamber20. The FFU21creates a downflow within the chamber20. The substrate processing unit30is equipped with a holder31, a supporting column32, and a driver33, and configured to perform a liquid processing on the wafer W placed thereon. The holder31is configured to hold the wafer W horizontally. The supporting column32is a vertically extending member. A base end of the supporting column32is rotatably supported by the driver33, and the supporting column32supports the holder31horizontally at a leading end thereof. The driver33is configured to rotate the supporting column32around a vertical axis. In the substrate processing unit30, by rotating the supporting column32with the driver33, the holder31supported by the supporting column32is rotated, so that the wafer W held by the holder31is rotated. A holding member311configured to hold the wafer W from the lateral side thereof is provided at a top surface of the holder31of the substrate processing unit30. The wafer W is horizontally held by this holding member311while being slightly spaced apart from the top surface of the holder31. Further, the wafer W is held by the holder31with a front surface thereof to be subjected to a substrate processing facing upwards. The liquid supply40is configured to supply a processing liquid onto the wafer W. The liquid supply40is equipped with a nozzle41, an arm42configured to support the nozzle41horizontally, and a rotating/elevating mechanism43configured to rotate and move the arm42up and down. The nozzle41is connected to a discharge line130. The nozzle41is configured to discharge the processing liquid supplied through the discharge line130. A pipeline configuration of the substrate processing system1including this discharge line130will be elaborated later. Further, though the present exemplary is described for an example where the single nozzle41is provided in the processing unit16, the number of the nozzle provided in the processing unit16is not limited to one. Further, though the present exemplary is described for an example where the nozzle41is disposed above (at a side of a front surface of) the wafer W in the processing unit16, the nozzle may be disposed under (at a side of a rear surface of) the wafer W. The recovery cup50is disposed to surround the holder31, and collects the processing liquid scattered from the wafer W by the rotation of the holder31. A drain port51is formed at a bottom of the recovery cup50, and the processing liquid collected by the recovery cup50is drained from the drain port51to the outside of the processing unit16. Further, an exhaust port52is formed at the bottom of the recovery cup50to exhaust a gas supplied from the FFU21to the outside of the processing unit16. The temperature sensor60(an example of a temperature detector) is configured to detect a temperature of the wafer W (an example of a substrate) onto which the processing liquid is discharged. To elaborate, the temperature sensor60is configured to measure a surface temperature of the wafer W. The temperature sensor60may be, by way of example, but not imitation, a radiation thermometer. The temperature sensor60is mounted to the chamber20with a mounting member61therebetween. The temperature sensor60measures a temperature of a preset position of the wafer W. The preset position is a previously set position and may be, for example, a center of the wafer W. The temperature sensor60may be fixed to the arm42. Further, the temperature sensor60may be fixed to an arm different from the arm42. <Pipeline Configuration of Substrate Processing System> Now, a pipeline configuration of the substrate processing system1connected to the processing unit16will be explained with reference toFIG.3.FIG.3is a schematic diagram illustrating the pipeline configuration of the substrate processing system1according to the exemplary embodiment. Here, the pipeline configuration for supplying the processing liquid will be explained. Besides this pipeline system for the processing liquid, the processing unit16is equipped with, by way of example, a pipeline configuration and a nozzle for supplying DIW onto the wafer W in a rinsing processing and a pipeline configuration and a nozzle for supplying IPA onto the wafer W in a drying processing. In the substrate processing system1, dilute sulfuric acid produced by a joint unit120is supplied into the processing unit16through the discharge line130. Sulfuric acid from a chemical liquid supply100and DIW from a DIW supply110are supplied into the joint unit120. In the joint unit120, the sulfuric acid and the DIW are mixed, so that the dilute sulfuric acid is produced. The chemical liquid supply100is configured to supply the sulfuric acid to the joint unit120. The chemical liquid supply100is equipped with a chemical liquid source101, a supply line102, a heater103, and a flow rate controller104. The sulfuric acid supplied into the supply line102from the chemical liquid source101is heated by a heater103to a first preset temperature. A flow rate of the sulfuric acid heated to the first preset temperature is adjusted by the flow rate controller104. The first preset temperature is a previously set temperature which allows a temperature of the processing liquid to become equal to or higher than 50° C., and is set to be equal to or lower than a boiling point of the processing liquid. The DIW supply110is configured to supply the DIW to the joint unit120. The DIW supply110is equipped with a DIW source111, a supply line112, a heater113, and a flow rate controller114. The DIW supplied into the supply line112from the DIW source111is heated by a heater113to a second preset temperature. A flow rate of the DIW heated to the second preset temperature is adjusted by the flow rate controller114. The second preset temperature is a previously set temperature which allows the temperature of the processing liquid to become equal to or higher than 50° C., and is set to be equal to or lower than the boiling point of the processing liquid. In the substrate processing system1, by using the flow rate controllers104and114, a concentration of the processing liquid produced in the joint unit120is adjusted to a preset concentration. The discharge line130is provided with a valve131. If the valve131is opened, the processing liquid adjusted to have the preset concentration is supplied to the wafer W. If the valve131is closed, the processing liquid is not supplied to the wafer W. The valve131is opened/closed by a motor (not shown) or the like. Further, in the substrate processing system1, by stopping the flow of the sulfuric acid in the flow rate controller104provided in the supply line102, the DIW may be supplied to the wafer W via the discharge line130. <Details of Control Device> Now, details of the control device4which controls the substrate processing system1will be explained with reference toFIG.4.FIG.4is a block diagram illustrating a schematic configuration of the control device4according to the exemplary embodiment. As stated above, the control device4includes the controller18and the storage19. The storage19may be configured by, for example, a semiconductor memory device such as a RAM (Random Access Memory) or a flash memory, or a storage device such as a hard disk or an optical disk. The storage19has a calculation formula storage19a. The calculation formula storage19astores s calculation formula for calculating an etching amount D in an etching processing. The etching amount D can be calculated from a processing time (t1−t0) in the etching processing and an etching rate k by using the expression (1). D=k×(t1−t0) (1) Here, “t1” denotes a supply time of the processing liquid, and “t0” represents a time when the wafer W reaches a target temperature at which the etching is begun. That is, the processing time is a time after the wafer W reaches the target temperature. The target temperature is equal to or higher than 50° C. and equal to or lower than the boiling point of the processing liquid. Further, the etching rate k can be calculated, by using the expression (2), from an average wafer temperature Tave after the wafer W reaches the target temperature. k=a×exp(b×Tave) (2) If “k” of the expression (2) is put in the place of “k” of the expression (1), the following expression (3) is obtained. D=(a×exp(b×Tave))×(t1−t0) (3) Here, “a” and “b” are exponential approximation fitting values. Further, “a” and “b” are calculated by using actual preliminary evaluation data. The preliminary evaluation data refers to data in which an etching processing is performed while varying a temperature of sulfuric acid and a concentration of sulfuric acid and a wafer temperature and an etching amount D′ are obtained under respective conditions. Further, a wafer W used to obtain the preliminary evaluation data is the same as the wafer W on which the etching processing is performed in the substrate processing system1. A measurement point of the temperatures of the wafer W in the preliminary evaluation data is the same as the measurement point of the temperatures detected by the temperature sensor60when the etching processing is performed in the substrate processing system1. First, a time average wafer temperature Tave′ in each condition is calculated from the etching processing time and the temperature of the wafer W. Further, an etching rate k′ in each condition is obtained from the etching processing time and the etching amount D′. Then, a graph in which the time average wafer temperature Tave′ in each condition and the etching rate k′ in each condition are plotted is created as shown inFIG.5, and is approximated by an exponential curve.FIG.5is a diagram showing an exponential curve according to the exemplary embodiment. The aforementioned “a” and “b” are calculated and set based on the approximated exponential curve. As stated above, the calculation formula of the expression (3) (an example of a given calculation formula) is a formula of an exponential function of the temperature of the wafer W and the processing time in the etching processing. The calculation formula storage19astores the calculation formula represented by the expression (3). Further, the calculation formula storage19astores the calculation formula for each etching processing condition, for example, the calculation formula according to the kind of the wafer W on which the etching processing is performed. Referring back toFIG.4, the controller18may be implemented by a CPU (Central Processing Unit) or MPU (Micro Processing Unit) or the like which executes the various programs stored in the storage19by using a RAM as a working area. Further, the controller18may be implemented by an integrated circuit such as, but not limited to, ASIC (Application Specific Integrated Circuit) or a FPGA (Field Programmable Gate Array). The controller18includes an acquisition unit18a, a calculation unit18b, a determination unit18cand an execution unit18d, and implements or carries out a function and an operation of a control processing to be described below. Further, the internal configuration of the controller18is not limited to the example shown inFIG.4, and the controller18may have various other configurations as long as it is capable of carrying out the following control processing. The acquisition unit18ais configured to acquire the information regarding the temperature of the wafer W (hereinafter, referred to as “wafer temperature”) detected by the temperature sensor60. The calculation unit18bis configured to calculate the etching amount D from the acquired wafer temperature by using the calculation formula stored in the calculation formula storage19a. That is, by using the calculation formula (an example of a given calculation formula), the calculation unit18bcalculates the etching amount D of the wafer W (an example of a substrate) based on the wafer temperature (an example of a temperature) detected by the temperature sensor60(an example of a temperature detector). The determination unit18cis configured to determine whether or not to end the etching processing. To elaborate, the determination unit18cmakes a determination upon whether the calculated etching amount D has reached a preset amount. The preset amount is a previously set value, and is an etching amount required for the wafer W. The execution unit18dis configured to perform the etching processing upon the wafer W (an example of the substrate) by the processing liquid based on the etching amount D. The execution unit18dcontrols the supply of the processing liquid upon the wafer W, thus allowing the etching processing to be performed on the wafer W. The execution unit18dcontrols a motor or the like, and performs the opening/closing of the valve131. To elaborate, to start the etching processing, the execution unit18dopens the valve131, thus beginning the supply of the processing liquid onto the wafer W. Further, if it is determined that the etching amount D has reached the preset amount, the execution unit18dcloses the valve131, stopping the supply of the processing liquid upon the wafer W. That is, if the etching amount D reaches the preset amount (given amount), the execution unit18dends the discharge of the processing liquid. Here, the function of the control device4of performing the discharge control of the processing liquid in the etching processing has been described. However, the control device4also performs, besides this discharge control, sulfuric acid temperature adjustment by the heater103and DIW temperature adjustment by the heater113. Furthermore, the control device4performs a rinsing processing and a drying processing as well as the etching processing. As stated above, the control device4calculates the etching amount D based on the wafer temperature by using the calculation formula, and ends the etching processing if the etching amount D reaches the preset amount. Thus, even if there is caused non-uniformity during the etching due to a non-uniform wafer temperature, the etching amount D can be made to reach the preset amount. <Specific Example of Control Processing> Now, a control processing according to the exemplary embodiment will be explained with reference toFIG.6.FIG.6is a flowchart illustrating the control processing according to the exemplary embodiment. The control device4begins the etching processing (S100). To elaborate, the control device4opens the valve131, thus allowing the processing liquid to be supplied to the wafer W. The control device4calculates the etching amount D (S101). To elaborate, the control device4acquires the wafer temperature from the temperature sensor60, and calculates the etching amount D based on the acquired wafer temperature by using the calculation formula. The control device4determines whether the calculated etching amount D has reached the preset amount (S102). If the etching amount D has reached the preset amount (S102: Yes), the control device4ends the etching processing (S103). Specifically, the control device4closes the valve131, thus stopping the discharge of the processing liquid onto the wafer W. If the calculated etching amount D is smaller than the preset amount (S102: No), the control device4carries on the calculation of the etching amount D (S101). Now, the wafer temperature and the etching amount D in the above-stated control processing will be described with reference toFIG.7AtoFIG.7C.FIG.7Ais a first diagram showing the wafer temperature and the etching amount D in the control processing according to the exemplary embodiment.FIG.7Bis a second diagram showing the wafer temperature and the etching amount D in the control processing according to the exemplary embodiment.FIG.7Cis a third diagram showing the wafer temperature and the etching amount D in the control processing according to the exemplary embodiment. If the supply of the processing liquid upon the wafer W is begun (FIG.7A), the temperature of the wafer W increases. If the temperature of the wafer W becomes equal to or higher than a target temperature at a time t0, the etching upon the wafer W by the processing liquid is begun, so that the etching amount D increases. Further, the etching amount D is calculated based on the aforementioned expression (3). As the supply of the processing liquid upon the wafer W is continued and the temperature of the wafer W is maintained equal to or higher than the target temperature, the etching progresses, so that the etching amount D increases (FIG.7B). If the calculated etching amount D reaches the preset amount (FIG.7C), the supply of the processing liquid upon the wafer W is stopped. Then, the temperature of the wafer W falls below the target temperature, so that the etching upon the wafer W is ended. Effects The substrate processing system1(an example of a substrate processing apparatus) includes the temperature sensor60(an example of a temperature detector), the calculation unit18band the execution unit18d. The temperature sensor60detects the temperature of the wafer W (an example of a substrate) onto which the processing liquid is discharged. The calculation unit18dcalculates, by using the calculation formula (given calculation formula), the etching amount D of the wafer W based on the temperature detected by the temperature sensor60. The execution unit18dperforms the etching processing upon the wafer W by the processing liquid based on the etching amount D. Accordingly, the substrate processing system1is capable of calculating the etching amount D based on the temperature of the wafer W and carrying out the etching processing based on the etching amount D. The substrate processing system1performs the etching processing based on the etching amount D even if the temperature of the processing liquid varies due to a minute change in the supply flow rate of the sulfuric acid or the DIW. Therefore, the substrate processing system1is capable of etching the wafer W accurately. Further, the execution unit18dends the supply of the processing liquid if the etching amount D reaches the preset value (an example of a given value). Accordingly, the substrate processing system1is capable of allowing the etching amount D to reach the preset amount even if the non-uniformity is caused during the etching due to the non-uniform wafer temperature. Therefore, the substrate processing system1is capable of etching the wafer W accurately. Furthermore, the calculation formula is a formula of the exponential function of the temperature and the processing time in the etching processing. Thus, the substrate processing system1is capable of calculating the etching amount D accurately, and thus capable of etching the wafer W with high accuracy. Further, the temperature sensor60detects the surface temperature of the wafer W. Accordingly, the substrate processing system1is capable of calculating the etching amount D based on the temperature of the wafer W on which the etching processing is performed. Thus, the substrate processing apparatus1is capable of etching the wafer W accurately. Further, the films formed on the wafer W on which the etching processing is performed are titanium nitride and tungsten. The substrate processing system1is capable of accurately etching the wafer W on which the films of the titanium nitride and the tungsten are formed. Further, the processing liquid is the dilute sulfuric acid prepared by diluting the sulfuric acid with the DIW (an example of pure water). Specifically, the processing liquid has the concentration in which the ratio between the sulfuric acid and the pure water ranges from 1:1 to 20:1. Further, the processing liquid has the temperature equal to or higher than 50° C. and equal to or lower than the boiling point of the processing liquid. Accordingly, the substrate processing system1is capable of etching the titanium nitride while suppressing etching of the tungsten. Modification Examples The substrate processing system1may calculate the etching amount D by using a formula of an exponential function different from the calculation formula of the exponential function represented by the expression (3). The formula of the exponential function is calculated from a correlation between the temperature of the wafer W and the etching amount D′ by using the preliminary evaluation data. By way of example, the substrate processing system1may calculate the etching amount D by using an Arrhenius equation represented by the following expression (4). K/A=exp(−E/RT) (4) “K” denotes a rate constant, and “A” is a frequency factor. Further, “E” indicates an activation energy; “R”, a gas constant; “T”, a temperature of the wafer W. The etching amount D is proportional to a section integration of the processing time of “K/A”. Thus, the etching amount D can be calculated by using the following expression (5). D=a×∫(K/A)dt(5) If the expression (4) is put in the expression (5), the etching amount D can be represented by the following expression (6). D=a×∫(exp(−E/RT))dt(6) Proportionality constants “a” and “E” are calculated and set by using the preliminary evaluation data. Specifically, based on the preliminary evaluation data, “a” is calculated from a gradient of an approximation straight line in a graph on which (∫(exp(−E/RT))dt) is plotted as a horizontal axis and the etching amount D′ is plotted as a vertical axis. Further, a value of “E” is varied, and the value allowing the highest coefficient of determination is calculated as “E”. The calculation formula of the expression (5) is stored in the calculation formula storage19a. The substrate processing system1may calculate the etching amount D by using the expression (5) stored in the calculation formula storage19a. Accordingly, the substrate processing system1is capable of etching the wafer W with high accuracy. Further, the method of measuring the temperature of the wafer W is not limited to using the temperature sensor60as described above. By way of example, in the substrate processing system1, a temperature sensor such as a thermocouple may be provided at a contact portion in contact with the wafer W. Furthermore, the substrate processing system1may measure temperatures of the wafer W at multiple positions. By way of example, the substrate processing system1may measure a temperature of a central portion of the wafer W, a temperature of a peripheral portion of the wafer W, and a temperature of a portion between the central portion and the peripheral portion of the wafer W. In this case, for example, calculation formulas set for the temperatures of the wafer W at the multiple positions are stored in the calculation formula storage19a. By way of example, the substrate processing system1calculates etching amounts D at the multiple positions of the wafer W and performs the etching processing based on the etching amounts D. Furthermore, the substrate processing system1may correct an etching amount D by estimating a difference between the multiple etching amounts D. In addition, the substrate processing system1may supply the processing liquid onto the wafer W while rotating the arm42. Further, the substrate processing system1may measure multiple temperatures of the wafer W by supplying the processing liquid onto the wafer W while rotating the arm42. Accordingly, the substrate processing system1is capable of etching the wafer W accurately. The substrate processing system1is capable of improving the uniformity of the etching amount D within the surface of the wafer W. Moreover, based on the etching amount D, the substrate processing system1may calculate a time taken before the etching processing is finished, and may end the etching processing based on the calculated time. The features of the substrate processing system1according to the exemplary embodiment and the modification examples may be applied in combinations. So far, the exemplary embodiments have been described. However, it should be noted that the above-described exemplary embodiments are illustrative in all aspects and are not anyway limiting. The above-described exemplary embodiments may be omitted, replaced and modified in various ways without departing from the scope and the spirit of claims According to the present disclosure, it is possible to etch the substrate with high accuracy. From the foregoing, it will be appreciated that the various embodiments of the present disclosure have been described herein for the purposes of illustration, and that various modifications may be made without departing from the scope and spirit of the present disclosure. Accordingly, the various embodiments disclosed herein are not intended to be limiting, with the true scope and spirit being indicated by the following claims. | 31,699 |
11862475 | Several of the figures are included as schematics. It is to be understood that the figures are for illustrative purposes, and are not to be considered of scale unless specifically stated to be of scale. Additionally, as schematics, the figures are provided to aid comprehension and may not include all aspects or information compared to realistic representations, and may include exaggerated material for illustrative purposes. In the appended figures, similar components and/or features may have the same reference label. Further, various components of the same type may be distinguished by following the reference label by a letter that distinguishes among the similar components. If only the first reference label is used in the specification, the description is applicable to any one of the similar components having the same first reference label irrespective of the letter. DETAILED DESCRIPTION OF THE INVENTION During plasma enhanced deposition processes, a remote plasma source (RPS) unit may be used to create and strike plasma. However, in some instances, the RPS unit may experience intermittent plasma strike faults, which may cause system downtime across multiple fabrication tools. Such faults may be caused when contaminants enter and poison the RPS unit, impacting the RPS unit's ability to successfully strike plasma. These contaminants may be caused by deposition gas that backstreams into the RPS unit. The deposition gas may change surface morphology of the internal surfaces of the RPS unit and cause failures when trying to strike plasma within the RPS unit. These problems cannot be overcome simply by flowing purge gas through the RPS unit and delivery tube, as this flow is parallel with deposition gas flow from the gasbox and creates a turbulence within the processing chamber. This turbulent flow of purge gas disturbs the flow pattern of deposition gases and results in on-wafer problems, such as lowering the uniformity of the wafer and/or creating more stress on the wafer. Additionally, the use of mechanical valves fails to provide a desirable solution, as radicals cause heat within moving actuators of mechanical valves and cause the mechanical valves to malfunction. The present technology overcomes these challenges by utilizing one or more chamber components that may facilitate positive pressure delivery of a purge gas at positions proximate the RPS unit to prevent deposition gases from backstreaming into the RPS unit. The present technology also provides one or more chamber components that mix the purge gas and deposition gas, rather than simply flowing a purge gas on its own downward from the RPS unit. By mixing the purge gas and deposition gas, any purge gas coming from the RPS unit (or introduced proximate the RPS unit) enters the processing chamber at the same time as the deposition gas and results in better uniformity of deposition gases into the processing region. The present technology utilizes alternative components within the chamber to reduce or eliminate the occurrence of RPS backstreaming. By removing the RPS backstreaming from the chamber, changes to the inner surfaces of the RPS unit are prevented, RPS strike faults may be eliminated, and better uniformity of deposition gases on the wafer may be achieved. Although the disclosure will routinely identify specific etching processes utilizing the disclosed technology, it will be readily understood that the systems and methods are equally applicable to deposition and cleaning processes as may occur in the described chambers. As such, the technology should not be considered to be so limited as for use with etching processes alone. FIG.1shows a top plan view of one embodiment of a processing system100of deposition, etching, baking, and curing chambers according to embodiments. In the figure, a pair of front opening unified pods102supply substrates of a variety of sizes that are received by robotic arms104and placed into a low pressure holding area106before being placed into one of the substrate processing chambers108a-f, positioned in tandem sections109a-c. A second robotic arm110may be used to transport the substrate wafers from the holding area106to the substrate processing chambers108a-fand back. Each substrate processing chamber108a-f, can be outfitted to perform a number of substrate processing operations including formation of stacks of semiconductor materials described herein in addition to plasma-enhanced chemical vapor deposition, atomic layer deposition, physical vapor deposition, etch, pre-clean, degas, orientation, and other substrate processes including, annealing, ashing, etc. The substrate processing chambers108a-fmay include one or more system components for depositing, annealing, curing and/or etching a dielectric or other film on the substrate. In one configuration, two pairs of the processing chambers, e.g.,108c-dand108e-f, may be used to deposit dielectric material on the substrate, and the third pair of processing chambers, e.g.,108a-b, may be used to etch the deposited dielectric. In another configuration, all three pairs of chambers, e.g.,108a-f, may be configured to deposit stacks of alternating dielectric films on the substrate. Any one or more of the processes described may be carried out in chambers separated from the fabrication system shown in different embodiments. It will be appreciated that additional configurations of deposition, etching, annealing, and curing chambers for dielectric films are contemplated by system100. FIG.2shows a schematic cross-sectional view of an exemplary processing system200according to embodiments of the present technology. The system may include a processing chamber205, and a remote plasma source (“RPS”) unit210. The RPS unit210may be stabilized on a platform212having support members214that may couple with the processing chamber205at one or more positions about the processing chamber205. By utilizing additional support members214along with platform212, the weight of the RPS unit210may be properly distributed to protect components from sheer or other stresses related to the weight of the RPS unit210. A delivery tube216may be coupled between or with the RPS unit210and the processing chamber205for delivering one or more precursors to the processing chamber205. A flange adaptor218may be positioned about the delivery tube216in order to provide additional stability and support against the RPS unit210, which may otherwise damage the delivery tube216from the support weight. The flange adaptor218may contact the platform212to provide support for the RPS unit210, additionally so that the weight of the RPS unit210is not borne on the delivery tube216. The processing chamber205may include a gas box220providing access to the processing chamber205. The gas box220may define an access to the processing chamber205, and in embodiments, the access may be centrally defined or located within the gas box220. The delivery tube216may be positioned or coupled within the access of the gas box220providing a precursor path between the RPS unit210and the interior of the processing chamber205. The flange adaptor218may also contact the top plate220to distribute at least a portion of the weight of the RPS unit210, to prevent or reduce stress on the delivery tube216. In embodiments a spacer222may at least partially define the processing chamber205exterior and interior walls. A gas distribution assembly225may be positioned within the processing chamber205proximate the delivery tube216, and the gas distribution assembly225may allow distribution of precursors or plasma effluents into the processing chamber205. A pumping liner230may be positioned within a processing region of the processing chamber205. The pumping liner230may allow unreacted precursors or plasma effluents to be exhausted from the processing chamber205. The pumping liner230may additionally allow particles etched in an etching process to be removed from the processing chamber205to prevent the particles from remaining on the substrate during subsequent processing operations. A pedestal235may be included in the processing region of the processing chamber205and may be configured to support a substrate during etching or other process operations. The pedestal235may have one or more chucking mechanisms in various embodiments including electrostatic, vacuum, or gravitational, for example. The pedestal235may be rotatable or translatable in embodiments, and may be raised towards or lowered from the gas distribution assembly225. In embodiments the pedestal235may include one or more lift pins for aiding transfer of a substrate into and out of the processing chamber205. Pedestal235may additionally include heating or cooling mechanisms for maintaining substrate temperatures during processing operations. The pedestal235may include an inlaid heating element including a filament, or may include one or more tubes or channels configured to pass a temperature controlled fluid that may raise or lower the temperature accordingly. Pedestal235may include a platform for supporting a substrate that is or includes a ceramic heater. The ceramic heater may heat the substrate to particular operating temperatures including from about 20° C. to over 1000° C. in embodiments. The ceramic heater may additionally heat the substrate above about 50° C., above about 100° C., above about 150° C., above about 200° C., above about 250° C., above about 300° C., above about 350° C., above about 400° C., above about 500° C., or higher in embodiments. The ceramic heater may additionally maintain the substrate temperature below about 1000° C., below about 900° C., below about 800° C., below about 700° C., below about 600° C., or below about 500° C. in embodiments. The ceramic heater may additionally be configured to heat or maintain the substrate temperature between about 100° C. and about 500° C. in embodiments, or between about 300° C. and about 500° C. in embodiments. In embodiments the heater is configured to maintain the substrate temperature below about 300° C., in which case alternative metal heating elements may be used instead of a ceramic heater. For example, a coated aluminum heater may be used, or an embedded or coated heater on an aluminum or treated aluminum pedestal. The components of processing chamber205may be configured to withstand the operating environment during etching or other processing operations. The components of processing chamber205may be an anodized or oxidized material, including hard anodized aluminum, for example. Each component within processing chamber205that may be contacted by plasma effluents or other corrosive materials may be treated or coated to protect against corrosion. Alternative materials may also be utilized to protect against corrosion from plasma effluents including fluorine or chlorine in embodiments. For example, one or more components within processing chamber205may be ceramic or quartz in embodiments. As a particular example, one or more components of gas distribution assembly225, spacer222, pumping liner230, or any component that may be contacted by plasma or non-plasma precursors may be or include quartz or ceramic. Additionally, delivery tube216may be or include quartz, such as including a quartz liner within the delivery tube216. The delivery tube may be aluminum or hard anodized aluminum in embodiments, and may be characterized by a quartz interior surface. RPS unit210may also be lined with quartz in order to protect the internal components from corrosion caused by precursors dissociated within the RPS unit210including or chlorine, for example. The RPS unit210may include anodized metals, and the RPS unit210chamber cavities may be lined with quartz to further protect against corrosion. By utilizing a remote plasma from RPS unit210, the processing chamber205may be further protected against internal corrosion caused by plasma generation. In embodiments, processing chamber205may not be configured to produce a plasma, and plasma generation may be performed externally to the processing chamber205in RPS unit210. In embodiments additional plasma processing may be performed within processing chamber205, such as by a capactively-coupled plasma, although other plasma sources may be used. For example, gas box220and one or more components of the gas distribution assembly225may be utilized as electrodes by which a capacitively-coupled plasma may be produced. Additional or alternative plasma components within the chamber may be used to assist with recombination of plasma effluents by reducing the path length from plasma generation to interaction with a substrate. Precursors dissociated by plasma will recombine after a certain residence time. For example, after a chlorine-based precursor is dissociated within RPS unit210, the precursor or plasma effluents may be flowed through delivery tube216into processing chamber205, and then interact with a substrate on pedestal235. Depending on the length of the path of travel for the radical effluents, the effluents or radicals may recombine and at least partially lose the reactivity of the radical precursor. Additionally, the more complicated the path of travel, such as through various tubes or channels, the more protection may be included in the system as each component in contact with the plasma effluents may be treated or coated to protect from corrosion. Accordingly, processing chamber205may include a relatively straight line of travel from RPS unit210into processing chamber205, and then through exhaust plenum230. Additionally, once within processing chamber205, precursors or plasma effluents may travel through one or more inline aspects of the gas distribution assembly225to contact a substrate. Components of the gas distribution assembly225may be utilized to improve uniformity of flow towards a substrate, but otherwise maintain a reduced length of precursor flow path to reduce recombination of the plasma effluents as well as residence time within the processing chamber205. FIG.3shows a schematic partial cross-sectional view of an exemplary semiconductor processing chamber300according to some embodiments of the present technology.FIG.3may include one or more components discussed above with regard toFIG.2, and may illustrate further details relating to that chamber. Chamber300is understood to include any feature or aspect of system200discussed previously in some embodiments. The chamber300may be used to perform semiconductor processing operations including deposition of hardmask materials as previously described, as well as other deposition, removal, and cleaning operations. Chamber300may show a partial view of a processing region of a semiconductor processing system, and may not include all of the components, and which are understood to be incorporated in some embodiments of chamber300. As noted,FIG.3may illustrate a portion of a processing chamber300. The chamber300may include a number of lid stack components, which may facilitate delivery or distribution of materials through the processing chamber300into a processing region305, such as where a substrate306may be positioned on a pedestal310, for example. A chamber lid plate315may extend across one or more plates of the lid stack and may provide structural support for components, such as a remote plasma source (“RPS”) unit370, which may provide precursors or plasma effluents for chamber cleaning or other processing operations. The RPS unit370may be stabilized on the chamber lid plate315. Some embodiments may utilize additional support members (not shown) that may couple with the processing chamber300at one or more positions about the processing chamber300to properly distribute the weight of the RPS unit370to protect components from sheer or other stresses related to the weight of the RPS unit370. A delivery tube327that defines a central aperture may extend between the RPS unit370and the processing chamber300for delivering one or more precursors to the processing chamber300. An output manifold320may be positioned on the lid plate315and may define a central aperture322, which may extend about a central axis of the chamber300or output manifold320. Processing chamber300may also include an insulator325, which may electrically or thermally separate the output manifold320from other lid stack components. Insulator325may also define a central aperture328, which may be axially aligned with the central aperture322of the output manifold320. Processing chamber300may also include a gasbox330, on which the insulator may be positioned. Gasbox330may be characterized by a first surface331and a second surface332that may be opposite the first surface. Central aperture333may extend fully through the gasbox from the first surface331to the second surface332. The central aperture333may be axially aligned with the central aperture322of the output manifold320, and may be axially aligned with the central aperture328of the insulator325. The apertures may define a channel within which the delivery tube327may be disposed. Gasbox330may also define one or more channels that may be fluidly accessed through the gasbox330, and may allow multiple precursors to be delivered through the lid stack in a variety of flow profiles. For example, gasbox330may define an annular channel335extending within the gasbox330, and which may be recessed from first surface331. As will be explained further below, annular channel335may be fluidly accessed through an inlet aperture, which may be positioned at any location about the gasbox330, and may afford coupling for one or more precursors to be delivered from a gas panel or manifold. The inlet aperture may extend through first surface331as illustrated by the arrow, for providing precursors into the gasbox330. In some embodiments, annular channel335may be concentric with the central aperture333of the gasbox330. Gasbox330may also define one or more outlet apertures336. Outlet apertures336may be defined through the annular channel335, and may extend from annular channel335through second surface332of the gasbox330. Hence, one or more precursors delivered into annular channel335through the gasbox330may bypass the RPS unit370and be delivered to one or more outer regions of the gasbox330through the gasbox330. Gasbox330may include additional features. For example, gasbox330may define a cooling channel357, which may allow a cooling fluid to be flowed about the gasbox330, and which may allow additional temperature control. As illustrated, the cooling channel357may be defined in the first surface331of the gasbox330, and a lid may extend about the cooling channel to form a hermetic seal. Cooling channel357may extend about central aperture333, and may also be concentric with the central aperture333. As illustrated, annular channel335may be formed or defined within the gasbox330between the cooling channel and the second surface of the gasbox330. In some embodiments the annular channel335may be vertically aligned with the cooling channel357, and may be offset from the cooling channel357within a depth of the gasbox330. To form the annular channel335, in some embodiments the gasbox330may include one or more stacked plates. The plates may be bonded, welded, or otherwise coupled together to form a complete structure. For example, gasbox330may include at least one plate, and may include two, three, four, or more plates depending on the features formed. As illustrated, gasbox330may include two or three plates, which may allow multiple paths to be formed to further distribute precursors towards the annular channel335. For example, with a single point of delivery, uniformity may be achieved by modulating conductance within the channel relative to the outlet apertures. However, by utilizing one or more conductance paths defined within the gasbox330, precursors may be delivered to multiple locations within the annular channel335, which may increase uniformity of delivery through the gasbox330, and may allow larger diameter outlet apertures without sacrificing delivery uniformity. Semiconductor processing chamber300may also include additional components in some embodiments, such as a blocker plate350, and a faceplate355. Blocker plate350may define a number of apertures that may operate as a choke to increase radial diffusion to improve uniformity of delivery. Blocker plate350may be a first location through the lid stack where precursors delivered to the central aperture333of the gasbox330and precursors delivered to the annular channel335of the gasbox330may intermix. As illustrated, a volume352may be formed or defined between the gasbox330and the blocker plate350. Volume352may be fluidly accessible from both central aperture333and the plurality of outlet apertures336. Precursors delivered into the zone may then at least partially mix or overlap before continuing through the lid stack. By allowing an amount of mixing prior to contacting the substrate surface, an amount of overlap may be provided, which may produce a smoother transition at the substrate, and may limit an interface from forming on a film or substrate surface. Faceplate355may then deliver precursors to the processing region, which may be at least partially defined from above by the faceplate355. The delivery tube327may extend through each of the central aperture322, central aperture328, and central aperture333such that a top372of the delivery tube327may be coupled with the RPS unit370and a bottom374of the delivery tube327extends through the second surface332of the gasbox330.FIG.4illustrates a schematic partial cross-sectional view of delivery tube327. In many embodiments, the delivery tube327may be characterized by a generally cylindrical sidewall, although it will be appreciated that other shapes of sidewalls are possible. The top372of the delivery tube327defines a fluid lumen that may receive precursors or plasma effluents from the RPS unit370and deliver the precursors or plasma effluents to the chamber300for chamber cleaning and/or other processing operations. The top372of the delivery tube327may taper from a large opening to a smaller diameter that defines a main body of the delivery tube327. The RPS unit370may also be used create a positive pressure flow of purge gas down the delivery tube327to help eliminate RPS backstreaming during deposition operations. For example, purge gas, such as argon, helium, hydrogen, and the like, may be flowed downward from the RPS through the delivery tube327. The purge gas may be flowed from the RPS unit370at various rates, which may be based on a flow rate of deposition gases through the delivery tube327. For example, the purge gas may be flowed from the RPS unit370at rates of greater than or about 100 standard cubic centimeters per minute (sccm), greater than or about 200 sccm, greater than or about 300 sccm, greater than or about 400 sccm, greater than or about 500 sccm, greater than or about 600 sccm, greater than or about 700 sccm, greater than or about 800 sccm, greater than or about 900 sccm, greater than or about 1 liter per minute, greater than or about 2 liters per minute, or more, although higher or lower flow rates may be used based on the flow rates of deposition gas used in a particular processing application. The apertures375may be sized based on a flow rate and/or fluid velocity required by a particular deposition application. For example, the apertures375may have diameters of greater than or about 0.010 inch, greater than or about 0.020 inch, greater than or about 0.030 inch, greater than or about 0.040 inch, greater than or about 0.050 inch, or more to deliver deposition gases at a desired flow rate and/or velocity. An upper region of the sidewall of the delivery tube327may define a number of radially arranged apertures375. Each of these apertures375may be aligned with outlets of the output manifold320, which may supply a deposition gas to the interior of the delivery tube327. For example, deposition gas may be flowed through the apertures375at a flow rate of at least or about 1 liter per minute, at least or about 2 liters per minute, at least or about 3 liters per minute, or more, although higher or lower flow rates may be used to meet the needs of a particular processing application. The apertures375may be arranged at regular or irregular intervals about a periphery of the delivery tube327. For example, four apertures375may be arranged with one aperture375positioned every 90 degrees about the periphery of the delivery tube327. However, it will be appreciated that any number of apertures375may be provided in any arrangement. In some embodiments, the apertures375may be arranged in multiple rows along a length of the delivery tube327. As just one example, the apertures375may be arranged in two rows that are spaced apart from one another by a vertical distance. For example, two rows of four apertures375may be defined by the delivery tube327, with the rows spaced apart from one another by a vertical distance. Some or all of the apertures375may extend through the sidewall of the delivery tube327at an angle that is aligned with radial lines of the delivery tube327, while in some embodiments some or all of the apertures375may be angled away from a central axis of the delivery tube327. For example, a top row of apertures375may be radially aligned, while a bottom row of apertures375may be angled away from a central axis of the delivery tube327. In some embodiments, the apertures375may be angled away from the central axis by between about 1 degree and 10 degrees, between about 2 degrees and 9 degrees, between about 3 degrees and 8 degrees, between about 4 degrees and 7 degrees, between about 5 degrees and 6 degrees, etc. In some embodiments in which the apertures375are arranged in multiple rows, the apertures375in one or more of the rows may have angular positions relative to the central axis of the delivery tube327that are offset from angular positions of apertures375in at least one other row. For example, apertures375may be arranged in a top row of four apertures375and a bottom row of four apertures375. The four apertures375in each row may be disposed at 90 degree intervals, with the top row and the bottom row being offset 45 degrees from one another such that the periphery of the delivery tube327includes an aperture every 45 degrees. In some embodiments, the apertures375of multiple rows of apertures375may be in vertical alignment with one another at similar angular positions. As discussed above, clean, inert purge gas, such as argon, helium, or hydrogen, may be flowed from the RPS unit370down the delivery tube327at a position that is above the apertures375. This flow of purge gas from the RPS unit370creates a downward positive pressure fluid flow that prevents RPS backstreaming and eliminates the possibility that backstreaming may cause any particulate in RPS unit370to be blown into processing chamber300and onto the substrate being processed. FIG.5shows a schematic partial cross-sectional view of an exemplary semiconductor processing chamber500according to some embodiments of the present technology.FIG.5may include one or more components discussed above with regard toFIGS.2and3, and may illustrate further details relating to that chamber. Chamber500is understood to include any feature or aspect of system200and/or chamber300discussed previously. Chamber500may show a partial view of a processing region of a semiconductor processing system, and may not include all of the components, and which are understood to be incorporated in some embodiments of chamber500. Chamber500may include a processing region505, such as where a substrate506may be positioned on a pedestal510, a RPS unit570, an output manifold520that defines a central aperture522, an insulator525that defines a central aperture528, and a gasbox530defining a central aperture533. Semiconductor processing chamber500may also include additional components in some embodiments, such as a blocker plate550, and a faceplate555. A delivery tube527may extend through each of the central aperture522, central aperture528, and central aperture533such that a top572of the delivery tube527may be coupled with the RPS unit570and a bottom574of the delivery tube527extends through the gasbox530. The delivery tube527provides a fluid path from the RPS unit570to the processing chamber500, enabling the RPS unit570to deliver precursors and/or plasma effluents to the chamber300for chamber cleaning and/or other processing operations.FIG.6is a schematic partial cross-sectional view of the delivery tube527. In many embodiments, the delivery tube527may be characterized by a generally cylindrical sidewall, although it will be appreciated that other shapes of sidewalls are possible. The top572of the delivery tube527may define a fluid lumen that may receive precursors or plasma effluents from the RPS unit570and deliver the precursors or plasma effluents to the chamber500for chamber cleaning or other processing operations. The top572of the delivery tube527may taper from a large opening to a smaller diameter that defines a main body of the delivery tube527. An upper region of the sidewall of the delivery tube527may define a number of sets of radially arranged apertures. For example, a set of upper apertures575and a set of lower apertures577may be defined by the sidewall of the delivery tube527. Lower apertures577aligned with outlets of the output manifold520, and may supply a deposition gas from the output manifold520to the interior of the delivery tube527. For example, deposition gas may be flowed through the lower apertures577at a flow rate of at least 1 liter per minute, at least 2 liters per minute, at least 3 liters per minute, or more, although higher or lower flow rates may be used to meet the needs of a particular processing application. Lower apertures577may be arranged at regular or irregular intervals about a periphery of the delivery tube527. For example, greater than or about two, greater than or about three, greater than or about four, or more lower apertures577may be arranged with one lower aperture577positioned every 90 degrees about the periphery of the delivery tube527. However, it will be appreciated that any number of lower apertures577may be provided in any arrangement. In some embodiments, lower apertures577may be arranged in multiple rows along a length of the delivery tube527. As just one example, lower apertures575may be arranged in two rows that are spaced apart from one another by a vertical distance. Upper apertures575may be positioned above the lower apertures577and may be aligned with outlets of the output manifold520. Upper apertures575may provide fluid paths for supplying a purge gas, such as argon, helium, hydrogen, and the like, to the interior of the delivery tube527. For example, the purge gas may be flowed through the upper aperture577at rates of greater than or about 100 sccm, greater than or about 200 sccm, greater than or about 300 sccm, greater than or about 400 sccm, greater than or about 500 sccm, greater than or about 600 sccm, greater than or about 700 sccm, greater than or about 800 sccm, greater than or about 900 sccm, greater than or about 1 liter per minute, greater than or about 2 liters per minute, or more, although higher or lower flow rates may be used based on the flow rates of deposition gas used in a particular processing application. By flowing clean, inert purge gas through the upper apertures575at a position that is above the lower apertures577, the flow of purge gas creates a positive pressure fluid barrier that prevents RPS backstreaming. The upper apertures575may be arranged at regular or irregular intervals about a periphery of the delivery tube527. For example, four upper apertures575may be arranged with one upper aperture575positioned every 90 degrees about the periphery of the delivery tube527. However, it will be appreciated that any number of upper apertures575may be provided in any arrangement. In some embodiments, upper apertures575may be arranged in multiple rows along a length of the delivery tube527. As just one example, upper apertures575may be arranged in two rows that are spaced apart from one another by a vertical distance. The upper apertures575and lower apertures577may be sized based on a flow rate and/or fluid velocity required by a particular deposition application. For example, the upper apertures575and lower apertures577may have diameters of greater than or about 0.010 inch, greater than or about 0.020 inch, greater than or about 0.030 inch, greater than or about 0.040 inch, greater than or about 0.050 inch, or more to deliver deposition gases at a desired flow rate and/or velocity. In some embodiments, all of the upper apertures575and lower apertures577may be the same size, while in other embodiments some or all of the upper apertures575and/or lower apertures577may have different sizes. For example, the upper apertures575may have a first diameter while the lower apertures577may have a second diameter that is smaller or larger than the first diameter. In some embodiments in which the upper apertures575and/or lower apertures577are arranged in multiple rows, the apertures in each row may have different sizes. As just one example, a top row of upper apertures575may have a different diameters than upper apertures575in a bottom row. In some embodiments, some or all of the upper apertures575and/or lower apertures577may extend through the sidewall of the delivery tube527at an angle that is aligned with radial lines of the delivery tube527, while in some embodiments some or all of the upper apertures575and/or lower apertures577may be angled away from a central axis of the delivery tube527. For example, a top row of the upper apertures575and/or lower apertures577may be radially aligned, while a bottom row of upper apertures575and/or lower apertures577may be angled away from a central axis of the delivery tube527. By angling some or all of the upper apertures575and/or lower apertures577away from the central axis, a rotational fluid flow may be created within the delivery tube527that may help mix the purge gases and deposition gases. In some embodiments, the upper apertures575and/or lower apertures577may be angled away from the central axis by between about 1 degree and 10 degrees, between about 2 degrees and 9 degrees, between about 3 degrees and 8 degrees, between about 4 degrees and 7 degrees, between about 5 degrees and 6 degrees, etc. Some or all of the upper apertures575may be in vertical alignment with some or all of the lower apertures577, while in some embodiments some or all of the upper apertures575may be angularly offset from some or all of the lower apertures577. In some embodiments in which the upper apertures575and/or lower apertures577are arranged in multiple rows, the upper apertures575and/or lower apertures577in one or more rows may have angular positions relative to the central axis of the delivery tube527that are offset from angular positions of apertures in at least one other row. For example, as illustrated the apertures of each row of both the upper apertures575and lower apertures577may be angularly offset from one another such that no apertures share an angular position. However, the upper apertures575and/or lower apertures577of some rows of upper apertures575and/or lower apertures577may have similar angular positions (i.e., may be in vertical alignment) as upper apertures575and/or lower apertures577in other rows. FIGS.7A-7Bshow schematic cross sections of exemplary delivery tubes according to some embodiments of the present technology.FIG.7Aillustrates a delivery tube700that may include similar features as delivery tubes327and527described herein. The delivery tube700may be characterized by at least one sidewall702that defines a fluid lumen704that extends from a RPS unit to a processing chamber of a semiconductor processing system. Oftentimes, the sidewall702may have a generally circular cross-section such that the delivery tube700is generally cylindrical, however other cross-sectional shapes are possible. The sidewall702may define a number of apertures706that extend through a thickness of the sidewall702to form fluid paths to the fluid lumen704. The apertures706may extend through the sidewall702along radial lines of the delivery tube700. For example, four apertures706may be provided at 90 degree intervals from one another, however other numbers and angular intervals, including irregular intervals, may be utilized in some embodiments.FIG.7Bshows another delivery tube710. Delivery tube710may be similar to delivery tube700and may include similar features as delivery tubes327and527described herein. Delivery tube710may be characterized by at least one sidewall712that defines a fluid lumen714that extends from a RPS unit to a processing chamber of a semiconductor processing system. The sidewall712may define a number of apertures716that may extend through the sidewall712an angle away from a central axis of the delivery tube710. In some embodiments, the apertures716may be angled away from the central axis by between about 1 degree and 10 degrees, between about 2 degrees and 9 degrees, between about 3 degrees and 8 degrees, between about 4 degrees and 7 degrees, between about 5 degrees and 6 degrees, etc. Oftentimes, an arrangement of apertures716such as shown here may be used in lower rows of apertures, such as the lower rows of apertures described in conjunction withFIGS.3-6. WhileFIGS.7A and7Bshow delivery tubes with four apertures, it will be appreciated that any number of apertures may be used in some embodiments. The apertures may be arranged at regular intervals, such as every 90 degrees, or may be arranged at irregular intervals. Additionally, it will be appreciated that the apertures inFIGS.7A and7Bmay represent those apertures in a single row and that multiple rows of apertures may be provided in a single delivery tube as described herein. In some embodiments, an arrangement of apertures such as apertures706may be used in one row, such as a top row, of a delivery tube, while an arrangement of apertures similar to apertures716may be used in another row, such as a bottom row of apertures. FIG.8shows a schematic partial cross-sectional view of an exemplary semiconductor processing chamber800according to some embodiments of the present technology.FIG.8may include one or more components discussed above with regard toFIGS.2and3, and may illustrate further details relating to that chamber. Chamber800is understood to include any feature or aspect of system200and/or chamber300discussed previously in some embodiments. Chamber800may show a partial view of a processing region of a semiconductor processing system, and may not include all of the components, and which are understood to be incorporated in some embodiments of chamber800. Chamber800may include a processing region805, such as where a substrate806may be positioned on a pedestal810. The chamber800may include a RPS unit870and a gasbox830that may define a central aperture833. Semiconductor processing chamber800may also include additional components in some embodiments, such as a blocker plate850, and a faceplate855. The delivery tube827may extend through central aperture833such that a top872of the delivery tube827may be coupled with the RPS unit870and a bottom874of the delivery tube827may extend through the gasbox830. An inert gas plenum880may be disposed about at least a portion of the delivery tube827and may be fluidly coupled with an interior of the delivery tube827via a number of apertures875defined in a sidewall of the delivery tube827. For example, a number of lumens882may extend between the purge gas plenum880and the delivery tube827to provide fluid paths from the purge gas plenum880to the apertures875. This enables the inert gas plenum880to deliver an inert gas, such as argon, helium, hydrogen, and the like, to the interior of the delivery tube827at a number of radial locations to generate a gas vortex within the interior of the delivery tube827. This vortex may draw fluid within the delivery tube827downward toward the gasbox830and may prevent backstreaming of any plasma, precursors, or deposition gas into the RPS unit870. The purge gas may be flowed through the apertures875at a rate of greater than or about 100 sccm, greater than or about 200 sccm, greater than or about 300 sccm, greater than or about 400 sccm, greater than or about 500 sccm, greater than or about 600 sccm, greater than or about 700 sccm, greater than or about 800 sccm, greater than or about 900 sccm, greater than or about 1 liter per minute, or more, with higher flow rates being used to combat higher levels of backstreaming gases. In many embodiments, the apertures875may be positioned in an upper region of the delivery tube827proximate the RPS unit870to generate a vortex that acts as a fluid barrier proximate the RPS unit870. The delivery tube827may be sized and shaped to maintain a post-ignition pressure of at least 5 Torr, commonly at least 10 Torr, and oftentimes at least 20 Torr, or higher. For example, in a particular embodiment, the delivery tube827may have a generally cylindrical sidewall that has a diameter at least or about 1.0 inch, at least or about 1.1 inches, at least or about 1.2 inches, at least or about 1.3 inches, at least or about 1.4 inches, at least or about 1.5 inches, or more, although it will be appreciated that other sizes and/or shapes of delivery tubes827are possible in various embodiments. The apertures875may have diameters of greater than or about 0.050 inch, greater than or about 0.100 inch, greater than or about 0.150 inch, greater than or about 0.200 inch, greater than or about 0.250 inch, greater than or about 0.300 inch, greater than or about 0.350 inch, greater than or about 0.400 inch, greater than or about 0.450 inch, greater than or about 0.500 inch, or more, which smaller apertures875generating a higher pressure drop within the delivery tube827. In some embodiments, some or all of the apertures875may be angled downward toward the gasbox830. Apertures875with downward angles may increase the positive pressure within the interior of the delivery tube827in a direction away from the RPS unit870when gas is introduced via the apertures875. The apertures875may be angled downward by between about 1 degree and 10 degrees, between about 2 degrees and 9 degrees, between about 3 degrees and 8 degrees, between about 4 degrees and 7 degrees, between about 5 degrees and 6 degrees, etc. relative to horizontal, with greater degrees of downward slope may creating stronger vortexes. The apertures875may be arranged at regular or irregular intervals about a periphery of the delivery tube827. In some embodiments, some or all of the apertures875may extend through the sidewall of the delivery tube827at an angle that is aligned with a radial line of the delivery tube827, while in some embodiments some or all of the apertures875may be angled away from a central axis of the delivery tube827along a horizontal axis of the delivery tube827.FIG.9shows a schematic cross-section of delivery tube827and inert gas plenum880. The apertures875may be coupled with the purge gas plenum880via lumens882. As noted above, lumens882may extend between the purge gas plenum880and the delivery tube827to provide fluid paths from the purge gas plenum880to the apertures875. The apertures875may be angled away from the central axis by between about 1 degree and 10 degrees, between about 2 degrees and 9 degrees, between about 3 degrees and 8 degrees, between about 4 degrees and 7 degrees, between about 5 degrees and 6 degrees, etc. While shown with14apertures875, it will be appreciated that any number of apertures875may be provided. In some embodiments, a single RPS unit may be used to deliver precursors or plasma effluents to multiple semiconductor processing chambers.FIG.10shows a simplified schematic illustrating such an arrangement, with an RPS unit1070being coupled with two delivery tubes1027a,1027b. Each delivery tube1027a1027bmay be similar to delivery tube827and may deliver precursors or plasma effluents to a respective processing chamber1000a,1000b. Each processing chamber1000a,1000bmay be similar to processing chamber300and/or800described herein and may each include a faceplate1010a,1010b. Inert gas plenums1080a,1080bmay be similar to inert gas plenum880and may be positioned about each respective delivery tube1027a,1027b. Each inert gas plenum1080a,1080bmay supply a respective delivery tube1027a,1028bwith a flow of inert gas, as described above in relation toFIGS.8and9. By providing each delivery tube/processing chamber pair with a dedicated inert gas plenum, the RPS unit1070is not only isolated from backstreaming but also may be isolated from the gases of each processing chamber1000, which enables the RPS unit1070to avoid cross talk between the different processing chambers1000. FIG.11illustrates a method1100of etching a substrate according to embodiments of the present technology. Method1100may include flowing a deposition gas from a deposition gas source into an interior of a delivery tube at operation1110. At operation1120, a purge gas may be flowed into the interior of the delivery tube at a plurality of fluid ports that are radially arranged about the delivery tube to prevent backflow of the deposition gas into a remote plasma system (RPS) positioned at a top end of the delivery tube. The deposition gas may be flowed into a faceplate coupled with a bottom end of the delivery tube at operation1030. The flowing of deposition gas from the deposition gas source into the interior of the delivery tube may include flowing the deposition gas from a manifold into the interior of the delivery tube via a plurality of apertures that are radially arranged about the delivery tube and that are disposed below the plurality of fluid ports. In some embodiments, flowing the deposition gas from the deposition gas source into the interior of the delivery tube may include flowing the deposition gas into the interior of the delivery tube from the RPS. At least some of the plurality of fluid ports may be angled away from a central axis of the delivery tube. At least some of the plurality of fluid ports may be angled downward toward the faceplate. The introduction of the purge gas into the interior of the delivery tube may include flowing the purge gas from a purse gas plenum into the interior of the delivery tube via the fluid ports. By flowing purge gas into the delivery tubes at positions above at least a portion of the deposition gas flow, the methods may prevent any gases from the chamber from backstreaming into the RPS. This helps prevent changes to the inner surfaces of the RPS unit in order to eliminate RPS strike faults and to delivery better uniformity of deposition gases on the wafer. In the preceding description, for the purposes of explanation, numerous details have been set forth in order to provide an understanding of various embodiments of the present technology. It will be apparent to one skilled in the art, however, that certain embodiments may be practiced without some of these details, or with additional details. Having disclosed several embodiments, it will be recognized by those of skill in the art that various modifications, alternative constructions, and equivalents may be used without departing from the spirit of the embodiments. Additionally, a number of well-known processes and elements have not been described in order to avoid unnecessarily obscuring the present technology. Accordingly, the above description should not be taken as limiting the scope of the technology. Where a range of values is provided, it is understood that each intervening value, to the smallest fraction of the unit of the lower limit, unless the context clearly dictates otherwise, between the upper and lower limits of that range is also specifically disclosed. Any narrower range between any stated values or unstated intervening values in a stated range and any other stated or intervening value in that stated range is encompassed. The upper and lower limits of those smaller ranges may independently be included or excluded in the range, and each range where either, neither, or both limits are included in the smaller ranges is also encompassed within the technology, subject to any specifically excluded limit in the stated range. Where the stated range includes one or both of the limits, ranges excluding either or both of those included limits are also included. As used herein and in the appended claims, the singular forms “a”, “an”, and “the” include plural references unless the context clearly dictates otherwise. Thus, for example, reference to “an aperture” includes a plurality of such apertures, and reference to “the plate” includes reference to one or more plates and equivalents thereof known to those skilled in the art, and so forth. Also, the words “comprise(s)”, “comprising”, “contain(s)”, “containing”, “include(s)”, and “including”, when used in this specification and in the following claims, are intended to specify the presence of stated features, integers, components, or operations, but they do not preclude the presence or addition of one or more other features, integers, components, operations, acts, or groups. | 49,445 |
11862476 | DETAILED DESCRIPTION OF EMBODIMENTS FIG.1illustrates a plan view showing a semiconductor device according to exemplary embodiments of inventive concepts.FIGS.2A,2B, and2Cillustrate cross-sectional views respectively taken along lines A-A′, B-B′, and C-C′ ofFIG.1.FIG.3illustrates a graph showing an oxygen concentration versus a depth of an active pattern, according to exemplary embodiments of inventive concepts. The semiconductor device shown inFIGS.1to3may be formed of at least a planar transistor such as a fin field-effect transistor (finFET). Referring toFIGS.1,2A to2C, and3, a first semiconductor layer110may be provided on a substrate100. The first semiconductor layer110may include an amorphous oxide semiconductor (AOS). The first semiconductor layer110may include a compound of oxygen (O) and at least two metals selected from a group consisting of zinc (Zn), indium (In), gallium (Ga), and tin (Sn). For example, the first semiconductor layer110may include indium-gallium-zinc oxide (IGZO) or indium-tin-zinc oxide (ITZO). The substrate100may be a semiconductor substrate including silicon, germanium, or silicon-germanium. The first semiconductor layer110may be provided thereon with a device isolation layer ST defining active patterns ACT. For example, the device isolation layer ST may include a silicon oxide layer. The active patterns ACT may be formed when an upper portion of the first semiconductor layer110is patterned. Each of the active patterns ACT may thus include an amorphous oxide semiconductor identical to that of the first semiconductor layer110. Each of the active patterns ACT may extend in a third direction D3parallel to a top surface of the substrate100. The active patterns ACT may be spaced apart from each other in the third direction D3. The active patterns ACT may be two-dimensionally arranged. Each of the active patterns ACT may have a width that decreases toward a vertical direction (i.e., a fourth direction D4) to the top surface of the substrate100. The width of each of the active patterns ACT may decrease with increasing distance from a bottom surface of the substrate100. First and second trenches TR1and TR2may be defined between the active patterns ACT. The device isolation layer ST may fill the first and second trenches TR1and TR2between the active patterns ACT. The first trench TR1may be defined between a pair of active patterns ACT adjacent to each other in a second direction D2. The second trench TR2may be defined between a pair of active patterns ACT adjacent to each other in the third direction D3. A first length L1may be provided between the pair of active patterns ACT adjacent to each other in the second direction D2. A second length L2may be provided between the pair of active patterns ACT adjacent to each other in the third direction D3. The second length L2may be greater than the first length L1. Therefore, the second trench TR2may have a depth from top surfaces of the active patterns ACT greater than that of the first trench TR1. For example, the second trench TR2may have a floor lower than that of the first trench TR1. Each of the active patterns ACT may include a first segment LP and a second segment UP on the first segment LP. For example, the first segment LP may be a lower portion of the active pattern ACT, and the second segment UP may be an upper portion of the active pattern ACT. The first segment LP may have an oxygen concentration less than that of the second segment UP. As shown inFIG.3, the second segment UP may have a top surface at a first level LV1, the first segment LP may have a bottom surface at a third level LV3, and the first and second segments LP and UP may have therebetween a boundary at a second level LV2. The active pattern ACT may have an oxygen concentration that decreases from the first level LV1toward the third level LV3. The oxygen concentration may rapidly decrease at the second level LV2. Referring back toFIGS.1and2A to2C, each of the active patterns ACT may include a first source/drain region SD1and a pair of second source/drain regions SD2. For example, the second segment UP of the active pattern ACT may include the first source/drain region SD1and the pair of second source/drain regions SD2. The first source/drain region SD1may be placed between the pair of second source/drain regions SD2. A pair of third trenches TR3may be defined on each of the active patterns ACT. Each of the third trenches TR3may be defined between the first source/drain region SD1and the second source/drain region SD2. The third trench TR3may downwardly extend from the top surface of the active pattern ACT toward the substrate100, while penetrating the second segment UP of the active pattern ACT. The third trench TR3may have a floor higher than those of the first and second trenches TR1and TR2. Each of the active patterns ACT may further include a pair of channel regions CH. For example, the first segment LP of the active pattern ACT may include the pair of channel regions CH. When viewed in plan, the channel region CH may be interposed between the first source/drain region SD1and the second source/drain region SD2. The channel region CH may be placed below the third trench TR3. The channel region CH may thus be positioned lower than the first and second source/drain regions SD1and SD2. Gate electrodes GE may be provided to run across the active patterns ACT and the device isolation layer ST. The gate electrodes GE may be provided in the third trenches TR3. The gate electrodes GE may extend in parallel to each other in the second direction D2. A pair of gate electrodes GE may be provided on the pair of channel regions CH of each of the active patterns ACT. The gate electrode GE may have a top surface lower than that of the active pattern ACT (e.g., a top surface of the first source/drain region SD1or a top surface of the second source/drain region SD2). Referring back toFIG.2C, the gate electrode GE may have an upper portion adjacent to the second segment UP of the active pattern ACT. The gate electrode GE may have a lower portion adjacent to the first segment LP of the active pattern ACT. For example, the lower portion of the gate electrode GE may be adjacent to the channel region CH. As the amorphous oxide semiconductor constituting the active pattern ACT increases in oxygen concentration, a transistor may increase in threshold voltage. For example, when a transistor is provided on an active pattern consisting of a first amorphous oxide semiconductor having a first oxygen concentration, and when the transistor has a first threshold voltage, the first amorphous oxide semiconductor may be defined to have the first threshold voltage. When a transistor is provided on an active pattern consisting of a second amorphous oxide semiconductor having a second oxygen concentration, and when the transistor has a second threshold voltage, the second amorphous oxide semiconductor may be defined to have the second threshold voltage. When the second oxygen concentration is greater than the first oxygen concentration, the second threshold voltage may be greater than the first threshold voltage. As the amorphous oxide semiconductor increases in oxygen concentration, the amorphous oxide semiconductor may also increase in resistance. In contrast, as the amorphous oxide semiconductor decreases in oxygen concentration, the transistor may decrease in threshold voltage and resistance. According to some exemplary embodiments of inventive concepts, the second segment UP of the active pattern ACT may have a relatively high oxygen concentration. When a threshold voltage is raised due to an increase in oxygen concentration, a current leakage may be reduced. The second segment UP may have a relatively high threshold voltage, and consequently, a current leakage may be prevented at the second segment UP adjacent to the upper portion of the gate electrode GE, which can be referred to as a gate-induced-drain leakage region. According to some exemplary embodiments of inventive concepts, the first segment LP of the active pattern ACT may have a relatively low oxygen concentration. When a threshold voltage is reduced due to a decrease in oxygen concentration, a resistance may be decreased and a current may smoothly flow. The first segment LP may have a relatively low threshold voltage, and consequently, a current boosting effect may occur at the channel region CH of the first segment LP. For example, a relatively large amount of current may flow through the channel region CH under a predetermined gate voltage. Referring back toFIG.2B, the channel region CH below the gate electrode GE may vertically protrude beyond the device isolation layer ST below the gate electrode GE. For example, the channel region CH below the gate electrode GE may be located at a level higher than that of a top surface of the device isolation layer ST below the gate electrode GE. The channel region CH below the gate electrode GE may have a fin shape. The gate electrode GE may have a first bottom surface BS1on the device isolation layer ST and a second bottom surface BS2on the channel region CH, and the first bottom surface BS1may be lower than the second bottom surface BS2. At least a portion PO of the gate electrode GE may be interposed between a pair of channel regions CH adjacent to each other in the second direction D2. The portion PO of the gate electrode GE may be placed on the device isolation layer ST filling the first trench TR1. The gate electrode GE may surround a top surface and opposite sidewalls of the channel region CH, which may result in improving electrical characteristics of a transistor. Referring back toFIGS.1and2A to2C, a gate dielectric layer GI may be interposed between the gate electrode GE and the active pattern ACT. A gate capping layer GP may be provided on the gate electrode GE. The gate capping layer GP may cover the top surface of the gate electrode GE. The gate capping layer GP may have a top surface coplanar with that of the active pattern ACT. The gate electrode GE may include one or more of conductive metal nitride (e.g., titanium nitride or tantalum nitride) and metal (e.g., titanium, tantalum, tungsten, copper, or aluminum). For example, the gate electrode GE may be formed of a metal layer and a polysilicon high-work function layer formed thereon. The gate dielectric layer GI may include one or more of a silicon oxide layer, a silicon nitride layer, a silicon oxynitride layer, and a high-k dielectric material. For example, the high-k dielectric material may include hafnium oxide, hafnium silicon oxide, lanthanum oxide, zirconium oxide, zirconium silicon oxide, tantalum oxide, titanium oxide, barium strontium titanium oxide, barium titanium oxide, strontium titanium oxide, lithium oxide, aluminum oxide, lead scandium tantalum oxide, lead zinc niobate, or a combination thereof. The gate capping layer GP may include one or more of a silicon oxide layer, a silicon nitride layer, and a silicon oxynitride layer. A first interlayer dielectric layer IL1may be provided on the substrate100. The first interlayer dielectric layer IL1may include first contact holes CNH1exposing the first source/drain regions SD1of the active patterns ACT. The first interlayer dielectric layer IL1may be provided thereon with line structures LST extending in a first direction D1. The line structures LST may be spaced apart from each other in the second direction D2. When viewed in plan, the line structures LST may intersect the gate electrodes GE. A pair of spacers SP may be provided on opposite sidewalls of each of the line structures LST. The spacers SP may include one or more of a silicon oxide layer, a silicon nitride layer, and a silicon oxynitride layer. Each of the line structures LST may include a conductive pattern CP, a barrier pattern BP, a bit line BL, and a mask pattern MP that are sequentially stacked. The conductive pattern CP may include a contact part CNP that fills the first contact hole CNH1and contacts the first source/drain region SD1. The barrier pattern BP may prevent a metallic material in the bit line BL from diffusing toward the conductive pattern CP. The bit line BL may be electrically connected to the first source/drain region SD1through the barrier pattern BP and the conductive pattern CP. The conductive pattern CP may include one of a doped semiconductor material (e.g., doped silicon or doped germanium), a metallic material (e.g., titanium, tantalum, tungsten, copper, or aluminum), and a metal-semiconductor compound (e.g., tungsten silicide, cobalt silicide, or titanium silicide). The barrier pattern BP may include conductive metal nitride (e.g., titanium nitride or tantalum nitride). The bit line BL may include a metallic material (e.g., titanium, tantalum, tungsten, copper, or aluminum). A second interlayer dielectric layer IL2may be provided on the first interlayer dielectric layer IL1. The second interlayer dielectric layer IL2may cover the spacers SP. Second contact holes CNH2may be provided to penetrate the second and first interlayer dielectric layer IL2and IL1and to expose the second source/drain regions SD2. Contacts CNT may be provided in the second contact holes CNH2. The contacts CNT may contact the second source/drain regions SD2. The spacers SP may separate the contacts CNT from the bit lines BL. The contacts CNT may include one or more of conductive metal nitride (e.g., titanium nitride or tantalum nitride) and metal (e.g., titanium, tantalum, tungsten, copper, or aluminum). A data storage element DS may be provided on each of the contacts CNT. The data storage element DS may be a memory element using one of a capacitor, a magnetic tunnel junction pattern, and a variable resistance body that includes a phase change material. For example, the data storage element DS may be a capacitor to form at least one of various types of memory such as dynamic random access memory (DRAM), not being limited thereto. FIGS.4,6,8,10,12, and14illustrate plan views showing a method of fabricating a semiconductor device according to exemplary embodiments of inventive concepts.FIGS.5,7A,9A,11A,13A, and15Aillustrate cross-sectional views taken along line A-A′ ofFIGS.4,6,8,10,12, and14, respectively.FIGS.7B,9B,11B,13B, and15Billustrate cross-sectional views taken along line B-B′ ofFIGS.6,8,10,12, and14, respectively.FIGS.7C,9C,11C,13C, and15Cillustrate cross-sectional views taken along line C-C′ ofFIGS.6,8,10,12, and14, respectively. Referring toFIGS.4and5, a first semiconductor layer110may be formed on a substrate100. For example, a sputtering process may be used to form the first semiconductor layer110. A target of the sputtering process may include a precursor of an amorphous oxide semiconductor. The target may include at least two metals selected from a group consisting of zinc (Zn), indium (In), gallium (Ga), and tin (Sn). In consequence, the first semiconductor layer110may be formed of the amorphous oxide semiconductor (e.g., indium-gallium-zinc oxide (IGZO) or indium-tin-zinc oxide (ITZO)). The formation of the first semiconductor layer110may include forming a first layer LL on the substrate100and forming a second layer UL on the first layer LL. The formation of the first layer LL may include performing a sputtering process under a first partial pressure of oxygen (O2). The formation of the second layer UL may include performing a sputtering process under a second partial pressure of oxygen (O2). The second partial pressure of oxygen may be greater than the first partial pressure of oxygen. Therefore, the second layer UL may have an oxygen concentration greater than that of the first layer LL (seeFIG.3). For example, the formation of the first layer LL and the formation of the second layer UL may be successively and sequentially performed in the same chamber. Referring toFIGS.6and7A to7C, an upper portion of the first semiconductor layer110may be patterned to form active patterns ACT. Each of the active patterns ACT may extend in a third direction D3parallel to a top surface of the substrate100. The active patterns ACT may be spaced apart from each other in the third direction D3. Each of the active patterns ACT may include a first segment LP formed when the first layer LL is patterned and a second segment UP formed when the second layer UL is patterned. The second segment UP may be formed on the first segment LP. The second segment UP may have an oxygen concentration greater than that of the first segment LP. First and second trenches TR1and TR2may be defined between the active patterns ACT. The first trench TR1may be defined between a pair of active patterns ACT adjacent to each other in a second direction D2. The second trench TR2may be defined between a pair of active patterns ACT adjacent to each other in the third direction D3. Referring toFIGS.8and9A to9C, a device isolation layer ST may be formed to fill the first and second trenches TR1and TR2. The device isolation layer ST may be formed to completely fill the first and second trenches TR1and TR2and to cover the active patterns ACT. A planarization process may be performed on the device isolation layer ST until top surfaces of the active patterns ACT are exposed. The active patterns ACT and the device isolation layer ST may be patterned to form third trenches TR3. When viewed in plan, each of the third trenches TR3may have a linear shape extending in the second direction D2. The formation of the third trenches TR3may include forming a hardmask pattern having openings and then performing an etching process in which the hardmask pattern is used as an etching mask to etch the exposed active patterns ACT and the device isolation layer ST. The third trench TR3may be formed shallower than the first trench TR1. During the etching process, the device isolation layer ST may be etched more than the active patterns ACT (seeFIG.9B). The active patterns ACT in the third trench TR3may vertically protrude beyond the device isolation layer ST. For example, the active patterns ACT in the third trench TR3may have fin shapes. Referring toFIGS.10and11A to11C, a gate dielectric layer GI, a gate electrode GE, and a gate capping layer GP may be formed in each of the third trenches TR3. For example, the gate dielectric layer GI may be conformally formed in each of the third trenches TR3. The gate dielectric layer GI may include one or more of a silicon oxide layer, a silicon nitride layer, a silicon oxynitride layer, and a high-k dielectric material. A conductive layer filling the third trenches TR3may be formed on the gate dielectric layer GI, which may result in forming gate electrodes GE. The conductive layer may include one or more of metal and conductive metal nitride. The gate dielectric layer GI and the gate electrode GE may be recessed, and then the gate capping layer GP may be formed on the recessed gate electrode GE. The gate capping layer GP may have a top surface coplanar with that of the active pattern ACT. A dopant implantation process may be performed to implant dopants into the active patterns ACT. The dopants may include hydrogen, indium, or a combination thereof. A first source/drain region SD1and a pair of second source/drain regions SD2may be defined on an upper portion of each of the active patterns ACT. The pair of second source/drain regions SD2may be spaced apart in the third direction D3from each other across the first source/drain region SD1. A channel region CH may be defined to indicate the first segment LP of the active pattern ACT, which first segment LP is positioned below the gate electrode GE. When viewed in plan, the channel region CH may be interposed between the first source/drain region SD1and the second source/drain region SD2. The gate electrode GE may be provided on a top surface and opposite sidewalls of the channel region CH. Referring toFIGS.12and13A to13C, a first interlayer dielectric layer IL1may be formed on an entire surface of the substrate100. For example, the first interlayer dielectric layer IL1may include a silicon oxide layer. The first interlayer dielectric layer IL1may be patterned to form first contact holes CNH1exposing the first source/drain regions SD1of the active patterns ACT. A first conductive layer CL1, a barrier layer BAL, and a second conductive layer CL2may be sequentially formed on the first interlayer dielectric layer IL1. The first conductive layer CL1may fill the first contact holes CNH1. For example, the first conductive layer CL1may contact the first source/drain regions SD1of the active patterns ACT. The first interlayer dielectric layer IL1may vertically separate the first conductive layer CL1from the second source/drain regions SD2of the active patterns ACT. The first conductive layer CL1may include one of a doped semiconductor material, a metallic material, and a metal-semiconductor compound. The barrier layer BAL may be formed to lie between the first conductive layer CL1and the second conductive layer CL2. The barrier layer BAL may include conductive metal nitride. The second conductive layer CL2may include a metallic material. The barrier layer BAL may prevent a metallic material in the second conductive layer CL2from diffusing toward the first conductive layer CL1. Referring back toFIGS.14and15A to15C, line structures LST may be formed to extend in a first direction D1on the first interlayer dielectric layer IL1. The line structures LST may be spaced apart from each other in the second direction D2. For example, mask patterns MP may be formed on the second conductive layer CL2. The mask patterns MP may be formed to have linear shapes extending in the first direction D1. For example, the mask patterns MP may include silicon nitride layers or silicon oxynitride layers. The mask patterns MP may be used as an etching mask to sequentially etch the second conductive layer CL2, the barrier layer BAL, and the first conductive layer CL1to respectively form a bit line BL, a barrier pattern BP, and a conductive pattern CP. The mask pattern MP, the bit line BL, the barrier pattern BP, and the conductive pattern CP may vertically overlap each other. The mask pattern MP, the bit line BL, the barrier pattern BP, and the conductive pattern CP may constitute the line structure LST. When viewed in plan, the bit lines BL may extend while intersecting the gate electrodes GE. The conductive pattern CP may include contact parts CNP filling the first contact holes CNH1. The conductive pattern CP may be connected through the contact part CNP to the first source/drain region SD1. For example, the bit line BL may be electrically connected through the conductive pattern CP to the first source/drain region SD1. A pair of spacers SP may be formed on opposite sidewalls of each of the line structures LST. The formation of the spacers SP may include conformally forming a spacer layer on the entire surface of the substrate100and anisotropically etching the spacer layer. Referring back toFIGS.1and2A to2C, a second interlayer dielectric layer IL2may be formed on the substrate100. For example, the second interlayer dielectric layer IL2may include a silicon oxide layer. A planarization process may be performed on the second interlayer dielectric layer IL2until top surfaces of the mask patterns MP are exposed. The second and first interlayer dielectric layers IL2and IL1may experience a patterning process to form second contact holes CNH2exposing the second source/drain regions SD2of the active patterns ACT. Since the mask patterns MP and the spacers SP are used as an etching mask during the patterning process, the second contact holes CNH2may be formed in a self-alignment manner. The second contact holes CNH2may be filled with a conductive material to form contacts CNT. The contacts CNT may be connected to the second source/drain regions SD2. A data storage element DS may be formed on each of the contacts CNT. For example, the data storage element DS may be a capacitor. FIG.16illustrates a graph showing a hydrogen concentration versus a depth of an active pattern, according to exemplary embodiments of inventive concepts. In the embodiment that follows, a detailed description of technical features repetitive to those of the semiconductor device discussed above with reference toFIGS.1,2A to2C, and3will be omitted, and a difference thereof will be discussed in detail. Referring toFIGS.1,2A to2C,3, and16, the active pattern ACT may include hydrogen as a dopant. The active pattern ACT may have a dopant concentration (or a hydrogen concentration) that increases from the first level LV1toward the third level LV3. The hydrogen concentration may rapidly increase at the second level LV2. A threshold voltage of the amorphous oxide semiconductor constituting the active pattern ACT may be reduced with an increase in hydrogen concentration of the amorphous oxide semiconductor. In contrast, the threshold voltage of the amorphous oxide semiconductor may be increased with a decrease in hydrogen concentration of the amorphous oxide semiconductor. For example, the dopant concentration (or the hydrogen concentration) may be adjusted to control the threshold voltage of the amorphous oxide semiconductor. According to some exemplary embodiments of inventive concepts, the second segment UP of the active pattern ACT may have a relatively low hydrogen concentration. When a threshold voltage is raised due to a decrease in hydrogen concentration, a current leakage may be reduced. In consequence, a current leakage may be prevented at the second segment UP adjacent to the upper portion of the gate electrode GE. FIGS.17A and17Billustrate cross-sectional views respectively taken along lines B-B′ and C-C′ ofFIG.1, showing a semiconductor device according to exemplary embodiments of inventive concepts. In the embodiment that follows, a detailed description of technical features repetitive to those of the semiconductor device discussed above with reference toFIGS.1,2A to2C, and3will be omitted, and a difference thereof will be discussed in detail. Referring toFIGS.1,2A,17A, and17B, each of the gate electrodes GE may include a first electrode FM and a second electrode WF on the first electrode FM. The first electrode FM may be adjacent to the first segment LP of the active pattern ACT. The second electrode WF may be adjacent to the second segment UP of the active pattern ACT. The second electrode WF may include a material whose work function is different from that of the first electrode FM. The first electrode FM may include a metallic material (e.g., titanium, tantalum, tungsten, or copper). The second electrode WF may include a doped semiconductor material (e.g., doped n-type polysilicon) or a metallic material (e.g., aluminum). According to some exemplary embodiments of inventive concepts, the stacking of the second electrode WF on the first electrode FM may increase a threshold voltage of the second segment UP adjacent to the second electrode WF. In consequence, a current leakage may be prevented at the second segment UP adjacent to the second electrode WF. FIGS.18and19illustrate cross-sectional views taken along line A-A′ ofFIG.1, showing a semiconductor device according to exemplary embodiments of inventive concepts. In the embodiment that follows, a detailed description of technical features repetitive to those of the semiconductor device discussed above with reference toFIGS.1,2A to2C, and3will be omitted, and a difference thereof will be discussed in detail. Referring toFIGS.1and18, an insulation layer120may be interposed between the substrate100and the first semiconductor layer110. For example, the first semiconductor layer110may be formed on the insulation layer120. The insulation layer120may include a silicon oxide layer. Referring toFIGS.1and19, an insulation layer120and a seed layer130may be interposed between the substrate100and the first semiconductor layer110. For example, the first semiconductor layer110may be grown from the seed layer130on the insulation layer120. FIGS.20A,20B, and20Cillustrate cross-sectional views respectively taken along lines A-A′, B-B′, and C-C′ ofFIG.1, showing a semiconductor device according to exemplary embodiments of inventive concepts. In the embodiment that follows, a detailed description of technical features repetitive to those of the semiconductor device discussed above with reference toFIGS.1,2A to2C, and3will be omitted, and a difference thereof will be discussed in detail. Referring toFIGS.1and20A to20C, a second semiconductor layer115may be provided on the first semiconductor layer110. The second semiconductor layer115may cover a surface of each of the active patterns ACT. The second semiconductor layer115may be interposed between the device isolation layer ST and the active patterns ACT. The second semiconductor layer115may have a threshold voltage greater than that of the first semiconductor layer110. Since the second semiconductor layer115covers the active pattern ACT, a current leakage may be prevented at the active pattern ACT. For example, the second semiconductor layer115may include an amorphous oxide semiconductor identical to that of the first semiconductor layer110. The second semiconductor layer115may have an oxygen concentration greater than that of the first semiconductor layer110. For example, the oxygen concentration of the second semiconductor layer115may be greater than that of the first segment LP. The oxygen concentration of the second semiconductor layer115may be greater than that of the second segment UP. The second semiconductor layer115may have a hydrogen concentration less than that of the first semiconductor layer110. For another example, the second semiconductor layer115may include an amorphous oxide semiconductor different from that of the first semiconductor layer110. The first semiconductor layer110may include indium-gallium-zinc oxide (IGZO), and the second semiconductor layer115may include indium-tin-zinc oxide (ITZO). For another example, the second semiconductor layer115may include silicon (Si) or silicon carbide (SiC). FIG.21illustrates a simplified circuit diagram showing a cell array of a three-dimensional semiconductor memory device according to exemplary embodiments of inventive concepts. Referring toFIG.21, a three-dimensional semiconductor memory device according to some exemplary embodiments of inventive concepts may include a cell array consisting of a plurality of sub-cell arrays SCA. The sub-cell arrays SCA may be arranged along a second direction D2. Each of the sub-cell arrays SCA may include a plurality of bit lines BL, a plurality of word lines WL, and a plurality of memory cell transistors MCT. One memory cell transistor MCT may be disposed between one word line WL and one bit line BL. The bit lines BL may be conductive patterns (e.g., metal lines) that are spaced apart from and disposed on a substrate. The bit lines BL may extend in a first direction D1. The bit lines BL in one sub-cell array SCA may be spaced apart from each other in a vertical direction (i.e., a third direction D3). The word lines WL may be conductive patterns (e.g., metal lines) that extend in a vertical direction (i.e., the third direction D3) to the substrate. The word lines WL in one sub-cell array SCA may be spaced apart from each other in the first direction D1. A gate of the memory cell transistor MCT may be connected to the word line WL, and a source of the memory cell transistor MCT may be connected to the bit line BL. Each of the memory cell transistors MCT may include a data storage element DS. For example, the data storage element DS may be a capacitor, and a drain of the memory cell transistor MCT may be connected to the capacitor. FIG.22illustrates a perspective view showing a three-dimensional semiconductor memory device according to exemplary embodiments of inventive concepts.FIG.23illustrates an enlarged perspective view showing a unit cell of the three-dimensional semiconductor memory device ofFIG.22. Referring toFIGS.21,22, and23, a substrate100may be provided thereon with one of the plurality of sub-cell arrays SCA discussed with reference toFIG.21. For example, the substrate100may be provided thereon with a stack structure SS including first, second, and third layers FL1, FL2, and FL3. The first, second, and third layers FL1, FL2, and FL3of the stack structure SS may be stacked in a vertical direction (i.e., a third direction D3). Each of the first, second, and third layers FL1, FL2, and FL3may include a plurality of active patterns ACT, a plurality of data storage elements DS, and a bit line BL. The active patterns ACT may be arranged in a first direction D1. The active patterns ACT may have linear, bar, or pillar shapes extending in a second direction D2. Each of the active patterns ACT may include an amorphous oxide semiconductor. For example, each of the active patterns ACT may include indium-gallium-zinc oxide (IGZO) or indium-tin-zinc oxide (ITZO). Each of the active patterns ACT may include a first segment LP and a second segment UP. The first segment LP and the second segment UP may be adjacent to each other in the second direction D2. For example, the second segment UP may extend in the second direction D2from the first segment LP. The first segment LP may have an oxygen concentration less than that of the second segment UP. A detailed description of this may be substantially the same as that of the first segment LP and the second segment UP of the active pattern ACT discussed above with reference toFIG.3. Each of the active patterns ACT may include a channel region CH, a first source/drain region SD1, and a second source/drain region SD2. The channel region CH may be interposed between the first and second source/drain regions SD1and SD2. The first segment LP of the active pattern ACT may include the channel region CH and the first source/drain region SD1. The second segment UP of the active pattern ACT may include the second source/drain region SD2. The data storage element DS may be electrically connected to the second segment UP of the active pattern ACT. The data storage element DS may be electrically connected to the second source/drain region SD2of the active pattern ACT. For example, the data storage element DS may be a capacitor. The bit line BL may be electrically connected to the first segment LP of the active pattern ACT. The bit line BL may be electrically connected to the first source/drain region SD1of the active pattern ACT. According to some exemplary embodiments of inventive concepts, the second segment UP of the active pattern ACT may have a relatively high oxygen concentration. The second segment UP may have a relatively high threshold voltage. In consequence, a current leakage may be prevented at the second segment UP connected to the data storage element DS. According to some exemplary embodiments of inventive concepts, the first segment LP of the active pattern ACT may have a relatively low oxygen concentration. The first segment LP may have a relatively low threshold voltage. As a result, a current boosting effect may occur at the channel region CH of the first segment LP. In addition, a current may smoothly flow between the first segment LP and the bit line BL. The bit lines BL may have linear or bar shapes extending in the first direction D1. The bit lines BL may be stacked along the third direction D3. The bit lines BL may include a conductive material. For example, the conductive material may include one of doped semiconductor (doped silicon, doped germanium, etc.), conductive metal nitride (titanium nitride, tantalum nitride, etc.), metal (tungsten, titanium, tantalum, etc.), and metal-semiconductor compound (tungsten silicide, cobalt silicide, titanium silicide, etc.). The substrate100may be provided thereon with gate electrodes GE penetrating the stack structure SS. The gate electrodes GE may have linear, bar, or pillar shapes extending in the third direction D3. The gate electrodes GE may be arranged in the first direction D1. When viewed in plan, each of the gate electrodes GE may be provided between a pair of active patterns ACT adjacent to each other. Each of the gate electrodes GE may vertically extend on sidewalls of a plurality of active patterns ACT that are vertically stacked. The gate electrodes GE may correspond to the word lines WL ofFIG.21. For example, one of the gate electrodes GE may be adjacent to a first one of the active patterns ACT on the first layer FL1, a first one of the active patterns ACT on the second layer FL2, and a first one of the active patterns ACT on the third layer FL3. Another of the gate electrodes GE may be adjacent to a second one of the active patterns ACT on the first layer FL1, a second one of the active patterns ACT on the second layer FL2, and a second one of the active patterns ACT on the third layer FL3. The gate electrode GE may be adjacent to the channel region CH of the active pattern ACT. A gate dielectric layer GI may be interposed between the gate electrode GE and the channel region CH. The gate electrodes GE may include a conductive material, which conductive material may be one of doped semiconductor, conductive metal nitride, metal, and metal-semiconductor compound. The gate dielectric layer GI may include one or more of a silicon oxide layer, a silicon nitride layer, a silicon oxynitride layer, and a high-k dielectric material. The substrate100may be provided thereon with a common source line CSL extending in the first direction D1along one lateral surface of the stack structure SS. The first segment LP of the active pattern ACT may be coupled to the common source line CSL. The common source line CSL may be connected to a body of each of the memory cell transistors MCT discussed with reference toFIG.21. The common source line CSL may include a conductive material, which conductive material may be one of doped semiconductor, conductive metal nitride, metal, and metal-semiconductor compound. Although not shown, an insulating material may fill empty spaces in the stack structure SS. For example, the insulating material may include one or more of a silicon oxide layer, a silicon nitride layer, and a silicon oxynitride layer. FIG.24illustrates a plan view showing a semiconductor device according to exemplary embodiments of inventive concepts.FIGS.25A,25B, and25Cillustrate cross-sectional views respectively taken along lines A-A′, B-B′, and C-C′ ofFIG.24. Referring toFIGS.24and25A to25C, a substrate100may be provided to include a logic cell region. The logic cell region may be provided with logic transistors constituting a logic circuit of a semiconductor device. A first semiconductor layer110may be provided on the substrate100. The first semiconductor layer110may include an amorphous oxide semiconductor. The first semiconductor layer110may be provided thereon with a device isolation layer ST defining active patterns ACT. A first trench TR1may be defined between the active patterns ACT. A second trench TR2may be defined adjacent to the active patterns ACT. The second trench TR2may be deeper than the first trench TR1. The device isolation layer ST may fill the first and second trenches TR1and TR2. The active patterns ACT may have upper portions that vertically protrude beyond the device isolation layer ST. Each of the upper portions of the active patterns ACT may have a fin shape. Each of the active patterns ACT may include a first segment LP and a second segment UP. For example, the second segment UP may have an oxygen concentration greater than that of the first segment LP. The second segment UP may have a threshold voltage greater than that of the first segment LP. Source/drain regions SD may be provided on the upper portions of the active patterns ACT. The source/drain regions SD may be provided on the second segment UP of the active pattern ACT. The source/drain regions SD may be epitaxial patterns formed by a selective epitaxial growth process. A channel region CH may be defined between a pair of source/drain regions SD. The first segment LP of the active pattern ACT may include the channel region CH. The first semiconductor layer110may be configured in such a way that the second segment UP has a ratio (e.g., volume ratio) greater than that of the first segment LP. The second segment UP may surround the first segment LP. According to some exemplary embodiments of inventive concepts, the second segment UP of the active pattern ACT may have a relatively high threshold voltage. As a result, the second segment UP may prevent a current leakage. Gate electrodes GE may be provided to run across the active patterns ACT and to extend in a first direction D1. The gate electrodes GE may be spaced apart from each other in a second direction D2. The gate electrodes GE may vertically overlap the channel regions CH. For example, the gate electrodes GE may include one or more of metal and conductive metal nitride. A pair of gate spacers GS may be disposed on opposite sidewalls of each of the gate electrodes GE. The gate spacers GS may include one or more of a silicon oxide layer, a silicon nitride layer, and a silicon oxynitride layer. A gate dielectric layer GI may be interposed between the gate electrode GE and the active pattern ACT. The gate dielectric layer GI may include a high-k dielectric material. A gate capping layer GP may be provided on each of the gate electrodes GE. The gate capping layer GP may include one or more of a silicon oxide layer, a silicon nitride layer, and a silicon oxynitride layer. A first interlayer dielectric layer IL1may be provided on the substrate100. The first interlayer dielectric layer IL1may cover the gate spacers GS and the source/drain regions SD. A second interlayer dielectric layer IL2may be provided on the first interlayer dielectric layer IL1. For example, the first and second interlayer dielectric layers IL1and IL2may include silicon oxide layers. A pair of gate electrodes GE may be provided therebetween with one or more contacts AC that penetrate the first and second interlayer dielectric layers IL1and IL2and are electrically connected to the source/drain regions SD. The contact CNT may include one or more of metal and conductive metal nitride. According to other exemplary embodiments of inventive concepts, the second segment UP may have an oxygen concentration less than that of the first segment LP. For example, the second segment UP may have a threshold voltage less than that of the first segment LP. As a result, the second segment UP may generate a current boosting effect. A semiconductor device according to inventive concepts may include an active pattern consisting of an amorphous oxide semiconductor. An oxygen concentration in the active pattern may be changed to prevent a current leakage and to generate a current boosting effect, which may result in improving electrical characteristics of the semiconductor device. Although the present invention has been described in connection with the embodiments of inventive concepts illustrated in the accompanying drawings, it will be understood to those skilled in the art that various changes and modifications may be made without departing from the technical spirit and essential feature of inventive concepts. It will be apparent to those skilled in the art that various substitution, modifications, and changes may be thereto without departing from the scope and spirit of the inventive concepts. | 43,660 |
11862477 | DETAILED DESCRIPTION As a technique for forming an n-type or p-type diffusion region in a gallium oxide-based semiconductor layer, for example, silicon as an n-type dopant may be ion-implanted into a gallium oxide-based semiconductor layer, and then the gallium-oxide semiconductor layer may be annealed under a nitrogen atmosphere to activate the ion-implanted silicon. As a result, the n-type diffusion region may be formed. In gallium oxide-based semiconductors, the activation rate of the dopant tends to decrease particularly when the dopant concentration is high. Therefore, in order to form a highly conductive diffusion region, it is necessary to implant the dopant at a high concentration. However, when the dopant is ion-implanted at a high concentration, the gallium oxide-based semiconductor layer is likely to become structurally amorphous. In order to recover the crystals of such an amorphized gallium oxide-based semiconductor layer, the gallium oxide-based semiconductor layer needs to be subjected to an annealing treatment at a high temperature. However, such a high temperature annealing treatment promotes oxygen release from the gallium oxide-based semiconductor layer. Thus, when the diffusion region is formed in the gallium oxide-based semiconductor layer, there is a concern that crystal damage due to amorphization and oxygen vacancy defects remains. In the above, the drawback that the crystal damage remains in the gallium oxide-based semiconductor layer has been described by taking the case of forming a highly conductive diffusion region as an example. However, even when a low conductive diffusion region is formed, the crystal damage naturally remains in the gallium oxide-based semiconductor layer. The present disclosure provides a technique for forming a diffusion region in a gallium oxide-based semiconductor layer with less crystal damage in a manufacturing method of a semiconductor device having the gallium oxide-based semiconductor layer. According to an aspect of the present disclosure, a method for manufacturing a semiconductor device having a gallium oxide-based semiconductor layer includes: ion-implanting dopant into a gallium oxide-based semiconductor layer while heating the gallium oxide-based semiconductor layer; and annealing the gallium oxide-based semiconductor layer under an oxygen atmosphere, after the ion-implanting. In such a method, since the dopant is ion-implanted into the gallium oxide semiconductor layer while heating the gallium oxide semiconductor layer, it is possible to suppress the gallium oxide semiconductor layer from becoming amorphous during the ion implantation. Further, since the gallium oxide-based semiconductor layer is annealed under an oxygen atmosphere, oxygen leakage from the gallium oxide-based semiconductor layer during the annealing can be suppressed. According to the method described above, a diffusion region can be formed in the gallium oxide-based semiconductor layer in a state of less crystal damage. Hereinafter, as an embodiment, a method for manufacturing a semiconductor device having a gallium oxide-based semiconductor layer will be described with reference to the drawings. In particular, an ion implantation process and an annealing process of the manufacturing method will be described. In the manufacturing method, processes other than the ion-implantation process and the annealing process may be performed by known manufacturing techniques. A semiconductor device manufactured by using the ion implantation process and the annealing process described below is not particularly limited, but may be, for example, a MOSFET, an IGBT, or a diode. First, as shown inFIG.1, a gallium oxide-based semiconductor layer1is prepared. In an example, the gallium oxide-based semiconductor layer1is a single crystal of β-Ga2O3in which the surface1S has a plane orientation of (001). The crystal structure of the gallium oxide-based semiconductor layer1is not limited to the single crystal of β-Ga2O3, but may be another crystal structure, for example, a single crystal of α-Ga2O3. Further, the crystal structure of the gallium oxide-based semiconductor layer1may contain another atom, in addition to gallium (Ga) and oxygen (O). Next, as shown inFIG.2, a dopant2is ion-implanted into a part of the surface layer portion of the gallium oxide-based semiconductor layer1by using an ion implantation technique. Namely, an ion-implantation process is performed. Although not shown, a mask is formed on the surface1S of the gallium oxide semiconductor layer1, and the dopant2is ion-implanted to a part of the surface layer portion of the gallium oxide semiconductor layer1exposed from an opening of the mask. The dopant2may be ion-implanted into the surface layer portion of the gallium oxide-based semiconductor layer1through multiple steps. The type of dopant2is not particularly limited. In the example, the dopant2is nitrogen (N), which is a p-type dopant. As another example, the dopant2may be silicon, which is an n-type dopant. The dopant2is ion-implanted in the surface layer portion of the gallium oxide semiconductor layer1so that the dopant concentration is 1×1020cm−3or more.FIG.4shows a concentration profile of nitrogen ion-implanted in the gallium oxide-based semiconductor layer1. As shown inFIG.4, it is confirmed that the nitrogen concentration is 1×1020cm−3or more from the surface to a depth of 300 nm. The ion-implantation process is performed while heating the gallium oxide-based semiconductor layer1. In the example, the heating temperature of the gallium oxide-based semiconductor layer1is 500 degrees Celsius (° C.). Note that the heating temperature of the gallium oxide-based semiconductor layer1may be equal to or higher than 500° C. and equal to or lower than the melting point of the gallium oxide-based semiconductor layer1. When the heating temperature is 500° C. or higher, it is possible to suppress the gallium oxide semiconductor layer1from becoming amorphous due to implantation damage during the ion implantation. Since the amorphization is suppressed, the dopant2is efficiently introduced into the lattice position. When the heating temperature is equal to or lower than the melting point, it is possible to suppress the gallium oxide-based semiconductor layer1from melting during the ion implantation. Note that the upper limit of the heating temperature can be specifically 1200° C. When the heating temperature is 1200° C. or lower, the crystallinity of the gallium oxide-based semiconductor layer1is well maintained at the time of the ion implantation. Next, as shown inFIG.3, the gallium oxide-based semiconductor layer1is subjected to an annealing treatment to activate the dopant2, thereby to form the diffusion region3. Namely, an annealing process is performed. The annealing process is performed under an oxygen atmosphere. The heating temperature of the gallium oxide-based semiconductor layer1is not particularly limited, but is 1000° C. in the example. The heating time of the gallium oxide-based semiconductor layer1is not particularly limited, but is 30 minutes in the example. Note that the heating temperature and the heating time may be appropriately adjusted to other conditions. For example, the heating temperature may be equal to or higher than 1000° C. and equal to or lower than the melting point of the gallium oxide-based semiconductor layer1. When the heating temperature is 1000° C. or higher, the crystals in the amorphized region of the surface layer portion of the gallium oxide-based semiconductor layer1can be effectively recovered. When the heating temperature is equal to or lower than the melting point, it is possible to suppress the gallium oxide-based semiconductor layer1from melting during the annealing process. Note that the upper limit of the heating temperature can be specifically 1200° C. When the heating temperature is 1200° C. or lower, the crystallinity of the gallium oxide-based semiconductor layer1is well maintained during the annealing process. The heating time is not particularly limited, and may be appropriately adjusted. As described above, the annealing process is performed in the oxygen atmosphere. As a result, oxygen leakage from the gallium oxide-based semiconductor layer1during the annealing process can be suppressed, so an occurrence of oxygen vacancy defects can be suppressed. Therefore, in the annealing process, it is possible to recover the crystals in the amorphized region due to the ion implantation process while suppressing the occurrence of oxygen vacancy defects. As described above, the combination of the ion implantation process and the annealing treatment process enables formation of the diffusion region3in the surface layer portion of the gallium oxide-based semiconductor layer1with less crystal damage. FIG.5shows the results of qualitative evaluation of crystallinity using the Rutherford backscatter analysis method. A vertical axis of the graph ofFIG.5represents an index Xminof the backscattering intensity when the crystal is irradiated with He ions. The higher the value Xminis, the worse the crystallinity is. InFIG.5, a comparative example 1 shows the result of a sample that was not subjected to the ion implantation process and the annealing process. The value Xminof the comparative example 1 is a reference value (26.1%). The closer the value Xminof the sample is to the reference value, the less the crystal damage due to the ion implantation process and the annealing process is. A present example shows the result of a sample of the example of the embodiment, in which the ion implantation process was carried out at 500° C., and the annealing process was carried out under an oxygen atmosphere at 1000° C. for 30 minutes. A comparative example 2 shows the result of a sample in which the ion implantation process was carried out at room temperature and the annealing process was carried out under an oxygen atmosphere at 1000° C. for 30 minutes, which is the same condition as in the present example (i.e., 1000° C. for 30 minutes under an oxygen atmosphere). The value Xminof the comparative example 2 is increased by about 20 points as compared with the comparative example 1. It is presumed that the sample, which was amorphized in the ion implantation process, could not be sufficiently crystallized even in the annealing process. In the present example of the embodiment, the value Xminis lower than that of the comparative example 2. It is presumed that the crustal damage remaining in the gallium oxide-based semiconductor layer1was suppressed by the combination of the ion implantation process and the annealing process in the present example of the embodiment. Namely, it is presumed that the amorphization during the ion implantation process was suppressed, and the oxygen leakage was compensated in the annealing process to suppress the occurrence of oxygen vacancy defects. Further, in the present example, the ion implantation is carried out so that the dopant concentration is 1×1020cm−3or more in the surface layer portion of the gallium oxide semiconductor layer1. When the ion implantation is carried out so as to have such a high dopant concentration, the amorphization is likely to be promoted, resulting the residual crystal damage and the reduction of activation rate. According to the technique of combining the ion implantation process and the annealing process in the above-described embodiment, it is possible to form the diffusion region3with less crystal damage even when it is desired to form the diffusion region at such a high dopant concentration. Therefore, the above-mentioned technique according to the embodiment is particularly useful when it is desired to form the diffusion region at a high dopant concentration. However, the above-described technique of the embodiment is useful only on the point of the reduction of the crystal damage, and is also useful in a case where the ion implantation is carried out under a low dose condition in which the dopant concentration is in the range of 1×1016cm−3or more and 1×1019cm−3or less. Although the specific examples of the present disclosure have been described in detail above, these are merely examples and do not limit the scope of claims. The techniques described in the claims include various modifications and modifications of the specific examples illustrated above. In addition, the technical elements described in the present description or the drawings exhibit technical usefulness alone or in various combinations, and are not limited to the combinations described in the claims at the time of filing. In addition, the techniques illustrated in the present specification or drawings can achieve multiple purposes at the same time, and achieving one of the purposes itself has technical usefulness. | 12,855 |
11862478 | DETAILED DESCRIPTION OF THE DRAWINGS The present invention is described in one or more embodiments in the following description with reference to the figures, in which like numerals represent the same or similar elements. While the invention is described in terms of the best mode for achieving the invention's objectives, it will be appreciated by those skilled in the art that it is intended to cover alternatives, modifications, and equivalents as may be included within the spirit and scope of the invention as defined by the appended claims and their equivalents as supported by the following disclosure and drawings. The term “semiconductor die” as used herein refers to both the singular and plural form of the words, and accordingly, can refer to both a single semiconductor device and multiple semiconductor devices. The terms “die” and “semiconductor die” are used interchangeably. Semiconductor devices are generally manufactured using two complex manufacturing processes: front-end manufacturing and back-end manufacturing. Front-end manufacturing involves the formation of a plurality of die on the surface of a semiconductor wafer. Each die on the wafer contains active and passive electrical components, which are electrically connected to form functional electrical circuits. Active electrical components, such as transistors and diodes, have the ability to control the flow of electrical current. Passive electrical components, such as capacitors, inductors, and resistors, create a relationship between voltage and current necessary to perform electrical circuit functions. Back-end manufacturing refers to cutting or singulating the finished wafer into the individual semiconductor die and packaging the semiconductor die for structural support, electrical interconnect, and environmental isolation. To singulate the semiconductor die, the wafer is scored and broken along non-functional regions of the wafer called saw streets or scribes. The wafer is singulated using a laser cutting tool or saw blade. After singulation, the individual semiconductor die are mounted to a package substrate that includes pins or contact pads for interconnection with other system components. Contact pads formed over the semiconductor die are then connected to contact pads within the package. The electrical connections can be made with conductive layers, bumps, stud bumps, conductive paste, wirebonds, or other suitable interconnect structure. An encapsulant or other molding compound is deposited over the package to provide physical support and electrical isolation. The finished package is then inserted into an electrical system and the functionality of the semiconductor device is made available to the other system components. FIG.1ashows a semiconductor wafer100with a base substrate material102, such as silicon, germanium, aluminum phosphide, aluminum arsenide, gallium arsenide, gallium nitride, indium phosphide, silicon carbide, or other bulk semiconductor material. A plurality of semiconductor die or components104is formed on wafer100separated by a non-active, inter-die wafer area or saw street106as described above. Saw street106provides cutting areas to singulate semiconductor wafer100into individual semiconductor die104. In one embodiment, semiconductor wafer100has a width or diameter of 100-450 millimeters (mm). FIG.1Bshows a cross-sectional view of a portion of semiconductor wafer100. Each semiconductor die104has a back or non-active surface108and an active surface110containing analog or digital circuits implemented as active devices, passive devices, conductive layers, and dielectric layers formed within or over the die and electrically interconnected according to the electrical design and function of the die. For example, the circuit may include one or more transistors, diodes, and other circuit elements formed within active surface110to implement analog circuits or digital circuits, such as digital signal processor (DSP), ASIC, MEMS, memory, or other signal processing circuit. Semiconductor die104may also contain integrated passive devices (IPDs), such as inductors, capacitors, and resistors, for RF signal processing. Back surface108of semiconductor wafer100may undergo an optional backgrinding operation with a mechanical grinding or etching process to remove a portion of base material102and reduce the thickness of semiconductor wafer100and semiconductor die104. An electrically conductive layer112is formed over active surface110using PVD, CVD, electrolytic plating, electroless plating process, or other suitable metal deposition process. Conductive layers112include one or more layers of aluminum (Al), copper (Cu), tin (Sn), nickel (Ni), gold (Au), silver (Ag), or other suitable electrically conductive material. Conductive layer112operates as contact pads electrically connected to the circuits on active surface110. Conductive layer112can be formed as contact pads disposed side-by-side a first distance from the edge of semiconductor die104, as shown inFIG.1B. Alternatively, conductive layer112can be formed as contact pads that are offset in multiple rows such that a first row of contact pads is disposed a first distance from the edge of the die, and a second row of contact pads alternating with the first row disposed a second distance from the edge of the die. Conductive layer112represents the last conductive layer formed over semiconductor die104with contact pads for subsequent electrical interconnect to a larger system. However, there may be one or more intermediate conductive and insulating layers formed between the actual semiconductor devices on active surface110and contact pads112for signal routing. An electrically conductive bump material is deposited over conductive layer112using an evaporation, electrolytic plating, electroless plating, ball drop, or screen printing process. The bump material can be Al, Sn, Ni, Au, Ag, Pb, Bi, Cu, solder, and combinations thereof, with an optional flux solution. For example, the bump material can be eutectic Sn/Pb, high-lead solder, or lead-free solder. The bump material is bonded to conductive layer112using a suitable attachment or bonding process. In one embodiment, the bump material is reflowed by heating the material above its melting point to form conductive balls or bumps114. In one embodiment, conductive bumps114are formed over an under bump metallization (UBM) having a wetting layer, barrier layer, and adhesion layer. Conductive bumps114can also be compression bonded or thermocompression bonded to conductive layer112. Conductive bumps114represents one type of interconnect structure that can be formed over conductive layer112for electrical connection to a substrate. The interconnect structure can also use bond wires, conductive paste, stud bump, micro bump, or other electrical interconnect. InFIG.1c, semiconductor wafer100is singulated through saw street106using a saw blade or laser cutting tool118into individual semiconductor die104. The individual semiconductor die104can be inspected and electrically tested for identification of KGD post-singulation. FIG.2aillustrates a cross-section of an exemplary semiconductor package150prior to selectively forming a shielding layer. Semiconductor package150is a system-in-package (SiP) device in some embodiments. Substrate152includes one or more insulating layers154interleaved with one or more conductive layers156. Insulating layer154is a core insulating board in one embodiment, with conductive layers156patterned over the top and bottom surfaces, e.g., a copper-clad laminate substrate. Conductive layers156also include conductive vias electrically coupled through insulating layers154. Substrate152can include any number of conductive layers156and insulating layers154interleaved over each other. A solder mask or passivation layer can be formed over either side or both sides of substrate152. Openings are formed in the passivation layer to expose contact pads of conductive layer156for subsequent interconnection. Any suitable type of substrate or leadframe is used for substrate152in other embodiments. Typically, packages150are formed on substrate152as a panel large enough to form several to hundreds or thousands of packages at one time. Packages150are then singulated into individual packages, of whichFIG.2ashows an example, by cutting through encapsulant168and substrate152. Any components desired to be shielded in semiconductor package150are mounted to or disposed over substrate152within shielding area160and electrically connected to conductive layers156. A shielding interface area161is provided for connection of the subsequently formed shielding layer to ground strip171of conductive layer156. A non-shielding area162contains other components not intended to be shielded.FIG.2aillustrates semiconductor die104mounted on substrate152along with discrete electrical components164within shielding area160as an example. Discrete components164can be passive components such as capacitors, resistors, or inductors, active components such as diodes or transistors, or any other desired electrical component. Multiple semiconductor die can be disposed in shielding area160. Semiconductor die104can be provided as part of a smaller sub-package rather than a bare die. Semiconductor die104is mounted to substrate152by disposing the semiconductor die on the substrate using, e.g., a pick-and-place process or machine, and then reflowing bumps114to physically and electrically connect the bumps to exposed contact pads of conductive layer156. Discrete components164are connected by similar solder bumps or solder paste166. Solder paste166can be printed onto substrate152or discrete components164prior to picking and placing the discrete components onto the substrate. Reflowing solder paste166physically and electrically couples discrete components164to contact pads of conductive layer156. After mounting of semiconductor die104, discrete components164, and any other desired electrical components onto substrate152within shielding area160, the components are encapsulated by encapsulant or molding compound168. Encapsulant168is deposited over substrate152, semiconductor die104, and discrete components164using paste printing, compressive molding, transfer molding, liquid encapsulant molding, vacuum lamination, spin coating, or another suitable applicator. Encapsulant168can be polymer composite material, such as epoxy resin, epoxy acrylate, or polymer with or without a filler. Encapsulant168is non-conductive, provides structural support, and environmentally protects the semiconductor device from external elements and contaminants. A mask or other mechanism can be used to prevent encapsulant168from covering shielding interface area161and non-shielding area162. In other embodiments, encapsulant168is deposited over shielding interface area161and non-shielding area162and then removed in the non-shielding area. A passivation layer formed over the top of substrate152can operate as an etch stop layer while removing the encapsulant in non-shielding area162and shielding interface area161. Openings are formed in the passivation layer after encapsulant168is removed to expose ground strip171and contact pads of land grid array172. Any electrical components that are desired to be left unshielded are disposed on or over substrate152within non-shielding area162. Non-shielding area162is populated with electrical components after encapsulation with encapsulant168to reduce complexity of masking the non-shielding area from being encapsulated. In other embodiments, components can be disposed on substrate152in non-shielding area162prior to depositing encapsulant168. Components in non-shielded area162can include board-to-board connectors and other physical interfaces, antennae disposed over substrate152or formed as part of conductive layers156, additional discrete components164, or any other desired electrical components. InFIG.2a, no components are disposed or formed in non-shielding area162over substrate152. Contact pads of conductive layer156are left exposed as a land grid array172for electrical interconnection or for addition of electrical components at a later stage. Another portion of conductive layer156is left exposed in shielding interface area161as ground strip171.FIG.2bshows a top-down plan view of ground strip171and land grid array172. Land grid array172provides exposed contact pads to electrically connect to semiconductor die104or the underlying device that package150is incorporated into. The electrical connection can be made by soldering components or a physical port onto land grid array172, or a temporary connection can be made using a device with pogo pins or other suitable structure. FIG.2cshows a metal frame200and film202that will be used as a carrier during formation of a shielding layer over package150.FIG.2cincludes a top-down view on the left side of the figure and a cross-sectional view on the right side of the figure.FIGS.2d,2e, and2gsimilarly show both a top-down view and a cross-sectional view of their respective processing steps. Frame200can be formed of aluminum, copper, steel, or another suitable metal. Alternatively, frame200can be formed from plastic, wood, or any other suitable rigid material. A tape or film202is mounted onto frame200to form a support base for a plurality of packages150. Film202is formed from polyimide (PI) in one embodiment. Film202has an adhesive coated on a surface of the film to allow the film to stick to metal frame200and to allow packages150to adhere to the film. The adhesive on film202can be a thermal or ultraviolet (UV) release adhesive. InFIG.2d, a plurality of openings204is formed through film202using laser cutting tool206, a mechanical punch, or any other suitable mechanism. Openings204are smaller than the footprint of packages150to allow the packages to be disposed on film202over the openings. Openings204facilitate removal of packages150from film202after forming a shielding layer. InFIG.2e, packages150are disposed over openings204using a pick-and-place process or machine. The bottom of substrate152physically contacts film202all the way around opening204such that each opening204is completely covered by a package150. In one embodiment, the overlap of substrate152over film202around opening204is between 0.1 mm and 0.5 mm on each side of the substrate. In other embodiments, openings204extend partially outside of the footprints of packages150. Adhesive on film202sticks packages140to the film. FIG.2fshows a preformed mask220that will be placed over non-shielding area162to block a shielding layer from being formed directly on the underlying components. Mask220includes sides222, front224, back226, and top228that define a mask cavity230. Each of sides222, front224, and back226has a height in the Z-axis direction of the illustrated axis. Sides222have widths along the Y-axis and thicknesses along the X-axis. Front224and back226have widths along the X-axis and thicknesses along the Y-axis. Top228has a thickness along the Z-axis, a length along the X-axis, and a width along the Y-axis. Land grid array172is disposed in mask cavity230during formation of the shielding layer. Sides222and back226have heights that are at least as high as the top of substrate152. In embodiments with components disposed on substrate152within non-shielding area162, mask220is made at least as tall as the tallest component within non-shielding area162. The bottoms of sides222and back226can rest on film202with top228extending over land grid array172or other components. Front224has a bottom lip232that is raised higher than the bottoms of sides222and back226along the Z-axis. The opening under lip232provides space for substrate152to extend from under mask220to outside the mask. Lip232contacts, or nearly contacts, the top surface of substrate152while sides222and back224extend down to surround the end of the substrate with non-shielding area162. The length of lip232along the X-axis is approximately the same or slightly longer than a width of substrate152in the same direction so that sides222contact or nearly contact the sides of the substrate. The widths of sides222are greater than a width of non-shielding area162so that back226sits just outside a footprint of substrate152when lip232is placed on the border between shielding interface area161and non-shielding area162. Mask220is formed of metal, liquid-crystal polymer (LCP), plastic, polymer, Teflon, glass, rubber, wood, film, tape, foil, combinations thereof, or any other solid material that can withstand the process of forming a shielding layer. Mask220is formed by molding, by folding or working a sheet of material into the desired shape, or by any other suitable means. FIGS.2g-2ishow packages150with masks220picked and placed over non-shielding areas162.FIG.2gshows top-down and cross-sectional views, whileFIG.2hshows a perspective view andFIG.2ishows a detailed top-down plan view. Mask220covers non-shielding area162to block metal molecules from being deposited on land grid array172during sputtering of a shielding layer. Shielding area160and shielding interface area161remain exposed for the formation of a shielding layer over those areas. Land grid array172, or any desired non-shielded electrical components, are disposed within cavity230of mask220. The bottoms of sides222and back226rest on film202. Lip232on the bottom of front224contacts or is slightly above the top surface of substrate152. Top228extends over the top of land grid array172. The portion of substrate152within non-shielding area162extends between sides222. Sides222and back226are sized and positioned to contact or nearly contact substrate152. FIG.2jshows another embodiment where packages252each have two land grid arrays172, one on each of two opposite sides of substrate152. Two masks220are used per package to mask both land grid arrays. When two masks220of adjacent packages252are disposed directly adjacent to each other, a space ‘X’ of at least 2 mm is maintained between the masks. Any number of land grid arrays or other components can be used with masks220shaped appropriately to cover all of the non-shielded components. Multiple masks are used when the components are disposed in multiple groupings on substrate152. FIG.2k, continuing fromFIGS.2g-2i, illustrates a conductive material being sputtered over packages150, as indicated by arrows262, to form a shielding layer260. Shielding layer260is formed using any suitable metal deposition technique, e.g., chemical vapor deposition, physical vapor deposition, other sputtering methods, spraying, or plating. The sputtered material can be copper, steel, aluminum, gold, combinations thereof, or any other suitable shielding layer material. Shielding layer260completely covers exposed surfaces of package150and mask220. In particular, all four side surfaces and the top surface of encapsulant168are covered by shielding layer260to surround the encapsulated components. Shielding layer260covers mask220, but the sputtered metal does not penetrate the mask. Shielding layer260is therefore not formed directly on land grid array172. All side surfaces of substrate152other than within mask220are covered by shielding layer260. The top surface of substrate152in shielding interface area161, between encapsulant168and mask220, is covered by shielding layer260. The top surface of substrate152in shielding interface area161includes exposed ground strip171, or a plurality of discrete contact pads, of conductive layer156that shielding layer260physically contacts to provide an electrical connection to a ground voltage node. In some embodiments, a portion of conductive layer156is exposed at a side surface of substrate152so that shielding layer260physically contacts the conductive layer on the sides of the substrate as well. InFIG.2l, masks220are removed, including the portion of shielding layer260formed on the masks. Masks220can be removed using the same pick and place machine that placed the masks inFIG.2hor using any other suitable mechanism. With masks220removed, the area within frame200remains completely covered in shielding layer260other than openings in the shielding layer around land grid array172where masks220had been located. Masks220are reusable, so the pick and place machine places the masks into a tray or other suitable storage medium for later re-application onto the next set of packages to be shielded. Masks220may deteriorate after multiple uses, or have another factor that limits the number of times an individual mask can be used. Testing can be done on a particular mask design, and then each mask can be discarded after a suitable number of reuses determined via testing. A metal mask220can typically be reused about thirty times. Packages150are unloaded from frame200and film202inFIG.2m. An actuator270presses on the bottom of substrate152through openings204to release packages150from the adhesive of film202. A UV light or heat can be applied to reduce the effect of the adhesive between film202and substrates152. Actuator270can move from package to package in concert with a pick and place machine that takes the lifted package150and loads a JEDEC tray, tape and reel, or other similar storage medium with the shielded packages. Shielding layer260remains covering encapsulant168, a portion of the side surfaces of substrate152, and the top surface of the substrate within shielding interface area161. FIG.3shows an enlarged cross-section of a completed package150. Shielding layer260surrounds semiconductor die104and discrete components164on all sides and on top. Shielding layer260extends down the side surfaces of substrate152within shielding area160and shielding interface area161. Shielding layer260covers the top surface of substrate152within shielding interface area161, including physically contacting ground strip171. Masks220have ensured that shielding layer260does not cover the portion of substrate152with land grid array172so that the land grid array remains available for later use. In some embodiments, the bottom surface of substrate152, opposite semiconductor die104, has solder bumps or another suitable interconnect structure formed on contact pads of conductive layer156for attaching and connecting packages150to a larger PCB of an electronic device. Contact pads of conductive layer156can remain exposed on the bottom surface as a bottom land grid array rather than adding another interconnect structure. While the process illustrated uses a metal frame200and film202as a carrier for packages150during formation of shielding layer260, any suitable type of carrier can be used, such as a panel of glass, aluminum, steel, copper, polymer, silicon, or another suitable material. Mask220has the advantages of being simple and reducing costs. Simplicity is provided by using a mask that can be placed and removed using common pick-and-place processing equipment. Cost is reduced by reusing mask220. The overall process is streamlined by allowing non-shielded components to be disposed on substrate152during the same manufacturing stage as shielded components, e.g., semiconductor die104. Prior art masking methods, e.g., tape masking, require that non-shielding area162remain free of components until after the shielding layer is formed and the mask is removed. FIGS.4aand4bshow footprint views of another embodiment as mask300.FIG.4ais a plan view of top228, whileFIG.4bis a bottom plan view showing cavity230. Mask300is machined from a block of aluminum using a CNC milling machine, laser etching, chemical etching, or another suitable means. In other embodiments, mask300is molded or formed using another process. Mask300can be formed out of any suitable metal, polymer, or other material. The top and bottom views of mask300include minimal features that would be easy for a computer vision system to reliably distinguish. Even though a bottom surface302of mask300, lip232, and surface304within cavity230are all at different elevations when mask300is viewed from the bottom, a vision camera may not be able to recognize a border between the features depending on the exact angle and lighting in a given situation. Without any significant distinguishing visual features, a pick-and-place machine utilizing a vision camera to locate a mask300is likely to place the mask over a package150misaligned as shown inFIG.4c. Mask300inFIG.4chas an angular offset relative to package150indicated by the character theta (θ). Sides222of mask300should be parallel to the Y-axis inFIG.4c, while front224and back226should be parallel to the X-axis. However, theta misalignment causes the sides, front, and back to be off by an angle theta from the desired orientation. Depending on the exact positioning of mask300relative to non-shielding region162, the theta offset can cause multiple problems. The theta offset can result in a portion of ground strip171being covered by mask300, in which case the connection of shielding layer260to ground will end up not being as strong as originally intended. Such a manufacturing defect increases resistance to ground for shielding layer260and may result in a reduction in the performance of the shielding layer. Additionally, one or more contact pads of land grid array172may be outside of the protection of mask300, in which case shielding layer260will be formed extending to the exposed pads. Unexpectedly short circuiting a land grid array172contact pad to shielding layer260is likely to cause a malfunction in the end device. FIGS.5aand5billustrate a mask320with fiducial markers322aand322bon top228and fiducial markers324aand324bon surface304in cavity230. Fiducial markers322and324help a vision camera theta-align masks320by giving the camera two discrete and easily visible markers at opposite sides of the mask from each other. Markers322aand322bare aligned with each other along the y-axis and have significant separation from each other along the x-axis. In one embodiment, fiducial markers322are approximately centered between front224and back226, and a distance from the center of a fiducial to the closer side222is approximately equal to half the distance from the front to the back. Fiducial markers324can likewise be centered between three adjacent sidewalls within cavity230or may be formed directly under and aligned to fiducial markers322. In other embodiments, fiducials322and324can be formed at any suitable position. Fiducials322and324are formed using ink, paint, or another suitable substance disposed on mask320using printing, spraying through a mask, brushing over a mask, or another suitable mechanism to form the substance in the desired fiducial shape. In other embodiments, color is added to mask320by anodization to form fiducials322and324. Fiducials can be formed in any desired color that contrasts with mask320. The fiducials can contrast in any way, whether by being a different color, a different texture, a different material, or any other machine discernable difference. Fiducials322and324can also be formed by etching into the surfaces of mask320rather than or in addition to adding a colored material to the mask. Fiducials322and324can be formed in any suitable shape, such as circle, triangle, rectangle, square, cross, or star. The fiducial shapes can be outlines only or entirely filled in shapes. Fiducial markers322and324provide a pair of discrete markers on each side of mask320that a vision camera can easily distinguish. Either fiducials322or324, depending on whether the vision camera is located above or below mask320, are used by the vision camera to theta-align the mask to package150, thus ensuring a high likelihood that ground strip171will be fully exposed outside the mask and land grid array172will be fully covered by the mask. In one embodiment, a pick-and-place machine picks up a mask320, moves the mask over a vision camera, and then uses feedback from the vision camera to confirm alignment of fiducials324aand324bon the y-axis prior to disposing the mask over land grid array172. Top fiducials322also help the vision camera recognize mask320when removing the mask after formation of shielding layer260. Another problem with mask300is that a lack of feature contrast makes teaching the vision camera to recognize the mask difficult.FIG.6shows a mask330with surface304within cavity230anodized to create an anodized surface332. Surface302and the bottom of lip232are covered with a polyimide tape or other suitable mask during anodization so that the process colorizes the inside of cavity230while leaving a clearly distinguishable outline of uncolored mask330material surrounding the cavity. Anodized surface332creates a readily apparent light and shade boundary line at important vision teaching areas334. The teaching areas334after anodization create four straight lines clearly establishing the position of mask330for the vision camera. The contrast lines in teaching areas334makes training a vision camera to recognize mask330easy. Accurate training of the vision camera results in mask330being properly theta-aligned when disposed over land grid array172, thus reducing manufacturing defects. Contract can be provided between surface332and the surrounding surfaces302and232in any suitable manner. The contract can be provided by anodizing or otherwise depositing a material on one side, the other, or both. The anodizing can create a visible color contrast or a contrast that is invisible to the human eye but machine detectable. The contract can be a difference in color, texture, material, or any other quality of the surfaces or underlying material. A mask with both anodization and fiducial markers324can be formed by drilling or etching into surface332and only partially through top228after anodizing. The hole drilling removes a portion of the anodized surface, revealing the underlying color of raw mask330material, so that fiducial markers have a color and shade contrast due to the underlying raw mask330material. In other embodiments, fiducial markers324can be formed prior to anodization and then masked so that the markers are not covered up. Fiducial markers324may also be formed on top of the anodized surface304after anodization. FIG.7shows a mask340that adds a two-dimensional barcode342on anodized surface332. A quick response (QR) code is an example of a type of two-dimensional barcode that could be used. Other methods of embedding data into a visual representation on surface332can be used in other embodiments. Barcode342adds traceability to masks340. Each mask340can have a unique identification number embedded in barcode342that is used for tracking. A computer system can programmatically scan a barcode and log scan history, location, usage, application, and other aspects of masks340and their use. The tracking with barcode342allows monitoring of the number of uses each mask340has been through, so that a reuse limit can be easily enforced. The reuse limit reduces the likelihood that a mask340will be reused to the point of wear and tear causing malfunction. Barcode342is formed on surface332in cavity230, but could be formed on top228instead or in addition. Barcode342can be printed directly on surface332or304, or printed on a sticker and then adhered to the surface of mask340. Barcode342can be used with any of the above-disclosed embodiments. FIGS.8aand8billustrate incorporating the above described shielded packages, e.g., package150with shielding layer260, into an electronic device.FIG.8aillustrates a partial cross-section of package150mounted onto a printed circuit board (PCB) or other substrate402as part of an electronic device400. Bumps406are formed on conductive layer156on the bottom of substrate152. Conductive bumps406can be formed at any stage of the manufacturing process, e.g., prior to molding encapsulant168, prior to singulation, or after forming shielding layer260. Bumps406are reflowed onto conductive layer404of PCB402to physically attach and electrically connect package150to the PCB. In other embodiments, thermocompression or other suitable attachment and connection methods are used. In some embodiments, an adhesive or underfill layer is used between package150and PCB402. Semiconductor die104is electrically coupled to conductive layer404through substrate152and bumps406. FIG.8billustrates electronic device400including PCB402with a plurality of semiconductor packages mounted on a surface of the PCB, including package150with shielding layer260and land grid array172. Land grid array172can have an interconnect structure soldered to or pressed against the land grid array to connect package150to PCB402, another package on PCB402, another PCB of the same or different electronic device, another package on another PCB, another electronic device, testing equipment, etc. Land grid array172can also simply be left exposed for subsequent temporary electrical connection to package150. Alternatively, other components instead of land grid array172remain exposed to provide their intended function without shielding layer260interfering. Electronic device400can have one type of semiconductor package, or multiple types of semiconductor packages, depending on the application. Electronic device400can be a stand-alone system that uses the semiconductor packages to perform one or more electrical functions. Alternatively, electronic device400can be a subcomponent of a larger system. For example, electronic device400can be part of a tablet computer, cellular phone, digital camera, communication system, or other electronic device. Electronic device400can also be a graphics card, network interface card, or another signal processing card that is inserted into a computer. The semiconductor packages can include microprocessors, memories, ASICs, logic circuits, analog circuits, RF circuits, discrete active or passive devices, or other semiconductor die or electrical components. InFIG.8b, PCB402provides a general substrate for structural support and electrical interconnection of the semiconductor packages mounted on the PCB. Conductive signal traces404are formed over a surface or within layers of PCB402using evaporation, electrolytic plating, electroless plating, screen printing, or other suitable metal deposition process. Signal traces404provide for electrical communication between the semiconductor packages, mounted components, and other external systems or components. Traces404also provide power and ground connections to the semiconductor packages as needed. In some embodiments, a semiconductor device has two packaging levels. First level packaging is a technique for mechanically and electrically attaching the semiconductor die to an intermediate substrate. Second level packaging involves mechanically and electrically attaching the intermediate substrate to PCB402. In other embodiments, a semiconductor device may only have the first level packaging where the die is mechanically and electrically mounted directly to PCB402. For the purpose of illustration, several types of first level packaging, including bond wire package446and flipchip448, are shown on PCB402. Additionally, several types of second level packaging, including ball grid array (BGA)450, bump chip carrier (BCC)452, land grid array (LGA)456, multi-chip module (MCM)458, quad flat non-leaded package (QFN)460, quad flat package462, and embedded wafer level ball grid array (eWLB)464are shown mounted on PCB402along with package150. Conductive traces404electrically couple the various packages and components disposed on PCB402to package150, giving use of the components within package150to other components on the PCB. Depending upon the system requirements, any combination of semiconductor packages, configured with any combination of first and second level packaging styles, as well as other electronic components, can be connected to PCB402. In some embodiments, electronic device400includes a single attached semiconductor package, while other embodiments call for multiple interconnected packages. By combining one or more semiconductor packages over a single substrate, manufacturers can incorporate pre-made components into electronic devices and systems. Because the semiconductor packages include sophisticated functionality, electronic devices can be manufactured using less expensive components and a streamlined manufacturing process. The resulting devices are less likely to fail and less expensive to manufacture resulting in a lower cost for consumers. While one or more embodiments of the present invention have been illustrated in detail, the skilled artisan will appreciate that modifications and adaptations to those embodiments may be made without departing from the scope of the present invention as set forth in the following claims. | 36,807 |
11862479 | DETAILED DESCRIPTION In the drawings, like reference numerals refer to like elements throughout, and the various features are not necessarily drawn to scale. In the following discussion and in the claims, the terms “including”, “includes”, “having”, “has”, “with”, or variants thereof are intended to be inclusive in a manner similar to the term “comprising”, and thus should be interpreted to mean “including, but not limited to . . . .” Also, the term “couple” or “couples” is intended to include indirect or direct electrical or mechanical connection or combinations thereof. For example, if a first device couples to or is coupled with a second device, that connection may be through a direct electrical connection, or through an indirect electrical connection via one or more intervening devices and connections. The various features of the disclosed examples can be used in connection with a variety of different semiconductor devices, including without limitation integrated circuits having multiple electronic components, as well as single component semiconductor devices (e.g., single transistor products, single diode products, etc.). Referring initially toFIGS.1and2, an example method100for fabricating a semiconductor device200in accordance with the present disclosure is shown. The method100begins at102, where first and second semiconductor dies are mounted to a die pad of a leadframe in spaced apart relation. The leadframe can be part of a panel of multiple leadframes, each having a die pad and a plurality of preformed contacts. Two semiconductor dies are mounted in spaced apart relation on a die pad of single leadframe, but it will be understood that more than two semiconductor dies can be mounted to a single die pad in spaced apart relation without departing from the scope of this disclosure. Mounting the semiconductor dies in spaced apart relation allows the die pad to be separated into (at least) first and second electrically isolated die pad portions each having a semiconductor die supported thereon during subsequent processing steps. At104, the first and second semiconductor dies are electrically coupled to at least one preformed contact of the leadframe. In one example, the electrical coupling can be by wirebonding, flipchip, or any other suitable manner of electrically connecting the semiconductor dies with the preformed contacts. At106, a molding structure is formed. The molding structure generally includes at least a portion of the semiconductor dies and at least a portion of the preformed contacts encapsulated/enclosed by a molding compound. Any suitable material can be used for forming the molding structure, such as epoxy, resin, or the like. At108, a trench is formed in the molding structure in a space between the first and second semiconductor dies. The trench has a depth and a position so as to separate the die pad into first and second die pad portions, each die pad portion supporting a semiconductor die. In some embodiments, the trench extends approximately halfway through a thickness of the molding structure. In one example, the trench is formed through at least a portion of the molding compound and at least a portion of the die pad. In other embodiments, the trench may only extend through the die pad, and not necessarily through any of the molding compound of the molding structure. In one example, the trench is formed through a reduced cross-sectional thickness portion of the die pad. The semiconductor dies are mounted to the die pad on opposite sides of the reduced cross-sectional thickness portion such that the reduced cross-sectional thickness portion of the die pad is generally located in the space between the spaced-apart semiconductor dies. This reduces the amount of conductive material that must be removed to form the trench/separate the die pad into first and second die pad portions. The reduced cross-sectional thickness portion can be, in some embodiments, a half-etched die pad having a trench extending in a plane perpendicular to the thickness dimension of the die pad. The trench can be on either face of the die pad (e.g., a face on which the semiconductor dies are mounted, or an opposite face). In one example, the trench is filled at110with a filler material (e.g., filler resin) to seal the trench and/or provide a planar surface. In other implementations the filling at110is omitted. Although the trench can be filled with a filler material, it is still referred to as a trench in this description whether it is filled or unfilled. At112, individual semiconductor devices are singulated from the panel of multiple semiconductor devices, such as by sawing. FIG.2shows two representative individual semiconductor devices200made in accordance with example method100are illustrated. Any number of semiconductor devices200can be made in accordance with aspects of the present disclosure. Each semiconductor device200, in one example, includes a first semiconductor die202mounted on a first die pad portion204and a second semiconductor die206mounted on a second die pad portion208. Each semiconductor die202and206in this example is electrically coupled to at least one preformed contact or lead210via bond wires212. The semiconductor dies202and206are also electrically coupled to each other by a bond wires214. An enclosure is formed by a molding compound218that encapsulates the semiconductor dies202and206, bond wires212and214, at least a portion of the preformed leads210, and at least a portion of the first and second die pad portions204and208. A trench220electrically isolates the first and second die pad portions204and208. The trench220in the illustrated embodiment has a depth D that corresponds to approximately half of a thickness T of the semiconductor device200. However, in other embodiments the trench220can have a different depth. In one example, the trench220is formed by removing at least a portion of the conductive material of the die pad of the leadframe to separate the die pad into the first and second die pad portions204and208. FIGS.3-8show the various stages of forming the semiconductor devices200. InFIG.3, a portion of a panel302of multiple leadframes304is illustrated. The panel302can include a leadframe array of virtually any size, andFIGS.3-8show two example leadframes304as part of the panel302. Each leadframe302in this example includes at least one die pad308and multiple preformed leads210. For simplicity, preformed leads210are only shown on the sides of the die pad308but additional preformed leads may surround the die pad308. Prior to singulation of the semiconductor dies from the panel302(e.g.,112inFIG.1), the preformed leads of adjacent leadframes304may be a common conductive structure that is subsequently severed during the singulation step. In one example, the preformed leads of adjacent leadframes may be separate conductive structures prior to singulation. As shown in the example ofFIG.4, each die pad308has a generally planar upper surface408upon which the first and second semiconductor dies202and206are mounted, while a lower surface410of each die pad308has a trench412. Trench412is centrally located and extends in a plane perpendicular to a thickness dimension T of the die pad308. The trench412results in a reduced cross-sectional thickness portion414of the die pad308. The trench412in one example is formed by etching the conductive material of the die pad308, or by other suitable methods. The trench220in one example is ultimately formed through the reduced cross-sectional thickness portion414of the die pad308so as to separate the die pad308into first and second die pad portions204and208. InFIG.5, the semiconductor dies202and206are mounted to the upper surface408of the die pad308(e.g.,102and104inFIG.1). Each semiconductor die202and206in one example is electrically coupled to one or more preformed leads210via bond wires212. The semiconductor dies202and206are also electrically connected to each other via one or more bond wires214. InFIG.6, a molding structure602is formed (e.g.,106inFIG.1). In one example, the molding compound218is applied and encapsulates the semiconductor dies202and206, bond wires212and214, at least a portion of the preformed contacts210, and at least a portion of the first and second die pad portions204and208. In one example, the molding compound218at least partially fills the trench412. InFIG.7, the trench220is formed (e.g.,108inFIG.1). In one example, the trench220extends through the reduced cross-sectional thickness portion414of the die pad308and thereby separates the die pad308into first and second die pad portions204and208. One method of forming the trench220is with a tape saw that is configured to saw approximately half-way through a thickness of the molding structure602. By forming the trench220at the reduced cross-sectional thickness portion414of the die pad308, the amount of wear on the tape saw is minimized as compared to forming the trench through a relatively thicker portion of the die pad308, as would be the case if trench412did not exist and the die pad308had a uniform thickness. That is, the amount of conductive material that must be removed by the tape saw in order to separate the die pad308into two die pad portions is minimized or reduced by sawing through the reduced cross-sectional thickness portion414of the die pad308. In various implementations, the relative dimensions of the overall thickness of the die pad308and the reduced cross-sectional thickness portion414formed by the trench412can be optimized to provide increased tape saw life while maintaining die pad support during fabrication processes. In one example, the reduced cross-sectional thickness portion414has a thickness that is approximately half of the overall thickness T of the die pad308. In other examples, the reduced cross-sectional thickness portion can be more or less than half of the overall thickness of the die pad308. In other examples, the reduced cross-sectional thickness portion can be eliminated, and the trench412can be formed through the full thickness of the die pad308. After forming the trench220, the trench220in one example is filled with a filler material702, as shown for example on the right side ofFIG.7(e.g.,108inFIG.1). In other examples, the filler material is omitted. InFIG.8, the devices200are singulated (e.g., as in process step112) by separating the devices200from the panel302, including cutting through the common conductive structure forming preformed leads210of each leadframe304. Singulation can be performed in any suitable manner, such as with a tape saw or other saw. The reduced thickness portion414of the die pad308of the leadframe304can be formed in one example by a trench in the top surface410of the die pad308, as opposed to the trench410of the examples ofFIGS.2-8which is formed in the bottom surface410of the die pad308. FIG.9shows first and second leadframes902having such configuration. The leadframes902can be part of a panel of leadframes (e.g., panel302) and can be substituted directly for leadframes304in the device and process described in connection withFIGS.1-8without otherwise modifying such device and process. Each leadframe902in one example includes at least one die pad908and multiple preformed leads910. Each die pad908in this example has a generally planar lower surface914, and an upper surface916upon which first and second semiconductor dies can be mounted on opposing sides of a trench918. Trench918is centrally located and extends in a plane perpendicular to a thickness dimension TDP of the die pad908. The trench918results in a reduced cross-sectional thickness portion918of the die pad908. The trench918can be formed by etching the conductive material of the die pad908, or by other suitable methods. The leadframes902can be otherwise processed in a similar manner to the leadframes302ofFIGS.1-8to produce semiconductor devices having at least two electrically isolated die pads/semiconductor dies in accordance with the present disclosure. Aspects of the present disclosure provide a method to produce semiconductor packages having multiple semiconductor dies supported on respective die pad portions that facilitates full support of the die pads during package processing, without the use of pre-molded or pre-taped leadframes. Aspects of the present disclosure can be implemented to provide a more cost-effective solution for manufacturing semiconductor packages having multiple semiconductor dies. Modifications are possible in the described embodiments, and other embodiments are possible, within the scope of the claims. | 12,629 |
11862480 | DETAILED DESCRIPTION Before describing several exemplary embodiments of the disclosure, it is to be understood that the disclosure is not limited to the details of construction or process steps set forth in the following description. The disclosure is capable of other embodiments and of being practiced or being carried out in various ways. Many of the details, dimensions, angles and other features shown in the Figures are merely illustrative of particular embodiments. Accordingly, other embodiments can have other details, components, dimensions, angles and features without departing from the spirit or scope of the present disclosure. In addition, further embodiments of the disclosure can be practiced without several of the details described below. As used in this specification and the appended claims, the term “substrate” refers to a surface, or portion of a surface, upon which a process acts. It will also be understood by those skilled in the art that reference to a substrate can also refer to only a portion of the substrate, unless the context clearly indicates otherwise. Additionally, reference to depositing on a substrate can mean both a bare substrate and a substrate with one or more films or features deposited or formed thereon A “substrate” as used herein, refers to any substrate or material surface formed on a substrate upon which film processing is performed during a fabrication process. For example, a substrate surface on which processing can be performed include materials such as silicon, silicon oxide, strained silicon, silicon on insulator (SOI), carbon doped silicon oxides, amorphous silicon, doped silicon, germanium, gallium arsenide, glass, sapphire, and any other materials such as metals, metal nitrides, metal alloys, and other conductive materials, depending on the application. Substrates include, without limitation, semiconductor wafers. Substrates may be exposed to a pretreatment process to polish, etch, reduce, oxidize, hydroxylate, anneal, UV cure, e-beam cure and/or bake the substrate surface. In addition to film processing directly on the surface of the substrate itself, in the present disclosure, any of the film processing steps disclosed may also be performed on an underlayer formed on the substrate as disclosed in more detail below, and the term “substrate surface” is intended to include such underlayer as the context indicates. Thus for example, where a film/layer or partial film/layer has been deposited onto a substrate surface, the exposed surface of the newly deposited film/layer becomes the substrate surface. As used in this specification and the appended claims, the terms “reactive compound,” “reactive gas,” “reactive species,” “precursor,” “process gas,” and the like are used interchangeably to mean a substance with a species capable of reacting with the substrate surface or material on the substrate surface in a surface reaction (e.g., chemisorption, oxidation, reduction). For example, a first “reactive gas” may simply adsorb onto the surface of a substrate and be available for further chemical reaction with a second reactive gas. Tremendous efforts have been devoted to reduce the outgassing of polymers during under bump metallization (UBM), such as temperature control and RF power tuning, etc. In one or more embodiments, covering the inner shield or walls of a processing chamber with one or more of titanium (Ti), barium (Ba), or cerium (Ce) through a pasting method helps to absorb outgassing molecules. As used herein, the term “pasting” refers to sputtering of a getter material such that the material adheres to the walls of a processing chamber, forming a layer of the getter material on the walls. In one or more embodiments, the concentration of outgassing molecules in the processing chamber can advantageously be significantly reduced. Accordingly, in one or more embodiments, the recontamination of the metal contact surface is minimized, helping to keep low contact resistance for better electronic device performance. Embodiments of the disclosure provide shutter disks comprising one or more of titanium (Ti), barium (Ba), or cerium (Ce) for physical vapor deposition (PVD) that allows pasting to minimize outgassing and control defects during etching of substrate. One or more embodiments provide improved and/or increased useful lifetime of the process kit. In one or more embodiments, it has been observed that pasting a getter material on/in a processing chamber, e.g. a pre-clean chamber, decreases the outgassing molecule concentration by at least two orders of magnitude. The observed results are superior to other methods, such as increasing pumping speed and improved gas conductance. Embodiments of the disclosure incorporate getter materials that are highly selective to reactive gas molecules, such as oxygen (O2), carbon monoxide (CO), carbon dioxide (CO2), and water (H2O). These reactive gas molecules can be detrimental to metal contact resistance in PVD deposited devices. Some embodiments advantageously provide titanium (Ti), barium (Ba), or cerium (Ce) shutter disks that minimize shield outgassing, extends shield kit life, prevents recontamination to metal surfaces, acts as getter materials, absorbs outgassing molecules including oxygen (O2), carbon monoxide (CO), carbon dioxide (CO2), and water (H2O) during processing, are capable of withstanding high temperature, and/or have minimum warpage during processing. Embodiments of the disclosure do not need chamber hardware modification, but instead utilize a shutter disk containing or comprising a getter material. In one or more embodiments, the shutter disk is transferred to the processing chamber and RF power is used to perform a sputtering process, sputtering the getter material on the sides of the processing chamber. In one or more embodiments, the shutter disk is insensitive to inert gas molecules such as argon (Ar) and helium (He), and, therefore, inert gas molecules have limited impact on the physical plasma sputtering effect in the pre-clean process. With reference toFIGS.1-4, one or more embodiments are directed to a method100of processing a substrate. The method illustrated inFIG.1is representative of a physical vapor deposition (PVD) process. As used herein, the terms “physical vapor deposition” or, alternatively, “sputtering” refer to a process for deposition of metals and related materials in the fabrication of semiconductor integrated circuits. Use of sputtering has been extended to depositing metal layers onto the sidewalls of high aspect-ratio holes such as vias or other vertical interconnect structures. Plasma sputtering may be accomplished using either DC sputtering or RF sputtering. Plasma sputtering typically includes a magnetron positioned at the back of the sputtering target including two magnets of opposing poles magnetically coupled at their back through a magnetic yoke to project a magnetic field into the processing space to increase the density of the plasma and enhance the sputtering rate from a front face of the target. Magnets used in the magnetron are typically closed loop for DC sputtering and open loop for RF sputtering. In plasma enhanced substrate processing systems, such as physical vapor deposition (PVD) chambers, high power density PVD sputtering with high magnetic fields and high DC power can produce high energy at a sputtering target, and cause a large rise in surface temperature of the sputtering target. The sputtering target is cooled by contacting a target backing plate with cooling fluid. In plasma sputtering as typically practiced commercially, a target of the material to be sputter deposited is sealed to a vacuum chamber containing the wafer to be coated. An inert gas, argon (Ar) for example, is admitted to the chamber. When a negative DC bias of several hundred volts is applied to the target while the chamber walls or shields remain grounded, the inert gas is excited into a plasma. The positively charged inert gas ions are attracted to the negatively biased target at high energy and sputter target atoms from the target. In one or more embodiments, at operation10, a getter material204is deposited on at least one wall of a processing chamber200. In one or more embodiments, the getter material204is deposited to a thickness202on the at least one wall of the processing chamber200. In one or more embodiments, the thickness202is greater than or equal to 10 nm, including a range of about 10 nm to about 100 μM. In one or more embodiments, the getter material206comprises one or more of titanium (Ti), barium (Ba), or cerium (Ce). In one or more embodiments, the getter material204is obtained by sputtering a shutter disk206. In one or more embodiments the sputtering process comprises exposing the shutter disk206to a plasma208. In one or more embodiments, the plasma208comprises an inert plasma. In some embodiments, the plasma208comprises one or more of argon (Ar) or helium (He). In one or more embodiments, the plasma208may be generated remotely or within the processing chamber200. In one or more embodiments, the plasma208is an inductively coupled plasma (ICP) or a conductively coupled plasma (CCP). Any suitable power can be used depending on, for example, the reactants, or the other process conditions. In some embodiments, the plasma208is generated with a plasma power in the range of about 10 W to about 3000 W. In some embodiments, the plasma208is generated with a plasma power less than or equal to about 3000 W, less than or equal to about 2000 W, less than or equal to about 1000 W, less than or equal to about 500 W, or less than or equal to about 250 W. In one or more embodiments, the shutter disk206comprises one or more of titanium (Ti), barium (Ba), or cerium (Ce). In a specific embodiment, the shutter disk206comprises titanium (Ti), and, upon sputtering, releases a getter material204comprising titanium (Ti) such that titanium is deposited on at least one wall of the processing chamber200. In one or more embodiments, at operation20, the shutter disk206is then moved or transferred to a buffer station. In some embodiments, the buffer station is located within the processing chamber200. In other embodiments, the buffer station is located in an adjacent chamber. In one or more embodiments, the shutter disk206is transferred by a robot. In one or more embodiments, at operation30, a substrate209is then positioned within the processing chamber200. In one or more embodiments, the substrate209comprises one or more of a silicon layer210, an oxide layer212, a metal layer214, a polymer layer216, or a native oxide layer218. In one or more embodiments, the oxide layer212comprises an aluminum oxide layer. In one or more embodiments, the metal layer214comprises one or more of aluminum (Al) or copper (Cu). In one or more embodiments, the polymer layer216comprises one or more of polyimide or polybenzoxazole. In one or more embodiments, at operation40, the substrate209is etched in the processing chamber200. In one or more embodiments, the substrate209is etched by a plasma208. In one or more embodiments, the plasma208comprises an inert plasma. In some embodiments, the plasma208comprises one or more of argon (Ar) or helium (He). In some embodiments, the plasma208is the same as the plasma used to sputter the getter material204on at least one side wall of the processing chamber. In other embodiments, the plasma208is different than the plasma that is used to sputter the getter material204. Without intending to be bound by theory, upon etching of the polymer layer216of the substrate209, the substrate209releases outgassing molecules, for example220,222,224,226. In one or more embodiments, the outgassing molecules are absorbed by the getter material204which was deposited on the sides of the processing chamber200. In one or more embodiments, the outgassing molecules comprise one or more of oxygen (02), carbon monoxide (CO), carbon dioxide (CO2) or water (H2O). As illustrated inFIG.4, because the getter material is able to absorb the outgassing molecules, the concentration of outgassing molecules in the processing chamber is significantly reduced, and, therefore, the recontamination to the metal contact surface214of the substrate209is minimized so as to keep low contact resistance for better electronic device performance. In one or more embodiments, the amount of outgassing molecules from the substrate209is reduced to less than or equal to about 10% of the outgassing molecules from a substrate in the processing chamber that does not contain the getter material. In one or more specific embodiments, the amount of outgassing carbon monoxide (CO) from the substrate209is reduced to less than or equal to about 10% of the outgassing carbon monoxide (CO) from a substrate in the processing chamber that does not contain the getter material. FIG.5shows a processing tool300in accordance with one or more embodiments of the disclosure. The embodiment shown inFIG.5is merely representative of one possible configuration and should not be taken as limiting the scope of the disclosure. For example, in some embodiments, the processing tool300has a different numbers of one or more of the processing chambers302, buffer stations310and/or robot308configurations than the illustrated embodiment. The exemplary processing tool300includes a processing chamber302, e.g. pre-clean chamber, which has a plurality of sides. The processing chamber302shown has a first side303a, a second side303b, a third side303c, and a fourth side303d. Although four sides are shown, those skilled in the art will understand that there can be any suitable number of sides to the processing chamber302depending on, for example, the overall configuration of the processing tool300. In some embodiments, there the processing chamber302has three sides, four sides, five sides, six sides, seven sides or eight sides. The processing chamber302has a robot308positioned therein. The robot308can be any suitable robot capable of moving a wafer during processing. In some embodiments, the robot308has a first arm309aand a second arm309b. The first arm309aand second arm309bcan be moved independently of the other arm. The first arm309aand second arm309bcan move in the x-y plane and/or along the z-axis. In some embodiments, the robot308includes a third arm (not shown) or a fourth arm (not shown). Each of the arms can move independently of other arms. The processing tool300can also include one or more buffer station310connected to the first side303aof the processing chamber302. The buffer stations310can perform the same or different functions. For example, the buffer stations may hold a cassette of wafers which are processed and returned to the original cassette, or one of the buffer stations may hold unprocessed wafers which are moved to the other buffer station after processing. In some embodiments, one or more of the buffer stations are configured to pre-treat, pre-heat or clean the wafers before and/or after processing. The processing tool300may also include one or more slit valves312between the processing chamber302and the buffer station310. The slit valves312can open and close to isolate the interior volume within the processing chamber302. For example, if the processing chamber302will generate plasma during processing, it may be helpful to close the slit valve for that processing chamber to prevent stray plasma from damaging the robot in the transfer station. A robot308can be used to move the wafers or cassettes into and out of the buffer stations310. The wafers or cassettes can be moved within the processing tool300by the robot308. In one or more embodiments, the robot308moves the shutter disk into and out of the processing chamber302to the buffer station310. A controller314may be provided and coupled to various components of the processing tool300to control the operation thereof. The controller314can be a single controller that controls the entire processing tool300, or multiple controllers that control individual portions of the processing tool300. For example, the processing tool300may include separate controllers for each of the processing chambers302, buffer station310, and robots308. In some embodiments, the processing chamber302further comprises a controller314connected to the plurality of substantially coplanar support surfaces304. In one or more embodiments, the controller314controls a movement speed of the substrate support assembly304. In some embodiments, the controller314includes a central processing unit (CPU)316, a memory318, input/outputs (I/O)320, and support circuits322. The controller314may control the processing tool300directly, or via computers (or controllers) associated with particular process chamber and/or support system components. The controller314may be one of any form of general-purpose computer processor that can be used in an industrial setting for controlling various chambers and sub-processors. The memory318or computer readable medium of the controller314may be one or more of readily available memory such as random access memory (RAM), read only memory (ROM), floppy disk, hard disk, optical storage media (e.g., compact disc or digital video disc), flash drive, or any other form of digital storage, local or remote. The memory318can retain an instruction set that is operable by the processor (CPU316) to control parameters and components of the processing tool300. The support circuits322are coupled to the CPU316for supporting the processor in a conventional manner. These circuits include cache, power supplies, clock circuits, input/output circuitry and subsystems, and the like. One or more processes may be stored in the memory318as software routine that, when executed or invoked by the processor, causes the processor to control the operation of the processing tool300or individual processing chambers in the manner described herein. The software routine may also be stored and/or executed by a second CPU (not shown) that is remotely located from the hardware being controlled by the CPU316. Some or all of the processes and methods of the present disclosure may also be performed in hardware. As such, the process may be implemented in software and executed using a computer system, in hardware as, e.g., an application specific integrated circuit or other type of hardware implementation, or as a combination of software and hardware. The software routine, when executed by the processor, transforms the general purpose computer into a specific purpose computer (controller) that controls the chamber operation such that the processes are performed. In some embodiments, the controller314has one or more configurations to execute individual processes or sub-processes to perform the method. The controller314can be connected to and configured to operate intermediate components to perform the functions of the methods. For example, the controller314can be connected to and configured to control one or more of gas valves, actuators, motors, slit valves, vacuum control or other components. Reference throughout this specification to “one embodiment,” “certain embodiments,” “one or more embodiments” or “an embodiment” means that a particular feature, structure, material, or characteristic described in connection with the embodiment is included in at least one embodiment of the disclosure. Thus, the appearances of the phrases such as “in one or more embodiments,” “in certain embodiments,” “in one embodiment” or “in an embodiment” in various places throughout this specification are not necessarily referring to the same embodiment of the disclosure. Furthermore, the particular features, structures, materials, or characteristics may be combined in any suitable manner in one or more embodiments. Although the disclosure herein has been described with reference to particular embodiments, those skilled in the art will understand that the embodiments described are merely illustrative of the principles and applications of the present disclosure. It will be apparent to those skilled in the art that various modifications and variations can be made to the method and apparatus of the present disclosure without departing from the spirit and scope of the disclosure. Thus, the present disclosure can include modifications and variations that are within the scope of the appended claims and their equivalents. | 20,442 |
11862481 | DETAILED DESCRIPTION Embodiments describe chip sealing structures which can accommodate die-to-die routing for inter-die or intra-die connections. The chip sealing structures may facilitate interconnection between adjacent circuit blocks, as well as arrayed harvesting where variable die sets and shapes can be selected and harvested from a source wafer. Exemplary structures include split metallic seal structures where the die-to-die routing extends through the split metallic seal structures, sealed box structures where the die-to-die routing jumps over the seal structures, back side die-to-die routing using nano or micro through silicon vias (TSVs), and electromagnetic field communication to communicate across adjacent seal structures without physical wiring. The seal structures in accordance with embodiments may also guard against microcracking, delamination, moisture ingress, ion diffusion, etc. toward a die core region, even when adjacent a scribed die edge (e.g. through the die-to-die routing). In one aspect, embodiments describe split metallic seal structures including lower and upper metallic seals which can overlap in a same metallization layer to block a free line of sight. Such a split metallic seal structure may allow for through seal interconnect routing to weave between the metallic seals, while the blocked free line of sight provides protection against microcracking, delamination, moisture ingress, ion diffusion, etc. As used herein, a through seal interconnect may be a portion of a die-to-die routing that extends through a split metallic seal structure, whether the die-to-die routing is diced or connects adjacent die areas. In an embodiment a chip structure includes a semiconductor substrate, and a first front-end-of-the-line (FEOL) die area of a first die patterned into the semiconductor substrate. A back-end-of-the-line (BEOL) build-up structure is formed over the first FEOL die area, with the BEOL build-up structure including a plurality of metallization layers including lower metallization layers and upper metallization layers spanning over the first FEOL die area. The BEOL build-up structure further includes a split metallic seal structure including an inner metallic seal and an outer metallic seal arranged with one of the split metallic seals being a lower metallic seal overlapping (or rising from) the lower metallization layers and another of the split metallic seals being an upper metallic seal overlapping (or hanging from) the upper metallization layers. In accordance with embodiments, the inner metallic seal and the outer metallic seal can both be formed in the same metallization layer (or multiple metallization layers) of the plurality of metallization layers. A through seal interconnect (e.g. inter-die wiring or intra-die wiring) can weave between the inner and outer metallic seals, and extend from the first FEOL die area and into a scribe region laterally outside of the outer metallic seal. The scribe region can be diced, or alternatively unused (dummy) such that the through seal interconnect can connect to an adjacent inter-die area or intra-die area, and optionally through a corresponding split metallic seal structure of the adjacent inter-die area or intra-die area. In another aspect, embodiments describe a sealed box structure which allows for the formation of die-to-die routing (inter-die or intra-die) while retaining full metallic seal (ring) structures without requiring openings or gaps to accommodate the die-to-die wiring. Such a sealed box structure may incorporate die-to-die routing over a passivated test pad layer, between the conventional top metallization layer in the BEOL build-up structure and the chip contact pads (e.g. under bump metallurgy, UBM, pads). This can allow die-to-die routing fabrication in a wafer fab, while scribing is performed after test. In an embodiment, a chip structure includes a semiconductor substrate and a first FEOL die area of a first die patterned into the semiconductor substrate. A BEOL build-up structure is formed over the first FEOL die area, and includes a plurality of metallization layers including a lower metallization layer and an upper metallization layer spanning over the first FEOL die area. The BEOL build-up structure additionally includes a metallic seal extending from the lower metallization layer to the upper metallization layer, a passivation layer over the upper metallization layer and directly on the metallic seal, an opening in the passivation layer, a die-to-die routing filling the opening and extending into a scribe region laterally outside of the metallic seal, a passivation layer over the die-to-die routing, and a plurality of chip contact pads over the passivation layer. In this manner the semiconductor substrate, metallic seal, and passivation layer form a sealed box, over which the die-to-die routing is formed. In another aspect, embodiments describe back side die-to-die routing that leverages through silicon vias (TSVs) to the FEOL process layers or lower level BEOL metallization layers. As such, die-to-die routing can be fabricated while keeping the metallic seals intact in the front-side, and without comprising FEOL layers and lower level BEOL dielectric layers that may have low-k materials that can be particularly susceptible to moisture penetration. In an embodiment, a chip structure includes a semiconductor substrate and a first FEOL die area of a first die patterned into the semiconductor substrate. A BEOL build-up structure is formed over the first FEOL die area, and includes a plurality of metallization layers including a lower metallization layer and an upper metallization layer spanning over the first device region, a metallic seal extending from the lower metallization layer to the upper metallization layer. a passivation layer over the upper metallization layer and directly on the metallic seal, and a die-to-die routing extending from the first device region, through the semiconductor substrate to a back side of the semiconductor substrate, and over into a scribe region laterally outside of the metallic seal. In yet another aspect, embodiments describe chip structures in which electromagnetic field communication structures, such as to facilitate capacitive, magnetic or photonic coupling, are integrated to communicate across adjacent seal structures without physical wiring. For example, coils or capacitors can be placed on opposite sides of a metallic seal, or over and under a passivation layer to facilitate communication across a sealed structure. As an option, repeater structures to receive and amplify and then re-transmit signals may be placed in the scribe area. In various embodiments, description is made with reference to figures. However, certain embodiments may be practiced without one or more of these specific details, or in combination with other known methods and configurations. In the following description, numerous specific details are set forth, such as specific configurations, dimensions and processes, etc., in order to provide a thorough understanding of the embodiments. In other instances, well-known semiconductor processes and manufacturing techniques have not been described in particular detail in order to not unnecessarily obscure the embodiments. Reference throughout this specification to “one embodiment” means that a particular feature, structure, configuration, or characteristic described in connection with the embodiment is included in at least one embodiment. Thus, the appearances of the phrase “in one embodiment” in various places throughout this specification are not necessarily referring to the same embodiment. Furthermore, the particular features, structures, configurations, or characteristics may be combined in any suitable manner in one or more embodiments. The terms “above”, “over”, “to”, “between”, “spanning” and “on” as used herein may refer to a relative position of one layer with respect to other layers. One layer “above”, “over”, “spanning” or “on” another layer or in “contact” with another layer may be directly in contact with the other layer or may have one or more intervening layers. One layer “between” layers may be directly in contact with the layers or may have one or more intervening layers. Referring now toFIG.1Aa schematic top view layout plan illustration is provided of a wafer102(e.g. silicon) including an array of dies104in which the adjacent FEOL die areas110of the dies104can be interconnected with die-to-die routing130, along with appropriate signal return paths. The separate FEOL die areas110(also referred to herein more generically as die areas110) and dies104in accordance with embodiments described herein (not limited toFIG.1A) may include distinct circuit blocks from one another. Each die area110may represent a complete system, or sub-system. Adjacent die areas110may perform the same or different function. In an embodiment, die area110interconnected with die-to-die routing can include a digital die area tied to a die area with another function, such as analog, wireless (e.g. radio frequency, RF) or wireless input/output, by way of non-limiting examples. The tied die areas110may be formed using the same processing nodes, whether or not having the same or different functions. Whether each die104and die area110includes a complete system, or are tied subsystems, the die-to-die routing130may be inter-die routing (different systems) or intra-die routing (different, or same subsystems within the same system). For example, intra die-to-die routing may connect different subsystems within a system on chip, SOC, where inter die-to-die routing can connect different SOCs, though this is illustrative, and embodiments are not limited to SOCs. Thus, while the following description and embodiments are made primary with regard to inter-die connections, the embodiments and descriptions of die areas110are equally applicable for intra-die connections, between die areas110of distinct circuit blocks within the same die104. The die areas110and dies104in accordance with embodiments are not limited to specific systems or subsystems of an SOC. Harvesting may include dicing any number of units required, or even having more units than required and accepting one or more units that fail. Additionally, redundancy can be added by including one or more extra units (dies), or complete sub-systems. In event of a unit failure, a good unit can be swapped. Redundancy can be at the time of manufacture, or swappable in the field. Various applications include harvesting of engines such as graphics processing units (GPU), central processing units (CPU), signal processing engines, a neural engines (e.g. neural network processing engine), artificial intelligence (AI) engines, networks, caches, etc., memory device such as static random-access memory (SRAM), magnetic random-access memory (MRAM), nonvolatile random-access memory (NVRAM), dynamic random-access memory (DRAM), NAND, and cache memory, other components such as a capacitor, inductor, resistor, power management integrated circuit (IC), amongst others including interfacing bars for logic or memory expansion, and interposer substrates. Array harvesting may also be extended to other applications including solar, display, probe pin arrays for automated test equipment (ATE), field programmable gate arrays (FPGA), etc. In accordance with embodiments, any or all FEOL die area edges can be configured to include die-to-die routing130. In many embodiments, a portion of the this die-to-die routing130may be referred to as a through seal interconnect. Furthermore, each FEOL die area110may be surrounded by metallic seal122(e.g. metallic seal ring), which may be a split metallic seal structure or full seal structure depending upon the embodiment. As shown inFIG.1A, dicing or scribe lanes can be located anywhere to accommodate yield (e.g. bad dies) or demand (e.g. need for larger die sets100). This is illustrated by dies sets100including one die (1X), two dies (2X), four dies (4X), etc. FIG.1Bis a schematic top view layout plan illustration of a wafer including an array of pre-arranged die sets100in accordance with an embodiment in which the die sets100are interconnected with die-to-die routing130. While the array of FEOL die areas110illustrated inFIG.1Acan allow for complete flexibility with scribing any combination of interconnected die sets, embodiments such as that illustrated inFIG.1Balso contemplate the arrangement of specific die sets connected with die-to-die routing. In such an embodiment, full metallic seal rings122B can be provided around the die sets100, while metallic seals122A, split metallic seal structures or full seal structures depending upon the embodiment, are provided between adjacent FEOL die areas110within the die sets100. Such a configuration may allow for additional metallic sealing of the scribed die sets, while still allowing for flexibility of scribing through the die-to-die routing130between adjacent FEOL die areas to facilitate improved wafer utilization. For example, such scribing may be performed to harvest a single die104, remove a bad die104, or harvest an irregular shape or custom number of dies104in a die set100. As a contrast withFIG.1A, which may be across multiple reticles, the embodiment illustrated inFIG.1Bmay be within a reticle suitable for smaller systems. Staying within reticle may allow simpler stitching interconnection. Dicing can also be through the die-to-die routing130between die areas. Referring now toFIG.2A, a schematic top view illustration is provided of a chip150including a die set and die-to-die routing130extending through a split metallic seal structure160in accordance with an embodiment. In the particular embodiments illustrated, the chip150includes a2X die set similar to that illustrated inFIG.1A, including metallic seals122, which can be split metallic seal structures160to accommodate the die-to-die routing. It is to be appreciated that this configuration is exemplary, and split metallic seal structures160can be included in a variety of configurations, including the various die sets ofFIGS.1A and1B, amongst other configurations. Accordingly, the illustration ofFIG.2Aand the following description are understood to be a particular implementation of the embodiments described herein, rather than limiting. For example, in the particular embodiment illustrated inFIG.2A, the split metallic seal structures160are only formed between adjacent die areas110that can accommodate die-to-die routing130. However, embodiments are not so limited, and split metallic seal structures160can be formed along any die area110side109. Furthermore, die-to-die routing130can be connected to any and all die area110sides109. FIG.2Bis a close-up cross-sectional side view illustration of the die-to-die routing130and split metallic seal structure160across section A-A in the die set ofFIG.2Ain accordance with an embodiment. As shown, the chip structure150includes a semiconductor substrate101(e.g. from wafer102). As shown, a one or more FEOL die areas110can be patterned into the semiconductor substrate, and a BEOL build-up structure120formed over the one or more FEOL die areas110. The FEOL die areas110can include input/output regions114, core regions112, etc. Wrapper regions may optionally be located adjacent to the core regions112, including supporting logic, test, clocking, debug etc. for the core circuits of the core regions112. The wrapper regions may additionally interface the core circuits to the input/output circuits of the input/output regions114to support the die-to-die routing130. Still referring toFIG.2B, the BEOL build-up structure120includes a plurality of metallization layers134, which may include lower metallization layers (Mlow), mid-level metallization layers (Mmid) and upper metallization layers (Mhigh) spanning over the FEOL die areas110. Each of the lower, mid-level, and upper metallization layers may each include one or more (e.g several) metallization layers dictated by design requirements. In accordance with embodiments, the metallic seals122A may be split metallic seal structures160including an inner metallic seal164and an outer metallic seal162arranged with one of the inner metallic seal and the outer metallic seal being a lower metallic seal163overlapping the lower metallization layers (Mlow) and the other of the inner metallic seal and the outer metallic seal being an upper metallic seal165overlapping the upper metallization layers (Mhigh). As used herein, the terms “inner” and “outer” when made with reference to the inner and outer metallic seals are made with reference to the core regions112relative to the scribe regions125. Thus, the inner metallic seals164may be closer to the inner core regions112of a die than the outer metallic seals162, which may be closer to the chip edges or scribe regions125(whether scribed, or connected to an adjacent die area). The split metallic seal structures160can be distinguished from full metallic seal structures, which may generally extend from the lowest lower metallization layers (Mlow) to the uppermost upper metallization layers (Mhigh), forming a continuous wall. In some embodiments at least some of the lower metallization layers may be formed between low dielectric constant (low-k) dielectric layers136(e.g. carbon doped silicon oxide, fluorinated silicon oxide, etc.). The higher metallization layers134, such as the mid-level or upper metallization layers may optionally be formed between low-k dielectric layers or other dielectric layers138(e.g. silicon oxide, silicate glass, etc.). Low-k dielectric layers may be particularly susceptible to moisture ingress. Additional dielectric layers, metallization layers (including test pad layer, additional routing layers, etc.), and passivation layers illustrated elsewhere herein may be included in the structure illustrated inFIG.2Babove the upper metallization layers. A top passivation layer182(e.g. nitride, polyimide, etc.) is however illustrated, with top chip contact pads141. In accordance with embodiments a through seal interconnect169extends from the first FEOL die area110, through the split metallic seal structure160, and into a scribe region125laterally outside of the outer metallic seal162. The through seal interconnects169may be at least a portion of the die-to-die routing130formed with vias132wiring layers of the metallization layers134. If the die areas110are scribed through the scribe region125, then the scribe line129can go through terminal ends of the through seal interconnects169/die-to-die routing130. If the die areas110are not scribed then the through seal interconnects169can pass through the split metallic seal structures160for both adjacent dies. In accordance with embodiments, portions of the outer metallic seal162(e.g. lower metallic seal163) and the inner metallic seal164(e.g. upper metallic seal165) are both formed in at least one same metallization layer134. This may facilitate blocking a clear (lateral) line of sight and protect against the formation of defects such as cracking or delamination, moisture ingress or for diffusion should dicing be performed through the scribe region125. Referring now again toFIG.2A, the split metallic seal structure160can be coupled to one or more charge sources or sinks145to control potential of at least one of the inner metallic seal164and the outer metallic seal162. The charge sources or sinks may be the same or different sources or sinks, such as low voltage source (Vss) inclusive of ground or lower operating voltage source, or other charge source such as power (e.g., high voltage, Vdd) or reference voltage, or even floating (high impedance connections, or alternating current coupled or both). The charge sources or sinks145may be connected to the split metallic seal structure160with charge source or sink routing149connected to, or within, the semiconductor substrate101, or interconnected to the split metallic seal structure160through one or more metallization layers or vias within the BEOL build-up structure120. FIG.2Cis a close-up cross-sectional side view illustration of the plurality of metallization layers forming the split metallic seal structure in the die set ofFIG.2Ain accordance with an embodiment. As shown, both the inner metallic seals164and outer metallic seals162can be formed of multiple via132walls and wiring layers135(e.g. trenches) of the metallization layers134. In a dual damascene structure this may include continuous filled trenches (wiring layers135) and vias132. Similarly, the schematic via132illustrations ofFIG.2Bfor the die-to-die routing130may include stacked vias132and wiring layers135. As shown inFIGS.2A-2C, the split metallic seal structures160in accordance with embodiments may allow for a continuous die-to-die routing130between adjacent die areas110. Additionally, while die-to-die routing130may navigate through multiple metallization layers134, the formation of a blockage to a lateral line of sight can provide physical, chemical, and electrical protection to the die areas110. In the particular embodiments illustrated inFIGS.2A-2Cthe outer metallic seal162is outside (exterior to) the input/output region114and the inner metallic seal164is between the input/output region114and the core region112including the core logic circuits of the die. For example, the inner metallic seal164may be located within what is traditionally termed a keep out zone (KOZ) between a core region112including core logic and outer input/output region114. In this manner the full sealing potential of the split metallic seal structures160is provided for the core region112, while at the same time providing access of the die-to-die routing130(and hence through seal interconnects169) to the input/output region114and a continuous die-to-die routing130. Additional modifications are possible. For example, referring again toFIG.2B, a decoupling capacitor119can be placed in the scribe region125for use when adjacent die areas110are to be connected, and scribed out when adjacent die areas110will not be connected. This can reduce demand on the dies and core regions112, for example with SOC, and additionally reduce wiring length. Referring again toFIG.2C, in accordance with embodiments dicing may be performed through the scribe regions125when harvesting chips150including one or more die areas110. As shown, a terminal end137of the through seal interconnect (die-to-die routing130) may result at the chip edge257. Referring now toFIGS.3A-3B,FIG.3Ais a cross-sectional side view illustration of a split metallic seal structure160coupled with a metal plane140of a charge source or sink routing149in accordance with an embodiment, andFIG.3Bis a close-cup schematic top view illustration of the metal plane140density of the charge source or sink routing149across area B-B ofFIG.3Ain accordance with an embodiment. The charge source or sink may be a variety of sources such as low voltage source (Vss) inclusive of ground or lower operating voltage source, or other charge source such as power (e.g., high voltage, Vdd) or reference voltage, or even floating. In an exemplary embodiment a charge source or sink routing149return can be shorted (e.g. grounded for a Vss sink) to the outer metallic seal162of the split metallic seal structure160. The inner metallic seal164can similarly be connected to a charge source or sink routing. This can potentially control cross-talk, while also providing a sealing function. Similar to the die-to-die routing130, the metal plane140can be formed in a metallization layer144(which can be a same layer as metallization layer134) and vias142(which can be similar to vias132). In an embodiment, the metallization layer144, rather than including conventional interconnect lines can include a metal plane140.FIG.3Billustrates interconnect lines of die-to-die routing130superimposed over a metal plane140of the (e.g. Vss) sealing structure. Thus, the metal plane140can be formed directly on top of the outer metallic seal162, which can form a sealing wall, while the metal plane140forms a sealing roof, or ceiling. Additionally, the through seal interconnects169(e.g. die-to-die routing) includes wiring that spans directly over the metal plane140. Still referring toFIG.3Bdensity of the metal plane140can be varied by area location. For example, the metal plane140may have a lower metal density in the scribe region125than in the die area110. For example, this may be achieved by patterned openings through the metallization layer144(seeFIG.6A) to reduce metal density. Thus, more openings may correspond to a reduced density, with a reduced density facilitating dicing. In an embodiment, the metal plane140is denser laterally inside the outer metallic seal162than laterally outside of the outer metallic seal162. The metal density may be graded. Referring now toFIGS.3C-3E,FIG.3Cillustrates a high metal density with an unpatterned metal plane140in area3C ofFIG.3B.FIG.3Dillustrates a plurality of openings146in the metal plane140in area3D ofFIG.3B, which reduces the overall metal density. The openings146may be a variety of shapes, and may accommodate jogs described elsewhere herein.FIG.3Eillustrates a plurality of lines147formed of the metal plane140in area3E ofFIG.3B. For example, the metal lines147may have the same or similar density as the die-to-die routing (through seal interconnects169). These are merely exemplary illustrations which show a possible graded metal density, and it is understood a variety of alternative arrangements are envisioned. It is to be appreciated that various illustrations herein, such asFIG.3A, are partial chip structure illustrations, and that additional dielectric layers, metallization layers (including test pad layer, additional routing layers, etc.), and passivation layers illustrated elsewhere herein may be included above the upper metallization layers. Thus, it is to be appreciated that additional structures may be included and that the illustrations provided are instead focused on specific structures in order to not unnecessarily obscure the embodiments. Up until this point, and in particular the close-up schematic cross-sectional side view illustrations inFIGS.2B and3Ahave illustrated the inner metallic seal164being between the input output regions144and core regions112(e.g. main logic) of the die areas110(i.e. within the keep out zone (KOZ)). Additionally, the outer metallic seals162can be over the die areas110, within the scribe regions125, or between the die areas110and scribe regions125. Such arrangements can help shield the core region, while allowing for navigation of the through seal interconnects. In accordance with embodiments, buffers can be located in various locations to facilitate the passage of signals between the core regions112, or adjacent wrapper regions113, and the input/output regions114. Wrapper regions may be supporting logic regions that interface the core region112circuits to the input/output region114circuits, for example for die-to-die communication. In addition to logic, they may support test, clocking, debug etc. In some configurations, it may be desirable to have no or minimum wrapper regions and the continue core region fabric. Thus, in the following embodiments, wrapper region and core region are described as being either separate or same regions. Referring now toFIGS.4A-4Bschematic cross-sections side view and top view illustrations are provided of a die-to-die routing including a buffer115in an I/O region114in accordance with an embodiment. As shown, the I/O region114can be electrically connected with the core region112or wrapper region113through one or more metallization layers134, while a buffer115is located in the I/O region114, for example to provide driving function, isolation function (e.g. between the core region112and I/O region114when scribed) and optionally electrostatic discharge (ESD) or electro-overstress (EOS) isolation should dicing be performed through the scribe region125. Such a configuration may require area within the input/output region114of the die. It is to be appreciated that the exemplary embodiment described and illustrated inFIGS.4A-4Bincludes signal routing and metal plane140ofFIG.3A-3B. The metal plane140may be connected to charge source or sinks, such as low voltage source (Vss) inclusive of ground or lower operating voltage source, or other charge source or sink such as power (e.g., high voltage, Vdd) or reference voltage, or even floating (high impedance connections, or alternating current coupled or both). It is to be appreciated that this is exemplary, and while the embodiments are combinable, it is not required. Thus, in the following description, illustration of various embodiments within the same figures is meant for convenience, and to not distract from the various illustrated structures being described. Thus, illustration of various embodiments within the same figures, while demonstrating compatibility of the various embodiments, is not to be interpreted as being required features to all embodiments. Yet another arrangement for buffer location is illustrated inFIGS.5A-5Bwhere a buffer115is instead located within the core region112or adjacent wrapper region113instead of the I/O region114. Such as configuration may allow for reduced die-to-die routing130distance, and area. More specifically, less area is used for the I/O region114compared to configurations where buffers are located in the I/O regions114. Additional embodiments are illustrated inFIGS.6A-6Cwhere a buffer115is instead located within the scribe region125. Such arrangements can take advantage of this additional area, where it is only used when adjacent dies are unscribed (e.g. joined), and connected with die-to-die routing130.FIG.6Ais substantially similar toFIG.5Awith a difference being additional vias132(or more specifically stacked vias132and metallization layers134or trenches as shown inFIG.2C) for the die-to-die routing130to connect with the buffer115outside of the outer metallic seal162within the scribe region125. Additionally, de-coupling capacitors supporting the power network for the buffer, and other circuits, may also be placed in the scribe region125. These additional vias132may extend through openings146in the metal plane140. Such a configuration may allow for both a reduced die-to-die routing130distance by taking advantage of a “free” area. As shown inFIGS.6B-6C, this can also allow the transmission signals to be send from near core regions112or wrapper regions113as shown inFIG.6Bor “deep” core (circuit) regions112or wrapper regions113within an interior of the dies or the core regions112further away. These can reduce latency and also provide on-chip fabric extensions. Referring now toFIGS.7A-7Eadditional die-to-die routing130modifications can be incorporated into the embodiments described herein. In particular, horizontal or vertical jogs131can be included, which may provide additional protection to crack propagation, ion diffusion or delamination.FIG.7Bis a schematic top view illustration of a horizontal jog within a same metallization layer134in accordance with an embodiment. As shown the jog131can be a non-straight line interconnect within a same metallization layer134(Mn+1). By comparison,FIG.7Cis a schematic side view illustration of die-to-die routing130including vertical jog131in which the routing is connected between multiple metallization layers144,134(Mn, Mn+1) with vias133.FIG.7Dis a schematic top view illustration of die-to-die routing130including a hybrid vertical and horizontal jog131. Thus,FIG.7Dcombines features ofFIGS.7B-7C, where a non-straight line interconnect is formed within multiple metallization layers144,134(Mn, Mn+1) to form the horizontal jog portion, where vias133connect the multiple metallization layers144,134(Mn, Mn1) to form the vertical jog portion.FIG.7Eis a schematic cross-sectional side view illustration of a die-to-die routing130including a vertical jog131in accordance with an embodiment. In the particular embodiment illustrated the vertical jog131dips into a lower metallization layer144used for the metal plane140of the charge source or sink sealing structure previously described. It is to be appreciated that such a configuration is exemplary, and the vertical jogs131can be formed in a variety of metallization layers134, including those sharing other die-to-die routing130lines. While the above descriptions of horizontal and vertical jogs131were made and illustrated separately, it is to be appreciated that embodiments may combine both horizontal and vertical jogs131within the same die-to-die routing130lines, or separate die-to-die routing130lines in the same chip structure. Horizontal jogs131in particular may mitigate straight crack propagation, and may be particularly applicable in lower density die-to-die routing130architecture where ample space is available. Vertical jogs131in particular may staple layers together to mitigate delamination and microcrack propagation. Combinations of horizontal and vertical jogs131in particular may be implemented by lowering the topmost metallization layer/via for the outer metallic seal162to accommodate routing of the vertical jogs131. Combinations of horizontal and vertical jogs131can also be used for rotating the die-to-die routing130lines. For example, this may resemble a bundled cable, where the wires of the die-to-die routing130are twisted. Such a configuration may average cross-talk among the wires of the die-to-die routing130. Additional configurations for split metallic seal structures160are envisioned in accordance with embodiments, for example to elongate diffusion lengths for moisture and ions or provide additional mechanical protection. In the embodiment illustrated inFIG.8, the split metallic seal structure160includes an additional second inner metallic seal166, which can be a second lower metallic seal163. Compared to the embodiments described, such a configuration may increase distances between adjacent die areas110, though can also allow for the input/output region114to be placed closer to the core region112since the inner metallic seal164is not located between the input/output region114and the core region112. The outer metallic seal162can now be considered an additional, or surplus, metallic seal structure which can be located in the scribe region125to potentially reduce distance between adjacent die areas110if the outer metallic seal162can be located in a typical scribe region width. Furthermore, the additional second inner metallic seal166can provide an additional barrier to line of sight, providing mechanical protection and further elongating a diffusion length. Likewise, more upper metallic seals and lower metallic seals can be added to meet reliability goals. An additional variation is illustrated inFIG.9, in which the inner metallic seal164is a partial metallic seal including both a partial upper metallic seal164A and partial lower metallic seal164B and vertical opening161therebetween to accommodate passage of the die-to-die routing130. Thus far embodiments have been described in which the die-to-die routing130is in the form of through seal interconnects169extending through split metallic seal structures160. Embodiments described herein also include additional sealed box structures. Generally, this may be accomplished at the expense of adding additional processing layers, while removing reliability concerns of partial/split metallic seal structures.FIG.10is a schematic cross-sectional side view illustration of a chip150including sealed box structures202for adjacent die areas110with die-to-die routing130landing on a passivated test pad layer175in accordance with an embodiment.FIG.11is a schematic cross-sectional side view illustration of a chip150including sealed box structures202for adjacent die areas110with die-to-die routing130landing on an upper metallization layer (Mhigh) in accordance with an embodiment. Generally, the sealed box structure202passivates the active area of the die to block moisture ingress, ion diffusion, oxidation etc. and protect the sensitive layers from environment. Typical materials include metal layers and passivation layers, such as inorganics (e.g. silicon, nitrides, carbides, oxides) as well as some polymers (e.g. polymers for more tolerant devices or applications). Referring to bothFIGS.10-11, the chip structure150may include a semiconductor substrate101, and FEOL die areas110patterned into the semiconductor substrate101. Illustrated inFIG.10are devices111(e.g. transistors) of the device areas110. A BEOL build-up structure120is formed over the semiconductor substrate101including a plurality of metallization layers134as previously described. Additionally, metallic seals122(e.g. full metallic seals) are formed extending from the lower metallization layers (Mlow) to the upper metallization layers (Mhigh). A passivation layer170is located over the upper metallization layer (Mhigh) and directly one the metallic seal122. In this manner, the metallic seal122provides side sealing, while the passivation layer176provides top sealing for the sealed box structures202. As shown, openings172can be formed in the passivation layer176and die-to-die routing130fills the openings172and extends into a scribe region125laterally outside of the metallic seal122. In this case the metal-filled openings172(or vias) also contributed to the sealed box structures202. Referring now specifically toFIG.10, a lower passivation layer170may be formed over the upper metallization layers (Mhigh) and patterned to form openings178exposing the upper metallization layer (Mhigh). A test pad layer175is formed over the lower passivation layer170and within the openings178and patterned to form metal pads174. In an embodiment, the test pad layer175and metal pads174are formed of aluminum, while the metallization layers134are formed of copper. In such a configuration, some metal pads174can be reserved for testing, while others are used for additional interconnection, including die-to-die routing130. As illustrated, the passivation layer176is formed over the test pad layer175, patterned to form openings172exposing the metal pads174, and the die-to die routing130is formed filling the openings172and extending into the scribe region125. Formation of die-to-die routing130may include dielectric layers180and metallization layers are previously described with dielectric layers138and metallization layers134. A top passivation layer182can then be formed over the die-to-die routing130and dielectric layers180, patterned to form openings and chip contact pads141located over the top passivation layer182. A final passivation layer184can then be formed over the chip contact pads141and patterned to expose the chip contact pads141. Rather than contacting a test pad layer175as inFIG.10, in the embodiment illustrated inFIG.11die-to-die routing130can build directly on the upper metallization layer (Mhigh). As shown, an optional lower passivation layer170and passivation layer176can be formed over the upper metallization layer (Mhigh) and patterned to form openings178,172, and die-to-die routing130formed filling the openings178,172(which can be one or more vias). Formation of die-to-die routing130may include dielectric layers180and metallization layers are previously described with dielectric layers138and metallization layers134. A top passivation layer182can then be formed over the die-to-die routing130and dielectric layers180, patterned to form openings and chip contact pads141located over the top passivation layer182. A final passivation layer184can then be formed over the chip contact pads141and patterned to expose the chip contact pads141. Similar to previously described embodiments, dicing may optionally be performed though the scribe region125, resulting in terminal ends of the die-to-die routing130along chip150edges. Where dicing is not performed between die areas110the die-to-die routing130may connect adjacent die areas110of adjacent dies104. Thus far embodiments have been described in which the die-to-die routing130can be formed through metallic seal structures, or over metallic seal structures. Referring now toFIGS.12-13additional embodiments are described in which die-to-die routing130can be realized on a back side of the semiconductor substrate101facilitating through silicon vias (TSV) and backside routing layers210(which can also be generally referred to as backside metallization). Similar to previous descriptions, the chip structures150include a semiconductor substrate101, FEOL die areas110patterned into the semiconductor substrate, and a BEOL build-up structure120including a plurality of metallization layers134including a lower metallization layer (Mlow) and an upper metallization layer (Mhigh) spanning over the first FEOL die area110(illustrated as devices111). Metallic seals122extend from the lower metallization layer to the upper metallization layer. A passivation layer may be formed over the upper metallization layer and directly on the metallic seals122to preserve a sealed box structure. As illustrated in bothFIGS.12-13a die-to-die routing130can extend from the first FEOL die area110, through the semiconductor substrate101to a back side118of the semiconductor substrate101, and over into a scribe region125laterally outside of the metallic seal122. The die-to-die routing130may be formed with vertical interconnects220and a backside routing layer210. Vertical interconnects220may include through vias (e.g. TSVs) through the semiconductor substrate101(e.g. silicon). The vertical interconnects can further extend to metallization layers in the BEOL build-up structure120. These may be the same vias (e.g. TSVs) or additional vias (e.g. vias132) from the BEOL build-up structure120. The backside routing layer210may be formed using thin film processing techniques or conventional BEOL build-up structure techniques including damascene structures. In an embodiment, the backside routing layer210includes metal wiring layers212, dielectric layers214and vias216extending through the dielectric layers. In the particular embodiment illustrated inFIG.12the vertical interconnects220may include nano-vias which can be built right into the FEOL process in the semiconductor substrate101. As shown, the interconnects with nano via TSVs may connect to the devices111, and may extend partially through or completely through to the back side118of the semiconductor substrate101. Furthermore, the nano-vias may be high densities (tens or hundreds of nm in pitch), and the semiconductor substrate101may be thinned to less than a 500 nm thickness in some embodiments. The nano-vias may optionally be connected to vias within the BEOL build-up structure120to connect to a metallization layer within the BEOL build-up structure120, such as to a lower metallization layer134(Mlow). The vertical interconnects220may be connected to any metallization layer within the BEOL build-up structure. In this manner, the vertical interconnects220of the die-to-die routing130can extend from a metallization layer within the BEOL build-up structure and through the FEOL die area110to a back side118of the semiconductor substrate101where the die-to-die routing130can be completed. In the particular embodiment illustrated inFIG.13the vertical interconnects220may include micro-vias which can extend through a thicker semiconductor substrate101, such as several microns thick. Additionally, micro-vias may have a pitch on the order of microns. Still referring toFIG.13, the micro-via TSVs of the vertical interconnects220may optionally be connected to vias (e.g. vias132) within the BEOL build-up structure120to connect to a metallization layer within the BEOL build-up structure120, such as to a mid-level or upper metallization layer134(Mhigh). The vertical interconnects220may be connected to any metallization layer within the BEOL build-up structure. In this manner, the vertical interconnects220of the die-to-die routing130can extend from a metallization layer within the BEOL build-up structure and through the FEOL die area110to a back side118of the semiconductor substrate101where the die-to-die routing130can be completed. In both cases using backside routing layer210to complete the die-to-die routing130allows for connections to be made without compromising the metallic seals122, and particularly the low-k dielectrics that may be particularly susceptible to moisture penetration. Additionally, fine wires may be available on the back side118of the semiconductor substrate, allowing for high wiring density. Additionally, the back side wiring may be used in addition to routing on the front side of the semiconductor substrate101for additional bandwidth. Similar to previously described embodiments, dicing may optionally be performed though the scribe region125, resulting in terminal ends of the die-to-die routing130along chip150edges. Where dicing is not performed between die areas110the die-to-die routing130may connect adjacent die areas110of adjacent dies104. Thus far embodiments have been described in which physical die-to-die routing130structures can be formed through metallic seal structures, over metallic seal structures, or behind the metallic seal structures. Embodiments also describe chip structures in which electromagnetic field communication structures can be used for wireless die-to-die communication. For example, coils or capacitors (or other electromagnetic structure like coupled lines, waveguides, etc.) can be used to facilitate coupling across a sealing structure, such as the dielectric passivation layer (or thinner metal layers) or the metallic seal structure. Referring now toFIGS.14A-14B,FIG.14Aschematic top view and cross-sectional side view illustrations are provided of a die-to-die routing130including electromagnetic field communication structures across a metallic seal122in accordance with an embodiment. For example, the electromagnetic field communication structures may function as transceivers240(Tx) and receivers242(Rx) across the metallic seals122. There may optionally be repeaters in the scribe region between the receivers242and transceivers240(e.g. where scribe line129is illustrated), that receive input from receivers242and retransmit on transceivers240. The repeaters may optionally include active elements. Referring toFIG.14B, similar to previously described embodiments, the chips150can include a semiconductor substrate101including device areas110and a BEOL build-up structure120. Metallic seals122may extend from lower metallization layers to upper metallization layers, and be capped with one or more lower passivation layers170or passivation layers176to form a sealed box structure202. In the embodiment illustrated inFIGS.14A-14B, the transceivers240and receivers242include coils243for magnetic coupling. Alternatively, the transceivers and receives can include capacitor plates for capacitive coupling. In an embodiment, the transceiver240is located over the die area110interior to the metallic seal122, while the receiver242is located within or adjacent the scribe region125exterior to the metallic seal, or vice versa. Additionally, metallization layer134wiring may be connected to the electromagnetic field communication structure (e.g. the transceiver or receiver) in the scribe region125. For capacitive coupled structures, the metallization layer134wiring may be a wire, whereas for magnetic coupled structures metallization layer134wiring may be a loop formed by two wires. Similar to previously described embodiments, dicing may optionally be performed though the scribe region125, resulting in terminal ends of the die-to-die routing130(metallization layer134) along chip150edges. Where dicing is not performed between die areas110the die-to-die routing130may connect adjacent die areas110of adjacent dies104. FIGS.15A-15Binclude schematic top view and cross-sectional side view illustrations of a die-to-die routing130including electromagnetic field communication structures across a passivation layer170in accordance with an embodiment. Thus, the electromagnetic field communication structures are formed over/under a passivation layer forming the sealed box structure202. Such a configuration can be well aligned with technology and provide strong coupling across the (dielectric passivation layer170, with less parasitics than when coupling across a metal seal structure. In the exemplary embodiment illustrated, the test pad layer175is used to form the top electromagnetic field communication structure (e.g. receiver242) while the top metallization layer (Mhigh) is used to form the bottom electromagnetic field communication structure (e.g. transceiver240), or vice versa. As shown, a metallization layer134may be formed between the lower passivation layer170and passivation layer176into the scribe region125. For capacitive coupled structures, the metallization layer134wiring may be a wire, whereas for magnetic coupled structures metallization layer134wiring may be a loop formed by two wires. Similar to previously described embodiments, dicing may optionally be performed though the scribe region125, resulting in terminal ends of the die-to-die routing130(metallization layer134) along chip150edges. Similarly, there may be repeater structures in the scribe region125(e.g. along metallization layer134between connected transceiver240and receiver242). Where dicing is not performed between die areas110the die-to-die routing130may connect adjacent die areas110of adjacent dies104. Likewise, similar toFIGS.14A-14B, while coils243are illustrated in the receiver242and transceiver240for magnetic coupling, the transceivers and receivers can alternatively include capacitor plates for capacitive coupling. In accordance with embodiments a chip150structure may include a semiconductor substrate101, a first front-end-of-the-line (FEOL) die area110of a first die patterned into the semiconductor substrate, and a back-end-of-the-line (BEOL) build-up structure120including a sealed box structure202including a metallic seal122and one or more passivation layers170over the metallic seal122to provide a barrier to environment. The chip150further includes a die-to-die routing130extending from the first FEOL die area110and into a scribe region outside of the sealed box structure, wherein the die-to-die routing additionally includes an electromagnetic field communication structure including a transceiver240and a receiver242to wirelessly communicate across the sealed box structure202. The transceiver240and receiver242may each include a coil243for magnetic coupling across the sealed box structure202. The transceiver240and receiver242may each include a capacitor for capacitive coupling across the sealed box structure202. In an embodiment, the transceiver and the receiver are located on laterally opposite sides of the metallic seal122. In an embodiment, transceiver and the receiver are vertically oriented on opposite sides of a first passivation layer170of the one or more passivation layers. In an embodiment, the chip150further includes a chip edge257in a scribe region125, and a terminal end137of the die-to-die routing at the chip edge257. In an embodiment, the die-to-die routing extends from a scribe region125to a second FEOL die area110of a second die patterned into the semiconductor substrate101. The electromagnetic field communication structures in accordance with embodiments can also include photonic waveguides. For example, photonic wafers and chips may also use the stitched die and harvesting techniques described herein. The wafers may be native photonic materials, or assembled (e.g. wafer, or chip on wafer bonded) with complementary metal oxide semiconductor (CMOS) and photonic wafers. It may be feasible that the photonic waveguides are of sufficient reliability (e.g. oxide, nitride construction) that they may be diced, without hazard. In such these may support planar (2D) solutions. In such a case, the sensitive circuits and photonics stays with a sealed box, such asFIGS.10-11where the critical elements are protected on all sides. Only the diced waveguide is exposed, but is immune because of its material set and construction, and the overall die stays safe. If the waveguide materials need reliability enhancements, or are known to be susceptible, the diced facet may be passivated, thereby providing the protection. An alternative to passivation, the effective distance to active or sensitive elements may be increased using tight meanders (tradeoff with optical loss). In addition, metallic seals122can be placed between meander paths, such that substantial metal walls exist as partial seal ring. In an embodiment, waveguides can also be incorporated with metallic seal structures. For example, the waveguides can meander through partial metallic seal structures within a same layer (e.g. ifFIGS.8-9instead were top view). In addition, a full metallic seal wall may be negotiated in the third dimension using optical vias, couplers, mirrors or additional waveguides, or photonic wire bonds. For example, such structures may be compatible with the sealed box structures described herein such asFIGS.10-11, with the waveguide optionally formed in an overlying passivation layer176,182or dielectric layer180. The sensitive elements (CMOS or photonic) are within a sealed box. A waveguide can couple one die to the other. The vertical photonic communication may be assisted using faceted mirrors, grating couplers, photonic vias. Communication to other die may be using waveguides, photonic wire bonds etc. Similar to the electromagnetic field communication structures using magnetic or capacitive coupling, the electromagnetic field communication structures including waveguides may include optical transceivers and optical receivers. Referring to previously describedFIG.14Asuch a transceiver240and receiver242can be located on opposite sides of the metallic seal122, or alternatively inside the metallic seals122of the corresponding adjacent die areas110(and thus communicate across two adjacent sealed box structures). Repeaters may optionally be located therebetween. In an embodiment, scribing between the two die areas110along scribe line129may proceed through the waveguide material, resulting in adjacent chips, one including a transceiver240and the other including the receiver242. Similarly, referring to previously describedFIG.15A, such a transceiver and receiver242can be located on opposite sides of the passivation layer170, or alternatively inside the metallic seals122of the corresponding adjacent die areas110(and thus communicate across two adjacent sealed box structures). Repeaters may optionally be located therebetween. In an embodiment, scribing between the two die areas110along scribe line129may proceed through the waveguide material, resulting in adjacent chips, one including a transceiver240and the other including the receiver242. The electromagnetic field communication structures in accordance with embodiments thus far have been described as being connected to waveguides, photonic wire bonds, metallization layers134of the BEOL build-up structure120, etc. Alternatively, at least one of the transceivers240or receivers242can be located in a chiplet (e.g. smaller silicon die that may be passive or active) to connect between adjacent die areas110or chips150. FIG.16is a schematic cross-sectional side view illustration of the die-to-die routing including a chiplet250with electromagnetic field communication structures connecting two adjacent die areas110in accordance with an embodiment. The electromagnetic coupling may be capacitive or inductive. As shown, the adjacent die areas110may be enclosed within respective sealed box structures202. In particular,FIG.16may be similar to that ofFIG.15B, where instead a chiplet including a transceiver240and receiver242are used to communicate with a corresponding receiver242and transceiver240within adjacent die areas110, formed in the same semiconductor substrate101. Bonding of the chiplet250may be achieved by fusion bonding, for example between two dielectric layers such as SiO2. Such a dielectric-dielectric fusion bonding process can be less expensive and less complex than hybrid bonding, and use finer pad pitch compared to solder bumping (e.g. micro bumps). Using thin dielectric between coupled structures with good alignment accuracy can keep signal levels high, mitigate cross-talk, and facilitate dense pad pitch. In the exemplary embodiment illustrated fusion bonding is performed between a dielectric layer252on the chiplet250and passivation layer184formed over the chip150. The chiplet250in accordance with embodiments may be a purely passive component including routing234, or may be active. Solder bumps230may optionally be placed on chip contact pads141. Solder bumps230may optionally be laterally adjacent the chiplet250. Alternatively, the chiplet250can be embedded within a routing layer. As shown, the chiplet may include routing234to complete the die-to-die routing. The chiplet250may be passive or active. Active chiplets can support repeaters. Where chiplet250is active, through silicon vias (TSVs) may be formed through the chiplet for back side251connection (e.g. for power). Alternatively, power can be capacitively or inductively coupled, and TSVs are not required. The chiplets250in accordance with embodiments may include electromagnetic field communication structures for connecting multiple chips150, where the individual chips150already include sealed box structures, or similar sealing structures. Thus, the electromagnetic filed communication structures can be extended to the package level without disrupting the sealing structures of the individual chips to be connected. FIG.17is a schematic cross-sectional side view illustration of the die-to-die routing including a chiplet250with electromagnetic field communication structures connecting two adjacent chips150in accordance with an embodiment. Chips150may be the same type of chips, or different type of chips. The chips150may be similar to any of the chips150described herein, and may include full metallic seal structures. As shown, a package200can include a two or more chips150embedded in an encapsulation material240, such as molding compound material or dielectric fill material. A package level passivation layer284can optionally be formed over the encapsulated chips250and the encapsulation material240. Package contact pads241and vias may be formed through the package level passivation layer284to contact the individual chips150. A chiplet250can be fusion (dielectric-dielectric) bonded to the package level passivation layer184as previously described with the passivation layer184. Alternatively, the chip250can be fusion bonded to the passivation layers184of the individual chips150. FIG.18is a schematic cross-sectional side view illustration of the die-to-die routing including a chiplet250embedded within a package level routing layer260, the chiplet250including electromagnetic field communication structures connecting two adjacent chips150in accordance with an embodiment.FIG.18is substantially similar toFIG.17with the addition of the package level routing layer260including metallization layers234(wiring layers), vias232and package contact pads241. In an alternatively embodiment, the chiplet250ofFIG.16could be embedded within a similar wiring layer260for chip150, effectively extending the BEOL build-up structure120. Summarizing, various methods for die-to-die connection have been described that use a combination of techniques, using FEOL, BEOL, through silicon vias, chiplets, and multiple types of electromagnetic structures (capacitive, magnetic, and optical/photonic) while maintaining reliability for diced parts. In utilizing the various aspects of the embodiments, it would become apparent to one skilled in the art that combinations or variations of the above embodiments are possible for forming seal structures that support efficient die-to-die routing. Although the embodiments have been described in language specific to structural features and/or methodological acts, it is to be understood that the appended claims are not necessarily limited to the specific features or acts described. The specific features and acts disclosed are instead to be understood as embodiments of the claims useful for illustration. | 60,643 |
11862482 | DETAILED DESCRIPTION The following disclosure provides many different embodiments, or examples, for implementing different features of the provided subject matter. Specific examples of components and arrangements are described below to simplify the present disclosure. These are, of course, merely examples and are not intended to be limiting. For example, the formation of a first feature over or on a second feature in the description that follows may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features may be formed between the first and second features, such that the first and second features may not be in direct contact. In addition, the present disclosure may repeat reference numerals and/or letters in the various examples. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed. Further, spatially relative terms, such as “beneath,” “below,” “lower,” “above,” “upper” and the like, may be used herein for ease of description to describe one element or feature's relationship to another element(s) or feature(s) as illustrated in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The apparatus may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein may likewise be interpreted accordingly. Various types of gasses may be introduced into a processing chamber of a bonding tool to reduce and/or prevent oxidation or other types of contamination prior to bonding a first semiconductor substrate and a second semiconductor substrate. The processing chamber may then be pumped down to a partial vacuum in preparation for bonding. Introduction of a gas into the processing chamber while the processing chamber is pressurized may result in a burst effect, in which the greater pressure of the gas relative to the pressure in the processing chamber causes the first semiconductor substrate to deform and prematurely touch or contact the second semiconductor substrate. This early or premature contact may occur between various portions of the first semiconductor substrate and various portions of the second semiconductor substrate. The early or premature contact may result in bonding uniformity issues across the first semiconductor substrate and the second semiconductor substrate, which can cause local area yield loss on the first semiconductor substrate and the second semiconductor substrate and/or malfunctions of devices on the first semiconductor substrate and the second semiconductor substrate. Some implementations described herein provide a bonding tool and methods of operation that may reduce, minimize, and/or prevent early or premature contact between semiconductor substrates that are to be bonded. In some implementations, the bonding tool includes a gas supply line that is configured to supply or provide various types of gasses to a processing chamber of the bonding tool. The gas supply line may extend directly between valves associated with one or more gas supply tanks and the processing chamber such that gas supply line is uninterrupted without any intervening valves or other types of structures that might otherwise cause a pressure buildup in the gas supply line between the processing chamber and the valves associated with the one or more gas supply tanks. In this way, the pressure in the gas supply line may be maintained at or near the pressure in the processing chamber so that gas provided to the processing chamber through the gas supply line does not cause a pressure imbalance in the processing chamber that might otherwise cause early or premature contact between semiconductor substrates that are to be bonded in the processing chamber. Accordingly, the gas supply line of the bonding tool described herein may increase bonding uniformity across semiconductor substrates that are to be bonded, may decrease local area yield loss on semiconductor substrates that are to be bonded, and/or may reduce malfunctions of devices on semiconductor substrates that are to be bonded. FIGS.1A and1Bare diagrams of an example bonding tool100described herein. The bonding tool100is a semiconductor processing tool that is capable of bonding two or more semiconductor substrates (e.g., two or more semiconductor wafers, two or more portions of a semiconductor device such as a photomask or a reticle, two or more semiconductor devices, two or more semiconductor substrates, among other examples) together. For example, the bonding tool100may include a eutectic bonding tool that is capable of forming a eutectic bond between two or more semiconductor substrates by heating the two or more semiconductor substrates to form a eutectic system between the materials of the two or more semiconductor substrates. As another example, the bonding tool100may include a fusion bonding tool, which may form a direct bond between two or more semiconductor substrates (e.g., without the use of additional intermediate layers between the two or more semiconductor substrates) by pre-bonding the two or more semiconductor substrates (e.g., at or near room temperature) and annealing the two or more semiconductor substrates to complete the direct bond. In some implementations, the bonding tool100bonds two or more semiconductor substrates using a combination of bonding techniques, which may be referred to as hybrid bonding. As shown inFIG.1A, the bonding tool100may include a processing chamber102in which two or more semiconductor substrates may be supported and bonded. The processing chamber102may include a sealed chamber that is configured to be heated to an elevated temperature and pumped down to a vacuum or a partial vacuum (e.g., in a range of approximately 0 millibar (mbar) to approximately 950 mbar). The processing chamber102may be configured to be hermetically sealed to minimize contaminant and humidity ingress and to maintain the internal environment within the processing chamber102at and/or within a particular temperature range and/or a particular pressure range. The processing chamber102may be connected with a gas supply system104, which may be configured to supply various types of processing gasses to the processing chamber102in support of semiconductor substrate bonding. The various types of gasses may be used to purge the processing chamber102of atmospheric gasses, contaminants, humidity, and/or other environmental conditions in the processing chamber102, and/or may be used to control the environment within the processing chamber102during a bonding operation to bond two or more semiconductor substrates. The processing chamber102may also be connected to a pump106, which may be configured to pressurize the processing chamber102by pumping gas out of the processing chamber102. The pump106may include a servo pump that is configured to maintain the pressure within the processing chamber102based on negative feedback, or may include another type of pump. The gas supply system104may include various components such as various types of valves, pipes, filters, and/or other types of plumbing fixtures. As shown inFIG.1A, the gas supply system104may include a plurality of gas supply tanks, such as a bonding gas supply tank108and a purge gas supply tank110. The bonding gas supply tank108may include a gas storage tank that is configured to store and supply a bonding gas that is to be used in a bonding operation performed by the bonding tool100. The bonding gas may include an inert gas such as argon (Ar), nitrogen (N2), and/or another inert gas. The purge gas supply tank110may include a gas storage tank that is configured to store a purge gas that is to be used to purge the processing chamber102of the bonding gas. The purge gas may include an inert gas, extra clean dry air, extreme extra clean dry air, and/or another type of gas. As further shown inFIG.1A, the gas supply system104may include a first valve112and a second valve114, among other valves. The first valve112may include a binary flow valve that is configured to selectively block and permit the flow of gas through the gas supply system104. In other words, the first valve112may include a two-position valve that is capable of being selectively configured in a first position to block the flow of gas through the gas supply system104to the processing chamber102or in a second position to permit the flow of gas through the gas supply system to the processing chamber102. The second valve114may include a variable valve or variable flow valve that is configured to regulate or modulate the flow of gas through the gas supply system104to the processing chamber102. For example, the second valve114may be configured to control (e.g., adjust, increase, decrease, modulate, and/or regulate) the flow rate of gas through the gas supply system104to the processing chamber102to maintain, in combination with the pump106, the pressure within the processing chamber102at a near-constant pressure within a particular pressure range or within a tolerance of a particular pressure setting. As further shown inFIG.1A, the gas supply system104may include a gas supply line116. The gas supply line116may include one or more pipes or tubes that are configured to supply and/or provide various types of gasses to the processing chamber102. The gas supply line116may be configured to maintain a pressure in the gas supply line116and/or to provide gas to the processing chamber102at a pressure that is approximately equal to (or within a 5% tolerance, a 10% tolerance, or another tolerance of) a bonding pressure in the processing chamber102. The bonding pressure in the processing chamber102may include a pressure at which semiconductor substrates are bonded in the processing chamber102by the bonding tool100. In some implementations, the bonding pressure may be in a range of approximately 0 mbar to approximately 5 mbar to enable precise control over the environment in the processing chamber102. Accordingly, the gas supply line116may be configured to maintain the pressure in the gas supply line116and/or to provide gas to the processing chamber102at a pressure that is in a range of approximately 0 mbar to approximately 5 mbar. However, other values for the pressure in the gas supply line116are within the scope of the present disclosure. This reduces, minimizes, and/or eliminates the likelihood that the pressure in the gas supply line116(and the pressure of gas provided to the processing chamber102through the gas supply line116) will cause deflection or deformation of a semiconductor substrate in the processing chamber102, which would otherwise cause early or premature contact or touching of the semiconductor substrate and another semiconductor substrate that are to be bonded. As further shown inFIG.1A, the gas supply line116may extend directly between the processing chamber102and the first valve112, and may extend directly between the processing chamber102and the second valve114. In particular, the pipes or tubes of the gas supply line116may extend between the processing chamber102and the valves112,114uninterrupted without any intervening valves or other types of structures that might otherwise cause a pressure buildup in the gas supply line116between the processing chamber102and the valves112,114. The uninterrupted piping of the gas supply line116reduces, minimizes, and/or eliminates the likelihood that the pressure in the gas supply line116will cause a large and sudden pressure differential in the processing chamber102, which might otherwise cause early or premature contact or touching of semiconductor substrates that are to be bonded in the processing chamber102. FIG.1Billustrates various details of the processing chamber102. As shown inFIG.1B, the processing chamber102may include an internal space118, a gas inlet120, and a gas outlet122. The gas inlet120may include a port, a nozzle, or another type of opening through which gas from the gas supply system104may be provided into the internal space118of the processing chamber102. In particular, the gas supply line116may be coupled to the gas inlet120to provide gas into the internal space118of the processing chamber102. The gas outlet122may include a port, a nozzle, or another type of opening through which gas may be purged or removed from the internal space118of the processing chamber102. In particular, the pump106may be coupled to the gas outlet122(e.g., directly or by other intervening plumbing fixtures) and may pump gas out of the internal space118of the processing chamber102through the gas outlet122. As further shown inFIG.1B, the processing chamber102may include various types of chucks in the internal space118, such as a thermal chuck124and a bonding chuck126, among other examples. The thermal chuck124may include a chuck that is configured to heat semiconductor substrates in the internal space118of the processing chamber102to an elevated temperature for eutectic bonding. The bonding chuck126may include a chuck that is configured to support and secure a semiconductor substrate that is to be bonded with another semiconductor substrate. The bonding chuck126may include a vacuum chuck or another type of chuck that is configured to minimize and/or prevent movement of a semiconductor substrate that is to be bonded with another semiconductor substrate. As further shown inFIG.1B, the processing chamber102may include a plurality of support members128. The plurality of support members128may be located on and/or around the bonding chuck126such that the plurality of support members128are configured to suspend a semiconductor substrate over a semiconductor substrate that is located on the bonding chuck126in preparation for bonding. The plurality of support members128may include flags, standoffs, and/or other types of support members. As indicated above,FIGS.1A and1Bare provided as an example. Other examples may differ from what is described with regard toFIGS.1A and1B. FIGS.2A-2Hare diagrams of an example implementation200described herein. The example implementation200may include an example process for bonding semiconductor substrates using the bonding tool100in a manner in which the likelihood of early or premature contact between the semiconductor substrates is minimized, as described herein. As shown inFIG.2A, a first semiconductor substrate202and a second semiconductor substrate204may be placed in the processing chamber102for bonding. In particular, the first semiconductor substrate202may be placed on the bonding chuck126in the internal space118, and the second semiconductor substrate204may be placed on the plurality of support members128such that the second semiconductor substrate204is suspended over the first semiconductor substrate202. In this way, the first semiconductor substrate202and the second semiconductor substrate204are spaced apart by a distance206. The distance206may be in a range of approximately 90 microns to approximately 110 microns to reduce the likelihood of shifting of the second semiconductor substrate204during bonding (which may cause bonding misalignment between the first semiconductor substrate202and the second semiconductor substrate204) and to reduce the likelihood of early or premature contact between the first semiconductor substrate202and the second semiconductor substrate204. However, other values for the distance206are within the scope of the present disclosure. In some implementations, the first semiconductor substrate202and the second semiconductor substrate204are manually positioned in the processing chamber102(e.g., by clean room personnel). In some implementations, the first semiconductor substrate202and the second semiconductor substrate204are automatically positioned in the processing chamber102by a transport device such as a robot arm or an equipment front end module (EFEM) tool, among other examples. As shown inFIG.2B, with the first semiconductor substrate202and the second semiconductor substrate204in the processing chamber102, the bonding tool100may use the gas supply system104to provide a bonding gas208to the processing chamber102to purge the environment in the processing chamber102. The bonding gas208may be used to purge the processing chamber102of contaminants (e.g., particles, dust, debris, and/or foreign objects), humidity, oxygen, and/or other environmental conditions. The bonding gas208may include an inert gas such as argon (Ar) or nitrogen (N2), among other examples. The bonding gas208may be supplied from the bonding gas supply tank108and through the first valve112. In particular, the bonding gas208may flow from the bonding gas supply tank108to the first valve112. The bonding tool100may actuate the first valve112to an open configuration in which the bonding gas208is permitted to flow through the first valve112. The bonding gas208may flow from the first valve112to the processing chamber102through the gas supply line116at a pressure (P1). The pressure (P1) may be a relatively high pressure to quickly purge the environment in the processing chamber102. As an example, the pressure (P1) may be approximately 1500 mbar or greater. In other examples, the pressure (P1) may be another pressure value. As shown inFIG.2C, the bonding tool100may actuate the first valve112to a closed configuration in which the bonding gas208is blocked from flowing through the first valve112(and thus, through the gas supply line116). The bonding tool100may activate the pump106to pump down the processing chamber102to a pressure (P2), which may correspond to the bonding pressure for bonding the first semiconductor substrate202and the second semiconductor substrate204. In some implementations, the bonding pressure is in a range of approximately 0 mbar to approximately 5 mbar to enable precise control of the environment in the processing chamber102, as described above. However, other values such as approximately 10 mbar, are within the scope of the present disclosure. As further shown inFIG.2C, the bonding tool100is enabled to maintain the pressure in the gas supply line116approximately equal to (or within a 5% tolerance, a 10% tolerance, or another tolerance of) the pressure in the processing chamber102(e.g., the bonding pressure, pressure (P2)). In particular, the pressure in the gas supply line116is capable of being maintained approximately equal to the pressure in the processing chamber102due to the gas supply line116extending directly between the processing chamber102and the valves112,114. In this way, there are no intervening valves, pumps, or other plumbing fixtures in the gas supply line116that might otherwise cause a residual amount of the high-pressure bonding gas208to remain in the gas supply line116after the first valve112is closed. As shown inFIG.2D, a gas mixture210may be purged from the internal space118of the processing chamber102through the gas outlet122. In particular, the gas mixture210may be purged during pressurization of the processing chamber102to the bonding pressure. The gas mixture210may include a combination of the environmental gas in the processing chamber102and the bonding gas208. As further shown inFIG.2D, the pump106may pump the internal space118down to the pressure (P2) such that the pressure between the first semiconductor substrate202and the second semiconductor substrate204, and the pressure in the internal space118of the processing chamber102, are approximately equal. As shown inFIG.2E, the bonding gas208may be provided to the processing chamber102to maintain the pressure in the processing chamber102approximately at the bonding pressure (e.g., the pressure (P2)). The bonding tool100may open the second valve114such that the bonding gas208is supplied from the bonding gas supply tank108through the second valve114. The bonding gas208may flow from the second valve114to the bonding chamber102through the gas supply line116. The pump106may continue pumping gas out of the processing chamber102as the bonding gas208is provided to the processing chamber102to control the environment within the processing chamber102(e.g., to control the humidity, the oxygen concentration, and/or the removal of contaminants). The pump106may continue pumping gas out of the processing chamber102, and the second valve114may regulate and/or modulate the flow of the bonding gas208through the gas supply line116to the processing chamber102, to maintain the pressure in the processing chamber102approximately at the bonding pressure (e.g., the pressure (P2)). As further shown inFIG.2E, the bonding gas208may be provided to the processing chamber at a pressure (P3). As indicated above, the gas supply line116may extend directly between the processing chamber102and the valves112,114without any intervening valves or other plumbing structures so as to prevent a build-up of residual bonding gas208in the gas supply line116after the processing chamber102is pressurized to the bonding pressure (e.g., the pressure (P2)). In this way, the pressure (P3) may be approximately equal to (or within a 5% tolerance, a 10% tolerance, or another tolerance of) the pressure (P2) in the processing chamber102, which may minimize the likelihood of and/or substantially prevent the first semiconductor substrate202and the second semiconductor substrate204touching prior to bonding the first semiconductor substrate202and the second semiconductor substrate204. Accordingly, the pressure (P3) of the bonding gas208provided to the processing chamber102may be in a range of approximately 0 mbar to approximately 5 mbar such that a pressure differential between the pressure (P2) in the processing chamber102and the pressure (P3) of the bonding gas208in the gas supply line116is in a range of approximately 0 mbar to approximately 5 mbar. However, other values for the pressure (P3) are within the scope of the present disclosure. As shown inFIG.2F, the bonding gas208may be provided into the internal space118of the processing chamber102through the gas inlet120of the processing chamber102. The bonding gas208may flow through the internal space118of the processing chamber102and out of the processing chamber102through the gas outlet122as the pump106pumps the bonding gas208through the processing chamber102. The pressure (P3) of the bonding gas208in the internal space118of the processing chamber102may be approximately equal to (or within a 5% tolerance, a 10% tolerance, or another tolerance of) the pressure (P2) in the internal space118between the first semiconductor substrate202and the second semiconductor substrate204to minimize deflection and/or deformation of the second semiconductor substrate204(which might otherwise cause early or premature contact between the first semiconductor substrate202and the second semiconductor substrate204). As shown inFIG.2G, with the pressure (P2) in the internal space118of the processing chamber102maintained approximately at the bonding pressure, the bonding tool100may actuate the plurality of support members128to cause the second semiconductor substrate204to drop onto the first semiconductor substrate202to bond the first semiconductor substrate202and the second semiconductor substrate204as part of a bonding operation. The bonding tool100may bond the first semiconductor substrate202and the second semiconductor substrate204as the pump106and the second valve114continue to cause the bonding gas208to flow through the internal space118of the processing chamber102. In some implementations, the bonding tool100increases (e.g., using the thermal chuck124) the temperature in the internal space118of the processing chamber102to perform a eutectic bonding operation to bond the first semiconductor substrate202and the second semiconductor substrate204. As shown inFIG.2H, after bonding of the first semiconductor substrate202and the second semiconductor substrate204, the bonding tool100may actuate the second valve114to a closed configuration to stop the flow of the bonding gas208to the processing chamber102. The bonding tool100may then actuate the first valve112to an open configuration to permit a purge gas212to flow from the purge gas supply tank110through the first valve112. The purge gas212may flow from the first valve112to the processing chamber102through the gas supply line116. The purge gas212may flow into the processing chamber102to purge the processing chamber102of the bonding gas208and to depressurize the processing chamber102back to atmospheric pressure. The bonded first semiconductor substrate202and second semiconductor substrate204may then be removed from the processing chamber102for further processing. As indicated above,FIGS.2A-2Hare provided as an example. Other examples may differ from what is described with regard toFIGS.2A-2H. FIG.3is a diagram of an example300of semiconductor substrate bonding performance described herein. The example300may illustrate examples of semiconductor substrate bonding performance for a semiconductor device310and a semiconductor device320. The semiconductor device310may be bonded by a bonding tool in which bonding gas is maintained in a gas supply line at a much greater pressure relative to the pressure in the processing chamber of the bonding tool. For example, the bonding gas may be maintained in the gas supply line at a pressure of approximately 1500 mbar or greater, whereas the pressure in the processing chamber may be approximately 100 mbar. However, other values for the pressure of the bonding gas are within the scope of the present disclosure. As shown inFIG.3, a bonding area312(or bonding interface) of the semiconductor device310may include one or more areas of imperfections314. The imperfections314may include discontinuities or voids that may result from early or premature contact between semiconductor substrates that were bonded to form the semiconductor device310. The semiconductor device320may be bonded by the bonding tool100described herein, in which the bonding gas208is maintained in the gas supply line116at a pressure (e.g., the pressure (P3)) that is approximately equal to the pressure (e.g., the pressure (P2)) in the processing chamber102of the bonding tool100. For example, the pressure of the bonding gas208in the gas supply line116, and the pressure in the processing chamber102may both be in a range of approximately 0 mbar to approximately 5 mbar. However, other values for the pressure in the gas supply line116are within the scope of the present disclosure. As shown inFIG.3, a bonding area322of the semiconductor device320may be absent (or near absent) of imperfections as a result of the approximately equal pressures in the processing chamber102and the gas supply line116substantially preventing early or premature contact between semiconductor substrates that were bonded to form the semiconductor device320. As indicated above,FIG.3is provided as an example. Other examples may differ from what is described with regard toFIG.3. FIG.4is a diagram of example components of a device400. In some implementations, the bonding tool100may include one or more devices400and/or one or more components of device400. As shown inFIG.4, device400may include a bus410, a processor420, a memory430, a storage component440, an input component450, an output component460, and a communication component470. Bus410includes a component that enables wired and/or wireless communication among the components of device400. Processor420includes a central processing unit, a graphics processing unit, a microprocessor, a controller, a microcontroller, a digital signal processor, a field-programmable gate array, an application-specific integrated circuit, and/or another type of processing component. Processor420is implemented in hardware, firmware, or a combination of hardware and software. In some implementations, processor420includes one or more processors capable of being programmed to perform a function. Memory430includes a random access memory, a read only memory, and/or another type of memory (e.g., a flash memory, a magnetic memory, and/or an optical memory). Storage component440stores information and/or software related to the operation of device400. For example, storage component440may include a hard disk drive, a magnetic disk drive, an optical disk drive, a solid state disk drive, a compact disc, a digital versatile disc, and/or another type of non-transitory computer-readable medium. Input component450enables device400to receive input, such as user input and/or sensed inputs. For example, input component450may include a touch screen, a keyboard, a keypad, a mouse, a button, a microphone, a switch, a sensor, a global positioning system component, an accelerometer, a gyroscope, and/or an actuator. Output component460enables device400to provide output, such as via a display, a speaker, and/or one or more light-emitting diodes. Communication component470enables device400to communicate with other devices, such as via a wired connection and/or a wireless connection. For example, communication component470may include a receiver, a transmitter, a transceiver, a modem, a network interface card, and/or an antenna. Device400may perform one or more processes described herein. For example, a non-transitory computer-readable medium (e.g., memory430and/or storage component440) may store a set of instructions (e.g., one or more instructions, code, software code, and/or program code) for execution by processor420. Processor420may execute the set of instructions to perform one or more processes described herein. In some implementations, execution of the set of instructions, by one or more processors420, causes the one or more processors420and/or the device400to perform one or more processes described herein. In some implementations, hardwired circuitry may be used instead of or in combination with the instructions to perform one or more processes described herein. Thus, implementations described herein are not limited to any specific combination of hardware circuitry and software. The number and arrangement of components shown inFIG.4are provided as an example. Device400may include additional components, fewer components, different components, or differently arranged components than those shown inFIG.4. Additionally, or alternatively, a set of components (e.g., one or more components) of device400may perform one or more functions described as being performed by another set of components of device400. FIG.5is a flowchart of an example process500associated with bonding semiconductor substrates. In some implementations, one or more process blocks ofFIG.5may be performed by a bonding tool (e.g., the bonding tool100). Additionally, or alternatively, one or more process blocks ofFIG.5may be performed by one or more components of device400, such as processor420, memory430, storage component440, input component450, output component460, and/or communication component470. As shown inFIG.5, process500may include positioning a first semiconductor substrate and a second semiconductor substrate in a processing chamber of a bonding tool (block510). For example, the first semiconductor substrate202and the second semiconductor substrate204may be placed in the processing chamber102of the bonding tool100, as described above. As further shown inFIG.5, process500may include providing a bonding gas to the processing chamber at a first pressure through a gas supply system of the bonding tool to purge the processing chamber (block520). For example, the bonding tool100may provide the bonding gas208to the processing chamber102at the first pressure (e.g., the pressure (P1)) through the gas supply system104of the bonding tool100to purge the processing chamber102, as described above. As further shown inFIG.5, process500may include pressurizing the processing chamber to a second pressure, where the second pressure is less than the first pressure (block530). For example, the bonding tool100may pressurize the processing chamber102to the second pressure (e.g., the pressure (P2)), as described above. In some implementations, the second pressure (e.g., the pressure (P2)) is less than the first pressure (e.g., the pressure (P1)). As further shown inFIG.5, process500may include providing the bonding gas to the processing chamber at a third pressure through the gas supply system to maintain the processing chamber approximately at the second pressure (block540). For example, the bonding tool100may provide the bonding gas208to the processing chamber102at the third pressure (e.g., the pressure (P3)) through the gas supply system104to maintain the processing chamber102approximately at the second pressure (e.g., the pressure (P2)), as described above. In some implementations, a pressure differential between the second pressure and the third pressure in a range of approximately 0 mbar to less than approximately 5 mbar. However, other values for the pressure differential are within the scope of the present disclosure. Process500may include additional implementations, such as any single implementation or any combination of implementations described below and/or in connection with one or more other processes described elsewhere herein. In a first implementation, the third pressure (e.g., the pressure (P3)) is in a range of approximately 0 mbar to approximately 5 mbar. In a second implementation, alone or in combination with the first implementation, providing the bonding gas208to the processing chamber102at the first pressure (e.g., the pressure (P1)) through the gas supply system104includes providing the bonding gas208to the processing chamber102at the first pressure (e.g., the pressure (P1)) through the first valve112of the gas supply system104and through the gas supply line116that extends directly from the first valve112to the processing chamber102without an intervening valve. In a third implementation, alone or in combination with one or more of the first and second implementations, providing the bonding gas208to the processing chamber102at the third pressure (e.g., the pressure (P3)) through the gas supply system104to maintain the processing chamber102approximately at the second pressure (e.g., the pressure (P2)) includes providing the bonding gas208to the processing chamber102at the third pressure (e.g., the pressure (P3)) through the second valve114of the gas supply system104and through the gas supply line116that extends directly from the second valve114to the processing chamber102without an intervening valve. In a fourth implementation, alone or in combination with one or more of the first through third implementations, the first valve112includes a binary flow valve and the second valve114includes a variable flow valve. In a fifth implementation, alone or in combination with one or more of the first through fourth implementations, process500includes bonding the first semiconductor substrate202and the second semiconductor substrate204while providing the bonding gas208to the processing chamber102at the third pressure (e.g., the pressure (P3)) through the gas supply system104to maintain the processing chamber102approximately at the second pressure (e.g., the pressure (P2)). In a sixth implementation, alone or in combination with one or more of the first through fifth implementations, providing the bonding gas208to the processing chamber102at the third pressure (e.g., the pressure (P3)) through the gas supply system104to maintain the processing chamber102approximately at the second pressure (e.g., the pressure (P2)) includes providing the bonding gas208to the processing chamber102at the third pressure (e.g., the pressure (P3)) through the gas supply system104to maintain the processing chamber102approximately at the second pressure (e.g., the pressure (P3)) to minimize the likelihood of the first semiconductor substrate (202) and the second semiconductor substrate (204) touching prior to bonding the first semiconductor substrate (202) and the second semiconductor substrate (204). AlthoughFIG.5shows example blocks of process500, in some implementations, process500may include additional blocks, fewer blocks, different blocks, or differently arranged blocks than those depicted inFIG.5. Additionally, or alternatively, two or more of the blocks of process500may be performed in parallel. FIG.6is a flowchart of an example process600associated with bonding semiconductor substrates. In some implementations, one or more process blocks ofFIG.6may be performed by a bonding tool (e.g., the bonding tool100). Additionally, or alternatively, one or more process blocks ofFIG.6may be performed by one or more components of device400, such as processor420, memory430, storage component440, input component450, output component460, and/or communication component470. As shown inFIG.6, process600may include opening a first valve of a gas supply system of a bonding tool to provide a bonding gas to a processing chamber of the bonding tool through a gas supply line of the gas supply system (block610). For example, the bonding tool100may open the first valve112of the gas supply system104of the bonding tool100to provide the bonding gas208to the processing chamber102of the bonding tool100through the gas supply line116of the gas supply system104, as described above. As further shown inFIG.6, process600may include closing the first valve after purging the processing chamber using the bonding gas (block620). For example, the bonding tool100may close the first valve114after purging the processing chamber102using the bonding gas208, as described above. As further shown inFIG.6, process600may include pressurizing the processing chamber and the gas supply line to a first pressure (block630). For example, the bonding tool100may pressurize the processing chamber102and the gas supply line116to a first pressure (e.g., the pressure (P2)), as described above. As further shown inFIG.6, process600may include opening a second valve to regulate a flow of the bonding gas to the processing chamber through the gas supply line to maintain the processing chamber approximately at the first pressure, where the bonding gas is supplied through the second valve at a second pressure (block640). For example, the bonding tool100may open the second valve114to regulate a flow of the bonding gas208to the processing chamber102through the gas supply line116to maintain the processing chamber102approximately at the first pressure (e.g., the pressure (P2)), as described above. In some implementations, the bonding gas208is supplied through the second valve114at a second pressure (e.g., the pressure (P3)). As further shown inFIG.6, process600may include bonding a first semiconductor substrate and a second semiconductor substrate in the processing chamber while the processing chamber is maintained approximately at the first pressure (block650). For example, the bonding tool100may bond the first semiconductor substrate202and the second semiconductor substrate204in the processing chamber102while the processing chamber102is maintained approximately at the first pressure (e.g., the pressure (P2)), as described above. Process600may include additional implementations, such as any single implementation or any combination of implementations described below and/or in connection with one or more other processes described elsewhere herein. In a first implementation, process600includes closing the second valve114after bonding the first semiconductor substrate202and the second semiconductor substrate204, and opening the first valve112to provide the purge gas212to the processing chamber102through the gas supply line116to purge the processing chamber102of the bonding gas208and to depressurize the processing chamber102. In a second implementation, alone or in combination with the first implementation, the first pressure (e.g., the pressure (P2)) and the second pressure (e.g., the pressure (P3)) are each in a range of approximately 0 mbar to approximately 10 mbar. In a third implementation, alone or in combination with one or more of the first and second implementations, process600includes placing the first semiconductor substrate202on a chuck (e.g., the bonding chuck126) in the processing chamber102, and placing the second semiconductor substrate204on the plurality of support members128in the processing chamber102, and bonding the first semiconductor substrate202and the second semiconductor substrate204includes actuating the plurality of support members128to cause the second semiconductor substrate204to drop onto the first semiconductor substrate202. In a fourth implementation, alone or in combination with one or more of the first through third implementations, the distance206between the first semiconductor substrate202on the chuck (e.g., the bonding chuck126) and the second semiconductor substrate204on the plurality of support members128is in a range of approximately 90 microns to approximately 110 microns. In a fifth implementation, alone or in combination with one or more of the first through fourth implementations, bonding the first semiconductor substrate202and the second semiconductor substrate204includes increasing a temperature in the processing chamber102to perform a eutectic bonding operation to bond the first semiconductor substrate202and the second semiconductor substrate204. In a sixth implementation, alone or in combination with one or more of the first through fifth implementations, the first valve114includes a binary flow valve and the second valve114includes a variable flow valve. In a seventh implementation, alone or in combination with one or more of the first through sixth implementations, the processing chamber102and the gas supply line116are pressurized to the first pressure (e.g., the pressure (P2)) to substantially prevent the first semiconductor substrate202and the second semiconductor substrate204from touching prior to bonding the first semiconductor substrate202and the second semiconductor substrate204. AlthoughFIG.6shows example blocks of process600, in some implementations, process600may include additional blocks, fewer blocks, different blocks, or differently arranged blocks than those depicted inFIG.6. Additionally, or alternatively, two or more of the blocks of process600may be performed in parallel. In this way, the bonding tool described herein may reduce, minimize, and/or prevent early or premature contact between semiconductor substrates that are to be bonded. In some implementations, the bonding tool includes a gas supply line that is configured to supply or provide various types of gasses to a processing chamber of the bonding tool. The gas supply line may extend directly between valves associated with one or more gas supply tanks and the processing chamber such that gas supply line is uninterrupted without any intervening valves or other types of structures that might otherwise cause a pressure buildup in the gas supply line between the processing chamber and the valves associated with the one or more gas supply tanks. In this way, the pressure in the gas supply line may be maintained at or near the pressure in the processing chamber so that gas provided to the processing chamber through the gas supply line does not cause a pressure imbalance in the processing chamber that might otherwise cause early or premature contact between semiconductor substrates that are to be bonded in the processing chamber. Accordingly, the gas supply line of the bonding tool described herein may increase bonding uniformity across semiconductor substrates that are to be bonded, may decrease local area yield loss on semiconductor substrates that are to be bonded, and/or may reduce malfunctions of devices on semiconductor substrates that are to be bonded. As described in greater detail above, some implementations described herein provide a bonding tool. The bonding tool includes a processing chamber. The bonding tool includes a pump configured to pump the processing chamber down to a bonding pressure. The bonding tool includes a gas supply system configured to provide a bonding gas to the processing chamber through a gas supply line of the gas supply system, where the gas supply line extends directly between a valve, that is configured to control a flow of the bonding gas from a bonding gas supply tank to the processing chamber through the gas supply line, and a gas inlet of the processing chamber. As described in greater detail above, some implementations described herein provide a method. The method includes positioning a first semiconductor substrate and a second semiconductor substrate in a processing chamber of a bonding tool. The method includes providing a bonding gas to the processing chamber at a first pressure through a gas supply system of the bonding tool to purge the processing chamber. The method includes pressurizing the processing chamber to a second pressure, where the second pressure is less than the first pressure. The method includes providing the bonding gas to the processing chamber at a third pressure through the gas supply system to maintain the processing chamber approximately at the second pressure, where a pressure differential between the second pressure and the third pressure in a range of approximately 0 millibar (mbar) to less than approximately 5 mbar. As described in greater detail above, some implementations described herein provide a method. The method includes opening a first valve of a gas supply system of a bonding tool to provide a bonding gas to a processing chamber of the bonding tool through a gas supply line of the gas supply system. The method includes closing the first valve after purging the processing chamber using the bonding gas. The method includes pressurizing the processing chamber to a first pressure and the gas supply line to a second pressure, where the first pressure and the second pressure are approximately equal. The method includes opening a second valve to regulate a flow of the bonding gas to the processing chamber through the gas supply line to maintain the processing chamber approximately at the first pressure. The method includes bonding a first semiconductor substrate and a second semiconductor substrate in the processing chamber while the processing chamber is maintained approximately at the first pressure. The foregoing outlines features of several embodiments so that those skilled in the art may better understand the aspects of the present disclosure. Those skilled in the art should appreciate that they may readily use the present disclosure as a basis for designing or modifying other processes and structures for carrying out the same purposes and/or achieving the same advantages of the embodiments introduced herein. Those skilled in the art should also realize that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and that they may make various changes, substitutions, and alterations herein without departing from the spirit and scope of the present disclosure. | 47,303 |
11862483 | DETAILED DESCRIPTION In the following detailed description, reference is made to the accompanying drawings, which form a part of the description. In the drawings, similar symbols typically identify similar components, unless context dictates otherwise. Furthermore, unless otherwise noted, the description of each successive drawing may reference features from one or more of the previous drawings to provide clearer context and a more substantive explanation of the current exemplary embodiment. Still, the exemplary embodiments described in the detailed description, drawings, and claims are not meant to be limiting. Other embodiments may be utilized, and other changes may be made, without departing from the spirit or scope of the subject matter presented herein. It will be readily understood that the aspects of the present disclosure, as generally described herein and illustrated in the drawings, may be arranged, substituted, combined, separated, and designed in a wide variety of different configurations, all of which are explicitly contemplated herein. Hereinafter, exemplary embodiments of a substrate processing method and a substrate processing apparatus according to the present disclosure will be described in detail with reference to the accompanying drawings. However, it should be noted that the substrate processing method and the substrate processing apparatus of the present disclosure are not limited by the following exemplary embodiments. In a liquid processing in which a substrate (hereinafter, referred to as “wafer”) such as a semiconductor wafer is processed by supplying a processing liquid onto the wafer, a wafer temperature in the liquid processing is one of critical factors that affect a processing result. Thus, to investigate more accurately whether the processing result is good or bad, it is required to measure the wafer temperature in the liquid processing appropriately. Conventionally, as a way to measure the wafer temperature, there is known a method of performing a liquid processing on a test wafer having a sensor therein through the same processes as those for a product wafer, and, then, estimating a temperature of the product wafer in the liquid processing from thus obtained temperature data. In this method, however, the temperatures of the product wafers in the liquid processing cannot be measured individually. In this regard, there is a demand for a technique capable of investigating, for every product wafer, the temperature of the product wafer in the liquid processing, and capable of appropriately investigating whether the result of the liquid processing upon the product wafer is good or bad. A substrate processing system according to an exemplary embodiment detects a local temperature (for example, a temperature of a central portion or a temperature of an edge portion, etc.) of a product wafer in a liquid processing by using one or more temperature sensors provided in a processing unit. Further, the substrate processing system according to the exemplary embodiment generates temperature distribution information indicating a temperature distribution within a surface of the product wafer in the liquid processing based on the detected temperature and one or more parameter values which specify processing conditions for the liquid processing. Further, the substrate processing system according to the exemplary embodiment determines whether the result of the liquid processing is good or bad based on the generated temperature distribution information. To elaborate, the substrate processing system according to the exemplary embodiment determines whether a result of each of a series of processings (for example, an etching processing, a drying processing, and so forth) included in the liquid processing for each product wafer based on the generated temperature distribution information. Furthermore, the substrate processing system according to the exemplary embodiment may also be capable of determining presence or absence of a difference in the result of the liquid processing between wafers, between processing units or between the lots. As stated above, in the substrate processing system according to the exemplary embodiment, by measuring, for every product wafer, the temperature distribution within the surface of the product wafer in the liquid processing, it is possible to investigate whether the result of the liquid processing is good or bad for each product wafer. Thus, in the substrate processing system according to the exemplary embodiment, abnormality in the result of the liquid processing and presence of various differences can be found out in early stage, making it possible to reduce production of defective wafers. <Outline of Substrate Processing System> A schematic configuration of a substrate processing system1(an example of a substrate processing apparatus) according to the exemplary embodiment will be described with reference toFIG.1.FIG.1is a diagram illustrating the schematic configuration of the substrate processing system1according to the exemplary embodiment. In the following, in order to clarify positional relationship, the X-axis, the Y-axis and the Z-axis that are orthogonal to each other will be defined, and the positive Z-axis direction will be regarded as a vertically upward direction. As depicted inFIG.1, the substrate processing system1includes a carry-in/out station2and a processing station3. The carry-in/out station2and the processing station3are provided adjacent to each other. The carry-in/out station2is provided with a carrier placing section11and a transfer section12. A plurality of carriers C each of which accommodates therein a plurality of substrates (semiconductor wafers W in the present exemplary embodiment) (hereinafter, referred to as wafers W) horizontally is provided in the carrier placing section11. The transfer section12is provided adjacent to the carrier placing section11, and provided with a substrate transfer device13and a delivery unit14. The substrate transfer device13is provided with a wafer holding mechanism configured to hold the wafer W. Further, the substrate transfer device13is movable horizontally and vertically and pivotable around a vertical axis, and transfers the wafers W between the carriers C and the delivery unit14by using the wafer holding mechanism. The processing station3is provided adjacent to the transfer section12. The processing station3is provided with a transfer section15and a plurality of processing units16. These processing units16are arranged at both sides of the transfer section15. The transfer section15is provided with a substrate transfer device17therein. The substrate transfer device17is provided with a wafer holding mechanism configured to hold the wafer W. Further, the substrate transfer device17is movable horizontally and vertically and pivotable around a vertical axis. The substrate transfer device17transfers the wafers W between the delivery unit14and the processing units16by using the wafer holding mechanism. The processing units16are configured to perform a substrate processing on the wafers W transferred by the substrate transfer device17. Each processing unit16holds the transferred wafer W, and performs the substrate processing on the held wafer W. The processing unit16performs the substrate processing by supplying a processing liquid onto the held wafer. The processing liquid may be, for example, an etching liquid. Though not particularly limited, the etching liquid may be HF (Hydro Fluoric acid), HCl (Hydro Chloric acid), TMAH (Tetra Methyl Ammonium Hydroxide), or the like. Alternatively, the processing liquid may be a cleaning liquid such as SC1 (mixed aqueous solution of ammonia and hydrogen peroxide) or DHF (Diluted Hydrofluoric acid). Still alternatively, the processing liquid may be a rinse liquid such as DIW (Delonized water), or a replacement liquid such as IPA (IsoPropyl Alcohol). Further, the substrate processing system1is equipped with a control device4. The control device4is, for example, a computer, and includes a controller18and a storage19. The storage19stores a program that controls various processings performed in the substrate processing system1. The controller18controls the operations of the substrate processing system1by reading and executing the program stored in the storage19. Further, the program may be recorded in a computer-readable recording medium, and installed from the recording medium to the storage19of the control device4. The computer-readable recording medium may be, for example, a hard disc (HD), a flexible disc (FD), a compact disc (CD), a magneto optical disc (MO), or a memory card. In the substrate processing system1configured as described above, the substrate transfer device13of the carry-in/out station2first takes out a product wafer W (hereinafter, simply referred to as “wafer W”) from a carrier C placed in the carrier placing section11, and then places the taken wafer Won the delivery unit14. The wafer W placed on the delivery unit14is taken out from the delivery unit14by the substrate transfer device17of the processing station3and carried into a processing unit16. The wafer W carried into the processing unit16is processed by the processing unit16, and then, carried out from the processing unit16and placed on the delivery unit14by the substrate transfer device17. After the processing of placing the wafer W on the delivery unit14, the wafer W is returned to the carrier C of the carrier placing section11by the substrate transfer device13. <Configuration of Processing Unit> Now, a configuration of the processing unit16will be explained with reference toFIG.2.FIG.2is a diagram illustrating a configuration of the processing unit16according to the exemplary embodiment. As shown inFIG.2, the processing unit16is equipped with a chamber20, a substrate holding mechanism30, a processing liquid supply40, a recovery cup50, and a rear surface supply60. The chamber20accommodates therein the substrate holding mechanism30, the processing liquid supply40, the recovery cup50, and the rear surface supply60. A FFU (Fan Filter Unit)21is provided at a ceiling of the chamber20. The FFU21is connected to a clean gas source21bvia a supply line21a, and creates a downflow within the chamber20by discharging a clean gas supplied from the clean gas source21bdownwards from the ceiling of the chamber20. The clean gas may be, by way of non-limiting example, dry air. Further, an inert gas such as N2(nitrogen) gas or an argon gas may be used as the clean gas. Furthermore, the clean gas supplied from the clean gas source21bis previously regulated to have a preset temperature and a preset humidity. The supply line21ais provided with a valve21c, a temperature adjuster21d, and a humidity adjuster21e. The valve21cserves to open or close the supply line21a. The temperature adjuster21dadjusts a temperature of the clean gas flowing in the supply line21a. The humidity adjuster21eadjusts a humidity of the clean gas flowing in the supply line21a. The valve21c, the temperature adjuster21dand the humidity adjuster21eare provided for each processing unit16. Accordingly, the substrate processing system1according to the exemplary embodiment is capable of adjusting the temperature and the humidity of the clean gas supplied from the FFU into the chamber20for the processing units16individually. The substrate holding mechanism30is equipped with a holder31, a supporting column32, and a driver33. The holder31holds the wafer W horizontally. To be specific, the holder31is equipped with a multiple number of grippers31a, and holds an edge portion of the wafer W with the grippers31a. The supporting column32is vertically extended. A base end of the supporting column32is rotatably supported by the driver33, and the supporting column32supports the holder31horizontally at a leading end thereof. The driver33is configured to rotate the supporting column32around a vertical axis. The substrate holding mechanism30rotates the supporting column32by using the driver33, thus allowing the holder31supported on the supporting column32to be rotated, and, accordingly, allowing the wafer W held by the holder31to be rotated as well. The processing liquid supply40is configured to supply various processing liquids onto the wafer W. The processing liquid supply40is equipped with a nozzle41disposed above the wafer W, an arm42supporting the nozzle41, and a moving mechanism43configured to move the arm42. The nozzle41is connected to a chemical liquid supply unit70to be described later via a supply line44a, and discharges a chemical liquid from the chemical liquid supply unit70onto a front surface of the wafer W. In the exemplary embodiment, the chemical liquid is an etching liquid. Further, the nozzle41is connected to a rinse liquid source80to be described later via a supply line44b, and supplies a rinse liquid from the rinse liquid source80onto the front surface of the wafer W. In the exemplary embodiment, the rinse liquid is DIW. Furthermore, the nozzle41is connected to a replacement liquid supply unit90to be described later via a supply line44c, and discharges a replacement liquid from the replacement liquid supply unit90onto the front surface (top surface) of the wafer W. In the exemplary embodiment, the replacement liquid is IPA. The supply line44ais provided with a valve45aand a temperature adjuster46a. The valve45aserves to open or close the supply line44a. The temperature adjuster46aadjusts a temperature of the etching liquid flowing in the supply line44aby using, for example, a Peltier device, temperature control water, or the like. Likewise, the supply line44cis provided with a valve45cand a temperature adjuster46c. The valve45cserves to open or close the supply line44c. The temperature adjuster46cadjusts a temperature of the IPA flowing in the supply line44c. The valve45aand the temperature adjuster46aare provided for each processing unit16. Accordingly, the substrate processing system1according to the exemplary embodiment is capable of adjusting the temperature of the etching liquid supplied from the chemical liquid supply unit70in the processing units16individually. Likewise, the valve45cand the temperature adjuster46care provided for each processing unit16. Accordingly, the substrate processing system1according to the exemplary embodiment is capable of adjusting the temperature of the IPA supplied from the replacement liquid supply unit90in the processing unit16individually. Furthermore, the supply line44bis provided with a valve45bconfigured to open or close the supply line44b. The recovery cup50is disposed to surround the holder31, and collects the processing liquid scattered from the wafer W when the holder31is rotated. A drain port51is formed at a bottom of the recovery cup50, and the processing liquid collected by the recovery cup50is drained from the drain port51to the outside of the processing unit16. Further, an exhaust port52is formed at the bottom of the recovery cup50to exhaust the gas supplied from the FFU21to the outside of the processing unit16. The rear surface supply60is disposed in, for example, a hollow portion vertically formed through the holder31and the supporting column32. A vertically extended flow path61is formed within the rear surface supply60. An upper end of the flow path61is formed as a discharge opening62opened toward a rear surface of the wafer W. The flow path61of the rear surface supply60is connected to a temperature control liquid source61bvia a supply line61a. The rear surface supply60discharges the temperature control liquid from the temperature control liquid source61btoward the rear surface of the wafer W through the discharge opening62. In the exemplary embodiment, the temperature control liquid is HDIW (Hot DIW), that is, DIW heated to a predetermined temperature. The supply line61ais provided with a valve61cand a temperature adjuster61d. The valve61cserves to open or close the supply line61a. The temperature controller61dadjusts a temperature of the temperature control liquid flowing in the supply line61a. The valve61cand the temperature adjuster61dare provided for each processing unit16. Accordingly, the substrate processing system1according to the exemplary embodiment is capable of adjusting the temperature of the temperature control liquid supplied from the rear surface supply60to the rear surface of the wafer W in the processing units16individually. <Example Layout of Temperature Sensors> An example layout of temperature sensors configured to detect a local temperature of the wafer W in the liquid processing will be explained with reference toFIG.3.FIG.3is a diagram illustrating the example layout of the temperature sensors according to the exemplary embodiment. As depicted inFIG.3, the processing unit16includes a first temperature sensor110and a plurality of second temperature sensors120. The first temperature sensor110is provided in the nozzle41, and detects a temperature of the processing liquid within the nozzle41. The processing liquid supplied from the nozzle41is discharged onto a central portion of the wafer W. Thus, the temperature detected by the first temperature sensor110may be regarded as a temperature of the central portion of the wafer Win the liquid processing. Further, the first temperature sensor110need not necessarily be provided at the nozzle41as long as it is provided downstream of the temperature adjusters46aand46cin the processing liquid supply40. The second temperature sensors120are provided at the grippers31aof the substrate holding mechanism30(seeFIG.2) to detect temperatures of leading ends (portions to be in contact with the wafer W) of the grippers31a.FIG.3illustrates an example where the substrate holding mechanism30has three grippers31a, and one second temperature sensor120is provided at the corresponding one of three grippers31a. The grippers31aare in contact with the edge portion of the wafer W. Thus, the temperature of the gripper31adetected by each second temperature sensor120may be regarded as a temperature of the edge portion of the wafer W in the liquid processing. Further, the processing unit16only needs to be equipped with at least one second temperature sensor120. That is, the second temperature sensor120needs to be provided at one of the plurality of grippers31aat least. Further, the second temperature sensor120is not limited to being provided at the gripper31aas long as it is provided at a member which comes into contact with the edge portion of the wafer W. <Configuration of Replacement Liquid Supply Unit> Now, the replacement liquid supply unit90will be explained with reference toFIG.4.FIG.4is a diagram illustrating a configuration of the replacement liquid supply unit90according to the exemplary embodiment. AlthoughFIG.4illustrates an example where two of the processing units16are connected to the replacement liquid supply unit90, the number of the processing units16connected to the single replacement liquid supply unit90is not limited to the present example. Furthermore, the chemical liquid supply unit70configured to supply the etching liquid to the processing unit(s)16may have the same configuration as the replacement liquid supply unit90. The replacement liquid supply unit90is equipped with a tank91, a replenishing device92, a drain line93, a circulation line94, a supply line95, and a return line96. The tank91stores the IPA therein. The replenishing device92supplies new IPA to the tank91. For example, the replenishing device72supplies the new IPA into the tank91when replacing the IPA of the tank91or when an amount of the IPA within the tank91falls below a certain amount. The drain line93serves to drain the IPA from the tank91when replacing the IPA within the tank91. Both ends of the circulation line94is connected to the tank91, and the circulation line94serves to return the IPA sent from the tank91back into the tank91. The circulation line94is configured to allow the IPA to flow to the outside of the tank91and then return to the tank91. The circulation line94is provided with a pump81, a heater82, a filter83, a flowmeter84, a temperature sensor85, and a backpressure valve86. These components are arranged in the order of the pump81, the heater82, the filter83, the flowmeter84, the temperature sensor85and the backpressure valve86from the upstream side in a flow direction of the IPA with respect to the tank91. The pump81is configured to force-feed the IPA in the circulation line94. The force-fed IPA circulates through the circulation line94and is returned back into the tank91. The heater82is provided in the circulation line94to adjust a temperature of the IPA. To be specific, the heater82heats the IPA. The heater82controls a heating amount of the IPA based on a signal from the control device4to adjust the temperature of the IPA. For example, the heating amount of the IPA by the heater82is adjusted based on a temperature of the IPA detected by the temperature sensor85. By way of example, the control device4adjusts the temperature of the IPA to a certain temperature by controlling the heater82. The certain temperature is a temperature allowing the IPA discharged from the nozzle of the processing liquid supply40onto the wafer W in the supply thereof to have a preset processing temperature. The certain temperature is a temperature set based on a thermal capacity of a filter73provided in the supply line95or the like. The filter83removes a foreign substance which is a contaminant such as a particle included in the IPA flowing in the circulation line94. The flowmeter84measures a flow rate of the IPA flowing in the circulation line94. The temperature sensor85detects the temperature of the IPA flowing in the circulation line94. The temperature sensor85is provided in the circulation line94upstream of a point to which the supply line95is connected. The backpressure valve86increases a degree of valve openness thereof when a pressure of the IPA at the upstream of the backpressure valve86is larger than a certain pressure. The backpressure valve86decreases the degree of valve openness when the pressure of the IPA at the upstream of the backpressure valve86is smaller than the certain pressure. The backpressure valve86functions to maintain the pressure of the processing liquid at the upstream side thereof at the certain pressure. The certain pressure is a previously set pressure. The degree of valve openness of the backpressure valve86is controlled by the control device4. By controlling the degree of valve openness of the backpressure valve86, the flow rate of the IPA in the circulation line94can be adjusted. That is, the backpressure valve86is provided in the circulation line94, and serves to adjust the flow rate of the IPA returning to the tank91through the circulation line94. Further, the flow rate of the IPA in the circulation line94may be adjusted by controlling a discharge pressure of the pump81. The flow rate of the IPA in the circulation line94is controlled based on the flow rate of the IPA detected by the flowmeter84. The supply line95is connected to the circulation line94. The supply line95is connected to the circulation line94downstream of the temperature sensor85and upstream of the backpressure valve86. The supply line95includes a plurality of supply lines, and these supply lines95are provided to correspond to the plurality of processing liquid supplies40. Each supply line95is branched off from the circulation line94and configured to be capable of supplying the IPA to the corresponding one of the processing liquid supplies40. Here, although the supply line95of the replacement liquid supply unit90and the supply line44cof the processing unit16are described as different supply lines, they may be implemented by one and the same supply line. The supply line95is provided with a flowmeter71, a constant-pressure valve72, and the filter73. They are arranged in the order of the flowmeter71, the constant-pressure valve72and the filter73in the flow direction of the IPA flowing from the circulation line94to the processing liquid supply40. The flowmeter71measures the flow rate of the IPA flowing in the supply line95. The constant-pressure valve72adjusts the pressure of the IPA at the downstream of the constant-pressure valve72. By way of example, the constant-pressure valve72adjusts the pressure of the IPA such that the discharge amount of the IPA discharged from the nozzle of the processing liquid supply40becomes a certain discharge amount. That is, the constant-pressure valve72adjusts the flow rate of the IPA discharged from the nozzle of the processing liquid supply40. The certain discharge amount is a previously set amount, and is set based on a processing condition for the wafer W. The constant-pressure valve72adjusts the pressure of the IPA based on a signal from the control device4. The filter73is provided in the supply line95upstream of a connection point where the return line96and the supply line95are connected. The filter73is provided in the supply line95downstream of the constant-pressure valve72. The filter73removes a foreign substance which is a contaminant such as a particle included in the IPA flowing in the supply line95. The return line96is connected to the supply line95to return the IPA to the tank91from the supply line95. The return line96is connected to the supply line95at a connection point between the filter73and the valve45c. The return line96includes a plurality of return lines, and these return lines96are provided to correspond to the plurality of processing liquid supplies40. Each return line96is provided with a valve74. The valve74serves to switch on and off of the flow of the IPA in the return line96. If the valve74is opened, the IPA flows from the supply line95into the return line96. The IPA flowing in the return line96is returned back into the tank91. If the valve74is closed, the IPA does not flow into the return line96. The valve74is opened or closed based on a signal from the control device4. The plurality of return lines96join each other at the downstream of the valves74in the flow direction of the IPA flowing in the return lines96, and are connected to the tank91. A temperature sensor75is provided in the return line96downstream of a point where the plurality of return lines96are connected. The temperature sensor75detects a temperature of the IPA returning to the tank91from the return line96. Further, the return line96may be connected to the circulation line94downstream of the backpressure valve86. The control device4controls the valve74provided in the return line96to be closed and the valve45cprovided in the processing unit16to be opened in a supply mode in which the IPA is supplied to the wafer W from the processing liquid supply40. Accordingly, the IPA is discharged from the nozzle of the processing liquid supply40without flowing into the return line96. Meanwhile, in a standby mode in which the IPA is not supplied to the wafer W from the processing liquid supply40, the control device4controls the valve45cprovided in the processing unit16to be closed and the valve74provided in the return line96to be opened. As a result, the IPA is returned back into the tank91through the return line96without being discharged from the processing liquid supply40. As stated above, in the substrate processing system1according to the exemplary embodiment, the IPA adjusted to the certain temperature by using the replacement liquid supply unit90can be supplied to the plurality of processing units16. Further, in the substrate processing system1according to the exemplary embodiment, the temperature of the IPA can be adjusted in the processing units16individually, using the temperature adjusters46crespectively provided in the processing units16. <Configuration of Control Device> Now, a configuration of the control device4according to the exemplary embodiment will be described with reference toFIG.5.FIG.5is a block diagram illustrating the configuration of the control device4according to the exemplary embodiment. As depicted inFIG.5, the control device4according to the exemplary embodiment includes the controller18and the storage19. The storage19is implemented by, for example, a semiconductor memory device such as a RAM (Random Access Memory) or a flash memory, or a storage device such as a hard disk or an optical disk. The storage19stores therein recipe information191, collection information192, a model expression193, temperature distribution information194, and designation information195. The controller18is implemented by, for example, a CPU (Central Processing Unit) or MPU (Micro Processing Unit) which executes various programs stored in a storage (for example, the storage19) within the control device4by using a RAM as a working area. Further, the controller18may be implemented by an integrated circuit such as, but not limited to, an ASIC (Application Specific Integrated Circuit) or a FPGA (Field Programmable Gate Array). The controller18includes an operation controller181, a collecting unit182, a monitoring unit183, a determination unit184and an abnormality handling unit185, and implements or carries out a function and an operation of a processing to be described below. Further, the internal configuration of the controller18is not limited to the example shown inFIG.5, and the controller18may have various other configurations as long as it is capable of carrying out a substrate processing to be described below. Furthermore, a connection relationship between the individual processors belonging to the controller18is not limited to the example shown inFIG.5, and may be different. The operation controller181controls the processing unit16based on the recipe information191stored in the storage19, thus allowing the processing unit16to perform a series of liquid processings upon the wafer W. The recipe information191is information indicating the content and the sequence of the liquid processings performed in the processing unit16, and includes multiple parameter values defining processing conditions for the liquid processings. By way of example, the recipe information191includes parameter values such as a processing time, a rotation number of the wafer W, a kind of the processing liquid, a discharge flow rate of the processing liquid, a discharge temperature of the processing liquid, and so forth. These parameter values are specified for each processings included in the liquid processings. Here, an example of the liquid processings performed under the control of the operation controller181will be explained with reference toFIG.6.FIG.6is a flowchart illustrating a sequence of the liquid processing performed by the processing unit16according to the exemplary embodiment. The series of liquid processings shown inFIG.6are performed according to the recipe information191. First, the processing unit16holds the wafer W, which is carried into the chamber20by the substrate transfer device17(seeFIG.1), by using the holder31of the substrate holding mechanism30. To elaborate, the processing unit16holds the edge portion of the wafer W with the plurality of grippers31a. Then, the processing unit16rotates the holder31around the vertical axis by using the driver33, thus allowing the wafer W to be rotated. Then, the processing unit16performs an etching processing (process S01). First, in the etching processing, the nozzle41is located above the center of the wafer W by using the moving mechanism43of the processing liquid supply40. Then, the processing unit16opens the valve45ato supply the etching liquid from the nozzle41onto the front surface of the wafer W being rotated. The etching liquid supplied to the center of the wafer W is diffused onto the entire front surface of the wafer W as the wafer W is rotated. Accordingly, the front surface of the wafer W is etched. Thereafter, the processing unit16closes the valve45a, thus stopping the supply of the etching liquid onto the wafer W. Subsequently, the processing unit16carries out a rinsing processing (process S02). In the rinsing processing, the valve45bis opened, thus allowing the DIW to be supplied from the nozzle41onto the front surface of the wafer W being rotated. The DIW supplied to the center of the wafer W is diffused onto the entire front surface of the wafer W as the wafer W is rotated. Accordingly, the etching liquid remaining on the front surface of the wafer W is washed away by the DIW. Then, the processing unit16closes the valve45b, thus stopping the supply of the DIW onto the wafer W. Next, the processing unit16performs a replacement processing (process S03). In the replacement processing, the valve45cis opened, thus allowing the IPA to be supplied from the nozzle41onto the front surface of the wafer W being rotated. The IPA supplied to the center of the wafer W is diffused onto the entire front surface of the wafer W as the wafer W is rotated. Accordingly, the DIW left on the front surface of the wafer W is replaced by the IPA. Then, the processing unit16closes the valve45c, thus stopping the supply of the IPA onto the wafer W. Then, the processing unit16performs a drying processing (process S04). In the drying processing, the wafer W is dried by being rotated at a speed higher than a rotation speed in the processes S01to S03by using the driver33. Then, the wafer W is carried out of the chamber20by the substrate transfer device17. Then, the series of liquid processings upon the single sheet of wafer W are completed. Reference is made back toFIG.5. During the liquid processings, the collecting unit182acquires temperature data from the first temperature sensor110of the processing unit16, and stores the acquired temperature data in the storage19as an item of “center temperature” in the collection information192. By way of example, the collecting unit182calculates, for each of the processings (the etching processing, the rinsing processing, the replacement processing, and the drying processing) included in the liquid processings, an average value of the temperatures detected by the first temperature sensor110in each processing, and stores the calculated average value in the storage19as a “center temperature” of the wafer W in each processing. Further, during the liquid processings, the collecting unit182acquires temperature data from the second temperature sensor120of the processing unit16, and stores the acquired temperature data in the storage19as an item of “edge temperature” in the collection information192. By way of example, the collecting unit182calculates, for each of the processings included in the liquid processings, an average value of temperatures detected by the second temperature sensor120in each processing, and stores the calculated average value in the storage19as an “edge temperature” of the wafer W in each processing. The collecting unit182also collects information other than the center temperature and the edge temperature. By way of example, the collecting unit182acquires a temperature within the chamber20, and stores this acquired temperature in the storage19as an item of “space temperature” in the collection information192. The temperature within the chamber20may be acquired by, for example, a non-illustrated temperature sensor provided within the chamber20, or may be acquired from the set temperature of the clean gas in the clean gas source21b. Furthermore, the collecting unit182also acquires humidity within the chamber20, and stores the acquired humidity in the storage19as an item of “space humidity” in the collection information192. The humidity within the chamber20may be acquired by, for example, a non-illustrated humidity sensor provided within the chamber20, or may be acquired from the set humidity of the clean gas in the clean gas source21b. In addition, the collecting unit182collects information upon the discharge flow rate and the rotation number from the recipe information191, and stores the acquired information in the storage19as an item of “discharge flow rate” and an item of “rotation number” in the collection information192, respectively. Further, the collecting unit182may collect a detection result of the flow rates from non-illustrated flowmeters provided in the supply lines44ato44c, for example, and may store the acquired detection result as the item of “discharge flow rate” in the storage19. Furthermore, the collecting unit182may also collect a detection result of a rotation number from a non-illustrated rotation sensor such as a rotary encoder configured to detect a rotation number of the supporting column32, for example, and may store the acquired detection result in the storage19as the item of “rotation number.” Besides, the collecting unit182may also collect information such as, but not limited to, an exhaust flow rate of the chamber20, a density of the processing liquid, and a thermal capacity of the processing liquid, and may store the collected information in the storage19as the collection information192. FIG.7is a diagram illustrating an example of the collection information192according to the exemplary embodiment. As depicted inFIG.7, the collection information192is information in which individual items of ‘wafer ID,’ ‘lot ID,’ ‘unit ID,’ ‘processing content,’ ‘center temperature,’ ‘edge temperature,’ ‘space temperature,’ ‘space humidity,’ ‘discharge flow rate,’ and ‘rotation number’ are related to each other. Identification information of the wafer W is stored in the item of ‘wafer ID.’ Identification information of a lot to which the wafer W belongs is stored in the item of ‘lot ID.’ Here, the lot is a manufacturing unit for product wafers. For example, a set of twenty five sheets of wafers W may be referred to as one lot. Identification information of the processing unit16which has processed the wafer W is stored in the item of ‘unit ID.’ Information for identifying the content of the liquid processings is stored in the item of ‘processing content.’ Further, inFIG.7, ‘S101’ is an example of identification information of the etching processing; ‘S102,’ an example of identification information of the rinsing processing; ‘S103,’ an example of identification information of the replacement processing; and ‘S104’, an example of identification information of the drying processing. The ‘center temperature’ refers to a temperature of the central portion of the wafer W during the liquid processing. Information based on temperature data obtained by the first temperature sensor110(for example, an average value of temperature data detected during the processing) is stored in the item of ‘center temperature.’ The ‘edge temperature’ refers to a temperature of the edge portion of the wafer W during the liquid processing. Information based on temperature data obtained by the second temperature sensors120(for example, an average value of temperature data detected during the processing) is stored in the item of ‘edge temperature.’ The ‘space temperature’ refers to a temperature within the chamber20, and the ‘space humidity’ refers to a humidity within the chamber20. For example, a temperature and a humidity detected by a non-illustrated temperature sensor and a non-illustrated humidity sensor provided within the chamber20are stored in the items of ‘space temperature’ and ‘space humidity,’ respectively. The ‘discharge flow rate’ refers to a discharge flow rate of the processing liquid, and the ‘rotation number’ refers to a rotation number of the wafer W. By way of example, information of the discharge flow rate and information of the rotation number acquired from the recipe information191are stored in the items of ‘discharge flow rate’ and ‘rotation number,’ respectively. The monitoring unit183monitors an in-surface temperature distribution of the wafer W during the liquid processing. To elaborate, by using the model expression193and the collection information192stored in the storage19, the monitoring unit183generates the temperature distribution information194indicating the in-surface temperature distribution of the wafer W during the liquid processing, and stores the generated temperature distribution information194in the storage19. Here, the model expression193is a model expression for estimating the in-surface temperature distribution of the wafer W during the liquid processing. To elaborate, the model expression193is one for estimating a temperature distribution within the entire surface of the wafer W from the local temperatures of the wafer W detected by the first and second temperature sensors110and120, using known parameter values. Further, from another point of view, the model expression193is one for correcting theoretical values of the in-surface temperature distribution of the wafer W derived from known processing conditions (parameters values) based on actual measurement values (sensor values). Upon the completion of the series of liquid processings upon the wafer W, the monitoring unit183acquires the collection information192upon the wafer W after being subjected to the liquid processing from the storage19. Then, the monitoring unit183puts the parameter values and the sensor values included in the acquired collection information192into the model expression193, thus producing the temperature distribution information194indicating the in-surface temperature distribution of the wafer W during the liquid processing. To be specific, temperatures at multiple points in a range from the central portion to the edge portion of the wafer W are obtained by using the model expression193. The monitoring unit183generates the temperature distribution information194by estimating temperatures between adjacent points among the multiple points by using, for example, regression analysis (curve fitting), and stores the generated temperature distribution information194in the storage19. The monitoring unit183generates the temperature distribution information194for each of the processings included in the liquid processings. FIG.8is a diagram illustrating an example of the temperature distribution information194according to the exemplary embodiment.FIG.8shows an example of the temperature distribution information194of a wafer W having a diameter of 300 mm. A horizontal axis of a graph ofFIG.8represents a wafer position, which indicates a distance from the center of the wafer W set as a reference point (0 mm). As depicted inFIG.8, the temperature distribution information194is information indicating temperatures (wafer temperatures) at respective positions (wafer positions) along a diametrical direction of the wafer W during the processing. By way of example, inFIG.8, black circles are data obtained from the model expression193, and a line connecting the black circles is data interpolated by the regression analysis, or the like. Further,FIG.8illustrates the temperature distribution information194in the form of a graph to ease understanding. However, the temperature distribution information194need not necessarily be in the form of the graph. The determination unit184determines whether the result of the liquid processing performed on the wafer W is good or bad, based on the temperature distribution information194stored in the storage19. The determination unit184makes this determination for each of the processings (the etching processing, the rinsing processing, the replacement processing, and the drying processing) included in the liquid processings. Here, an example of the good or bad determination upon the result of the etching processing will be explained with referenceFIG.9toFIG.12.FIG.9is a diagram showing an example of an etching rate conversion processing.FIG.10is a diagram illustrating an example of determining presence or absence of a difference between the wafers W.FIG.11is a diagram illustrating an example of determining presence or absence of a difference between the processing units16.FIG.12is a diagram illustrating an example of determining presence or absence of a difference between the lots. As shown inFIG.9, the determination unit184converts the temperature distribution information194into etching rate distribution information by using sensitivity data indicating a relationship between the temperature and the etching rate. The etching rate distribution information is information indicating etching rates (A/min) at respective positions (wafer positions) along the diametrical direction of the wafer W. The etching rate distribution information is stored in the storage19by being matched with, for example, the wafer ID, the lot ID, the unit ID, and the like. Then, based on the etching rate distribution information, the determination unit184determines whether the result of the etching processing is good or bad. By way of example, the determination unit184calculates an average value of the etching rates in the entire surface of the wafer W by using the etching rate distribution information. Then, the determination unit184determines whether the calculated average value exceeds a previously set threshold value. If the calculated average value exceeds the threshold value, the determination unit184makes a determination that the result of the etching processing is normal, whereas if it is below the threshold value, the determination unit184makes a determination that the result of the etching processing is abnormal. Further, the determination unit184also calculates a difference rate between a maximum value and a minimum value of the etching rates, referring to the etching rate distribution information. For example, the determination unit184calculates, as the difference rate, a ratio of a difference between the maximum value and the minimum value with respect to the maximum value. The determination unit184then determines whether the calculated difference rate is below a previously set threshold value. If the calculated difference rate is below the threshold value, the determination unit184makes a determination that in-surface uniformity of the etching processing is normal. If, however, the calculated difference rate is equal to or larger than the threshold value, the determination unit184makes a determination that the in-surface uniformity of the etching processing is abnormal. As stated above, the determination unit184is capable of determining, for each wafer W, whether the result of the etching processing upon the wafer W is good or bad, based on the temperature distribution information194of the corresponding wafer W. Moreover, the determination unit184may determine presence or absence of a difference in the etching processing between the wafers W. For example,FIG.10shows an example result of an etching average value and etching uniformity for each of four wafers W with wafer IDs of ‘W1,’ ‘W2,’ ‘W3,’ and ‘W4.’ InFIG.10, the etching average value is the above-described average value of the etching rates, and the etching uniformity is the above-described difference rate of the etching rates. The etching average values and the etching uniformity of the four wafers W shown inFIG.10are all values regarded as being normal. As depicted inFIG.10, the etching average value and the etching uniformity of the wafer W with the wafer ID of ‘W4’ are different from those of the other three wafers W. In such a case, the determination unit184makes a determination that there is generated a difference in the etching processing (etching average value and etching uniformity) of the wafer W with the wafer ID of ‘W4’ with respect to the other wafers W. As an example, the determination unit184accumulates information upon the etching average values and the etching uniformity of wafers W processed in the past, and calculates, from the accumulated information, reference values (for example, average values) for the etching average values and the etching uniformity. Then, the determination unit184calculates, for each wafer W, a difference in the etching average value and a difference in the etching uniformity of this wafer W from the reference values. If any of the calculated difference exceeds a previously set threshold value, the determination unit184makes a determination that there is generated the difference between the wafers W. Furthermore, the determination unit184may also determine presence or absence of the difference in the etching processing between the processing units16. For example,FIG.11shows an average value of the etching average values and an average value of the etching uniformity of a multiple number of wafers W processed in each of four processing units16with unit IDs of ‘U1,’ ‘U2,’ ‘U3,’ and ‘U4.’ Below, the average value of the etching average values and the average value of the etching uniformity of the multiple number of wafers W processed in any of the processing units16will be referred to as an etching average value and etching uniformity of the corresponding processing unit16. As depicted inFIG.11, the etching average value and the etching uniformity of the processing unit16with the unit ID of ‘U4’ are different from those of the other three processing units16. In such a case, the determination unit184makes a determination that there is generated a difference in the etching average value and the etching uniformity of the processing unit16with the unit ID of ‘U4’ with respect to the other processing units16. As an example, the determination unit184accumulates, for each processing unit16, information upon the etching average values and the etching uniformity of the wafers W processed in the past, and calculates, for each processing unit16, an average value of the etching average values and an average value of the etching uniformity from the accumulated information. Further, the determination unit184acquires a reference value for the etching average values and a reference value for the etching uniformity by calculating average values of the calculated average values for the respective processing units16. Then, the determination unit184calculates, for each processing unit16, a difference of the etching average value from the corresponding reference value and a difference of the etching uniformity from the corresponding reference value. If any of the calculated differences exceeds a previously set threshold value, the determination unit184makes a determination that there is generated a difference between the processing units16. In addition, the determination unit184may also determine presence or absence of the difference in the etching processing between the lots. For example,FIG.12shows average values of the etching average values and the etching uniformity of a multiple number of wafers W belonging to each of four lots with lot IDs of ‘L1,’ ‘L2,’ ‘L3,’ and ‘L4.’ Below, the average values of the etching average values and the etching uniformity of the multiple number of wafers W included in any of the lots will be referred to as an etching average value and etching uniformity of the corresponding lot. As depicted inFIG.12, the etching average value and the etching uniformity of the lot with the lot ID of ‘L4’ are different from those of the other three lots. In such a case, the determination unit184makes a determination that there is generated a difference in the etching average value and the etching uniformity in the lot with the lot ID of ‘L4’ with respect to the other lots. As an example, the determination unit184accumulates, for each lot, information upon etching average values and the etching uniformity of the multiple number wafers W included in the corresponding lot, and calculates, for each lot, an average value of the etching average values and an average value of the etching uniformity from the accumulated information. Further, the determination unit184acquires a reference value for the etching average values and a reference value for the etching uniformity by calculating average values of the calculated average values for the respective lots. Then, the determination unit184calculates, for each lot, a difference of the etching average value from the corresponding reference value and a difference of the etching uniformity from the corresponding reference value. If any of the calculated difference exceeds a previously set threshold value, the determination unit184makes a determination that there is generated a difference between the lots. Additionally, the determination unit184also determines whether the result of the drying processing is good or bad. To elaborate, based on the temperature distribution information194, the determination unit184determines presence or absence of condensation on the wafer W in the drying processing. This will be elaborated later. The abnormality handling unit185performs a preset abnormality handling processing when abnormality of the liquid processing is determined by the determination unit184. By way of example, the abnormality handling unit185may perform a processing of changing the processing condition for the liquid processing as the abnormality handling processing. Here, the designation information195specifying changeable processing conditions is stored in the storage19. The designation information195may be appropriately altered by, for example, a user of the substrate processing system1. The abnormality handling unit185may change the processing conditions designated by the designation information195such that results of subsequent liquid processings fall within a normal range. By way of example, assume that there is generated, in one of the processing units16, the difference between the processing units16. In such a case, the abnormality handling unit185may change the discharge temperature of the etching liquid in the corresponding processing unit16having the difference. This may be accomplished by, for example, changing parameter values designating the heating temperature by the temperature adjuster46a. To elaborate, the abnormality handling unit185adjusts the discharge temperature of the etching liquid by the temperature adjuster46aindividually such that the difference of the corresponding processing unit16in the etching average value and the etching uniformity from the reference values fall within a normal range. Furthermore, the abnormality handling unit185may determine new parameter values designating the heating temperature by the temperature adjuster46aby performing an inverse operation, using the model expression193, for example. Further, the abnormality handling unit185may vary the discharge temperature of the etching liquid by changing parameter values designating the heating temperature of the etching liquid by the heater82of the chemical liquid supply unit70. By way of example, assume that it is determined that a certain wafer W has the abnormality in the etching average value or the etching uniformity. In this case, the abnormality handling unit185may control the chemical liquid supply unit70to change the discharge temperature of the etching liquid onto a wafer W to be subjected to subsequent liquid processings. Furthermore, the abnormality handling unit185may vary the in-surface temperature distribution of the wafer W in the liquid processing by changing the processing conditions such that the temperature control liquid is supplied from the rear surface supply60. This may be accomplished by changing, for example, a parameter value defining a heating temperature of the temperature control liquid by the temperature adjuster61d, a parameter value defining an opening/closing of the valve61c, a parameter value defining a heating temperature of the temperature control liquid by the temperature control liquid source61b, and so forth. Moreover, the abnormality handling unit185may vary the in-surface temperature distribution of the wafer W in the liquid processing by changing the temperature within the chamber20. This may be accomplished by changing a parameter value defining a heating temperature by the temperature adjuster21d, for example. Besides, when the abnormality of, for example, the etching average value is found, the abnormality handling unit185may change a parameter value defining a discharging time of the etching liquid such that the etching average value falls within a normal range. In addition, in the determination processing by the determination unit184, if it is determined that the condensation may have occurred in the drying processing, the abnormality handling unit185may change a dew point temperature by controlling the temperature adjuster21dto change the internal temperature of the chamber20. Further, the abnormality handling unit185may change the dew point temperature by controlling the humidity adjuster21eto change the humidity within the chamber20. Moreover, the abnormality handling unit185may change the temperature of the wafer W in the replacement processing by controlling at least one of the temperature adjuster46c, the replacement liquid supply unit90and the rear surface supply60. Besides, the abnormality handling unit185may perform, as the abnormality handling processing, a processing of outputting abnormality information to an external device5connected to the control device4through a network such as Internet. In the abnormality information, information indicating the content of abnormality is matched with the wafer ID or the like. <Sequence of Monitoring Processing> Now, a sequence of the monitoring processing performed by the controller18will be explained with reference toFIG.13.FIG.13is a flowchart showing the sequence of the monitoring processing according to the exemplary embodiment. As illustrated inFIG.13, the collecting unit182of the controller18collects multiple parameter values defining processing conditions for the liquid processing and sensor values of various sensors including the first temperature sensor110and the second temperature sensor120(process S101). Then, the monitoring unit183of the controller18generates the temperature distribution information194by using the collection information192and the model expression193(process S102). Then, the determination unit184of the controller18determines, based on the generated temperature distribution information194, whether the result of the liquid processing is normal (process S103). A specific example of this determination will be described later. If it is determined in the process S103that the result of the liquid processing is not normal, that is, the result of the liquid processing is abnormal (process S103, No), the abnormality handling unit185of the controller18performs the abnormality handling processing (process S104). If the processing of the process S104is completed or if it is determined in the process S103that the result of the liquid processing is normal (process S103, Yes), the controller18ends the monitoring processing. First Example of Determination Processing: Comparison of Temperature Distribution Information with Threshold Value FIG.14is a flowchart illustrating a first example of the determination processing of the process S103shown inFIG.13. As depicted inFIG.14, by comparing the temperature distribution information194with a previously set threshold value, the determination unit184of the controller18determines whether a temperature region below the threshold value exists (process S201). If there is no temperature region below the threshold value (process S201, No), the determination unit184makes a determination that the processing result of the liquid processing (for example, the etching processing) is normal (process S202). Meanwhile, if there exists the temperature region below the threshold value (process S201, Yes), the determination unit184makes a determination that the processing result of the liquid processing is abnormal (process S203). By way of example, if the previously set threshold value is 50° C., it is determined based on the temperature distribution information194whether there exists a region below 50° C. within the surface of the wafer W. If the region below 50° C. exists, the determination unit184makes a determination that the processing result of the liquid processing (for example, the etching processing) is abnormal. In this example, the determination processing is performed by using the lower-limit threshold value. However, the determination unit184may carry out the determination processing by using an upper-limit threshold value. Further, the determination unit184may perform the determination processing by using a threshold range having upper and lower limits. Second Example of Determination Processing: Comparison of Etching Rate Distribution Information with Threshold Value FIG.15is a flowchart illustrating a second example of the determination processing of the process S103shown inFIG.13. As depicted inFIG.15, the determination unit184converts the temperature distribution information194to the etching rate distribution information (process S301), and calculates an etching rate average value and an etching rate uniformity based on the etching rate distribution information (process S302). Then, the determination unit184determines whether the etching average value exceeds a threshold value (process S303), and if not (process S303, No), the determination unit184makes a determination that the result of the etching processing is abnormal (process S306). Meanwhile, if the etching average value is found in the process S303to exceed the threshold value (process S303, Yes), the determination unit184determines whether the etching uniformity falls below a threshold value (process S304). In this processing, if the etching uniformity is not below the threshold value (process S304, No), the determination unit184makes a determination that the result of the etching processing is abnormal (process S306). Meanwhile, if the etching uniformity is below the threshold value (process S303, Yes), the determination unit184makes a determination that the result of the etching processing is normal (process S305). Third Example of Determination Processing: Regarding Whether Result of Drying Processing is Good or Bad FIG.16is a flowchart illustrating a third example of the determination processing of the process S103shown inFIG.13. As depicted inFIG.16, the determination unit184first calculates a dew point temperature (process S401). For example, the determination unit184calculates the dew point temperature within the chamber20in the liquid processing by using the space temperature and the space humidity included in the collection information192. Then, by comparing the temperature distribution information194and the dew point temperature, the determination unit184determines whether a temperature region below the dew point temperature exists (process S402). If there exists no temperature region below the dew point temperature (process S401, No), the determination unit184makes a determination that the result of the drying processing is normal, that is, there is no possibility of the occurrence of the condensation on the wafer W during the drying processing (process S403). Meanwhile, if there is the temperature region below the dew point temperature (process S402, Yes), the determination unit184makes a determination that the result of the drying processing is abnormal, that is, the condensation may have occurred on the wafer W during the drying processing (process S404). Further, the determination unit184may not necessarily perform the processing of the process S401. For example, the determination unit184may make the determination of the process S402by using a previously set dew point temperature. Further, the temperature and the humidity used in the calculation of the dew point temperature need not necessarily be the temperature and the humidity within the chamber20, and they may be, for example, a temperature and a humidity within a factory in which the substrate processing system1is installed. As stated above, the substrate processing method according to the exemplary embodiment includes a process of performing a liquid processing, a detecting process, a generating process, and a determining process. In the process of performing the liquid processing, the liquid processing is performed on a substrate (for example, a wafer W), using a processing unit (for example, the processing unit16) equipped with a substrate holding mechanism (for example, the substrate holding mechanism30) configured to hold the substrate horizontally and a processing liquid supply (for example, the processing liquid supply40) configured to supply a processing liquid (for example, the etching liquid, the rinse liquid, or the replacement liquid) onto the substrate held by the substrate holding mechanism. In the detecting process, a temperature of a central portion of the substrate and a temperature of an edge portion of the substrate in the liquid processing are respectively detected by using a plurality of sensors (for example, the first temperature sensor110, the second temperature sensor120, etc.) provided in the processing unit. In the generating process, temperature distribution information (for example, the temperature distribution information194) indicating an in-surface temperature distribution of the substrate in the liquid processing is generated based on one or more parameter values defining a processing condition for the liquid processing and the temperatures of the central portion and the edge portion of the substrate detected in the detecting process. In the determining process, based on the temperature distribution information, it is determined whether a result of the liquid processing is good or bad. Thus, according to the substrate processing method of the exemplary embodiment, it is possible to investigate appropriately, for each product wafer, whether a result of a liquid processing upon the product substrate is good or bad. The processing liquid supply includes a nozzle (for example, the nozzle41) configured to discharge the processing liquid; and a supply line (for example, the supply lines44ato44c) connected to the nozzle to supply the processing liquid to the nozzle. Further, in the process of performing the liquid processing, the processing liquid is discharged toward the central portion of the substrate from the nozzle. Further, in the detecting process, a temperature detected by a temperature sensor (for example, the first temperature sensor110) provided in the nozzle or the supply line is detected as a temperature of the central portion of the substrate. Accordingly, the temperature of the central portion of the substrate can be easily investigated. The substrate holding mechanism includes a plurality of grippers (for example, the grippers31a) each configured to hold an edge portion of the substrate. Further, in the detecting process, a temperature detected by a temperature sensor (for example, the second temperature sensor120) provided in at least one of the plurality of grippers is detected as a temperature of the edge portion of the substrate. Accordingly, the temperature of the edge portion of the substrate can be easily investigated. The one or more parameter values include at least one of a space temperature within the processing unit, a space humidity within the processing unit, a discharge flow rate of the processing liquid, or a rotation number of the substrate. Accordingly, accuracy of the temperature distribution information can be improved. In the determining process, presence or absence of a difference in a result of the liquid processing between a plurality of substrates (for example, a difference between wafers W) is detected for each substrate based on multiple temperature distribution information generated by the generating process. Accordingly, presence or absence of the difference between the wafers can be monitored easily. In the process of performing the liquid processing, the liquid processing upon the plurality of substrates is performed by using a plurality of processing units. Further, in the determining process, presence or absence of a difference in the result of the liquid processing between the plurality of processing units (for example, a difference between the processing units16) is determined for each processing unit based on the multiple temperature distribution information generated by the generating process. Accordingly, presence or absence of the difference between the processing units can be monitored easily. In the determining process, presence or absence of a difference in the result of the liquid processing between a plurality of lots (for example, a different between the lots) is determined for each lot as a manufacturing unit of substrates based on the multiple temperature distribution information generated by the generating process. Accordingly, presence or absence of the difference between the lots can be easily monitored. The substrate processing method according to the exemplary embodiment includes a process of acquiring a dew point temperature within the processing unit. Further, in the determining process, presence or absence of condensation on the substrate in the liquid processing (for example, the drying processing) is detected based on the temperature distribution information and the dew point temperature. Accordingly, it is possible to easily specify a substrate on which a watermark is likely to be formed. The substrate processing method according to the exemplary embodiment includes a process of correcting a temperature of the processing liquid discharged from the processing liquid supply by controlling a temperature adjuster (for example, the temperature adjusters46aand46c) provided in the supply line based on the temperature distribution information. Accordingly, it is possible to reduce the number of substrates determined to be abnormal in the result of the liquid processing. The substrate processing method according to the exemplary embodiment includes a process of correcting at least one of the one or more parameter values based on the temperature distribution information. Accordingly, it is possible to reduce the number of substrates determined to be abnormal in the result of the liquid processing. It should be noted that the above-described exemplary embodiment is illustrative in all aspects and is not anyway limiting. The above-described exemplary embodiment may be omitted, replaced and modified in various ways without departing from the scope and the spirit of claims. According to the exemplary embodiment, it is possible to appropriately investigate, for every product substrate, whether the result of the liquid processing upon the product substrate is good or bad. From the foregoing, it will be appreciated that various embodiments of the present disclosure have been described herein for purposes of illustration, and that various modifications may be made without departing from the scope and spirit of the present disclosure. Accordingly, the various embodiments disclosed herein are not intended to be limiting. The scope of the inventive concept is defined by the following claims and their equivalents rather than by the detailed description of the exemplary embodiments. It shall be understood that all modifications and embodiments conceived from the meaning and scope of the claims and their equivalents are included in the scope of the inventive concept. | 71,485 |
11862484 | DETAILED DESCRIPTION Embodiments will now be explained with reference to the accompanying drawings. The present invention is not limited to the embodiments. A semiconductor manufacturing apparatus according to the present embodiment comprises a chamber. A chemical-agent supply part is configured to supply a water-repellent agent or an organic solvent to a surface of a semiconductor substrate having been cleaned with a cleaning liquid in the chamber. A spray part is configured to spray a water-capture agent capturing water into an atmosphere in the chamber. First Embodiment FIG.1shows an example of a configuration of a surface treatment apparatus10for a semiconductor substrate according to a first embodiment. The surface treatment apparatus10includes a mounting unit100on which a semiconductor substrate (a wafer) W is mounted, a liquid supply unit200that supplies liquids, a chamber300that hermetically seals the semiconductor substrate W, and a spray unit400that sprays a water-capture agent2. The mounting unit100includes a rotary shaft102, a spin base103, and chuck pins104. The rotary shaft102extends substantially in a vertical direction and the disk-like spin base103is attached on an upper end of the rotary shaft102. A motor (not shown) can rotate the rotary shaft102and the spin base103. The chuck pins104are provided on peripheral edges of the spin base103, respectively. The chuck pins104fix the semiconductor substrate W on the spin base103by putting the semiconductor substrate W between the chuck pins104. The mounting unit100can rotate the semiconductor substrate W while keeping the semiconductor substrate W substantially horizontally. The liquid supply unit200discharges a liquid1to a surface of the semiconductor substrate W near a rotation center thereof. By allowing the mounting unit100to rotate the semiconductor substrate W, the discharged liquid1can spread in a radial direction of the semiconductor substrate W and can be applied on the surface of the semiconductor substrate W. Furthermore, by allowing the mounting unit100to rotate the semiconductor substrate W, the liquid1on the semiconductor substrate W can be drained off and the semiconductor substrate W can be spin-dried. The excessive liquid1spattering in the radial direction of the semiconductor substrate W is discharged via a waste liquid pipe105. For example, the liquid1is a cleaning liquid, a water-repellent agent, DIW (deionized water) or an organic solvent. The liquid supply unit200includes a first chemical-liquid supply unit210that supplies the cleaning liquid for cleaning the semiconductor substrate W to the surface of the semiconductor substrate W, a second chemical-liquid supply unit220serving as a chemical-agent supply unit that supplies the water-repellent agent for forming a water-repellent protection film to the surface of the semiconductor substrate W, and a DIW supply unit230that supplies the DIW to the surface of the semiconductor substrate W. The cleaning liquid supplied from the first chemical-liquid supply unit210passes through a supply pipe212and is discharged from a nozzle211. For example, the cleaning liquid is an SC1 liquid (Ammonia-Hydrogen Peroxide mixture) or an SPM liquid (Sulfuric acid-Hydrogen Peroxide Mixture) and is a chemical liquid used for removing etching residues and the like. The water-repellent agent supplied from the second chemical-liquid supply unit220passes through a supply pipe222and is discharged from a nozzle221. The water-repellent agent is a chemical liquid for forming the water-repellent protection film on surfaces of patterns formed on the semiconductor substrate W and making the surfaces of the patterns water repellent. For example, the water-repellent agent is a silane coupling agent. The silane coupling agent contains hydrolytic groups having an affinity and a reactivity to inorganic materials and organic functional groups chemically bonding organic materials in molecules. Examples of the silane coupling agent include hexamethyldisilazane (HMDS), tetramethylsilyldimethylamine (TMSDMA), and trimethylsilyldimethylamine (TMSDEA). The DIW supplied from the DIW supply unit230passes through a supply pipe232and is discharged from a nozzle231. The DIW is used to rinse away a chemical liquid on the semiconductor substrate W. The spray unit400sprays the water-capture agent2into the chamber300so as to capture water contained in an atmosphere in the chamber300. Although not limited to a specific one, the water-capture agent2suffices to be a chemical agent that easily reacts to the water and that does not react to the chamber300, the semiconductor substrate W, and the water-repellent agent. For example, the silane coupling agent serving as the water-repellent agent can be used as the water-capture agent2. Examples of the silane coupling agent include HMDS, TMSDMA, and TMSDEA mentioned above. A material same as that of the water-repellent agent can be used as that of the water-capture agent2. However, when any one of HMDS, TMSDMA, and TMSDEA is used as the water-repellent agent, any of HMDS, TMSDMA, and TMSDEA can be used as the water-capture agent2. In this case, a different material from that of the water-repellent agent can be used as the material of the water-capture agent2. The spray unit400evaporates the water-repellent agent2and sprays the evaporated water-repellent agent2into the chamber300. The water-repellent agent2thereby reacts to the water in the atmosphere in the chamber300and captures the water. In other words, the water-capture agent2absorbs the water in the chamber300. The spray unit400sprays the evaporated water-capture agent2into the atmosphere in the chamber300either simultaneously with or before a timing at which the second chemical-liquid supply unit220supplies the water-repellent agent to the surface of the semiconductor substrate W. The spray unit400can continue spraying the water-repellent agent2into the chamber300in parallel to the supply of the water-repellent agent while the second chemical-liquid supply unit220is supplying the water-repellent agent. The water-capture agent2can thereby sufficiently capture the water in the chamber300before the water-repellent agent is supplied to the semiconductor substrate W. Therefore, it is possible to suppress the water-repellent agent from reacting to the water in the atmosphere in the chamber300and being deactivated. The spray unit400can spray the water-capture agent2continuously, instantaneously or intermittently. The surface treatment apparatus10can include a vacuum device (not shown) that evacuates the air from the interior of the chamber300. In this case, the vacuum device discharges the water in the chamber300to outside to some extent and the spray unit400sprays the water-repellent agent into the chamber300in a vacuum. It is thereby possible to remove the water in the chamber300more efficiently. Furthermore, the surface treatment apparatus10can include an excimer UV (ultraviolet) irradiation unit (not shown). The excimer UV irradiation unit can selectively remove the water-repellent protection film by irradiating UV light on the semiconductor substrate W. FIG.2shows a contact angle θ of a liquid on patterns4on the semiconductor substrate W. When an aspect ratio of the patterns4becomes higher by downscaling the patterns4, a liquid5enters between adjacent patterns4by the capillary of the liquid5. In this case, power P with which the liquid5acts on the patterns4is represented by the following Equation (1). P=2×γ×cos θ·HSPACE (1) In this equation, SPACE denotes a space between adjacent patterns4. H denotes the height of each pattern4. γ denotes the surface tension of the liquid5. It is understood that as the contact angle θ is closer to 90°, then cos θ becomes closer to zero and the power P acting on the patterns4becomes lower. The fact that the contact angle θ is closer to 90° means that the surface of the semiconductor substrate W (the surface of each pattern4) is made water repellent. Therefore, pattern collapsing can be suppressed by making the surface of the semiconductor substrate W water repellent. To make the surface of the semiconductor substrate W water repellent, the water-repellent protection film is formed on the surface of the semiconductor substrate W using the water-repellent agent such as the silane coupling agent (a sililation treatment). However, when the water is present in the chamber300, the silane coupling agent has a hydrolytic reaction to the water in the chamber300and loses a water-repellent function. That is, the silane coupling agent is deactivated. For example, when the silane coupling agent is supplied to the rotation center of the semiconductor substrate W shown inFIG.1, it is likely that the silane coupling agent reacts to the water and is deactivated before the silane coupling agent spreads through peripheral edges of the semiconductor substrate W. In this case, the water-repellent protection film is formed on the patterns4near a central portion of the semiconductor substrate W but not on the patterns4near the peripheral edges of the semiconductor substrate W. On the other hand, according to the first embodiment, the spray unit400sprays the evaporated water-capture agent2into the chamber300at or before a time of supplying the water-repellent agent. Because the water-capture agent2reacts to the water in the chamber300, a water amount in the chamber300greatly decreases at the time of supplying the water-repellent agent. This can suppress deactivation of the water-repellent agent. As a result, it is possible to ensure making the surface of the semiconductor substrate W and the surfaces of the patterns4water repellent, to make the contact angle θ closer to 90°, and to suppress collapsing of the patterns4on the semiconductor substrate W. FIGS.3A to3Dare cross-sectional views showing a manufacturing method of a NAND flash memory according to the first embodiment.FIG.4is a flowchart showing a surface treatment method according to the first embodiment. The surface treatment method according to the first embodiment is applied to, for example, processes of cleaning and drying the semiconductor substrate W in processing of charge accumulation layers CA (floating gates, for example) of the NAND flash memory. Although a sidewall transfer process is often used to process the charge accumulation layers CA, an ordinary resist transfer process is used here for the brevity of descriptions. Needless to mention, the first embodiment is also applicable to cleaning and drying processes in the sidewall transfer process. First, a gate dielectric film20is formed on the semiconductor substrate W. The gate dielectric film20is formed by thermally oxidizing the semiconductor substrate W. The thickness of the gate dielectric film20is about 5 nm, for example. Next, a polysilicon layer30is formed on the gate dielectric film20. The polysilicon layer30is used as the material of the charge accumulation layers CA. The thickness of the polysilicon layer30is about 100 nm, for example. Next, a silicon nitride film40is formed on the polysilicon layer30. The silicon nitride film40functions as an etching stopper. The thickness of the silicon nitride film40is about 100 nm, for example. Next, a silicon oxide film50is formed on the silicon nitride film40. The silicon oxide film50is used as hard masks HM for processing the polysilicon layer30(the charge accumulation layers CA) or the like. The thickness of the silicon oxide film50is 250 nm, for example. Next, a sacrificial film60is formed on the silicon oxide film50. It suffices that the sacrificial film60is made of a material that can selectively etch the silicon oxide film50. For example, a silicon nitride film, a polysilicon film or the like can be used as the sacrificial film60. The thickness of the sacrificial film60is 100 nm, for example. Next, using a lithographic technique, a resist layer70is formed on the sacrificial film60. The resist layer70is patterned to process the sacrificial film60into patterns of the charge accumulation layers CA. For example, the resist layer70is formed into line-and-space patterns. The line width and space width of the resist layer70are both about 20 nm, for example. The structure shown inFIG.3Ais obtained in this manner. Next, using the resist layer70as a mask, the sacrificial film60is processed by a RIE (Reactive Ion Etching) method. After removing the resist layer70using, for example, a SPM liquid (Sulfuric acid-Hydrogen Peroxide Mixture), the silicon oxide film50is processed by the RIE method with the sacrificial film60used as a mask. Etching of the silicon oxide film50stops on the silicon nitride film40. The structure of the hard masks HM is thereby obtained as shown inFIG.3B. At this time, an aspect ratio of each hard mask HM is about 10. The sacrificial film60can be removed at the time of etching the silicon oxide film50. When the sidewall transfer process is used, the sacrificial film60is used as a core of sidewall masks (not shown). For example, after narrowing the width of the sacrificial film60by slimming, a sidewall film (not shown) is deposited on the sacrificial film60. Thereafter, the sidewall film is etched back, thereby leaving the sidewall film on both side surfaces of the sacrificial film60as the sidewall masks. The sidewall masks are formed by removing the sacrificial film60. When the silicon oxide film50is etched using the sidewall masks as a mask, it is possible to form the hard masks HM each having a smaller line width and a smaller space width than those of a minimum feature size F (Feature size) that can be formed by the lithographic technique. In this way, the hard masks HM can be alternatively processed using the sidewall transfer process. Needless to mention, the hard masks HM can be processed into smaller patterns by repeating the sidewall transfer process. Next, the semiconductor substrate W is cleaned so as to remove etching residues generated in the etching of the silicon oxide film50. For example, the semiconductor substrate W is subjected to a cleaning treatment using the SPM liquid or the SC1 liquid. After the cleaning treatment, the chemical liquid is rinsed away with the DIW. At this time, the DIW enters between the adjacent hard masks HM. When the surface of the semiconductor substrate W is dried in a state where the DIW is present between the hard masks HM, the capillary or surface tension (the power P represented by the Equation (1) mentioned above) of the DIW possibly causes collapsing of the hard masks HM. To prevent this possibility, the surface treatment apparatus10according to the first embodiment forms a water-repellent protection film R on the surface of the semiconductor substrate W and those of the patterns after the cleaning treatment. A method of forming the water-repellent protection film R is described below with reference toFIG.4. FIG.4is a flowchart showing the surface treatment method according to the first embodiment. As shown inFIG.4, after mounting the semiconductor substrate W on the mounting unit100(S10), the mounting unit100rotates the semiconductor substrate W. The first chemical-liquid supply unit210supplies the cleaning liquid for cleaning the semiconductor substrate W to the surface of the semiconductor substrate W arranged in the chamber300. The cleaning liquid spreads throughout the surface of the semiconductor substrate W by rotation of the semiconductor substrate W. The etching residues are thereby removed (S20: cleaning treatment). After cleaning the semiconductor substrate W, the DIW supply unit230supplies the DIW to the semiconductor substrate W. The DIW spreads throughout the surface of the semiconductor substrate W by the rotation of the semiconductor substrate W. The cleaning liquid on the surface of the semiconductor substrate W is thereby rinsed away with the DIW (S30: DIW rinse treatment). Next, the spray unit400evaporates the water-capture agent2and sprays the evaporated water-capture agent2into the chamber300. The water-capture agent2thereby captures the water in the atmosphere in the chamber300(S40: water capture treatment). For example, HMDS serving as the silane coupling agent can be used as the water-capture agent2. In this case, HMDS reacts to the water and changes to silanol. Furthermore, the bimolecular silanol is condensed into inactive siloxane. In this way, because the water-capture agent2reacts to the water and changes to the inactive substance, the water in the chamber300can be reduced. Simultaneously with or after spraying of the water-capture agent2, the second chemical-liquid supply unit220supplies the water-repellent agent to the surface of the semiconductor substrate W (S50: sililation treatment). The water-repellent agent spreads throughout the surface of the semiconductor substrate W by the rotation of the semiconductor substrate W. For example, the water-repellent agent is TMSDMA serving as the silane coupling agent. At this time, the water-repellent agent can spread throughout the surface of the semiconductor substrate W without being deactivated because the water is hardly present in the chamber300. The water-repellent protection film R is thereby formed on the entire surfaces of the patterns on the semiconductor substrate W. When the patterns on the semiconductor substrate W are formed of a silicon-based film such as the silicon nitride film or the polysilicon film, sufficient water repellency is not often ensured because of an insufficient sililation reaction even after the sililation treatment using the silane coupling agent. In this case, before Step S50, the surfaces of the silicon-based patterns are changed to silicon oxide-based chemical oxide films using another chemical liquid. When the sililation treatment is subsequently performed, it is possible to improve water repellency after the sililation treatment. Many residues are generated after the etching by the RIE method. It is difficult to form the water-repellent protection film in a state where many residues remain. Therefore, it is effective to remove the residues by the cleaning treatment so as to form the water-repellent protection film. In addition, plasma damages are accumulated on the surfaces of the patterns by the RIE method and dangling bonds are generated. When a reforming treatment is performed using a cleaning liquid having an oxidation effect, the dangling bonds terminate at OH groups. If many OH groups are present, the sililation reaction probability increases, which facilitates forming the water-repellent protection film. This can further improve the water repellency. Even when the patterns are formed of the silicon oxide film, identical effects can be obtained. When the cleaning liquid has also a reforming effect (an oxidation effect), it is possible to simultaneously perform the cleaning treatment and the reforming treatment using the single cleaning liquid. Next, the DIW supply unit230supplies the DIW on the semiconductor substrate W and rinses again the surface of the semiconductor substrate W (S60: DIW rinse treatment). The DIW spreads throughout the surface of the semiconductor substrate W by the rotation of the semiconductor substrate W. The mounting unit100accelerates a rotational speed for rotating the semiconductor substrate W to a predetermined speed, thereby draining off and drying the DIW on the surface of the semiconductor substrate W (S70: spin drying treatment). At this time, the DIW can be easily removed from the semiconductor substrate W because surfaces of the hard masks HM are already in a water repellent state. Furthermore, even if the DIW is present between the adjacent hard masks HM, the capillary or surface tension of the DIW is very low because the surfaces of the hard masks HM are already in the water repellent state. Therefore, it is difficult for the hard masks HM to collapse. Next, using the hard masks HM as a mask, the polysilicon layer30, the gate dielectric film20, and the semiconductor substrate W are processed by the RIE method. The structure shown inFIG.3Dis thereby obtained. Thereafter, STI (Shallow Trench Isolation), IPD (Inter Poly Dielectric), control gates, and the like are formed using well-known processes, thereby completing the NAND flash memory. As described above, according to the first embodiment, the water-capture agent2is sprayed into the atmosphere in the chamber300either simultaneously with or before the timing of supplying the water-repellent agent to the surface of the semiconductor substrate W. The water-capture agent2thereby captures the water in the chamber300before the water-repellent agent is supplied to the semiconductor substrate W. Therefore, it is possible to suppress the water-repellent agent from reacting to the water in the atmosphere in the chamber300and being deactivated. As a result, according to the first embodiment, it is possible to ensure making the surface of the semiconductor substrate W water repellent and to suppress collapsing of the patterns on the semiconductor substrate W. Second Embodiment The surface treatment apparatus10and a surface treatment method according to a second embodiment differ from those according to the first embodiment in the use of an organic solvent in place of the water-repellent agent. Therefore, the second chemical-liquid supply unit220shown inFIG.1supplies not the water-repellent agent but the organic solvent to the semiconductor substrate W. In this case, it is unnecessary to perform the DIW rinse treatment in Step S60shown inFIG.4. Other configurations and processes of the second embodiment can be identical to those of the first embodiment. Because configurations of the surface treatment apparatus according to the second embodiment are basically identical to those of the surface treatment apparatus10according to the first embodiment shown inFIG.1, detailed explanations thereof will be omitted. In the second embodiment, the organic solvent is IPA, for example. The water-repellent agent can be used as the water-capture agent2similarly to the water-capture agent2in the first embodiment. The organic solvent is used in place of the water-repellent agent. This is because most of organic solvents have properties of low surface tension and high volatility. Because of the low surface tension, it is possible to suppress collapsing of the patterns on the semiconductor substrate W as described above. Because of the high volatility, the drying treatment can be performed swiftly and easily. Therefore, the liquid supplied from the second chemical-liquid supply unit220suffices to be a liquid low in surface tension without being specifically limited to the organic solvent. The liquid having the high volatility as well as the low surface tension is preferable because the high volatility is advantageous in the drying treatment. The spray unit400sprays the water-capture agent2into the atmosphere in the chamber300either simultaneously with or before a timing at which the second chemical-liquid supply unit220supplies the organic solvent to the surface of the semiconductor substrate W. The spray unit400can continue spraying the water-repellent agent2into the chamber300in parallel to the supply of the organic solvent while the second chemical-liquid supply unit220is supplying the organic solvent. The water-capture agent2can thereby capture the water in the chamber300before the organic solvent is supplied to the semiconductor substrate W. Therefore, the organic solvent is suppressed from absorbing the water in the atmosphere in the chamber300and the organic solvent displaces the water present on the surfaces of the patterns on the semiconductor substrate W. The spray unit400can spray the water-capture agent2continuously, instantaneously or intermittently. FIG.5is a flowchart showing the surface treatment method according to the second embodiment. Because Steps S10to S40inFIG.5are identical to Steps S10to S40inFIG.4, detailed explanations thereof will be omitted. Simultaneously with or after spraying of the water-capture agent2, the second chemical-liquid supply unit220supplies the organic solvent (IPA, for example) to the surface of the semiconductor substrate W (S51). At this time, the organic solvent spreads throughout the surface of the semiconductor substrate W without absorbing the water because the water is hardly present in the chamber300. The organic solvent thereby displaces the water present on the surfaces of the patterns on the semiconductor substrate W. Therefore, it is possible to suppress watermarks from being formed on the surface of the semiconductor substrate W at the time of an IPA drying treatment. Thereafter, the semiconductor substrate W is dried by the spin drying treatment. Step S70shown inFIG.5is the same as Step S70shown inFIG.4. Generally, when the IPA that is the organic solvent is used in the cleaning process, the IPA displaces the DIW on the semiconductor substrate W and dries the surface of the semiconductor substrate W (the IPA drying treatment). However, if much water is contained in the atmosphere in the chamber300, there is a probability that the IPA absorbs the water at the time of the IPD drying treatment and that watermarks are formed on the surface of the semiconductor substrate W when the surface is dried. According to the second embodiment, the water-capture agent2is sprayed into the atmosphere in the chamber300either simultaneously with or before the timing of supplying the organic solvent to the surface of the semiconductor substrate W. The water-capture agent2can thereby capture the water in the chamber300before the organic solvent is supplied to the semiconductor substrate W. Therefore, the organic solvent can displace the water on the surface of the semiconductor substrate W and those of the patterns without absorbing the water in the chamber300. If the IPA displaces the water on the surface of the semiconductor substrate W and those of the patterns, then wettability of the liquid5on the surface of the semiconductor substrate W improves and cos θ in the Equation (1) becomes larger, but γ in the Equation (1) becomes smaller. The power P thereby becomes lower as a whole. As a result, it is possible to suppress collapsing of the patterns on the semiconductor substrate W and to suppress the watermarks from being formed on the semiconductor substrate W. The first and second embodiments are not limited to the patterns of the hard masks HM described above but applicable to arbitrary patterns having a high aspect ratio. Furthermore, the first and second embodiments are not limited to the patterns of the hard masks HM in the process of cleaning the semiconductor substrate W but applicable to resist patterns after development in a lithographic process. Furthermore, while the spray unit400shown inFIG.1can be arranged in an upper portion of the chamber300in the first embodiment, the spray unit400can be formed integrally with the second chemical-liquid supply unit220. When the material of the water-capture agent2is the same as that of the water-repellent agent, a common pipe to the spray unit400and the second chemical-liquid supply unit220can be used by forming the spray unit400and the second chemical-liquid supply unit220integrally. This makes it relatively easier to pull out the pipe. The first and second embodiments can be combined. In this case, the surface treatment apparatus10includes both a water-repellent-agent supply unit that supplies the water-repellent agent and an IPA supply unit that supplies the IPA. For example, after cleaning the semiconductor substrate W, the surface treatment apparatus10rinses the cleaning liquid with the DIW and supplies the IPA to the semiconductor substrate W by the method according to the second embodiment. The IPA thereby displaces the water on the semiconductor substrate W. The surface treatment apparatus10supplies the water-repellent agent to the semiconductor substrate W by the method according to the first embodiment. The water-repellent protection film is thereby formed on the surface of the semiconductor substrate W (the surface of each pattern). The surface treatment apparatus10supplies the IPA again to the semiconductor substrate W by the method according to the second embodiment. The IPA thereby displaces the water-repellent agent. Furthermore, the water treatment apparatus10supplies the DIW again to the semiconductor substrate W. The DIW thereby displaces the IPA. Thereafter, the water treatment apparatus10dries the semiconductor substrate W by spinning the semiconductor substrate W. At this time, the semiconductor substrate W can be dried without collapsing of the patterns on the semiconductor substrate W because the surfaces of the patterns on the semiconductor substrate W are in a water repellent state. Third Embodiment FIGS.6A and6Bshow an example of a configuration of a surface treatment apparatus30for semiconductor substrates according to a third embodiment. In the first and second embodiments, the surface treatment apparatus10is a single-wafer surface treatment apparatus for processing semiconductor substrates W one by one. On the other hand, the surface treatment apparatus30according to the third embodiment is a batch surface treatment apparatus for batch-processing a plurality of semiconductor substrates W. Therefore, the chamber300accommodates a plurality of semiconductor substrates W (semiconductor substrates W corresponding to two lots, for example) at a time. The interior of the chamber300can be kept in a vacuum when processing the semiconductor substrates W. The chemical-liquid supply unit220sprays an evaporated organic solvent (IPA, for example)3into the chamber300so as to supply the organic solvent3to the semiconductor substrates W. The organic solvent3, which is evaporated, can spread through surfaces of the semiconductor substrates W. The spray unit400sprays the evaporated water-capture agent2into the chamber300. The water-capture agent2, which is evaporated similarly, can spread through the surfaces of the semiconductor substrates W. Forms of the chemical-liquid supply unit220and the spray unit400are not limited to specific ones, so that either nozzle-like units shown inFIGS.6A and6Bor the box-like units shown inFIG.1can be used as the chemical-liquid supply unit220and the spray unit400. For example, the IPA can be used as the organic solvent3similarly to the organic solvent in the second embodiment. Any of the water-repellent agents can be used as the water-capture agent2similarly to the water-capture agent2in the first embodiment. A DIW reservoir500is a reservoir that stores therein the DIW and in which a batch of semiconductor substrates W can be immersed in the DIW. The DIW in the DIW reservoir500is circulated, filtered so as to keep a lightly doped state after use, and reused. FIG.7is a flowchart showing a surface treatment method according to the third embodiment. The surface treatment method according to the third embodiment is described with reference toFIGS.6A,6B, and7. First, the semiconductor substrates W are subjected to the cleaning treatment using the cleaning liquid (S22). The cleaning treatment can be performed either outside or inside of the chamber300. In the third embodiment, it is assumed that the semiconductor substrates W are cleaned outside of the chamber300and that the semiconductor substrates W are arranged in the chamber300after the cleaning liquid is rinsed away with the DIW. The cleaning treatment can be performed either on every semiconductor substrate W or collectively on a plurality of semiconductor substrates W as a batch process. When the cleaning treatment is performed as the batch process, it suffices to store the cleaning liquid in a reservoir (not shown) similar to the DIW reservoir500and to immerse the semiconductor substrates W in the reservoir. A case of performing the cleaning treatment inside of the chamber300is described later in a modification of the third embodiment. As described above, after the cleaning treatment, the cleaning liquid on the semiconductor substrates W is rinsed away with the DIW (S32). As shown inFIG.6A, the semiconductor substrates W are introduced into the chamber300in a vacuum, the semiconductor substrates W are immersed in the DIW reservoir500, and surfaces of the semiconductor substrates W are rinsed with the DIW (S42). Before or after arranging the semiconductor substrates W in the chamber300, the spray unit400evaporates the water-capture agent2and sprays the evaporated water-capture agent2into the chamber300. The water-capture agent2thereby captures the water in the atmosphere in the chamber300(S52). Simultaneously with or after spraying of the water-capture agent2, the chemical-liquid supply unit220supplies the evaporated organic solvent3to the surfaces of the semiconductor substrates W (S62). The organic solvent3can easily spread through the surfaces of the semiconductor substrates W because the organic solvent3is sprayed in an evaporated state. At this time, the organic solvent3can spread throughout the surfaces of the semiconductor substrates W without absorbing the water because the water is hardly present in the chamber300. The organic solvent (IPA, for example)3can thereby easily displace the water on the entire surfaces of the semiconductor substrates W when the chemical-liquid supply unit220supplies the organic solvent3. Next, the semiconductor substrates W are pulled out of the DIW reservoir500and dried (S72). At this time, the organic solvent3displaces the water on the surfaces of the hard masks HM. Therefore, it is easy to remove the DIW from the semiconductor substrates W and it is difficult for the patterns of the hard masks HM to collapse. It is also possible to suppress watermarks from being formed on the surfaces of the semiconductor substrates W. Other processes in the third embodiment can be performed similarly to the corresponding processes in the second embodiment. According to the third embodiment, it is thereby possible to perform the IPA drying treatment collectively on a batch of the semiconductor substrates W. The third embodiment can achieve effects identical to those of the second embodiment. MODIFICATION OF THIRD EMBODIMENT In the third embodiment, the cleaning treatment for cleaning the semiconductor substrates W (S22inFIG.7) and the DIW rinse treatment for rinsing away the cleaning liquid with the DIW (S32inFIG.7) are performed outside of the chamber300. In the modification of the third embodiment, the cleaning treatment for cleaning the semiconductor substrates W and the rinse treatment for rinsing away the cleaning liquid with the DIW are performed inside of the chamber300. In this case, it suffices to initially store the cleaning liquid in the treatment reservoir500and to replace the cleaning liquid in the treatment reservoir500with the DIW after performing the cleaning treatment. At this time, the semiconductor substrates W can be kept stored in the treatment reservoir500. Alternatively, the semiconductor substrates W can be temporarily pulled out of the treatment reservoir500and, after replacing the cleaning liquid in the treatment reservoir500with the DIW, the semiconductor substrates W can be stored again in the treatment reservoir500and the cleaning liquid on the semiconductor substrates W can be rinsed with the DIW. After rinsing the cleaning liquid with the DIW, the semiconductor substrates W are pulled out of the treatment reservoir500, and Steps S42to S72shown inFIG.7are performed. According to this modification, the cleaning treatment and the drying treatment can be performed for every batch of the semiconductor substrates W. This modification can also achieve effects identical to those of the third embodiment. While certain embodiments have been described, these embodiments have been presented by way of example only, and are not intended to limit the scope of the inventions. Indeed, the novel methods and systems described herein may be embodied in a variety of other forms; furthermore, various omissions, substitutions and changes in the form of the methods and systems described herein may be made without departing from the spirit of the inventions. The accompanying claims and their equivalents are intended to cover such forms or modifications as would fall within the scope and spirit of the inventions. | 36,488 |
11862485 | DETAILED DESCRIPTION In the following detailed description, reference is made to the accompanying drawings, which form a part of the description. In the drawings, similar symbols typically identify similar components, unless context dictates otherwise. Furthermore, unless otherwise noted, the description of each successive drawing may reference features from one or more of the previous drawings to provide clearer context and a more substantive explanation of the current exemplary embodiment. Still, the exemplary embodiments described in the detailed description, drawings, and claims are not meant to be limiting. Other embodiments may be utilized, and other changes may be made, without departing from the spirit or scope of the subject matter presented herein. It will be readily understood that the aspects of the present disclosure, as generally described herein and illustrated in the drawings, may be arranged, substituted, combined, separated, and designed in a wide variety of different configurations, all of which are explicitly contemplated herein. A manufacturing process for a semiconductor device or the like includes a processing of coating a resist liquid on a substrate to form a resist pattern. In this processing, while rotating a semiconductor wafer (hereinafter, simply referred to as “wafer”) held by, for example, a spin chuck, the resist liquid is discharged onto a substantially central portion to the wafer from a nozzle. The resist liquid includes a component of the resist film, made of an organic material, and a solvent for this component. If the resist liquid comes into contact with the atmosphere, it is highly likely to be dried, and, if the resist liquid is dried, a concentration of the resist liquid or the like may be changed. For the reason, there is adopted a method of suppressing the drying of the resist liquid within the nozzle by forming an air layer and a solvent layer (liquid layer of the solvent) at an outside of the resist liquid layer within a leading end portion of the nozzle when the nozzle is not being used. This method involves performing dummy dispensing of the resist liquid within the nozzle, forming the air layer by suctioning the inside of the nozzle, and suctioning the inside of the nozzle while immersing the leading end portion of the nozzle in the solvent. In this method, the resist liquid attached to an inner wall of the nozzle when the air layer is formed in the leading end portion of the nozzle may be collected to a discharge opening of the nozzle, forming a thin film of the resist liquid at the discharge opening of the nozzle. If the thin film of the resist liquid is formed at the discharge opening of the nozzle, the solvent may be easily introduced into the nozzle when it comes into contact with the thin film of the resist film as the leading end portion of the nozzle is immersed in the solvent. However, when using a high-viscosity resist liquid such as a resist thin film for a 3D NAND memory, the resist liquid attached to the inner wall of the nozzle is difficult to collect to the discharge opening of the nozzle. Therefore, the thin film of the resist liquid is difficult to form at the discharge opening of the nozzle, as compared to a case where the conventional low-viscosity resist liquid is used. As a result, even if the inside of the nozzle is suctioned while keeping the leading end portion of the nozzle immersed in the solvent, the solvent is difficult to introduce into the nozzle, since the thin film of the resist film is not formed at the discharge opening of the nozzle. That is, in the conventional nozzle standby device, it has been difficult to form a liquid layer of the solvent in the leading end portion of the nozzle when the resist liquid has high viscosity. In view of the foregoing, the present disclosure provides a technique enabling, in forming the liquid layer of the solvent by sucking the solvent into the leading end portion of the nozzle for discharging the processing liquid when the nozzle stands by in the nozzle accommodation unit, to form the liquid layer of the solvent in the leading end portion of the nozzle even if the processing liquid to be discharged has high viscosity. Hereinafter, a nozzle standby device and an operation method of a liquid processing apparatus according to an exemplary embodiment will be described with reference to the accompanying drawings. In the present specification and the drawings, parts having substantially same functional configurations will be assigned same reference numerals, and redundant description thereof will be omitted. FIG.1andFIG.2are a longitudinal side view and a perspective view, respectively, illustrating a schematic configuration of a liquid processing apparatus1equipped with a nozzle standby device according to an exemplary embodiment.FIG.3is a perspective view illustrating a nozzle unit provided in the liquid processing apparatus.FIG.4is a longitudinal side view illustrating a coating nozzle provided in the nozzle unit and a part of a standby unit.FIG.5is a transversal cross sectional view of a nozzle accommodation unit cut to include a solvent discharge opening.FIG.6is a longitudinal side view illustrating the nozzle unit and the standby unit. The liquid processing apparatus1is equipped with, as illustrated inFIG.1andFIG.2, a spin chuck2as a substrate holder configured to hold a wafer W horizontally by attracting a central portion of a rear surface of the wafer W. This spin chuck2is configured to be pivotable around a vertical axis and moved up and down with the wafer W held thereon by a driving mechanism22, which has an actuator such as a motor, via a driving shaft21. A cup23having a top opening is provided around the spin chuck2, surrounding the wafer W on the spin chuck2. The cup23receives and collects a liquid scattered or falling from the wafer W. Further, the liquid processing apparatus1is equipped with a nozzle unit3. The nozzle unit3is configured to discharge a coating liquid from a coating nozzle41onto a substantially center portion of a front surface of the wafer W held by the spin chuck2. This nozzle unit3includes a plurality of (for example, 10) coating nozzles41each configured to discharge a processing liquid; and, for example, one solvent nozzle42configured to discharge a solvent for the processing liquid. The coating nozzles41and the solvent nozzle42are fixed to a support31as one body. The processing liquid is of a type which is solidified by being dried. For example, the processing liquid may be a resist liquid having high viscosity (e.g., 50 cp to 1000 cp) for use in the manufacture of a 3D NAND memory. Further, the processing liquid may be a pigment resist (OCCF) or a water-soluble resist. The solvent may be, by way of non-limiting example, water or thinner such as PGMEA or OK73. In the following, the coating nozzles41and the solvent nozzle42may sometimes be simply referred to as nozzles41and42, respectively. The coating nozzles41and the solvent nozzle42are fixed to the support31such that they are arranged in a straight line along a transversal direction (Y-axis direction ofFIG.2) of the liquid processing apparatus1. Each coating nozzle41has a base end portion43connected to the support31; a cylindrical portion44extending vertically downwards from the base end portion43; and a leading end portion45having a substantially truncated conical shape with a gradually decreasing diameter as it goes downwards from the cylindrical portion44. A vertically extending path46for the processing liquid is formed through the base end portion43, the cylindrical portion44and the leading end portion45. The path46is opened at a leading end side of the nozzle as a discharge opening47for the processing liquid. The discharge opening47may be formed to have, for example, a circular shape, when viewed from the top. The solvent nozzle42has the same configuration as the coating nozzle41, for example. The coating nozzles41and the solvent nozzle42are supported by the common support31, and configured to be moved by a moving mechanism32between a processing position where they supply the processing liquid or the like onto the wafer W on the spin chuck2and a standby position where they are accommodated in a standby unit5to be described later. By way of example, the moving mechanism32is equipped with, as depicted inFIG.2, a horizontally moving member34configured to be moved along a guide33extending in the transversal direction (Y-axis direction ofFIG.2); and an arm35extending inwards (positive X-axis direction ofFIG.2) from the horizontally moving member34and having the support31at a leading end thereof. The arm35is configured to be moved up and down by an elevating mechanism (not shown) having an actuator such as a cylinder, thus enabling height adjustment of the nozzles41and42. The respective coating nozzles41are connected to different processing liquid sources100, as shown inFIG.1, for example. The processing liquid sources100store therein, for example, different kinds of resist liquids, or resist liquids of the same kind but having different viscosity. For example, the resist liquid for the resist thin film of the 3D NAND memory is stored as the processing liquid. Provided at a processing liquid supply path101between one coating nozzle41and the corresponding processing liquid source100are, for example, a suck-back valve SV as a suction device for the solvent and a flow rate controller102. The suck-back valve SV is configured to retreat (suck back) a leading end liquid surface of the processing liquid remaining in the path46of the coating nozzle41toward the corresponding processing liquid source101side when the discharge of the processing liquid from the coating nozzle41is stopped. The suck-back valve SV is equipped with, for example, a bellows having therein a suction room communicating with the corresponding processing liquid supply path101, and is configured to suck the processing liquid within the coating nozzle41toward the corresponding processing liquid supply path101side by expanding the bellows to turn the inside of the suction room into a negative pressure. Further, the suck-back valve SV is provided with a needle. By changing the maximum volume of the suction room with this needle, a distance by which the leading end liquid surface of the processing liquid is retreated can be adjusted. The flow rate controller102is configured to adjust a flow rate of the processing liquid, and is equipped with an opening/closing valve, a mass flow controller, and so forth. The solvent nozzle42is connected to a solvent source100in which the solvent is stored. A flow rate controller112is provided in a solvent supply path111between the solvent nozzle42and the solvent source110. The flow rate controller112is configured to adjust a flow rate of the solvent, and is equipped with an opening/closing valve, a mass flow controller, and so forth. The suck-back valves SV and the flow rate controllers102and112are controlled by a controller U to be described later. Further, the liquid processing apparatus1is equipped with, as illustrated inFIG.1andFIG.2, the standby unit5as a nozzle standby device. The standby unit5is provided on an outer surface of the cup23, for example. The standby unit5includes as many nozzle accommodation units51as the number (eleven in the shown example) of the nozzles41and42, as shown inFIG.6, for example. Each of the nozzle accommodation units51has a cylindrical shape, and the coating nozzles41and the solvent nozzle42can be accommodated in the corresponding nozzle accommodation units51individually. These nozzle accommodation units51are arranged in a straight line along, for example, a transversal direction (Y-axis direction ofFIG.6). The nozzle accommodation units51for the coating nozzles41have the same structure, which will be described with reference toFIG.4.FIG.4illustrates the leftmost nozzle accommodation unit51inFIG.6. A portion of this nozzle accommodation unit51for accommodating the cylindrical portion44and the leading end portion45of the corresponding coating nozzle41is of, for example, a cylindrical shape, and a lower part of the nozzle accommodation unit51is configured as a diameter reducing portion52whose inner diameter becomes smaller as it goes downwards, for example. Further, a lower end of the nozzle accommodation unit51communicates with, through a drain opening53, a drain space54shared between the nozzle accommodation units51. A liquid introduced into the drain space54is drained to the outside of the liquid processing apparatus1through a drain path55. When the nozzle unit3is located at the standby position where it is accommodated in the standby unit5, the leading end portion45of each of the coating nozzles41is located in the corresponding diameter reducing portion52of the corresponding nozzle accommodation unit51, as shown inFIG.4andFIG.6. An inner circumferential surface of the diameter reducing portion52corresponds to an inner circumferential surface surrounding the leading end portion of the corresponding coating nozzle41. Further, the drain opening53is located under the discharge opening47of the nozzle41to face the discharge opening47. The drain opening53has a circular shape when viewed from the top, and has a diameter larger than an outer diameter of a portion of the coating nozzle41corresponding to the discharge opening47of the coating nozzle41. For example, a portion with the smallest inner diameter between the diameter reducing portion52and the liquid drain space54corresponds to the drain opening53. Further, a solvent discharge opening56through which the solvent is supplied is provided in a lower sidewall (for example, a sidewall of the diameter reducing portion52) of the nozzle accommodation unit51for the coating nozzle41. The solvent discharge opening56is formed to discharge the solvent so that the solvent flows along an inner circumferential surface of the diameter reducing portion52, for example. To elaborate, the solvent discharge opening56is provided in a tangent direction of the diameter reducing portion52, as shown inFIG.5, for example. Accordingly, the solvent discharged from the solvent discharge opening56is guided along the inner circumferential surface of the nozzle accommodation unit51to be drained from the drain opening53. That is, with the above-described configuration, in the diameter reducing portion52, the solvent discharged from the solvent discharge opening56falls down, forming a swirling flow. Here, the structure of the diameter reducing portion52will be elaborated. The inner circumferential surface of the diameter reducing portion52according to the present exemplary embodiment includes, as depicted inFIG.4, a first inner circumferential surface52a, a second inner circumferential surface52b, and a third inner circumferential surface52c. The first inner circumferential surface52ais a surface with a decreasing inner diameter as it goes toward the drain opening53from a wall surface of the nozzle accommodation unit51facing the cylindrical portion44of the coating nozzle41. The first inner circumferential surface52ahas the same shape as a side surface of a truncated cone, and is formed as a slopped surface with respect to a center line C of the nozzle accommodation unit51. In the present specification, the center line C of the nozzle accommodation unit51refers to a line passing through a center of a circle formed by an inner circumferential surface51aof the nozzle accommodation unit51afacing the cylindrical portion44of the coating nozzle41. The second inner circumferential surface52bis a surface extending from a lower end of the first inner circumferential surface52atoward the drain opening53. In the present exemplary embodiment, an inner diameter of an upper end of the second inner circumferential surface52bis the same as an inner diameter of a lower end of the first inner circumferential surface52a, and the second inner circumferential surface52bmaintains this inner diameter as it goes from the inner circumferential surface52atoward the drain opening53. That is, the second inner circumferential surface52bof the present exemplary embodiment extends parallel to the center line C of the nozzle accommodation unit51and is not inclined with respect to the center line C. Further, the shape of the second inner circumferential surface52bmay not be limited to the example of the present exemplary embodiment. By way of non-limiting example, the second inner circumferential surface52bmay be inclined with respect to the center line C of the nozzle accommodation unit51and have a diameter which decreases as it goes from the lower end of the first inner circumferential surface52atoward the drain opening53. That is, the shapes of the first inner circumferential surface52aand the second inner circumferential surface52bare not particularly limited as long as they are formed at different angles with respect to the center line C of the nozzle accommodation unit. FIG.7is the same cross sectional view asFIG.4, and it illustrates a cross section cut along the center line C of the nozzle accommodation unit51to include the center line C. The first inner circumferential surface52ais formed such that an intersection point P of two straight lines extending along two opposite portions of the first inner circumferential surface52ashown on the cross section ofFIG.7is located above the discharge opening47of the coating nozzle41when the coating nozzle41is placed within the diameter reducing portion52. The first inner circumferential surface52ainclined with respect to the center line C of the nozzle accommodation unit51in this way makes it difficult for the solvent discharged from the solvent discharge opening56to be drained as will be described later, thus making it easy for the solvent to be collected into the diameter reducing portion52while the solvent is being drained. Further, an angle formed by the two opposite portions of the first inner circumferential surface52ashown on the cross section cut along the center line C of the nozzle accommodation unit51to include the center line C is desirably in a range from 120 degrees to 180 degrees. Furthermore, it is also desirable that the first inner circumferential surface52ais formed such that the intersection point P is located in a region inside the second inner circumferential surface52b, as in the present exemplary embodiment. If the first inner circumferential surface52ais formed such that the intersection point P is located in the region inside the second inner circumferential surface52b, it is easier to collect the solvent into the diameter reducing portion52while the solvent discharged from the solvent discharge opening56is being drained through the drain opening53. The third inner circumferential surface52cextends from a lower end of the second inner circumferential surface52btoward the drain opening53, and is formed to have an inner diameter which becomes smaller as it goes toward the drain opening53from the lower end of the second inner circumferential surface52b. This third inner circumferential surface52cimpedes a flow of the solvent heading toward the drain opening53from the second inner circumferential surface52b, making it difficult for the solvent discharged from the solvent discharge opening56to be drained from the drain opening53. Accordingly, while the solvent discharged from the solvent discharge opening56is being drained from the drain opening53, it become easier to collect the solvent into the diameter reducing portion52. Furthermore, the inner circumferential surface of the diameter reducing portion52may not include the third inner circumferential surface52c. However, in order to collect the solvent into the diameter reducing portion52easily as stated above, it is desirable to provide the third inner circumferential surface52c. In addition, if the third inner circumferential surface52cis formed, it is desirable that the angle formed by the two opposite portions of the first inner circumferential surface52aand an angle formed by two opposite portions of the third inner circumferential surface52cshown on the cross section cut along the center line C of the nozzle accommodation unit51to include the center line C are equal. With this configuration, it becomes easier to collect the solvent into the diameter reducing portion52while draining the solvent once discharged from the solvent discharge opening56from the drain opening53. Moreover, if the third inner circumferential surface52cis not formed, it is desirable that the second inner circumferential surface52bis formed to have an inner diameter which becomes smaller as it goes from the lower end of the first inner circumferential surface52atoward the drain opening53. As illustrated inFIG.6, each solvent discharge opening56is connected to a solvent source57in which the solvent is stored. Flow rate controllers59are respectively provided in solvent supply paths58between the solvent discharge openings56and the solvent source57. The flow rate controller59is configured to adjust a flow rate of the solvent discharged from the corresponding solvent discharge opening56, and is equipped with an opening/closing valve, a mass flow controller, and so forth. Each flow rate controller59is controlled by the controller U to be described later. A solvent supply unit including the solvent source57, the solvent supply path58, and the flow rate controller59supplies the solvent into the solvent discharge opening56to allow the solvent to be discharged from the solvent discharge opening56at a preset flow rate when a liquid layer of the solvent is formed within the coating nozzle41. Further, the nozzle accommodation unit51corresponding to the solvent nozzle42has the same configuration as the nozzle accommodation units51corresponding to the coating nozzles41except that the solvent discharge opening56, for example, is not formed therein. The coating nozzles41and the solvent nozzle42of the nozzle unit3are arranged on, for example, a straight line passing through a rotation center of the wafer W, and the nozzle accommodation units51of the standby unit5are also arranged on the straight line passing through the rotation center of the wafer W. The liquid processing apparatus1configured as described above is equipped with the controller U. The controller U may be, for example, a computer including a CPU, a memory, and so forth, and has a program storage (not shown). The program storage stores therein a program for controlling the suck-back valves SV, the flow rate controllers102,112and59, and so forth to control a wafer processing to be described later. Further, the program may be recorded on a computer-readable recording medium and installed from the recording medium to the controller U. A part or the whole of the program may be implemented by dedicated hardware (circuit board). Now, with reference toFIG.8AtoFIG.9, the wafer processing using the liquid processing apparatus1will be described for an example where a coating processing of the resist liquid is performed by using one coating nozzle41(hereinafter, referred to as “coating nozzle41A”) of the nozzle unit3. First, a pre-wet processing of discharging the solvent onto the front surface of the wafer W held by the spin chuck2from the solvent nozzle42is performed. To elaborate, the spin chuck2is raised to above the cup23, and the wafer W is delivered onto the spin chuck2from a wafer transfer device (not shown). Subsequently, the nozzle unit3is moved to a position where the solvent nozzle42supplies the solvent onto the rotation center of the wafer W held by the spin chuck2, and the thinner as the solvent is supplied. Then, the wafer W is rotated by the spin chuck2, and the thinner is diffused to a peripheral portion of the wafer W by a centrifugal force. Thereafter, a coating processing is performed by discharging a resist liquid having viscosity of, e.g., 50 cp to 1000 cp from the coating nozzle41A onto the front surface of the wafer W held by the spin chuck2. To elaborate, after the pre-wet processing, the rotation of the spin chuck2is stopped, and the nozzle unit3is moved to a position where the coating nozzle41A supplies the resist liquid onto the rotation center of the wafer W held by the spin chuck2, and the resist liquid is discharged. Then, the wafer W is rotated by the spin chuck2, and the resist liquid is diffused to the peripheral portion of the wafer W from the central portion thereof by the centrifugal force. The wafer W coated with the resist liquid is then delivered to the wafer transfer device. Meanwhile, if the discharge of the coating liquid is not performed for more than a preset time after the completion of this coating processing, the nozzle unit3is moved to a position where it faces the standby unit5, and is then lowered to accommodate the leading end portions of the respective coating nozzles41in the corresponding nozzle accommodation units51, thus locating the coating nozzles41at the standby positions. In this state, a resist liquid71within a leading end of the path46of the coating nozzle41A is discharged into the nozzle accommodation unit51by the dummy dispensing (seeFIG.8A). The resist liquid71is drained to the drain space54through the drain opening53of the nozzle accommodation unit51. Subsequently, a first suction is performed by the suck-back valve SV provided in the processing liquid supply path101of the coating nozzle41A. Accordingly, a liquid surface of the resist liquid71within the path46of the coating nozzle41A is retreated toward the processing liquid supply path101side to rise from the leading end of the coating nozzle41A, as shown inFIG.8B. For example, the liquid surface of the resist liquid71within the coating nozzle41A rises about 1 mm to about 3 mm from the leading end of the coating nozzle41A. Then, as illustrated inFIG.8C, a second suction is performed by the suck-back valve SV, and by discharging a solvent72into the nozzle accommodation unit51from the solvent discharge opening56at a preset flow rate, a liquid layer of the solvent (solvent layer83) is formed in a leading end portion of the path46of the coating nozzle41A. The solvent72discharged from the solvent discharge opening56flows along the inner circumferential surface of the diameter reducing portion52of the nozzle accommodation unit51, falls down as the swirling flow, and is then drained from the drain opening53. While the solvent72is being dropped in a spiral shape after being guided along the inner circumferential surface of the nozzle accommodation unit51as stated above, the solvent72is difficult to drain from the drain opening53since the first inner circumferential surface52ais formed such that the aforementioned intersection point P (seeFIG.7) is located above the discharge opening47of the coating nozzle41A. Accordingly, it becomes easy for the solvent72to be collected in the diameter reducing portion52temporarily. If the resist liquid71has the high viscosity, a thin film of the resist liquid71, which contributes to the formation of the solvent layer83, is difficult to form at the discharge opening57of the coating nozzle41A. According to the standby unit5of the present exemplary embodiment, however, the solvent72is easily collected into the diameter reducing portion52. Therefore, the discharge opening47of the coating nozzle41A located in the diameter reducing portion52can be kept closed by the solvent72which is gathered in the diameter reducing portion52temporarily. Thus, even if the thin film of the resist liquid71is not formed at the discharge opening47of the coating nozzle41A, the solvent72may be easily introduced into the path46. Accordingly, even if the resist liquid has the high viscosity, it is possible to form the solvent layer83in the path46of the coating nozzle41A. Meanwhile, in the conventional standby unit, since the aforementioned intersection point P is located under the second inner circumferential surface52b, the solvent72is difficult to collect into the diameter reducing portion52. That is, the solvent72may be easily drained from the drain opening53, making it difficult to maintain the discharge opening47of the coating nozzle41A closed by the solvent72. As a result, in the conventional standby unit, it has been difficult to form the solvent layer83unless the thin film of the resist liquid71is formed at the leading end of the coating nozzle41A. As stated above, a processing liquid layer81, an air layer82and the solvent layer83are formed within the path46of the coating nozzle41A in sequence from the processing liquid supply path101side, as illustrated inFIG.8D. Accordingly, since the processing liquid (resist liquid) within the leading end of the coating nozzle41A is blocked from the atmosphere by the air layer82and the solvent layer83, the drying of the processing liquid can be suppressed. By way of example, the suction by the suck-back valve SV is carried out such that the liquid surface of the solvent layer83within the coating nozzle41A rises about 5 mm to 15 mm from the leading end of the coating nozzle41A. Further, in the state that the discharge of the solvent72from the solvent discharge opening56is stopped, the path46within the coating nozzle41A may be suctioned by the suck-back valve SV to additionally form an air layer (not shown) outside the solvent layer83within the leading end of the coating nozzle41A. By additionally forming the air layer at a leading end side outer than the solvent layer83within the coating nozzle41A in this way, sucking of droplets of the solvent72into the leading end of the coating nozzle41A can be suppressed. In the state that the solvent layer83or the like is formed as stated above, the respective coating nozzles41stand by at the standby positions within the standby unit5. Now, the coating processing performed on the wafer W in the liquid processing apparatus1by using the nozzle unit3in which the processing liquid layer81, the air layer82and the solvent layer83are formed in the leading end of each coating nozzle41will be described for an example where one coating nozzle41A of the nozzle unit3is used. First, a processing of expelling the solvent layer83from the coating nozzle41A is performed. That is, the coating nozzle41A is placed at the standby position in the standby unit5, and a preset amount of the resist liquid71is discharged from the nozzle41A to expel the solvent layer83in the leading end of the nozzle41A. Then, the sucking-back of the resist liquid71is performed. At this time, to reduce the waste amount of the resist liquid71, a supply amount of the resist liquid71for expelling only the solvent layer83may be previously calculated by experiment. For example, by lowering the liquid surface of the resist liquid71by, e.g., about 2 mm, the solvent layer83may be expelled. Afterwards, the nozzle unit3is moved to a processing position where the coating nozzle41A supplies the coating liquid to the wafer W, and the resist liquid is supplied onto the wafer W from the coating nozzle41A so that the coating processing is performed in the same way as described above. Then, if the discharge of the coating liquid is not performed for more than a preset time after the completion of the coating processing, the used coating nozzle41A is accommodated back into the nozzle accommodation unit51of the standby unit5, and the processing liquid layer81, the air layer82and the solvent layer83are formed within the coating nozzle41A in sequence from the processing liquid supply path101side, as described above. Thereafter, when a coating processing is performed by using another coating nozzle41(hereinafter, referred to as “coating nozzle41B”) different from the aforementioned coating nozzle41A, the solvent layer83of the coating nozzle41B is expelled, the same as in the case of the coating nozzle41A. Then, after the coating processing of the resist liquid as the processing liquid is performed on the wafer W by using this coating nozzle41B, the nozzle unit3is placed at the standby position of the standby unit5, and the processing of forming the processing liquid layer81, the air layer82, and the solvent layer83within the leading end of this coating nozzle41B is performed. Further, the processing of expelling the solvent of the coating nozzle41A to be used, the subsequent preset coating processing, the subsequent processing of forming the processing liquid layer81, the air layer82and the solvent layer83within the leading end of the coating nozzle41A, and the subsequent coating processing using another coating nozzle41B or the like are performed based on the program stored in the controller U. As stated above, the standby unit5configured as the nozzle standby device according to the present exemplary embodiment is equipped with the nozzle accommodation units51and the solvent discharge openings56. Each nozzle accommodation unit51has the diameter reducing portion52having the first inner circumferential surface52aand the second inner circumferential surface52bso that the inner diameter thereof decreases as it goes toward the drain opening53. Further, on the cross section cut along the center line C of the nozzle accommodation unit51to include the center line C, the intersection point P of the two straight lines respectively extending along the two opposite portions of the first inner circumferential surface52ais located above the discharge opening47of the coating nozzle41when the leading end portion45of the coating nozzle41is placed in the diameter reducing portion52. With this standby unit5, it is easy to collect the solvent into the diameter reducing portion52when the solvent discharged from the solvent discharge opening56is drained from the drain opening53. Accordingly, the solvent can be easily introduced into the path46of the coating nozzle41. Thus, according to the standby unit5of the present exemplary embodiment, in forming the liquid layer of the solvent by standing-by the coating nozzle41for discharging the resist liquid71in the nozzle accommodation unit51and sucking the solvent into the leading end portion45of the coating nozzle41, it is possible to form the liquid layer of the solvent in the leading end portion45of the coating nozzle41even if the resist liquid71to be discharged has high viscosity. Further, since the solvent72is easily collected into the diameter reducing portion52in the standby unit5according to the present exemplary embodiment, there is a concern that the solvent may be collected into the nozzle accommodation unit51excessively if the supply of the solvent72from the solvent discharge opening56is continued. As a resolution, it may be desirable to provide a solvent drain opening60different from the drain opening53in a region above the solvent discharge opening56to drain the surplus of the solvent. The solvent drain opening60is connected to the drain path55(seeFIG.6) into which the processing liquid and the solvent drained from the drain opening53flows, and is drained to the outside of the liquid processing apparatus1through the drain path55. If the solvent drain opening60is provided as described above, the solvent72excessively collected and thus overflown from the nozzle accommodation unit51is drained from the nozzle accommodation unit51, so that the rise of the liquid surface of the solvent72can be suppressed. Accordingly, the adhesion of the solvent72to the side surface of the coating nozzle41can be suppressed. Although the solvent discharge opening56is formed in the first inner circumferential surface52ain the above-described exemplary embodiment, the location of the solvent discharge opening56is not particularly limited as long as the solvent can fall down, forming the swirling flow as shown inFIG.5. By way of example, the solvent discharge opening56may be formed above the first inner circumferential surface52a, that is, above the diameter reducing portion52, as illustrated inFIG.11. If the solvent discharge opening56is located above the diameter reducing portion52, the range where the swirling flow is formed can be enlarged in the vertical direction (Z-axis direction), so that the swirling flow can be easily maintained until the solvent is drained from the drain opening53. Accordingly, when forming the liquid layer of the solvent by sucking the solvent from the leading end portion45of the coating nozzle41, the solvent can be easily collected into the diameter reducing portion52, making it easy to form the liquid layer of the solvent in the path46of the coating nozzle41. Further, in the above-described exemplary embodiment, when performing preliminary discharging in which the processing liquid is discharged before forming the liquid layer of the solvent by sucking the solvent into the leading end portion45of the coating nozzle41, as shown inFIG.8A, only the processing liquid (the resist liquid71in the example ofFIG.8A) is discharged. Meanwhile, if the processing liquid has high viscosity, the processing liquid is difficult to drain from the drain opening53, and the processing liquid may adhere to the wall surface within the nozzle accommodation unit51, resulting in clogging of the nozzle accommodation unit51. If such clogging occurs, the leading end portion45of the coating nozzle41standing by in the nozzle accommodation unit51may be contaminated. As a resolution, when performing the aforementioned preliminary discharging, it is desirable to perform the discharging of the processing liquid from the coating nozzle41and the discharging of the solvent from the solvent discharge opening56at the same time. Since the processing liquid of the high viscosity can be diluted by the solvent, the draining of the processing liquid from the drain opening53can be accelerated. Furthermore, in the above-described exemplary embodiment, the nozzle unit3is configured to be moved between the processing position and the standby position. However, it is more desirable that the nozzle unit3is configured to be moved between the processing position, the standby position, and a preliminary discharging standby position. The preliminary discharging standby position refers to a position where the leading end portion45of each coating nozzle41is accommodated in the corresponding nozzle accommodation unit51in the state that the discharge opening47of the coating nozzle41is located higher than the solvent discharge opening56. In the present example, the controller U, for example, may perform a control of moving the coating nozzle41such that the leading end portion45of the coating nozzle41is located above the solvent discharge opening56. When performing the preliminary discharging, it is desirable that the nozzle unit3is being moved to the aforementioned preliminary discharging standby position. Accordingly, the processing liquid (the resist liquid71in the example ofFIG.12) diluted by the solvent72does not adhere to the coating nozzle41, so that the contamination of the leading end portion45of the coating nozzle41can be suppressed. Moreover, the above exemplary embodiment has been described for the example where the nozzle unit3has the plurality of coating nozzles41. However, the number of the coating nozzles41is not limited thereto, and the present exemplary embodiment may be applicable to a configuration where the nozzle unit3has a single coating nozzle. In addition, the nozzle standby device according to the present disclosure may also be applicable to a liquid processing apparatus for a processing target substrate other than the semiconductor wafer, for example, a FPD (Flat Panel Display) substrate. It should be noted that the exemplary embodiment is illustrative in all aspects and is not anyway limiting. The above-described exemplary embodiment may be omitted, replaced and modified in various ways without departing from the scope and the spirit of claims. According to the exemplary embodiment, in forming the liquid layer of the solvent by sucking the solvent into the leading end portion of the nozzle for discharging the processing liquid when the nozzle stands by in the nozzle accommodation unit, it is possible to form the liquid layer of the solvent in the leading end portion of the nozzle even if the processing liquid to be discharged has high viscosity. From the foregoing, it will be appreciated that various embodiments of the present disclosure have been described herein for purposes of illustration, and that various modifications may be made without departing from the scope and spirit of the present disclosure. Accordingly, the various embodiments disclosed herein are not intended to be limiting. The scope of the inventive concept is defined by the following claims and their equivalents rather than by the detailed description of the exemplary embodiments. It shall be understood that all modifications and embodiments conceived from the meaning and scope of the claims and their equivalents are included in the scope of the inventive concept. | 41,057 |
11862486 | DETAILED DESCRIPTION FIG.1is a plan view illustrating an outline of a substrate processing system provided with a processing unit according to an exemplary embodiment of the present disclosure. In the following, in order to clarify positional relationships, the X-axis, Y-axis and Z-axis which are orthogonal to each other will be defined. The positive Z-axis direction will be regarded as a vertically upward direction. As illustrated inFIG.1, a substrate processing system1includes a carry-in/out station2and a processing station3. The carry-in/out station2and the processing station3are provided adjacent to each other. The carry-in/out station2is provided with a carrier placing section11and a transfer section12. In the carrier placing section11, a plurality of carriers C is placed to accommodate a plurality of substrates (semiconductor wafers in the present exemplary embodiment) (hereinafter, referred to as “wafers W”) horizontally. The transfer section12is provided adjacent to the carrier placing section11, and provided with a substrate transfer device13and a delivery unit14. The substrate transfer device13is provided with a wafer holding mechanism configured to hold the wafer W. Further, the substrate transfer device13is movable horizontally and vertically and pivotable around a vertical axis, and transfers the wafers W between the carriers C and the delivery unit14by using the wafer holding mechanism. The processing station3is provided adjacent to the transfer section12. The processing station3is provided with a transfer section15and a plurality of processing units16. The plurality of processing units16is arranged at both sides of the transfer section15. The transfer section15is provided with a substrate transfer device17therein. The substrate transfer device17is provided with a wafer holding mechanism configured to hold the wafer W. Further, the substrate transfer device17is movable horizontally and vertically and pivotable around a vertical axis. The substrate transfer device17transfers the wafers W between the delivery unit14and the processing units16by using the wafer holding mechanism. The processing units16perform a predetermined substrate processing on the wafers W transferred by the substrate transfer device17. Further, the substrate processing system1is provided with a control device4. The control device4is, for example, a computer, and includes a control unit18and a storage unit19. The storage unit19stores a program that controls various processings performed in the substrate processing system1. The control unit18controls the operations of the substrate processing system1by reading and executing the program stored in the storage unit19. Further, the program may be recorded in a computer-readable recording medium, and installed from the recording medium to the storage unit19of the control device4. The computer-readable recording medium may be, for example, a hard disc (HD), a flexible disc (FD), a compact disc (CD), a magnet optical disc (MO), or a memory card. In the substrate processing system1configured as described above, the substrate transfer device13of the carry-in/out station2first takes out a wafer W from a carrier C placed in the carrier placing section11, and then places the taken wafer W on the delivery unit14. The wafer W placed on the delivery unit14is taken out from the delivery unit14by the substrate transfer device17of the processing station3and carried into a processing unit16. The wafer W carried into the processing unit16is processed by the processing unit16, and then, carried out from the processing unit16and placed on the delivery unit14by the substrate transfer device17. After the processing of placing the wafer W on the delivery unit14, the wafer W returns to the carrier C of the carrier placing section11by the substrate transfer device13. Now, referring toFIG.2andFIG.3, a configuration of the processing unit16will be discussed. The processing unit16is provided with a chamber20, a substrate holding mechanism30, a processing fluid supply unit40, and a recovery cup50. The chamber20accommodates the substrate holding mechanism30, the processing fluid supply unit40, and the recovery cup50. A fan filter unit (FFU)21configured to form a downflow within the chamber20is provided on the ceiling of the chamber20. The substrate holding mechanism30is provided with a substrate holding unit31, a shaft unit32, and a rotational driving unit33. The substrate holding unit31is configured to hold the wafer W horizontally. As the rotational driving unit33rotates the substrate holding unit31via the shaft unit32, the wafer W held by the substrate holding unit31is rotated around the vertical axis. The processing fluid supply unit40is equipped with a multiple number of movable nozzles41each configured to supply a processing fluid (a processing liquid or a processing gas) onto the wafer W. In the present exemplary embodiment, the multiple number of nozzles41include a first nozzle41a, a drying gas nozzle41b, a second nozzle41cand a solvent nozzle41d. Besides these nozzles, the multiple number of nozzles41may further include another nozzle for supplying a processing fluid. To elaborate, as shown inFIG.3, the processing fluid supply unit40is equipped with a first nozzle arm42A and a second nozzle arm42B. For the simplicity of illustration, only one nozzle arm42A between the two nozzle arms42A and42B is shown inFIG.2. The first nozzle41aand the drying gas nozzle41bare provided at the first nozzle arm42A, and the second nozzle41cand the solvent nozzle41dare provided at the second nozzle arm42B. The first nozzle41aand the second nozzle41care respectively provided at the first nozzle arm42A and the second nozzle arm42B to discharge a liquid directly downwards. Each of the nozzle arms42A and42B is configured to be pivotable around the vertical axis (as indicated by arrows MA and MB inFIG.3) and vertically movable by an arm driving unit43shown inFIG.2. By rotating the nozzle arms42A and42B, the nozzles41(41ato41d) provided at the nozzle arms42A and42B can be located at positions between a position directly above a center O of the wafer W and standby positions (as shown inFIG.3) at an outside of the recovery cup50when viewed from the top. As depicted inFIG.3, the first nozzle41ais connected with an etching liquid supply unit (chemical liquid supply unit)71and a first rinse liquid supply unit72. By switching a switching valve device73, either an etching liquid (e.g., nitrohydrofluoric acid) or a rinse liquid (e.g., DIW (Deionized Water), i.e., pure water) is selectively supplied from the first nozzle41a. Further, the second nozzle41cis connected with a cleaning liquid supply unit (chemical liquid supply unit)74and a second rinse liquid supply unit75. By switching a switching valve device76, either a cleaning liquid (e.g., SC-1) or a rinse liquid (e.g., pure water) is selectively supplied from the second nozzle41c. Each of the switching valve devices73and76may be implemented by a single three-way valve or two opening/closing valves. The drying gas nozzle41bis connected with a nitrogen gas supply unit77, and the solvent nozzle41dis connected with an IPA (isopropyl alcohol) supply unit78. Though not illustrated, each of the processing fluid supply units71,72,74,75,77and78is equipped with: a processing fluid supply source composed of a tank, a cylinder and a factory power supply source; a pipeline connecting the processing fluid supply source and the corresponding nozzle41(41ato41d); and a flow control device such as an opening/closing valve and a flow rate control valve provided at the corresponding pipeline. Particularly, as illustrated inFIG.2, the recovery cup50is disposed to surround the substrate holding unit31, and collects the liquid scattered from the wafer W after being supplied from the nozzle41onto the wafer W being rotated. A drain port51is formed on the bottom of the recovery cup50, and the processing liquid collected by the recovery cup50is drained from the drain port51to the outside of the processing unit16. Further, an exhaust port52is formed on the bottom of the recovery cup50to discharge an atmosphere within the recovery cup50to the outside of the chamber20(processing unit16). The processing fluid supply unit40is also equipped with an outer nozzle45. When viewed from the top (that is, inFIG.3), a discharge opening45aof the outer nozzle45is located at least at an outside of an outer edge of the wafer W held by the substrate holding unit31. In the shown example, the discharge opening45aof the outer nozzle45is located at an outside of an inner edge50aof an upper end opening of the recovery cup50, when viewed from the top. Particularly, as depicted inFIG.4, the outer nozzle45is configured to be movable up and down by an elevating mechanism46. Though not illustrated in detail, the elevating mechanism46may be implemented by, by way of non-limiting example, a linear actuator which is equipped with an electric rotating motor and a ball screw having a screw shaft rotated by the electric rotating motor. A bellows47is disposed to surround a movable portion of the elevating mechanism46such that the elevating mechanism46is not exposed to the atmosphere of the processing liquid. In the present exemplary embodiment, the outer nozzle45is not movable horizontally (in the X and Y directions) but movable only vertically (in the Z direction). That is, the outer nozzle45is provided such that a relative position thereof with respect to the wafer W is not changed when viewed from the top. If a continuous control over a height position of the outer nozzle45is not required, a multi-position air cylinder may be used as the linear actuator. In an example shown inFIG.4, an upper end of the bellows47is in firm contact with a bottom surface of the outer nozzle45, and a lower end of the bellows47is in firm contact with a top surface of a bottom plate (partition plate)54surrounding the recovery cup50. A main body portion46aof the elevating mechanism46is placed under the bottom plate54. An elevating rod46bconfigured to be moved up and down by being driven through the main body portion46aof the elevating mechanism46is extended through a hole54aformed at the bottom plate54and surrounded by the bellows47. DIW as the rinse liquid is supplied to the outer nozzle45from a rinse liquid supply unit48. The rinse liquid supply unit48is equipped with a rinse liquid supply line (passageway)48b; and a flowmeter48c, a flow rate control valve48dand an opening/closing valve48eprovided at the rinse liquid supply line48bin sequence from the upstream side. One end of this rinse liquid supply line48bis connected to a rinse liquid supply source48asuch as a tank, and the other end thereof is connected to the outer nozzle45. A drain line48gis branched from the rinse liquid supply line48bat a branch point48fat a downstream of the opening/closing valve48e. The drain line48gis provided with an opening/closing valve48h. A height position of a downstream end of the drain line48gis lower than the outer nozzle45. It is desirable to provide a liquid-receiving member49under the outer nozzle45. The liquid-receiving member49receives the rinse liquid discharged from the outer nozzle45(but not reaching the wafer W) immediately after the discharge of the rinse liquid from the outer nozzle45is begun (that is, immediately after the opening/closing valve48eis opened) and immediately before the discharge of the rinse liquid from the outer nozzle45is completely stopped (that is, immediately after the opening/closing valve48eis closed). Further, the liquid-receiving member49also receives the liquid (rinse liquid) falling down from the outer nozzle45after the opening/closing valve48eis closed. The rinse liquid received by the liquid-receiving member49is drained through a non-illustrated drain line to the outside of the processing unit16. The liquid-receiving member49may be fixed to the recovery cup50or the bottom plate54. The liquid-receiving member49may be connected to the outer nozzle45to be moved up and down along with the outer nozzle45. The rinse liquid is supplied from the outer nozzle45onto a surface (a device formation surface facing upwards) of the wafer W held by the substrate holding unit31. The outer nozzle45is provided such that rinse liquid discharged from the outer nozzle45flies on a straight line connecting the discharge opening45aof the outer nozzle45and the center O of the wafer W, when viewed from the top. An arrival position (arrival point) of the rinse liquid arriving at the surface of the wafer W after being discharged from the outer nozzle45is determined based on a discharge flow rate (a flow rate per unit time) of the rinse liquid from the outer nozzle45, the height position of the outer nozzle45and a discharge angle (ascending angle or descending angle) of the outer nozzle45. In the present exemplary embodiment, since there is provided no actuator configured to change the discharge angle of the outer nozzle45, the aforementioned arrival position is determined based on the discharge flow rate of the rinse liquid from the outer nozzle45and the height position of the outer nozzle45. Further, the discharge angle of the outer nozzle45may be manually adjusted at the time of initial setting or maintenance. When the rinse liquid is discharged from the outer nozzle45, the control device4feedback-controls the opening degree of the flow rate control valve48dbased on a detection value of the flowmeter48cin order to obtain the discharge flow rate defined in a process recipe. In order to allow the rinse liquid reaching the surface of the wafer W being rotated after being discharged from the outer nozzle45to be uniformly diffused on the entire surface of the wafer W, it is desirable that the rinse liquid arrives at the center O of the wafer W. To allow the rinse liquid to arrive at the center O of the wafer W regardless of the discharge flow rate of the rinse liquid, the height position of the outer nozzle45is adjusted by the elevating mechanism46. The height of the outer nozzle45at which the rinse liquid is allowed to reach the center O of the wafer W may be calculated for individual discharge flow rates of the rinse liquid in advance through experiment (or simulation). A combination of the discharge flow rate of the rinse liquid and the height position of the outer nozzle45determined based on this experiment result is set as a process parameter, which is recorded in the process recipe. For example, the process recipe may be stored in the storage unit19of the control device4. Further, it may be also possible to set the rinse liquid to arrive at a position deviated from the center O of the wafer W. Even in such a case, however, it may be desirable to allow the rinse liquid to arrive at a position where the rinse liquid can be diffused to the center O of the wafer W by an arrival force of the rinse liquid on the wafer W, thus allowing a central region of the wafer W including the center O of the wafer W to be covered with a liquid film of the rinse liquid. In this case as well, a combination of the discharge flow rate of the rinse liquid and the height position of the outer nozzle45for achieving this target arrival position can be previously obtained through experiment. The rinse liquid is discharged from the outer nozzle45by opening the opening/closing valve48eand closing the opening/closing valve48h, and then, the discharge of the rinse liquid from the outer nozzle45is stopped by closing the opening/closing valve48e. Then, if the opening/closing valve48his opened, the rinse liquid existing in the outer nozzle45, in a region of the rinse liquid supply line48bdownstream of the opening/closing valve48eand in the drain line48gis drained from the drain line48gby a siphon effect. By emptying the outer nozzle45and the region of the rinse liquid supply line48bdownstream of the opening/closing valve48e, the next time when the rinse liquid is discharged from the outer nozzle45by opening the opening/closing valve48e, a flow velocity of the rinse liquid discharged from the outer nozzle45immediately after the beginning of the discharge is increased. Accordingly, the amount of the rinse liquid arriving at a position other than the center O of the wafer W immediately after the beginning of the discharge of the rinse liquid can be reduced. Now, an example of a series of processes performed on each single sheet of wafer W by using the processing unit16of the above-described substrate processing system1will be explained. [Carry-in of Wafer] The wafer W is carried into the processing unit16by the substrate transfer device17and held by the substrate holding mechanism30. [Etching Process] The substrate holding mechanism30starts to rotate the wafer W around the vertical axis. The rotation of the wafer W is continued until a drying process to be described later is ended. The first nozzle41aof the first nozzle arm42A is located at a position directly above a position P1(seeFIG.3) on the wafer W distanced from the center O of the wafer W by a distance L1. The first nozzle41adischarges an etching liquid (e.g., DHF (dilute hydrofluoric acid)) directly downwards. Accordingly, the etching liquid arrives at the position P1which is distanced from the center O of the wafer W by the distance L1. The etching liquid having reached the position P1is flown on the wafer W while being diffused toward a periphery of the wafer W by a centrifugal force. Further, the etching liquid having arrived at the position P1is diffused up to the center O of the wafer W by the arrival force, and then is flown while being diffused toward the periphery of the wafer W by the centrifugal force. Accordingly, the entire surface of the wafer W is covered with the liquid film of the etching liquid. By maintaining this state for a preset time period, the surface of the wafer W is etched. Further, the distance L1is set to be a value which guarantees that the etching liquid having arrived at the position P1is diffused up to the center O of the wafer W by the arrival force. By way of example, though varied depending on the discharge flow rate of the etching liquid, the distance L1may be set to be 15 mm. By allowing the etching liquid to arrive not at the center O of the wafer W but at the position slightly deviated from the center O of the wafer W, the center O of the wafer W can be suppressed from being over-etched as compared to the other portion of the wafer W. That is, uniformity of the etching within the surface of the wafer W can be improved. Then, while discharging the etching liquid from the first nozzle41a, the first nozzle41ais moved to the position directly above the center O of the wafer W. [First Rinsing Process] After the first nozzle41ais moved to the position directly above the center O of the wafer W, the switching valve device73is immediately operated so that the liquid discharged from the first nozzle41ais switched from the etching liquid to a rinse liquid (DIW). The rinse liquid discharged from the first nozzle41aarrives at the center O of the wafer W and is flown on the wafer W while being diffused toward the periphery of the wafer W by the centrifugal force, so that the surface of the wafer W is covered with a liquid film of the rinse liquid. As a result, the etching liquid remaining on the wafer W and a reaction product generated through the etching process are washed away by the rinse liquid. Subsequently, while discharging the rinse liquid from the first nozzle41a, the first nozzle41ais moved to a position directly above a position P2near the center O of the wafer W. Specifically, the position P2is distanced apart from the center O of the wafer W by a distance L2. At this time, the rinse liquid discharged from the first nozzle41aarrives at the position P2on the surface of the wafer W. The distance L2is set to be a value which guarantees that the rinse liquid having arrived at the position P2is diffused up to the center O of the wafer W by the arrival force. By way of example, though varied depending on the discharge flow rate of the rinse liquid, the distance L2may be set to be 15 mm. The distance L2and the position P2may be the same as the distance L1and the position P1, respectively. Then, the rinse liquid (DIW) is discharged from the outer nozzle45so that the rinse liquid arrives at the center O of the wafer W. At this time, the rinse liquid is discharged from both the first nozzle41aand the outer nozzle45simultaneously. For the convenience of the following explanation, this state will be referred to as “first simultaneous discharge state.” Thereafter, the discharge of the rinse liquid from the first nozzle41ais stopped, and the first nozzle41ais moved to the standby position (shown inFIG.3). Then, the second nozzle41cis located at a position directly above the position P2distanced apart from the center O of the wafer W by the distance L2. At this time, the second nozzle41cpasses through a space above the center of the wafer W. While the second nozzle41cis being moved, the second nozzle41cdoes not interfere with a flow (trajectory) of the rinse liquid being discharged from the outer nozzle toward the center of the wafer W. Next, the rinse liquid is discharged from the second nozzle41c. The second nozzle41cdischarges the rinse liquid directly downwards. Accordingly, the rinse liquid discharged from the second nozzle41carrives at the position P2on the surface of the wafer W. At this time, the rinse liquid is discharged from both the second nozzle41cand the outer nozzle45simultaneously. For the convenience of the following explanation, this state will be referred to as “second simultaneous discharge state.” Thereafter, the discharge of the rinse liquid from the outer nozzle45is stopped, and the second nozzle41cis moved to the position directly above the center O of the wafer W while continuing to discharge the rinse liquid from the second nozzle41c. As stated above, by using the outer nozzle45, it is possible to perform the switchover of the nozzle arms42A and42B, that is, the switchover of the first nozzle41aand the second nozzle41cwhile maintaining the state where the entire surface of the wafer W is covered with the rinse liquid. [Chemical Liquid Cleaning Process] After the second nozzle41cis moved to the position directly above the center O of the wafer W, the switching valve device76is operated so that the liquid discharged from the second nozzle41cis switched from the rinse liquid (DIW) to a cleaning liquid (a chemical liquid for cleaning, e.g., SC-1). The cleaning liquid discharged from the second nozzle41carrives at the center O of the wafer W and is flown on the wafer W while being diffused toward the periphery thereof by the centrifugal force, so that the surface of the wafer W is covered with a liquid film of the cleaning liquid. As a result, an organic contaminant existing on the wafer W is washed away by the cleaning liquid. [Second Rinsing Process] Thereafter, the liquid discharged from the second nozzle41cis changed from the cleaning liquid to the rinse liquid. The rinse liquid discharged from the second nozzle41carrives at the center O of the wafer W and is flown on the wafer W while being diffused toward the periphery of the wafer W by the centrifugal force, so that the surface of the wafer W is covered with a liquid film of the rinse liquid. As a result, the cleaning liquid remaining on the wafer W and a reaction product generated through the cleaning process are washed away by the rinse liquid. [Solvent Replacing Process] While continuing the discharge of the rinse liquid from the second nozzle41c, IPA is discharged from the solvent nozzle41d, and while maintaining this state, the solvent nozzle41dis moved to the position directly above the center O of the wafer W. Then, the discharge of the rinse liquid from the second nozzle41cis stopped. The IPA discharged from the solvent nozzle41dfalls down onto the center O of the wafer W and is flown on the wafer W while being diffused toward the periphery of the wafer W by the centrifugal force. As a result, the rinse liquid (DIW) on the surface of the wafer W is replaced by the IPA, and the surface of the wafer W is covered with a liquid film of the IPA. [Drying Process] While the solvent nozzle41dis discharging the IPA to the center O of the wafer W, the drying gas nozzle41bis moved to above a position near the center O of the wafer W within a range where the nozzle arms42A and42B do not collide with each other. Then, the solvent nozzle41dis moved toward the periphery of the wafer W. If the solvent nozzle41dis retreated from above the center O of the wafer W, the drying gas nozzle41bis moved to directly above the center O of the wafer W, and a drying gas (e.g., a nitrogen gas, dry air, or the like) is discharged from the drying gas nozzle41b. The drying gas nozzle41bis then moved toward the periphery of the wafer W. At this time, the solvent nozzle41dand the drying gas nozzle41bare moved toward the periphery of the wafer W while maintaining the positional relationship that the solvent nozzle41dis located at an outer position than the drying gas nozzle41bin the radial direction of the wafer W. Accordingly, a circular drying region is enlarged from the central portion of the wafer W toward the periphery thereof, and, finally, the entire surface of the wafer W is dried. Through the above-described operations, the series of processes upon the single sheet of wafer W are ended. The completely processed wafer W is carried out of the processing unit16by the substrate transfer device17. When performing the above-described processes, there might be assumed a case where a device, which is vulnerable to electrification, is previously formed on the wafer W as the target of the processing. In this case, to suppress triboelectrification, the flow rate of the rinse liquid is required to be small. Meanwhile, when processing a wafer which does not have such a requirement, it may be desirable to set the flow rate of the rinse liquid to be large to shorten a processing time. By adding the automatic elevating function to the outer nozzle45as stated above, the height position of the outer nozzle45can be changed in response to the variation in the flow rate of the rinse liquid. Thus, the arrival position of the rinse liquid can be allowed to be set at the center of the wafer W regardless of the flow rate of the rinse liquid. Therefore, even if the discharge flow rate of the rinse liquid as a process parameter is differed between a preceding processing lot and a following processing lot, it is not needed to stop the overall operations of the substrate processing system1or to open a panel of the processing unit16for the manual adjustment. Hence, the substrate processing system1can be run effectively. Furthermore, in the above-described exemplary embodiment, the height position of the outer nozzle45can be adjusted by the elevating mechanism46which is the linear actuator. However, the exemplary embodiment is not limited thereto, and, the discharge angle of the outer nozzle45may be adjusted by an actuator90, for example, a ball screw operated by an electric rotating motor, as shown inFIG.5. In the example shown inFIG.5, a supporting column91is provided on the bottom plate54, and the outer nozzle45is rotatably supported on the supporting column91via a horizontal shaft92provided at the supporting column91. As the actuator90pushes (pulls) an appropriate portion of the outer nozzle45(inFIG.5, a rear end portion of the outer nozzle45) which is distanced apart from the horizontal shaft92, the discharge angle (ascending angle or descending angle) of the outer nozzle45is changed. Accordingly, the discharge angle of the rinse liquid discharged from the outer nozzle45is changed, so that the arrival position of the rinse liquid onto the wafer W can be changed. In the example shown inFIG.5as well, the position of the outer nozzle45in the horizontal direction is maintained constant. Now, there will be explained an experiment which is conducted to investigate a desirable arrival position of the rinse liquid discharged from the first nozzle41a(or the second nozzle41c) onto the surface of the wafer W to suppress splash of the liquid in the aforementioned first and second simultaneous discharge states. Since the first simultaneous discharge state and the second simultaneous discharge state are substantially same, the experiment is performed only for the first simultaneous discharge state. As stated earlier, since the arrival position of the rinse liquid from the outer nozzle45is required to be the center O of the wafer W, the arrival position of the rinse liquid discharged from the first nozzle41ais changed in the experiment. To achieve various positions of the first nozzle41ato be described below, a nozzle arm dedicated for testing is used as the nozzle arm holding the first nozzle41a. To describe the arrival positions, an XY orthogonal coordinate system is set on the surface of the wafer W as shown inFIG.6which is a plan view of the wafer W being rotated when viewed from directly above. The center (rotation center) O of the wafer W is called an origin (hereinafter, sometimes referred to as “origin O”) of the XY orthogonal coordinate system. A flight trajectory of the rinse liquid reaching the origin O after being discharged from the outer nozzle45is indicated by a thick dashed line. A straight line including the flight trajectory of the rinse liquid is defined as the Y-axis, and the direction of the flight of the rinse liquid is defined as the positive Y-axis direction. A straight line including a second vector obtained by rotating a first vector, which is started from the origin O and oriented toward the positive Y-axis direction, by 90 degrees in a rotational direction R of the wafer W around the origin O is defined as the X-axis. The positive X-axis direction coincides with the direction of the second vector. That is, inFIG.6, since the rotational direction of the wafer W is clockwise, the upward direction ofFIG.6becomes the positive Y-axis direction, and the rightward direction ofFIG.6becomes the positive X-axis direction. Further, if the rotational direction of the wafer W is counterclockwise, the leftward direction ofFIG.6becomes the positive X-axis direction. Further, the X-axis and the Y-axis of the XY orthogonal coordinate system shown inFIG.6may coincide with the X-axis and the Y-axis shown inFIG.1(as in the processing units16shown in the lower part ofFIG.1) or may not. Splashes that occur when the horizontal position of the first nozzle41a, that is, the arrival position of the rinse liquid discharged from the first nozzle41ais set to positions S1, S2, S3, S4, S5and S6shown inFIG.6are investigated. Distances from the origin O as the rotation center of the wafer W to the respective positions S1to S6are all 15 mm, and only angular positions are different. S2and S5are positions on the X-axis; S3, a position 45 degrees behind the position S2in the rotational direction R of the wafer; S1, a position rotated 45 degrees from the position S2in the rotational direction R of the wafer; S6, a position 45 degrees behind the position S5in the rotational direction R of the wafer W; and S4, a position rotated 45 degrees from the position S5in the rotational direction R of the wafer. Experiment conditions are as follows. The rotational speed of the wafer W is set to be 1500 rpm; the discharge flow rate of the rinse liquid from the outer nozzle, 1.5 L/min; and the discharge flow rate of the rinse liquid from the first nozzle41ais set to have three levels of 0.5 L/min, 1.0 L/min and 1.5 L/min. Presence or absence of splashes and occurrence situation thereof are determined based on a high-speed video and high-resolution still images. Experiment results are shown in the following table. TABLE 1Flow rate (L/min)S1S2S3S4S5S60.5◯◯XXΔΔ1.0◯ΔXXXΔ1.5◯XXXXX In the above Table 1, a symbol “O” implies that no splash has occurred; a symbol “A” implies that a splash has occurred on rare occasions; and a symbol “X” indicates that a splash has occurred all the time. As a result of observing the images, on the positions S2and S3, splashes are found to occur when the liquid discharged from the first nozzle41afalls down on the liquid film of the rinse liquid which is discharged from the outer nozzle45to be diffused on the wafer W after reaching the wafer W ((except when the flow rate is 0.5 L/min). Meanwhile, on the positions S4, S5and S6, splashes are found to occur when the liquid discharged from the outer nozzle45falls down on the liquid film of the rinse liquid which is discharged from the first nozzle41ato be diffused on the wafer W after reaching the wafer W. On the position S1, any of the aforementioned splashes has not occurred regardless of the discharge flow rate from the first nozzle41a. In view of this result, it is found out that the splashes can be suppressed from occurring by setting the arrival position of the rinse liquid from the first nozzle41ato be a fourth quadrant (that is, X>0, Y<0) on the aforementioned XY orthogonal coordinate system. As can be seen from this experiment result, it is desirable that the position P1of the first nozzle41aand the position P2of the second nozzle41cin the aforementioned first and second simultaneous discharge states in the exemplary embodiment are set to be the position S1as mentioned in the above-described experiment. In the above-described exemplary embodiment, when performing the series of processes on the wafer W, the outer nozzle45and the movable nozzles41ato41dprovided at the nozzle arms42A and42B are used together. However, the exemplary embodiment is not limited thereto. By way of example, all of the processing liquids supplied to the wafer W may be supplied from a single or a plurality of outer nozzles. The rinse liquid is not limited to the pure water (DIW). To add conductivity, a solution prepared by dissolving a small amount of carbon dioxide gas and/or ammonia in DIW may be used. The processing liquid discharged from the outer nozzle45is not be limited to the rinse liquid but any of various other kinds of processing liquids such as an acidic chemical liquid, an alkaline chemical liquid and an organic solvent may be discharged from the outer nozzle45. In case of supplying the chemical liquid from the outer nozzle45, it may be considered, for the purpose of saving the chemical liquid, to supply the chemical liquid to the center of the wafer W at a relatively large flow rate at first to form a liquid film of the chemical liquid rapidly on the entire surface of the wafer W and then to supply the chemical liquid to the center of the wafer W at a relatively small flow rate only to the extent that the liquid film of the chemical liquid can be maintained. In this case as well, by lowering the height position of the outer nozzle45when discharging the chemical liquid from the outer nozzle45at the relatively large flow rate and by raising the height position of the outer nozzle45when discharging the chemical liquid from the outer nozzle45at the relatively small flow rate, the arrival position of the chemical liquid can be set to be the center of the wafer W regardless of the discharge flow rate of the chemical liquid. The claims of the present application are different and possibly, at least in some aspects, broader in scope than the claims pursued in the parent application. To the extent any prior amendments or characterizations of the scope of any claim or cited document made during prosecution of the parent could be construed as a disclaimer of any subject matter supported by the present disclosure, Applicants hereby rescind and retract such disclaimer. Accordingly, the references previously presented in the parent applications may need to be revisited. | 35,976 |
11862487 | DETAILED DESCRIPTION OF THE INVENTION FIG.1shows a schematic first device10according to the invention which is not true to scale comprising a first, lower substrate holder6u, and a second, upper substrate holder6o. The two substrate holders6u,6oinclude at least one first component1u,1o. Fixing elements3, which are used to fix substrates2u,2o, are located on the components1u,1o. In the upper component1o, there is preferably an opening12through which a deformation element4can move. The deformation element4is used to deform the second upper substrate2o. According to the invention, the components1o,1uare designed in such a way that they have recesses7o,7uin which the substrates2u,2oare located. The edge of the first components1u,1ohas elevations8u,80. The elevations8u,8ohave internal walls8ui,8oi. The interior walls8ui,8oihave a height tu, to. The horizontal distances between the inner walls8ui,8oiand peripheries9u,90of the substrates2u,2oare hu, ho. Furthermore, the elevations8u,8ohave an expansion surface8us,8osaccording to the invention with a length wu, wo, which widen the substrate surfaces2us,2osfor transporting the gas beyond the peripheries9u,9o. As a result, according to the invention, the isenthalpic expansion process takes place outside the device10according to the invention and not directly outside the substrates1u,1o. The problem is thus shifted outwards via the expansion surface8us,8os. The vertical distances between the expansion surfaces8us,8osand the substrate surfaces2us,2osof the substrates2u,2oare vu, vo. In this embodiment according to the invention, the geometries are fixed and cannot be changed. The distances hu, ho, vu, vo were deliberately set too large to increase clarity. In real embodiments, they should be only a few μm, in particular up to max. 1.0 mm, large. FIG.2ashows a schematic, improved second inventive device10′, which is not to scale, in a first process step according to the invention, which consists of at least two components1u′,5uon the underside and/or two components1u′,5oon the upper side. It is also conceivable that one of the two substrate holders6u′,6o′ is constructed in the same manner as the substrate holders6u,6ofromFIG.1. For the sake of simplicity, only the lower substrate holder6u′ will be described. The lower substrate holder6u′ has a first outer component1u′, in which an inner, second component5ucan move in a translational and/or rotary manner. The relative displacement of the two components1u′ and5uis used to position the substrate surface2usrelative to the expansion surface8us. According to the invention, the exiting gas or the exiting gas mixture is to be conducted via the expansion surface Bus from the device10′ according to the invention so that the isenthalpic expansion process does not take place directly on the substrate peripheries9u,9oand thus a condensation of gases, in particular water vapour, is prevented by temperature drop. In contrast to the first device10according to the invention, however, the position of the substrate surface2usrelative to the expansion surface Bus can be precisely adjusted and thus the fluid flow can be optimized outwards. Similar considerations apply to the upper substrate holder6o′. FIG.2bshows the schematic improved second embodiment 10′, which is not to scale, according to the invention in a second process step according to the invention in which the two substrate holders1u′,1o′ were brought closer to one another in such a way that an expansion surface spacing d results. At the same time, a substrate surface gap g exists. FIG.2cshows the schematic, non-scale-corrected, improved second embodiment 10′, which is not to scale, according to the invention in a third inventive process step, in which the two second components5u,5omove translationally such that the substrate surface spacing g decreases to g′. It would also be conceivable that the desired substrate surface spacing g had already been achieved inFIG.2b, with which the third inventive process step would be optional provided that it is possible to dispense with the optimization of the vertical distances vu, vo. FIG.2dshows the schematic, improved second embodiment 10′, which is not to scale, according to the invention in a fourth process step according to the invention in which the deformation element4deforms the upper substrate2oand thus starts the bonding process. The upper substrate2ois detached from the upper substrate holder6o′, in particular by a controlled switching-off of the fixing elements3. From this point onwards, a bond wave13, which is symmetrical in its entirety, is formed, which drives a compressed gas in front of it. FIG.2eshows a schematic, enlarged scale illustration of a lateral part of the improved embodiment 10′ according to the invention in a fifth process step according to the invention, as well as a pressure (or pressure difference) temperature-position graph. In this process step, the two substrates2u,2owere almost completely joined to one another, with the exception of the edge regions of the substrates2u,2owhich are relevant according to the invention. The gas displaced by the bond wave13can spread over the expansion surfaces8us,80swithout an isenthalpic expansion into the outer region14. Only in the vicinity of the outer region14does the isenthalpic expansion occur, which would have led to a cooling and condensation of the gas in the case of negative JTC. By expanding the substrate surfaces2us,2osvia the expansion surfaces8us,80s, the isenthalpic expansion could thus be geometrically delayed. In the graph, the pressure difference p-p0is plotted on the left-hand abscissa. The pressure p0is the ambient pressure in the outer region p0. The ambient pressure p0corresponds mostly to 1 bar. In general, however, the embodiment according to the invention can itself be installed in a pressure chamber in which an increased ambient pressure can be adjusted. In general, the ambient pressure p0is less than 10 bar, preferably less than 5 bar, more preferably less than 3 bar, most preferably less than 2 bar, most preferably 1 bar. The pressure p represents the pressure at the indicated position. The pressure values p lie between 20 bar and p0, preferably between 10 bar and p0, more preferably between 5 bar and p0, most preferably between 3 bar and p0, most preferably between 2 bar and p0. The different pressure curves15,15′,15″,15′″ represent the pressure curve for four differently advanced bonding steps.FIG.2ecorrelates with the first pressure profile15. The pressure profile15″ is produced, for example, at a point in time in which the two substrate surfaces2us,2oshave already been completely bonded to one another. Although the pressure curves15,15′ and partial15″ still lie between the substrates, there is no isenthalpic expansion, but only the compression of the gas. The region of the isenthalpic expansion is advantageously located in the shaded region17, that is, in all cases outside the substrates2u,2o. In this region, a discharged gas can easily condense, since it is no longer on the substrate surfaces2us,2os. It can be seen that the pressure curve15″ is located outside the substrates2u,2o, in contrast toFIG.2of the cited printed document Castex et al.,Mechanism of Edge Bonding Void Formation in Hydrophilie Direct, ECS Solid State Letters,2 (6) P47-P50 (2013). By means of the hole11, an evacuation and/or a flushing of the interior space of the embodiment 10′ according to the invention can be performed, which further reduces the negative effect. Thus, it is conceivable to use a gas which changes the JTC of the gas mixture between the two substrates2u,2osuch that the isenthalpic expansion leads to heating rather than cooling. In all the figures shown, inclined inner walls8ui,8oiof the elevations8u,8oare conceivable, which facilitate the loading of the substrates2u,2o. The recess7u,7owould then have the form of a truncated cone. FIG.3ashows a schematic graph of an inversion curve of an arbitrary gas or gas mixture. The areas with positive JTC (grey) and those with negative JTC (white) can be seen. The graph is a p-T graph. The gas under consideration therefore has a positive or negative JTC depending on the pressure present and the temperature. If the state parameters pressure and temperature were exactly on the inversion curve, the JTC would be zero. For ideal gases and gas mixtures the JTC is always zero. Only real gases or gas mixtures are therefore considered. In order to produce a heating according to the invention of a gas or of a gas mixture, it must be ensured that the gas or gas mixture is always in the region with a negative JTC. At standard normal conditions, there are only three gases which have a negative JTC, namely, helium, hydrogen, and neon. FIG.3bshows a schematic graph of the inversion curves of nitrogen, hydrogen and helium. It can be seen that nitrogen has a positive JTC for standard standard conditions (about 298, 15 K, 1 bar) and will therefore cool down with an isenthalpic expansion. It is therefore also a further aspect according to the invention to take measures according to the invention in the bonding process according to the invention in order to remove gases, in particular atmospheric nitrogen, with a positive JTC as far as possible from the atmosphere and, preferably, entirely by gases with positive JTC. The two gases hydrogen and helium, on the other hand, have inversion curves that lie far below 298, 15K. Hydrogen and helium, therefore, are heated under is standardized conditions under an isenthalpic expansion and thus counteract a condensation of other gases, in particular water vapour. FIG.4ashows a schematic illustration of a substrate periphery9having a first defect type18, which is not true to scale. The first defect type18represents a dent. FIG.4bshows a schematic illustration of a substrate periphery9with a second defect type18′, which is not true to scale′. The second defect type18′ represents a substrate surface2swith high surface roughness. FIG.4cshows a schematic illustration of a substrate periphery9with a substrate surface2son which adsorbed gases, in particular water, are located, which is not to scale. This state actually represents the normal state of most surfaces. With regard to the process according to the invention, this state is nevertheless classified as a third defect type18″. The third defect type18″ thus represents a substrate surface2swith adsorbed gases, in particular water. The water is, in particular, only present as a monolayer. FIG.4dshows a schematic illustration of a substrate periphery9having a fourth defect type18′″, which is not true to scale. The fourth defect type18′″ represents a substrate surface2swith a locally concentrated, condensed gas, in particular water. FIG.4eshows a schematic illustration of a substrate periphery9with a fifth defect type18IV, which is not true to scale. The fifth defect type18IV represents a substrate surface2swith a particle. FIG.5ashows a first widening according to the invention of the elevation8′ with a curved expansion surface8s′, which increases the volume towards the outside. FIG.5bshows a second widening according to the invention of the elevation8″ with a curved expansion surface8s″, which reduces the volume to the outside. This element acts thermodynamically as a throttle valve. FIG.5cshows a third extension according to the invention of the elevation8′ “with a curved expansion surface8s′”, which increases the volume outwards linearly. FIG.5dshows a second enlargement according to the invention of the elevation8IV with a curved expansion surface8sIV which linearly reduces the volume to the outside. This element acts thermodynamically as a throttle valve. FIG.6ashows a schematic, enlarged scale view of a right-hand part of an improved substrate holder6uin which the production of the constructional features hu, vu has been dispensed with by the introduction of a rounded radius of curvature or bevel radius R. The manufacture of such a transition is much easier and more efficient in terms of construction technology. The radius of curvature or bevel radius R is, in particular, equal to the radius of curvature of the substrate periphery9. The person skilled in the art knows that the substrate peripheries9in the cross section according to the SEMI standard do not necessarily describe a semi-circle, but can be arbitrarily shaped. For the sake of completeness, it is therefore mentioned that the radius of curvature or bevel radius R is a parameter with the aid of which the best attempt is made to adapt the substrate2u, in particular its substrate periphery9, to the lower substrate holder6u. For an upper substrate holder6o, analogous considerations apply where necessary and desired. The deviation between the radius of curvature or bevel radius R and the curvature of the substrate periphery9is in particular less than 5%, preferably less than 3%, more preferably less than 2%, most preferably less than 1%, most preferably of all less than 0.1%. The use of a radius of curvature or bevel radius R can be combined with the use of the distances hu, ho, vu, vo. FIG.6bshows a schematic enlarged view of a right-hand part of a further, improved substrate holder6uin which the elevation8u′ has been designed as a ring which is mounted on the component1u. The mounting is not explained in more detail here.8u′ can be welded, glued, bonded, screwed riveted etc. with the component1u. FIG.6cshows a schematic enlarged view of a right-hand part of a further, improved substrate holder6uin which the elevation8u′ has been designed as a ring which is mounted in a step21of the component1u. The mounting is not explained in more detail here.8u′ can be welded, glued, bonded, screwed riveted etc. with the component1u. The elevations8u′ designed as rings inFIGS.6band6care preferably also interchangeable. Thus, a plurality of different rings8u′ can be constructed and, if necessary, exchanged to adjust the elevations8u′ accordingly and optimize them for the process. FIG.6dshows a schematic enlarged view of a right-hand part of a further, improved substrate holder6uin which a nozzle22provides an overpressure from outside. Such nozzle systems have also already been mentioned in part in PCT/EP2016053268. FIG.6eshows a schematic enlarged view of a right-hand part of a further, improved substrate holder6uin which the hole11′ has been constructed in such a way that the gas or gas mixture can be flushed directly in the direction of the substrate. FIG.7shows an embodiment, which is not to scale, of a first embodiment of a surface enlargement means19. In this case, a substrate2is enclosed by means of the radius of curvature and bevel radius R of the surface enlargement means19. Between the substrate surface2sto be bonded and an expansion surface8sof the surface enlarging means19, there is a vertical spacing vo, which is preferably less than 10 micrometres, particularly preferably less than 1 micrometre. The substrate surface2sis expanded by the expansion surface8s. FIG.8shows a further embodiment which is not true to scale of a surface enlargement means19′. In this case, compared toFIG.7, the substrate2is merely supported on the outer substrate periphery9, preferably with a low pressing force. The substrate2is thereby completely enclosed. The bevel radius R is intended to surround the outer substrate periphery9, in particular, perfectly. In the figures, the same components or components with the same function are labelled with the same reference numbers. REFERENCE LIST 1,1u,1oFirst/outer component2,2u,2oSubstrates2s,2us,2osSubstrate surface3Fixings4Deformation element5u,5oSecond/inner component6u,6u′,6o,6o′ Substrate holder7o,7uRecess8o,8u,8u′,8,8′,8″,8′″,8IV,8V Elevation8oi,8uiInterior wall8os, Bus,8s,8s′,8s″,8s′″,8sIV Expansion surface9,9u,9oSubstrate periphery10,10′ Bonding device11,11′ Hole12Opening13Bond wave14Outside area15,15′,15″,15′″ Pressure curve16Temperature curve17Range of isenthalpic expansion18,18′,18″,18′″,18IV Defect19,19′ Surface enlarging means20Rounding21Graduation22Nozzlea Angled Expansion surface spacingg Substrate surface spacingwu, wo Elevation widthtu, to Elevation depthho, hu Horizontal distancesvo, vo vu, vu′ Vertical distancesP Pressure between the substratesp0Ambient pressureR Radius of curvature or bevel radius | 16,412 |
11862488 | DETAILED DESCRIPTION In the following detailed description, reference is made to the accompanying drawings, which form a part hereof. The illustrative embodiments described in the detailed description, drawings, and claims are not meant to be limiting. Other embodiments may be utilized, and other changes may be made without departing from the spirit or scope of the subject matter presented here. Hereinafter, embodiments of the present disclosure will be described with reference to the drawings. First Embodiment First, a first embodiment will be described. FIG.1is a cross-sectional view illustrating an example of a substrate stage according to the first embodiment, andFIG.2is a cross-sectional view illustrating another example of the substrate stage according to the first embodiment. The first embodiment is a basic embodiment. In the present embodiment, a substrate stage10is provided in a processing container of a processing apparatus in which a processing (e.g., a film forming processing) is performed on a substrate W (e.g., a semiconductor wafer). The substrate stage10has a substrate placing surface10aon which the substrate W is placed. The substrate stage10has a stage body1and a thermocouple3that detects a temperature near the substrate placing surface10aof the stage body1. Further, heaters2are provided in the stage body1. Then, the substrate W is placed on the substrate placing surface10a, and a processing (e.g., a CVD film forming processing) is performed on the substrate W in a state where the inside of the processing container is maintained in a vacuum. The stage body1may be entirely made of a metal or a ceramic bulk material, or as illustrated inFIG.2, may have an electrostatic chuck12that adsorbs the substrate W on a base substrate11including a bulk material. The electrostatic chuck12is formed by providing an electrode14in a dielectric body13such as alumina. As illustrated, a surface of the electrostatic chuck12may be an embossed surface having a plurality of protrusions13a. In this case, the surface of the protrusion13aserves as the substrate placing surface10a. The electrode14is connected with an electrostatic adsorption power source (a DC power source)15. The electrostatic chuck12may be a bulk material, or may be formed by thermal spraying. A heater2functions as a temperature adjuster, and during a processing performed in a substrate apparatus, for example, in a case of a CVD film formation, heats the stage body1to heat the substrate W to a processing temperature. A mechanism which allows a temperature adjusting medium to flow through the stage body1may be used as a temperature adjuster depending on processings, instead of the heater2. The thermocouple3has a temperature measuring unit3aformed on the surface on the substrate placing surface10aside of the stage body1in a state where a first metal film21and a second metal film22are stacked. In the temperature measuring unit3a, the first metal film21and the second metal film22are brought into contact with each other to form a circuit, and a thermo-electromotive force is generated. Therefore, the temperature of a portion near the substrate placing surface10aof the stage body1is detected. In the example inFIG.1, the temperature measuring unit3ais formed on the surface of a recess1bformed on the substrate placing surface10aside of the stage body1, and a space is provided between the temperature measuring unit3aand the substrate W. Further, in the example inFIG.2, the temperature measuring unit3ais formed on the surface of a recess13bformed between the protrusions13a, and a space is provided between the temperature measuring unit3aand the substrate W. A thin insulating film may be provided between the temperature measuring unit3aand the substrate W. The thickness of the first metal film21and the second metal film22is about 0.1 μm to 100 μm, and may be formed by a film forming technique such as thermal spraying, CVD, PVD, and plating. Among them, thermal spraying may be used. Examples of a combination of the first metal film21and the second metal film22may include chromel and alumel. Additionally, a combination of materials used as a thermocouple in the related art, such as a combination of platinum-rhodium alloy and platinum, and iron and constantan may be adopted. The thermocouple3includes compensating lead wires23and24connected to the first metal film21and the second metal film22, and extending vertically downward in the stage body1. The compensating lead wires23and24may be made of the same material as the first metal film21and the second metal film22, respectively, but may be made of a different material such as copper or tungsten. The compensating lead wires23and24are connected to a controller40(to be described later). The heater is supplied with power from a heater power source30. The controller40controls the output of the heater power source30based on a signal from the thermocouple3, such that the temperature of the substrate placing surface10aof the substrate stage10becomes a predetermined temperature. In the substrate stage10configured as described above, the substrate W transferred into the processing container by a transfer mechanism (not illustrated) outside the processing container is placed on the substrate placing surface10a. When providing the electrostatic chuck12, a DC voltage is applied to the electrode14to electrostatically adsorb the substrate W. At this time, the output from the heater power source30is controlled by the controller40based on a detection signal of the temperature measuring unit3aof the thermocouple3including the first metal film21and the second metal film22, so that the temperature near the substrate placing surface10aof the stage body1is controlled. Further, the inside of the processing container is controlled to a predetermined vacuum pressure. In this state, a predetermined processing (e.g., a CVD film forming processing) is performed on the substrate W. In the related art, the temperature of the substrate stage has been measured by inserting a sheath thermocouple, configured by inserting a thermocouple wire into a metal tube, into a thermocouple insertion hole formed in the stage body. In this case, it is not always possible to insert the thermocouple near the substrate placing surface, and the temperature at the position where the temperature measuring unit of the thermocouple exists is lower than that of the substrate placing surface, and thus, the thermal responsiveness was not sufficient. As a result, it was difficult to control the temperature of the substrate placing surface with high accuracy. Particularly, when there is an electrostatic chuck, as illustrated inFIG.3, a sheath thermocouple3′ is inserted only to a position below the electrostatic chuck12, as in Japanese Patent Laid-Open Publication No. 11-251038. When the electrostatic chuck12is formed by thermal spraying, vacuum leakage occurs when drilling a hole, and it is physically difficult insert a thermocouple to the surface of the stage body1. With regard to this aspect, according to the present embodiment, the temperature measuring unit3aof the thermocouple3is formed by stacking the first metal film21and the second metal film22on the surface on the substrate placing surface10aof the stage body1. As a result, it is possible to dispose the temperature measuring unit3aat a position close to the substrate placing surface10aof the stage body1. Therefore, because of good responsiveness, it is possible to control the temperature of the substrate placing surface with high accuracy, and to control also the temperature of the substrate W with high accuracy. The present embodiment has a remarkable effect, particularly when there is a thermal sprayed electrostatic chuck into which a sheath thermocouple is not able to be inserted. Further, in the present embodiment, since the first metal film21and the second metal film22are not in point-contact or line-contact as in a thermocouple in the related art, but in surface-contact, it is also advantageous in that the temperature near the substrate placing surface of the substrate stage10may be reliably measured. Second Embodiment Subsequently, a second embodiment will be described. FIG.4is a cross-sectional view illustrating an example of a substrate stage according to a second embodiment. The second embodiment is a more specific embodiment. In the present embodiment, a substrate stage100is provided in a processing container of a processing apparatus in which a processing (e.g., a film forming processing) is performed on a substrate W (e.g., a semiconductor wafer). The substrate stage100has a substrate placing surface100aon which the substrate W is placed. The substrate stage100has a stage body101and a thermocouple103that detects a temperature near the substrate placing surface100aof the stage body101. Then, the substrate W is placed on the substrate placing surface100a, and a processing (e.g., a CVD film forming processing) is performed on the substrate W in a state where the inside of the processing container is maintained in a vacuum. The stage body101includes a base substrate111including a metal such as aluminum or titanium or a ceramic bulk material, and an electrostatic chuck112formed thereon by thermal spraying. The thermocouple103has a temperature measuring unit103aformed on the surface on the substrate placing surface side of the stage body101, that is the surface of the electrostatic chuck112in a state where a first metal film121and a second metal film122are stacked. In the temperature measuring unit103a, the first metal film121and the second metal film122are brought into contact with each other to form a circuit, and a thermo-electromotive force is generated. Therefore, the temperature of a portion near the substrate placing surface100aof the stage body101is detected. On the surface of the electrostatic chuck112, a thin insulating film130having a thickness of about 10 μm to 1,000 μm including an insulating ceramic such as alumina is formed by thermal spraying so as to cover the temperature measuring unit103aof the thermocouple103including the first metal film121and the second metal film122. A plurality of protrusions130ahaving a height of about 10 μm to 100 μm is formed on a surface of the insulating film130, and a surface of the protrusions130aserves as the surface placing surface100a. The protrusion130amay be formed by embossing the insulating film130, or may be formed of diamond-like carbon, TiN, or the like on the insulating film130. Further, as illustrated inFIG.5, a plurality of protrusions131having a height of about 0.1 μm to 100 μm may be formed of diamond-like carbon, TiN, or the like, directly on a portion of the electrostatic chuck112other than the temperature measuring unit103a, and a space may be provided between the temperature measuring unit103of the thermocouple103and the substrate W. In this case, the surface of the protrusion131serves as the substrate placing surface100a. Further, a thin insulating film up to a position lower than the protrusion131may be formed on the surface of the temperature measuring unit103a. The thickness of the first metal film121and the second metal film122is about 0.1 μm to 100 μm, and may be formed by a film forming technique such as thermal spraying, CVD, PVD, and plating. Among them, thermal spraying may be used. Examples of a combination of the first metal film121and the second metal film122may include chromel and alumel. Additionally, a combination of materials used as a thermocouple in the related art, such as a combination of platinum-rhodium alloy and platinum, and iron and constantan may be adopted. The thermocouple103includes compensating lead wires123and124connected to the first metal film121and the second metal film122, and extending vertically downward in the electrostatic chuck112. The compensating lead wires123and124may be made of the same material as the first metal film121and the second metal film122, respectively, but may be made of a different material such as copper or tungsten. The electrostatic chuck112includes a plurality of thermal sprayed layers (thermal sprayed coatings). Specifically, the electrostatic chuck112includes a first thermal sprayed layer112a, a second thermal sprayed layer112b, a third thermal sprayed layer112c, a fourth thermal sprayed layer112d, a fifth thermal sprayed layer112e, a sixth thermal sprayed layer112f, and a seventh thermal sprayed layer112g, from the base substrate111. The total thickness of the electrostatic chuck112is about 5 mm to 20 mm. The seventh thermal sprayed layer112g, which is an uppermost layer, is a dielectric layer113afor implementing electrostatic adsorption, and is made of, for example, an insulating ceramic such as alumina Al2O3. The sixth thermal sprayed layer112funder the seventh thermal sprayed layer112ghas an electrostatic adsorption electrode layer114containing, for example, tungsten. The fifth thermal sprayed layer112eunder the sixth thermal sprayed layer112fis mainly formed of an insulating layer113bcontaining, for example, an insulating ceramic such as alumina. The fourth thermal sprayed layer112dunder the fifth thermal sprayed layer112ehas a main heater layer102aand an inner heater layer102bcontaining tungsten. The third thermal sprayed layer112cunder the fourth thermal sprayed layer112dis mainly formed of an insulating layer113bcontaining, for example, an insulating ceramic such as alumina. The second thermal sprayed layer112bunder the third thermal sprayed layer112chas a heater layer102ccontaining tungsten. The first thermal sprayed layer112a, which is a lowermost layer, is formed of the insulating layer113bcontaining, for example, an insulating ceramic such as alumina. A first electrode wiring layer134aconnected to the electrode layer114and extending vertically downward is formed in the fifth thermal sprayed layer112e. Further, a second electrode wiring layer134bconnected to the first electrode wiring layer134aand extending vertically downward, a first heater wiring layer132aextending vertically downward from the main heater layer102a, and a first inner heater wiring layer133aextending vertically downward from the inner heater layer102bare formed in the third thermal sprayed layer112c. In addition to the heater layer102c, a third electrode wiring layer134cthat has one end connected to the second electrode wiring layer134band is extending horizontally, and a second inner heater wiring layer133bconnected to the first inner heater wiring layer133aand extending vertically downward are formed in the second thermal sprayed layer112b. A fourth electrode wiring layer134d, a second heater wiring layer132b, and a third inner heater wiring layer133care formed in the first thermal sprayed layer112a. The fourth electrode wiring layer134dis connected to the other end of the third electrode wiring layer134c, and extends vertically downward. The second heater wiring layer132bis connected to the heater layer102c, and extends vertically downward. The third inner heater wiring layer133cis connected to the second inner heater wiring layer133b, and extends vertically downward. The electrode wiring layers and the heater wiring layers are formed of the same material as those of the electrodes and heaters, for example, tungsten. The compensating lead wires123and124of the thermocouple103are provided in the thermal first sprayed layer112a, the second thermal sprayed layer112b, the third thermal sprayed layer112c, the fourth thermal sprayed layer112d, the fifth thermal sprayed layer112e, the sixth thermal sprayed layer112f, and the seventh thermal sprayed layer112g. The compensating lead wires123and124in the thermal sprayed layers may be formed by thermal spraying at the time of thermal spraying of each layer. Alternatively, each layer may be thermally sprayed in a state where the compensating lead wires123and124are rod-shaped and set vertically. The remaining portions of the second thermal sprayed layer112b, the fourth thermal sprayed layer112d, and the sixth thermal sprayed layer112fare the insulating layers113bcontaining, for example, insulating ceramic such as alumina. When forming each of the thermal sprayed layers, for example, an insulating layer is formed by thermal spraying of, for example, alumina, and etching is performed thereon, and then thermal spraying of an electrode, a heater, a wiring, or the like is performed on the etched portion using a mask. A through hole141is formed in the base substrate at a position corresponding to the fourth electrode wiring layer134din the first thermal sprayed layer112a, and an electrode wiring142connected to the fourth electrode wiring layer134dis drawn to the outside through the through hole141. A connecting portion between the fourth electrode wiring layer134dand the electrode wiring142is sealed by a sealing portion143made of resin or the line, and thus, leakage is prevented. Further, through holes151and161are respectively formed in the base substrate111at positions corresponding to the second heater wiring layer132band the third inner heater wiring layer133cin the first thermal sprayed layer112a. Heater wirings152and162are respectively connected to the second heater wiring layer132band the third inner heater wiring layer133c, and the heater wirings152and162are respectively drawn to the outside through the through holes151and161. A connecting portion between the second heater wiring layer132band the heater wiring152, and a connecting portion between the third inner heater wiring layer133cand the heater wiring162are respectively sealed by sealing portions153and163of resin or the like, and thus, leakage is prevented. A through hole171is formed in the base substrate111at a position corresponding to the compensating lead wires123and124in the electrostatic chuck112. Compensating lead wires173and174, which are components of the thermocouple103, respectively, are connected to the compensating lead wires123and124in the electrostatic chuck112, and the compensating lead wires173and174are drawn to the outside through the through hole171. Connecting portions between the compensating lead wires123and124in the electrostatic chuck112and the compensating lead wires173and174are sealed by a sealing portion172made of resin or the line, and thus, leakage is prevented. The electrode wiring142is connected to the electrostatic adsorption power source. Further, the heater wiring152is connected to the heater power source. The compensating lead wires173and174are connected to the controller (neither is shown inFIG.4; seeFIGS.1and2). Similarly to the first embodiment, power is supplied from a heater power source to the main heater layer102a, the inner heater layer102b, and the heater layer102c. A controller controls the output of the heater power source based on a signal from the thermocouple103such that the temperature of the substrate placing surface100aof the stage body101becomes a predetermined temperature. In the substrate stage100configured as described above, the substrate W transferred into the processing container by a transfer mechanism (not illustrated) outside the processing container is placed on the substrate placing surface100a. Then, a DC voltage is applied to the electrode114of the electrostatic chuck112to electrostatically adsorb the substrate W. At this time, the output from the heater power source is controlled by the controller based on a detection signal of the temperature measuring unit103aof the thermocouple103including the first metal film121and the second metal film122, so that the temperature near the substrate placing surface100aof the stage body101is controlled. Further, the inside of the processing container is controlled to a predetermined vacuum pressure. In this state, a predetermined processing, for example, a CVD film forming processing is performed on the substrate W. Also in the present embodiment, the temperature measuring unit103aof the thermocouple103is formed by stacking the first metal film121and the second metal film122on the surface on the substrate placing surface100aof the stage body101. As a result, it is possible to dispose the temperature measuring unit103aat a position close to the substrate placing surface100aof the stage body101. Therefore, because of good responsiveness, it is possible to control the temperature of the substrate placing surface with high accuracy, and to control also the temperature of the substrate W with high accuracy. Further, since it is possible to form the compensating lead wires123and124connected to the first metal film121and the second metal film122in the electrostatic chuck112without drilling a hole in the electrostatic chuck112formed by thermal spraying, a problem of vacuum leakage does not occur. Also in the present embodiment, similarly to the first embodiment, since the first metal film121and the second metal film122are in surface-contact, it is advantageous in that the temperature near the substrate placing surface of the substrate stage100may be reliably measured. For example, in the embodiment, the substrate stage having a specific shape is described, but the shape of the substrate stage is not limited thereto. Further, a film forming processing, particularly a CVD film forming processing is described as an example of the applied processing. However, the present disclosure is not limited thereto, and may be applied to another processing such as a PVD film forming processing or an etching processing. According to the present disclosure, a substrate stage capable of controlling a temperature of the substrate placing surface with high accuracy is provided. From the foregoing, it will be appreciated that various embodiments of the present disclosure have been described herein for purposes of illustration, and that various modifications may be made without departing from the scope and spirit of the present disclosure. Accordingly, the various embodiments disclosed herein are not intended to be limiting, with the true scope and spirit being indicated by the following claims. | 22,141 |
11862489 | DETAILED DESCRIPTION Reference will now be made in detail to various embodiments, examples of which are illustrated in the accompanying drawings. In the following detailed description, numerous specific details are set forth in order to provide a thorough understanding of the present disclosure. However, it will be apparent to one of ordinary skill in the art that the present disclosure may be practiced without these specific details. In other instances, well-known methods, procedures, systems, and components have not been described in detail so as not to unnecessarily obscure aspects of the various embodiments. An embodiment of a substrate processing apparatus will be described with reference to the accompanying drawings. FIG.1is a schematic view illustrating a configuration of a substrate processing system according to an embodiment. In the following description, in order to clarify positional relationships, an X axis, a Y axis, and a Z axis, which are orthogonal to one another, are defined, and the positive direction of the Z axis is defined as a vertically upward direction. As illustrated inFIG.1, a substrate processing system1includes a loading/unloading station2and a processing station3. The loading/unloading station2and the processing station3are provided adjacent to each other. The loading/unloading station2includes a carrier placement part11and a transport part12. A plurality of carriers C, each configured to accommodate a plurality of substrates (semiconductor wafers W in this embodiment) (hereinafter, referred to as “wafers W”) in a horizontal state, are placed in the carrier placement part11. The transport part12is provided adjacent to the carrier placement part11, and includes therein a substrate transport apparatus13and a delivery part14. The substrate transport apparatus13includes a wafer holding mechanism configured to hold a wafer W. In addition, the substrate transport apparatus13is capable of moving in the horizontal direction and the vertical direction and rotating about the vertical axis, and thus transports a wafer W between a carrier C and the delivery part14using the wafer holding mechanism. The processing station3is provided adjacent to the transport part12. The processing station3includes a transport part15and a plurality of processing units16. The plurality of processing units16are arranged side by side on both sides of the transport part15. The transport part15includes therein a substrate transport apparatus17. The substrate transport apparatus17includes a wafer holding mechanism configured to hold a wafer W. In addition, the substrate transport apparatus17is capable of moving in the horizontal direction and the vertical direction and rotating about the vertical axis. The substrate transport apparatus17transports a wafer W between the delivery part14and a processing unit16using the wafer holding mechanism. The processing unit16performs predetermined substrate processing on the wafer W transported by the substrate transport apparatus17. In addition, the substrate processing system1includes a control device4. The control device4is, for example, a computer, and includes a controller18and a storage19. In the storage19, a program for controlling various processes executed in the substrate processing system1is stored. The controller18controls the operation of the substrate processing system1by reading and executing the program stored in the storage19. Further, such a program may be stored in a computer-readable storage medium, and may be installed in the storage19of the control device4from the storage medium. The computer-readable storage medium includes, for example, a hard disk (HD), a flexible disk (FD), a compact disc (CD), a magneto-optical disc (MO), and a memory card. In the substrate processing system1configured as described above, first, the substrate transport apparatus13of the loading/unloading station2removes a wafer W from a carrier C placed in the carrier placement part11and places the removed wafer W on the delivery part14. The wafer W placed on the delivery part14is taken out from the delivery part14by the substrate transport apparatus17in the processing station3, and is loaded into a processing unit16. After being processed by the processing unit16, the wafer W loaded into the processing unit16is unloaded from the processing unit16and placed on the delivery part14by the substrate transport apparatus17. Then, the processed wafer W placed on the delivery part14is returned to the carrier C in the carrier placement part11by the substrate transport apparatus13. Next, the configuration of the processing unit16will be described with reference toFIG.2. The processing unit16includes a substrate holding/rotating mechanism30having a heating mechanism. The substrate holding/rotating mechanism30includes a rotary stage310configured to hold a wafer W in a horizontal orientation, that is, a substrate holder, and an electric motor (a rotary driver)350configured to rotate the rotary stage310around a vertical axis (a rotation axis Ax).FIG.2illustrates the rotation axis Ax and a gas passage354, which will be described later, in an overlapping state. The rotary stage310includes a chuck plate312, electric heaters314and316, a ferrite plate318, and power receiving coils320and322in this order from the upper side. A ferrite ring324is provided between the power receiving coils320and322. The chuck plate312is an overall disk-shaped member having a radius larger than that of the wafer W which is a target object. The chuck plate312may be formed of, for example, thermally conductive ceramics. Grooves313are formed in the top surface of the chuck plate312. The wafer W is attached to the top surface of the chuck plate312by applying a suction force to the grooves313in the state in which the wafer W is placed on the top surface of the chuck plate312. As the electric heaters314and316, a resistance heater, for example, may be used. As the resistance heater, a polyimide heater, for example, may be used. The electric heaters314and316are installed on the bottom surface of the chuck plate312. As illustrated inFIGS.2and3, the electric heater314is installed in a first ring-shaped region A1in the central region of the bottom surface of the chuck plate312. The electric heater314mainly heats the region A1of the chuck plate312. Hereinafter, the electric heater314will also be referred to as an “inner heater314.” The electric heater316is installed in a second ring-shaped area A2in the peripheral portion (outside the central portion) of the bottom surface of the chuck plate312. The electric heater316mainly heats the region A2of the chuck plate312. Hereinafter, the electric heater316will also be referred to as an “outer heater316.” InFIG.3, “r1” means an average of the radius of the inner peripheral edge and the radius of the outer peripheral edge of the region A1, and this is called a “first distance,” which represents a distance from the rotation axis Ax to the region A1. In addition, “r2” means an average of the radius of the inner peripheral edge and the radius of the outer peripheral edge of the region A2, and this is called a “second distance,” which represents a distance from the rotation center Ax to the region A2. The second distance r2is greater than the first distance r1. The region of the chuck plate312covered by one electric heater is also called a “heating zone.” In the case of this embodiment, two heating zones (an inner heating zone A1and an outer heating zone A2) are set. Further, the heat generated by the inner heater314also heats the outer heating zone, and the heat generated by the outer heater316also heats the inner heating zone. However, if the chuck plate312is formed sufficiently thin, it is possible to perform temperature control without considering that the inner heater314heats the outer heating zone and the outer heater316heats the inner heating zone. When polyimide heaters are used as the electric heaters314and316, the electric heaters314and316may be formed by an inner heater pattern and an outer heater pattern formed on a common polyimide base material. Although not illustrated inFIG.3, the heater patterns of the electric heaters314and316are formed by resistance-heating elements that meander and extend in the regions A1and A2, respectively. Instead of the polyimide heaters, another type of electric heater, for example, ceramic heaters, may be used. When the ceramic heaters are used, the resistance-heating elements may be embedded in the chuck plate312. The power receiving coils320and322may be thin (doughnut-shaped) coils having an axis (coil axis) extending in the vertical direction. The axes of the two coils320and322described above substantially coincide with the rotation axis Ax. The power receiving coil320is installed in the central portion of the bottom surface of the disk-shaped ferrite plate318. Hereinafter, the power receiving coil320will also be referred to as an “inner power receiving coil320.” The power receiving coil322is installed in the peripheral portion of the bottom surface of the ferrite plate318. Hereinafter, the power receiving coil322will also be referred to as an “outer power receiving coil322.” An annular ferrite ring324is installed between the inner power receiving coil320and the outer power receiving coil322. When the rotary stage310is viewed from directly above, the regions in which the power receiving coils320and322are located substantially coincide with the first and second ring-shaped regions A1and A2in which the electric heaters314and316are arranged. When the processing unit16is configured to process a 12-inch wafer, as an example, the inner power receiving coil320may have an inner diameter of about 30 mm and an outer diameter of about 70 mm, and the outer power receiving coil322may have an inner diameter of about 70 mm (+the width of the ferrite ring) and an outer diameter of about 140 mm. The winding line of the inner power receiving coil320is electrically connected to the inner heater314. The winding line of the outer power receiving coil322is electrically connected to the outer heater316. The upper end of the rotary shaft352of the electric motor350is connected to the center of the bottom surface of the chuck plate312. The chuck plate312is integrally connected to the electric heaters314and316, the ferrite plate318, the power receiving coils320and322, and the ferrite ring324. Therefore, by operating the electric motor350, the members312,314,316,318,320,322and324integrally rotate around the vertical axis (the rotation axis Ax). Inside the rotary shaft352of the electric motor350, the gas passage354for transmitting a suction force to the grooves313in the top surface of the chuck plate312is formed. The gas passage354is connected to a vacuum pump356and a gas supply source358via a rotary joint355attached to the lower end of the rotary shaft352. A switching valve device360including, for example, a three-way valve, is installed in the gas passage354in order to select only one of the vacuum pump356and the gas supply source358. By suctioning the inner space of the groove313by the vacuum pump356, the wafer W placed on the chuck plate312is attached to the chuck plate312. By supplying the suction release gas such as nitrogen gas from the gas supply source358to the grooves313, the attachment of the wafer W to the chuck plate312is released. An inner power feeding coil402and an outer power feeding coil404are installed below the inner power receiving coil320and the outer power receiving coil322with a vertical gap G therebetween. The inner power feeding coil402and the outer power feeding coil404are thin (doughnut-shaped) coils having an axis (a coil axis) extending in the vertical direction. The axes of the two coils402and404described above substantially coincide with the rotation axis Ax. The gap G is preferably 10 mm or less, and more preferably 5 mm or less. From the viewpoint of power feeding efficiency, the size of the gap G is preferably smaller. However, the minimum value of the size of the gap G is limited from the viewpoint of manufacturing precision of the rotary stage310, which is a rotating body, and prevention of collision with the power feeding member400due to, for example, shaking during operation. The inner power feeding coil402and the outer power feeding coil404are installed on the top surface of a disk-shaped ferrite plate406. When the rotary stage310is viewed from directly above, the arrangement regions of the power feeding coils402and404are the same or substantially the same as the arrangement regions of the power receiving coils320and322. Therefore, regardless of the rotation phase (angular position) of the chuck plate312, the inner power feeding coil402always faces the inner power receiving coil320in the direction of the rotation axis Ax, and the outer power feeding coil404faces the outer power receiving coil322in the direction of the rotation axis Ax. An annular ferrite ring408is installed between the inner power feeding coil402and the outer power feeding coil404. In order to simplify the technology below, the assembly of the inner power feeding coil402, the outer power feeding coil404, the ferrite plate406, and the ferrite ring408will also be referred to as a “power feeding member400.” FIG.4schematically illustrates an arrangement of the inner power receiving coil320and the outer power receiving coil322on the ferrite plate318. The arrangement of the inner power feeding coil402and the outer power feeding coil404on the ferrite plate406is the same. As illustrated inFIG.2, the inner power feeding coil402and the outer power feeding coil404are supplied with radio-frequency power having a frequency of, for example, about 1 kHz to 4 MHz from a radio-frequency power supply unit410. The radio-frequency power supply unit410has an inner coil power feeding part412for supplying radio-frequency power to the inner power feeding coil402, and an outer coil power feeding part414for supplying radio-frequency power to the outer power feeding coil404. By supplying radio-frequency power to the inner power feeding coil402and the outer power feeding coil404, current flows through the inner power receiving coil320and the outer power receiving coil322by electromagnetic induction. This current causes the inner heater314and the outer heater316to generate heat. As described above, power is wirelessly fed to the inner heater314and the outer heater316. Hereinafter, in order to simplify the technology, the wireless power feeding system to which the inner power feeding coil402and the inner power receiving coil320belong will also be referred to as an “inner power feeding channel,” and the wireless power feeding system to which the outer power feeding coil404and the outer power receiving coil322belong will also be referred to as an “outer power feeding channel.” The inner coil power feeding part412and the outer coil power feeding part414supply radio-frequency power having different frequencies. The resonance frequency of the circuit (resonance circuit) including the inner power receiving coil320and the inner heater314is adapted to substantially match the frequency of the radio-frequency power supplied by the inner coil power feeding part412. In addition, the resonance frequency of the circuit (resonance circuit) including the outer power receiving coil322and the outer heater316is adapted to substantially match the frequency of the radio-frequency power supplied by the outer coil power feeding part414. This makes it possible to prevent mutual interference between the inner power feeding channel and the outer power feeding channel. The power receiving coils320and322mainly provide an inductance L in the resonance circuit, and the electric heaters314and316mainly provide a resistance R in the resonance circuit. In order to adjust the resonance frequency of the resonance circuit, a capacitor having a capacitance C may be provided in the circuit described above. It is preferable to use a capacitor having a fixed capacitance. The resonance frequency may be adjusted according to the known principle of LCR resonance circuits. FIG.5schematically illustrates a relationship between frequency and output voltage of a power receiving coil. For example, the circuit including the inner power receiving coil320may be configured to have a characteristic indicated by the leftmost curve, and the circuit including the outer power receiving coil322may be configured to have a characteristic indicated by the second curve from the left. As illustrated inFIG.5, it is preferable that the frequencies at which the output voltage exhibits a peak value, that is, the resonance frequencies, are sufficiently spaced apart from each other such that the characteristic curves, in which mutual interference between the power feeding channels is a problem, do not overlap each other. In the case of providing more than two power feeding channels, design may be made based on the same concept. Ferrite acts as an electromagnetic shield. For this reason, it is possible to prevent the electronic devices constituting the processing unit16above the ferrite plate318and below the ferrite plate406from malfunctioning due to electromagnetic waves. In addition, it is possible to prevent the electronic devices or semiconductor devices already formed on a wafer W from being damaged by an abnormal temperature increase due to radio-frequency induction heating. By providing the ferrite rings324and408, it is possible to prevent mutual interference between the inner power feeding channel and the outer power feeding channel. As a result, it becomes possible to individually control the amount of heat generated by the inner heater314and the outer heater316with high precision. Since it is difficult for eddy current to flow in the ferrite, abnormal heat generation due to radio-frequency induction heating does not occur in the ferrite plates318and406and the ferrite rings324and408, and since it is possible to suppress power loss to a low level, power feeding efficiency is also improved. For example, it has been confirmed through tests that power feeding efficiency of about 90% was obtained. Above the chuck plate312of the rotary stage310, non-contact temperature sensors52and54are provided. The non-contact temperature sensors52and54may be, for example, infrared (IR) temperature sensors. The temperature sensor52is capable of detecting the temperature of the central portion of the top surface of the chuck plate312or the central portion of the wafer W placed on the chuck plate312, and will also be referred to as an “inner temperature sensor52.” The temperature sensor54is capable of detecting the temperature of the peripheral portion of the top surface of the chuck plate312or the peripheral portion of the wafer W placed on the chuck plate312, and will also be referred to as an “outer temperature sensor54.” The operation of the radio-frequency power supply unit410is controlled by a temperature controller420. The temperature detected by the inner temperature sensor52and the outer temperature sensor54are input to the temperature controller420. The inner temperature sensor52, the outer temperature sensor54, and the temperature controller420may be connected by a wire. Based on the difference between the temperature detected by the inner temperature sensor52and the set temperature, the temperature controller420controls feedback of the power feeding to the inner power feeding coil402by the inner coil power feeding part412. Based on the difference between the temperature detected by the outer temperature sensor54and the set temperature, the temperature controller420controls feedback of power feeding to the outer power feeding coil404by the outer coil power feeding part414. The feedback control may be, for example, PID control or ON/OFF control. As the ON/OFF control, hysteresis control may be used, for example, when the values detected by the temperature sensors52and54exceed an OFF set temperature (e.g., a target temperature +2 degrees C.), the power feeding is turned off, and when the values detected by the temperature sensor fall below an ON set temperature (e.g. the target temperature −2 degrees C.), the power feeding is turned on. The control of the supplied power in the PID control may be performed by duty control of, for example, pulse width modulation (PWM) (which is microscopically a control involving ON/OFF operation, but is different from the ON/OFF control described above). In both cases of performing hysteresis (ON/OFF) control and performing duty control, it is preferable to turn on/off the power feeding in the vicinity of zero volts of an AC load voltage. As a result, it is possible to suppress the generation of switching noise and inrush current. Instead of the non-contact-type temperature sensors52and54described above, a contact-type temperature sensor (not illustrated) embedded in the chuck plate312may be used. In this case, the temperature detected by the contact-type temperature sensor may be transmitted to the temperature controller420by a wireless transmission device that operates using the power extracted from at least one of the inner power receiving coil320and the outer power receiving coil322. However, in the rotary stage310, which rotates at a relatively high speed and is located in a strong electromagnetic field, it is preferable to avoid installation of a device (actuator) that performs electrical operations such as switching, control, and transmission/reception (e.g., SSR or MPU), or a device that performs mechanical operations as much as possible. The processing unit16is provided with a processing liquid supply part60configured to supply a processing liquid, such as a chemical liquid (e.g., an etching liquid or a cleaning liquid), a rinsing liquid, a drying solvent, or a drying gas, to a surface (the surface to be processed) of a wafer W held by the substrate holding/rotating mechanism30. The processing fluid supply part60includes at least one nozzle62, at least one nozzle arm64(a nozzle moving mechanism) configured to carry and move the nozzle62, and a processing fluid supply mechanism66configured to supply a processing liquid to the nozzle62. The nozzle arm64is capable of moving the carried nozzle62between a processing position above the center of the wafer W and a standby position outside the wafer W. Although not illustrated in detail, the processing liquid supply mechanism66includes, for example, a factory power source, a pipe (pipeline) connected to a processing liquid supply source, such as a tank and a cylinder, and a flow control device (e.g., an opening/closing valve, a flow meter, or a flow rate control valve) disposed in the pipe. The processing unit16has a liquid receiving cup70installed around the substrate holding/rotating mechanism30so as to collect the processing liquid scattered from the rotating wafer W. The liquid receiving cup70has an exhaust port72for evacuating the internal space in the liquid receiving cup70, and a drain port74for discharging the liquid from the liquid receiving cup70. The processing unit16has a chamber (housing), which is not illustrated inFIG.2, and the components illustrated inFIG.2are arranged in this chamber. A fan filter unit (FFU) may be installed on the ceiling of the chamber. An upper protective cover81and a lower protective cover82are installed to protect the constituent elements of the rotary stage310and the constituent elements of the power feeding member400from a corrosive atmosphere (e.g., an atmosphere derived from a chemical liquid). The upper protective cover81covers the periphery of the rotary stage310, which is a rotating body, and the lower protective cover82covers the periphery of the power feeding member400, which is a non-rotating body. The lower end of the upper protective cover81and the upper end of the lower protective cover82are configured to form a non-contact seal84, for example, a labyrinth seal, as schematically illustrated inFIG.2. This makes it possible to prevent the mist of a processing liquid from entering the space inside the upper protective cover81and the lower protective cover82from the space outside the upper protective cover81and the lower protective cover82while enabling the upper protective cover81and the lower protective cover82to rotate relative to each other. The mist of the processing liquid may be prevented from entering the space inside the upper protective cover81and the lower protective cover82from the space outside the upper protective cover81and the lower protective cover82by increasing the pressure inside the upper protective cover81and the lower protective cover82by supplying gas to the space inside the upper protective cover81and the lower protective cover82. As illustrated inFIG.2, the lower end of the lower protective cover82may be connected to the liquid receiving cup70. Each of the constituent elements of the rotary stage310and the constituent elements of the power feeding member400includes one or more, preferably three or more, lift pin holes92and94(only one of the lift pin holes92and only one of the lift pin holes94being illustrated inFIG.2). When the lift pin holes92and94penetrate the ferrite as in the exemplary configuration illustrated inFIG.2, eddy current having a problematic size is not generated by magnetic flux leaking through the holes having a size similar to that of the lift pine holes92and94. In the case of adopting a configuration in which the lift pin holes92and94penetrate the portion in which no ferrite is present, it is preferable to surround at least the outer peripheries of the lift pin holes with a magnetic material (ferrite) in order to suppress the influence of eddy current. A lift pin98which is raised and lowered by a linear actuator96(e.g., an air cylinder) is inserted into each lift pin hole94in the power feeding member400. When the rotary stage310is positioned at a specific angular position (rotation phase) such that the lift pin holes92in the rotary stage310and the lift pin holes94in the power feeding member400are aligned, it is possible to raise and lower the lift pins98through the lift pin holes92in the rotary stage310. The wafer W placed on the chuck plate312can be lifted by raising the tips of the lift pins98to a position above the top surface of the chuck plate312. In this state, the wafer W can be delivered between the lift pins98and the arm of the substrate transport apparatus17(seeFIG.1). The wafer W can be placed on the top surface of the chuck plate312by lowering the tips of the lift pins98supporting the wafer W to a position below the top surface of the chuck plate312. The liquid processing of a wafer W performed by the processing unit16will be briefly described. The wafer W loaded into the processing unit16is attached to the chuck plate312by suction. In this state, by operating the electric motor350, the wafer W held by the chuck plate312is rotated. At this time, power is fed from the radio-frequency power supply unit410to the inner power feeding coil402and the outer power feeding coil404. As a result, a current generated by electromagnetic induction flows from the inner power receiving coil320to the inner heater314and then from the outer power receiving coil322to the outer heater316. By the feedback control described above, the temperature of the central portion of the wafer W heated by the inner heater314and the temperature of the peripheral portion of the wafer W heated by the outer heater316are respectively controlled to desired values. A processing liquid, such as a chemical liquid, is supplied to the surface of the wafer W from the nozzle62of the processing fluid supply part60in the central portion of the surface of the rotating wafer W, the temperature of which is controlled, whereby chemical liquid processing is performed on the surface of the wafer W. By moving the nozzle62, a liquid application point of the chemical liquid ejected from the nozzle62on the wafer surface may be moved (e.g., reciprocated between the central portion and the peripheral portion of the wafer). After the completion of the chemical liquid processing, the processing liquid supply part60may perform a rinsing process by supplying a rinsing liquid (e.g., pure water (DIW)) to the wafer W, and may then perform a drying process (e.g., a centrifugal drying process) of the wafer W. Between the rinsing process and the drying process, a drying fluid replacement process may be performed, in which the rinsing liquid is replaced with a drying fluid such as isopropyl alcohol (IPA). When performing the drying process, IPA and a drying gas, such as nitrogen gas, may be simultaneously supplied to the wafer W. Heating by the inner heater314and the outer heater316may be performed only when performing the chemical liquid processing. In order to accelerate drying, heating by the inner heater314and the outer heater316may be performed during the drying process (that is, when the processing liquid is not supplied to the wafer W). According to the embodiment described above, it is possible to heat the wafer W by the electric heater through non-contact power feeding from the non-rotating power feeding coil (power transmission coil) to the power receiving coil rotating together with the chuck plate holding the wafer W and the electric heater. A complicated contact-type mechanism for feeding power to the rotating electric heater (e.g., a power feeding mechanism using a rolling bearing or a snap ring) is not necessary. According to the embodiment described above, it is possible to heat the wafer W through the chuck plate312, regardless of whether the rotary stage310(a substrate holding part) is rotating or not, and regardless of the rotation speed. Even when the liquid processing of the wafer W is performed at a high temperature, it is possible to perform the liquid processing of the wafer W while rotating the wafer W. Therefore, it is possible to process the wafer W while removing a reaction product from the surface of the wafer W, and thus liquid processing quality can be improved. According to the embodiment described above, by supplying the chemical liquid at normal temperature to the wafer W which is heated and rotated, it is possible to perform the liquid processing while maintaining the temperature of the interface between the surface of the wafer W and the chemical liquid high. In this case, since it is not necessary to heat the chemical liquid before supplying the same, it is possible to suppress consumption of the chemical liquid. According to the embodiment described above, since the current controlled through the inner power receiving coil320and the outer power receiving coil322is supplied to the inner heater314and the outer heater316, it is possible to control the amount of heat generated by the heaters314and316, and hence to control the temperature of the wafer W with high precision. According to the embodiment described above, compared to, for example, the case of adopting a method of heating a metal heating member provided in the chuck part by radio-frequency induction heating, it is possible to control the temperature and temperature distribution of the wafer W more precisely. Therefore, it is possible to improve liquid processing quality. Further, according to the embodiment described above, it is possible to independently control the temperature of the central portion of the wafer and the temperature of the peripheral portion of the wafer using the inner heater314and the outer heater316. Therefore, by increasing the amount of heat generated by the heater314or316corresponding to a region of the wafer W, in which the temperature tends to be lower, to be higher than that of the other heater, it is possible to make the temperature at the interface between the wafer surface and the processing liquid uniform in the plane of the wafer W. Therefore, it is possible to improve the in-plane uniformity of processing. The following are examples of the causes of the temperature difference between the central portion and the peripheral portion of a wafer. (1) The relative velocity between the atmosphere (e.g., air) surrounding the wafer W and the surface of the wafer W is higher at the peripheral portion where the peripheral velocity (distance r from the rotation center of the wafer in a radial direction×angular velocity ω) is higher. Thus, the peripheral edge of the wafer W is easily cooled. (2) When a high-temperature processing liquid is supplied to the central portion of the wafer W having a temperature lower than the temperature of the processing liquid, the processing liquid spreads to the peripheral portion of the wafer W while heat is transferred therefrom to the wafer W. Thus, the temperature of the processing liquid decreases toward the peripheral edge. (3) When supplying a highly volatile processing liquid to the central portion of the wafer W, heat removed from the wafer W by vaporization of the processing liquid increases toward the peripheral edge. Next, a first modification of the present embodiment described above will be described. In the first modification, as illustrated inFIG.6, on the top surface of the ferrite plate406, there is provided only one large doughnut-shaped power feeding coil402A centered on the rotation axis Ax. Two power receiving coils320and322described above with reference toFIG.3are installed on the bottom surface of the ferrite plate318. Electric heaters314and316are electrically connected to the power receiving coils320and322, respectively. When the rotary stage310is viewed from directly above, the arrangement regions of the power receiving coils320and322are included in the arrangement region of the large power feeding coil (the first power feeding coil)402A. That is, the large power feeding coil402A is arranged to face both the power receiving coils320and322, regardless of the rotation phase of the rotary stage. In the first modification, the radio-frequency power supply unit410is configured as a radio-frequency power supply unit, the output frequency of which is variable. That is, the radio-frequency power supply unit410is configured to be capable of selectively supplying, to the power feeding coil402A, a frequency corresponding to (substantially the same as) the resonance frequency of the resonance circuit to which the power receiving coil320belongs (a first resonance frequency) and a frequency corresponding to the resonance frequency of the resonance circuit to which the power receiving coil322belongs (a second resonance frequency). In this case, the radio-frequency power supply unit410may include a first coil power feeding part412configured to steadily output the radio-frequency power having the first resonance frequency, a second coil-feeding part414configured to steadily output the radio-frequency power having the second resonance frequency, and a switch configured to electrically connect only one of the first coil power feeding part412and the second coil power feeding part414to the power feeding coil402A. Alternatively, the radio-frequency power supply unit410may have a single coil power feeding part having a variable output frequency. The radio-frequency power supply unit410may include a zero-cross circuit. It is possible to selectively heat the electric heaters314and316by switching the frequency output from the radio-frequency power supply unit410. By switching the frequency output from the radio-frequency power supply unit410at high speed, it is possible to cause the electric heaters314and316to be heated substantially at the same time. By adjusting the ratio of the energization times of the electric heaters314and316, it is possible to control the ratio of the amount of heat generated by the electric heaters314and316. Next, a second modification will be described. As illustrated inFIG.7, the second modification includes a plurality of (eight in the illustrated example) inner power receiving coils320S and a plurality of (eight in the illustrated example) outer power receiving coils322S. Like the inner power receiving coil320described above, the plurality of inner power receiving coils320S are arranged in a ring-shaped region A1in which the distance from the rotation axis Ax (the first distance r1) is relatively small. Further, the plurality of inner power receiving coils320S are arranged at different circumferential positions in the ring-shaped region A1at equal intervals in the circumferential direction. Like the outer power receiving coil322described above, the plurality of outer power receiving coils322S are arranged in a ring-shaped region A2in which the distance from the rotation axis Ax (the first distance r2) is relatively large. The plurality of outer power receiving coils322S are arranged at different circumferential positions in the ring-shaped region A2at equal intervals in the circumferential direction. In the second modification, one electric heater (not illustrated) is electrically connected to one inner power receiving coil320S so as to form one resonance circuit. The resonance frequencies of the resonance circuits belonging to different inner power receiving coils320S are different from each other. One electric heater (not illustrated) is electrically connected to one outer power receiving coil322S so as to form one resonance circuit. The resonance frequencies of resonance circuits belonging to different outer power receiving coils322S are different from each other. In this second modification, a plurality of recesses having shapes matching the shapes of the power receiving coils320S and322S and the power feeding coils402S and404S may be formed on the bottom surface of the ferrite plate318and the top surface of the ferrite plate406. One coil may be stored in each recess. In this case, the ferrite ring may not be provided. The radio-frequency power supply unit410is installed with one coil power feeding part for one power feeding coil402S or404S. Different coil power feeding parts supply radio-frequency power of different frequencies. In the second modification, while the rotary stage310is rotating, when the power receiving coils320S or322S face the power feeding coils420S or404S supplied with radio-frequency power of a frequency corresponding to the resonance frequency of the resonance circuit, which belongs to the power receiving coil, in the direction of the rotation axis Ax, sufficiently large current flows through the electric heater connected to the power receiving coil. In addition, in the second modification, by positioning the rotary stage310such that the resonance frequency of the power receiving coils facing the power feeding coils matches with the frequency of power fed to the power feeding coils, it is possible to supply sufficiently large current to all of the power receiving coils when the rotation of the rotary stage310is stopped. According to the second modification, it is possible to set a plurality of heating zones along the circumferential direction. Therefore, even if a non-uniform temperature distribution occurs along the circumferential direction of the wafer W, it is possible to eliminate or reduce the same. When a plurality of heating zones are set at the same radial position as in the second modification, it is preferable to control power feeding from the radio-frequency power supply unit410through the temperature controller420using a contact-type temperature sensor embedded into the chuck plate312. Various other modifications are possible. For example, the arrangement of the power feeding coil illustrated inFIG.4and the arrangement of the power receiving coils illustrated inFIG.7may be combined. In this case, in the radio-frequency power supply unit410, radio-frequency power is supplied to the inner power feeding coil402and the outer power feeding coil404illustrated inFIG.4from the variable-frequency inner coil power feeding part412and outer coil power feeding part414. From the viewpoint of ease of manufacture, when the rotary stage310is viewed from above, it is preferable that the heating zone (heater arrangement region) and the power receiving coil arrangement region be the same or substantially the same (see, for example,FIGS.3and4). However, since the electric heaters and the power receiving coils are connected by a wire, the heaters and coils do not necessarily have to have such an arrangement. It should be understood that the embodiments disclosed herein are illustrative and are not limiting in all aspects. The above-described embodiments may be omitted, replaced, or modified in various forms without departing from the scope and spirit of the appended claims. Processing performed on a wafer W is not limited to liquid processing such as wet etching processing or chemical liquid cleaning processing, and may be coating processing for applying a film, such as a resist film or an antireflection film, to the surface of the wafer W. In the case of the coating processing, in addition to applying a film forming liquid while heating the wafer W, it is possible to bake the wafer W, for example, immediately after the film forming liquid is applied while rotating the wafer W. The substrate which is a target object is not limited to a semiconductor wafer, but may be any of various substrates used in the semiconductor device manufacturing field, such as a glass substrate or a ceramic substrate. According to the present disclosure, it is possible to control the temperature distribution of a substrate with high precision. While certain embodiments have been described, these embodiments have been presented by way of example only, and are not intended to limit the scope of the disclosures. Indeed, the embodiments described herein may be embodied in a variety of other forms. Furthermore, various omissions, substitutions and changes in the form of the embodiments described herein may be made without departing from the spirit of the disclosures. The accompanying claims and their equivalents are intended to cover such forms or modifications as would fall within the scope and spirit of the disclosures. | 42,247 |
11862490 | REFERENCE NUMERALS 11—furnace tube body;12—furnace bottom;13—pedestal;14—cassette;15—first heater;16—second heater;17—gas intake tube;18—exhaust port;19—vertical tube;20—reaction chamber;100—manipulator;141—supporting post;142—supporting part;143—base. DESCRIPTION OF EMBODIMENTS In order to make the object, technical solution and advantages of the present application clearer, the embodiments of the present application will be further described in detail below in conjunction with specific embodiments and with reference to the accompanying drawings. It should be understood that these descriptions are merely exemplary rather than intended to limit the scope of the present application. In addition, descriptions of well-known structures and technologies are omitted in the following description in order to avoid the unnecessary confusion of the concept of the present application. Referring toFIGS.1to3, the embodiments of the present application provide a diffusion furnace, including: a furnace tube structure including a furnace tube body11and a furnace bottom12, a bottom of the furnace tube body11being connected to the furnace bottom12to form a reaction chamber20; and a carrying structure including a pedestal13and a plurality of cassettes14disposed on the pedestal13, the pedestal13being disposed on the furnace bottom12. Three, four, five or more cassettes14may be disposed. Referring toFIG.4, a single cassette14includes a plurality of supporting posts141and a plurality of supporting parts142, with the plurality of supporting parts142evenly distributed at intervals along a vertical direction of the supporting posts141, and wafers are disposed on the supporting parts142. The wafers are carried by the cassettes and sequentially arranged in a single row from the top down. A height of a single original cassette structure is normally set as 144 slots, with a wafer being capable of being disposed on each slot. Four cassette structures may be disposed, that is, 50 slots may be designed on each cassette14, 200 slots in total. Therefore, a height of the furnace tube body11can be decreased and a width of the furnace tube body11can be increased, thus enlarging a space of equipment repair and maintenance, which is favorable for the repair and maintenance of the equipment. Moreover, a decrease in a height of the reaction chamber20reduces a difference between upper and lower reaction conditions, so that a difference in filming quality of the wafers can be reduced, increasing the yield of products. Furthermore, since the difference between the upper and lower reaction conditions is reduced, the process time can be shortened, increasing the efficiency of production. In some embodiments, the wafers are carried by the cassettes and sequentially arranged in a single row from the top down. The height of a single original cassette structure is normally set as 144 slots, with a wafer being capable of being disposed on each slot. Three cassette structures may be disposed, that is, 60 slots may be designed on each cassette14, 180 slots in total. Therefore, a height of the furnace tube body11can be decreased and a width of the furnace tube body11can be increased (i.e., a diameter of the reaction chamber20is increased), thus enlarging a space of equipment repair and maintenance, which is favorable for the repair and maintenance of the equipment. Moreover, a decrease in a height of the reaction chamber20reduces a difference between upper and lower reaction conditions, so that a difference in filming quality of the wafers can be reduced, increasing the yield of products. Furthermore, since the difference between the upper and lower reaction conditions is reduced, the process time can be shortened, increasing the efficiency of production. In some embodiments, the wafers are carried by the cassettes and sequentially arranged in a single row from the top down. The height of a single original cassette structure is normally set as 144 slots, with a wafer being capable of being disposed on each slot. Five cassette structures may be disposed, that is, 40 slots may be designed on each cassette14, 200 slots in total. Therefore, a height of the furnace tube body11can be decreased and a width of the furnace tube body11can be increased (i.e., a diameter of the reaction chamber20is increased), thus enlarging a space of equipment repair and maintenance, which is favorable for the repair and maintenance of the equipment. Moreover, a decrease in a height of the reaction chamber20reduces a difference between upper and lower reaction conditions, so that a difference in filming quality of the wafers can be reduced, increasing the yield of products. Furthermore, since the difference between the upper and lower reaction conditions is reduced, the process time can be shortened, increasing the efficiency of production. In some embodiments, the pedestal13is rotatably connected to the furnace bottom12. A rotary shaft may be disposed at a center of the pedestal13. The pedestal13may be rotated relative to the furnace bottom12, so that the plurality of cassettes14on the pedestal13can be synchronously rotated. Thus, a concentration of the reactive gas in the reaction chamber20can be more uniform, which contributes to the more uniform formation of a film thickness of the wafers, and consequently, a uniform filming effect and a uniform filming quality are achieved, reducing the difference. In some embodiments, the cassettes14are rotatably connected to the pedestal13. The cassette14may further include a base143, supporting posts141may be fixed on the base143, and a rotary shaft may be disposed at the bottom of the base143, so that the cassette14can be rotated relative to the pedestal13. Therefore, each cassette14can be separately rotated, further stirring the reactive gas in the reaction chamber20, so that the concentration of the reactive gas in the reaction chamber20can be more uniform and temperature distribution in the reaction chamber20can be more uniform to reduce a temperature difference in the reaction chamber20, achieving the uniform heating of surfaces of the wafers and the uniform contact between the surfaces of the wafers and the reactive gas, which contributes to the more uniform formation of the film thickness of the wafers, and consequently, a uniform filming effect and a uniform filming quality are achieved, reducing the difference. In one embodiment of the present application, the furnace tube body11and the furnace bottom12are arranged to move up and down relative to each other. In some embodiments, the furnace tube body11may be arranged to move up and down, and second heaters16and a gas path system on the furnace tube body11may move up and down together, while the furnace bottom12may be stationary. In some embodiments, the furnace bottom12may be arranged to move up and down, so that the carrying structure on the furnace bottom12can move up and down together, while the furnace tube body11may be stationary. The direction of an arrow shown inFIG.2is a direction along which the furnace tube body11or the furnace bottom12moves up and down. In some embodiments, the plurality of the cassettes14are distributed in a circumferential array at intervals along a central axis of rotation of the pedestal13and the furnace bottom12. Optionally, a number of the cassettes14is set as four. Since the cassettes14can be separately rotated and the pedestal13can be rotated relative to the furnace bottom12, the cassettes can be rotated separately or together. The cassettes14may be evenly distributed in a circumferential array at intervals on the pedestal13, and a width direction or diameter of the reaction chamber20may be designed to be optimized and minimized. In addition, during taking off and placing wafers, each cassette14is required to be rotated to the fixed position A, and the wafers are then handled by a manipulator100. Thus, the pedestal13can be rotated and accurately positioned, so that each cassette14can be rotated clockwise and accurately stopped at the fixed position A. Therefore, the wafers on the four cassettes14can be transferred, taken off or placed by the same set of manipulator100without adding extra transfer cost. The direction of an arrow shown inFIG.3is a direction of rotation of the pedestal13. In some embodiments, each of the cassettes is arranged to be separately rotated relative to the pedestal; and/or the plurality of cassettes are arranged to be rotated together relative to the furnace bottom through the pedestal. In some embodiments, a first heater15is disposed at a center surrounded by the plurality of cassettes14, and is connected to the pedestal13. By adding the first heater15at the center surrounded by the four cassettes14, the problem of nonuniform heating of the wafers caused by the increased diameter of the reaction chamber can be solved. In some embodiments, the furnace tube structure further includes second heaters16, which are distributed outside the furnace tube body11. The second heaters16are disposed on an outer sidewall and top of the furnace tube body11and combined with the first heater15disposed at the center of the reaction chamber20, so that the problem of low center temperature and top temperature caused by the increased diameter of the reaction chamber can be solved, enabling the wafers to be heated more uniformly. Under a same temperature, film thicknesses are different due to a concentration problem of the reactive gas, but adjusting the temperature to solve the concentration problem will make film thickness etch rates different. Since the reaction chamber is of a vertical structure, there exists a problem in the entry and discharge of the gas, leading to nonuniform gas concentrations at different heights in the reaction chamber. Aimed at these problems, the applicant of the present application also adopts the following technical solution: the furnace tube structure further includes a gas path system configured to supply the reactive gas to the reaction chamber20; the gas path system includes a gas intake tube17, an exhaust port18and vertical tubes19communicated with the gas intake tube, with the gas intake tube17disposed on the furnace tube body11and close to the bottom of the furnace tube body11and the exhaust port18disposed at the top of the furnace tube body11and communicated with the reaction chamber20; and the reactive gas in the vertical tubes19is blown to gaps between the wafers spaced in a vertical direction. The vertical tube19may be provided with a plurality of blowholes, which are evenly arranged at intervals along a vertical direction of the vertical tube19, a bottom end of the vertical tube19is communicated with the gas intake tube17, and thus, the reactive gas can sequentially be blown to the gap between each two wafers spaced in the vertical direction from the bottom up, so that the surfaces of the wafers can be in uniform contact with the reactive gas. The exhaust port18may be disposed at a central position of the top of the furnace tube body11. As shown inFIG.1, the direction of an arrow is a direction along which the reactive gas enters the reaction chamber20from the gas intake tube17and the gas discharged from the exhaust port18flows. Thus, the flow of the reactive gas can circulate from the bottom up in a smoother manner, and consequently, the entry and discharge of the gas better meet the law of gas flow. Moreover, since the cassettes14can be rotated together and/or separately, gas concentrations at different heights in the reaction chamber can be more uniformly dispersed, which contributes to the more uniform formation of the film thickness of the wafers, and consequently, a uniform filming effect and filming quality is achieved, reducing the difference, and the process time can be shortened, increasing the efficiency of production. In some embodiments, the vertical tubes19are distributed in a circumferential array at intervals along the central axis of rotation of the pedestal13and the furnace bottom12. The vertical tubes19are in one-to-one correspondence with the cassettes14, which are located between the vertical tubes19and the first heater15. The vertical tubes19are disposed outside the cassettes14, and each vertical tube19may be disposed in one-to-one correspondence with each cassette14. The vertical tubes19may be disposed on diameters of two opposite cassettes14passing through the center of rotation of the pedestal13and the furnace bottom12. Thus, the reactive gas can sequentially be blown to the gap between each two wafers spaced in the vertical direction from the bottom up, reach the center and then get out from the exhaust port18, so the flow of the reactive gas can circulate from the bottom up and from the outside to the inside in a smoother manner, enabling the surfaces of the wafers to be in uniform contact with the reactive gas. In an exemplary embodiment, the gas intake tube includes a main gas inlet and an annular tube communicated with the main gas inlet, with the annular tube circularly disposed along the plurality of cassettes, and the vertical tubes19are communicated with the annular tube. The reactive gas can enter the annular tube from the main gas inlet, then respectively enter the vertical tubes19and sequentially be blown to the gap between each two wafers spaced in the vertical direction via the blowholes from the bottom up, so that the surfaces of the wafers can be in uniform contact with the reactive gas. Alternatively, a plurality of gas intake tubes17are disposed to be in one-to-one correspondence with and communicated with the vertical tubes19, and thus, the gas intake tubes17are distributed at intervals along the furnace tube body11. In some embodiments, the furnace tube structure further includes a gas path system configured to supply the reactive gas to the reaction chamber, and the gas path system includes a gas intake structure and an exhaust structure, both of which are disposed on the furnace tube body and communicated with the reaction chamber. The reactive gas enters the reaction chamber20via the gas intake structure, is blown to the gaps between the wafers spaced in the vertical direction and carried by the cassettes14and then gets out via the exhaust structure. Both the gas intake structure and the exhaust structure may be disposed on the furnace tube body11, the gas intake structure may be disposed at the bottom of the furnace tube body11, and the exhaust structure may be disposed at the top of the furnace tube body11; or the gas intake structure may be disposed close to the bottom of the furnace tube body11, and the exhaust structure may be disposed on a sidewall of the furnace tube body11close to the top; or both the gas intake structure and the exhaust structure may be disposed on the sidewall of the furnace tube body11, and the exhaust structure may be higher than the gas intake structure. The gas intake structure and the exhaust structure may be arranged in various ways, which are not limited herein. In some embodiments, the gas intake structure includes a gas intake tube17, which is disposed close to the bottom of the furnace tube body11; the gas path system further includes vertical tubes19communicated with the gas intake tube, and the vertical tube19is provided with a plurality of blowholes distributed at intervals along the vertical direction of the vertical tube19, so that the reactive gas in the vertical tube19can be blown to the gaps between the wafers spaced in the vertical direction; the exhaust structure includes an exhaust passage and an exhaust port, with the exhaust passage arranged vertically, a top end of the exhaust passage communicated with the reaction chamber20and a bottom end of the exhaust passage communicated with the exhaust port; the exhaust port is higher than the gas intake tube, and the exhaust passage is higher than the cassettes14. The vertical tube19may be provided with a plurality of blowholes, which are evenly arranged at intervals along the vertical direction of the vertical tube19, the bottom end of the vertical tube19is communicated with the gas intake tube17, and thus, the reactive gas can sequentially be blown to the gap between each two wafers spaced in the vertical direction from the bottom up, so that the surfaces of the wafers can be in uniform contact with the reactive gas. Since the exhaust passage is higher than the cassettes14, the reactive gas then enters the exhaust passage from the top end of the exhaust passage and gets out via the exhaust port, and thus, the reactive gas in the reaction chamber20can circulate in a direction from the bottom up in a smoother manner. Consequently, not only can the surfaces of the wafers be in uniform contact with the reactive gas, but also the concentration of the reactive gas in the reaction chamber20can be more uniformly distributed by the flow of the reactive gas, and accordingly, the temperature in the reaction chamber20can be more uniform as well. In some embodiments, the gas intake structure includes a gas intake tube17, which is disposed close to the bottom of the furnace tube body11; the exhaust structure includes an exhaust passage and an exhaust port, with the exhaust passage arranged vertically, the top end of the exhaust passage communicated with the reaction chamber20and the bottom end of the exhaust passage communicated with the exhaust port; the exhaust port is higher than the gas intake tube, and the exhaust passage is higher than the cassettes14. The reactive gas enters the reaction chamber20via the gas intake tube17, and is sequentially blown to the gap between each two wafers spaced in the vertical direction from the bottom up. Since the exhaust passage is higher than the cassettes14, the reactive gas then enters the exhaust passage from the top end of the exhaust passage and gets out via the exhaust port, and thus, the reactive gas in the reaction chamber20can circulate in a direction from the bottom up in a smoother manner. Consequently, not only can the surfaces of the wafers be in uniform contact with the reactive gas, but also the concentration of the reactive gas in the reaction chamber20can be more uniformly distributed by the flow of the reactive gas, and accordingly, the temperature in the reaction chamber20can be more uniform as well. It should be understood that the aforementioned specific embodiments of the present application are merely intended to illustrate or explain the principle of the present application rather than constitute a limitation to the present application. Therefore, any modification, equivalent substitution, improvement and the like made without departing from the spirit and scope of the present application shall be included in the protection scope of the present application. In addition, the appended claims of the present application are intended to cover all changes and modifications that fall within the scope and boundaries of the appended claims or equivalents of such scope and boundaries. | 19,052 |
11862491 | DETAILED DESCRIPTION As the inventive concept allows for various changes and numerous embodiments, exemplary embodiments will be illustrated in the drawings and described in detail in the written description. However, this is not intended to limit the inventive concept to particular modes of practice, and it should be appreciated that all changes, equivalents, and substitutes that do not depart from the spirit and scope of the inventive concept are encompassed in the inventive concept. In describing the inventive concept, detailed descriptions related to well-known functions or configurations will be omitted when they may make subject matters of the inventive concept obscure. The terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit the scope of the inventive concept. The terms of a singular form may include plural forms unless otherwise specified. It should be understood that terms such as “comprise”, “include”, and “have”, when used herein, specify the presence of stated features, numbers, steps, operations, components, parts, or combinations thereof, but do not preclude the presence or addition of one or more other features, numbers, steps, operations, components, parts, or combinations thereof. The terms such as first, second, and the like may be used to describe various components, but the components should not be limited by the terms. The terms may be used only for distinguishing one component from others. Hereinafter, embodiments according to the inventive concept will be described in detail with reference to the accompanying drawings. In describing the embodiments with reference to the accompanying drawings, identical or corresponding components are provided with identical reference numerals in the drawings regardless of the reference numerals, and repetitive descriptions thereof will be omitted. FIG.1is a schematic plan view illustrating a substrate treating apparatus of the inventive concept. Referring toFIG.1, the substrate treating apparatus10includes an index module100and a process module200. The index module100may include a load port120, an index chamber140, and a light treatment chamber300. The load port120, the index chamber140, and the process module200are sequentially arranged in a row. Hereinafter, a direction in which the load port120, the index chamber140, and the process module200are arranged is referred to as a first direction12. A direction perpendicular to the first direction12when viewed from above is referred to as a second direction14, and a direction perpendicular to the plane including the first direction12and the second direction14is referred to as a third direction16. A carrier C having substrates W received therein is seated on the load port120. A plurality of load ports120are provided. The load ports120are disposed in a row along the second direction14.FIG.1illustrates one example that the index module100includes four load ports120. However, the number of load ports120may be increased or decreased depending on conditions such as process efficiency and footprint of the process module200. Slots (not illustrated) that support edges of the substrates W are formed in the carrier C. The slots are arranged in the third direction16. The substrates W are located in the carrier C so as to be stacked in a state of being spaced apart from each other along the third direction16. A front opening unified pod (FOUP) may be used as the carrier C. The index chamber140is located between the load ports120and a load-lock chamber220. The index chamber140has a rectangular parallelepiped shape including a front panel, a rear panel, and opposite side panels and includes, in the interior thereof, an index robot144for transferring the substrates W between the carriers C seated on the load ports120, the load-lock chamber220, and the light treatment chamber300. Although not illustrated, controlled air flow systems, such as vents and a laminar flow system, may be included in the index chamber140to prevent introduction of particle contaminants into the interior space of the index chamber140. The light treatment chamber300may be provided at one side of the index chamber140. A specific configuration of the light treatment chamber300will be described below. The process module200may include the load-lock chamber220, a transfer chamber240, liquid treatment chambers260, and supercritical chambers280. The transfer chamber240is disposed such that the lengthwise direction thereof is parallel to the first direction12. The liquid treatment chambers260or the supercritical chambers280are disposed on one side and an opposite side of the transfer chamber240along the second direction14. The liquid treatment chambers260located on the one side of the transfer chamber240and the supercritical chambers280located on the opposite side of the transfer chamber240may be symmetric to each other with respect to the transfer chamber240. Some of the liquid treatment chambers260may be disposed along the lengthwise direction of the transfer chamber240. Furthermore, other liquid treatment chambers260may be disposed to be stacked one above another. That is, the liquid treatment chambers260may be disposed in an A×B array (A and B being natural numbers of 1 or larger) on the one side of the transfer chamber240. Here, “A” denotes the number of liquid treatment chambers260provided in a row along the first direction12, and “B” denotes the number of liquid treatment chambers260provided in a column along the third direction16. In a case where four or six liquid treatment chambers260are provided on the one side of the transfer chamber240, the liquid treatment chambers260may be disposed in a 2×2 or 3×2 array. The number of liquid treatment chambers260may be increased or decreased. Alternatively, the liquid treatment chambers260may be provided on only the one side of the transfer chamber240. In another case, the liquid treatment chambers260may be provided in a single layer on the one side and the opposite side of the transfer chamber240. The supercritical chambers280may be provided similarly to the liquid treatment chambers260described above. On the opposite side of the transfer chamber240, the supercritical chambers280may be disposed similarly to the liquid treatment chambers260described above. Although it has been exemplified that the liquid treatment chambers260are provided on the one side of the transfer chamber240and the supercritical chambers280are provided on the opposite side of the transfer chamber240, the inventive concept is not limited thereto. For example, the arrangement of the liquid treatment chambers260and the supercritical chambers280may be modified in various ways. The load-lock chamber220is disposed between the index chamber140and the transfer chamber240. The load-lock chamber220provides a space in which the substrates W stay before transferred between the transfer chamber240and the index chamber140. The load-lock chamber220has slots (not illustrated) therein, and the substrates W are placed in the slots. The slots (not illustrated) are spaced apart from each other along the third direction16. In the load-lock chamber220, a face opposite the index chamber140and a face opposite the transfer chamber240may be open. The transfer chamber240may transfer the substrates W between the load-lock chamber220, the liquid treatment chambers260, and the supercritical chambers280. A guide rail242and a main robot244may be provided in the transfer chamber240. The guide rail242is disposed such that the lengthwise direction thereof is parallel to the first direction12. The main robot244is installed on the guide rail242and rectilinearly moves on the guide rail242along the first direction12. Hereinafter, components for transferring the substrates W are defined as a transfer unit. For example, the transfer chamber240and the index chamber140may be included in the transfer unit. In addition, the main robot244provided in the transfer chamber240and the index robot144may be included in the transfer unit. Substrate treating apparatuses for performing cleaning processes on the substrates W may be provided in the liquid treatment chambers260. For example, the cleaning processes may include a substrate cleaning process, a stripping process, and an organic-residue removal process that use treatment fluids containing alcohol content. The substrate treating apparatuses provided in the liquid treatment chambers260may have different structures depending on the types of cleaning processes performed. Selectively, the substrate treating apparatuses in the liquid treatment chambers260may have the same structure. Selectively, the liquid treatment chambers260may be divided into a plurality of groups. Substrate treating apparatuses provided in the liquid treatment chambers260belonging to the same group may have the same structure, and substrate treating apparatuses provided in the liquid treatment chambers260belonging to different groups may have different structures. For example, in a case where the liquid treatment chambers260are divided into two groups, a first group of liquid treatment chambers260may be provided on the one side of the transfer chamber240, and a second group of liquid treatment chambers260may be provided on the opposite side of the transfer chamber240. Selectively, on the one side and the opposite side of the transfer chamber240, the first group of liquid treatment chambers260may be provided in a lower layer, and the second group of liquid treatment chambers260may be provided in an upper layer. The first group of liquid treatment chambers260and the second group of liquid treatment chambers260may be distinguished from each other depending on the types of chemicals used or the types of cleaning methods. Hereinafter, one example of the substrate treating apparatuses provided in the liquid treatment chambers260will be described. FIG.2is a view illustrating the substrate treating apparatus provided in the liquid treatment chamber ofFIG.1. Referring toFIG.2, the substrate treating apparatus2600provided in the liquid treatment chamber includes a treatment vessel2620, a substrate support unit2640, a lifting unit2660, and a liquid dispensing unit2680. The substrate treating apparatus2600provided in the liquid treatment chamber260may dispense treatment liquids onto a substrate W. For example, the treatment liquids may include a chemical, a rinsing solution, and an organic solvent. The chemical may be a liquid having a property of acid or base. The chemical may include sulfuric acid (H2SO4), phosphoric acid (P2O5), hydrofluoric acid (HF), and ammonium hydroxide (NH4OH). The chemical may be a diluted sulfuric acid peroxide (DSP) mixture. The rinsing solution may be deionized water (H2O). The organic solvent may be isopropyl alcohol (IPA). The treatment vessel2620provides a treatment space in which the substrate W is treated. The treatment vessel2620has a cylindrical shape that is open at the top. The treatment vessel2620has an inner recovery bowl2622and an outer recovery bowl2626. The recovery bowls2622and2626recover different treatment liquids used for processes. The inner recovery bowl2622has an annular ring shape that surrounds the substrate support unit2640, and the outer recovery bowl2626has an annular ring shape that surrounds the inner recovery bowl2622. An inner space2622aof the inner recovery bowl2622functions as the first inlet2622athrough which a treatment liquid is introduced into the inner recovery bowl2622. A space2626abetween the inner recovery bowl2622and the outer recovery bowl2626functions as the second inlet2626athrough which a treatment liquid is introduced into the outer recovery bowl2626. According to an embodiment, the inlets2622aand2626amay be located at different heights. Recovery line2622band2626bare connected to lower surfaces of the bottoms of the recovery bowls2622and2626. The treatment liquids introduced into the recovery bowls2622and2626may be supplied to an external treatment liquid regeneration system (not illustrated) through the recovery lines2622band2626band may be regenerated by the regeneration system. The substrate support unit2640supports the substrate W in the treatment space. The substrate support unit2640supports and rotates the substrate W during a process. The substrate support unit340has a support plate2642, a support pin2644, a chuck pin2646, and a rotary drive member. The support plate2642is provided in a substantially circular plate shape and has an upper surface and a lower surface. The lower surface has a smaller diameter than the upper surface. The upper surface and the lower surface are located such that the central axes thereof are in agreement with each other. A plurality of support pins2644are provided. The support pins2644are disposed on an edge portion of the upper surface of the support plate2642so as to be spaced apart from each other at predetermined intervals. The support pins2642protrude upward from the support plate2642. The support pins2644are disposed to form an annular ring shape as a whole by a combination thereof. The support pins2644support the edge of a rear surface of the substrate W such that the substrate W is spaced apart from the upper surface of the support plate2642by a predetermined distance. A plurality of chuck pins2646are provided. The chuck pins2646are disposed farther away from the center of the support plate2642than the support pins2644. The chuck pins2646protrude upward from the upper surface of the support plate2642. The chuck pins2646support the side of the substrate W such that the substrate W does not deviate from a correct position to a side when the support plate2642is rotated. The chuck pins2646are rectilinearly movable between an outer position and an inner position along the radial direction of the support plate2642. The outer position is a position farther away from the center of the support plate2642than the inner position. When the substrate W is loaded onto or unloaded from the support plate2642, the chuck pins2646are located in the outer position, and when a process is performed on the substrate W, the chuck pins2646are located in the inner position. The inner position is a position in which the chuck pins2646and the side of the substrate W are brought into contact with each other, and the outer position is a position in which the chuck pins2646and the substrate W are spaced apart from each other. The rotary drive member2648and2649rotates the support plate2642. The support plate2642is rotatable about the central axis thereof by the rotary drive member2648and2649. The rotary drive member2648and2649includes a support shaft2648and an actuator2649. The support shaft2648has a cylindrical shape facing in the third direction16. An upper end of the support shaft2648is fixedly coupled to the lower surface of the support plate2642. According to an embodiment, the support shaft2648may be fixedly coupled to the center of the lower surface of the support plate2642. The actuator2649provides a driving force to rotate the support shaft2648. The support shaft2648is rotated by the actuator2649, and the support plate2642is rotatable together with the support shaft2648. The lifting unit2660rectilinearly moves the treatment vessel2620in an up-down direction. The height of the treatment vessel2620relative to the support plate2642is changed as the treatment vessel2620is moved in the up-down direction. The lifting unit2660lowers the treatment vessel2620such that the support plate2642further protrudes upward beyond the treatment vessel2620when the substrate W is loaded onto or unloaded from the support plate2642. Furthermore, when a process is performed, the height of the treatment vessel2620is adjusted depending on the types of treatment liquids dispensed onto the substrate W such that the treatment liquids are introduced into the preset recovery bowls2622and2626. The lifting unit2660has a bracket2662, a movable shaft2664, and an actuator2666. The bracket2662is fixedly attached to an outer wall of the treatment vessel2620, and the movable shaft2664is fixedly coupled to the bracket2664and is moved in the up-down direction by the actuator2666. Selectively, the lifting unit2660may move the support plate2642in the up-down direction. The liquid dispensing unit2680dispenses a treatment liquid onto the substrate W. A plurality of liquid dispensing units2680may be provided. The liquid dispensing units2680may dispense different types of treatment liquids onto the substrate W. The liquid dispensing unit2680may include a movable member2681and a nozzle2690. The movable member2681moves the nozzle2690between a process position and a standby position. Here, the process position is defined as a position in which the nozzle2690is opposite the substrate W supported on the substrate support unit2640, and the standby position is defined as a position in which the nozzle2690deviates from the process position. According to an embodiment, the process position includes a pre-treatment position and a post-treatment position. The pre-treatment position is a position in which the nozzle2690dispenses a treatment liquid to a first dispensing position, and the post-treatment position is a position in which the nozzle2690dispenses the treatment liquid to a second dispensing position. The first dispensing position may be a position closer to the center of the substrate W than the second dispensing position, and the second dispensing position may be a position including an end portion of the substrate W. Selectively, the second dispensing position may be an area adjacent to the end portion of the substrate W. The movable member2681includes a support shaft2686, an arm2682, and an actuator2688. The support shaft2686is located on one side of the treatment vessel2620. The support shaft2686has a rod shape, the lengthwise direction of which is parallel to the third direction16. The support shaft2686is rotatable by the actuator2688. The support shaft2686is movable upward and downward. The arm2682is coupled to an upper end of the support shaft2686. The arm2682extends from the support shaft2686at a right angle thereto. The nozzle2690is fixedly coupled to an end of the arm2682. As the support shaft2686is rotated, the nozzle2690is able to swing together with the arm2682. The nozzle2690may swing between the process position and the standby position. Selectively, the arm2682is movable forward and backward along the lengthwise direction thereof. When viewed from above, the path along which the nozzle2690is moved may be in agreement with the central axis of the substrate W in the process position. FIG.3is a view illustrating a substrate treating apparatus provided in the supercritical chamber ofFIG.1. Referring toFIG.3, the supercritical chamber280may supply a supercritical fluid to a substrate W. The supercritical fluid may be carbon dioxide in a supercritical state. The substrate treating apparatus2800provided in the supercritical chamber280includes a housing2810, a fluid supply unit2830, and an exhaust unit2860. The substrate W is supported by a support means (not illustrated) in a treatment space of the housing2810. The housing2810provides a space in which a supercritical process is performed. The housing2810includes a lower body2811and an upper body2812that are combined with each other to form the treatment space inside. The upper body2812is fixed in position, and the lower body2811is moved upward or downward. When the substrate W is loaded into or unloaded from the housing2810, the lower body2811and the upper body2812are spaced apart from each other, and when a process is performed on the substrate W, the lower body2811and the upper body2812are brought into close contact with each other. The fluid supply unit2830supplies the supercritical fluid into the housing2810. The supercritical fluid may be carbon dioxide in a supercritical state. The exhaust unit2860releases the supercritical fluid from the housing2810. The exhaust unit2860is provided at the lower body2811. FIG.4is a sectional view illustrating a light treatment chamber according to an embodiment of the inventive concept.FIG.5is a plan view illustrating an irradiation unit ofFIG.4.FIG.6is a sectional view of the irradiation unit ofFIG.4. Referring toFIGS.4to6, a substrate treating apparatus3000is provided in the light treatment chamber300. The light treatment chamber300may irradiate light to a substrate W treated in the liquid treatment chamber260. Furthermore, the light treatment chamber300may irradiate light to a substrate W treated in the supercritical chamber260. For example, the light treatment chamber300may irradiate light to a substrate W subjected to a drying process in the supercritical chamber260. The light treatment chamber300may remove organic matter remaining on a substrate W by irradiating light to the substrate W. The substrate treating apparatus3000provided in the light treatment chamber300may include a chamber3100, a support unit3200, and the irradiation unit3300. The chamber3100may have an interior space. The chamber3100may have a rectangular parallelepiped shape. The chamber3100may have a rectangular parallelepiped shape that is open at the top. The chamber3100may have an opening3110formed in a sidewall thereof, and the opening3110may be connected with the index chamber140and may be used as a passage through which the substrate W is loaded into or unloaded from the chamber3100. The opening3110may be opened or closed by a door3120. The support unit3200may support the substrate W in the interior space of the chamber3100. The support unit3200may be provided in the interior space of the chamber3100. The support unit3200may include a support plate3210, a lifting actuator3212, and a rotary actuator3214. The support plate3210may support the substrate W. The support plate3210may have a plate shape. The support plate3210may have a seating surface on which the substrate W is supported. When viewed from the side, the support plate3210may have a shape that is wide at the top and narrow at the bottom. The support plate3210may have a gradually increasing area toward the top thereof. The support plate3210may clamp the substrate W by vacuum pressure. Alternatively, the support plate3210may clamp the substrate W by a mechanical clamping method. In another case, the substrate W may be placed on the seating surface of the support plate3210without a separate clamping device. The lifting actuator3212may raise or lower the support plate3210. The lifting actuator3212may adjust the distance between the substrate W and the irradiation unit3300by raising or lowering the support plate3210. For example, when the irradiation unit3300irradiates light, the lifting actuator3212may decrease the distance between the substrate W and the irradiation unit3300by raising the support plate3210. In contrast, in a case where the irradiation unit3300does not irradiate light, the lifting actuator3212may increase the distance between the substrate W and the irradiation unit3300by lowering the support plate3210. Furthermore, the height of the support plate3300may be changed even while the irradiation unit3300irradiates light to the substrate W. The rotary actuator3214may rotate the support plate3210. The rotary actuator3214may be provided at the bottom of the support plate3210. The rotary actuator3214may be coupled with a lower surface of the support plate3210. The rotary actuator3214may rotate the support plate3210when the irradiation unit3300irradiates light. Accordingly, light may be uniformly irradiated to the substrate W. The irradiation unit3300may be disposed at the top of the chamber3100. The irradiation unit3300may irradiate light to the substrate W supported on the support unit3200. The irradiation unit3300may include a housing3301, light sources3310,3320, and3330, and a reflector3340. The light sources3310,3320, and3330may include the first light source3310, the second light source3320, and the third light source3330. The housing3301may have an interior space. The housing3301may have a rectangular parallelepiped shape. The housing3301may have a rectangular parallelepiped shape that is open at the bottom. The housing3301may have a shape corresponding to the chamber3100. The housing3301may be combined with the chamber3100to form an interior space. The housing3301may be provided at the top of the chamber3100and may be combined with the chamber3100. The first light source3310, the second light source3320, and the third light source3330may irradiate light. The first light source3310, the second light source3320, and the third light source3330may have a bar shape. When viewed from above, the first light source3310, the second light source3320, and the third light source3330may be alternately disposed such that adjacent light sources differ from one another. When viewed from above, the second light source3320, the first light source3310, and the third light source3330may be disposed in a serial order. Furthermore, the first light source3310, the second light source3320, and the third light source3330may be disposed at different heights. For example, the first light source3310may be disposed in a higher position than the second light source3320. The first light source3310may be disposed in a higher position than the third light source3330. The second light source3320and the third light source3330may be disposed at the same height. The first light source3310may irradiate first light L1to the substrate W. The second light source3320may irradiate second light L2to the substrate W. The third light source3330may irradiate third light L3to the substrate W. The first light source3310may be one of a flash lamp that irradiates a flash, an infrared lamp that irradiates infrared light, and an ultraviolet lamp that irradiates ultraviolet light. The second light source3320may be one of a flash lamp that irradiates a flash, an infrared lamp that irradiates infrared light, and an ultraviolet lamp that irradiates ultraviolet light. The third light source3330may be one of a flash lamp that irradiates a flash, an infrared lamp that irradiates infrared light, and an ultraviolet lamp that irradiates ultraviolet light. Hereinafter, it will be exemplified that the first light source3310is a flash lamp, the second light source3320is an ultraviolet lamp, and the third light source3330is an infrared lamp. Without being limited thereto, however, the types of the first light source3310, the second light source3320, and the third light source3330may be diversely changed. Furthermore, in the drawings, the irradiation unit3300is illustrated as including the first light source3310, the second light source3320, and the third light source3330. However, the inventive concept is not limited thereto. For example, only a selected one of the light sources3310,3320, and3330may be used. For example, the first light source3310may be provided alone in the irradiation unit3300. Alternatively, the second light source3320may be provided alone in the irradiation unit3300. In another case, the third light source3330may be provided alone in the irradiation unit3300. In another case, the first light source3310and the second light source3320may be provided in the irradiation unit3300. In another case, the first light source3310and the third light source3330may be provided in the irradiation unit3300. In another case, the second light source3320and the third light source3330may be provided in the irradiation unit3300. Hereinafter, light irradiated by the first light source3310is defined as the first light L1, light irradiated by the second light source3320is defined as the second light L2, and light irradiated by the third light source3330is defined as the third light L3. The first light L1and the second light L2may have different wavelength ranges. The first light L1and the third light L3may have different wavelength ranges. The second light L2and the third light L3may have different wavelength ranges. For example, the first light L1may have a wavelength range of 300 nm to 1000 nm. In a case where the first light source3310is implemented with a flash lamp, the energy of a flash irradiated by the first light source3310may be alternately changed every predetermined interval. Radiant heat of the first light L1irradiated by the first light source3310may be transferred to organic matter P adhering to the substrate W. The second light L2may have a wavelength range of 400 nm or more. In a case where the second light source3320is implemented with an ultraviolet lamp, the second light L2may have a wavelength of 254 nm or 185 nm. In a case where the second light L2has a wavelength of 254 nm, the second light L2may decompose ozone (O3). Accordingly, the second light L2may generate reactive oxygen species. In a case where the second light L2has a wavelength of 185 nm, the second light L2may decompose oxygen (O2). Accordingly, the second light L2may generate reactive oxygen species. Alternatively, the second light source3320may simultaneously irradiate the second light L2having a wavelength of 254 nm and the second light L2having a wavelength of 185 nm. In this case, the second light source3320may generate reactive oxygen species from ozone (O3) and oxygen (O2), thereby improving efficiency in treating the substrate W. The third light L3may have a wavelength range of 800 nm or more. In a case where the third light source3330is implemented with an infrared lamp, the third light L3may transfer heat to the organic matter P adhering to the substrate W. Accordingly, the organic matter P may be carbonized. The reflector3340may reflect light irradiated by the irradiation unit3300toward the surface of the substrate W supported on the support unit3200. For example, the reflector3340may reflect light irradiated by the first light source3310, the second light source3320, and the third light source3330toward the surface of the substrate W. The reflector3340may be formed of a material capable of reflecting light. The reflector3340may be provided to surround the first light source3310, the second light source3320, and the third light source3330. For example, the reflector3340may have a shape that surrounds an area over the first light source3310, the second light source3320, and the third light source3330. Furthermore, when viewed from the side, the reflector3340may have a round shape. For example, the reflector3340may have a cylindrical shape that is open at one side. When the first light source3310, the second light source3320, and the third light source3330irradiate light, the temperatures of the respective light sources3310,3320, and3330rise. Therefore, the substrate treating apparatus3000provided in the light treatment chamber300may have a cooling means. For example, the cooling means may include a first cooling line3010installed in the housing3301, a second cooling line3020installed in the chamber3100, and a refrigerant supply source3030that supplies a refrigerant into the first cooling line3010. The refrigerant may be a cooling fluid. The cooling fluid may be cooling water. Alternatively, the refrigerant may be a cooling gas. The cooling fluid supplied through the refrigerant supply source3030circulates through the first cooling line3010and the second cooling line3020. The first cooling line3010and the second cooling line3020may be connected with each other. A controller (not illustrated) may control the substrate treating apparatus10. The controller may control the substrate treating apparatus10to perform a substrate treating method that will be described below. For example, the controller may control the liquid treatment chamber260, the transfer unit, and the light treatment chamber300such that the substrate W is treated in the liquid treatment chamber260and then transferred to the light treatment chamber300. Furthermore, the controller may control the supercritical chamber280, the transfer unit, and the light treatment chamber300such that the substrate W is treated in the supercritical chamber280and then transferred to the light treatment chamber300. Hereinafter, a substrate treating method according to an embodiment of the inventive concept will be described. The substrate treating method according to the embodiment of the inventive concept may include a liquid treatment step, a supercritical treatment step, and a light treatment step. The liquid treatment step may be a step of treating the substrate W by dispensing a treatment liquid such as an organic solvent onto the substrate W. The liquid treatment step may be performed in the liquid treatment chamber260. The supercritical treatment step may be a step of treating the substrate W by supplying a supercritical fluid to the substrate W. The supercritical treatment step may be performed in the supercritical chamber280. The light treatment step may be a step of removing organic matter remaining on the substrate W by irradiating light to the substrate W. The light treatment step may be performed in the light treatment chamber300. The light treatment step may be performed after the supercritical treatment step. The light treatment step may be performed after the liquid treatment step. For example, the liquid treatment step, the supercritical treatment step, and the light treatment step may be sequentially performed. Hereinafter, one example of the light treatment step will be described in detail.FIG.7is a view illustrating a state in which light is irradiated to a substrate in the light treatment chamber ofFIG.4. Referring toFIG.7, the irradiation unit3300may irradiate light to the substrate W supported on the support unit3200. The irradiation unit3300may irradiate the first light L1, the second light L2, and the third light L3to the substrate W supported on the support unit3200. The first light L1and the second light L2may be simultaneously or sequentially irradiated. The first light L1and the third light L3may be simultaneously or sequentially irradiated. The second light L2and the third light L3may be simultaneously or sequentially irradiated. The first light L1, the second light L2, and the third light L3may be simultaneously or sequentially irradiated. While the light is irradiated to the substrate W, the substrate W may be rotated. Alternatively, while the light is irradiated to the substrate W, the light sources irradiating the light may rotate. In addition, while the light is irradiated to the substrate W, the distance between the substrate W and the irradiation unit3300may be adjusted. FIG.8is a view illustrating a state in which the second light source ofFIG.4irradiates the second light to treat a substrate, andFIG.9is a view illustrating a state in which the first light source ofFIG.4irradiates the first light to treat the substrate. Referring toFIG.8, the second light L2may be irradiated to the substrate W. The second light L2may be ultraviolet light. The second light L2may have a wavelength of 400 nm or less. The second light L2may have a wavelength of 254 nm or 185 nm. The second light L2may generate an active material. The second light L2may generate reactive oxygen species from oxygen or ozone. The reactive oxygen species generated by the second light L2may react with the organic matter P adhering to the substrate W. The organic matter P reacting with the reactive oxygen species may be decomposed. Furthermore, the organic matter P reacting with the reactive oxygen species may be oxidized. Accordingly, the particle size of the organic matter P may be decreased. Referring toFIG.9, the first light L1may be irradiated to the substrate W after the second light L2is irradiated to the substrate W. The first light L1may be a flash. The first light L1may have a wavelength range of 300 nm to 1000 nm. The flash irradiated by the first light source3310may generate radiant heat. The radiant heat generated by the first light L1may remove the organic matter P adhering to the substrate W. For example, the radiant heat may sublimate the organic matter P. Although it has been exemplified that the first light L1is irradiated after the second light L2is irradiated, the inventive concept is not limited thereto. For example, the first light L1and the second light L2may be simultaneously irradiated to the substrate W. FIG.10is a view illustrating a change in energy transferred to a substrate by the first light over time, andFIG.11is a view illustrating a change in energy transferred to a substrate by the first light and the third light ofFIG.4over time. Referring toFIGS.10and11, the first light L1irradiated by the first light source3310may be a flash. The energy of the flash irradiated by the first light source3310may be alternately changed every preset interval. Accordingly, higher energy may be transferred to the substrate W even though the first light source3310irradiates light with the same output. When the first light source3310alone irradiates the first light L1, the organic matter P may not be appropriately removed in a time range in which the energy of the first light L1is low. Therefore, according to an embodiment of the inventive concept, the first light L1and the third light L3may be simultaneously irradiated to the substrate W. Thus, energy transferred to the substrate W in the time range in which the energy of the first light L1is low may be increased. That is, the temperature of the substrate W may be raised and maintained by irradiating the third light L3. Furthermore, the organic matter P adhering to the substrate W may be effectively removed through the first light L1. In addition, when the first light L1, the second light L2, and the third light L3described above are irradiated to the substrate W, reactive oxygen species may be generated and may decrease the particle size of the organic matter P adhering to the substrate W, the temperature of the substrate W may be raised and maintained, and the organic matter P may be effectively removed by irradiating light having high energy at the same output to the substrate W. FIG.12is a view illustrating part of a light treatment chamber according to another embodiment of the inventive concept. Referring toFIG.12, a substrate treating apparatus3000aprovided in the light treatment chamber may include a reflector3340a. The reflector3340amay be provided to surround a first light source3310a, a second light source3320a, and a third light source3330a. In this embodiment, three reflectors may be installed as the three light sources are installed. A housing3301a, a first cooling line3010a, the first light source3310a, the second light source3320a, and the third light source3330aare the same as, or similar to, those described above. Therefore, detailed descriptions thereabout will be omitted. FIG.13is a sectional view illustrating a light treatment chamber according to another embodiment of the inventive concept, andFIG.14is a plan view illustrating an irradiation unit ofFIG.13. With the exception of the irradiation unit3300b, a substrate treating apparatus3000bprovided in the light treatment chamber according to the other embodiment of the inventive concept is the same as, or similar to, the substrate treating apparatuses described above. Therefore, the following description will be focused on a difference therebetween. The irradiation unit3300bmay include a plate3350b. The plate3350bmay be disposed over a support unit3210b. The plate3350bmay be coupled with a drive member3352a. The drive member3352amay rotate the plate3350b. Light sources3310b,3320b, and3330birradiating light may have a block shape. The light sources3310b,3320b, and3330bhaving the block shape may be provided on the plate3350bso as to be detachable. The light sources3310b,3320b, and3330bmay have pins, and the plate3350bmay have holes into which the pins are inserted. Furthermore, a plurality of light sources3310b, a plurality of light sources3320b, and a plurality of light sources3330bmay be arranged in a lateral direction and/or a longitudinal direction. Here, the lateral direction and/or the longitudinal direction does not mean only a straight direction. Furthermore, when viewed from above, the light sources3310b,3320b, and3330bmay be alternately mounted on the plate3350bsuch that adjacent light sources differ from one another. In this case, light may be more uniformly irradiated to a substrate W than in a case where light sources are provided in a bar shape. FIG.14illustrates one example that the light sources3310b,3320b, and3330bare disposed in a circular shape as a whole. However, as illustrated inFIG.15, the light sources3310b,3320b, and3330bmay be disposed on a straight line when viewed from above. FIG.16is a view illustrating a light treatment chamber according to another embodiment of the inventive concept. A buffer chamber400may be provided under a chamber3100dthat the light treatment chamber3000dhas. The buffer chamber400may include a plurality of slots410for temporarily storing substrates W. The substrates W may be transferred into the buffer chamber400after removal of organic matter P in the chamber3100d. The substrates W in the buffer chamber400may be transferred into a carrier by the index robot144after the substrates W are cooled to a temperature at which the substrates W are able to be transferred. Although not illustrated, a means for lowering the temperatures of the substrates W may be added to the buffer chamber400. FIG.17is a schematic plan view illustrating a substrate treating apparatus according to another embodiment.FIG.18is a perspective view illustrating major parts of an index module illustrated inFIG.17.FIG.19is a side sectional view illustrating a light treatment chamber installed on a load port. Referring toFIGS.17to19, the substrate treating apparatus10eaccording to the other embodiment includes the index module100e, a process module200e, and the light treatment chamber300e. The index module100e, the process module200e, and the light treatment chamber300ehave configurations and functions substantially similar to the configurations and functions of the index module100, the process module200, and the light treatment chamber300illustrated inFIG.1. Therefore, the following description will be focused on a difference therebetween. The light treatment chamber300eis characterized by being mounted on the load port120e. Accordingly, without a considerable change in design, the light treatment chamber300emay be additionally mounted on a substrate treating facility already installed in a semiconductor manufacturing line. For example, the light treatment chamber300emay be mounted on one load port among four load ports120edisposed at the front of the index module100eand may add a process of removing organic matter on the surface of a substrate before the substrate is transferred to a carrier C after a supercritical drying process. To this end, the light treatment chamber300emay include a carrier door3600that is opened or closed by a door opener1230in the state in which the light treatment chamber300eis mounted on the load port120e. Likewise to a door of a general carrier (FOUP), the carrier door3600has a registration pin hole3601and a latch key hole3602. The registration pin hole3601is used to determine a position, and the latch key hole3602is used to open or close the carrier door3600. Meanwhile, the load port120eincludes a drive table1210and a port door1220, and the port door1220constitutes part of a front side of an index chamber140e. Furthermore, in this embodiment, a wall of the index chamber140econstitutes part of a FIMS face corresponding to a FOUP described in SEMI standards. Reference numeral1221denotes a registration pin, and reference numeral1222denotes a latch key. Both the registration pin1221and the latch key1222are installed on the surface of the port door1220. The registration pin1221serves to perform positioning in a state of being inserted into the registration pin hole3601formed in the carrier door3600. Furthermore, the latch key1222is rotated after being inserted into the latch key hole3602formed in the carrier door3600. Accordingly, a coupling member (not illustrated) of a clamping mechanism may be removed from a chamber3100e, and thus the carrier door3600may be opened. This operation may be performed identically to an operation of opening or closing a FOUP door described in SEMI standards. As described above, according to the embodiments of the inventive concept, the substrate treating apparatus and method may improve efficiency in treating a substrate. Furthermore, according to the embodiments of the inventive concept, the substrate treating apparatus and method may efficiently remove organic matter remaining on a substrate. In addition, according to the embodiments of the inventive concept, the light treatment chamber may be easily mounted on an existing substrate treating apparatus. Effects of the inventive concept are not limited to the above-described effects, and any other effects not mentioned herein may be clearly understood from this specification and the accompanying drawings by those skilled in the art to which the inventive concept pertains. The above description exemplifies the inventive concept. Furthermore, the above-mentioned contents describe exemplary embodiments of the inventive concept, and the inventive concept may be used in various other combinations, changes, and environments. That is, variations or modifications can be made to the inventive concept without departing from the scope of the inventive concept that is disclosed in the specification, the equivalent scope to the written disclosures, and/or the technical or knowledge range of those skilled in the art. The written embodiments describe the best state for implementing the technical spirit of the inventive concept, and various changes required in specific applications and purposes of the inventive concept can be made. Accordingly, the detailed description of the inventive concept is not intended to restrict the inventive concept in the disclosed embodiment state. In addition, it should be construed that the attached claims include other embodiments. While the inventive concept has been described with reference to exemplary embodiments, it will be apparent to those skilled in the art that various changes and modifications may be made without departing from the spirit and scope of the inventive concept. Therefore, it should be understood that the above embodiments are not limiting, but illustrative. | 46,673 |
11862492 | DETAILED DESCRIPTION The figures and descriptions provided herein may have been simplified to illustrate aspects that are relevant for a clear understanding of the herein described devices, systems, and methods, while eliminating, for the purpose of clarity, other aspects that may be found in typical similar devices, systems, and methods. Those of ordinary skill may recognize that other elements and/or operations may be desirable and/or necessary to implement the devices, systems, and methods described herein. But because such elements and operations are well known in the art, and because they do not facilitate a better understanding of the present disclosure, a discussion of such elements and operations may not be provided herein. However, the present disclosure is deemed to inherently include all such elements, variations, and modifications to the described aspects that would be known to those of ordinary skill in the art. The terminology used herein is for the purpose of describing particular example embodiments only and is not intended to be limiting. For example, as used herein, the singular forms “a”, “an” and “the” may be intended to include the plural forms as well, unless the context clearly indicates otherwise. The terms “comprises,” “comprising,” “including,” and “having,” are inclusive and therefore specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof. The method steps, processes, and operations described herein are not to be construed as necessarily requiring their performance in the particular order discussed or illustrated, unless specifically identified as an order of performance. It is also to be understood that additional or alternative steps may be employed. When an element or layer is referred to as being “on”, “engaged to”, “connected to” or “coupled to” another element or layer, it may be directly on, engaged, connected or coupled to the other element or layer, or intervening elements or layers may be present. In contrast, when an element is referred to as being “directly on,” “directly engaged to”, “directly connected to” or “directly coupled to” another element or layer, there may be no intervening elements or layers present. Other words used to describe the relationship between elements should be interpreted in a like fashion (e.g., “between” versus “directly between,” “adjacent” versus “directly adjacent,” etc.). As used herein, the term “and/or” includes any and all combinations of one or more of the associated listed items. Although the terms first, second, third, etc., may be used herein to describe various elements, components, regions, layers and/or sections, these elements, components, regions, layers and/or sections should not be limited by these terms. These terms may be only used to distinguish one element, component, region, layer or section from another element, component, region, layer or section. That is, terms such as “first,” “second,” and other numerical terms, when used herein, do not imply a sequence or order unless clearly indicated by the context. Thus, a first element, component, region, layer or section discussed below could be termed a second element, component, region, layer or section without departing from the teachings of the exemplary embodiments. To the extent processor-implemented modules, systems and methods of design and control use are disclosed herein, they may provide access to and transformation of a plurality of types of digital content, including but not limited to video, image, text, audio, metadata, algorithms, interactive and document content, and may track, deliver, manipulate, transform and report the accessed content. Described embodiments of these modules, systems and methods are intended to be exemplary and not limiting. As such, it is contemplated that the herein described systems and methods may be adapted and may be extended to provide enhancements and/or additions to the exemplary modules, systems and methods described. The disclosure is thus intended to include all such extensions. Embodiments include the generation of ramped electrical interconnections using additive manufacturing techniques, i.e., 3D printing, and conductive inks, such as nanoparticle conductive inks, in multilayer, such as two layers, circuits. By way of example, embodiments may allow for integration and interconnection of molded top and bottom circuits, and may additionally include capabilities to place surface mount components within end-mold electronics. More particularly, a multilayer, such as a two layer, circuit may have a ramped version of a “VIA” (vertical interconnect access), also referred to herein as a ramp interconnect access (RIA), which provides a connection non-vertical VIA between two layers of the multilayer circuit. The RIA ramp may be created by any known methodology, such as by molding, machining, cutting, or the like. For example, laser drilling, laser micro machining, C&C machining, shape molding, and the like may be methodologies employed in the embodiments to create the ramp without departing from the disclosure. By way of particular non-limiting example, a C&C machine may be used to remove a ramp-shaped slice from a second circuit layer substrate, whereby a ramp is created having a high point starting at the plane of the second layer circuit, and having a low point ending slightly below, at, or slightly above a plane provided for the first circuit level. Conductive material may then be added to the ramp to provide a RIA interconnecting the first and second layer circuits. Thereby, the embodiments may remedy drawbacks of a typical VIA's vertical holes, which are generally used to electrically connect layers of a multilayer circuit in the prior art. In a known VIA context, the vertical hole must be filled with conductive material from the first circuit layer all the way up to and including the plane provided by the second circuit layer in order to provide the electrical connection. However, in typical prior art embodiments, difficulties may arise in the process that creates and fills the VIA. For example, such difficulties may include curing of the conductive material in the hole prior to the conductive material reaching all the way down to the first circuit layer, such that a non-conductive gap occurs at the lower portion of the VIA; the VIA walls being overly rough, such that the conductive material gets “caught” along the VIA side walls, which impedes or negates conductivity; roughing of the conductive material as it is inserted, such that open holes are created in the VIA that adversely affect conductivity; and mechanical instability of the conductive material in the hole such that VIA conductivity is adversely affected, such as because of a lack of mechanical support necessary to support the vertical rise of the VIA, by way of non-limiting example. In the embodiments, additive manufacturing methodologies may be used, once the ramp is created, to additively provide the conductive material that provides the conductive path from the first circuit layer to the second, or subsequent, circuit layer. Such conductive material may be provided, by way of non-limiting example, by piezo-jet printing, inkjet printing, by screen printing, or by any similar known methodology suitable to provide the characteristics discussed herein. By way of non-limiting example, a piezo-jet printing head, provided by Neotech AMT GmbH, may be used to inject ink through a piezo-actuator based on applying force to the ink to thus provide a drop-on-demand nozzle that allows for the regulation of each ink drop printed. The ability to regulate ink drops upon ejection from a print head may allow for refined control of the ink thus printed, which, as will be understood to the skilled artisan, improves the conductivity and stability provided by the RIA created in the embodiments. For example, regulated ink ejection may allow for ink drops of a preselected size to be dropped on demand from a range of 5 to 30 mm of distance above the print surface, and may allow for the printing of the RIAs disclosed herein in three dimensions, such as dependent on ink type and other processing factors discussed throughout. Of course, typical additive manufacturing process parameters may be considered in the embodiments, and varied in accordance with the creation of particular types of RIA, as will be appreciated by the skilled artisan in light of the discussion herein. For example, a piezo-jet printer head with a 50 micrometer/03 nozzle type may be employed, such as with a print frequency of 250 Hz. FIG.1illustrates a cross-sectional view of an exemplary RIA system10according to the embodiments. In the illustration, a first layer circuit12and a second layer circuit14may be provided in a first plane and a second plane, respectively. By way of example, the first layer circuit12may be built upon any suitably receptive surface, such as a polycarbonate film, and/or may comprise one or more traces, plates, or plated traces, such as a Cu plated trace. The second layer circuit14may be provided upon a surface provided physically upon the first layer circuit12that does not interfere with operation of the first layer circuit12, such as any production plastic material, such as a molded Acrylonitrile Butadiene Styrene (ABS). As illustrated, a ramped area16may be provided from the second layer circuit14“downward” at a given angle20to the first layer circuit12. Upon the ramp16thus provided may be additively manufactured a conductive RIA22that interconnects conductive components12a,14aof the second layer circuit14and the first layer circuit12. As illustrated in the example ofFIG.1, the ramp angle20may vary, by way of non-limiting example, between about 45° and 70°. Moreover, the ramp size may be approximately 500 to 1500 microns, or, more particularly, 800 to 1000 microns, by way of non-limiting example. FIG.2shows an isometric view of a first12and second layer14circuit according to the embodiments. In the illustration, the first layer circuit12includes conductive traces102and surface mount technology (SMT) components104embedded within the molded substrate106upon which the second layer circuit14is provided. In the illustration, a ramped area110may be provided, such as by “drilling”, machining, or otherwise removing or creating of a triangular area to provide an angled ramp110from a conductive trace on the second layer circuit120to the conductive trace102on the first layer circuit12, as shown. Also illustrated is a conductive material122, such as a conductive printed ink, additively placed along the full linear distance of the ramp to thereby conductively connect the second layer trace120to the first layer trace102. By way of non-limiting example, the ink used may be a silver conductive ink and may be printed by a piezo-jet print head, such as is discussed throughout. Additionally, a “target”, such as a target conductive disc or the like, may be provided in electrical connection to the first trace102at the base of the ramp, i.e., at ramp point3as discussed herein. This target may provide enhanced connectivity of the conductive material122along the ramp to the first layer trace102. Of note, connective point12aofFIG.1may be, for example, such a target. FIG.3illustrates a circuit level view of a RIA202in accordance with some embodiments. Further,FIG.3includes an inset akin to the illustration ofFIG.1, wherein points1,2and3along the ramp204may be compared to the actual points1,2and3in the actual circuit202ofFIG.3. The printed material122printed “down” the ramp of the RIA202may be further viewed in an actual circuit with respect toFIG.4, which again includes the inset illustration akin to that ofFIG.1that compares points1,2and3along the ramp in actuality, and in a schematic cross-sectional view. Of note, particularly with respect to the exemplary illustration ofFIG.4, a sharp edge at ramp point1, or a surface having extraordinary roughness proximate to point2and along the slope of the ramp, may adversely affect conductivity of the RIA202. As such, the ramp along its slope and/or at points proximate to point2may have a suitable roughness matched to the printed ink used to provide the RIA, such that conductivity is maintained; and the topmost area of the RIA, i.e., the ramp at point1, may be rounded or otherwise smoothed to eliminate sharp edges, and thus prevent cracks, voids, or thin spots for the printed ink as it initially descends the RIA from the first level circuit to the second level circuit. FIG.5illustrates an exemplary RIA402having a ramp404at an angle of approximately 46°. As illustrated, the ink thickness of the RIA402may vary at points along the ramp, such that conductivity is maintained. By way of non-limiting example, the ink thickness in microns at point1of the RIA402may be, by way of non-limiting example, between 25 and 75 microns, or more particularly between 30 and 45 microns, such that the concerns referenced above with regard to the sharper edge at the inception of the RIA at point1are addressed so that conductivity is maintained as the RIA ramps downward. However, at point2of the RIA402, a different thickness in microns may be provided, such as a thickness in the range of 10 to 40 microns, or more particularly 20 to 25 microns, by way of non-limiting example, which varied thickness may be based, at least in part, upon the roughness of the RIA402along the ramp surface and particularly proximate to point2. As discussed throughout, various additive manufacturing methods may be employed in the embodiments. For example, although jetted inks, such as piezo-jetted inks, are discussed herein by way of particular example, other additive manufacturing methodologies, such as screen printing of inks, may be employed. Also as referenced throughout, the ink and print methods employed may depend on the design needs in particular embodiments, such as particular needs for ink thickness on certain surfaces or in certain operating environments, the ability to suitable address surface roughness at the top of, bottom of, or along the ramp, and/or contact resistance at one or more points along the RIA. For example, for certain RIA's, a screen printed ink may provide a 1.45 ohms/sq resistance, which may be acceptable in certain embodiments. However, a jetted ink may provide a contact resistance of 1/10 to 1/20 or less of that contact resistance in certain circumstances, which may be necessary in particular embodiments. FIG.6provides a particular implementation of the RIA502as discussed herein. In the illustration, silver flake ink is screen printed on a polycarbonate film substrate504to provide the first layer circuit506. Components510of the first layer circuit506are suitably and conductively bonded to the first layer circuit506, and an end mold thermoplastic injection molding is used to provide the substrate512for the upper layer plane upon which the second layer circuit514is provided. A machine, such as two-axis C&C machine, may machine into the molded material512that provides the plane for the second layer circuit514and may remove a thin layer at a time by interpolating along the cutting surface in order to create a ramp520. Thereafter, a piezo-aerosol jet may dispense silver nanoparticle ink along the ramp520, before, during, or after screen printing or similar dispensing to create the second level circuit514. The printed RIA may require curing, such as curing at 85° C., for a given time period, such as 30 minutes. FIG.7illustrates with particularity the machining602of a ramp604in accordance with the embodiments. As shown, one thin layer at a time may be machined602, such that layers are removed at an increasing depth on one side of the machined area as compared to the other. Thereby, a ramp604upon which a RIA may be created is provided. FIGS.8A and8Billustrate a machined ramp702without ink, and the same machined ramp702after printing of the ink704thereon. Of note particularly with respect toFIG.8B, the size of the ink trace704as it is printed down the ramp may vary in accordance with the factors discussed herein throughout, as may the thickness thereof. For example, the size and thickness of the trace704may vary based on the roughness of the ramp surface, the sharpness at the inception point of the ramp702on the second layer circuit710, and the steepness of the angle of the ramp702along which the RIA is printed, by way of non-limiting example. FIG.8Cillustrates the printed RIA ofFIG.8Bin an isometric view. Further, included inFIG.8Cis an inset cross-sectional schematic akin to that ofFIG.1, illustrating points1,2and3of the RIA after printing as discussed throughout. It will be understood, in light of the discussion herein, that various modifications may be made to the embodiments without departing from the scope of the disclosure, and such modifications may depend on design choices made. For example, the curing discussed herein of the RIA printed ramp trace, such as may occur at 85° C. for 30 minutes as referenced, may be dependent on the use of certain inks, such as a silver nanoparticle ink that contains 60 weight percent bulk silver. If other inks having other silver, or metal, contents are used, needless to say, the curing aspects may be varied or avoided. For example, it may be necessary that low temperature curing nanoparticle conductive inks are employed, such as in order to avoid degradation of temperature sensitive molded parts upon which the second layer circuit is provided. For example, an ABS molded part may have a glass transition temperature of 105° C., and thereby the curing for the ink used for the RIA must occur at a temperature well below this glass transition temperature. In the foregoing Detailed Description, it can be seen that various features are often grouped together in a single embodiment for the purpose of clarity and brevity of the disclosure. This method of disclosure is not to be interpreted as reflecting an intention that the embodiments require more features than are expressly recited herein. Rather, the disclosure is to encompass all variations and modifications to the disclosed embodiments that would be understood to the skilled artisan in light of the disclosure. | 18,467 |
11862493 | DETAILED DESCRIPTION The devices, systems, and methods disclosed herein provide correcting component failures in semiconductor manufacturing tools (e.g., end of life prediction for the plasma source gun in an ion implant semiconductor manufacturing tool). The devices, systems, and methods disclosed herein may provide critical component failure prediction (e.g., by using a deep learning model) for ion implanting tools using derived sensor readings. A processing device may receive, from a plurality of sensors associated with manufacturing equipment (e.g., an ion implant tool), current sensor data corresponding to features (e.g., pressure, temperature, flow, power, etc.). The processing device may further perform feature analysis to generate additional features for the current sensor data. Additional features may be generated based on one or more features. For example, additional features may include one or more of a ratio, a range, delta, a maximum value, etc. The processing device may further provide the additional features as input to a trained machine learning model and subsequently obtain one or more outputs from the trained machine learning model. The one or more outputs may be indicative of a level of confidence of a predicted window. The processing device may predict, based on the level of confidence of the predicted window, whether one or more components of the ion implant tool are within a pre-failure window. A pre-failure window may be a window of time (e.g., 24 hours, 48 hours) before failure of a component is predicted to occur. The processing device may further, responsive to predicting that the one or more components are within the pre-failure window, perform a corrective action associated with the ion implant tool. The corrective action (e.g., correcting and/or preemptively correcting component failures) may include providing an alert, interrupting operation of the manufacturing equipment, and/or causing the one or more components to be replaced. The devices, systems, and methods disclosed herein provide correcting component failures in semiconductor manufacturing tools (e.g., end of life prediction for the plasma source gun in an ion implant semiconductor manufacturing tool). The devices, systems, and methods disclosed herein may provide critical component failure prediction (e.g., by using a deep learning model) for ion implanting tools using derived sensor readings. A processing device may receive, from a plurality of sensors associated with manufacturing equipment (e.g., an ion implant tool), current sensor data corresponding to features (e.g., pressure, temperature, flow, power, etc.). The processing device may further perform feature analysis to generate additional features for the current sensor data. Additional features may be generated based on one or features. For example, additional features may include one or more of a ratio, a range, delta, a maximum value, etc. The processing device may further provide the additional features as input to a trained machine learning model and subsequently obtain one or more outputs from the trained machine learning model. The one or more outputs may be indicative of a level of confidence of a predicted window. The processing device may predict, based on the level of confidence of the predicted window, whether one or more components of the ion implant tool are within a pre-failure window. A pre-failure window may be a window of time (e.g., 24 hours, 48 hours) before failure of a component is predicted to occur. The processing device may further, responsive to predicting that the one or more components are within the pre-failure window, perform a corrective action associated with the ion implant tool. The corrective action (e.g., correcting and/or preemptively correcting component failures) may include providing an alert, interrupting operation of the manufacturing equipment, and/or causing the one or more components to be replaced. The devices, systems, and methods disclosed herein also provide training of a machine learning model for prediction of failure of components. In some embodiments, a processing device may receive, from sensors associated with manufacturing equipment (e.g., an ion implant tool), historical sensor data corresponding to features (e.g., historical values for sensor, pressure, flow, power, etc. data). The processing device may further determine windows corresponding to the historical sensor data. The windows may include a normal operation window for a first subset of the historical sensor data and a pre-failure window for a second subset of the historical sensor data. The processing device may further perform feature analysis to generate additional features for the historical sensor data (e.g., ratio, range, delta, maximum, etc.). The processing device may further train a machine learning model using training data including the additional features and target output including the windows to generate a trained machine learning model. The trained machine learning model may be capable of generating one or more outputs indicative of whether one or more components (e.g., ion implant tool components) are within the pre-failure window (e.g., to perform corrective action associated with one or more components of ion implant tools). The machine learning model may be trained using historical sensor data associated with first manufacturing equipment and may be used to predict component failure for other manufacturing equipment. Aspects of the present disclosure also result in technological advantages. Conventionally, a component is used until failure or is replaced prematurely. By a processing device predicting a pre-failure window (e.g., end of life, 24 hours, 48 hours) for one or more components, the processing device may cause corrective action so that the one or more components are replaced before failure. Replacing the components before failure (e.g., instead of after failure) reduces downtime, reduces damage to the manufacturing equipment and products, reduces unscheduled maintenance, reduces expedited shipping of replacement components, etc. Replacing the components within the pre-failure window (e.g., instead of arbitrarily replacing components very prematurely) reduces waste of current components that still are usable, reduces cost associated with too frequently replacing components, reduces maintenance, etc. Receiving sensor data, reducing noise, and performing feature analysis (prior to using the trained machine learning model to predict whether one or more components are within the pre-failure window) provides significant reduction in energy consumption (e.g., battery consumption), bandwidth, latency, and so forth compared to analyzing all of the sensor data (e.g., including noise and all of the features). FIG.1is a block diagram illustrating an exemplary system architecture100, according to certain embodiments. The system architecture100includes client device120, failure prediction server130, and a data store140. The failure prediction server130may be part of a failure prediction system110. The client device120, failure prediction server130, data store140, server machine170, server machine180, manufacturing equipment124(e.g., ion implant tools, etc.), and sensors126may be coupled to each other via a network160for failure prediction. In some embodiments, network160is a public network that provides client device120with access to the failure prediction server130, data store140, and other publicly available computing devices. In some embodiments, network160is a private network that provides client device120with access to the failure prediction server130, data store140, and other privately available computing devices. Network160may include one or more wide area networks (WANs), local area networks (LANs), wired networks (e.g., Ethernet network), wireless networks (e.g., an 802.11 network or a Wi-Fi network), cellular networks (e.g., a Long Term Evolution (LTE) network), routers, hubs, switches, server computers, and/or a combination thereof. The manufacturing equipment124may be used for semiconductor processing. The manufacturing equipment124may include an ion implant tool. An ion implant tool may insert atoms into a semiconductor device to control the flow of electricity through the semiconductor device (e.g., to make transistors, etc.). The manufacturing equipment124(e.g., ion implant tool) may include components, such as flood gun124A, source gun124B, etc. A flood gun124A may be an electromechanical device that provides a steady flow of low-energy electrons to a target (e.g., flood area, an area on an insulator or a semiconductor). A source gun124B (e.g., plasma source gun) may be a plasma source for depositing plasma on a semiconductor device (e.g., eject plasma with a significant streaming velocity to have an energetic deposition of the plasma on the semiconductor device). A limiting factor of uninterrupted performance of the manufacturing equipment124(e.g., ion implant tool) may be failure of one or more components (e.g., flood gun124A, source gun124B, etc.) which may lead to unplanned down time. Sensors126may capture sensor data (e.g., raw sensor data, temperature, pressure, power, flow, etc.) associated with the manufacturing equipment124. For example, an ion implanter tool may be equipped with hundreds of sensors with acquisition speed of thousands of hertz. Given the number of sensors, speed of acquisition of sensor data, and life expectancy of components (e.g., six months, etc.), the volume of sensor data (e.g., raw sensor data) captured may be very large. The sensor data142from sensors126may be stored in the data store140. The client device120may include a computing device such as personal computers (PCs), laptops, mobile phones, smart phones, tablet computers, netbook computers, network connected televisions (“smart TV”), network-connected media players (e.g., Blu-ray player), a set-top-box, over-the-top (OTT) streaming devices, operator boxes, etc. The client device120may be capable of transmitting information (e.g., a selection of manufacturing equipment124for the failure prediction) via network160and receiving indications associated with a predicted failure (e.g., level of confidence of a predicted window, instructions to execute a corrective action, etc.) via network160. The instructions associated with a predicted failure may specify that one or more components of the manufacturing equipment124are currently associated with a predicted window156B of time (e.g., normal operation window, a pre-failure window, a failure window, etc.). The instructions associated with a predicted failure may indicate one or more of an amount of time until failure, components that are to be replaced, how to replace the components, whether operation of the manufacturing equipment124has been interrupted (e.g., has been shut down), or whether operation of the manufacturing equipment124should be interrupted. The client device120may display an alert via a graphical user interface (GUI) responsive to receiving the indications associated with a predicted failure. Each client device120may include an operating system that allows users to generate, view, and edit information and view alerts. The client device120may include a computing device such as personal computers (PCs), laptops, mobile phones, smart phones, tablet computers, netbook computers, network connected televisions (“smart TV”), network-connected media players (e.g., Blu-ray player), a set-top-box, over-the-top (OTT) streaming devices, operator boxes, etc. The client device120may be capable of transmitting information (e.g., a selection of manufacturing equipment124for the failure prediction) via network160and receiving indications associated a predicted failure (e.g., level of confidence of a predicted window, instructions to execute a corrective action, etc.) via network160. The instructions associated with a predicted failure may specify that one or more components of the manufacturing equipment124are currently associated with a predicted window156B of time (e.g., normal operation window, a pre-failure window, a failure window, etc.). The instructions associated with a predicted failure may indicate one or more of an amount of time until failure, components that are to be replaced, how to replace the components, whether operation of the manufacturing equipment124has been interrupted (e.g., has been shut down), or whether operation of the manufacturing equipment124should be interrupted. The client device120may display an alert via a graphical user interface (GUI) responsive to receiving the indications associated with a predicted failure. Each client device120may include an operating system that allows users to generate, view, and edit information and view alerts. The client device120may include a corrective action component122. Corrective action component122may receive user input (e.g., via a GUI displayed via the client device120) and may generate, based on the user input, an indication that failure prediction is to be executed for manufacturing equipment124. The corrective action component122may transmit the indication to the failure prediction server130. In some embodiments, corrective action component122transmits sensor data142(e.g., from sensors126coupled to manufacturing equipment124) to failure prediction server130. The corrective action component122may receive an indication associated with a predicted failure from the failure prediction server130(e.g., responsive to the failure prediction server130determining a pre-failure window). The corrective action component122may cause a corrective action to be performed. A corrective action may refer to correcting and/or preemptively correcting component failures (e.g., based on predicting a pre-failure window). For example, to cause a corrective action to be performed, corrective action component122may provide an alert (e.g., via a GUI of client device120, via manufacturing equipment124, etc.), may interrupt operation of the manufacturing equipment124(e.g., shut down one or more portions of the manufacturing equipment124), and/or may cause the one or more components to be replaced. The failure prediction server130may include one or more computing devices such as a rackmount server, a router computer, a server computer, a personal computer, a mainframe computer, a laptop computer, a tablet computer, a desktop computer, etc. The failure prediction server130may include a failure prediction component132. In some embodiments, the failure prediction component132may receive sensor data142(e.g., from sensors126coupled to manufacturing equipment124). The sensor data142may include recorded values over time and a corresponding time stamp for each value (e.g., a first recorded temperature at a first point in time, a second recorded temperature at a second point in time, etc.). The sensor data142may be raw trace data (e.g., without any feature engineering). The failure prediction component132may remove noise from current sensor data150, perform feature analysis to generate additional features for the current sensor data150, predict whether one or more components of the manufacturing equipment124are within a pre-failure window, and perform a corrective action associated with the manufacturing equipment124responsive to predicting the one or more components are within the pre-failure window. To predict whether components are within the pre-failure window, the failure prediction component132may provide the current sensor data150(e.g., current additional features154) to the model190(e.g., a convolutional long short-term memory (LSTM) (convLSTM) model, a deep learning model, a random forest model, etc.) for failure prediction. The failure prediction component132may receive a level of confidence158for a predicted window156B from the model190based on the current sensor data150. Each feature (e.g., historical feature146, current feature152, etc.) of the sensor data150may include a sequence (e.g., first value, second value, etc.), timestamps (e.g., time at first value, time at second value, etc.), and an indication of which sensor126corresponds to the sequence. Each additional feature (e.g., historical additional feature148, current additional feature154) may be generated by performing one or more operations on one or more of the features. The one or more operations may include one or more of a ratio, a range, a delta, or a maximum value of features (e.g., corresponding sensor data) from one or more of the plurality of sensors126. For example, a first feature may be a sequence of pressure measurements received from a pressure sensor of the sensors126, a second feature may be a sequence of temperature measurements received from a temperature sensor of the sensors126, and a first additional feature may be a ratio of the sequence of pressure measurements divided by each corresponding temperature measurement (e.g., first additional feature may be a sequence including a first pressure value at a first point in time divided by a first temperature value at the first point in time, a second pressure value at a second point in time divided by a second temperature value at the second point in time, etc.). Data store140may be a memory (e.g., random access memory), a drive (e.g., a hard drive, a flash drive), a database system, or another type of component or device capable of storing data. Data store140may include multiple storage components (e.g., multiple drives or multiple databases) that may span multiple computing devices (e.g., multiple server computers). The data store140may store one or more of sensor data142(e.g., historical sensor data144, historical features146, historical additional features148, current sensor data150, current features152, current additional features154, etc.), windows156(e.g., historical windows156A, predicted windows156B), levels of confidence158, etc. In some embodiments, failure prediction system110further includes server machine170and server machine180. The server machines170and180may be one or more computing devices (such as a rackmount server, a router computer, a server computer, a personal computer, a mainframe computer, a laptop computer, a tablet computer, a desktop computer, etc.), data stores (e.g., hard disks, memories databases), networks, software components, or hardware components. Server machine170includes a data set generator172that is capable of generating one or more data sets (e.g., a set of data inputs210and a set of target outputs220in FIG.2) to train, validate, or test a machine learning model190. Some operations of data set generator172are described in detail below with respect toFIGS.2and6. In some embodiments, the data set generator172may partition the historical sensor data144into a training set (e.g., sixty percent of the historical sensor data144), a validating set (e.g., twenty percent of the historical sensor data144), and a testing set (e.g., twenty percent of the historical sensor data144). Server machine180includes a training engine182. In some embodiments, server machine180includes a training engine182, a validation engine184, and a testing engine186. The training engine182may be capable of training a machine learning model190using the training set from data set generator172. The training engine182may generate one or more trained machine learning models190. The validation engine184may be capable of validating a trained machine learning model190using the validation set from data set generator172. The validation engine184may determine an accuracy of each of the trained machine learning models190based on the validation set. The validation engine184may discard trained machine learning models190that have an accuracy that does not meet a threshold accuracy. The testing engine186may be capable of testing a trained machine learning model190using a testing set from data set generator172. The testing engine186may determine a trained machine learning model190that has the highest accuracy of all of the trained machine learning models based on the testing sets. The machine learning model190may refer to the model artifact that is created by the training engine182using a training set that includes data inputs and corresponding target outputs (correct answers for respective training inputs). Patterns in the data sets can be found that map the data input to the target output (the correct answer), and the machine learning model190is provided mappings that captures these patterns. In some embodiments, the machine learning model190may use one or more LSTM layers and a softmax layer (seeFIGS.7A-B). In some embodiments, the failure prediction component132may provide the historical sensor data144and historical windows156A to the data set generator172. The data set generator172may provide the historical sensor data144as input and the historical windows156as output to one or more of training engine182, validation engine184, and/or testing engine186to one or more of train, validate, or test the machine learning model190. In some embodiments, the failure prediction system110may generate different models190based on one or more of different hyperparameters (e.g., different numbers of LSTM layers), different types of machine learning models, different sets of historical additional features148, etc. The failure prediction system110may one or more of train, validate, or test the different models190and select the model190that is most accurate. In some embodiments, failure prediction component132may provide the current sensor data150as input to the trained machine learning model190, and run trained machine learning model190on the input to obtain one or more outputs. As described in detail below with respect toFIG.4, failure prediction component132may be capable of determining a predicted window156B (e.g., based on the output of the trained machine learning model190, by extracting the a level of confidence of the predicted window156B from the output, etc.). The failure prediction component132may also determine confidence data based on the output. The confidence data may indicate a level of confidence that the predicted window156B corresponds to the manufacturing equipment124. The failure prediction component132may use the levels of confidence158to select the predicted window156B. The failure prediction component132may determine multiple predicted windows156B and corresponding levels of confidence158based on the output of the model190(e.g., 10% level of confidence for a normal operation window and 90% level of confidence for a pre-failure operation window). In some embodiments, the failure prediction component132selects the predicted window with the highest level of confidence. In some embodiments, the failure prediction component132selects the predicted window that has a level of confidence over 50%. The failure prediction component132may determine multiple predicted windows156B and corresponding levels of confidence158based on the output of the model190(e.g., 10% level of confidence that normal operation window and 90% level of confidence that pre-failure operation window). In some embodiments, the failure prediction component132selects the predicted window with the highest level of confidence. In some embodiments, the failure prediction component132selects the predicted window that has a level of confidence over 50%. For purpose of illustration, rather than limitation, aspects of the disclosure describe the training of a machine learning model and use of a trained learning model using current sensor data150to determine predicted windows156B. In other implementations, a heuristic model or rule-based model is used to determine predicted windows156based on sensor data142(e.g., historical sensor data144, current sensor data150, etc.). Any of the information described with respect to data inputs210ofFIG.2may be monitored or otherwise used in the heuristic or rule-based model. In some embodiments, the functions of client device120, failure prediction server130, server machine170, and server machine180may be provided by a fewer number of machines. For example, in some embodiments server machines170and180may be integrated into a single machine. In some other embodiments, server machine170, server machine180, and failure prediction server130may be integrated into a single machine. In general, functions described in one embodiment as being performed by client device120, server machine170, and server machine180can also be performed on failure prediction server130in other embodiments, if appropriate. In addition, the functionality attributed to a particular component can be performed by different or multiple components operating together. For example, in some embodiments, the failure prediction server130may receive the user input indicating manufacturing equipment124(e.g., a semiconductor processing tool) for the failure prediction and the failure prediction server130may provide the alert, shut down the manufacturing equipment124, etc. based on the level of confidence158of the predicted window156B. In another example, client device120may one or more of remove noise from the sensor data142, perform feature analysis on the sensor data142, determine the level of confidence158of the predicted windows156B, predict whether the one or more components are within the pre-failure window, or perform the corrective action. In another example, the data set generator172may remove the noise from the historical sensor data144and perform feature analysis on the historical sensor data144. In addition, the functions of a particular component can be performed by different or multiple components operating together. One or more of the failure prediction server130, server machine170, or server machine180may be accessed as a service provided to other systems or devices through appropriate application programming interfaces (API). In embodiments, a “user” may be represented as a single individual. However, other embodiments of the disclosure encompass a “user” being an entity controlled by a plurality of users and/or an automated source. For example, a set of individual users federated as a group of administrators may be considered a “user.” Although embodiments of the disclosure are discussed in terms of sensor data150received from sensors126coupled to manufacturing equipment124, embodiments may also be generally applied to data received over time (e.g., irregular time series data, etc.). Embodiments may be generally applied to optimizing processes that generate data over time. Examples of manufacturing equipment124for wafer or display manufacturing are physical vapor deposition (PVD) equipment, chemical vapor deposition (CVD) equipment, atomic layer deposition (ALD) equipment, chemical mechanical polishing (CMP) equipment, and etch equipment. FIG.2is an example data set generator272(e.g., data set generator172ofFIG.1) to create data sets for a machine learning model290(e.g., model190ofFIG.1) using historical sensor data244(e.g., historical sensor data144ofFIG.1), according to certain embodiments. System200ofFIG.2shows data set generator272, data inputs210, and target outputs220. In some embodiments, data set generator272generates a data set (e.g., training set, validating set, testing set) that includes one or more data inputs210(e.g., training input, validating input, testing input) and one or more target outputs220. The data set may also include mapping data that maps the data inputs210to the target outputs220. Data inputs210may also be referred to as “features,” “attributes,” or “information.” In some embodiments, data set generator272may provide the data set to one or more of the training engine182, validating engine184, or testing engine186, where the data set is used to train, validate, or test the machine learning model190. Some embodiments of generating a training set may further be described with respect toFIG.6. In some embodiments, data inputs210may include one or more sets of features212A for the historical sensor data244. Each set of features212may include at least one of a historical feature246(e.g., historical feature146ofFIG.1) or a historical additional feature248(e.g., historical additional feature148ofFIG.1). For example, a set of features212may include one or more historical additional features248. In some embodiments, data set generator272may generate a first data input210A corresponding to a first set of features212A to train, validate, or test a first machine learning model and the data set generator272may generate a second data input210B corresponding to a second set of features212B to train, validate, or test a second machine learning model. Data inputs210and target outputs220to train, validate, or test a machine learning model may include information from a particular facility (e.g., from a particular semiconductor manufacturing facility). For example, the historical sensor data244may be from the same manufacturing facility as the current sensor data150ofFIG.1. In some embodiments, the information used to train the machine learning model may be from specific groups of components of the manufacturing facility having specific characteristics (e.g., components from a specific timeframe, components for a specific type of manufacturing equipment, etc.) and allow the trained machine learning model to predict pre-failure windows for a specific group of components based on historical sensor data associated with one or more components sharing characteristics of the specific group. In some embodiments, the information used to train the machine learning model may be for components from two or more manufacturing facilities and may allow the trained machine learning model to determine outcomes for components based on input from one manufacturing facility. In some embodiments, the information used to train the machine learning model may be associated with one or more first ion implant tools and the trained machine learning model may be used to predict component failure for one or more second ion implant tools that are different from the one or more first ion implant tools. Data inputs210and target outputs220to train, validate, or test a machine learning model may include information form a particular facility (e.g., from a particular semiconductor manufacturing facility). For example, the historical sensor data244may be form the same manufacturing facility as the current sensor data150ofFIG.1. In some embodiments, the information used to train the machine learning model may be from specific groups of components of the manufacturing facility having specific characteristics (e.g., components from a specific timeframe, components for a specific type of manufacturing equipment, etc.) and allow the trained machine learning model to predict pre-failure windows for a specific group of components based on historical sensor data associated with one or more components sharing characteristics of the specific group. In some embodiments, the information used to train the machine learning model may be for components from two or more manufacturing facilities and may allow the trained machine learning model to determine outcomes for components based on input from one manufacturing facility. In some embodiments, the information used to train the machine learning model may be associated with one or more first ion implant tools and the trained machine learning model may be used to predict component failure for one or more second ion implant tools that are different from the one or more first ion implant tools. In some embodiments, subsequent to generating a data input210and training, validating, or testing machine learning model190using the data set, the machine learning model190may be further trained, validated, or tested or adjusted (e.g., adjusting weights associated with input data of the machine learning model190, such as connection weights in a neural network, tuning hyperparameters, etc.) using additional historical sensor data and corresponding historical windows from one or more manufacturing facilities. FIG.3is a block diagram illustrating a system300for determining a level of confidence358(e.g., level of confidence158ofFIG.1) of predicted windows356B (e.g., predicted windows156B ofFIG.1). The system300may provide failure prediction for semiconductor manufacturing tools (e.g., end of life prediction for the plasma source gun in an ion implant semiconductor manufacturing tool). At block310, the system300(e.g., failure prediction system110ofFIG.1) performs data partitioning (e.g., via data set generator172of server machine170ofFIG.1) of the historical sensor data344(e.g., historical sensor data144ofFIG.1) to generate the training set302, validation set304, and testing set306. In some embodiments, the system300generates a plurality of sets of features corresponding to each of the data sets. At block312, the system300performs model training (e.g., via training engine182ofFIG.1) using the training set302. The system300may train multiple models using multiple sets of features of the training set302(e.g., a first set of features of the training set302, a second set of features of the training set302, etc.). At block314, the system300performs model validation (e.g., via validation engine184ofFIG.1) using the validation set304. The system300may validate each of the trained models using a corresponding set of features of the validation set304. At block314, the system may determine an accuracy of each of the one or more trained models and may determine whether one or more of the trained models has an accuracy that meets a threshold accuracy. Responsive to determining that none of the trained models has an accuracy that meets a threshold accuracy, flow returns to block312where the system300performs model training using different sets of features of the training set. Responsive to determining that one or more of the trained models has an accuracy that meets a threshold accuracy, flow continues to block316. At block316, the system300performs model selection to determine which of the one or more trained models that meet the threshold accuracy has the highest accuracy (e.g., the selected model308). Responsive to determining that two or more of the trained models that meet the threshold accuracy have the same accuracy, flow may return to block312where the system300performs model training using further refined training sets corresponding to further refined sets of features for determining a trained model that has the highest accuracy. At block318, the system300performs model testing (e.g., via testing engine186ofFIG.1) using the testing set306to test the selected model308. At block318, the system300may determine whether accuracy of the selected model308meets a threshold accuracy using the testing set306. Responsive to accuracy of the selected model308not meeting the threshold accuracy (e.g., the selected model308is overly fit to the validation set304), flow continues to block312where the system300performs model training using different training sets corresponding to different sets of features. Responsive to determining that the selected model308has an accuracy that meets a threshold accuracy based on the testing set306, flow continues to block320. In at least block312, the model may learn patterns in the historical sensor data to make predictions and in block318, the system300may apply the model on the remaining data (e.g., testing set306) to test the predictions. In some embodiments, in addition to using different sets of features (e.g., different combinations of historical additional features148) for one or more of training, validating, or testing of different models, the system300may also include different hyperparameters in the different models to determine which features and which hyperparameters provide the highest accuracy. In some embodiments, instead of using different sets of features for the one or more of training, validating or testing different models, the system300uses different hyperparameters in the different models (e.g., where each model uses the same set of historical additional features148) to determine which hyperparameters provide the highest accuracy. At block320, system300uses the trained model (e.g., selected model308) to receive current sensor data350(e.g., current sensor data150ofFIG.1) and to output a level of confidence358of a predicted window356B (e.g., level of confidence158of a predicted window156B ofFIG.1). Responsive to receiving additional sensor data, the additional sensor data may be input into block312to update the trained model via model re-training. FIGS.4-6are flow diagrams illustrating example methods400,500, and600associated with failure prediction, according to certain embodiments. Methods400,500, and600may be performed by processing logic that may include hardware (e.g., circuitry, dedicated logic, programmable logic, microcode, processing device, etc.), software (such as instructions run on a processing device, a general purpose computer system, or a dedicated machine), firmware, microcode, or a combination thereof. In one embodiment, methods400,500, and600may be performed, in part, by failure prediction system110. In some embodiments, methods400,500, and600may be performed by failure prediction server130. In some embodiments, a non-transitory computer readable storage medium stores instructions that when executed by a processing device (e.g., of failure prediction system110) cause the processing device to perform methods400,500, and600. For simplicity of explanation, methods400,500, and600are depicted and described as a series of acts. However, acts in accordance with this disclosure can occur in various orders and/or concurrently and with other acts not presented and described herein. Furthermore, not all illustrated acts may be performed to implement the methods400,500, and600in accordance with the disclosed subject matter. In addition, those skilled in the art will understand and appreciate that the methods400,500, and600could alternatively be represented as a series of interrelated states via a state diagram or events. FIG.4is a flow diagram of a method400for predicting component failure, according to certain embodiments. In some embodiments, method400is performed by processing logic of failure prediction component132of the failure prediction server130. At block402, the processing logic receives, from sensors (e.g., sensors126) associated with manufacturing equipment (e.g., manufacturing equipment124, an ion implant tool), current sensor data (e.g., current sensor data150) corresponding to features. The features may be sequences of current sensor data, where each sequence of current sensor data is captured by a corresponding sensor. In some embodiments, the current sensor data is streamed to the processing logic. The processing logic may receive the sensor data in the form of one or more of a dataset, a matrix, etc. In some embodiments, the sensor data is saved and aggregated in the data store140. In some embodiments, at block404, the processing logic removes noise from the current sensor data. In some embodiments, the processing logic removes the noise from the current sensor data by averaging the current sensor data over intervals (e.g., average sensor data values over 10 second periods of time, etc.). In some embodiments, the processing logic removes the noise by removing the outliers from the current sensor data. At block406, the processing logic performs feature analysis to generate additional features (e.g., current additional features154) for the current sensor data. The additional features may include one or more of a ratio, a range, a delta, or a maximum value of corresponding sensor data from one or more of the plurality of sensors. In some embodiments, the additional features may include statistical features (e.g., mean, standard deviation, etc.) of key sensors In some embodiments, the processing logic performs the feature analysis by receiving user input indicating the additional features that are to be calculated. In some embodiments, a model for feature analysis (e.g., feature engineering) is generated (seeFIG.5, based on user input of additional features, based on user input of other parameters, without user input). The model for feature analysis may be a convolutional neural network (CNN) (e.g. that performs one-dimension convolutions). The CNN may excel at learning the temporal structure in sensor data142and may determine invariant features for failure and normal data (e.g., for determining normal operation window, pre-failure window, etc.). The processing logic may perform the analysis by receiving the current sensor data in a matrix and processing the matrix via one-dimensional convolutions to output the plurality of additional features. At block408, the processing logic provides the additional features (e.g., subsequent to the removing of the noise) as input to a trained machine learning model. The trained machine learning model may include one or more LSTM layers and a softmax layer. The trained machine learning model may have learned spatial features as sequences by the one or more LSTM layers. The time series structure may be built into the prediction. The trained machine learning model may be weighted to penalize misclassifications (e.g., to avoid having false positives). A current prediction generated by the method400may be based on a previous time step of the current sensor data150. At block410, the processing logic obtains one or more outputs from the trained machine learning model. In some embodiments, the one or more outputs are indicative of a level of confidence (e.g., level of confidence158) of a predicted window (e.g., predicted window156B). In some embodiments, the processing logic extracts from the one or more outputs, the level of confidence of the predicted window. In some embodiments, the processing logic determines multiple predicted windows and corresponding levels of confidence (e.g., 10% level of confidence for a normal operation window and 90% level of confidence for a pre-failure window). At block410, the processing logic obtains one or more outputs from the trained machine learning model. In some embodiments, the one or more outputs are indicative of a level of confidence (e.g., level of confidence158) of a predicted window (e.g., predicted window156B). In some embodiments, the processing logic extracts from the one or more outputs, the level of confidence of the predicted window. In some embodiments, the processing logic determines multiple predicted windows and corresponding levels of confidence (e.g., 10% level of confidence that normal operation window and 90% level of confidence that pre-failure window). At block412, the processing logic predicts, based on the level of confidence of the predicted window, whether one or more components of the manufacturing equipment (e.g., ion implant tool) are within a pre-failure window. The processing logic may predict that the one or more components are within the pre-failure window by determining the level of confidence of the predicted window indicates greater than 50% confidence of the pre-failure window. At block414, the processing logic determines whether the level of confidence of the predicted window indicates the one or more components of the ion implant tool are within the pre-failure window. Responsive to the level of confidence of the predicted window indicating the one or more components are not within the pre-failure window, flow continues to block402where additional sensor data is received (e.g., a loop of method400). Responsive to the level of confidence of the predicted window indicating the one or more components are within the pre-failure window, flow continues to block416. The one or more components may be a component of an ion implant tool, such as at least one of a flood gun or a source gun. At block416, the processing logic performs a corrective action associated with the ion implant tool (e.g., responsive to predicting that the one or more components are within the pre-failure window). The corrective action may include one or more of causing a graphical user interface to display an alert, interrupting operation (e.g., shutting down, slowing speed, stopping specific processes, etc.) of the manufacturing equipment (e.g., ion implant tool), or causing the one or more components to be replaced. At block502, the processing logic receives, from sensors (e.g., sensors126) associated with manufacturing equipment124(e.g., an ion implant tool), historical sensor data (e.g., historical sensor data144) corresponding to features (e.g., measurement values and corresponding times stamps received from the sensors126associated with the manufacturing equipment124). At block502, the processing logic receives, from sensors (e.g., sensors126) associated with manufacturing equipment124(e.g., an ion implant tool), historical sensor data (e.g., historical sensor data144) corresponding to features (e.g., measurement values and corresponding times stamps received form the sensors126associated with the manufacturing equipment124). In some embodiments, at block504, the processing logic removes noise from the historical sensor data. The processing logic may remove the noise from the historical sensor data by one or more of averaging the historical sensor data over intervals or removing outliers. At block506, the processing logic determines windows (e.g., historical windows156A) including a normal operation window for a first subset of the historical sensor data and a pre-failure window for a second subset of the historical sensor data. The processing logic may determine windows by determining a time of failure (e.g., based on a peak of sensor data values, based on a peak of health index values such as inFIG.8B). The processing logic may determine sensor data captured more than a set amount of time (e.g., 24 hours, 48 hours) before the time of failure corresponds to the normal operation window, sensor data captured between the time of failure and the set amount of time before the failure corresponds to the pre-failure window, and the sensor data captured after the time of failure corresponds to the failure window. At block508, the processing logic performs feature analysis to generate additional features (e.g., historical additional features148) for the historical sensor data. The additional features may include one or more of a ratio, a range, a delta, or a maximum value of corresponding sensor data from one or more of the plurality of sensors. The processing logic may perform the feature analysis by receiving the historical sensor data in a matrix and processing the matrix via one-dimensional convolutions to output the plurality of additional features. In some embodiments, the processing logic receives user input corresponding to the additional features (e.g., operations and specific sensors associated with the additional features). The processing logic may train a CNN (e.g., based on the user input of the additional features, with user input of parameters, without user input, etc.) and the trained CNN may be used in method400to determine additional features (e.g., current additional features154) for using the trained machine learning model At block510, the processing logic trains a machine learning model (e.g., including one or more LSTM levels and a softmax layer) using training data including the additional features (e.g., subsequent to the removing of the noise) and target output including the windows to generate a trained machine learning model. The trained machine learning model may be capable of generating one or more outputs indicative of whether one or more ion implant tool components (e.g., from one or more ion implant tools, from one or more manufacturing equipment124, etc.) are within the pre-failure window (see method400ofFIG.4). In some embodiments, the processing logic trains multiple models using one or more of different features (e.g., historical features146, historical additional features148) or different hyperparameters. The processing logic may one or more of train, validate, or test the different models (e.g., evaluate the models) to select the model that gives the highest accuracy. In some embodiments, the processing logic deploys the trained machine learning model to predict whether one or more components of manufacturing equipment (e.g., flood gun, source gun, etc. of ion implant tools) are within a pre-failure window for performing a corrective action (e.g., associated with one or more ion implant tools). In some embodiments, the trained machine learning model is to receive input based on current sensor data from a second plurality of sensors associated with a second ion implant tool (e.g., different than the ion implant tool used for training the machine learning model) for the predicting whether the one or more components are within the pre-failure window. FIG.6is a flow diagram of a method600for generating a data set for a machine learning model for predicting component failure, according to certain embodiments. Failure prediction system110may use method600to at least one of train, validate, or test a machine learning model, in accordance with embodiments of the disclosure. In some embodiments, one or more operations of method600may be performed by data set generator172of server machine170as described with respect toFIGS.1and2. It may be noted that components described with respect toFIGS.1and2may be used to illustrate aspects ofFIG.6. Referring toFIG.6, at block602, the processing logic initializes a data set T to an empty set. At block604, the processing logic generates first data input (e.g., first training input, first validating input) that includes a first set of features for the historical sensor data (as described with respect toFIG.2). The first data input may include one or more features (e.g., historical features146) and/or one or more additional features (e.g., historical additional features148) of historical sensor data (e.g., historical sensor data144). At block606, processing logic generates a first target output for one or more of the data inputs (e.g., first data input). The first target output provides an indication of a historical window (e.g., historical window156A). At block608, processing logic optionally generates mapping data that is indicative of an input/output mapping. The input/output mapping (or mapping data) may refer to the data input (e.g., one or more of the data inputs described herein), the target output for the data input (e.g., where the target output identifies a predicted window), and an association between the data input(s) and the target output. At block610, processing logic adds the mapping data generated at block610to data set T. At block614, processing logic provides data set T to train, validate, or test machine learning model190. In some embodiments, data set T is a training set and is provided to training engine182of server machine180to perform the training. In some embodiments, data set T is a validation set and is provided to validation engine184of server machine180to perform the validating. In some embodiments, data set T is a testing set and is provided to testing engine186of server machine180to perform the testing. In some embodiments, the data set T may be partitioned into a training set, a validation set, and a testing set (e.g., the training set may be 60%, the validation set may be 20%, and the testing set may be 20%). Responsive to the machine learning model being trained (e.g., and validated, tested, and meeting a threshold accuracy), the trained machine learning model may be used (e.g., by failure prediction component132) for failure prediction (seeFIGS.3-4). At block614, processing logic provides data set T to train, validate, or test machine learning model190. In some embodiments, data set T is a training set and is provided to training engine182of server machine180to perform the training. In some embodiments, data set T is a validation set and is provided to validation engine184of server machine180to perform the validating. In some embodiments, data set T is a testing set and is provided to testing engine186of server machine180to perform the testing. In some embodiments, the data set T may be partitioned into a training set, a validation set, and a testing set (e.g., the training set may be 60%, the validation set may be 20%, and the validation set may be 20%). Responsive to the machine learning model being trained (e.g., and validated, tested, and meeting a threshold accuracy), the trained machine learning model may be used (e.g., by failure prediction component132) for failure prediction (seeFIGS.3-4). In the case of a neural network, for example, input values of a given input/output mapping (e.g., numerical values associated with data inputs210) are input to the neural network, and output values (e.g., numerical values associated with target outputs220) of the input/output mapping are stored in the output nodes of the neural network. The connection weights in the neural network are then adjusted in accordance with a learning algorithm (e.g., back propagation, etc.), and the procedure is repeated for the other input/output mappings in data set T. The trained machine learning model may be implemented by failure prediction component132(of failure prediction server130) to predict a failure window for one or more components. FIGS.7A-Bare block diagrams illustrating systems700A and700B for failure prediction, according to certain embodiments. Referring toFIG.7A, system700A may receive input data710. The input data710may be sensor data in a matrix. Noise may be removed from the sensor data (e.g., by averaging the raw data over intervals to generate the sensor data, by removing outliers from the sensor data). System700A may perform one-dimensional convolutions720(e.g., of a trained CNN) on the input data710. In some embodiments a CNN (e.g., that performs one-dimensional convolutions) was trained based on user input associated with additional features (e.g., indicating the operations to be used to generate the additional features). The system700A may perform the one-dimensional convolutions720on the input data710(e.g., subsequent to removal of noise) to perform feature analysis to generate additional features for the input data. The additional features may include one or more of a ratio, a range, a delta, a maximum value, etc. of corresponding sensor data. System700A may input the additional features into a LSTM layer730of a machine learning model. The number of LSTM layers may be a hyperparameter that is tuned by training and retraining the machine learning model based on sensor data. Referring toFIG.7B, system700B includes LSTM layers730that may receive additional features based on the input data710. The output of the LSTM layers730may transmitted to the softmax layer740. The softmax layer may generate one or more outputs. The one or more outputs may include a corresponding level of confidence for one or more predicted windows. For example, the softmax layer may generate a first level of confidence of the normal operation window, a second level of confidence for the pre-failure window, and a third level of confidence for the failure window. The levels of confidence may add up to 100%. The window that corresponds to a level of confidence greater than 50% may be used. Referring toFIG.7B, system700B includes LSTM layers730that may receive additional features based on the input data710. The output of the LSTM layers730may transmitted to the softmax layer740. The softmax layer may generate one or more outputs. The one or more outputs may include a corresponding level of confidence for one or more predicted windows. For example, the softmax layer may generate a first level of confidence of the normal operation window, a second window of confidence for the pre-failure window, and a third level of confidence for the failure window. The levels of confidence may add up to 100%. The window that corresponds to a level of confidence greater than 50% may be used. FIGS.8A-Bare graphs800A and800B illustrating failure prediction, according to certain embodiments. Referring toFIG.8A, graph800A displays features values (e.g., historical additional features148, current additional features154, etc.) over time. A first window of time may correspond to class 0 (e.g., normal operation window). A second window of time may correspond to class 1 (e.g., pre-failure window). A third window of time may correspond to class 2 (e.g., failure window). Class 0 may end and class 1 may begin a set amount of time (e.g., 24 hours, 48 hours, etc.) before the failure date (e.g., historical failure date, predicted failure date). Class 1 may end and class 2 may begin at the time of failure of the one or more components. The historical sensor data may be labeled according to the corresponding window (e.g., class 0, 1, or 2). Referring toFIG.8B, graph800B displays a health index plotted over time (e.g., has corresponding time stamps). The health index may be based on one or more of the outcome of convolutional LSTM, sensor data, additional features, etc. The health index may be substantially stable over a normal operation window. During the pre-failure window, the health index may peak and substantially at time of failure, the health index may drop. A first subset of the sensor data may correspond to time stamps in the normal operation window, a second subset of the sensor data may correspond to time stamps in the pre-failure window, and a third subset of the sensor data may correspond to time stamps in the failure window. Each of the subsets of sensor data may be labeled according to the corresponding window (e.g., class). FIG.9is a block diagram illustrating a computer system900, according to certain embodiments. In some embodiments, computer system900may be connected (e.g., via a network, such as a Local Area Network (LAN), an intranet, an extranet, or the Internet) to other computer systems. Computer system900may operate in the capacity of a server or a client computer in a client-server environment, or as a peer computer in a peer-to-peer or distributed network environment. Computer system900may be provided by a personal computer (PC), a tablet PC, a set-top box (STB), a Personal Digital Assistant (PDA), a cellular telephone, a web appliance, a server, a network router, switch or bridge, or any device capable of executing a set of instructions (sequential or otherwise) that specify actions to be taken by that device. Further, the term “computer” shall include any collection of computers that individually or jointly execute a set (or multiple sets) of instructions to perform any one or more of the methods described herein. In a further aspect, the computer system900may include a processing device902, a volatile memory904(e.g., random access memory (RAM)), a non-volatile memory906(e.g., read-only memory (ROM) or electrically-erasable programmable ROM (EEPROM)), and a data storage device916, which may communicate with each other via a bus908. Processing device902may be provided by one or more processors such as a general purpose processor (such as, for example, a complex instruction set computing (CISC) microprocessor, a reduced instruction set computing (RISC) microprocessor, a very long instruction word (VLIW) microprocessor, a microprocessor implementing other types of instruction sets, or a microprocessor implementing a combination of types of instruction sets) or a specialized processor (such as, for example, an application specific integrated circuit (ASIC), a field programmable gate array (FPGA), a digital signal processor (DSP), or a network processor). Computer system900may further include a network interface device922. Computer system900also may include a video display unit910(e.g., an LCD), an alphanumeric input device912(e.g., a keyboard), a cursor control device914(e.g., a mouse), and a signal generation device920. In some implementations, data storage device916may include a non-transitory computer-readable storage medium924on which may store instructions926encoding any one or more of the methods or functions described herein, including instructions encoding the failure prediction component132or corrective action component122ofFIG.1and for implementing methods described herein. Instructions926may also reside, completely or partially, within volatile memory904and/or within processing device902during execution thereof by computer system900, hence, volatile memory904and processing device902may also constitute machine-readable storage media. While computer-readable storage medium924is shown in the illustrative examples as a single medium, the term “computer-readable storage medium” shall include a single medium or multiple media (e.g., a centralized or distributed database, and/or associated caches and servers) that store the one or more sets of executable instructions. The term “computer-readable storage medium” shall also include any tangible medium that is capable of storing or encoding a set of instructions for execution by a computer that cause the computer to perform any one or more of the methods described herein. The term “computer-readable storage medium” shall include, but not be limited to, solid-state memories, optical media, and magnetic media. The methods, components, and features described herein may be implemented by discrete hardware components or may be integrated in the functionality of other hardware components such as ASICS, FPGAs, DSPs or similar devices. In addition, the methods, components, and features may be implemented by firmware modules or functional circuitry within hardware devices. Further, the methods, components, and features may be implemented in any combination of hardware devices and computer program components, or in computer programs. Unless specifically stated otherwise, terms such as “receiving,” “performing,” “providing,” “obtaining,” “extracting,” “predicting,” “removing,” “causing,” “interrupting,” “determining,” “training,” “deploying,” or the like, refer to actions and processes performed or implemented by computer systems that manipulates and transforms data represented as physical (electronic) quantities within the computer system registers and memories into other data similarly represented as physical quantities within the computer system memories or registers or other such information storage, transmission or display devices. Also, the terms “first,” “second,” “third,” “fourth,” etc. as used herein are meant as labels to distinguish among different elements and may not have an ordinal meaning according to their numerical designation. Examples described herein also relate to an apparatus for performing the methods described herein. This apparatus may be specially constructed for performing the methods described herein, or it may include a general purpose computer system selectively programmed by a computer program stored in the computer system. Such a computer program may be stored in a computer-readable tangible storage medium. The methods and illustrative examples described herein are not inherently related to any particular computer or other apparatus. Various general purpose systems may be used in accordance with the teachings described herein, or it may prove convenient to construct more specialized apparatus to perform methods described herein and/or each of their individual functions, routines, subroutines, or operations. Examples of the structure for a variety of these systems are set forth in the description above. The above description is intended to be illustrative, and not restrictive. Although the present disclosure has been described with references to specific illustrative examples and implementations, it will be recognized that the present disclosure is not limited to the examples and implementations described. The scope of the disclosure should be determined with reference to the following claims, along with the full scope of equivalents to which the claims are entitled. | 64,399 |
11862494 | Reference numerals:10, processing apparatus;20, first detection apparatus;201, light emitting apparatus;202, light receiving apparatus;30, second detection apparatus;40, crane;41, crane track;42, FOUP;43, semiconductor device;44, FOUP load port. DETAILED DESCRIPTION In order to facilitate understanding of the present disclosure, the present disclosure will be described more fully hereinafter with reference to the accompanying drawings. Preferred embodiments of the present disclosure are illustrated in the accompanying drawings. However, the present disclosure may be embodied in many different forms and is not limited to the embodiments described herein. Rather, these embodiments are provided for the purpose of making a disclosure of the present disclosure more comprehensive. Unless defined otherwise, all technical and scientific terms used herein have the same meaning as commonly understood by those skilled in the art to which the present disclosure belongs. The terminology used in the specification of the present disclosure is for the purpose of describing specific embodiments only and is not intended to limit the present disclosure. The term “and/or” used herein includes any and all combinations of one or more of the associated listed items. In the description of the present disclosure, it should be noted that terminologies of “upper”, “lower”, “vertical”, “horizontal”, “inner”, “outer” and the like that indicate relations of directions or positions are based on the relations of directions or positions shown in the accompanying drawings, which are only to facilitate description of the present disclosure and to simplify the description of the present disclosure, rather than to indicate or imply that the referred device or element is limited to the specific direction or to be operated or configured in the specific direction. Therefore, the above-mentioned terminologies shall not be interpreted as confine to the present disclosure. When the FOUP is transported up and down by the crane, if there is a foreign matter (e.g., a worker or other objects) in a region between the FOUP load port of the semiconductor device and the crane, the worker or other objects may collide with the FOUP to cause damage to the wafer. In order to avoid this situation, in the related art, a light sensor is installed on the semiconductor device. A light emitting terminal is installed at one end of the semiconductor device, and a light receiving terminal is installed at the other end of the semiconductor device. When there is a foreign matter in the monitoring range of the light sensor, the semiconductor device sends a warning signal, and the crane will not transport the FOUP up and down, so that the worker is prevented from colliding with the FOUP. As shown inFIG.1, during the wafer processing, an FOUP42may be used to store and transport a wafer, and the FOUP is transported by a crane40to a semiconductor device43and loaded onto a FOUP load port44of the semiconductor device43. When the FOUP42is transported up and down by the crane40, if there is a foreign matter (e.g., a worker or other objects) in a region between the FOUP load port of the semiconductor device and the crane, the worker or other objects may collide with the FOUP42to cause damage to the wafer. In order to avoid this situation, in the related art, a light sensor is installed on the semiconductor device43. A light emitting terminal is installed at one end of the semiconductor device43, and a light receiving terminal is installed at the other end of the semiconductor device. When there is a foreign matter in the monitoring range of the light sensor, the semiconductor device43sends a warning signal, and the crane40will not transport the FOUP42up and down, so that the worker is prevented from colliding with the FOUP42. However, there is a disadvantage in the related art that in a working state of the semiconductor device43, the light sensor will keep working. In this case, when the crane40does not move up and down, if a worker wants to closely observe or photograph the wafer in the semiconductor device43, it is difficult for the worker to move, and it is easy to trigger the light sensor to cause a false alarm. As shown inFIG.2, in order to solve the foregoing problems, the present disclosure provides a system for monitoring the crane40. The system includes: a first detection apparatus20configured to detect a position of the crane40, to send a first detection signal when the crane40is located above an FOUP load port44, and to send a second detection signal when the crane40leaves a space above the FOUP load port44; a processing apparatus10electrically connected to the first detection apparatus20, and configured to generate a start control signal responsive to receiving the first detection signal, and to generate a stop control signal responsive to receiving the second detection signal; and a second detection apparatus30electrically connected to the processing apparatus10, and configured to start a detection of whether there is a foreign matter between the crane40and the FOUP load port44after receiving the start control signal, and to stop the detection after receiving the stop control signal. When the crane40reaches to the space above the FOUP load port44of the semiconductor device43, the first detection apparatus20detects the crane40and thus sends a first detection signal. The processing apparatus10outputs the start control signal after receiving the first detection signal to trigger the second detection apparatus30. In this case, the second detection apparatus30may be turned on and start the detection. Therefore, the second detection apparatus30may not perform the detection when the crane40does not stop in the space above the FOUP load port44of the semiconductor device43or when the crane40leaves the space above the FOUP load port44of the semiconductor device43. In this case, when the worker is observing or photographing the wafer, he will not be detected by the second detection apparatus30, thereby facilitating the observing and photographing operations of the worker. In an alternative embodiment, the processing apparatus10generates the start control signal and sends the start control signal to the second detection apparatus30after the processing apparatus continuously receives the first detection signal within a first preset time. The start control signal may be set to be generated and sent when a second preset time (e.g., 1-2 s) has passed after the reception of the first detection signal. If the crane40leaves the space above the semiconductor device43within 1-2 seconds and the processing apparatus10does not continuously receive the first detection signal within the first preset time, the processing apparatus10does not generate and send the start control signal. That is, the second detection apparatus30does not receive the start control signal, which greatly reduces the situation that the second detection apparatus30is turned on by mistake since the crane40passes over the semiconductor device43. The crane40does not affect the observing and photographing operations of the worker when the crane just passes over the semiconductor device43. As shown inFIG.3, in an alternative embodiment, the crane40moves along a crane track41. The first detection apparatus20is a light sensing detector and includes a light emitting apparatus201and a light receiving apparatus202. The light emitting apparatus201is arranged on an upper side of the crane track41, and the light receiving apparatus202is arranged on a lower side of the crane track41. The light emitting apparatus201emits the detection light. The light receiving apparatus202is located on a light path of the detection light emitted by the light emitting apparatus201. In an alternative embodiment, a direction of the light path of the detection light is perpendicular to a moving direction of the crane40. The light emitting apparatus201and the light receiving apparatus202of the first detection apparatus20are fixedly connected to the crane track41. The crane40passes between the light emitting apparatus201and the light receiving apparatus202. When the crane40is located between the light emitting apparatus201and the light receiving apparatus202, the light receiving apparatus202cannot receive the light emitted by the light emitting apparatus, so as to generate the first detection signal. When the light receiving apparatus202can receive the detection light emitted by the light emitting apparatus201, the first detection apparatus20generates the second detection signal. Of course, in other examples, the first detection apparatus20may also be an acoustic detector and the like, as long as it is a detector that can realize the foregoing functions, which may be used herein as the first detection apparatus20. Referring toFIG.1andFIG.4, in an alternative embodiment, the second detection apparatus30is a ranging detector. The ranging detector is configured to detect a distance between the crane40and the FOUP load port44, and transmit the detected detection data to the processing apparatus10. The processing apparatus10determines whether there is a foreign matter between the crane40and the FOUP load port44based on the detection data. If there is a foreign matter between the crane40and the FOUP load port44, the processing apparatus10sends a warning signal, and the FOUP will not be conveyed between the crane40and the FOUP load port44. If the second detection apparatus30detects that there is no foreign matter between the crane40and the FOUP load port44, the FOUP42may be conveyed between the crane40and the FOUP load port44. During the conveyance of the FOUP42between the crane40and the FOUP load port44, the second detection apparatus30is further configured to measure the distance between the FOUP42and the crane40. The ranging detector may be an ultrasonic ranging sensor, a laser ranging sensor, or an infrared ranging sensor. The ultrasonic ranging sensor is a sensor developed by using the characteristics of ultrasonic waves, which consists mainly of piezoelectric wafers, and can emit and receive ultrasonic waves. The ultrasonic waves may be significantly reflected by impurities or interfaces to form echoes. If the second detection apparatus30is an ultrasonic ranging sensor, the second detection apparatus30is fixedly connected to the crane track41, and a sound wave emission direction of the second detection apparatus30faces to the FOUP load port44. When the FOUP42is conveyed between the FOUP load port44and the crane40(the FOUP42is conveyed from the crane40to the FOUP load port44and the FOUP42moves from the FOUP load port44to the crane40), the detection data of the second detection apparatus30includes the distance between the FOUP42and the crane40. The working principle of the laser ranging sensor is described as follows. After a laser pulse is generated on a target by a laser diode, the laser is scattered in all directions after being reflected by the target. Part of the scattered light is returned to a sensing receiver, is received by an optical system, and then is imaged onto an avalanche photodiode which is an optical sensor with an internal amplification function. Therefore, an extremely weak optical signal can be detected, and the time elapsed when the laser pulse is emitted, returned, and received can be recorded and processed, so that the target distance can be determined. If the second detection apparatus30is a laser ranging sensor, the second detection apparatus30is fixedly connected to the crane track41, and an emission direction of the laser diode faces to the FOUP load port44. When the FOUP42is conveyed between the FOUP load port44and the crane40, the detection data of the second detection apparatus30includes the distance between the FOUP42and the crane40. The infrared ranging sensor has a pair of infrared signal emitting and receiving diodes. An infrared light beam is emitted by using the infrared ranging sensor, and a reflection process is formed after an object is irradiated by the infrared light beam. After the infrared light beam is reflected to the sensor, a signal is received, and then data of a time difference between emission and reception is received by CCD image processing. A distance from the object is calculated after the signal is processed by a signal processor. If the second detection apparatus30is a laser ranging sensor, the second detection apparatus30is fixedly connected to the crane track41, and the infrared light emitted by the infrared ranging sensor faces to the FOUP load port44. When the FOUP42is conveyed between the FOUP load port44and the crane40, the detection data of the second detection apparatus30includes the distance between the FOUP42and the crane40. In an alternative embodiment, by measuring the distance between the FOUP42and the crane40, a conveying speed of the FOUP42and whether the FOUP42is inclined may be detected when the FOUP42is conveyed between the crane40and the FOUP load port44, so as to determine whether the FOUP42is abnormal during conveyance. Specifically, the processing apparatus10obtains a travelling speed trend graph and/or a swing balance trend graph of the FOUP42based on the detection data detected by the second detection apparatus30. The processing apparatus10may be a central processing unit for processing information. When the FOUP42is detected by the second detection apparatus30, a distance between the FOUP42and the crane track41is measured. These data are transmitted to the processing apparatus10. The traveling speed of the FOUP42may be calculated through the change of the distance between the FOUP and the crane track, and the speed trend graph of the FOUP42may be made according to the detection data and the historical detection data. It is also possible to detect whether the FOUP42is inclined while the FOUP42is conveyed between the crane40and the FOUP load port44, thereby obtaining a swing balance trend graph. By comparing the current detection data with the speed trend graph and/or the swing balance trend graph, it is possible to determine whether the FOUP42has an abnormal motion. Meanwhile, according to the data of the semiconductor device43, it is determined whether the abnormal motion of the FOUP42is caused by the semiconductor device43or by the crane40. In an alternative embodiment, the processing apparatus10includes a transmission circuit for transmitting detection data detected by the second detection apparatus30to a main system for storage. The detection data is uploaded to the main system for storage through the transmission circuit, so that data loss possibly caused by system failure is avoided. Even if the device is replaced, the data is still reserved, thereby facilitating other subsequent researches. In an alternative embodiment, the processing apparatus10includes a counting assembly for counting the number of times of starting and stopping of the second detection apparatus30and counting the capacity of the corresponding semiconductor device43within a specified time period based on the number of times of starting and stopping of the second detection apparatus30. Since the second detection apparatus30works only when the semiconductor device43interacts with the FOUP42, the number of times of starting and stopping of the second detection apparatus30corresponds to the capacity of the semiconductor device43. A time period, such as an hour, a day, or a month, etc., is specified, and the capacity of the semiconductor device43within such a time period may be counted by counting the number of times of starting and stopping of the second detection apparatus30within the specified time period. In an alternative embodiment, a detection range of the second detection apparatus30covers a region between the crane40and all of the FOUP load ports44on the semiconductor device43. Therefore, less detection or false detection is not easy to occur. As shown inFIG.5, the present disclosure also provides a method for monitoring a crane40, which may be executed based on the crane monitoring system described in the above embodiments. For the specific structure of the crane monitoring system, reference is made to the above embodiments, which will not be repeated herein. The method includes the following operations. In S10, a position of a crane40is detected by a first detection apparatus20, a first detection signal is sent by the first detection apparatus when the crane40is located above an FOUP load port44of a semiconductor device43, and a second detection signal is sent by the first detection apparatus when the crane40leaves a space above the FOUP load port44. In S20, a start control signal is generated by a processing apparatus10when the first detection signal is received by the processing apparatus, and a stop control signal is generated by the processing apparatus when the second detection signal is received by the processing apparatus. In S30, a detection of whether there is a foreign matter between the crane40and the FOUP load port44is started by a second detection apparatus after the start control signal is received by the second detection apparatus, and the detection is stopped by the second detection apparatus after the stop control signal is received by the second detection apparatus. In an alternative embodiment, in S10, specifically, the crane40moves along a crane track41. The first detection apparatus20may be a light sensing detector and includes a light emitting apparatus201and a light receiving apparatus202. The light emitting apparatus201is arranged on an upper side of the crane track41, and the light receiving apparatus202is arranged on a lower side of the crane track41. The light emitting apparatus201emits the detection light. The light receiving apparatus202is located on a light path of the detection light emitted by the light emitting apparatus201. In an alternative example, a direction of the light path of the detection light is perpendicular to a moving direction of the crane40. The light emitting apparatus201and the light receiving apparatus202of the first detection apparatus20are fixedly connected to the crane track41. The crane40passes between the light emitting apparatus201and the light receiving apparatus202. When the crane40is located between the light emitting apparatus201and the light receiving apparatus202, the light receiving apparatus202cannot receive the light emitted by the light emitting apparatus, so that a first detection signal is generated. When the light receiving apparatus202can receive the detection light emitted by the light emitting apparatus201, the first detection apparatus20generates a second detection signal. In S20, in an alternative embodiment, specifically, the first detection apparatus20is electrically connected to the processing apparatus10. The processing apparatus10generates a start control signal responsive to receiving the first detection signal, and generates a stop control signal responsive to receiving the second detection signal. The processing apparatus10may be a central processing unit for processing information. In an alternative embodiment, the processing apparatus10generates the start control signal and sends the start control signal to the second detection apparatus30after the processing apparatus continuously receives the first detection signal within a first preset time. The start control signal may be set to be generated and sent when a second preset time (e.g., 1-2 s) has passed after the reception of the first detection signal. If the crane40leaves the space above the semiconductor device43within 1-2 seconds and the processing apparatus10does not continuously receive the first detection signal within the first preset time, the processing apparatus10does not generate and send the start control signal. That is, the second detection apparatus30does not receive the start control signal, which greatly reduces the situation that the second detection apparatus30is turned on by mistake since the crane40passes over the semiconductor device43. The crane40does not affect the observing and photographing operations of the worker when the crane just passes over the semiconductor device43. In S30, in an alternative embodiment, specifically, the second detection apparatus30is a ranging detector. The ranging detector is configured to detect the distance between the crane40and the FOUP load port44, and transmit the detected detection data to the processing apparatus10. The processing apparatus10determines whether there is a foreign matter between the crane40and the FOUP load port44based on the detection data. If there is a foreign matter between the crane40and the FOUP load port44, the processing apparatus10sends a warning signal. The ranging detector may be an ultrasonic ranging sensor, a laser ranging sensor, or an infrared ranging sensor. The ultrasonic ranging sensor is a sensor developed by using the characteristics of ultrasonic waves, which consists mainly of piezoelectric wafers, and can emit and receive ultrasonic waves. The ultrasonic waves may be significantly reflected by impurities or interfaces to form echoes. If the second detection apparatus30is an ultrasonic ranging sensor, the second detection apparatus30is fixedly connected to the crane track41, and a sound wave emission direction of the second detection apparatus30faces to the FOUP load port44. When the FOUP42is conveyed between the FOUP load port44and the crane40, the detection data of the second detection apparatus30includes the distance between the FOUP42and the crane40. The working principle of the laser ranging sensor is described as follows. After laser pulse is generated on a target by a laser diode, laser is scattered in all directions after being reflected by the target. Part of the scattered light is returned to a sensing receiver, is received by an optical system, and then is imaged onto an avalanche photodiode which is an optical sensor with an internal amplification function. Therefore, an extremely weak optical signal can be detected, and the time elapsed when the laser pulse is emitted, returned, and received can be recorded and processed, so that the target distance can be determined. If the second detection apparatus30is a laser ranging sensor, the second detection apparatus30is fixedly connected to the crane track41, and an emission direction of the laser diode faces to the FOUP load port44. When the FOUP42is conveyed between the FOUP load port44and the crane40, the detection data of the second detection apparatus30includes the distance between the FOUP42and the crane40. The infrared ranging sensor has a pair of infrared signal emitting and receiving diodes. An infrared light beam is emitted by using the infrared ranging sensor, and a reflection process is formed after an object is irradiated by the infrared light beam. After the infrared light beam is reflected to the sensor, a signal is received, and then data of a time difference between emission and reception is received by CCD image processing. A distance from the object is calculated after the signal is processed by a signal processor. If the second detection apparatus30is a laser ranging sensor, the second detection apparatus30is fixedly connected to the crane track41, and the infrared light emitted by the infrared ranging sensor faces to the FOUP load port44. When the FOUP42is conveyed between the FOUP load port44and the crane40, the detection data of the second detection apparatus30includes the distance between the FOUP42and the crane40. In an alternative embodiment, a detection range of the second detection apparatus30covers a region between the crane40and all of the FOUP load ports44on the semiconductor device43. Therefore, less detection or false detection is not easy to occur. As shown inFIG.6, in an alternative embodiment, after S30, the method further includes the following operations. In S40, the FOUP42is conveyable between the crane40and the FOUP load port44after the second detection apparatus30detects that there is no foreign matter between the crane40and the FOUP load port44, and a conveying speed of the FOUP42and whether the FOUP is inclined are further detected by the second detection apparatus30when the FOUP42is conveyed between the crane40and the FOUP load port44, so as to determine whether the FOUP42is abnormal during conveyance. Specifically, the second detection apparatus30is electrically connected to the processing apparatus10, and transmits the detected detection data to the processing apparatus10. When the second detection apparatus30detects that there is no foreign matter between the crane40and the FOUP load port44, the FOUP42may be conveyed between the crane40and the FOUP load port44. In the conveying process of the FOUP42between the crane40and the FOUP load port44, the second detection apparatus30can measure the distance between the FOUP42and the crane40in real time. The second detection apparatus30is further configured to detect the conveying speed of the FOUP42and whether the FOUP42is inclined when the FOUP42is conveyed between the crane40and the FOUP load port44, so as to determine whether the FOUP42is abnormal during conveyance. The processing apparatus10obtains a travelling speed trend graph and/or a swing balance trend graph of the FOUP42based on the detection data detected by the second detection apparatus30. The processing apparatus10may be a central processing unit for processing information. When the FOUP42is detected by the second detection apparatus30, the distance between the FOUP42and the crane track41is measured. These data are transmitted to the processing apparatus10. The traveling speed of the FOUP42may be calculated by the change of the distance between the FOUP and the crane track, and the speed trend graph of the FOUP42may be made according to the detection data and the historical detection data. It is also possible to detect whether the FOUP42is inclined while the FOUP42is conveyed between the crane40and the FOUP load port44, thereby obtaining a swing balance trend graph. By comparing the current detection data with the speed trend graph and/or the swing balance trend graph, it is possible to determine whether the FOUP42has an abnormal motion. Meanwhile, according to the data of the semiconductor device43, it is determined whether the abnormal motion of the FOUP42is caused by the semiconductor device43or by the crane40. As shown inFIG.6, in an alternative embodiment, after S40, the method further includes the following operations. In S50, detection data detected by the second detection apparatus30is transmitted to a main system for storage. In S60, the number of times of starting and stopping of the second detection apparatus30is counted, and capacity of the semiconductor device43is counted based on the number of times of starting and stopping of the second detection apparatus30. In S50, specifically, the processing apparatus10includes a transmission circuit for transmitting the detection data detected by the second detection apparatus30to a main system for storage. The detection data is uploaded to the main system for storage through the transmission circuit, so that data loss possibly caused by system failure is avoided. Even if the device is replaced, the data is still reserved, thereby facilitating other subsequent researches. In S60, specifically, the processing apparatus10includes a counting assembly for counting the number of times of starting and stopping of the second detection apparatus30and counting the capacity of the corresponding semiconductor device43within a specified time period based on the number of times of starting and stopping of the second detection apparatus30. Since the second detection apparatus30works only when the semiconductor device43interacts with the FOUP42, the number of times of starting and stopping of the second detection apparatus30corresponds to the capacity of the semiconductor device43. A time period, such as an hour, a day, or a month, etc., is specified, and the capacity of the semiconductor device43within such a time period may be counted by counting the number of times of starting and stopping of the second detection apparatus30within the specified time period. In the present disclosure, when the crane40reaches to the space right above the FOUP load port44and the FOUP42is ready to be lowered to a specified position, the first detection apparatus20detects the crane40and thus sends a first detection signal. The processing apparatus10outputs a start control signal after receiving the first detection signal to trigger the second detection apparatus30. In this case, the second detection apparatus30may be turned on and start the detection. Therefore, the second detection apparatus30may not perform the detection when the crane40dose not transport the FOUP42. In this case, when the worker is observing or photographing the wafer, he will not be detected by the second detection apparatus30, thereby facilitating the observing and photographing operations of the worker. The technical features of the embodiments described above can be arbitrarily combined. In order to make the description simple, not all the possible combinations of the technical features in the above embodiments are completely described. However, all of the combinations of these technical features should be considered as within the scope described in the present specification as long as there is no contradiction in the combinations of these technical features. The above embodiments merely illustrate several implementations of the present disclosure, and the description thereof is specific and detailed, but they are not constructed as limiting the patent scope of the present disclosure. It should be noted that a number of variations and improvements made by those of ordinary skill in the art without departing from the conception of the present disclosure are within the protection scope of the present disclosure. Therefore, the patent protection scope of the present disclosure should be subject to the appended claims. | 30,184 |
11862495 | DESCRIPTION OF EMBODIMENTS The embodiments of the monitor wafer measuring method and measuring apparatus according to the present application will be described in details below in conjunction with the accompanying drawings. Provided in this embodiment of the present invention is a monitor wafer measuring method.FIG.1is a flow chart illustrating a monitor wafer measuring method in the embodiments of the present application,FIG.2is a schematic structural diagram of a measuring apparatus in the embodiments of the present application, and the monitor wafer measuring method as shown inFIG.1may be applied to the measuring apparatus as illustrated inFIG.2. As shown inFIG.1andFIG.2, the monitor wafer measuring method according to this embodiment includes the following steps. Step S11: fixing a product wafer22, the product wafer22having several alignment marks221and product measuring sites222corresponding respectively to the alignment marks221. In particular, the product wafer22is used as a reference system for positioning a monitor wafer. While positioning, the product wafer22remains unchanged with respect to a carrying surface inside the measuring apparatus for carrying the product wafer. With the measuring apparatus shown inFIG.2as an example, a first carrying structure20in the measuring apparatus is configured for carrying the product wafer22. While the product wafer22is utilized as the reference system for positioning a monitor wafer, the product wafer22remains unchanged with respect to the position of the first carrying structure. The first carrying structure20may be, but not limited to, a chuck. There may be one or a plurality of alignment marks221on the product wafer22. The number of the alignment marks221may be chosen by those skilled in the art based on actual needs, e.g., based on the number of measuring sites to be measured on the monitor wafer. “A/the plurality of” mentioned in this embodiment refers to two and more than two. The specific shapes of the alignment marks221can be set by those skilled in the art, as actually required. When there are a plurality of alignment marks221on the product wafer22, the shapes of the plurality of alignment marks221could be different, in order to facilitate identification for different measuring sites to be measured on the monitor wafer. Step S12: determining the product measuring sites222according to the alignment marks221. Step S13: placing a monitor wafer23, a projection of the monitor wafer23in a vertical direction being aligned with and coinciding with the product wafer22. The projection of the monitor wafer23in the vertical direction being aligned with and coinciding with the product wafer22means that, after the product wafer22and the monitor wafer23are fixed, the projection of the monitor wafer23in the vertical direction coincides completely with the product wafer22. The measuring apparatus shown inFIG.2is still taken as an example. A second carrying structure21in the measuring apparatus is configured for carrying the monitor wafer23. When the monitor wafer23is fixed to the second carrying structure21, the projection of the monitor wafer23in a Z-axis direction is aligned with and coincides with the product wafer22located on the first carrying structure20. Defining a relative position relationship between the monitor wafer23and the product wafer22facilitates subsequent measurement for the monitor wafer23by taking the product wafer22as the reference system. The second carrying structure21may be, but not limited to, a chuck. In particular, after the product measuring sites222on the product wafer22are determined according to the alignment marks221, i.e., positional alignment of the product wafer22on the measuring apparatus is realized, the product wafer22can then be measured directly. When the monitor wafer23is placed, it is ensured that the projection of the monitor wafer23in the vertical direction is aligned with and coincides with the product wafer22. Due to the alignment of the position of the product wafer22on the measuring apparatus, the alignment of the corresponding monitor wafer23on the measuring apparatus is also attained, which is to say, the alignment for the measuring position of the monitor wafer23is achieved by the product wafer22. Alternatively, the method, after placing the monitor wafer23, further includes:measuring the monitor wafer23directly. In particular, when the measuring sites to be measured on the monitor wafer23are corresponding to the product measuring sites222determined on the product wafer22, the monitor wafer23can be measured directly since the projection of the monitor wafer23in the vertical direction is aligned with and coincides with the product wafer22. Alternatively, the monitor wafer23has a plurality of measuring sites to be measured thereon, the plurality of product measuring sites222are in one-to-one correspondence with the plurality of measuring sites to be measured; the method, after placing the monitor wafer, further includes the following steps:selecting a measuring site to be measured232as a target measuring site to be measured232, and selecting a standard measuring site corresponding to the target measuring site to be measured232as a target standard measuring site, to take the alignment mark221corresponding to the target standard measuring site as a target alignment mark221; andmeasuring the target measuring site to be measured232according to the target alignment mark221. Alternatively, the step of measuring the target measuring site to be measured232according to the target alignment mark221includes:judging whether the target alignment mark221is aligned with a predetermined position261, and if so, measuring the target measuring site to be measured232. Alternatively, the step of judging whether the target alignment mark221is aligned with a predetermined position261includes:judging, through an optical detection method, whether the target alignment mark221is aligned with the predetermined position261. Alternatively, the method further includes the following step:judging whether the target alignment mark221is aligned with the predetermined position261, and if not, moving the product wafer22and the monitor wafer23synchronously. In particular, as shown inFIG.2, a first measuring unit26and a first stage27connected with the first measuring unit26may also be provided in the measuring apparatus. The first measuring unit26is configured for judging, through an optical detection method, whether the target alignment mark221is aligned with the predetermined position261. The first stage27extends in a vertical direction (i.e., Z-axis direction inFIG.2), the first measuring unit26may move in the extension direction (i.e., Z-axis direction) of the first stage27, and accordingly the distance between the first measuring unit26and the first stage27is adjusted to obtain a clear alignment mark221image. The first stage27and the first measuring unit26are invariable in their positions. The predetermined position261is a detection position for the first measuring unit26. The product measuring sites222on the product wafer22are in one-to-one correspondence with the measuring sites to be measured on the monitor wafer23, and for each product measuring site222on the product wafer22, an alignment mark221corresponding thereto is set. After one measuring site to be measured232on the monitor wafer23is selected as the target measuring site to be measured232, the target alignment mark221corresponding to the target measuring site to be measured232can be obtained in accordance with a corresponding relationship among the measuring site to be measured232, the standard measuring site and the alignment mark221. Subsequently, the positions of the product wafer22and the monitor wafer23inside the measuring apparatus can be corrected by identifying the target alignment mark221via the first measuring unit26. For example, when the first measuring unit26does not detect the target alignment mark221, it is confirmed that the target alignment mark221is not aligned with the predetermined position261, and the product wafer22and the monitor wafer23are moved synchronously until the first measuring unit26can detect the complete target alignment mark221. Alternatively, the monitor wafer measuring method further includes the following steps:providing a measuring component for measuring the monitor wafer23;acquiring a spacing between each standard measuring site and the alignment mark221corresponding thereto;moving the product wafer22and the monitor wafer23synchronously according to the spacing between the target alignment mark221and the target standard measuring site when it is confirmed that the target alignment mark221is aligned with the predetermined position261, such that the target measuring site to be measured232is aligned with the measuring component; andmeasuring the target measuring site to be measured232through the measuring component. In particular, after the position of the monitor wafer23is corrected through the alignment mark221on the product wafer22, in order to ensure that the direction and distance of movement of the monitor wafer23are the same as the direction and distance of movement of the product wafer22and further that there is high measurement accuracy at the target measuring site to be measured232on the monitor wafer23, it is required to move the product wafer22and the monitor wafer23synchronously. Alternatively, the step of placing a monitor wafer23includes:fixing a monitor wafer23above the product wafer22, such that a projection of the monitor wafer23in a vertical direction is aligned with and coincides with the product wafer22. Alternatively, the step of moving the product wafer22and the monitor wafer23synchronously includes:providing a first carrying structure20and a second carrying structure21located above the first carrying structure20, the first carrying structure20being configured for carrying and fixing the product wafer22, the second carrying structure21being configured for carrying and fixing the monitor wafer23, the first carrying structure20and the second carrying structure21being connected to a same moving structure24; andsynchronously driving the first carrying structure20and the second carrying structure21to move through the moving structure24. For example, as shown inFIG.2, the measuring apparatus includes a pedestal30and the moving structure24is arranged on the pedestal30. The first carrying structure20is arranged above the moving structure, the second carrying structure21is arranged above the first carrying structure20, the first carrying structure20and the second carrying structure21are connected through a connecting structure29, and the first carrying structure20is connected with the moving structure24. The moving structure24includes a first driving portion241and a second driving portion242. The first driving portion241is configured for driving the first carrying structure20to move in a first horizontal direction (e.g., X-axis direction), while causing, through the connecting structure29, the second carrying structure21to move synchronously in the first horizontal direction. The second driving portion242is configured for driving the first carrying structure20to move in a second horizontal direction (e.g., Y-axis direction), while causing, through the connecting structure29, the second carrying structure21to move synchronously in the second horizontal direction. The first horizontal direction is perpendicular to the second horizontal direction. This embodiment involves arranging the first carrying structure20below the second carrying structure21. Also, those skilled in the art may adjust, as actually required, the relative position relationship between the first carrying structure20and the second carrying structure21, e.g., the first carrying structure20is arranged above the second carrying structure21. When a plurality of monitor wafers are measured or a plurality of measuring sites to be measured on one monitor wafer are measured, the position of the product wafer acting as the reference system is unchanged, in order to ensure the accuracy and comparability of measurement results. However, when the first carrying structure for carrying the product wafer or the moving structure connected with the first carrying structure is replaced due to hardware issues, recalibration is desired for the position of the product wafer. The method for calibrating the position of the product wafer may involve setting a calibration mark on the product wafer and then adjusting the position of the product wafer by identifying the calibration mark. Furthermore, also provided in this embodiment is a measuring apparatus, andFIG.2is a schematic structural diagram of the measuring apparatus in the embodiments of the present application. The measuring apparatus according to this embodiment may measure a monitor wafer using the method as shown inFIG.1. As illustrated inFIG.2, the measuring apparatus includes:a first carrying structure20for carrying and fixing a product wafer22, the product wafer22having several alignment marks221and product measuring sites222corresponding respectively to the alignment marks221;a second carrying structure21for carrying and fixing a monitor wafer23, a projection of the monitor wafer23located on the second carrying structure21, in a vertical direction, being aligned with and coinciding with the product wafer22located on the first carrying structure20; anda measuring module for measuring the monitor wafer23after the product measuring sites222are determined according to the alignment marks221. Alternatively, the monitor wafer23has a plurality of measuring sites to be measured thereon, the plurality of product measuring sites222are in one-to-one correspondence with the plurality of measuring sites to be measured;the measuring module is further configured for judging whether a target alignment mark221is aligned with a predetermined position261, the target alignment mark221is an alignment mark221corresponding to a target standard measuring site, the target standard measuring site is a standard measuring site corresponding to a target measuring site to be measured232, and the target measuring site to be measured232is a measuring site to be measured232selected by a user. Alternatively, the measuring module includes:a first measuring unit26located above the first carrying structure20, for judging whether the target alignment mark221is aligned with the predetermined position261. Alternatively, the measuring apparatus further includes:a measuring component for measuring the monitor wafer23;the measuring module is further configured for acquiring a spacing between each standard measuring site and the alignment mark221corresponding thereto; when it is confirmed that the target alignment mark221is aligned with the predetermined position261, the measuring module is further configured for moving the product wafer22and the monitor wafer23synchronously according to the spacing between the target alignment mark221and the target standard measuring site, such that the target measuring site to be measured232is aligned with the measuring component. Alternatively, the first carrying structure20is located below the second carrying structure21. Alternatively, the second carrying structure21is further configured for carrying a semiconductor structure, the semiconductor structure having an identification mark therein;a second measuring unit25located above the second carrying structure21, for measuring the monitor wafer23and for judging whether the identification mark is aligned with the predetermined position261. In particular, the measuring apparatus further includes a second stage28, the second stage28extends in a vertical direction (i.e., Z-axis direction), the second measuring unit25may move up and down along the second stage28, so that the distance between the second measuring unit25and the semiconductor structure located above the second carrying structure21is adjusted to obtain a clear identification mark image. When the semiconductor structure (i.e., a process product) is measured, since the semiconductor structure itself has the identification mark, the identification mark on the semiconductor structure can be identified directly by the second measuring unit25, so as to correct the position of the semiconductor structure without any correction through the product wafer. Alternatively, the measuring apparatus further includes:a connecting structure29located between the first carrying structure20and the second carrying structure21, for connecting the first carrying structure20and the second carrying structure21; anda moving structure24located below and connected with the first carrying structure20, for synchronously driving the first carrying structure20and the second carrying structure21to move. In the monitor wafer measuring method and measuring apparatus according to this embodiment, measuring sites on a monitor wafer are determined by providing a product wafer having alignment marks221and identifying the alignment marks221on the product wafer while the monitor wafer is measured. That is, the product wafer is taken as a reference system, so that positional errors of the monitor wafer during the measurement process can be reduced or even eliminated, and product-level measuring position accuracy can be achieved for the monitor wafer. | 17,454 |
11862496 | DETAILED DESCRIPTION Various exemplary embodiments will be described below. In the following detailed description, numerous specific details are set forth in order to provide a thorough understanding of the present disclosure. However, it will be apparent to one of ordinary skill in the art that the present disclosure may be practiced without these specific details. In other instances, well-known methods, procedures, systems, and components have not been described in detail so as not to unnecessarily obscure aspects of the various embodiments. In one exemplary embodiment, there is provided a substrate processing control method in a substrate processing apparatus that includes a first factor including a plurality of first levels for performing a first process on a substrate based on a first parameter, and a second factor including a plurality of second levels for performing a second process on the substrate based on a second parameter, the method including: an acquisition step of acquiring a data set for each of a plurality of substrates subjected to the first process at the first level and then subjected to the second process at the second level, the data set including information specifying the first level at which the first process has been performed, information specifying the second level at which the second process has been performed, and information about a characteristic amount relating to characteristics of the substrate; a calculation step of calculating information including an expected value of the characteristic amount, a level deviation of the first level with respect to the expected value, and a level deviation of the second level with respect to the expected value based on the data set corresponding to each of the plurality of substrates; and a correction step of correcting the first parameter at the first level or the second parameter at the second level based on the information calculated in the calculation step. In the above-mentioned substrate processing control method, the data set including the information specifying the first level at which the first process has been performed, the information specifying the second level at which the second process has been performed, and the information about a characteristic amount relating to characteristics of the substrate is acquired. Then, in the calculation step, the information including the expected Value of the characteristic amount, the level deviation of the first level with respect to the expected value, and the level deviation of the second level with respect to the expected value is calculated based on this data set. Furthermore, the first parameter at the first level or the second parameter at the second level is corrected based on the information thus calculated. With such a configuration, the parameters can be corrected based on the expected value of the characteristic amount and the level deviation, which are calculated for the first level and the second level. Accordingly, even if the substrates have been processed at a plurality of levels such as plural types of processing units, it is possible to appropriately correct the target value for each unit through the use of the data set including the characteristic amount of the substrate. In the calculation step, the information including the level deviation of the first level with respect to the expected value and the level deviation of the second level with respect to the expected value may be calculated based on the data set corresponding to each of the plurality of substrates so that the norm other than the expected value of the characteristic amount based on the data set is minimized. With the above configuration, when calculating the first level deviation at the first level and the second level deviation at the second level, the level deviations are calculated so that the norm other than the expected value of the characteristic amount is minimized. Thus, for example, even when only a data set falling within a range, in which the unit deviation for each unit cannot be calculated by the conventional method such as the least square method or the like, can be acquired, it is possible to calculate the first level deviation and the second level deviation. Accordingly, it is possible to appropriately perform the correction for each unit with respect to the expected value of the characteristic amount. In the calculation step, when a norm minimization priority corresponding to an order of prioritizing reduction of correction values of the first factor and the second factor is predetermined for the first factor and the second factor, a unit deviation may be calculated sequentially from the factor having a higher norm minimization priority based on the data set so that the norm other than the expected value of an average value of the characteristic amounts is minimized. When the norm minimization priority corresponding to the order of prioritizing reduction of the correction values is determined for each factor, the unit deviation is calculated sequentially from the factor having a high norm minimization priority so that the norm is minimized. With such a configuration, it is possible to prevent the factor having the high norm minimization priority from being corrected by including a unit deviation derived from another factor. Accordingly, it becomes possible to reduce the correction value for the factor having the high norm minimization priority. In another exemplary embodiment, there is provided a substrate processing apparatus including: a plurality of first processing units configured to perform a first process on a substrate based on a first parameter; a plurality of second processing units configured to perform a second process on the substrate based on a second parameter; a characteristic amount information acquisition part configured to acquire information about characteristics of the substrate subjected to the first process in one of the plurality of first processing units and then subjected to the second process in one of the plurality of second processing units; and a controller configured to control the plurality of first processing units and the plurality of second processing units, wherein the controller is configured to: acquire a data set for each of a plurality of substrates subjected to the first process in the one of the plurality of first processing units and then subjected to the second process in the one of the plurality of second processing units from the characteristic amount information acquisition part, the data set including information specifying the first processing unit in which the first process has been performed, information specifying the second processing unit in which the second process has been performed, and information about a characteristic amount relating to the characteristics of the substrate; calculate information including an expected value of the characteristic amount, a unit deviation of the first processing unit with respect to the expected value, and a unit deviation of the second processing unit with respect to the expected value based on the data set corresponding to each of the plurality of substrates; and correct the first parameter in the first processing unit or the second parameter in the second processing unit based on the calculated information. In another exemplary embodiment, there is provided a non-transitory computer-readable storage medium storing a program that causes an apparatus to execute the aforementioned substrate processing control method. Various exemplary embodiments will be described below. In the description, the same elements or the elements having the same function will be designated by like reference symbols, and the redundant description thereof will be omitted. [Substrate Processing System] A substrate processing system1is a system that forms a photosensitive film on a substrate, exposes the photosensitive film, and develops the photosensitive film. The substrate to be processed is, for example, a semiconductor wafer W. The substrate processing system1includes a coating/developing apparatus2and an exposure apparatus3. The exposure apparatus3performs an exposure process on a resist film (photosensitive film) formed on the wafer W (substrate). Specifically, the exposure apparatus3irradiates an exposure target portion of the resist film with energy rays by a method such as liquid immersion exposure or the like. The coating/developing apparatus2performs a process of forming a resist film on the surface of the wafer W (substrate) before the exposure process performed by the exposure apparatus3, and performs a developing process on the resist film after the exposure process. [Substrate Processing Apparatus] A configuration of the coating/developing apparatus2will be described below as an example of a substrate processing apparatus. As shown inFIGS.1and2, the coating/developing apparatus2includes a carrier block4, a processing block5, an interface block6, and a control device100(control part). The carrier block4loads the water W into the coating/developing apparatus2and unloads the wafer W from the coating/developing apparatus2. For example, the carrier block4is capable of supporting a plurality of carriers C (accommodation parts) for the wafer W and is provided with a transfer device A1including a delivery arm built therein. The carrier C accommodates, for example, a plurality of circular wafers W. The transfer device A1takes out the wafer W from the carrier C and delivers the wafer W to the processing block5. The transfer device A1receives the wafer W from the processing block5and returns the wafer W into the carrier C. The processing block5includes a plurality of processing modules11,12,13and14. The processing module11includes a plurality of coating units U1, a plurality of heat treatment units U2, a plurality of inspection units U3, and a transfer device A3that transfers the wafer W to these units. The processing module11forms a lower layer film on the surface of the wafer W using the coating unit U1and the heat treatment unit U2. For example, the coating unit U1of the processing module11coats a processing liquid for formation of the lower layer film on the wafer W while rotating the wafer W at a predetermined rotation speed. The heat treatment unit112of the processing module11performs various heat treatments associated with the formation of the lower layer film. The heat treatment unit U2includes, for example, a heating plate and a cooling plate built therein. The heat treatment unit U2performs a heat treatment by heating the wafer W with the heating plate to a predetermined heating temperature and cooling the heated water W with the cooling plate. The inspection unit U3performs a process for inspecting the surface state of the wafer W, and acquires, for example, information about a film thickness as information indicating the surface state of the wafer W. The processing module12includes a plurality of coating units U1, a plurality of heat treatment units U2, a plurality of inspection units U3, and a transfer device A3that transfers the wafer W to these units. The processing module12forms a resist film on the lower layer film using the coating unit U1and the heat treatment unit U2. The processing module12may be referred to as a COT module. Further, the coating unit U1of the processing module12may be referred to as a COT unit. The coating unit U1of the processing module12forms a coating film on the surface of the wafer W by coating a processing liquid for forming the resist film on the lower layer film. The heat treatment unit U2of the processing module12performs various heat treatments associated with the formation of the resist film. The heat treatment unit U2of the processing module12forms a resist film by subjecting the wafer W, on which the coating film is formed, to a heat treatment (PAB: Pre Applied Bake) at a predetermined heating temperature. The inspection unit U3performs a process for inspecting the surface state of the wafer W, and acquires, for example, information about a film thickness as information indicating the surface state of the wafer W. The processing module13includes a plurality of coating units U1, a plurality of heat treatment units U2, a plurality of inspection units U3, and a transfer device A3that transfers the wafer W to these units. The processing module13forms an upper layer film on the resist film using the coating unit U1and the heat treatment unit U2. For example, the coating unit U1of the processing module13coats a liquid for forming the upper layer film on the resist film while rotating the wafer W at a predetermined rotation speed. The heat treatment unit U2of the treatment module13performs various heat treatments associated with the formation of the upper layer film. The inspection unit U3performs a process for inspecting the surface state of the wafer W, and acquires, for example, information about a film thickness as information indicating the surface state of the wafer W. The processing module14includes a plurality of coating units U1, a plurality of heat treatment units U2, and a transfer device A3that transfers the wafer W to these units. The processing module14develops the exposed resist film using the coating unit U1and the heat treatment unit U2. The coating unit U1of the processing module14develops the resist film, for example, by applying a developing liquid onto the surface of the exposed wafer W while rotating the wafer W at a predetermined number of rotations, and then rinsing the wafer W with a rinsing liquid. The heat treatment unit U2of the processing module14performs various heat treatments associated with the developing process. Specific examples of the heat treatment may include a heat treatment before the developing process (PEB: Post Exposure Bake), a heat treatment after the developing process (PB: Post Bake), and the like. A shelf unit U10is provided in the processing block5on the side of the carrier block4. The shelf unit U10is divided into a plurality of cells arranged in a vertical direction. A transfer device A7including a lifting arm is provided near the shelf unit U10. The transfer device A7moves the wafer W up and down between the cells of the shelf unit U10. A shelf unit U11is provided in the processing block5on the side of the interface block6. The shelf unit U11is divided into a plurality of cells arranged in the vertical direction. The interface block6delivers the wafer W to and from the exposure apparatus3. For example, the interface block6is provided with a transfer device A8including a delivery arm built therein and is connected to the exposure apparatus3. The transfer device A8transfers the wafer W disposed on the shelf unit U11to the exposure apparatus3, receives the wafer W from the exposure apparatus3, and returns the wafer W to the shelf unit U11. [Inspection Unit] The inspection unit U3included in each of the processing modules11to13will be described. The inspection unit U3acquires information about a film thickness of the film (the lower layer film, the resist film or the upper layer film) formed by the coating unit U1and the heat treatment unit U2. In the present embodiment, the film thickness is a kind of information relating to the characteristics of the substrate, and is used as a characteristic amount indicating the characteristics of the substrate on which the film is formed. As shown inFIG.3, the inspection unit U3includes a housing30, a holding part31, a linear driving part32, a capturing part33, and a light projecting/reflecting part34. The holding part31holds the wafer W horizontally. The linear driving part32uses, for example, an electric motor as a power source, and moves the holding part31along a horizontal linear path. The capturing part33has a camera35such as a CCD camera or the like. The camera35is provided on one end side in the inspection unit U3in the movement direction of the holding part31and is oriented to the other end side in the movement direction. The light projecting reflecting part34projects light onto the capturing range and guides the reflected light from the capturing range toward the camera35. For example, the light projecting/reflecting part34has a half mirror36and a light source37. The half mirror36is provided at a position higher than the holding part31in the middle portion of the movement range of the linear driving part32, and is configured to reflect light from below toward the camera35. The light source37is provided above the half mirror36, and is configured to irradiate illumination light downward through the half mirror36. The inspection unit U3operates as follows to acquire image data of the surface of the wafer W. First, the linear driving part32moves the capturing part33. Thus, the wafer W passes under the half mirror36. In this passing process, the reflected light from each portion of the surface of the wafer W is sequentially sent to the camera35. The camera35focuses an image using the reflected light from each portion of the surface of the wafer W, and acquires image data of the surface of the wafer W. When a film thickness of the film formed on the surface of the wafer W is changed, for example, the color of the surface of the wafer W is changed according to the film thickness, whereby the image data of the surface of the wafer W obtained by the camera35is changed. That is, the acquisition of the image data of the surface of the wafer W is equivalent to the acquisition of information about the film thickness of the film formed on the surface of the wafer W. The method of calculating the film thickness from the image data is not particularly limited. The image data acquired by the camera35is sent to the control device100. The control device100may estimate the film thickness of the film on the surface of the wafer W based on the image data. The estimation result is held as an inspection result in the control device100. [Control Device] An example of the control device100will be described in detail. The control device100controls each element included in the coating/developing apparatus2. The control device100is configured to perform a process including an act of forming each of the above-described films on the surface of the wafer W and an act of performing the developing process. The control device100is also configured to execute correction of parameters relating to the process based on the result of executing the process. Details of the process and the like will be described later. As shown inFIG.4, the control device100includes an inspection result holding part101, a correction value calculation part102, a recipe holding part106, and a unit controller107as functional configurations. In addition, the correction value calculation part102includes a regression coefficient calculator103and a parameter correction value calculator104. The control device100implements changing the control content in the coating unit U1and the heat treatment unit U2based on the inspection result obtained by the inspection unit U3. This point will be described with reference toFIG.4. In the following embodiments, as an example, the control of the processing module12that forms the resist film on the wafer W will be described. In the case of the processing module12, a process (first process) relating to the coating of the processing liquid in the coating unit U1(first processing unit) and a process (second process) relating to the heat treatment of the processing liquid in the heat treatment unit U2(second processing unit) are performed on the wafer W. The inspection result holding part101has a function of acquiring the inspection result obtained by the inspection unit U3, i.e., the inspection result relating to the resist film on the surface of the wafer W from the inspection unit U3, and holding the inspection result. Further, in the inspection suit holding part101, information that identifies in which unit (coating unit U1and heat treatment unit U2) the wafer W corresponding to the inspection result has been processed is acquired based on the process recipe held in the recipe holding part106described later. The inspection result holding part101acquires a data set relating to one substrate by correlating these pieces of information with the inspection results and holds the acquired data set. A series of information (data set) for each substrate held in the inspection result holding part101is used by the correction value calculation part102to calculate a correction value. The correction value calculation part102has a function of calculating a correction value based on the data set including the inspection results held in the inspection result holding part101. The calculation of the correction value by the correction value calculation part102is performed by the regression coefficient calculator103and the parameter correction value calculator104. The regression coefficient calculator103calculates an expected value of a group average film thickness (characteristic amount) obtained by regression calculation, an expected value of a film thickness deviation between the coating units U1, and an expected value of a film thickness deviation between the heat treatment units U2. Further, the parameter correction value calculator104calculates a correction value of the parameter for each unit based on the values calculated by the regression coefficient calculator103. Details of the calculation in each part will be described later. The correction value calculation part102individually calculates correction values for each of the plurality of coating units U1and the plurality of heat treatment units U2included in the processing module12as a target. The recipe holding part106has a function of holding the process recipe relating to the processing module12. The process recipe specifies the unit (coating unit U1and heat treatment unit U2) in which the process is to be performed for each wafer W, and designates various parameters used when the process is performed in each unit. The unit controller107has a function of controlling each unit so that each unit executes the process in a state in which the correction value calculated by the correction value calculation part102is applied to the process recipe held in the recipe holding part106. Next, the calculation of the correction value and the control performed using the correction value, which are executed by the control device100, will be described with reference toFIG.4. As described above, the processing module12includes the plurality of coating units U1and the plurality of heat treatment units U2. InFIG.4, the coating units U1are indicated as COT1, COT2, COT3and so forth. Furthermore, the heat treatment units U2are indicated as PAB1, PAB2, PAB3and so forth. In the processing module12, the wafer W is delivered in the order of the coating unit U1, the heat treatment unit U2, and the inspection unit U3, and a predetermined process is performed in each unit to form a resist film on the surface of the wafer W. The plurality of coating units U1(COT1, COT2. . . ) and the plurality of heat treatment units U2(PAB1, PAB2. . . ) through which the wafer W passes are determined by the process recipe held in the recipe holding part106of the control device100. In addition, what kind of process is to be performed in each unit is also determined by the process recipe. The plurality of coating units U1and the plurality of heat treatment units U2included in the processing module12may be handled as a group that incorporates the units capable of constituting a path of one wafer W. Due to the structure of the processing module12or the function of the apparatus, there is no possibility that the wafer W loaded into a specific coating unit U1(e.g., COT1) is loaded into all the heat treatment units U2. That is, the process recipe is created on the assumption that the wafer W loaded into the specific coating unit U1(e.g., COT1) is loaded into some specific heat treatment units U2. In other words, the combination of the coating unit U1and the heat treatment unit U2through which one wafer W may pass is not randomly selected from all the units but is selected from a specific group. Also, the path of the wafer W in the process recipe is set in this manner. As described above, the plurality of coating units U1and the plurality of heat treatment its U2included in the processing module12may be handled by being divided into a plurality of groups, each of which incorporates the units that perform a process on the same wafer W.FIG.4shows a state in which COT1to COT4and PAB1to PAB4constitute one group G1. In such a state, the same unit group such as COT1to COT4or PAB1to PAB4included in one group G1is referred to as a “factor.” Moreover, each unit of COT1and COT2is called a “level.” That is, a first factor (COT group) includes a plurality of first levels (coating units U1), and a second factor (PAB group) includes a plurality of second levels (heat treatment units U2). Further,FIG.4shows a state in which there are two groups G2and G3constituted by units different from the units included in the group G1. In the processing module12, a resist film is formed on one wafer W by the coating unit U1and the heat treatment unit U2included in any of the groups G1to G3, and the wafer W is inspected by the inspection unit U3. By the way, when the processing module12includes a plurality of coating units U1and a plurality of heat treatment units U2, even if each unit performs a substrate processing under the same process condition so that the resist film becomes uniform, variations may occur in the film formed depending on the characteristics of the unit. In the case of forming the resist film on the surface of the wafer W, for example, in the coating unit U1, the thickness of the film formed on the surface of the wafer W is changed depending on the rotation speed of the wafer W when coating the processing liquid. However, when a plurality of coating units U1is operated by designating the same parameter (rotational speed), there is a possibility that the coated film thickness may vary under the influence of the unit temperature and the like. In the heat treatment unit U2, the film thickness of the film formed on the surface of the wafer W is changed depending on the heating temperate of the wafer W during the heat treatment. However, when a plurality of heat treatment units U2is operated by designating the same parameter (heating temperature), there is a possibility that the temperature of the wafer W is changed slightly between the units. If the temperature of the wafer W varies between the units, there is a possibility that the film thickness of the resist film solidified and formed on the wafer W varies. As described above, even when the process recipe for forming a resist film having a predetermined film thickness is the same, if the characteristics of each unit have variations, there is a possibility that the variations in the thickness of the resist film are caused by the variations in the characteristics of each unit. That is, depending on which unit the wafer W is processed through, the film thickness of the resist film may differ between the wafers W. However, when the film thickness is not a desired value and a certain difference in the film thickness is generated under the influence of the characteristics of a certain unit in the process based on the process recipe, a correction value for correcting a difference (from the desired value) caused by the respective unit is calculated for the unit. Then, by controlling the unit through the use of the parameter that takes the correction value into account, it is presumably possible to reduce the change in the film thickness due to the characteristics of the unit. The unit controller107corrects the parameter of the unit specified by the process recipe held in the recipe holding part106based on the correction value, and then controls each unit using the corrected parameter. With such a configuration, it becomes possible to control the unit while reflecting the correction value. However, the plurality of wafers W does not pass through the same unit as described above, but is processed by any one of the coating units U1and any one of the heat treatment units U2included in one group (one of G1to G3). Of course, there are wafers W that pass through the same path. However, the units in which a process is performed are different for each wafer W. Therefore, when an inspection result is obtained which indicates that the film thickness of a certain wafer W is different from the film thickness assumed in the process recipe, it is considered that the coating unit U1or the heat treatment unit U2(at least one of them) which has processed the respective wafer W needs to be subjected to correction. However, there may be a case where it is difficult to concretely specify the unit and the correction amount that can bring the film thickness closer to a target value. It is considered possible to estimate the characteristics of each unit based on comparison with the film thickness of the wafer W processed in another unit. However, it is also necessary to consider that the film thickness of the wafer W processed in another unit includes the influence of the characteristics of the respective unit. In a module such as the processing module12or the like that executes a plurality of processes, there may be a case where it is possible to specify which of the plurality of processes has affected the characteristics of the finished product (e.g., the film thickness of the resist film). When a plurality of coating units U1and a plurality of heat treatment units U2are included in the same group such as the group G1of the processing module12, if there is a predetermined inspection result, it is possible to specify the unit that has affected the film thickness and the degree of influence on the film thickness. That is, the deviation for each unit (unit deviation) can be specified according to the predetermined inspection result. The term “unit deviation” used herein means a deviation from an expected value of a film thickness change amount after performing the process by each unit. The film thickness change amount in the coating unit U1is a change in the coating amount of the processing liquid, and the film thickness change amount in the heat treatment unit U2is a change in the film thickness before and after the heat treatment. The unit deviation ay also be called a level deviation. The unit deviation relating to the coating unit U1may be referred to as a first level deviation, and the unit deviation relating to the heat treatment unit U2may be referred to as a second level deviation. Specifically, for example, if there is an inspection result of the film thickness corresponding to a combination of all the units in the group through which the wafer W can pass, it is possible to specify the unit that has affected the film thickness and the degree of influence on the film thickness by using the least square method or the like. That is, in the case of COT1to COT4and PAB1to PAB4, if all 16 combinations of inspection results are available, it is possible to specify the unit deviation relating to each unit. Furthermore, as another example, even when there is not a combination of all the units, if the combination of the units through which the wafer W passes is not divided into a plurality of sets, it is possible to use a series of inspection results (predetermined inspection results) included in this one set. The term “set” is the combinations associated with each other and may also be referred to as a subgroup. However, it is impossible to evaluate the unit through which the wafer W has not passed (the unit for which an inspection result does not exist). However, even if the units are in the same group, there may be a case where a specific combination of the coating unit and the heat treatment unit is not executed in terms of the process flow of the wafer W in the apparatus. In such a case, even if the units are in the same group, the combination of the units through which the wafer W passes is divided into a plurality of sets (subgroups), which makes it difficult to specify the unit deviation. In this case, it is required to calculate the correction value for each unit after adding certain estimation. Further, when the units are controlled by giving some correction values to the rotation speed of the coating unit U1or the heating temperature of the heat treatment unit U2in order to keep the film thickness of the wafer W at a predetermined value, there may be a case where a difference in controllability exists between the coating unit U1and the heat treatment unit U2. For example, the control of changing the rotation speed in the coating unit U1can be relatively easily performed, but the control of changing the heating temperature in the heat treatment unit U2may be more difficult than the control of changing the rotation speed. Accordingly, in a case where calculating the correction value for each unit cannot be done accurately but requires adding some kind of estimation, it may be required to perform the estimation so that the correction amount for the heating temperature becomes small. When performing a two-step process (coating and heat treatment) using two different parameters in this way so that the film thickness of the wafer W becomes a predetermined value, there may be a case where the priority for correction is determined. Accordingly, the control device100sets a concept of a group target value (a film thickness that becomes a group target) when performing a correction relating to the coating unit U1and the heat treatment unit U2in the processing module12. Then, the control device100calculates a correction value for reducing the unit deviation in each unit while bringing the average value of the film thickness in each group close to the group target value. The group target value may be a film thickness that becomes a target value designated by the user, or may be an average of all units included in any of a plurality of groups included in the apparatus. Assuming that the group target value is an average value of the film thicknesses of the respective groups, the correction value may be calculated so that only the unit deviation is reduced, without performing the correction relating to the average value of the film thicknesses of the groups. Of the above corrections, the correction for reducing the unit deviation may be referred to as in-layer average correction. Further, when the group target value is different from a current average value of the film thicknesses, a target correction is performed so that the expected value of the average film thickness becomes the group target value. Subsequently, the correction values for each coating unit U1and each heat treatment unit U2in the processing module12are calculated based on these correction values. The regression coefficient calculator103and the parameter correction value calculator104calculate the correction value at each of these stages. The details of the calculation of the correction value at each stage will be described later. The control device100is composed of one or more control computers. For example, the control device100includes a circuit120shown inFIG.5. The circuit120includes one or more processors121, a memory122, a storage123, and an input/output port124. The storage123includes a non-transitory computer-readable storage medium such as a hard disk or the like. The storage medium stores a program for causing the control device100to execute a process procedure described later. The storage medium may be a removable medium such as a non-volatile semiconductor memory, a magnetic disk, or an optical disk. The memory122temporarily stores the program loaded from the storage medium of the storage123and the calculation result obtained by the processor121. The processor121constitutes each functional module described above by executing the above program in cooperation with the memory122. The input/output port124inputs and outputs an electric signal to and from a control target member according to a command from the processor121. The hardware configuration of the control device100is not necessarily limited to the one in which each functional module is constituted by the program. For example, each functional module of the control device100may be constituted by a dedicated logic circuit or an ASIC (Application Specific Integrated Circuit) in which the dedicated logic circuit is integrated. [Process Procedure] Next, a process procedure executed in the coating/developing apparatus2will be described as an example of a coating/developing process. In the process procedure, first, the control device100controls the transfer device A1so as to transfer a target wafer W in the carrier C to the shelf unit U10, and controls the transfer device A7so as to arrange the wafer W in the cell for the processing module11. Next, the control device100controls the transfer device A3so as to transfer the wafer W of the shelf unit U10to the coating unit U1and the heat treatment unit U2in the processing module11. Further, the control device100controls the coating unit U1and the heat treatment unit U2so as to form a lower layer film on the surface of the wafer W. After forming the lower layer film, the control device100may control the transfer device A3so as to transfer the wafer W to the inspection unit13, and may control the inspection unit U3so as to inspect the surface state of the wafer W (e.g., the film thickness of the lower layer film). Thereafter, the control device100controls the transfer device A3so as to return the wafer W on which the lower layer film has been formed to the shelf unit U10, and controls the transfer device A7so as to arrange the wafer W in the cell for the processing module12. Next, the control device100controls the transfer device A3so as to transfer the wafer W of the shelf unit U10to the coating unit U1and the heat treatment unit U2in the processing module12. Further, the control device100controls the coating unit U1and the heat treatment unit U2so as to form a resist film on the lower layer film of the wafer W. For example, the control device100controls the coating unit U1so as to form the resist film by coating a processing liquid for forming the resist film on the lower layer film of the wafer W. Subsequently, the control device100controls the heat treatment unit U2so as to subject the resist film to a heat treatment. After forming the resist film, the control device100controls the transfer device A3so as to transfer the water W to the inspection unit U3, and controls the inspection unit U3so as to inspect the surface state of the wafer W (e.g., the film thickness of the resist film). After acquiring the inspection result from the inspection unit U3, the control device100calculates an expected value of the average film thickness in the group and the unit deviation relating to the coating unit U1and the heat treatment unit U2from the inspection result. Specifically, the control device100calculates the unit deviations (first and second unit deviations) relating to the rotation speed (first parameter) in the coating unit U1(first processing unit) and the heating temperature (second parameter) in the heat treatment unit U2(second processing unit). Then, the control device100specifies correction values relating to the film thickness from the calculated unit deviations, and corrects and controls the rotation speed or the heating temperature in each unit. Thereafter, the control device100controls the transfer device A3so as to return the wafer W to the shelf unit U10, and controls the transfer device A7so as to arrange the wafer W in the cell for the processing module13. Next, the control device100controls the transfer device A3so as to transfer the wafer W of the shelf unit U10to each unit in the processing module13, and controls the coating unit U1and the heat treatment unit U2so as to form an upper layer film on the resist film of the wafer W. After forming the upper layer film, the control device100may control the transfer device A3so as to transfer the water W to the inspection unit U3, and may control the inspection unit U3to inspect the surface state of the wafer W (e.g., the film thickness of the upper layer film). Thereafter, the control device100controls the transfer device A3so as to transfer the wafer W to the shelf unit U11. Next, the control device100controls the transfer device A8so as to send the wafer W of the shelf unit U11to the exposure apparatus3. Thereafter, the control device100controls the transfer device A8so as to receive the exposed wafer W from the exposure apparatus3and arrange the wafer W in the cell of the shelf unit U11for the processing module14. Subsequently, the control device100controls the transfer device A3so as to transfer the wafer W of the shelf unit U11to each unit in the processing module14, and controls the coating unit U1and the heat treatment unit U2so as to perform a developing process on the resist film of the wafer W. Thereafter, the control device100controls the transfer device A3so as to return the wafer W to the shelf unit U10, and controls the transfer devices A7and A1so as to return the wafer W into the carrier C. Thus, the process is completed. [Substrate Processing Control Method] Next, a substrate processing control method for the processing module12performed by the control device100will be described with reference toFIGS.6to12. The substrate processing control method includes a procedure of calculating correction values relating to the rotation speed (first parameter) of the coating unit U1(first processing unit) and the heating temperature (second parameter) of the heat treatment unit U2(second processing unit), and a procedure of controlling each unit. As shown inFIG.6, first, the control device100executes step S01(acquisition step). In step S01, the inspection result (film thickness inspection result) relating to the wafer W is acquired from the inspection unit U3and held in the inspection result holding part101. At this time, the inspection result holding part101acquires, from the recipe holding part106, information that specifies the units (the coating unit U1and the heat treatment unit U2) that have processed the wafer W for which the inspection result has been acquired. Thus, a series of data sets is acquired by the control device100. The information specifying the units that have processed the wafer W (the coating unit U1and the heat treatment unit U2) may be acquired from the inspection unit U3. Next, the control device100executes step S02(calculation step). In step S02, the regression coefficient calculator103of the correction value calculation part102creates a model relating to the film thickness change based on the inspection result held in the inspection result holding part101. Specifically, the regression coefficient calculator103creates a model relating to the film thickness change that corresponds to a change in parameter setting in each unit when controlling the film thickness by each process in the coating unit U1and the heat treatment unit U2in a specific group. Then, a function (objective function) for estimating an expected value of the average film thickness, an expected value of the unit deviation of the coating unit U1, and an expected value of the unit deviation of the heat treatment unit U2in the specific group is set based on the model. Thereafter, the optimum solution of the expected value of the average film thickness, the unit deviation of the coating unit U1, and the unit deviation of the heat treatment unit U2is obtained so that the unit deviations of the coating unit U1and the heat treatment unit U2come close to zero while the expected value of the average film thickness comes close to the group target value described above. The optimum solution of the expected value of the average film thickness, the unit deviation of the coating unit U1, and the unit deviation of the heat treatment unit U2corresponds to the regression coefficient. The optimum solution of the expected value of the average film thickness, the unit deviation of the coating unit U1, and the unit deviation of the heat treatment unit U2can be obtained by solving an equality-constrained least squares problem. The equality-constrained least squares problem is based on a model that assumes the control of the film thickness in a group including a plurality of coating units U1and a plurality of heat treatment units U2. However, depending on a condition, the solution of the equality-constrained least squares problem may not be uniquely determined due to lack of rank. Therefore, by adding a constraint condition so as to minimize the norm of the unit deviation of the coating unit U1and the unit deviation of the heat treatment unit U2except for the expected value of the average film thickness, the equality-constrained least squares problem is formulated as a kind of multi-objective optimization problem. Then, the regression coefficient can be calculated by solving the above multi-objective optimization problem. It can be said that the above constraint condition is set such that the priority relating to minimizing the norm of the unit deviation of the coating unit U1and the unit deviation of the heat treatment unit U2(norm minimization priority) is higher than the norm minimization priority of the average film thickness. When the optimum solutions of the expected value of the average film thickness, the unit deviation of the coating unit U1, and the unit deviation of the heat treatment unit U2are obtained by solving the above multi-objective optimization problem, the control device100executes step S03(correction step). In step S03, the correction value of the parameter corresponding to the optimum solution is obtained based on these optimum solutions. The parameter correction value calculator104calculates a correction value of the parameter. By executing step S03, the correction value of the film thickness in each unit is fixed. Therefore, the correction value of the parameter corresponding to the correction value of the film thickness is calculated. The calculation of the correction value of the parameter in each unit can be performed based on the relationship between the film thickness held by the control device100in advance and the parameter of each unit. That is, the change in the film thickness when the parameter (norm) of each unit is changed is acquired in advance, and the size of the film thickness to be changed by correction is obtained from the unit deviation, whereby a correction value of the parameter can be obtained from the relationship acquired in advance. Next, the control device100executes step S04(correction step). In step S04, the unit controller107controls each unit (the coating unit U1or the heat treatment unit U2) based on the process recipe held in the recipe holding part106and the correction value calculated by the correction value calculation part102. A corrected parameter is calculated by applying the correction value calculated by the correction value calculation part102to the parameter in each unit included in the process recipe. The unit controller107controls each unit based on the corrected parameter. Thus, a process is performed in each unit while reflecting the correction value. The above series of procedures will be described as a specific example with reference toFIG.7A. InFIG.7A, three groups G10to G30are shown. The group G10is composed of COT11, COT12, and PAB11to PAB13. The group G20is composed of COT21, COT22, and PAB21to PAB23. Further, the group G30is composed of COT31, COT32, and PAB31to PAB33.FIG.7Ashows the unit deviation of the film thickness for each unit included in each group. A value R1indicated by a broken line for each unit in the group G10indicates an average value of the film thickness of the wafer W processed in the group G10. As shown inFIG.7A, the average value of the film thickness of the wafer W in the group G10is 90.05 nm. On the other hand, the film thickness of COT11is 89.73 nm. This indicates that as the water W is processed in the COT11, the COT11affects the change in the film thickness such that the film thickness of the resist film subjected to the heat treatment is decreased by 0.32 nm from the target value of 90.05 μm (−0.32 nm). The film thickness of PAB11is 90.13 nm. This indicates that as the wafer W is processed in the PAB11, the PAB11affects the change in the film thickness such that the film thickness of the resist film subjected to the heat treatment is increased by 0.08 nm from the target value of 90.05 nm (+0.08 nm). As described above, it can be noted that before the correction, the process in each unit affects the change in the film thickness of the resist film subjected to the heat treatment. In the case of COT11, −0.32 nm is the unit deviation relating to the film thickness. In the case of PAB11, +0.08 nm is the unit deviation relating to the film thickness. Therefore, the wafer W that has passed through the COT11and the PAB11undergoes a film thickness change corresponding to the unit deviations of the two units, whereby the film thickness is changed by −0.32 nm+0.08 nm=−0.24 mm with respect to the group target value (the average value of the film thicknesses of the wafers W). In this way, the correction value calculation part102sets the group target value for each group based on the result held in the inspection result holding part101. Then, the correction value calculation part102calculates unit deviations (first unit deviation and second unit deviation) relating to the film thickness change in the process performed in each unit, based on the difference from the group target value. The group target value may be set to a value different from the average value of the film thicknesses of the wafers W. If the unit deviation relating to the film thickness for each unit group can be calculated, the correction value may be set based on the unit deviation. That is, since the unit deviation with respect to the change in film thickness is −0.32 nm in the case of COT11, it is only necessary to calculate the correction value of the parameter for implementing the process so that the film thickness becomes +0.32 nm. Furthermore, since the unit deviation with respect to the change in film thickness is +0.08 nm in the case of PAB11, it is only necessary to calculate the correction value of the parameter for implementing the process so that the film thickness becomes −0.08 nm. As for the calculation of the regression coefficient described in step S02, the detailed procedure may be changed in accordance with the inspection result held in the inspection result holding part101and in consideration of the safety degree or the correction ease with respect to the correction of the parameter for correction. That is, the priority for minimizing the norm (norm minimization priority) may be set, and the detailed procedure for calculating the correction value may be changed in consideration of this priority.FIG.8shows a procedure for calculating the correction value when the norm minimization priority is taken into consideration. First, the regression coefficient calculator103executes step S11. In step S11, it is determined whether the unit deviation can be calculated by the least square method (equality-constrained least square method) using the result held in the inspection result holding part10. Then, if the result of this determination is YES, the regression coefficient calculator103executes step S12. In step S12, the unit deviations (first unit deviation and second unit deviation) of each unit are calculated using the equality-constrained least square method. As described above, if there is an inspection result of the film thickness corresponding to the combination of all the units in the same group through which the wafer W can pass, the unit deviations relating to all the units can be specified by using the equality-constrained least square method. For example,FIG.9Ashows an example of a group including four coating units U1i.e., COT1to COT4, and four heat treatment units U2, i.e., PAB1to PAB4. In the group shown inFIG.9A, if the inspection results of the film thickness of the resist film in all the combinations can be obtained, as shown inFIG.9B, the unit deviation relating to each unit can be calculated using the equality-constrained least square method. That is, by means of the equality-constrained least square method, it is possible to calculate the overall average (the average value of the film thicknesses in the group) and the unit deviation (a value corresponding to the difference) of the film thickness of the resist film for each unit with respect to the overall average. Although the case where the inspection result of the film thickness of the resist film in all the combinations is obtained has been described above, whether or not the unit deviation can be calculated using the equality-constrained least square method may actually depend on whether the obtained result is divided into subgroups. Therefore, in step S11, it is determined whether the obtained result is divided into subgroups. Then, if the determination result in step S11is YES, the unit deviation and the correction value are calculated in step S12by using the equality-constrained least square method. Meanwhile, when the determination result in step S11is NO, i.e., when the inspection results are not sufficiently uniform so that the unit deviation cannot be calculated by the equality-constrained least square method, the regression coefficient calculator103executes step S13. In step S13, it is determined whether or not there is a norm minimization priority when calculating the unit deviation and the correction value for each factor (unit group) (whether or not the norm minimization priority is different for each factor). Then, when the result of this determination is YES, i.e., when there is a norm minimization priority when calculating the unit deviation and the correction value for each factor (whether or not the norm minimization priority is different for each factor), the regression coefficient calculator103executes step S14. In step S14, the unit deviation is calculated while minimizing the norm for the group target value in the order based on the norm minimization priority for each factor. On the other hand, when the result of this determination is NO, i.e., when there is no norm minimization priority when calculating the unit deviation and the correction value for each factor (if the norm minimization priority for each factor is the same), the regression coefficient calculator103executes step S15. In step S15, the unit deviation for each unit is calculated so that the norm of all factors other than the intercept is minimized. With reference toFIG.8, the procedure for changing the calculation method depending on whether the unit deviation can be calculated by the equality-constrained least square method and whether there is the norm minimization priority for each factor has been described above. However, the calculation (steps S12, S14and S15) under each condition shown inFIG.8may be integrated into step S14. That is, the unit deviation may be calculated by executing only step S14without performing steps S11and S13. For example, if the solution can be obtained by using the equality-constrained least square method as in step S12, it means that the solution has no degree of freedom. In this case, the same solution is calculated regardless of whether or not there is a norm minimization priority. Therefore, the solution can also be obtained by appropriately setting the norm minimization priority and executing the algorithm corresponding to step S14. Furthermore, if it is considered that the norm minimization priority in step S14is the same for each factor in step S15, the solution is obtained by the same algorithm as in step S14. Therefore, even if only step S14is executed, it is possible to obtain the same solution as that available when the calculation is performed based on the flow ofFIG.8. Steps S13to S15will be described with reference toFIGS.10A and10BandFIGS.11and12.FIG.10Ashows an inspection result in a group including five coating units U1, i.e., COT1to COT5, and five heat treatment units U2, i.e., PAB1to PAB5. In the example shown inFIG.10A, the inspection result of the film thickness of the resist film is not obtained for all the combinations. That is,FIG.10Ashows a state in which Set1as an inspection result relating to the combination of COT1, COT2, COT3, PAB1, and PAB2and Set2as an inspection result relating to the combination of COT4, COT5, PAB3, PAB4, and PAB5is obtained. In this state, as shown inFIG.10B, it is possible to calculate an overall average (corresponding to the group target value), differences between the overall average and average values of Set1and Set2, and a unit deviation of each unit from the group target value based on the least square method in Set1and Set2, respectively. However, the unit deviation of each unit is the Set unit for which the inspection result is obtained. Therefore, the correction value based on this unit deviation is a correction value for making correction toward the average value in the Set unit, and is not a correction value corresponding to correction made on a group-by-group basis. In addition, if the unit deviation of each unit with respect to the overall average in the group is calculated by the least square method with the obtained inspection result shown inFIG.10A, the equation is insufficient for the unknown number. Therefore, there are infinite solutions. That is, the unit deviation of the process in each unit cannot be calculated. In the case where there is an infinite number of solutions in the equality-constrained least square method, it is general to select the solution that minimizes the norm of explanatory variables. In this example, the overall average (intercept) and each unit deviation correspond to the explanatory variables.FIG.11shows a result of calculating the unit deviation of each unit from the inspection result shown inFIG.10Aso that the norm of each unit deviation excluding the expected value (intercept) of the average film thickness in the group is minimized. In this case, as shown inFIG.11, the norm of COT/PAB is 1.572, and the unit deviations for COT1to COT5and PAB1to PAB5are 1.278 and 0.915, respectively. It can be said that the process (calculation) of specifying the solution under the norm minimization condition corresponds to step S15shown inFIG.8. Further, a known method may be used as a specific procedure of the process of specifying the solution under the norm minimization condition. In the result shown inFIG.11, the norm other than the intercept in the entirety of the plurality of units is minimized. However, the priority of correction regarding the parameter according to the unit is not taken into account. As described above, when there is a circumstance in which it is desired to reduce the correction value for the heating temperature of the heat treatment unit U2, a norm minimization process is performed so that the correction value of the heating temperature for the part relating to the parameter for which the correction value is desired to be reduced, i.e., the heat treatment unit U2, is reduced. In the case of the present embodiment, a process of calculating the unit deviation is performed so that the norm of the heating temperature of the heat treatment unit U2is minimized. As described above, when the norm minimization priorities relating to the unit deviation calculation (correction value calculation) are different for the parameters of individual units, the unit deviation of each unit for minimizing the norm is calculated from the parameter having a high norm minimization priority. In the case of the present embodiment, the parameters of each unit are two types of parameters, i.e., the rotation speed of the coating unit U1and the heating temperature of the heat treatment unit U2. The parameter having a high norm minimization priority corresponds to a parameter whose correction value is not desired to be increased more than necessary. Examples of the parameter (factor) whose correction value is not desired to be increased more than necessary include a parameter that is not easily corrected, and a parameter that may cause a certain risk when subjected to correction. On the other hand, examples of the parameter whose correction value may be large include a parameter that can be easily corrected, and a parameter that has a small risk when subjected to correction. When a parameter whose correction value is desired to be kept as small as possible is present as described above, a factor (unit group) to which the parameter belongs is treated as having a high norm minimization priority. Then, when minimizing the norm, the minimization calculation is performed from a factor having a higher norm minimization priority. In the case of the configuration of the present embodiment, the PAB having the heating temperature as a parameter is a factor having a higher norm minimization priority than the COT having the rotation speed as a parameter. Therefore, the unit deviation of the process for each unit for minimizing the norm is calculated from the factor having a higher norm minimization priority, i.e., the PAB. The unit deviation calculation (the calculation corresponding to step S14inFIG.8) in consideration of the norm minimization priority can be performed by, for example, the following method. That is, the equality constraint and the objective function in which the expected value of the average film thickness in a certain group and the unit deviation of the film thickness in each unit are used as explanatory variables (regression coefficient) be described. Then, an additional objective function considering the norm minimization priority is added, and the regression coefficient is calculated by solving the multi-objective optimization problem. Thus, the unit deviation can be calculated so as to minimize the norm in consideration of the norm minimization priority for each unit. A known method may be used to calculate the regression coefficient itself. FIG.12shows the result of calculating the unit deviation of each unit by the above-described procedure. In the result shown inFIG.12, as compared with the result shown inFIG.11, the square error remains the same. However, the unit deviations of COT1to COT5are large and the unit deviations of PAB1to PAB5are small. Specifically, in the result shown inFIG.12, the norm of the coating unit U1(COT1to COT5) is 1.681, and the norm of the heat treatment unit U2(PAB1to PAB5) is 0.663. In the case of a configuration in which the unit deviation of the process for each unit is calculated so that the norm is minimized sequentially from the factor with the highest norm minimization priority, the norm for the entire unit is not the minimum. For example, in the calculation result shown inFIG.11, the COT/PAB norm is 1.572. In the calculation result shown inFIG.12, the COT/PAB norm is 1.807. However, for the process of a unit relating to a factor having a high norm minimization priority, the unit deviation can be calculated to be small. In other words, the norm can be reduced with respect to the unit deviation of the process relating to the parameter having a higher norm minimization priority. This is because the calculation is performed so that the unit deviation relating to the factor having a higher noun minimization priority becomes smaller. Whether or not the norm minimization priority is set can be determined by the correction value calculation part102of the control device100. Then, when step S13is executed, the determination can be performed based on the information held by the apparatus itself. In the present embodiment, a case where the unit deviations (first unit deviation and second unit deviation) are calculated to perform calculation for the process based on two parameters in two processing units will be described. The two processing units are the coating unit U1and the heat treatment unit U2, and the two parameters are the rotation speed and the heating temperature. However, the above procedure can be performed by the same procedure even when the number of processing units is three or more and the number of types of parameters is increased to three or more. That is, when the norm minimization priorities of three stages are set to the three types of processing units (i.e., three types of processes), the process of calculating the unit deviation for minimizing the norm is repeated sequentially from the processing unit having the highest norm minimization priority as described above. Thus, the three types of unit deviations in the three types of units that perform the three processes can be calculated in a state in which the priority is taken into consideration. Furthermore, even when the number of types of processing units and parameters is four or more, the unit deviation can be calculated by the same procedure in consideration of the priority. The norm minimization priority may be set only in some processing units (some processes). The substrate processing control method described above may be configured to be performed at a predetermined timing when performing the substrate processing using the substrate processing system1. For example, the substrate processing may be performed at a timing designated by the user. In addition, when the processing of the substrates of an arbitrary lot is completed, the film thickness of the predetermined number of substrates closest to the lot may be referred to, and the process may be performed when the simple average of the film thicknesses of the substrates processed in each unit deviates from a predetermined range. In this case, a correction amount in each unit may be calculated from the aforementioned simple average. Furthermore, the start of the above process may be determined based on the result of comparison between the 95% confidence interval and the reference value. Specifically, when the process is completed for the substrates of an arbitrary lot, the 95% confidence interval of the estimated value in the case of estimating the unit deviation of each unit is calculated from the measurement result of the film thicknesses of the predetermined number of substrates closest to the lot. Then, when the 95% confidence interval does not include a value serving as a reference of the estimated value, it may be determined that the above process is performed. For example, when the group target value is the same as the current expected value of the average film thickness, the case where the 95% confidence interval of the unit deviation in the coating unit U1or the heat treatment unit U2does not include the reference value 0 may be used as a trigger for starting the substrate processing control method. In addition, when the group target value is set separately from the expected value of the average film thickness, it may be assumed that, for example, only the first unit is involved in the correction of the average film thickness. Then, based on this assumption, the case where the 95% confidence interval of the sum of the expected value of the average film thickness and the deviation of the first unit does not include the group target value as the reference value may be used as a trigger. In this case, the case where the 95% confidence interval of the deviation of the second unit does not include the reference value 0 may be used as a trigger. The above-described method is an example, and the present disclosure is not limited thereto. [Operation] According to the substrate processing control method and the substrate processing apparatus according to the above-described embodiments, the data set including information specifying the first level (coating unit U1) at which the first process has been performed, information specifying the second level (heat treatment unit U2) at which the second process has been performed, and information about a characteristic amount (e.g., a film thickness) relating to characteristics of the substrate is acquired by the plurality of processed substrates. Furthermore, in the calculation step, the information including the expected value of the characteristic amount, the level deviation of the first level with respect to the expected value, and the level deviation of the second level with respect to the expected value is calculated. Moreover, the first parameter in the first unit or the second parameter in the second unit is corrected based on the calculated information. With such a configuration, the level deviation can be calculated for each of the plurality of first processing levels and the plurality of second processing levels, and the respective parameters can be corrected based on the level deviation. Accordingly, even if the substrates have been processed at a plurality of levels such as plural types of processing units, it is possible to appropriately correct the target value for each unit through the use of the data set including the characteristic amount of the substrate. Conventionally, a method of correcting a characteristic amount relating to the characteristics of a processed substrate has been studied when the characteristic amount is different from a target value. However, there has not been studied a method of appropriately determining a desirable correction amount of a parameter relating to a processing unit that has performed a certain process and then correcting the parameter, based on the characteristic amount of the substrate repeatedly subjected to plural kinds of processing. In particular, when there is a plurality of processing units for performing a plural kinds of processing, there has not been studied a method of considering the degree of change in characteristic amount of a substrate changed by a certain processing unit and then calculating a correction value for correcting the characteristic amount. On the other hand, according to the substrate processing control method and the substrate processing apparatus described above, the level deviation is calculated for each of the first level and the second level, and the parameter of each unit is corrected based on the calculation result. Therefore, even if the substrate has been processed at a plurality of levels such as plural types of processing units, it is possible to appropriately correct the target value for each unit through the use of the data set including the characteristic amount of the substrate. In addition, in the above-described embodiments, when calculating the first level deviation at the first level and the second level deviation at the second level, the level deviations are calculated so that the norm other than the expected value of the characteristic amount is minimized. With the above configuration, the first level deviation (first unit deviation) and the second level deviation (second unit deviation) can be calculated even when only a data set is acquired in a range in which the unit deviation for each unit cannot be calculated by the conventional method such as the least square method. Therefore, according to the above configuration, it is possible to appropriately correct the target value for each unit. In particular, even when the data set is insufficient, the unit deviation for each unit can be appropriately calculated from the viewpoint of minimizing the norm. Therefore, it becomes possible to perform more appropriate correction. Further, in the above-described embodiments, when the norm minimization priority corresponding to the order of prioritizing reduction of correction values is predetermined, the unit deviation is calculated sequentially from the factor having a higher norm minimization priority so that the norm other than the expected value of the characteristic amount becomes smallest. With such a configuration, it is possible to prevent the factor having a higher norm minimization priority from being corrected by including a unit deviation derived from another factor. Therefore, it becomes possible to reduce the correction value for the factor having a higher norm minimization priority. In the above-described embodiments, the heating temperature of the heat treatment unit U2corresponding to the second parameter is a parameter belonging to the factor having a higher norm minimization priority. Therefore, the correction value of the heating temperature can be reduced by adopting the configuration in which the correction value is calculated by minimizing the norm of the unit deviation from the heat treatment unit U2. Furthermore, as in the above-described embodiments, it is possible to divide the plurality of first processing units and the plurality of second processing units into groups, each of which includes processing units that may possibly perform processing on one substrate. In such a case, a first unit deviation and a second unit deviation are calculated by setting a group target value for each group including the processing units that may possibly perform processing on one substrate. Thus, the unit deviation can be calculated more accurately as compared with a configuration in which the unit deviation is calculated in consideration of the combination of the processing units that may not possibly perform processing on one substrate. When the unit deviation is calculated without considering the group, for example, the unit deviation may possibly be calculated in consideration of the substrate processing using the first processing unit and the second processing unit included in different groups. In such a case, there is a possibility that the calculation accuracy of the unit deviation decreases. On the other hand, by adopting the configuration in which the unit deviation is calculated for each group as described above, it is possible to accurately calculate the unit deviation. Other Embodiments Although various exemplary embodiments have been described above, various omissions, substitutions and changes may be made without being limited to the exemplary embodiments described above. In addition, elements in different embodiments may be combined to form other embodiments. For example, in the above-described embodiments, there has been described a case where the parameter of each of the plurality of coating units U1and the plurality of heat treatment unit U2is corrected in forming a resist film in the processing module12. However, the substrate processing control method described above may also be applied to a process different from forming the resist film on the substrate. For example, the lower layer film and the upper layer film are formed in the coating/developing apparatus2described above. The control device100may also control these processes while correcting the parameter. Furthermore, the parameter correction by the control device100may be applied to a substrate processing not described in the above-described embodiment. As can be noted from the foregoing, the target of the calculation of the unit deviation relating to the process and the correction of the parameter based on the unit deviation described in the above embodiment is not particularly limited. Further, the characteristic amount is not limited to the film thickness of the film formed on the substrate. For example, a line width of a resist pattern may be used as the characteristic amount. Moreover, the parameter relating to the first process and the parameter relating to the second process may also be appropriately changed according to the characteristic amount. For example, in the above-described embodiments, the rotation speed of the coating unit U1for coating the processing liquid is used as a parameter. However, the rotation speed may be selected as a parameter for other processing units that perform processing while rotating the substrate. Furthermore, when performing some kind of processes using the processing liquid, the characteristics of the processing liquid may be selected as a parameter. In addition, one of the processing conditions in the processing unit may be selected as a parameter. As described above, the characteristic amount relating to the characteristics of the substrate may be appropriately selected, and the first process and the second process may be appropriately selected according to the characteristic amount. In addition, the first parameter in the first process and the second parameter in the second process may also be appropriately changed based on the characteristic amount and the like. Furthermore, in the above-described embodiments, there has been described a configuration in which as shown inFIG.6, the regression coefficient is calculated and then the correction value of the parameter for each unit is calculated. However, this procedure may be changed. In addition, it may be possible to adopt a configuration in which when the control device100calculates the correction value, all steps shown inFIG.8are not performed. For example, when it is possible to acquire only the data set for Which the unit deviation cannot be calculated by the least square method and when it is determined that there is priority for each factor, step S11and step S13may be omitted. As described above, when the number or contents of data sets acquired by the control device100, the characteristics of the parameter of the processing unit for which the unit deviation and the correction value are calculated, and the like are known in advance, the processing may be appropriately omitted based on the contents grasped by the control device100. In the above-described embodiments, there has been described a case where the expected value of the average film thickness, the first unit deviation, and the second unit deviation are handled separately when calculating the correction value for reducing the unit deviation while taking the norm minimization priority into consideration. However, it may be possible to adopt a configuration in which some of these three elements are handled collectively. Specifically, it is conceivable to integrally handle the expected value of the average film thickness and the first unit deviation (the unit deviation of the coating unit U1) described in the above embodiments. In this case, a combination of the first unit deviation and the expected value (intercept) of the average film thickness may be handled as the expected value of the film thickness of the first unit, the objective function may be described by the expected value of the film thickness relating to the first unit and the second unit deviation, and an optimum solution of these regression coefficients may be calculated. The expected value of the film thickness relating to the first unit is not zero. However, the same effect as the norm minimization of the first unit deviation can be obtained by replacing the norm minimization with variance minimization. According to the present disclosure in some embodiments, it is possible to provide a technique capable of properly controlling various parameters according to a substrate processing state. While certain embodiments have been described, these embodiments have been presented by way of example only, and are not intended to limit the scope of the disclosures. Indeed, the embodiments described herein may be embodied in a variety of other forms. Furthermore, various omissions, substitutions and changes in the form of the embodiments described herein may be made without departing from the spirit of the disclosures. The accompanying claims and their equivalents are intended to cover such forms or modifications as would fall within the scope and spirit of the disclosures. | 80,135 |
11862497 | DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Reference throughout this specification to “one embodiment” or “an embodiment” means that a particular feature, structure, material, or characteristic described in connection with the embodiment is included in at least one embodiment of the application, but do not denote that they are present in every embodiment. Thus, the appearances of the phrases “in one embodiment” or “in an embodiment” in various places throughout this specification are not necessarily referring to the same embodiment of the application. Furthermore, the particular features, structures, materials, or characteristics may be combined in any suitable manner in one or more embodiments. Techniques herein provide methods for uniquely identifying semiconductor chips at the die level across multiple wafers and lots using conventional available semiconductor processing techniques. This includes using direct-write processing that provides die-by-die unique marking. Patterning of semiconductors typically involves using an optical lithography system. Such systems use, for example, deep ultraviolet (DUV) electromagnetic radiation to create high resolution relief image patterns in a photosensitive resist material. Such relief image patterns are then used as a template for selective deposition, etch processes, and other microfabrication processing. Images realized in photoresist are projections of a master pattern on a photomask. The photomask is generally constructed of chromium and quartz, which integrate to create opaque and transparent regions that dictate the propagation of a source radiation at the mask interface. This photomask effectively defines a pattern of actinic radiation that reaches a film or layer of a photosensitive material. This creates a latent pattern within the photosensitive material by changing a solubility of the material where the pattern of light interacted with the material. The latent pattern is developed with one or more developing chemicals, which results in a relief pattern on the substrate. Although mask-based photolithography is effective, one limitation of this process is that the construction of a photomask is not trivial. Building a photomask is time-consuming and relatively expensive. Moreover, a given photomask pattern is fixed or identical for all wafers processed with that photomask.FIG.1Aillustrates a fixed pattern produced by mask-based projection lithography that is applied to a set of wafers, for example, wafer1and wafer2. Alternative mask-less patterning techniques exist that deploy direct write technology. Direct-write systems include electron beam lithography, plasmonic lithography, grating light valve lithography and digital light projection patterning systems, among others. Direct-write lithography in operation typically involves feeding a design file to a write engine. The write engine guides an exposure process to define patterns in a sensitive material based upon a coordinate grid to drive the write head(s). One advantage of direct-write systems is that exposure patterns are not restricted by physical media (such as a photomask) and are instead digitally generated. Thus, each exposure can use a different design file or modification of the design file so that each individual exposure can differ from previous and subsequent exposures. Differences can be minor or substantial.FIG.1Billustrates how direct-write lithography can generate a different exposure pattern (for example, “A” and “B”) for different wafers (for example, wafer1and wafer2). As used herein, each wafer and/or each die can contain unique information by altering information in the digital domain prior to pattern exposure. In one non-limiting embodiment, direct write lithography is used to place an electrical identifier at a specific location on a per-wafer or per-device basis in photoresist. Placement of such a unique mark can be effected as a latent pattern in photosensitive material that integrates with conventional coating/develop processes. Such a unique direct-write mark can be added without concern of physical mask (photomask) overhead because wafer pattern data is stored in the digital domain. Conventional wet or dry etch processes can then be used to transfer the serialization permanently into an underlying layer. The underlying layer may be a conductive or dielectric layer in some embodiments. In other embodiments, the underlying layer may be an oxide layer or nitride layer. A particular type of electrical identification employed in the marking method described herein is selectable by each user or system controller, and/or type of identification/authentication desired. Such unique markings can be simple or expansive with information contained. For example, a given unique identifier can be a simple serial number for each die. Alternatively, a unique identifier can include date of manufacture, chip specifications, generation of technology, origination fab, lot, et cetera. Techniques described herein include a standalone approach that provides marking of simple, unique circuit performance parameters that are tunable on a die-level basis. Tunable characteristics include resistivity and capacitance, among others. For example, a simple doped polysilicon resistor can have a tuned resistance based upon its length as depicted inFIG.2AandFIG.2B. A length of wire on a die ofFIG.2Ahas a resistance of 15 ohms, while a length of wire on a die ofFIG.2Bhas a resistance of 30 ohms. Alternatively, various metals can be used so that no additional processing steps (other than direct write exposure) are needed. For example, a direct write pattern is filled as part of a dual damascene metallization process. During packaging, an electrically testable configuration can be made such that the resistance is easily read to identify that the optical serialization given to a specific die matches its electrical characteristic. In another embodiment, techniques herein are applied to security applications that require encryption parity for code/decode. In other words, simple, electrically tunable circuit components can be used for unique authentication. In some embodiments, unique marking can include apportioning or designing a particular area for ID marking.FIG.3illustrates a typical 2×2 die recital used to scan four die for recital fielded. It is noted that the bulk of the area is used for a particular circuit design. This can include placement of transistors, field-effect transistors, logic, memory, wiring, et cetera. A smaller area within the die boundaries is then designated or apportioned for unique electrical wiring. In this example, such areas are a small box in the upper left corner of each die (ID001, ID002, ID003, ID004). The area designated for unique identification marking may be less than one square millimeter. Exposure of unique wiring structures can occur before or after mask-based exposure. For example, a wafer is prepared for lithographic exposure in a coater-developer (track) tool by coating a wafer with a photoresist film. The wafer is then ready for transport to a scanner or stepper. Prior to transfer to a scanner, the wafer can move to another tool or another module within the coater-developer for exposure of a unique mark by way of direct-write exposure. Alternatively, a mask-based exposure is executed first, followed by a direct-write exposure (such as using a laser galvanometer projection device). FIG.4illustrates how a unique wiring structure is formed by direct-writing lithographic exposure in one region of a given die, while die circuitry can be formed in the remaining area of the die. It is noted that remaining circuity can also be formed by direct-write lithography, but for relatively smaller resolutions masked-based photolithography is usually needed for resolution and throughput. Unique wiring structures herein do not need to be formed at dimensions of advanced semiconductor nodes, and can have relaxed resolution that is within the capability of various laser galvo, and other direct-write projection technology. Direct-writing and mask-based photolithography may not be needed, as long as a unique wiring structure is formed in the die with a unique electrical signature. Unique wiring structures herein can be simple or complex, and can incorporate graphical design elements. In one embodiment, a set or matrix of conductive paths can be used to create any combination of values, which provides a unique electrical identifier. By way of a non-limiting example,FIG.5shows an array or matrix of conductive paths. For this example, six conductive paths are shown. Each conductive path is labeled as Bit1, Bit2, Bit3, Bit4, Bit5, and Bit6. More or fewer conductive paths can be used depending on an amount of different unique identifier combinations desired. These conductive paths can also be considered as digits or values or value-character positions. Each conductive path can have a corresponding value. This value can be a resistance/capacitance value. A number of different resistance values possible in a given conductive path can be configured as desired. For example, values can range from 0-10, 0-500, or a thousand or more. An initial value can be zero as inFIG.6. It is noted that there is no conductor formed between Bit1and ground (or other conductive target or part of a corresponding circuit). Thus, there is infinite resistance and this state can be a first value for a first code (e.g. code00). Likewise, there is no metal completing the other conductive paths (for example, Bit2to ground). Each conductive path contact (Bit1, Bit2, . . . ) can be connected to a mux. With no poly or metal, all conductive paths are open. Referring now toFIG.7, there is a conductive structure connecting the Bit1contact to the ground, thus an electrical signal can be transmitted through the Bit1conductive path from the Bit1contact to the ground/target. For example, a relatively thin wire is formed between the Bit1contact and the ground, this entire electrical structure being patterned via direct-write lithography. With a relatively thin wire, the resistance between the Bit1contact and the ground can be relatively high. This resistance value can be associated with a second value or code (e.g. code01). The first conductive path can be formed then with different geometries to create a different resistance value.FIG.8shows an example of creating a different resistance value. InFIG.8, a direct-write pattern design defines a segment of the conductive path to have a greater thickness. This can appear as a block along the wire. With added thickness in this segment, resistivity can decrease resulting in a different resistance value between Bit1and ground as compared toFIG.7along Bit1conductive path (between Bit1and ground). This different resistance value can be a third value (e.g. code03). Conductive path resistance for each die or wafer can be further modified by directly writing new geometries for each conductive path. For example,FIG.9shows that for the length of this particular conductive path, up to eight blocks can be added to the conductive path. The number of blocks can be increased by resizing the blocks and/or lengthening the conductive path. With up to eight blocks added to the wire, the Bit1conductive path can support ten different digits/values/codes corresponding to different resistance values. For example, one digit for no wire, a second digit for wire only, and third through tenth digits for up to eight blocks. A mux or other circuitry can be used to test each conductive path for a resistance value. With eight blocks of poly added, the resistance would be less than with 7 blocks of poly (along a wire). Likewise, with 6 total blocks on the wire, the resistance would be less than with 7 blocks. The wiring structure can be varied in resistance using various different geometries. For example, in addition to adding blocks or segments on a wire, a width of the core line or core wire itself can be varied. In the example of the wiring structure ofFIG.10, it is noted that a width of the wire (line) extending between the Bit1contact and the ground is thicker as compared to a wire width ofFIG.9. If a given design enables 10 different line widths per conductive path, and each line width can have 0-8 blocks (9 different resistances), then the Bit1conductive path can support 91 different codes (including having no line). A total number of different codes (resistance values) for each conductive path can have any number of different values from geometric variations. This same resistance/capacitance design process can be repeated for the next conductive path and each subsequent conductive path. It is noted that for capacitance measurements, an underlying plate can be used. If each conductive path ofFIG.10can support 100 different values, and there are six conductive paths, then 1e12unique values can be created. Each conductive path/bit line can have a resistance read using a mux type circuit or other circuitry to read resistance (or capacitance). In another embodiment, the unique electrical signature or unique resistance value from the unique electrical structure can be coupled with an optical signature from the geometry. This combination can then provide a two factor authentication if desired. As can be appreciated, there are various geometric configurations of the wiring structure including placement of blocks. Referring now toFIG.11, and conductive path of Bit1, there are 5 blocks of 8 possible blocks formed. From top to bottom, the blocks are placed in the 1st, 3rd, 5th, 6th, and 8thpositions. The same resistance can be achieved by placing these blocks in the 1stthrough 5thpositions. While the resistance is the same, the visual placement is different. This visual difference can be used to create different optical/graphical patterns based on wiring geometry. In the conductive path of Bit3, four blocks are placed in the 5ththrough 8thspots instead of the 1stthrough 4thspots, or the even or odd numbered spots, et cetera. As can be appreciated, each conductive path can accommodate different physical arrangements of a specific resistance value depending on number of blocks compared to open spaces. It is noted also that blocks can be formed even when there is no wire between contact and target. For example, conductive paths Bit2and Bit5have no wire between contact and target, but still have placement of blocks. With the option of adjustable placement of blocks, the physical arrangement of blocks can function as a graphical signature or pictogram. Line widths can also function as part of the optical key. In other words, block placement along conductive paths can function as pixels of an image. This wiring structure can then be checked for a unique electrical value, and can also be viewed, via a microscope, to identify a unique graphical signature. Accordingly, the wiring structure can function as both a unique electrical identifier as well as a graphical/optical identifier. The optical, digital pattern provides a second level of security. The unique wiring structure or resistive structure herein can be built on any layer on a given chip. For example, the unique wiring structure can be placed on Metal01or Metal10or a top layer. If the unique structure is built on a lower level, then vias can extend several layers. The unique structure can go around an active parallel plate. The unique structure can be electrically connected to a corresponding chip or be isolated from the chip and attached to a separate processor. The unique electrical identifier for each chip can be measured while the chip is packaged. With the optical identifier, some packaging may need to be removed to view the optical pattern. A mux can be used to minimize contacts/pins to the unique electrical pattern. Having a mux device inside can help independently check each bit line. For example, there can be one input to a mux and one output to the mux. And then the mux can determine which clock line it reads. In the preceding description, specific details have been set forth, such as a particular geometry of a processing system and descriptions of various components and processes used therein. It should be understood, however, that techniques herein may be practiced in other embodiments that depart from these specific details, and that such details are for purposes of explanation and not limitation. Embodiments disclosed herein have been described with reference to the accompanying drawings. Similarly, for purposes of explanation, specific numbers, materials, and configurations have been set forth in order to provide a thorough understanding. Nevertheless, embodiments may be practiced without such specific details. Components having substantially the same functional constructions are denoted by like reference characters, and thus any redundant descriptions may be omitted. Various techniques have been described as multiple discrete operations to assist in understanding the various embodiments. The order of description should not be construed as to imply that these operations are necessarily order dependent. Indeed, these operations need not be performed in the order of presentation. Operations described may be performed in a different order than the described embodiment. Various additional operations may be performed and/or described operations may be omitted in additional embodiments. “Substrate” or “target substrate” as used herein generically refers to an object being processed in accordance with the invention. The substrate may include any material portion or structure of a device, particularly a semiconductor or other electronics device, and may, for example, be a base substrate structure, such as a semiconductor wafer, reticle, or a layer on or overlying a base substrate structure such as a thin film. Thus, substrate is not limited to any particular base structure, underlying layer or overlying layer, patterned or un-patterned, but rather, is contemplated to include any such layer or base structure, and any combination of layers and/or base structures. The description may reference particular types of substrates, but this is for illustrative purposes only. Those skilled in the art will also understand that there can be many variations made to the operations of the techniques explained above while still achieving the same objectives. Such variations are intended to be covered by the scope of this disclosure. As such, the foregoing descriptions of the embodiments are not intended to be limiting. Rather, any limitations to the embodiments are presented in the following claims. | 18,703 |
11862498 | DETAILED DESCRIPTION FIGS.1-14illustrate exemplary substrate processing apparatus100,100A,200,300,400,500,800,900,1200,1300in accordance with aspects of the disclosed embodiment. Although the aspects of the disclosed embodiment will be described with reference to the drawings, it should be understood that the aspects of the disclosed embodiment can be embodied in many forms. In addition, any suitable size, shape or type of elements or materials could be used. Based on the problems and limitations of conventional substrate processing apparatus noted above, it is desirable to have a new and innovative substrate handler and associated controls framework that are configured to operate in vacuum environment substantially without bearing and lubricants, perform substrate transfers across scalable distances without impacting the substrate handler design, transport substrates at higher accelerations than the conventional solutions noted above (i.e., substantially without requiring new end-effector materials), and operate multiple substrate handlers in a coordinated manner to avoid collisions and reduce a footprint of the substrate processing apparatus. Referring toFIGS.15A-15C, a wafer handler1500is part of linear electrical (or electric) machine1599(as will be described in greater detail herein and also referred to as an electromagnetic conveyor substrate transport apparatus) included in the substrate processing apparatus ofFIGS.1-14. The wafer handler1500includes a paramagnetic base1510(also referred to as a reaction platen) (e.g., made of copper, aluminum or other suitable diamagnetic or nonmagnetic material that can induce Eddy currents) that is shaped to effect at least bi-directional linear induction propulsion along a direction of linear tracks1550formed by at least one linear induction motor stator1560, and independent rotation of the base1510. The wafer handler1500also includes an end-effector1520that is rigidly attached to the base1510and configured to stably hold substrates for transport throughout a respective chamber of a substrate processing apparatus. The wafer handler1500is controlled by actuator and sensor control units, as will be described herein so that the configuration of the wafer handler1500is not dependent on the stroke distances the wafer handler1500can cover (or extend). The independence of the wafer handler configuration1500is effected by utilizing a network of actuators1700and sensors2000(shown in and described in greater detail with respect toFIGS.17-20and39) that are physically distributed along at least a length of the substrate processing apparatus (such as along a length of a transport chamber118) as will be described herein. In the aspects of the disclosed embodiment, the actuators1700and sensors2000are not tied to any specific substrate handler1500; rather, the same actuators1700and sensors2000(are common to and) can control multiple substrate handlers1500concurrently, which reduces cost of ownership of the substrate handlers1500as the substrate handlers1500may be added to or removed from a substrate processing apparatus without adding additional actuators and sensors. Concurrent control of multiple substrate handlers1500with common actuators1700and sensors2000is effected by a control system in accordance with the aspects of the disclosed embodiment (described in greater detail below) that is configured to dynamically allocate the excitation phase of each actuator coil unit (also referred to as an electromagnet) of the common actuators1700between different excitation phases in a manner that provides continuity of force vectors for performing wafer handler motion in a three-dimensional space with control of up to six degrees of freedom from the common (set) of actuators1700. As will be described herein, the concurrently controlled substrate handlers1500may be controlled in roll, pitch, and/or yaw to allow two or more independently operated substrate handlers1500to decrease a distance between the substrate handlers1500by tilting each (or at least one) of the substrate handlers1500along a rotation axis substantially parallel to the motion thrust direction (see, e.g.,FIG.29). As noted above, conventional robotic manipulators with articulated links require substantially different mechanical designs as the required stroke of the manipulators is increased in order to reach a larger number of process modules, which increases the cost of the robotic manipulators and may shorten robotic manipulator service intervals. Contrary to conventional substrate handling systems, the aspects of the disclosed embodiment are highly scalable when compared to existing commonly accepted substrate handling solutions (such as those described above) without adding complexity and reliability concerns resultant from an increased number of mechanical components. The aspects of the disclosed embodiment also effect substantially higher substrate processing throughput compared to the conventional substrate handling solution. As described herein, the aspects of the disclosed embodiment include an innovative motion sensing controls framework that pitches a substrate holding surface of the substrate handler end effector towards a direction of movement to provide for higher accelerations compared to the conventional substrate handling solutions while maintaining contact between the wafer and the end effector without slippage. As will be described in greater detail herein, the aspects of the disclosed embodiment provide for a magnetic levitated substrate transport apparatus based on linear induction technology that is configured to provide lift, lateral stabilization, and propulsion to the substrate handler. Aspects of the disclosed embodiment also provide for a linear induction motor stator operating in and forming independently controlled linear tracks that are orthogonal or otherwise angled at an orientation between being substantially parallel and substantially orthogonal and/or forming arcuate or rotary paths over a two-dimensional area. The aspects of the disclosed embodiment provide a coil controller that is configured to generate alternating current at a prescribed frequency and amplitude for each phase of each linear induction motor stator associated with a respective linear track1550. The propulsion forces provided by the linear tracks are controlled so as to rotate the base1510, independent of linear movement of the base along the tracks, where the propulsion forces generate a moment load around an axis of rotation of the base1510. The aspects of the disclosed embodiment include a control system configured to track a position of the base1510and control the phase currents of the independent linear tracks1550for controlling motion of the base1510along a desired propulsion direction along the independent linear tracks1550. The control system, in accordance with aspects of the disclosed embodiment, also provides for motion of the base1510in a lift direction while maintaining lateral stabilization of the base1510. The control system is configured to generate propulsion forces with the linear tracks1550so as to control roll, pitch, and yaw of the substrate handler1500, where the roll, pitch, and yaw motions of the substrate handler1500may be employed to maximize substrate production throughput by adjusting an inclination of the substrate handler1500(see, e.g.,FIG.21) depending on a desired acceleration of the substrate handler1500in linear and/or rotation directions of motion, so as to increase the acceleration threshold along a thrust direction of the substrate handler1500. The aspects of the disclosed embodiment include a sensor processing unit1850(seeFIG.18) that may be part of a sensor and controls network such as EtherCat® (Ethernet for Control Automation Technology, referred to as ECat inFIG.18), EtherNet® (referred to as ENet inFIG.18) or other suitable sensor and controls network. The sensor processing unit includes a general-purpose sensor and processing hardware (including non-transient computer program code or software) configured to interface with multiple sensor technologies such as cameras1810, CCD arrays1811, accelerometers1812, temperature sensors1813, proximity or distance sensors1814, magnetic sensors1815, vibration sensors1816, or any other suitable sensors. Referring toFIG.1A, there is shown a schematic plan view of a substrate processing apparatus100incorporating aspects of the disclosed embodiment. The substrate processing apparatus100is connected to an environmental front end module (EFEM)114which has a number of load ports112as shown inFIG.1A. The load ports112are capable of supporting a number of substrate storage canisters171such as for example conventional FOUP canisters; though any other suitable type may be provided. The EFEM114communicates with the processing apparatus through load locks116which are connected to the processing apparatus as will be described further below. The EFEM114(which may be open to atmosphere) has a substrate transport apparatus (not shown—but in some aspects is similar to the linear electrical machine1599described herein) capable of transporting substrates from load ports112to load locks116. The EFEM114may further include substrate alignment capability, batch handling capability, substrate and carrier identification capability or otherwise. In other aspects, the load locks116may interface directly with the load ports112as in the case where the load locks have batch handling capability or in the case where the load locks have the ability to transfer wafers directly from the FOUP to the lock. Some examples of such apparatus are disclosed in U.S. Pat. Nos. 6,071,059, 6,375,403, 6,461,094, 5,588,789, 5,613,821, 5,607,276, 5,954,472, 6,120,229, and 6,869,263 all of which are incorporated by reference herein in their entirety. In other aspects, other load lock options may be provided. Still referring toFIG.1A, the processing apparatus100, may be used for processing semiconductor substrates (e.g. 200 mm, 300 mm, 450 mm, or other suitably sized wafers), panels for flat panel displays, or any other desired kind of substrate, generally comprises transport chamber118(which in one aspects holds a sealed atmosphere therein), processing modules120, and at least one substrate transport apparatus or linear electrical machine1599. The substrate transport apparatus1599in the aspect shown may be integrated with the chamber118or coupled to the chamber in any suitable manner as will be described herein. In this aspect, processing modules120are mounted on both sides of the chamber118. In other aspects, processing modules120may be mounted on one side of the chamber118as shown for example inFIG.2. In the aspect shown inFIG.1A, processing modules120are mounted opposite each other in rows Y1, Y2or vertical planes. In other aspects, the processing modules120may be staggered from each other on the opposite sides of the transport chamber118or stacked in a vertical direction relative to each other. Referring also toFIGS.15A-15C, the transport apparatus1599has substrate handler1500that is moved in the chamber118to transport substrates between load locks116and the processing chambers120. In the aspect shown, only one substrate handler1500is provided; however, in other aspects more than one substrate handler may be provided. As seen inFIG.1A, the transport chamber118(which is subjected to vacuum or an inert atmosphere or simply a clean environment or a combination thereof in its interior) has a configuration, and employs the novel substrate transport apparatus1599that allows the processing modules120to be mounted to the chamber118in a Cartesian arrangement with processing modules120arrayed in substantially parallel vertical planes or rows. This results in the processing apparatus100having a more compact footprint than a comparable conventional processing apparatus, such as those described herein. Moreover, the transport chamber118may be capable of being provided with any desired length (i.e., the length is scalable) to add any desired number of processing modules120, as will be described in greater detail below, in order to increase throughput. The transport chamber118may also be capable of supporting any desired number of transport apparatus1599therein and allowing the transport apparatus1599to reach any desired processing chamber120coupled to the transport chamber118without interfering with each other. This in effect decouples the throughput of the processing apparatus100from the handling capacity of the transport apparatus1599, and hence the processing apparatus100throughput becomes processing limited rather than handling limited. Accordingly, throughput can be increased as desired by adding processing modules120and corresponding handling capacity on the same platform. Still referring toFIG.1A, the transport chamber118in this aspect has a general rectangular shape though in other aspects the chamber may have any other suitable shape. The chamber118has a slender shape (i.e. length much longer than width) and defines a generally linear transport path for the transport apparatus1599therein. The chamber118has longitudinal side walls118S. The side walls118S have transport openings or ports1180(also referred to as substrate pass through openings) formed therethrough. The transport ports1180are sized large enough to allow substrates to pass through the ports (can be sealable through valves) into and out of the transport chamber118. As can be seen inFIG.1A, the processing modules120in this aspect are mounted outside the side walls118S with each processing module120being aligned with a corresponding transport port1180in the transport chamber118. As can be realized, each processing module120may be sealed against the sides118S of the chamber118around the periphery of the corresponding transport aperture to maintain the vacuum in the transport chamber. Each processing module120may have a valve, controlled by any suitable means to close the transport port when desired. The transport ports1180may be located in the same horizontal plane. Accordingly, the processing modules on the chamber are also aligned in the same horizontal plane. In other aspects, the transport ports1180may be disposed in different horizontal planes. As seen inFIG.1A, in this aspect, the load locks116are mounted to the chamber sides118S at the two front most transport ports1180. This allows the load locks116to be adjacent the EFEM14at the front of the processing apparatus. In other aspects, the load locks116may be located at any other transport ports1180on the transport chamber118such as shown for example inFIG.2. The hexahedron shape of the transport chamber118allows the length of the chamber to be selected as desired in order to mount as many rows of processing modules120as desired (for example seeFIGS.1B,3,4-7showing other aspects in which the transport chamber118length is such to accommodate any number of processing modules120). As noted before, the transport chamber118in the aspect shown inFIG.1Ahas a substrate transport apparatus1599having a single substrate handler1500. The transport apparatus1599is integrated with the chamber118to translate substrate handler1500back and forth in the chamber118between front118F and back118R. The substrate handler1500of the substrate transport apparatus1599has at least one end effector1520for holding one or more substrates. It should be understood that the transport apparatus1599, shown inFIG.1Ais a representative transport apparatus and, includes the substrate handler1500which is magnetically supported from the linear tracks1550. The transport apparatus1599will be described in greater detail below. The transport chamber118may form a frame with a level reference plane1299(e.g., that defines or otherwise corresponds (e.g., is substantially parallel) with a wafer transport plane1290—seeFIG.12B) linear tracks1550may be mounted to the side walls118S or floor of the transport chamber118and may extend the length of the chamber118. This allows the substrate handler1500to traverse the length of the chamber118. As will be described in greater detail below the linear tracks1550ofFIG.1Aeach include an array of electromagnets or actuators1700, also referred to herein as a network of actuators as inFIGS.14A,15B,15B,16B,16C, and17(e.g., that form at least one linear induction motor stator1560), connected to the transport chamber118to form a drive plane1598at a predetermined height H relative to the reference plane1299, the array of electromagnets1700being arranged so that a series of the electromagnets1700define at least one drive line within the drive plane1598, and each of the electromagnets1700A-1700n(seeFIG.15B) being coupled to an alternating current (AC) power source1585energizing each electromagnet1700A-1700n, where the alternating power source is, in one aspect, a three phase alternating current power source. As noted above (seeFIG.15A), the base or reaction platen1510is formed of a paramagnetic, diamagnetic, or non-magnetic conductive material disposed to cooperate with the electromagnets1700A-1700nof the array of electromagnets1700so that excitation of the electromagnets1700A-1700nwith alternating current from the alternating current source1585generates levitation forces FZ and propulsion forces FP (seeFIG.21) against the base1510that controllably levitate and propel the base1510along the at least one drive line177-180(see, e.g.,FIGS.1-8), in a controlled attitude relative to the drive plane1598. FIG.1Bshows another aspect of a substrate processing apparatus100A which is generally similar to apparatus100. In this aspect, the transport chamber118has two substrate handlers1500A,1500B independently operated by the array of electromagnets1700(as inFIG.16C). The substrate handlers1500A,1500B are substantially the same as the substrate handler1500in the previously described aspect. Both of the substrate handlers1500A,1500B may be supported from a common array of electromagnets1700as described before. The base1510of each substrate handler1500A,1500B may be driven by the same at least one linear induction motor stator1560as will be described herein, by individually controlling each coil element or electromagnet1700A-1700n(as inFIG.15B). Thus, as can be realized the end effector1520each substrate handler1500can be independently moved in linear movement and/or rotation using the at least one linear induction motor stator1560. However, in this aspect the substrate handlers1500A,1500B are not capable of passing each other in the transport chamber118as the transport chamber118includes but one drive line177(compared to transport chambers having multiple substantially parallel drive lines as shown inFIGS.8-10). Accordingly, the processing modules120are positioned along the length of the transport chamber118so that the substrate may be transported to be processed in the processing module in a sequence which would avoid the substrate handlers1500A,1500B from interfering with each other. For example, processing modules for coating may be located before heating modules, and cooling modules and etching modules may be located last. However, referring toFIGS.8-10, the transport chamber118may have any suitable width to provide for two or more drive substantially parallel drive lines177,178that extend at least along a portion of a longitudinal length of the transport chamber118so that the two substrate handlers1500A,1500B pass adjacent each other (akin to a side rail or bypass rail). In the aspects illustrated inFIGS.8-10the transport apparatus1599has two drive lines177,178but in other aspects any suitable number of substantially parallel longitudinally extending drive lines may be provided. In accordance with some aspects of the disclosed embodiment, the array of electromagnets1700(or at least a portion thereof) may also be used as heater for the wafer handler (e.g., so as to control heating of the reaction platen and/or wafer to a desired predetermined temperature and for a desired predetermined time) as in the case where it is desired to eliminate water vapor (e.g., gas) or potentially pre-heat the wafer/substrate picked from, e.g., a load port en route to a process module or alternatively reduce thermal gradient between the wafer at the process module and the wafer handler end effector. The heating of the wafer handler may be effected with the reaction platen in transit or with the reaction platen held static in a predetermined location/position. Still In accordance with some aspects of the disclosed embodiment, the array of electromagnets1700(or at least a portion thereof) may also be used as heaters as in the case where it is desired that the transport chamber118be heated for degas as in the case to eliminate water vapor for example. Controlled heating of the transport chamber118to a predetermined temperature for a predetermined time may be with the reaction platen static. The controlled heating of the transport chamber118may facilitate thermal scanning with suitable thermal sensors/infrared sensors of the transport chamber118, such as to identify presence and map a location of the reaction platen within the transport chamber118at cold start or power off of the transport chamber118and drives. Referring now toFIGS.4and5there are shown other substrate processing apparatus400,500in accordance with other aspects of the disclosed embodiment. As seen inFIGS.4and5the transport chamber(s)118,118A,118B,118C in these aspects is elongated to accommodate additional processing modules120. The apparatus shown inFIG.4has twelve (12) processing modules120connected to the transport chamber118. The processing apparatus500inFIG.5is illustrated as having two transport chambers118A,118B coupled to each other by a bridging chamber118C that provides for movement of the substrate handlers1500between the transport chambers118A,118B. Here, each transport chamber118A,118B inFIG.5has 24 processing modules120connected thereto. The numbers of processing modules120shown in these aspects are merely exemplary, and the substrate processing apparatus may have any other number of processing modules120as previously described. The processing modules120in these aspects are disposed along the sides of the respective transport chamber118A,118B in a Cartesian arrangement similar to that previously discussed. The number of rows of processing modules120in these aspects, however have been greatly increased (e.g. six (6) rows in the apparatus ofFIG.4, and twelve (12) rows in each of the apparatus ofFIG.5). In the aspect shown inFIG.4, the EFEM may be removed and the load ports112may be mated directly to the load locks116. The transport chambers of the substrate processing apparatus400,500inFIGS.4, and5may have multiple substrate handlers1500to handle the substrates between the load locks116and the processing chambers120. The number of substrate handlers1500shown is merely exemplary and more or fewer apparatus may be used. The substrate transport apparatus1599(a portion of which is illustrated inFIGS.4and5) in these aspects are generally similar to that previously described, comprising the linear tracks1550and substrate handler(s)1500. In the aspects shown inFIGS.4and5, while only a single longitudinal drive line (e.g., drive lines177,178,179is illustrated in each chamber118,118A,118B,118C, it should be understood that in other aspects multiple drive lines may longitudinally extend along each chamber118,118A,118B,118C in a manner substantially similar to that illustrated inFIGS.8-10. As can be realized, as with the other substrate transport apparatus100,100A,200,300,800,900,1200,1300described herein, the substrate transport apparatus400,500has a controller199for controlling the movements of the one or more substrate handlers1500of the substrate transport apparatus1599. Still referring toFIG.5, the transport chambers118A,118B in this case may be mated directly to a tool300(e.g., a stocker, photolithography cell, or other suitable processing tool) where the substrates are delivered to and removed from the tool300through chamber118C. As may be realized fromFIGS.1B,3and4-5the transport chamber118may be extended as desired to run throughout the processing facility P (FIG.5, and example of which is illustrated inFIG.7). As seen inFIG.5, and as will be described in further detail below, the transport chamber (generally referred to as transport chamber118) may connect and communicate with various sections or bays118P1-118P4in the processing facility P such as for example storage, lithography tool, metal deposition tool or any other suitable tool bays. Bays interconnected by the transport chamber118may also be configured as process bays or processes118P1,118P3. Each bay has desired tools (e.g. lithography, metal deposition, heat soaking, cleaning) to accomplish a given fabrication process in the semiconductor workpiece. In either case, the transport chamber118has processing modules120, corresponding to the various tools in the facility bays, communicably connected thereto, as previously described, to allow transfer of the semiconductor workpiece between chamber118and processing modules120. Hence, the transport chamber118may contain different environmental conditions such as atmospheric, vacuum, ultra-high vacuum (e.g., 10−5Torr), inert gas, or any other, throughout its length corresponding to the environments of the various processing modules connected to the transport chamber. Accordingly, the section118P1of the chamber in a given process or bay or within a portion of the bay, may have for example, one environmental condition (e.g. atmospheric), and another section118P2,118P3of the chamber118may have a different environmental condition. As noted before, the section118P1-118P4of the chamber118with different environments therein may be in different bays of the facility, or may all be in one bay of the facility.FIG.5shows the chamber118having four sections118P-118P4with different environments for example purposes only. The chamber118in this aspect may have as many sections with as many different environments as desired. As seen inFIG.5, the substrate handlers1500in the transport chamber118are capable of transiting between sections118P1-118P4of the chamber118with different environments therein. Hence, as can be realized fromFIG.5, each of the substrate handlers1500may with one pick move a semiconductor workpiece from the tool in one process or bay of the processing facility to another tool with a different environment in a different process or bay of the process facility. For example, substrate handler1500A may pick a substrate in processing module301, which may be an atmospheric module, lithography, etching or any other desired processing module in section118P1, of transport chamber118. The substrate handler1500A may then move along drive line177(or a drive line substantially parallel thereto where more than one longitudinal drive line are provided) from section118P1of the chamber118to section118P3(e.g., where the other substrate handlers1500are controller to avoid interference with substrate handler1500A in any suitable manner). In section118P3, the substrate handler1500A may place the substrate in processing module302, which may be any desired processing module. As can be realized fromFIG.5, the transport chamber118may be modular, with chamber modules connected as desired to form the chamber118(e.g., formed by the three chamber sections118A,118B,118C, where each chamber section118A,118B,118C may also include one or more chamber modules that are coupled to each other in any suitable manner). Referring also toFIG.1A, the modules may include internal walls118I, similar to walls118F,118R inFIG.1A, to segregate sections118P1-118P4of the chamber118. Internal walls181may include slot valves, or any other suitable valve allowing one section of the chamber118P1-118P4to communicate with one or more adjoining sections. The slot valves118V, may be sized to allow, one or more substrate handlers1500to transit through the valves18V from one section118P1-118P4to another. In this way, the substrate handlers1500may move anywhere throughout the chamber118. The valves118V may be closed to isolate sections118P1-1184of the chamber118so that the different sections may contain disparate environments as described before. Further, the internal walls118I of the chamber modules may be located to form load locks (see section118P4) as shown inFIG.5. The load locks118P4(only one is shown inFIG.5for example purposes) may be located in chamber118as desired and may hold any desired number of substrate handlers1500therein. In the aspect shown inFIG.5, processes within chamber sections118A and118B may be the same processes, for example etch, where the processing apparatus500including tool300(such as a stocker) are capable of processing substrates without any associated material handling overhead associated with transporting FOUPS from the stocker to individual process modules120via an automated material handling system, and transporting individual wafers via EFEM's to the respective processing modules120. Instead, a robot within the stocker directly transfers FOUPS171to the load ports (three load ports are shown per chamber section, more or less could be provided depending on throughput requirements) where the wafers are batch moved into locks and dispatched to their respective process module(s) depending on the desired process and/or throughput required. The chamber sections118A,118B or the stocker300may further have metrology capability, sorting capability, material identification capability, test capability, inspection capability, etc. as required to effectively process and test substrates. In the aspect of the disclosed embodiment shown inFIG.5, more or less chamber sections118A and118B may be provided that have different processes, for example etch, CMP, copper deposition, PVD, CVD, etc. where the chamber sections118A,118B, etc. in combination with the tool300being, for example a photolithography cell are capable of processing substrates without the associated material handling overhead associated with transporting FOUPs from stockers to individual process tool bays and a lithography bay via an automated material handling system, and transporting individual wafers via EFEM's to the respective processing tools. Instead, the automation within the lithography cell directly transfers FOUPS, substrates or material to the load ports112(again three load ports are shown per chamber section/process type, noting more or less could be provided depending on throughput requirements) where the substrates are dispatched to their respective process depending on the desired process and/or throughput required. An example of such an alternative is shown inFIG.7. In this manner, the apparatus inFIG.5processes substrates with less cost, lower footprint, less WIP required (compared to the conventional processing systems described herein)—therefor with less inventory and with a quicker turnaround when looking at the time to process a single carrier lot (or “hot lot”), and with a higher degree of contamination control resulting in significant advantages for the fabrication facility operator. The chamber sections118A,118B (each of which may be referred to as a tool or tool section) or the tool or cell300may further have metrology capability, processing capability, sorting capability, material identification capability, test capability, inspection capability, etc. as required to effectively process and test substrates. As can be realized fromFIG.5, the chamber sections118A,118B, and tool300may be coupled to share a common controller environment (e.g. inert atmosphere, or vacuum). This ensures that substrates remain in a controlled environment from tool300and throughout the substrate processing apparatus500. This eliminates use of special environment controls of the FOUPs as in conventional substrate processing apparatus such as those shown inFIGS.37and38. Referring now toFIG.7, there is shown an exemplary fabrication facility layout601incorporating aspects of the disclosed embodiment that are shown inFIG.5. Wafer handlers406, similar to wafer handlers1500transport substrates or wafers through process steps within the fabrication facility601through transport chambers602,604,606,608,610,612,614,616,618,620,624,626. Process steps may include epitaxial silicon630, dielectric deposition632, photolithography634, etching636, ion implantation638, rapid thermal processing640, metrology642, dielectric deposition644, etching646, metal deposition648, electroplating650, chemical mechanical polishing652. In other aspects, more or less processes may be involved or mixed; such as etch, metal deposition, heating and cooling operations in the same sequence. As noted before, wafer handlers406may be capable of carrying a single wafer or multiple wafers and may have transfer capability, such as in the case where wafer handler406has the capability to pick a processed wafer and place an unprocessed wafer at the same module. Wafer handlers406may travel through isolation valves654for direct tool to tool or bay to bay transfer or process to process transfer. Valves654may be sealed valves or simply conductance type valves depending upon the pressure differential or gas species difference on either side of a given valve654. In this manner, wafers or substrates may be transferred from one process step to the next with a single handling step or “one touch”. As a result, contamination due to handling is minimized. Examples of such pressure or species difference could be for example, clean air on one side and nitrogen on the other; or roughing pressure vacuum levels on one side and high vacuum on the other; or vacuum on one side and nitrogen on the other. Load locks656, similar to chambers118P4inFIG.5, may be used to transition between one environment and another; for example between vacuum and nitrogen or argon. In other aspects, other pressures or species may be provided in any number of combinations. Load locks656may be capable of transitioning a single wafer handler or multiple wafer handlers in a manner substantially similar to that described herein where a single drive line or multiple substantially parallel and/or orthogonal drive lines are provided. Alternately, substrate(s) may be transferred into load lock656on shelves (not shown) or otherwise where the wafer handler406is not desired to pass through the valve. Additional features658such as alignment modules, metrology modules, cleaning modules, process modules (ex: etch, deposition, polish, etc.), thermal conditioning modules or otherwise, may be incorporated in lock656or the transport chambers. Service ports660may be provided to remove wafer handlers406or wafers from the tool. Wafer or carrier stockers662,664may be provided to store and buffer process and or test wafers. In other aspects, stockers662,664may not be provided, such as where carts are directed to lithography tools directly. Another example is where indexer or wafer storage module666is provided on the tool set. Recirculation unit668may be provided to circulate and or filter air or the gas species in any given section such as tool section612. Recirculation unit668may have a gas purge, particle filters, chemical filters, temperature control, humidity control or other features to condition the gas species being processed. In a given tool section more or less circulation and or filter or conditioning units may be provided. Isolation stages670may be provided to isolate wafer handlers406and/or wafers from different processes or tool sections that cannot be cross contaminated. Locks or interconnects672may be provided to change wafer handler406orientation or direction in the event the wafer handler406may pick or place within a generic workspace without an orientation change. In other aspects or methods any suitable combination of process sequences or make up could be provided. Referring now toFIG.6, the controller199controls the propulsion forces, generated by the array of electromagnets1700, across the base1510so as to impart a controlled yaw moment on the base, yawing the base1510about a yaw axis (e.g., axis of rotation777), substantially normal to the drive plane1598, from a first predetermined orientation relative to the frame of the chamber118(such as where the end effector1520is substantially aligned with drive line177), to a second different predetermined orientation relative to the frame of the chamber118(such as where the end effector is extended into process module120). As may be realized yawing of the base1510may be performed in conjunction with propulsion motion of the base1510(such as where a single drive line is provided in the chamber118) or with the base at a predetermined location (such as where the base1510is rotation while remaining substantially stationary along the X and Y axes). In one aspect, referring also forFIG.15C, the controller199controls the propulsion forces (e.g., Fxright, Fxleft), generated by the array of electromagnets1700, so as to impart a moment couple (illustrated inFIG.15Cwith movement of the substrate handler1500along the X axis) on the base1510effecting controlled yaw of the base1510so as to effect at least one of positioning and centering of a substrate (also referred to as a wafer payload or payload) on the base1510relative to a predetermined substrate holding location (such as a load lock, process module, etc.) of the frame of the chamber118. As may be realized, pitch (rotation about Y axis) and roll (rotation about X axis) (seeFIGS.15A and15B) control may be effected with the controller199(controlling lift forces Fz across the reaction platen) simultaneously with yaw motion countering dynamic moment coupling and maintaining substantially flat yaw of the wafer holder/reaction platen in the wafer transfer plane. Where a single drive line177is provided in each transport chamber (as illustrated inFIGS.1A,1B,2,4, and5) or where access to a process module, such as process module120A (seeFIG.8) from a drive line178closest to the process module120A (such as when multiple substantially parallel longitudinal drive lines177,178are provided—seeFIG.8), the controller199is configured to drive the base1510simultaneously in two or more of yaw, pitch, roll, and in propulsion (as described herein) to pick and place substrates from any suitable substrate holding stations (e.g. load locks116, process modules120, etc.). For example, the controller199is configured to energize the actuators1700as described herein so that the base moves along the drive line177and rotates about a base rotation axis777so that a substrate seating surface1520A of the substrate handler1520enters a process module120or other suitable holding station where the substrate S travels along a substantially straight line path790in a predetermined wafer/substrate transfer plane. Referring toFIGS.8-11, in other aspects, where multiple longitudinal drive lines177,178are provided in the transport chamber118the base1510may be rotated so that the substrate handler1520is aligned with a desired/predetermined substrate holding station prior to entrance into the substrate holding station. For example, the base1510may be positioned at an intersection between drive lines178and179A, where drive line179provides for extension and retraction of the substrate handler into substrate holding station120BH of process module120B (e.g., in a propulsion direction substantially orthogonal (or any suitable angle that enables access to the process module) to the propulsion direction along drive lines177,178). The base1510may be rotated about rotation axis777so that the substrate handler1520is aligned with the substrate holding station120BH and the base may be moved along drive line179A to move or extend the substrate handler1520into the substrate holding station120BH for picking/placing a substrate(s). Referring toFIGS.14and14A-14C, while the substrate handler1500has been described as including an end effector1520, in other aspects one or more substrate handlers may be configured as a cart1500C that is configured to support one or more substrates on the base1510. For example, the base1510may include one or more substrate supports1431-1433configured to stably hold a substrate (e.g., from the bottom or edge grip) so that substrate handlers1500,1500A,1500B or substrate transports within, e.g., a load or other substrate holding station, may transport substrate(s) to and from the substrate supports1431-1433. In one aspect, the substrate supports1431-1433may be configured to substantially center one or more substrates on the base1510(i.e., the supports are self-centering supports, that are either passive supports or may be actuated (e.g., piezo-electric) from a suitable power source energized on the reaction platen) so that a center of the substrate(s) is substantially coincident with the axis of rotation777of the base. In some aspects, one or more of the carts1500C may include a substrate support rack1440for holding two or more substrates in a stack, where each rack level includes respective substrate supports1431-1433,1431A-1433A. Referring toFIGS.14and14A, the carts1500C may provide an interface between the substrate handlers1500A,1500B and the load locks116where a transport apparatus116R (such as a SCARA arm, linear sliding arm, etc.) of the load lock transfers substrate(s) to the cart1500C and the substrate handlers1500A,1500B pick the substrates from the cart and vice versa. In other aspects, where the process module120includes a transport apparatus120R (such as a SCARA arm, linear sliding arm, etc.) the carts1500C may be employed to transfer substrate(s) to and from the process module120. While the base1510of the carts1500C (and of the substrate handlers1500,1500A,1500B) are illustrated as having a circular shape when viewed from the top (seeFIG.14C) in other aspects, the base1510may have any suitable shape (e.g., square, rectangular, circular, etc. when viewed from the top) that otherwise interfaces with the array of electromagnets1700for effecting one or more of linear propulsion, lift, yaw, pitch, roll, and rotation control of the base1510. Referring toFIGS.12A,12B,13A,13B, while the transport chamber118has been described above as a longitudinally extended chamber that forms part of a linear processing tool, in other aspects, the transport chamber may have a cluster tool configuration. For example, referring toFIGS.12A and12Bthe transfer chamber118T1has a substantially square configuration (although in other aspects the transfer chamber may have any suitable shape such as hexagonal, octagonal, etc.). In this aspect an electrical machine1599R (substantially similar to the linear electrical machine1599) is configured as a side-by-side transport apparatus that includes at least two side-by-side substrate handlers1500A,1500B that are substantially similar to substrate handler1500described herein. The array of electromagnets1700in this aspect is configured to move the substrate handlers1500A,1500B so that the substrate handlers1500A,1500B rotate about common axis of rotation1277(such axis being akin to a θ axis of, for example, a conventional SCARA type robot) for changing a direction of “extension and retraction” (the terms extension and retraction are being used herein for convenience noting that the extension and retraction is effected by linear propulsion movement of the substrate handler1500,1500A,1500B along a respective drive line) of the side-by-side transport apparatus. For example, the array of electromagnets1700has an arrangement that forms drive lines177,178,179,180. Here drive lines177,178are spaced from one another and substantially parallel to one other so as to be substantially aligned with a respective transport openings1180A,1180F and1180B,1180E. The drive lines179,180are substantially orthogonal to drive lines177,178and are spaced from one another and substantially parallel to one other so as to be substantially aligned with a respective transport openings1180C,1180H and1180D,1180G. The drive lines can be in any suitable pattern (such as arced or curved segments with constant or varying radii) and orientation and the description that follows is for exemplary purposes. The electromagnets1700A-1700N (illustrated inFIG.12Abut not numbered for clarity of the figure) provide for at least linear propulsion of the substrate handlers1500A,1500B through the transport openings1180A-1180H. In this aspect, the array of electromagnets1700also includes rotational electromagnet sub-arrays1231-1234that effect, under control of controller199, with the electromagnets that form the drive lines177-180the rotation of the substrate handlers1500A,1500B about the common axis of rotation1277. Alternatively, the electromagnets may form a dense enough and large enough grid without being specifically designated for propulsion or rotation and can perform that function based on the base's1510position and the control law of the controller199. As may be realized, while the substrate handlers1500A,1500B may rotate about the common axis of rotation1277at the same time, extension and retraction of the substrate handler1500A,1500B may be independent of extension and retraction of the other one of the substrate handler1500A,1500B. In general, the motion of the substrate handler1500A,1500B is independent of each other and the complexity of that motion can range from one degree of freedom to six degrees of freedom. Referring toFIG.12B, in one aspect, the electrical machine1599R includes multiple transport levels1220A,1220B that are stacked one above the other. In this aspect, each level1220A,1220B is formed by a respective level support1221each having a respective reference plane1299R that is substantially parallel with the level reference plane1299of the transport chamber118T1frame. Each level support1221includes an array of electromagnets1700substantially similar to that illustrated inFIG.12Afor linearly driving the side-by-side substrate handlers1500A,1500B along drive lines177-180and rotating the side by side substrate handlers1500A,1500B (e.g., with full six degree of freedom control) about the common axis of rotation1277. Each level support1221is coupled to a common Z axis drive1211that moves the level supports1221and the substrate handlers1500A,1500B thereon in the Z direction so as to align the end effectors1520of the substrate handlers1500A,1500B on the respective level supports1221with a substrate transport plane1290of the transport openings1180of the transport chamber118T1. The Z axis drive1211may be any suitable linear actuator such as a screw drive, electromagnetic drive, pneumatic drive, hydraulic drive, etc. In another aspect referring toFIGS.13A and13Bthe transfer chamber118T2has a substantially hexagonal configuration (although in other aspects the transfer chamber may have any suitable shape as noted herein). In this aspect the electrical machine1599R (substantially similar to the linear electrical machine1599ofFIG.15C) is configured as a radial transport apparatus that includes a substrate handler1500having a double ended/sided end effector1520D, as will be described herein (although in other aspects a single ended/sided end effector may be employed). The array of electromagnets1700in this aspect is configured to rotate the substrate handler1500about axis of rotation1377(such axis being akin to a θ axis of, for example, a conventional SCARA type robot) for changing a direction of “extension and retraction” (the terms extension and retraction are being used herein for convenience noting that the extension and retraction is effected by linear propulsion movement of the substrate handler1500along a respective drive line), and linearly propel the substrate handler1500so as to extend through the transport openings1180A-1180F. For example, the array of electromagnets1700has an arrangement that forms radially offset drive lines177,178,179, where an angle α between adjacent drive lines depends on the number of sides/facets of the transport chamber118T2on which the transport openings1180A-1180F are located. The electromagnets1700A-1700N (illustrated inFIG.12Abut not numbered for clarity of the figure) provide for at least linear propulsion of the substrate handler1500through the transport openings1180A-1180H and rotation of the substrate handler1500about axis of rotation1377with full six degree of freedom control so as to maintain linear transport and rotation in a desired attitude in pitch and roll. Referring toFIG.13B, in one aspect, the electrical machine1599R includes multiple transport levels1320A,1320B that are stacked one above the other in a manner substantially similar to that described above with respect toFIG.12B. For example, each level1320A,1320B is formed by a respective level support1321each having a respective reference plane1299R that is substantially parallel with the level reference plane1299of the transport chamber118T1frame. Each level support1321includes an array of electromagnets1700substantially similar to that illustrated inFIG.13Afor linearly driving (along drive lines177-179) and rotating (about axis1377) the substrate handler1500. Each level support1321is coupled to a common Z axis drive1311(that is substantially similar to Z-axis drive1211) that moves the level supports1321and the substrate handler1500thereon in the Z direction so as to align each of the end effector1520D of the substrate hander1500on the respective level supports1321with a substrate transport plane1390of the transport openings1180of the transport chamber118T2. Referring toFIGS.12B and13B, the vertical motion provided by the Z actuator1211can be used for enabling the wafer handler1220A or1220B to perform wafer handoff operations such as pick or place to/from a wafer process station. The supports1221,1321can include a single module (level) with the purpose of providing additional elevation capability to the wafer handler1220A,1220B to achieve larger vertical strokes during the wafer handoff operations. For example, in the case of process modules or load locks that have more than one stacked wafer slot, it would be advantageous to have a vertical lift apparatus such as Z-axis actuator1211,1311to be able to reach each of the stacked wafer slots without increase of applied levitation power provided by the electrical machine1599R. Referring toFIGS.12A and12B, the vertical lift apparatus (or Z-axis actuator)1211and level1221, in another aspect, has dual (or more) separate and independently operable apparatus, e.g., one for each wafer handler1520. This would give the ability to perform independent vertical strokes for different wafer handlers that can access different slots on at least two independent stations (e.g., process modules, load locks, etc.). Referring now toFIGS.15A,15B,15C,16A,16B,16Cthe linear electrical machine1599will be described in greater detail (again noting that the electrical machine1599R is substantially similar to the linear electrical machine1599). Generally, the linear electrical machine1599includes a structure1500without magnets and any, moving parts such as bearings, revolute or prismatic joints, metal bands, pulleys, steel cables or belts. As noted above, the base1510is formed of a paramagnetic material, diamagnetic material, or a non-magnetic conductive materal. The base1510may have any suitable shape and size for cooperating with the electromagnets1700A-1700nof the array of electromagnets1700so as to stably transport substrates S in the manner (s) described herein, one aspect, as illustrated inFIGS.9and11-160the base1510is shown with a frusto-conical shape where the tapered side1510TS of the frustum1510FR face the array of electromagnets1700(although other suitable shapes are operative). Here the tapered side1510TS of the frusto-conical shape have an angle λ (seeFIG.15B) that is between about 50° and about 60° relative to the planar surfaces of the frustum1510FR; while in other aspects the angle λ may be greater than about 60° or less than about 50°. In other aspects, the base may have a frusto-pyramidal shape as shown inFIGS.8,8A, and10. Here each side1510TSP of the frustum1510FRP have an angle λ (seeFIG.8B) that is between about 50° and about 60° relative to the planar surfaces of the frustum1510FRP; while in other aspects the angle λ may be greater than about 60′ or less than about 50°. While the frusta-pyramidal shape is illustrated as having four sides, in other aspects the frusto-pyramidal shape may have any suitable number of sides, such as, for example, six or eight sides or may be round or have curved sides. In other aspects, the base1510may not have a frusto-conical or frusta-pyramidal shape and it may comprise of a planar shape with suitable and asymmetric contour and size in order to be properly controlled by electromagnets1700. The end-effector1520,1520D may be substantially similar to conventional end effectors; however, as described herein the end effector is rigidly coupled to the base1510. As an example, the end effector may be a single sided/ended (see end effector1520) with a single substrate holding location1520A, a double sided; ended (see end effector1520D) with two longitudinally spaced apart substrate holding locations1520A,1520B, a side-by-side configuration where multiple substrate holding locations are arranged side-by-side (e.g., laterally spaced apart) and supported from a common base so as to extend through side-by-side substrate transport openings, a stacked configuration were multiple substrate holding locations are arranged in a stack one above the other and supported from a common base so as to extend through vertically arrayed substrate transport openings, while in other aspects the end effector may have any suitable configuration. The end effector1520,1520D may be made of materials that can one or more of withstand high temperatures, have low mass density, have low thermal expansion, have low thermal conductivity and have low outgassing. A suitable material from which the end effector1520,1520D may be constructed is Alumina Oxide (Al2O3), although any suitable material may be used. In one aspect, the end-effector1520,1520D is coupled to the base1510with a substantially rigid and unarticulated stanchion1510S so as to set the end-effector1520,1520D at a suitable nominal height H2relative to, for example, level reference plane1299. The substrate handler1500, as described herein, is moved in space (in at least three degrees of freedom) using electrodynamic levitation principles. The actuation elements (e.g., actuators1700), as shown inFIGS.15A-15C,16B, and16C include independently controlled coils or electromagnetics1700A-1700n(a so referred to herein as coil segments) that generate desired magnetic field that induces thrust and lift force vectors the base1510. In some aspects, referring toFIGS.10,10A,11, and11A, multiple substrate handlers may be nested with respect to each other so as to travel linearly along the drive lines177-180as a single unit with the end effectors1520of the nested substrate handler disposed in a stack one above the other. For example, referring toFIGS.10and10Athe nested bases1510FP (may be symmetrical as a body of revolution, revolute symmetry e.g., frusto-conical, or bi-symmetrical, e.g., frusto-pyramidal, or a channel shaped cross section of which are illustrated inFIG.10A) are configured so that one base1510FP may be inserted into another base1510FP so as to stack the bases1510FP in manner similar to that of stacking cups one inside the other. The bases1510FP may be configured so that when stacked the vertical space between end effectors1520(e.g., when the end effectors1520are substantially level with the level reference plane1299) is substantially the same as a vertical space between stacked substrate holding stations so as to provide for simultaneous picking and placing of substrates by the stacked end effectors1520. The stacking of the bases1510FP provides, in one aspect, depending on the levitation forces generated by the array of electromagnets1700, independent vertical or Z-axis movement of at least one of the bases1510FP (and the respective substrate handler1500A,1500B the base is part of). In this example, the uppermost substrate handler1500B may be moved in the Z-axis independent of the lowermost substrate handler1500A; however, when the uppermost substrate handler1500B is lifted away from the lowermost substrate handler1500A, the lowermost substrate handler1500A may also be moved in the Z-axis direction independent of the uppermost substrate handler1500B. Here, bi-symmetrical bases are interlocked and rotation of the substrate handlers1500A,1500B is linked by virtue of the shape of the bases1510FP so that the substrate handlers1500A,1500B rotate in unison. The stackable configuration of the bases1510FP provides the stacking of any suitable number of substrate handlers one above the other (in this example two are shown stacked one above the other but in other aspects more than two substrate handlers may be stacked one above the other). Referring toFIGS.11and11A, the revolute symmetry bases1510FC may be stacked one above the other, moved in the propulsion direction, and moved relative to each other along the Z-axis in a manner substantially similar to that described above with respect to the frusto-pyramidal bases1510FP. However, in this aspect, the revolute symmetry shape of the bases1510FC does not interlock and provides for independent rotation of each substrate handler1500A,1500B about substrate handler axis of rotation relative to another of the substrate handlers1500A,1500B. Independent rotation of the frusto-conical based substrate handlers1500A,1500B effects a fast swapping of substrates from a single substrate holding station such as where end effector1520of substrate handler1500A is aligned with substrate holding station120BH for picking substrate S1, where end effector1520of substrate handler1500B is rotated to a position so as to not extend into the substrate holding station120BH. Once the substrate S1is removed from substrate holding station120BH by substrate handler1500A, the positions of the end effectors1520of the substrate handlers may be swapped so that end effector1520of substrate handler1500B is aligned with the substrate holding station120BH for placing substrate S2at the substrate holding station120BH while end effector1520of substrate handler1500A is rotated to a position so as to not enter the substrate holding station120BH. As may be realized, the substrate handlers1500A,1500B may be moved along the Z-axis to accommodate the stacked heights of the end effectors relative to a height of the substrate holding station120BH. Though symmetrical (revolute about one or more axis) bases have been illustrated, in other aspects one or more bases may be asymmetrical or lacking any axis of symmetry. As described herein linear propulsion is generally provided by two parallel linear tracks1550(may be a single track) of independently controlled electromagnets1700A-1700n. The number of electromagnets1700A-1700nare spaced apart from one another depending on dimensions of the base1510so as to control all six degrees of freedom (roll, pitch, yaw, and translation in each of the X, Y, Z directions) of the substrate handler in space. For example, as illustrated inFIG.15B, the electromagnets1700A-1700nmay be spaced apart from each other so that two or more electromagnets1700A-1700n(cooperating so as to form a motor actuator (primary)1701and in combination with the base (secondary)1510the motor) of each parallel linear track1550are disposed underneath the base1510at all times in the direction of motion of the base so as to stably levitate and propel the base1510(as may be realized,FIGS.15A,15Bschematically illustrate a representative configuration of the system, and are provided to show generally an exemplary representation of the interrelationship between the base1510and the electromagnets1700A-1700n, and is not intended as limiting in any way. The size, numbers, and spacing (e.g., pitch) of the electromagnets1700A-1700nin both the X and Y axes may vary, as may the size and shape of the base1510in relation to the electromagnets1700A-1700n. In one aspect, as illustrated in.FIG.8, the array of electromagnets1700may also include stabilization tracks15505disposed laterally outward of the tracks1550. The stabilization tracks may be substantially similar to the tracks1550and are configured to provide additional stabilization of the base1510through the generation of additional lift and/or propulsion forces (e.g., in addition to the lift and propulsion forces generated by electromagnets of the parallel linear tracks1550) that act on the base1510. The result is a substrate handler1500that can move along a direction of the tracks1550(i.e., the propulsion direction) while changing orientation in one or more of roll, pitch and yaw. According to magnetic induction principles where the electromagnets1700A-1700nare akin to the “primary” and the base1510corresponds to the “secondary” where electrical currents are induced by means of Eddy current effects. FIG.17shows an actuator control system network1799, in accordance with an aspect of the disclosed embodiment, configured to effect individual control of each electromagnet1700A-1700nto provide the desired force components and degrees of freedom described and illustrated with respect toFIGS.15A-16C. In one aspect, the actuator control system is configured so that the electromagnets1700A-1700nform motor actuator units (collectively referred to as the motor actuator), each motor actuator unit having m number of electromagnets/coils cooperating to form the motor (where m is a dynamically selectable number of two or more electromagnets forming one or more of the motor actuator units as will be described further below). The actuator control system network1799is thus a scalable motion control system that has a clustered architecture with at least a master controller1760and distributed local drive controllers1750A-1750nas will be described in greater detail below. In this aspect, groups of electromagnets1700G1-1700Gn are coupled to a respective local drive controller1750A-1750nthat is configured to control the electrical currents on electromagnet1700A-1700nwithin the respective group of electromagnets1700G1-1700Gn. The local drive controller1750A-1750ncan be a “slave” in a network that is connected to a master controller1760that is configured to specify the desired forces (e.g., thrust and lift) for each individual electromagnet1700A-1700nto effect the desired motion of the substrate handler1500in space. As will be described herein, the electromagnets1700A-1700ncan be physical electromagnets/coils that ran be dynamically configured when it comes to the respective “phase” definitions of each coil with respect to “phase” definitions of the other electromagnets/coils of the given motor actuator unit so that the position of the given motor actuator unit (formed of cooperative excitation phases of the motor under propulsion) may be deemed as moving virtually in unison with the base propulsion, though the physical electromagnets/coils are fixed (e.g., static) as will be described further below. This provides continuity in the desired force vectors for motion control of the substrate handler. In accordance with aspects of the disclosed embodiment, and referring toFIGS.18and19, position feedback sensors2000are distributed on the frame of the chamber118. The sensors2000are configured for sensing position of the base1510along the drive plane1598and are communicably coupled to the controller199so the controller199registers the sensed position of the base1510, wherein the controller199is configured to sequentially excite the electromagnets1700A-1700nof the array of electromagnets1700corresponding to the sensed position in the manner described herein. FIGS.18and19illustrate a sensor control system network1899, in accordance with an aspect of the disclosed embodiment, that is configured to provide position feedback of the substrate handler1500in space, e.g., relative to the frame of the transport chamber118. The sensor control system network1899may be a scalable sensor control system that has a clustered architecture with at least the master controller1760and distributed local sensor controllers1850A-1850nas will be described in greater detail below. In this aspect, groups of sensors1800G1-1800Gn are coupled to a respective local sensor controller1850A-1850n(also referred to herein as a sensor processing unit)that is configured as a “slave” in a network that is connected to the master controller1760(or other suitable master controller in communication with master controller1760). Each of the local sensor controller1850A-1850nincludes a central processing unit1851and associated hardware interfaces1852that can support different types of sensor technologies such as those described herein. The local sensor controller1850A-1850ncan be integrated into a real time network such as EtherCat and/or a non-real time network such as Ethernet or similar. The sensors2000can be distributed along the propulsion path (e.g., drive lines177-180) of the substrate handler so as to detect the location/position of the substrate handler in space, e.g., relative to the frame of the transport chamber118. FIG.20illustrates a distributed sensor arrays2001that includes sensors2000A-2000nrelative to a substrate handler1500base1510and how the relationship between characteristic dimensions of the base1510and the sensors2000A-2000nthat effects a continuous feedback of the position of the substrate handler1500. As can be seen inFIG.20, the sensors2000A-2000nare disposed at a predetermine intervals or sensor pitch Ps where a sensor spacing Δ is provided between adjacent sensors2000A-2000n. Each sensor2000A-2000nhas a length so as to provide a predetermined sensing range Ls and the base1510has a length Lb. The relationship between these characteristics to provide continuous feedback is: Ls/2>Ps−Ls=>Ps<(3/2)Ls[2]where the length Lb of the base1510is: Lb=nPs+Ls/2(wheren=1,2,3, . . . ) [3] In accordance with aspects of the disclosed embodiment, each sensor2000A-2000nincludes any suitable deice (s) that can measure the longitudinal displacement and/or the air gap between the substrate handler1500base1510and a bottom reference surface, such as the level reference plane1299(see, e.g.,FIG.15A). The Master Controller1760is configured to track the location of the substrate handler1500by dictating which local sensor controller1850A-1850nshould be actively reporting feedback from the appropriate sensors1700A-1700n. The combination of the actuator control system network1799and the sensor control system Network.1899forms a motion control infrastructure for the six degrees of freedom of the substrate handler1500as shown inFIGS.15A-16C. Referring toFIG.39, a control system network3999that has a clustered architecture representative of the actuator control system network.1799and the sensor control system network1899will be described. In the example illustrated inFIG.39, there are three drive lines177,179A,1798, each having respective array of electromagnets forming respective tracks1550A-1550F (though shown as linear, may be arcuate). For example, drive line177is formed by tracks1550A and1550B having electromagnets177ER1-177ERn and177EL1-177ELn. Drive line179A is formed by tracks1550C and1550D having electromagnets179AER1-179AERn and179AEL1-179AELn. Drive line1798is formed by tracks1550E and1550F having electromagnets179BER1-179BERn and179BEL1-179BELn. The configuration of the electrical machine illustrated inFIG.39is exemplary and may have any other suitable configuration. InFIG.39the control system network includes the master controller1760, cluster controllers3950A-39500and local controllers1750DL,1750DLA,1750DLB,1850DL,1850DLA,1850DL1. Local controller1750DL corresponds to drive line177, local controller1750DLA corresponds to drive line179A, and local controller1750DLB corresponds to drive line179B. Each of the local controller(s)1750DL,1750DLA,1750DTE is substantially similar to distributed local drive controllers1750A-1750nso that each drive line177,179A,179B includes a distributed arrangement of local drive controllers1750A-1750nas described above with respect toFIG.17for controlling respective groups170001-17000nof electromagnets1700A-1700n. Similarly, Local controller1850DL corresponds to drive Line177, local controller1850DLA corresponds to drive line179A, and local controller1850DLB corresponds to drive line179B. Each of the local controller(s)1850DL,1850DLA,1850DLB is substantially similar to distributed local sensor controllers1850A-1850nso that each drive line177,179A,179B includes a distributed arrangement of local sensor controllers1850A-1850nas described above with respect toFIG.18for controlling respective groups180001-1800Gn of sensors2000A-2000n. In one aspect, as shown inFIG.39each of the local controllers1750DL,1750DLA,1750DLB,1850DL,1850DIA,1850DLB is connected (e.g., through a wireless and/or wired connection) to a respective cluster controller3950A-3950C. For example, each of the local controllers1750DL,1850DL, of crave line177are coupled to cluster controller3950B, each of the local controllers1750DMA,1850DLA of drive line179A are coupled to cluster controller3950A, and each of the local controllers1750DLB,1850DLB of drive line179B are coupled to cluster controller3950C. In other aspects, the local controllers may be connected (e.g., through a wireless or wired connection) directly to the master controller1760as shown inFIGS.17and19). In still other aspects, the local controllers may be connected (e.g., through a wireless or wired connection) to both the master controller1760and the respective cluster controller3950A-3950C to provide redundant substantially failsafe control of the local controllers. Each of the cluster controllers3950A-39500are connected (e.g., through a wireless or wired connection) to the master controller1760. Each of the master controller1760, cluster controllers3950A-3950C, and local controllers1750DL,1750DLA,1750DLB,1850DL,1850DLA,1850DLB includes any suitable processors and non-transitory computer program code to effect motion control of the substrate handlers1500as described herein. The master controller1760supervises the overall operation of the control system network3999, each of the cluster controllers3950A-39500supervises the operations of the respective local controllers1750DL,1750DLA,1750DLB,1850DL,1850DLA,1850DLB, and each local controller1750DL,1750DLA,1750DLB,1850DL,1850DLA,1850DLB is utilized to drive the electromagnets and/or provide position feedback (of a substrate handler1500) corresponding to the respective drive lines177,179A,179B. The clustered architecture provides the features of a centralized control network and the features of a distributed control network where required, within the network topology. The architecture as disclosed herein is advantageous because clusters may be distributed where required within the network, and each cluster controller3950A-3950C is capable of providing highly centralized control within the cluster it manages. Network traffic associated with highly centralized control is generally confined within each cluster and local controllers1750DL,1750DLA,1750DLB,1850DL,1850DLA,1850DLB may be located close to electromagnets or sensors to which they control, reducing problems associated with power and signal cabling. In addition, the clustered architecture allows for direct control of the local controllers1750DL,1750DLA,1750DLB,1850DL,1850DLA,1850DLB by the master controller1760where required. Furthermore, because intense network traffic is generally confined within the clusters, and the clusters are capable of a high level of control, the architecture may accommodate a large number of clusters. Thus, the architecture provides a high level of scalability and allows for an efficient distribution of controllers. It is noted that while a clustered control architecture is described above, clustered architecture is merely an example of a suitable control architecture, although any suitable control architecture may be employed. In another aspect of the disclosed embodiment, the local controllers1750DL,1750DLA,1750DLB,18501M,1850DLA,1850DLB shown inFIG.39can be directly connected to the master controller1760. In this aspect, the master controller software is responsible for (e.g., the master controller is configured to control) several aspects of the real time control of the wafer handler's motion and the local controllers would be responsible (e.g., configured for) all low level feedback and actuation aspects of the control architecture. Still referring toFIG.39and also toFIGS.15A-16C, in accordance with aspects of the disclosed embodiment, the processor3901of the master controller1760is programmed with a dynamic model3910of the base1510(e.g., the dynamic model is stored in any suitable memory3902accessible by the processor3901) with a payload (e.g., substrate(s) S) thereon and without a payload. The processor3901is also programmed with a dynamic model3911of frictional forces μ between the substrate S and the end effector1520. A form factor3912of the machine electronics (e.g., number of electromagnets, spacing between electromagnets, number of drive lines and their respective orientations, propulsion to lift relationship, etc.) relative to the base1510may also be stored in memory3902and accessible by the processor3901. The master controller1760is programmed or otherwise configured to determine kinematic motion of the base1510from an initial substrate handler pose to a final substrate handler pose. The master controller1760is also programmed or otherwise configured to determine the kinematics of attitude/yaw control (in three degrees of freedom—pitch, roll, yaw) related to the determined kinematic motion. In one aspect, the kinematic motion and the kinematics of attitude/yaw are determined e.g., using one or more of dynamic model3910, dynamic model3911and form factor3912in combination with a predetermined substrate process recipe (e.g., where and when the substrate is to be transferred and what process is to be performed on the substrate). One method for controlling a machine such as the electrical machines described herein is to calculate a trajectory for each of propulsion (along the X and/or Y axes), lift (along the Z axis), roll, pitch, yaw. Such trajectories can be conveniently defined by a series of position, velocity and time values grouped into frames, referred to as PVT frames. FIG.40Ashows an exemplary PVT frame4005. The PVT frame4005includes position data4010(which may include start location (X,Y,Z), end location (X,Y,Z), and attitude (roll, pitch, yaw), velocity data4015, and time data4020. In one aspect the data is in binary format grouped together in one or more bytes. In another aspect each of the position data4010, velocity data4015, and time data4020occupies four bytes (while in other aspects the each of the position data4010, velocity data4015, and time data4020occupies more or less than four bytes). PVT frame4005may optionally include header information4025and trailing information4030, both of which may include identification, parity, error correction, or other types of data. PVT frame4005may include additional data of varying lengths or amounts between or among the header, position, velocity, time, and trailing data. It should be noted that the PVT frame4005is not limited to any particular length. In other aspects, the PVT frame is either reduced to a PT frame or a P frame only. The communication from the master controller1760to the cluster/local controllers1750DL,1750DLA,1750DLB,1850DL,1850DLA,1850DLB may include different sets of values, which are peripherally related to the desired motion, for example, these values could De frequencies, phase offsets, current values and/or voltage values of the electromagnets/coil under control. The master controller1760implements the desired algorithmic transformation, calculates and streams via the motion network such quantities (effectively to every coil through an hierarchical scheme of cluster and local controllers). It is a feature of the aspects of the disclosed embodiment to use these series of values as inputs for the dynamic models3910,3911of the controlled electrical machine to calculate theoretical lift forces and propulsion forces to be applied by predetermined electromagnets1700A-1700nso that the base1510follows the desired trajectory. It is also a feature of the aspects of the disclosed embodiment to use elements of the dynamic models3910,3911to scale feedback control signals used by the local controllers1750DL,1750DLA,1750DLB,1850DL,1850DLA,1850DLB for each electromagnet under their control. The lift forces, propulsion forces, and scaling terms may advantageously account for non linearities and dynamic cross coupling among individual drive lines177,179A,179B. The lift forces, propulsion forces may be referred to herein as feedforward terms and the scaling term may be referred to as a gain term. Using the electrical machine1599shown inFIG.39(also referring toFIGS.15A-16C) as an example, the master controller1760may generate a trajectory for each drive line177,179A,179B, along which a substrate handler1500is to travel, in terms of a commanded position, velocity and acceleration. Using an inverse kinematic model of one or more of the base1510and/or frictional forces p, the master controller1760may utilize the trajectory information to generate corresponding feedforward, and gain terms. These terms may be grouped together with the trajectory information in frames specific to each drive line177,179A,179B, referred to as PVT-FG frames.FIG.40Billustrates an exemplary PVT-FG frame4095. PVT-FG frame4095includes optional header4025, position data4010, velocity data4015, time data4020, and optional trailing information4030, similar to PVT frame4005. In addition, PVT-FG frame4095includes at least one feedforward term4050and at least one gain term4060. The data may be in binary format grouped together in one or more bytes. In one aspect of the PVT-FG frame4095the position data4010, velocity data4015, time data4020, feedforward term4050, and gain term460each occupy four bytes (while in other aspects they may each occupy more or less than four bytes). Similar to PVT frame4005, PVT-FG frame4095may include other data of varying lengths or amounts, distributed among or between the various terms. The PVT-FG frames may (or in other aspects the PVT frames) then be distributed over the control system network3999. The cluster controllers3950A-3950C, receive the data, and may interpolate between two consecutive frames to obtain an instantaneous position, velocity, feedforward term and gain value, and utilize this information to effect control of the substrate handler1500. For example, each cluster controller3950A-3950C employs the PVT-FG frames (or in some aspects the PVT frames), or other suitable information/commands, from the master controller1760to generate the propulsion forces Fx (propulsion force along the X axis), Fy (propulsion force along the Y axis), and lift force Fz (along the Z axis) to effect one or more of levelling, propulsion, and three degree of freedom attitude control (e.g., roll, pitch, yaw) of the substrate handler1500and base1510thereof. In some aspects, the form factor3912of the machine electronics may be programmed at the cluster controller3950A-3950C level, rather than or in addition to being programmed in the master controller1760, where the form factor is used to establish the lift to propulsion relationship(s), and with the data provided by the master controller1760to generate the lift and propulsion forces noted above. In other aspects, the cluster controllers3950A-3950C and local controllers1750DL,1750DLA,1750DLB,1850DL,1850DLA,1850DLB may receive corresponding data from the master controller1760, and utilize the data to control the electromagnets1700A-1700nand movement of the substrate handler1500along one of more of the drive lines177,179A,179B. The cluster controllers3950A-3950C (or alternatively the local controllers1750DL,1750DLA,1750DLB,1850DL,1850DLA,1850DLB) command electromagnet1700A-1700nmodulation, which commands are sent to and received by the respective local controllers1750DL,1750DLA,1750DLB,1850DL,1850DLA,1850DLB, to effect one or more of dynamic phase allocation and the creation of virtual multiphase motor actuator units as described in greater detail herein. FIG.21illustrates an exemplary controlled motion (s) of the substrate handler1500in accordance with aspects of the disclosed embodiment with respect to increased substrate handler throughput while carry ng a substrate S. Here, the controller199controls the levitation forces (e.g., FZT, FZL), generated by the array of electromagnets1700, so as to impart differential levitation forces (illustrated inFIG.21) across the base1510that effect a controlled inclination (e.g., e+ or e−) of the base1510, relative to the drive plane1598, that controls a predetermined reaction platen attitude in at least one of pitch (shown inFIGS.15B,21and27) and roll (shown inFIGS.15A and29). In one aspect, the controller199controls the levitation forces (e.g., FZT, FZL), generated by the array of electromagnets1700of the motor actuator units (that are virtually moving), so as to effect a predetermined bias attitude BA+ or BA− of the base1510, relative to the drive plane1598, that imparts a bias reaction force F2(FIG.23), from a base payload seating surface (e.g., such as a substrate seating surface1520SS (FIGS.23,25A,25B) of the end effector1520or a seating surface defined by substrate supports of cart1431-1433of cart1500C) on a substrate S supported by the base seating surface, in a direction countering payload inertial force arising from acceleration of the reaction platen along the drive plane1598. The controller199is configured to determine acceleration of the base1510(and the substrate handler thereof) along the drive plane1598at least from changes in the position of the base1510sensed by the sensors2000, and in response to the acceleration determined, control the bias attitude of the base1510to provide the predetermined bias attitude countering the payload inertial force arising from the acceleration of the base1510. In other aspects the controller199may apply a predefined acceleration from commanded trajectory for bias attitude control. Here, the controller199controls excitation of the electromagnets1700A-1700nof the virtually moving motor actuator units of the array of electromagnets1700so as to set the bias attitude BA+ or BA− to bias the base1510against inertial forces tending to displace a substrate S, seated against the base1510(e.g., on an end effector1520thereof or substrate supports1431-1433thereof), relative to the base1510along a seat between the substrate S and the base1510(see, e.g.,FIGS.23,25A,25B). As an example of countering payload inertial forces, starting at the left-hand side ofFIG.21, a substrate handler1500(which may be any of the substrate handlers described herein) is depicted at a starting point of a motion in direction2122inFIG.21. As the substrate handler begins to move, a set of propulsion force vectors FP and lift force vectors FZ are generated by the Control System (e.g., the actuator control system network1799and the sensor control system Network1899which may be part of controller199) so as to cause the substrate handler1500to accelerate in the motion direction with an increased Pitch angle e+ (e.g., the end effector1520is tilted in, e.g., a clockwise direction). To effect the increased pitch angle e+ the lift force vectors FZ are generated so that a magnitude of a trailing lift force vector FZTis larger than a magnitude of a leading lift force vector FZL(where leading and trailing are in reference to the motion direction). As the substrate handler reaches approximately its halfway point towards the end of the motion (e.g., such as where there is substantially zero acceleration of the substrate handler1500), the pitch angle e+ is reduced in magnitude so that the tilted orientation of the end effector1520is reversed from the clockwise orientation to zero (e.g., substantially parallel with the level reference plane1299—the trailing lift force vector FZTand the leading lift force vector FZLare substantially equal). At this point in the trajectory, the substrate handler1500motion begins a deceleration stage where the pitch angle e− is decreased so that the end effector1520pitches to a counter clockwise orientation. To effect the decreased pitch angle e− the lift force vectors FZ are generated so that the magnitude of the trailing lift force vector FZTis less than a magnitude of the leading lift force vector FZL). As the substrate handler1500reaches its final destination, the pitch angle e− is increased to zero so that the tilted orientation of the end effector1520is substantially parallel with the level reference plane1299, as in the start of the motion. As may be realized, while the pitch of the end effector is increased or decreased to account for acceleration and deceleration of the substrate handler1500substantially without slippage of the substrate S relative to the end effector while travelling along a substantially straight/linear path (such as along drive lines177-180), in other aspects, the roll r and/or pitch e of the substrate handler1500may be increased or decreased to provide for higher rotational accelerations of the substrate handler1500(such as about one or more of axes777,1277,1377in a manner substantially similar to that described above with respect to the linear motion (seeFIG.21Awhich illustrates rolling of the end effector in rotation direction with roll control as shown inFIG.15Awhere lift force vector FZleftis greater than lift force vector FZright). The motion control illustrated inFIG.21effects a substantially faster substrate motion transport (e.g., provides for higher accelerations substantially without substrate slippage relative to the end effector) when compared to conventional substrate transport where the end effector is parallel with the wafer transfer plane throughout end effector motion. As an example, if the pitch angle e ofFIG.21is set to be zero (as with conventional substrate transports) during the entire motion then the maximum allowable propulsion acceleration is limited to the static coefficient of friction (μ) between the substrate S and a contact surface of the end effector1520. This is illustrated inFIG.22, which constitutes the typical use case in a conventional substrate transport where the substrate S is held by its back side in contact with the end-effector. As it can be seen inFIG.22, the maximum acceleration imposed to the substrate S μg before wafer slippage takes place. Where “g” is the acceleration of gravity (about 9.8/S2), μ is the coefficient of friction, M is the mass of the substrate, W is the weight of the substrate, and N is the normal force. FIG.23illustrates the case where the substrate (having a mass in) is carried by substrate handler1500(having a mass M) with a pitch angle e while the substrate handier1500is accelerated in the X direction. The force diagrams inFIG.23illustrate the dynamics of the motion of the substrate S and substrate handler1500. InFIG.23, the substrate hander1500is accelerated along the propulsion direction X with acceleration a. As a result, the force at the substrate handler is represented by the variable F1. The acceleration a along the X direction, impacts the reaction (normal) force N on the substrate S in a way that once added to the weight of the substrate W yields a resultant wafer force F2. It is possible to relate the angle e and the acceleration a in such a way that the substrate S substantially does not slip relative to the end effector1520of the substrate handler1500. To substantially prevent wafer slippage, two situations can be considered for the sake of clarity. First, it is assumed that there is no friction between the substrate and the end effector1520.FIG.24illustrates a free body diagram of the substrate S on the end effector1520in the absence of friction μ. As can be seen inFIG.24, despite the absence of friction μ, an acceleration a can be determined in terms of the pitch angle e such that the substrate mass in is traveling along the X direction. This relation is expressed by equation (4) below: a=gtane[4] where g is the acceleration of gravity (9.8 m/s2).FIG.24Aillustrates wafer slippage regions in terms of the pitch angle e. It is noted that the substrate S will slip relative to the end effector1520without friction μ if the pitch angle e is substantially zero. The curve illustrated inFIG.24Arepresents the desired pitch angle “e” to keep the substrate S moving at an acceleration “a” along the X direction without slippage. Alternatively, the same curve ofFIG.24Acan be interpreted as the demanded acceleration “a” of the substrate handler1500to prevent the substrate S from slipping while moving along the X direction with the pitch angle “e”. Deviation from the curve illustrated inFIG.24Awill cause the substrate S to slide either “downhill” or “uphill” (where the terms downhill and uphill are used for convenience relative to the pitch) relative to the end effector1520depending on the acceleration value. FIGS.25A and25Bshow the effect of a non-zero static friction coefficient μ on the relation between acceleration a and pitch angle e. For example,FIG.25Aillustrates a minimum propulsion acceleration before slippage of the substrate S relative to the end effector1520takes place. In this case, the friction force direction points “uphill” to substantially prevent the wafer mass m from sliding “downhill” (again relative to the direction of pitch). Here, the “slowest” expected acceleration to prevent wafer slippage is calculated as: amin=[−μ+tane]/[1+μ tane][5] FIG.25B, illustrates the case for the maximum (e.g., fastest) expected propulsion acceleration a before slippage of the substrate S relative to the end effector1520. In this case, the friction force direction points “downhill” to substantially prevent the wafer mass m from sliding “uphill” (again relative to the direction of pitch). Here, the “fastest” expected acceleration a is calculated as: amax=[μ+tane]/[1−μ tane][6] Consequently, in the presence of a non-zero static friction coefficient μ the propulsion acceleration a should stay within the limits below in order to prevent substrate S slippage, for a given pitch angle: amin<a<amax[7] FIG.26provides an example of the dependency between acceleration a and pitch angle e for a static coefficient of μ that is about 0.1, which is a typical value for substrate handlers used in high temperature applications. The curve ofFIG.24Ais repeated inFIG.26under the case of μ equal to about 0. The region between the top and bottom curves (μ equal to about 0.1) represents a non-slippage region. (e.g., a region of acceleration for a given pitch angle where the substrate slippage relative to the end effector substantially does not occur). The areas outside this region may have wafer slippage either in the upwards of downwards direction relative to the substrate handler inclination (i.e., pitch angle e). In the example ofFIG.26, the maximum acceleration with a substantially zero pitch angle is about 0.1 g which is the fastest acceleration that conventional substrate handlers can provide for typical high temperature applications. If the pitch angle e is set to about 16 degrees of inclination, the substrate can be transported at accelerations as high as 0.4 g using the same end effector material (as in conventional substrate handlers) which constitutes a substantial throughput improvement compared to the conventional substrate handlers. The pitch angle e can be set according to a predetermined acceleration in order to maximize throughput such as depicted inFIG.21. FIG.27illustrates active control of the substrate handler1500orientation in roll, pitch, and yaw with respect to leveling of the substrate handler1500relative to a substrate station, such as process module120. Mechanical deflection imposes challenges on entering and exiting process module openings2780which are becoming increasingly smaller in height H3due to the need of optimizing process module120process times. Conventional substrate transports generally suffer from the inherent potential of mechanical deflection due to the presence of articulated links with bearings that add weight and decrease stiffness, noting that compensating for the end-effector orientation as the wafer goes through the process module opening2780may not be practical. In these cases, it is becoming increasingly difficult to be able to comply with more restrictive mechanical deflection constraints. The aspects of the disclosed embodiment provide a solution to mechanical deflection that dynamically compensates for any mechanical deflection by controlling the substrate handler orientation in space, relative to the level reference plane (e.g., by adjusting the roll, pitch and yaw angles as described herein) such that a substrate passes through the process module opening2780substantially without contact between the substrate S and the opening2780and substantially without contact between the end effector1520and the opening2780. FIGS.15A-16Cillustrate the controlled adjustment, by the local drive controller(s)1750A-1750nand the local sensor controller (s)1850A-1850n, of the roll and yaw angles of the substrate handler1500in addition to the pitch angle. Referring also toFIG.27, the controlled adjustment of each of the roll, yaw, and pitch angles (e.g., by differentially varying at least the lift force vectors acting on the base1510as described herein) effects leveling a position of the substrate handler1500at any suitable substrate holding station such as a process module120so that a plane2770of the substrate S (and end effector1520on which the substrate S is supported) is substantially the same as a plane2771defined by the substrate holding station120substrate support surface2760. In some aspects, the roll, yaw, and pitch angles are adjusted independent of each other. The controlled adjustment of the substrate handler1500orientation angles (e.g., roll, pitch, and yaw) also provides for compensation of mechanical deflection of the end effector1520due to, for, example, the substrate loading as well as the weight of the substrate handler1500structure. Referring toFIGS.8-11and28and29, as described above, in some aspects multiple drive lines177,178are provided so as to extend longitudinally along a length of the transport chamber118to provide passage of one substrate handler1500by another substrate handler along the longitudinal direction of the transport chamber118.FIG.28illustrates passage of two substrate handlers1500A,1500B past one another with substrate handler1500A traveling along an inbound track1550A and with substrate handler1500B travelling along an outbound track1550B. Here each of the substrate handlers1500A,1500B have roll, pith, and yaw angles so that the plane2770of the end effector1520(and substrate s held thereon) is substantially parallel (i.e., level) with the level reference plane1299. Here, with the end effectors1520level, the transport chamber118has a lateral width W1. However, in accordance with aspects of the disclosed embodiment, the width of the transport chamber118may be minimized or otherwise reduced from lateral width W1to lateral width W2by adjusting one or more of the roll, the pitch, and the yaw of the substrate handlers1500A,1500B as they pass one another along the length of the transport chamber118. For example, as illustrated inFIG.29the roll angle of each substrate handler1500A,1500B may be adjusted to a predetermined angle β relative to the level reference plane1299to avoid contact between the substrate handlers1500A,1500B as they move past one another during a period of time that both substrate handlers1500A,1500B would otherwise occupy the same space. The predetermined roll angle β may depend on end effector configuration (e.g., so that the substrate S does not slip relative to the end effector). As may be realized it advantageous to have control of the roll, pitch, and/or yaw angles of each substrate handler1500in order to reduce a footprint of: the transport chamber118that houses the wafer handling automation, where the reduced footprint at least increases tool density on the fabrication facility floor and decreases pump down times of the transport chamber which may result in increased throughput. Referring now toFIGS.17and30, an exemplary control of the array of electromagnets1700will be described where dynamic phase allocation is employed. As described herein, the controller199(which in one aspect is a clustered or master controller as described herein—seeFIG.39) is operably coupled to the array of electromagnets1700and the alternating current power source1585(the power source may be any suitable type and can be direct current in which case the controller driving circuit will modulate that to desired frequency/phase for as many alternating current power phases as desired) and configured so as to sequentially excite the electromagnets1700A-1700nwith multiphase alternating current so that the base1510of a substrate handler1500is levitated and propelled with at least one of attitude control and yaw control with a common set of the electromagnets1700A-1700n(such as those electromagnets of a respective drive line177-180). As noted above, the controller199is configured to sequentially excite the electromagnets1700A-1700ncooperating in multi-phase alternating current excitation that form motor actuator units1701corresponding to the position of the base1510sensed by the sensor2000. The number n (an integer in the example of three or more, though in other aspects may be two or more) of electromagnets1700A-1700nof each motor actuator unit1701as well as the location (static) of the respective n electromagnets1700A-1700nof each motor actuator unit1701are dynamically selectable by the controller199in effecting lift and propulsion of the base (secondary)1510at any given time throughout operation of the motor actuator. Each of the electromagnets1700A-1700ngenerates, from excitation with common multiphase alternating current having a single common frequency per phase, both the separately controllable levitation and the propulsion forces against the base1510so as to control the base1510with up to six independent degrees of freedom including at least one of attitude and yaw at least with the base1510levitated. The common single frequency per phase of each phase (here respective phases A, B, C) may be selectably variable from different desired excitation frequencies so that levitation and propulsion forces generated by the motor actuation unit1701enable substantially independent control of the base1510in each of the up to six independent degrees of freedom. In one aspect, the controller199controls the roll, pitch, and yaw angles generated by the array of electromagnets1700A-1700narranged in the respective motor actuator units1701, including at least the attitude with the base1510levitated and propelled so as to move relative to the array of electromagnets1700along the at least one drive line177-180from a first predetermined position P1(seeFIG.1B) with respect to the frame of the chamber118to a second different predetermined position P2(seeFIG.1B) with respect to the frame of the chamber118. In one aspect, the controller199controls the roll, pitch, and yaw angles generated by the array of electromagnets1700, including at least the base1510attitude and the base1510yaw with the base1510levitated and stationary relative to the array of electromagnets1700in a predetermined position (such as position P2inFIG.1B) along the at least one drive line177-180with respect to the frame of the chamber118. FIGS.32A and32Billustrate an example where each electromagnet (or coil unit)1700A-1700ngrouped so as to define a motor actuator unit1701having dynamically selected number of electromagnets, for example three electromagnets (n=3) and three corresponding phases (m==3) with an electrical angle between the phases of 120° (see alsoFIG.17) also dynamically associated with the three different phases A, B, C so that association of each phase A, B, C with the corresponding static electromagnet1700A1700ncomports with the dynamic state of the motor actuation unit1701. Accordingly, with the electromagnets of the motor actuator unit.1701propelling the base1510(e.g., along direction3100) each phase A, B, C respectively changes or moves from one static electromagnet to another (i.e., rolling the designation or allocation of the respective phases to consecutive electromagnets1700A-1700nso as to generate a virtual (motion) multi-phase actuator unit3000,3000tP1,3000tP2of each of the linear electrical machine1599and the electrical machine1599R proceeding in the direction of motion3100commensurate with motion of the base1510generated by the excitation of the electromagnets1700A-1700ncorresponding to the virtual motion multi-phase actuation unit3000,3000tP1,3000tP2. This dynamic relationship or association producing the virtual motion multi-phase actuator unit3000,3000tP1,3000tP2between coil units and phase will be referred to here for convenience as “dynamic phase allocation” wherein the virtual motion of the representative virtual motion multi-phase actuator unit3000,3000tP1,3000tP2effecting propulsion of the base1510is illustrated schematically inFIG.30(see alsoFIG.17). Here the virtual motion multi-phase actuator unit (or “MAU” inFIG.17)3000has dynamically selected three electromagnets and associated phases A, B, C, shown in an initial (representative) position P=0 at time t=t0. The respective excitation of the virtual motion multi-phase actuator unit3000electromagnets generate propulsion forces that move the platen/base1510between t1 and t2 (see alsoFIGS.32A-32B). Here, as shown, at P=0 and t=t0, electromagnets1700A-1700C are grouped to form virtual motion multi-phase actuator unit3000, and are respectively, associated with phases A, B, C. Coincident with generation of propulsion forces Fx, respective excitation of virtual motion multi-phase actuator unit3000electromagnets1700A-1700C generate separately controllable lift forces Fy with a controlled variable height relative to the platen/base1510, that simultaneously lifts and effect tilt adjustment of the platen/base1510simultaneously with propulsion (seeFIGS.32A-32B). As may be realized, under effect of the lift Fy and propulsion Fx forces imparted by the respective electromagnets1700A-1700C of the virtual motion multi-phase actuator unit3000at time t=t0 and position P=0 the platen/base1510moves (relative to the transfer chamber and hence the static electromagnets1700A-1700C) with a predetermined lift and tilt. To maintain steady state tilt of the platen/base1510during motion away from the group of electromagnets1700A-1700C (defining virtual motion multi phase actuator unit3000at P=0 and T=T0) the controller199and circuitry3050, of the respective electromagnets of the electromagnet array1700A-1700n, are configured to dynamically “move” (or “change”) the allocation of the respective phases A, B, C (from the initial virtual motion multi-phase actuator unit3000at P=0 and t=t0) commensurate with the travel of the platen/base1510at time t=t1 and position P=1 to corresponding electromagnets1700B-1700D that now define virtual motion multi-phase actuator unit3000tP1disposed at position P=1 at time t=t1, and subsequently allocation of the respective phases A, B, C (from the virtual motion multi-phase actuator unit3000tP1at P=1 and t=t1) commensurate with the travel of the platen/base1510at time t=t2 and position P=2 to corresponding electromagnets1700C-1700E that now define virtual motion multi-phase actuator unit3000tP2disposed at position P=2 at time t=t2, and so on. Dynamic phase allocation is repeated throughout platen/base1510motion so that the phase distribution with respect to the platen, and excitation by respective phases (here A, B, C) of the platen/base1510remain substantially steady state throughout motion of the platen/base1510. The virtual multi-phase actuator unit3000,3000tP1,3000tP2may comprise a series of electromagnets1700A-1700nof the array of electromagnets1700coupled to at least the multiphase alternating current power source1585that define at least one drive line177-180within the drive plane1598, where electromagnets1700A-1700nin the series of electromagnets1700A-1700nare dynamically grouped into at least one multiphase actuator unit DLIM1, DLIM2, DLIM3, and each of the at least one multiphase actuator unit DLIM1, DLIM2, DLIM3being coupled to at least the multiphase alternating current power source1585. In this case, on initiating propulsion (effecting motion of the base/secondary) by excitation of corresponding electromagnet groups of the motor actuation unit at an initial position (P=0, t=0) the definition of phases A, B, C and the associated “motors” (e.g., DLIM1, DLIM2, DLIM3) are changing in space and time (Pi, ti), as described above, in order to maintain substantially steady state force vectors FZ1, FZ2, FX1, FX2imparted on the base1510throughout the range of motion, that provide a desired substantially steady state or constant tilt orientation of the substrate handler1500throughout the range of motion. As noted herein, an exemplary actuator control system network1799configured to effect dynamic phase allocation is described with respect toFIG.17. As can be seen inFIGS.32A and32B, the dynamic phase allocation is controlled by the controller199so that the respective electromagnets1700A-1700ngrouped into corresponding motor actuation units (such as described herein) energized by the multiphase alternating current A, B, C present, with respect to the base1510(represented by the front portion3110and rear portion3111), a substantially steady state multiphase distribution across respective electromagnets1700A-1700nof the virtually moving at least one multiphase actuator unit DLIM1, DLIM2, DLIM3. It is noted that the phase currents A, B, C are illustrated within respective electromagnets1700A-1700nand the phase current distribution across the at least one multiphase actuator unit DLIM1, DLIM2, DLIM3remains constant or steady state with respect to the base1510(e.g., as an example of steady state note phase current A remains at the trailing end of the rear portion3111, phase current C remains at the leading end of the rear portion3111, and phase current B remains in the center of the rear portion3111throughout movement of the base1510and the at least one (virtually moving) multiphase actuator unit DLIM1, DLIM2, DLIM3in the direction3100). In greater detail of dynamic phase allocation,FIG.30depicts at time t1 electromagnets1700A,1700B,1700C which are respectively defined as phases A, B, C (FIGS.30and32A) which generate a spatial force vector(s) that provides separately controllable lift and propulsion forces of a predetermined substrate handler1500(i.e., a wafer handler identified by the sensors2000and selected for movement by the controller199). As the substrate handler1500moves in space (e.g., along the drive line associated with the array of electromagnets1700), at time t2 electromagnets1700B,1700C,1700D respectively become phases A, B, C (FIGS.30and32B). As the substrate handier1500continues to travel along the drive line (which in this example is in direction.3100as shown inFIGS.32A,32B, and32C), at time t3 phases A, B, C are associated with electromagnets1700C,1700D,1700E, respectively. This dynamic phase allocation effects continuous spatial and time control of the vectors that maintain propulsion, lift, and orientation of the predetermined substrate handler1500. In one aspect, the alternating current power source1585is coupled to each of the electromagnets1700A-1700nof the array of electromagnets1700through any suitable signal conditioning circuitry3050which may include current amplification power supply units3011or any other suitable signal processing. The phase A, B, C currents are transmitted to each of the local drive controllers1750A-1750nwhich, under control of or in response to instruction from, master controller1760provide a specified one of the phase currents to the respective electromagnets in the manner noted above to effect dynamic phase allocation. As described herein, the base1510(FIG.16B) of a substrate handler cooperates with the electromagnets1700A-1700nof the at least one multiphase actuator unit (FIG.32B) DLIM, DLIM2, DLIM3so that excitation of the electromagnets1700A-1700nwith alternating current generates levitation and propulsion forces against the base1510that controllably levitate and propel the base1510along the at least one drive line177-180, in a controlled attitude relative to the drive plane1598. The controller199(which in some aspects includes at least the master controller1760and any controller subordinate to the master controller such as the local drive controllers1750A-1750n; however in other aspects the controller may have any suitable configuration), is operable co d to the alternating current power source1585and the array of electromagnets1700. The alternating current power source1585may include any suitable associated circuitry3050through which the alternating current power source1585connected to the array of electromagnets1700. The alternating current power source1585is controlled by the local drive controllers or any other suitable controller such as the master controller1760. Typical control parameters for the alternating current power source comprise of signal amplitude, signal frequency, and phase shift relative to a reference coil unit. Other types of control parameters may be defined. As used herein the “phase” A, B, C as illustrated inFIG.30is similar to a particular coil in a multi-phase electrical motor; however, the each of the phase definitions (such as A, B, C inFIG.30) is not physically tied to any particular coil. As a comparison with prior art, if segmented linear induction motors with static phase allocation were to be used with their own dedicated controls, then it would be difficult to effect angle/tilt controls when the substrate handler transitions from one segment to the next.FIGS.31A and31B, illustrate this problem of maintaining pitch controls across static segmented linear induction motors.FIG.31Ashows the front portion3110and rear portion3111of a base1510or secondary with induced forces along the Z and X axes. The first motor segment (SLIM1) with phases A, B and C generate the forces Fz1and Fx1to lift and propel the rear portion3111of the base. The second motor segment (SLIM2) generates forces Fz2and Fx2for the front portion3110of the base using its respective phases A, B and C. As the base moves in direction3100, the front and rear portions3110,3111of the base will transition into the next linear induction motor segments. This is shown inFIG.31B. At this position, the rear portion3111of the base overlaps with phases B and C of SLIM1and phase A of SLIM2. At the same time, the front portion3110of the base overlaps with phases B and C of SLIM2and phase A for SLIM3. As a result, it is not possible to maintain the same required forces Fz1, Fx1, Fz2, Fx2since for instance SLIM2phases are being shared by both front and rear portions3110,3111of the base. As described before, and now referring toFIG.32Cin one aspect, controlling propulsion and levitation simultaneously and separately (so that propulsion forces and lift forces are separately controllable in full, so that control of each may be deemed independent of another though both forces are effected by excitation with common multiphase alternating current having a single common frequency per phase, the common frequency per phase is selectably variable from different desired frequencies) may be effected by a variant of the dynamic phase allocation described herein, where one or more dynamic linear motor (DLIM) may include a selectable n number of phases associated with electromagnets defining the virtual motion multi phase actuator unit, where n can be an integer larger than three. The number n of electromagnets defining the virtual motion multi-phase actuator unit may be dynamically selected, for example, for effecting different moves of the platen/base1510depending on kinematic characteristics of the desired move. Here the excitation frequency commonly applied per phase of the virtual motion multi-phase actuator unit is selected by the controller199so as to generate desired kinematic performance and control of the platen/base1510. Here, the phase control algorithm maintains the same electrical phase angle difference between the phases (e.g., electromagnets of the motor, as shown inFIG.32C. The electrical phase difference is calculated relative to a reference phase or relative to each phase. The electrical phase angle difference φ between phases may range from about −180 degrees to about 180 degrees, where a value of about 0 degrees corresponds to no propulsion force, while positive and negative values provide for propulsion forces in positive and negative direction, respectively. Depending on the value of the electrical phase angle difference m the number of electromagnets within a respective dynamic linear motor varies. Here, the boundary between DLIM1(illustrated for exemplary purposes with 6 electromagnets) and DLIM2as shown inFIG.32Cis dynamic. In another aspect of the dynamic linear motor electromagnet/phase allocation, not all electromagnets of dynamic linear motor need to be energized at the same time. Referring to DLIM1, only m (in this example m=4) electromagnets out of all n (in this example n=6) electromagnets of dynamic linear motor DLIM1(where m is the number of electromagnets covered by the base (or secondary)) are energized to effect lift and propulsion of the base1510, while the other electromagnets of the n electromagnets of the dynamic linear motor DLIM1can be turned off. Referring now to, for example,FIGS.1A-11,15A-15C,17,28,29, and41an exemplary method for a linear electrical machine1599will be described in accordance with one or more aspects of the disclosed embodiment. In the method the linear electrical machine1599is provided with a frame (FIG.41, Block4100), where the frame has a level reference plane1299. A drive plane1598is formed (FIG.41, Block4110) with an array of electromagnets1700connected to the frame. The drive plane1598is located at a predetermined height H relative to the level reference plane1299. The array of electromagnets1700being arranged so that a series of electromagnets of the array of electromagnets define at least one drive line177,178within the drive plane1598, and each of the electromagnets1700A-1700n(seeFIG.15B) being coupled to an alternating current (AC) power source1585energizing each electromagnet1700A-1700n. At least one reaction platen1510is provided (FIG.41, Block4120) where the at least one reaction platen1510is of paramagnetic, diamagnetic, or non-magnetic conductive material disposed to cooperate with the electromagnets1700A-1700nof the array of electromagnets1700. The electromagnets1700A-1700nare excited with alternating current to generate levitation and propulsion forces FZ, FP (FIG.41, Block4130) against the reaction platen1510that controllably levitate and propel the reaction platen1510along the at least one drive line, in a controlled attitude relative to the drive plane1598. In the method for the linear electric machine1599the electromagnets1700A-1700nare sequentially excited, with a controller199operably coupled to the array of electromagnets1700and the alternating current power source1585, with multiphase alternating current so that each reaction platen1510is levitated and propelled with up to six degrees of freedom including at least one of attitude control and yaw control with a common set of the electromagnets1700A-1700n, each of which generates, from excitation with common multiphase alternating current having a single common frequency per phase, both the levitation and the propulsion forces FZ, FP against the reaction platen1510so as to control the reaction platen1510with up to six degrees of freedom including at least one of reaction platen attitude and reaction platen yaw at least with the reaction platen1510levitated. Referring now to, for example,FIGS.1A-11,15A15C,17,28,29,30, and42, a method for an electromagnetic conveyor substrate transport apparatus1599will be described in accordance with one or more aspects of the disclosed embodiment. In the method the electromagnetic conveyor substrate transport apparatus1599is provided with a chamber118(FIG.42, Block4200) configured to hold a sealed atmosphere therein, and having a level reference plane1299and at least one substrate pass through opening1180for transferring a substrate in and out of the chamber118through the opening1180. A drive plane1598is formed (FIG.42, Block4210) with an array of electromagnets1700connected to the chamber118. The drive plane1598is located at a predetermined height H relative to the level reference plane1299. The array of electromagnets1700being arranged so that a series of electromagnets1700A-1700nof the array of electromagnets1700define at least one drive line177,178within the drive plane1598, electromagnets1700A-1700nin the series of electromagnets1700A-1700nbeing grouped into at least one multiphase actuator unit, and each of the at least one multiphase actuator unit being coupled to a multiphase alternating current (AC) power source1585. At least one reaction platen1510is provided (FIG.42, Block4220) where the at least one reaction platen1510is of paramagnetic, diamagnetic, or non-magnetic conductive material disposed to cooperate with the electromagnets1700A-1700nof the at least one multiphase actuator unit. The electromagnets1700A-1700nare excited with alternating current to generate levitation and propulsion forces FZ, FP (FIG.42, Block4230) against the reaction platen1510that controllably levitate and propel the reaction platen1510along the at least one drive line177,178, in a controlled attitude relative to the drive plane1598. The electromagnets1700A-1700nare sequentially excited, with a controller199operably coupled to the array of electromagnets1700and alternating current power source1585, with multiphase alternating current so that a reaction platen1510is levitated and propelled, wherein each alternating current phase, of the multiphase alternating current, is dynamically allocated between respective electromagnets1700A-1700nso that the alternating current phase of each respective electromagnet1700A-1700n, of the electromagnet group of the at least one multiphase actuator unit, changes from a first alternating current phase to a second different alternating current phase so in effect the electromagnet group moves virtually and the at least one multiphase actuator unit formed by the electromagnet group moves virtually via dynamic phase allocation along the drive line177,178. In accordance with one or more aspects of the disclosed embodiment a linear electrical machine comprises:a frame with a level reference plane;an array of electromagnets, connected to the frame to form a drive plane at a predetermined height relative to the level reference plane, the array of electromagnets being arranged so that a series of electromagnets of the array of electromagnets define at least one drive line within the drive plane, and each of the electromagnets being coupled to an alternating current power source energizing each electromagnet;at least one reaction platen of paramagnetic, diamagnetic, or non-magnetic conductive material disposed to cooperate with the electromagnets of the array of electromagnets so that excitation of the electromagnets with alternating current generates levitation and propulsion forces against the reaction platen that controllably levitate and propel the reaction platen along the at least one drive line, in a controlled attitude relative to the drive plane; anda controller operably coupled to the array of electromagnets and the alternating current power source and configured so as to sequentially excite the electromagnets with multiphase alternating current so that each reaction platen is levitated and propelled with up to six degrees of freedom including at least one of attitude control and yaw control with a common set of the electromagnets, each of which generates, from excitation with common multiphase alternating current having a single common frequency per phase, both the levitation and the propulsion forces against the reaction platen so as to control the reaction platen with up to six degrees of freedom including at least one of reaction platen attitude and reaction platen yaw at least with the reaction platen levitated. In accordance with one or more aspects of the disclosed embodiment the controller controls the up to six degrees of freedom, generated by the array of electromagnets, including at least the reaction platen attitude with the reaction platen levitated and propelled so as to move relative to the array of electromagnets along the at least one drive line from a first predetermined position with respect to the frame to a second different predetermined position with respect to the frame. In accordance with one or more aspects of the disclosed embodiment the controller controls the up to six degrees of freedom, generated by the array of electromagnets, including at least the reaction platen attitude and the reaction platen yaw with the reaction platen levitated and stationary relative to the array of electromagnets in a predetermined position along the at least one drive line with respect to the frame. In accordance with one or more aspects of the disclosed embodiment the controller controls the propulsion forces, generated by the array of electromagnets, across the reaction platen so as to impart a controlled yaw moment on the reaction platen, yawing the reaction platen about a yaw axis, substantially normal to the drive plane, from a first predetermined orientation relative to the frame, to a second different predetermined orientation relative to the frame. In accordance with one or more aspects of the disclosed embodiment the controller controls the propulsion forces, generated by the array of electromagnets, so as to impart a moment couple on the reaction platen effecting controlled yaw of the reaction platen so as to effect at least one of positioning and centering of a wafer payload on the reaction platen relative to a predetermined wafer holding location of the frame. In accordance with one or more aspects of the disclosed embodiment the controller controls the levitation forces, generated by the array of electromagnets, so as to impart differential levitation forces across the reaction platen that effect a controlled inclination of the reaction platen, relative to the drive plane, that controls a predetermined reaction platen attitude in at least one of reaction platen pitch and reaction platen roll. In accordance with one or more aspects of the disclosed embodiment the controller controls the levitation forces, generated by the array of electromagnets, so as to effect a predetermined bias attitude of the reaction platen, relative to the drive plane, that imparts a bias reaction force, from a reaction platen payload seating surface on a payload supported by the reaction platen seating surface, in a direction countering payload inertial force arising from acceleration of the reaction platen along the drive plane. In accordance with one or more aspects of the disclosed embodiment the linear electrical machine further comprises position feedback sensors distributed on the frame configured for sensing position of the reaction platen along the drive plane and communicably coupled to the controller so the controller registers the sensed position of the reaction platen, wherein the controller is configured to sequentially excite the electromagnets of the array of electromagnets corresponding to the sensed position. In accordance with one or more aspects of the disclosed embodiment the controller is configured to determine acceleration of the reaction platen along the drive plane at least from changes in the sensed position, and in response to the acceleration determined, control a bias attitude of the reaction platen to provide the predetermined bias attitude countering the payload inertial force arising from the acceleration of the reaction platen. In accordance with one or more aspects of the disclosed embodiment the controller controls excitation of the electromagnets of the array of electromagnets so as to set the reaction platen attitude to bias the reaction platen against inertial forces tending to displace a payload, seated against the reaction platen, relative to the reaction platen along a seat between the payload and the reaction platen. In accordance with one or more aspects of the disclosed embodiment an electromagnetic conveyor substrate transport apparatus comprises:a chamber configured to hold a sealed atmosphere therein, and having a level reference plane and at least one substrate pass through opening for transferring a substrate in and out of the chamber through the opening;an array of electromagnets, connected to the chamber to form a drive plane at a predetermined height relative to the level reference plane, the array of electromagnets being arranged so that a series of electromagnets of the array of electromagnets define at least one drive line within the drive plane, electromagnets in the series of electromagnets being grouped into at least one multiphase actuator unit, and each of the at least one multiphase actuator unit being coupled to a multiphase alternating current power source;at least one reaction platen of paramagnetic, diamagnetic, or non-magnetic conductive material disposed to cooperate with the electromagnets of the at least one multiphase actuator unit so that excitation of the electromagnets with alternating current generates levitation and propulsion forces against the reaction platen that controllably levitate and propel the reaction platen along the at least one drive line, in a controlled attitude relative to the drive plane; anda controller operably coupled to the array of electromagnets and alternating current power source and configured so as to sequentially excite the electromagnets with multiphase alternating current so that a reaction platen is levitated and propelled, wherein each alternating current phase, of the multiphase alternating current, is dynamically allocated between respective electromagnets so that the alternating current phase of each respective electromagnet, of the electromagnet group of the at least one multiphase actuator unit, changes from a first alternating current phase to a second different alternating current phase so in effect the electromagnet group moves virtually and the at least one multiphase actuator unit formed by the electromagnet group moves virtually via dynamic phase allocation along the drive line. In accordance with one or more aspects of the disclosed embodiment the reaction platen is levitated and propelled with up to six degrees of freedom including at least one of attitude and yaw control with the virtually moving at least one multiphase actuator unit. In accordance with one or more aspects of the disclosed embodiment the controller controls the up to six degrees of freedom, generated by the array of electromagnets, including at least the reaction platen attitude with the reaction platen levitated and propelled so as to move relative to the array of electromagnets along the at least one drive line from a first predetermined position with respect to the chamber to a second different predetermined position with respect to the chamber. In accordance with one or more aspects of the disclosed embodiment the controller controls the up to six degrees of freedom, generated by the array of electromagnets, including at least the reaction platen attitude and the reaction platen yaw with the reaction platen levitated and stationary relative to the array of electromagnets in a predetermined position along the at least one drive line with respect to the chamber. In accordance with one or more aspects of the disclosed embodiment the dynamic phase allocation is controlled so that the virtually moving at least one multiphase actuator unit moves virtually along the drive line substantially coincident with reaction platen movement along the drive line from propulsion by the virtually moving at least one multiphase actuator unit. In accordance with one or more aspects of the disclosed embodiment the controller controls the propulsion forces, generated by the array of electromagnets, across the reaction platen so as to impart a controlled yaw moment on the reaction platen, yawing the reaction platen about a yaw axis, substantially normal to the drive plane, from a first predetermined orientation relative to the chamber, to a second different predetermined orientation relative to the chamber. In accordance with one or more aspects of the disclosed embodiment the controller controls the propulsion forces, generated by the array of electromagnets, so as to impart a moment couple on the reaction platen effecting controlled yaw of the reaction platen so as to effect at least one of positioning and centering of a wafer payload on the reaction platen relative to a predetermined wafer holding location of the chamber. In accordance with one or more aspects of the disclosed embodiment the controller controls the levitation forces, generated by the array of electromagnets, so as to impart differential levitation forces across the reaction platen that effect a controlled inclination of the reaction platen, relative to the drive plane, that controls a predetermined reaction platen attitude in at least one of reaction platen pitch and reaction platen roll. In accordance with one or more aspects of the disclosed embodiment the controller controls the levitation forces, generated by the array of electromagnets, so as to effect a predetermined bias attitude of the reaction platen, relative to the drive plane, that imparts a bias reaction force, from a reaction platen payload seating surface on a payload supported by the reaction platen seating surface, in a direction countering payload inertial force arising from acceleration of the reaction platen along the drive plane. In accordance with one or more aspects of the disclosed embodiment the electromagnetic conveyor substrate transport apparatus further comprises position feedback sensors distributed on the chamber configured for sensing position of the reaction platen along the drive plane and communicably coupled to the controller so the controller registers the sensed position of the reaction platen, wherein the controller is configured to sequentially excite the electromagnets of the array of electromagnets corresponding to the sensed position. In accordance with one or more aspects of the disclosed embodiment the controller is configured to determine acceleration of the reaction platen along the drive plane at least from changes in the sensed position, and in response to the acceleration determined, control a bias attitude of the reaction platen to provide the predetermined bias attitude countering the payload inertial force arising from the acceleration of the reaction platen. In accordance with one or more aspects of the disclosed embodiment the controller controls excitation of the electromagnets of the array of electromagnets so as to set the reaction platen attitude to bias the reaction platen against inertial forces tending to displace a payload, seated against the reaction platen, relative to the reaction platen along a seat between the payload and the reaction platen. In accordance with one or more aspects of the disclosed embodiment the dynamic phase allocation is controlled so that the respective electromagnets energized by the multiphase alternating current present, with respect to the reaction platen, a substantially steady state multiphase distribution across respective electromagnets of the virtually moving at least one multiphase actuator unit. In accordance with one or more aspects of the disclosed embodiment method for a linear electrical machine is provided. The method comprises:providing the linear electrical machine with a frame, the frame having a level reference plane;forming a drive plane with an array of electromagnets connected to the frame, the drive plane is located at a predetermined height relative to the level reference plane, the array of electromagnets being arranged so that a series of electromagnets of the array of electromagnets define at least one drive line within the drive plane, and each of the electromagnets being coupled to an alternating current power source energizing each electromagnet;providing at least one reaction platen of paramagnetic, diamagnetic, or non-magnetic conductive material disposed to cooperate with the electromagnets of the array of electromagnets; andexciting the electromagnets with alternating current to generate levitation and propulsion forces against the reaction platen that controllably levitate and propel the reaction platen along the at least one drive line, in a controlled attitude relative to the drive plane;wherein the electromagnets are sequentially excited, with a controller operably coupled to the array of electromagnets and the alternating current power source, with multiphase alternating current so that each reaction platen is levitated and propelled with up to six degrees of freedom including at least one of attitude control and yaw control with a common set of the electromagnets, each of which generates, from excitation with common multiphase alternating current having a single common frequency per phase, both the levitation and the propulsion forces against the reaction platen so as to control the reaction platen with up to six degrees of freedom including at least one of reaction platen attitude and reaction platen yaw at least with the reaction platen levitated. In accordance with one or more aspects of the disclosed embodiment the controller controls the up to six degrees of freedom, generated by the array of electromagnets, including at least the reaction platen attitude with the reaction platen levitated and propelled so as to move relative to the array of electromagnets along the at least one drive line from a first predetermined position with respect to the frame to a second different predetermined position with respect to the frame. In accordance with one or more aspects of the disclosed embodiment the controller controls the up to six degrees of freedom, generated by the array of electromagnets, including at least the reaction platen attitude and the reaction platen yaw with the reaction platen levitated and stationary relative to the array of electromagnets in a predetermined position along the at least one drive line with respect to the frame. In accordance with one or more aspects of the disclosed embodiment the controller controls the propulsion forces, generated by the array of electromagnets, across the reaction platen so as to impart a controlled yaw moment on the reaction platen, yawing the reaction platen about a yaw axis, substantially normal to the drive plane, from a first predetermined orientation relative to the frame, to a second different predetermined orientation relative to the frame. In accordance with one or more aspects of the disclosed embodiment the controller controls the propulsion forces, generated by the array of electromagnets, so as to impart a moment couple on the reaction platen effecting controlled yaw of the reaction platen so as to effect at least one of positioning and centering of a wafer payload on the reaction platen relative to a predetermined wafer holding location of the frame. In accordance with one or more aspects of the disclosed embodiment the controller controls the levitation forces, generated by the array of electromagnets, so as to impart differential levitation forces across the reaction platen that effect a controlled inclination of the reaction platen, relative to the drive plane, that controls a predetermined reaction platen attitude in at least one of reaction platen pitch and reaction platen roll. In accordance with one or more aspects of the disclosed embodiment the controller controls the levitation forces, generated by the array of electromagnets, so as to effect a predetermined bias attitude of the reaction platen, relative to the drive plane, that imparts a bias reaction force, from a reaction platen payload seating surface on a payload supported by the reaction platen seating surface, in a direction countering payload inertial force arising from acceleration of the reaction platen along the drive plane. In accordance with one or more aspects of the disclosed embodiment method further comprises sensing, with position feedback sensors distributed on the frame, position of the reaction platen along the drive plane and communicably coupled to the controller so the controller registers the sensed position of the reaction platen, wherein the controller sequentially excites the electromagnets of the array of electromagnets corresponding to the sensed position. In accordance with one or more aspects of the disclosed embodiment the controller determines acceleration of the reaction platen along the drive plane at least from changes in the sensed position, and in response to the acceleration determined, control a bias attitude of the reaction platen to provide the predetermined bias attitude countering the payload inertial force arising from the acceleration of the reaction platen. In accordance with one or more aspects of the disclosed embodiment the controller controls excitation of the electromagnets of the array of electromagnets so as to set the reaction platen attitude to bias the reaction platen against inertial forces tending to displace a payload, seated against the reaction platen, relative to the reaction platen along a seat between the payload and the reaction platen. In accordance with one or more aspects of the disclosed embodiment a method for an electromagnetic conveyor substrate transport apparatus is provided. The method comprises:providing the electromagnetic conveyor substrate transport apparatus with a chamber configured to hold a sealed atmosphere therein, and having a level reference plane and at least one substrate pass through opening for transferring a substrate in and out of the chamber through the opening;forming a drive plane with an array of electromagnets connected to the chamber, the drive plane is located at a predetermined height relative to the level reference plane, the array of electromagnets being arranged so that a series of electromagnets of the array of electromagnets define at least one drive line within the drive plane, electromagnets in the series of electromagnets being grouped into at least one multiphase actuator unit, and each of the at least one multiphase actuator unit being coupled to a multiphase alternating current power source;providing at least one reaction platen of paramagnetic, diamagnetic, or non-magnetic conductive material disposed to cooperate with the electromagnets of the at least one multiphase actuator unit; andexciting the electromagnets with alternating current to generate levitation and propulsion forces against the reaction platen that controllably levitate and propel the reaction platen along the at least one drive line, in a controlled attitude relative to the drive plane;wherein the electromagnets are sequentially excited, with a controller operably coupled to the array of electromagnets and alternating current power source, with multiphase alternating current so that a reaction platen is levitated and propelled, wherein each alternating current phase, of the multiphase alternating current, is dynamically allocated between respective electromagnets so that the alternating current phase of each respective electromagnet, of the electromagnet group of the at least one multiphase actuator unit, changes from a first alternating current phase to a second different alternating current phase so in effect the electromagnet group moves virtually and the at least one multiphase actuator unit formed by the electromagnet group moves virtually via dynamic phase allocation along the drive line. In accordance with one or more aspects of the disclosed embodiment the reaction platen is levitated and propelled with up to six degrees of freedom including at least one of attitude and yaw control with the virtually moving at least one multiphase actuator unit. In accordance with one or more aspects of the disclosed embodiment the controller controls the up to six degrees of freedom, generated by the array of electromagnets, including at least the reaction platen attitude with the reaction platen levitated and propelled so as to move relative to the array of electromagnets along the at least one drive line from a first predetermined position with respect to the chamber to a second different predetermined position with respect to the chamber. In accordance with one or more aspects of the disclosed embodiment the controller controls the up to six degrees of freedom, generated by the array of electromagnets, including at least the reaction platen attitude and the reaction platen yaw with the reaction platen levitated and stationary relative to the array of electromagnets in a predetermined position along the at least one drive line with respect to the chamber. In accordance with one or more aspects of the disclosed embodiment the dynamic phase allocation is controlled so that the virtually moving at least one multiphase actuator unit moves virtually along the drive line substantially coincident with reaction platen movement along the drive line from propulsion by the virtually moving at least one multiphase actuator unit. In accordance with one or more aspects of the disclosed embodiment the controller controls the propulsion forces, generated by the array of electromagnets, across the reaction platen so as to impart a controlled yaw moment on the reaction platen, yawing the reaction platen about a yaw axis, substantially normal to the drive plane, from a first predetermined orientation relative to the chamber, to a second different predetermined orientation relative to the chamber. In accordance with one or more aspects of the disclosed embodiment the controller controls the propulsion forces, generated by the array of electromagnets, so as to impart a moment couple on the reaction platen effecting controlled yaw of the reaction platen so as to effect at least one of positioning and centering of a wafer payload on the reaction platen relative to a predetermined wafer holding location of the chamber. In accordance with one or more aspects of the disclosed embodiment the controller controls the levitation forces, generated by the array of electromagnets, so as to impart differential levitation forces across the reaction platen that effect a controlled inclination of the reaction platen, relative to the drive plane, that controls a predetermined reaction platen attitude in at least one of reaction platen pitch and reaction platen roll. In accordance with one or more aspects of the disclosed embodiment the controller controls the levitation forces, generated by the array of electromagnets, so as to effect a predetermined bias attitude of the reaction platen, relative to the drive plane, that imparts a bias reaction force, from a reaction platen payload seating surface on a payload supported by the reaction platen seating surface, in a direction countering payload inertial force arising from acceleration of the reaction platen along the drive plane. In accordance with one or more aspects of the disclosed embodiment the method further comprises sensing, with the position feedback sensors distributed on the chamber, position of the reaction platen along the drive plane and communicably coupled to the controller so the controller registers the sensed position of the reaction platen, wherein the controller is configured to sequentially excite the electromagnets of the array of electromagnets corresponding to the sensed position. In accordance with one or more aspects of the disclosed embodiment the controller determines acceleration of the reaction platen along the drive plane at least from changes in the sensed position, and in response to the acceleration determined, control a bias attitude of the reaction platen to provide the predetermined bias attitude countering the payload inertial force arising from the acceleration of the reaction platen. In accordance with one or more aspects of the disclosed embodiment the controller controls excitation of the electromagnets of the array of electromagnets so as to set the reaction platen attitude to bias the reaction platen against inertial forces tending to displace a payload, seated against the reaction platen, relative to the reaction platen along a seat between the payload and the reaction platen. In accordance with one or more aspects of the disclosed embodiment the dynamic phase allocation is controlled so that the respective electromagnets energized by the multiphase alternating current present, with respect to the reaction platen, a substantially steady state multiphase distribution across respective electromagnets of the virtually moving at least one multiphase actuator unit. It should be understood that the foregoing description is only illustrative of the aspects of the disclosed embodiment. Various alternatives and modifications can be devised by those skilled in the art without departing from the aspects of the disclosed embodiment. Accordingly, the aspects of the disclosed embodiment are intended to embrace all such alternatives, modifications and variances that fall within the scope of any claims appended hereto. Further, the mere fact that different features are recited in mutually different dependent or independent claims does not indicate that a combination of these features cannot be advantageously used, such a combination remaining within the scope of the aspects of the present disclosure. | 147,214 |
11862499 | DETAILED DESCRIPTION The implementations disclosed herein provide for an integrated sensor controller for precision optical detection of substrate positioning while the substrates are being transferred to or between processing chambers (which may include deposition chambers, etching chambers, plasma chambers, and so on). For example, the implementations disclosed helps to accurately determine positioning of a substrate on a robot blade and provide data for a controller of the robot blade to correct or compensate for a misplacement of the substrate before the substrate is delivered to a destination location. The robotic systems allow a quick and efficient delivery of substrates for processing into processing chambers and an automated retrieval of the processed substrates from the processing chambers. Robotic delivery/retrieval systems greatly increase a yield of the manufacturing process but pose some specific quality control challenges. As the substrate is being picked up (e.g., from a substrate carrier, such as a front opening unified port) by the robot blade and transported through a factory (front-end) interface, load-lock chamber, transfer chamber, etc., to one of the processing chambers of a device manufacturing machine, the substrate's position on the blade may be different from an ideal location relative to the blade and may lead to an incorrect positioning of the substrate delivered into the processing chamber. This may result in sub-standard physical and/or chemical properties of the eventual product (e.g., an incorrect placement of dopants on the substrate, a non-uniform thickness of a film deposited on the surface of the substrate, and the like). To improve quality of the product yield, a system of optical sensors connected to a microcontroller may be used so that exact moments of time when the substrate (or its edge) arrives at a specific point in space are determined. Based on a difference between the actual arrival time and an (ideal) reference arrival time, for a number of such specific points in space, the microcontroller can determine the actual position (e.g., shift and angular misalignment) of the substrate on the robot blade. Subsequently, a blade control module can determine what corrective action (e.g., a compensating change of the blade's trajectory) may be performed to compensate for the error in the substrate positioning. In one embodiment, the optical sensors operate by outputting a light signal and detecting a precise moment of time when an event associated with the output light occurs. Such an event may be an instance when the output light is reflected off the arrived substrate and into a detector of light, in some implementations. In other implementations, the output light may be continuously incident on the detector but occluded by the arrived substrate, and so on. The light output by a sensor and detected by a light detector may undergo processing by an optical amplifier. In existing implementations, a dedicated amplifier is typically associated with each separate sensor. Each amplifier may, therefore, require separate tuning and maintenance. This increases costs of optical detectors. Each separate optical amplifier circuit (and an associated optical path of the optical signal) may have its own detection delay time (the time it takes for optical and electric circuits to detect and process the event) or even its own distribution of delay times. The distributions for each amplifier circuit may be centered at different values of the delay time and may have different widths. In various devices the resulting overall distribution of delay times may be rather broad, e.g., 30 microseconds, or even more. Aspects and implementations of the present disclosure address this and other technological shortcomings by improving tunability, consistency, and accuracy of the optical sensing technology used in substrate processing. Described herein is an integrated optical sensing controller in which an optical amplifier, as well as other optical circuitry (e.g., a light emitting diode (LED) driver, one or more optical (de)multiplexers, an analog-to-digital converter, etc.), is able to support multiple optical sensors. Further disclosed is software-implemented configurability of the optical circuitry using a microcontroller integrated with the optical circuitry. Such integrated—into a single assembly—optical circuits, analog electronics and digital electronics reduce system costs, improve accuracy of optical sensing and allow real time software control. This alleviates or eliminates manual calibration and maintenance of the optical amplifiers in the conventional sensing devices which feature separate amplifiers serving separate sensors. FIG.1illustrates one exemplary implementation of a manufacturing machine100capable of supporting accurate optical sensing of substrates112transported on a moving blade into a processing chamber106(as schematically depicted with the substrate's position in chamber116) and/or out of a processing chamber106. Embodiments described with regards to optical sensing of substrates entering or leaving a processing chamber also apply to optical sensing of substrates entering or leaving a loading station (e.g., load lock) and/or other station. In one implementation, the manufacturing machine100includes a loading station102, a transfer chamber104, and one or more processing chambers106. The processing chamber(s)106are interfaced to the transfer chamber104via transfer ports (not shown) in some embodiments. The number of processing chamber(s) associated with the transfer chamber104may vary (with three processing chambers indicated inFIG.1, as a way of example). Additionally, the design and shape of the transfer chamber104may vary. In the illustrated embodiment, the transfer chamber104has a hexagonal shape with each side being of approximately equal width. In other embodiments, the transfer chamber104may have four, five, seven, eight, or more sides. Additionally, different sides may have different widths or lengths. For example, the transfer chamber104may have four sides and be of rectangular shape or of square shape. In another example, the transfer chamber may have five sides and be of a wedge shape. As shown, each side of the transfer chamber104is connected to a single processing chamber106. However, in other implementations one or more of the sides may be connected to multiple processing chambers. For example, a first side may be connected to two processing chambers, and a second side may be connected to one processing chamber. Substrate112can be a silicon wafer (e.g., a crystalline or amorphous silicon wafer), a glass wafer, a film or a stack of films, a wafer package, such as a thinned wafer on a carrier, and the like. In some implementations, substrate112can be a process kit component, e.g., an edge ring or any other replaceable component of the manufacturing machine. Substrate112can be a diagnostic device, such as an optical inspection tool, introduced into a processing chamber (a load-lock chamber, or any other part of the manufacturing machine) for inspection, replacement, and/or maintenance. The transfer chamber104includes a robot108, a robot blade110, and an optical sensing tool for accurate optical sensing of a positioning of a substrate112that is being transported by the robot blade110for processing in one of the processing chambers106. An optical sensing tool may additionally or alternatively be positioned for optical sensing of a positioning of a substrate112that is being transported by the robot blade110into or out of loading station102and/or other processing chambers106. The transfer chamber104may be held under pressure that is higher or lower than atmospheric pressure. For example, the transfer chamber104may be maintained under vacuum. Additionally, or alternatively, the transfer chamber104may be maintained at an elevated temperature in some embodiments. The robot blade110may be attached to an extendable arm sufficient to move the robot blade110into the processing chamber106to deliver the substrate to the chamber prior to processing and to retrieve the substrate from the chamber after the processing is complete. The robot blade110is configured to enter the processing chamber(s)106through a slit valve port (not shown) while a lid to the processing chamber(s)106remains closed. The processing chamber(s)106may contain processing gases, plasma, and various particles used in deposition processes. A magnetic field may exist inside the processing chamber(s)106. The inside of the processing chamber(s)106may be held at temperatures and pressures that are different from the temperature and pressure outside the processing chamber(s)106. The manufacturing machine100includes an integrated sensor controller (ISC)150, which may be coupled to multiple sensors114. Each sensor114includes a sensor head to output a light signal. In some implementations, the sensor heads include light-emitting diodes (LEDs). In some implementations, the sensor heads are ends of optical fibers that deliver light generated elsewhere, e.g., inside the ISC150. Each sensor114includes a light detector to detect light output by the respective sensor head. In some implementations, the light detectors are optical detectors configured to deliver received (RX) optical signals to ISC150. For example, some or each of the optical detectors may be ends of optical fibers connected to ISC150. In other implementations, the light detectors are photoemission detectors configured to deliver electric signals to ISC150. The light delivered (TX) to optical heads may be in the visible range, infrared range, ultraviolet range, or any other range of electromagnetic radiation suitable for the task of sensing a substrate position. In some implementations, the sensors114are mounted on the door of the transfer chamber104, inside the transfer chamber104, inside of a slit valve assembly, inside of a load port, inside the loading station102, and/or inside any one of the processing chambers106. A master computing device118may control operations of the robot108and may also receive optical sensing data from ISC150, including processed information derived from the data obtained by the sensors114. In some implementations, the master computing device118reconfigures ISC150at run time. In some implementations, communication between the master computing device118and the ISC150is performed wirelessly. The master computing device118may include a blade control module120. The blade control module may be capable of correcting, based on the information obtained from the ISC150, the position of the substrate112on the robot blade110, e.g., to determine if the position is outside the tolerances of a manufacturing process. In some implementations, some of the functionality of the blade control module120is implemented as part of the ISC150. FIG.2illustrates an exemplary integrated circuit architecture200capable of providing precision optical detection of substrate positioning prior, during, or after substrate transportation to or from a processing chamber, in accordance with some implementations of the present disclosure. The integrated circuit architecture200includes a number of sensors114(numbered from114-1to114-n, wherein n is the number of sensors), sensor connectors206, a sensor circuit210, an isolation circuit220, and/or a logic circuit240. In some implementations, the sensor connectors206, the sensor circuit210, the isolation circuit220, and the logic circuit240are integrated as a single system-on-chip (SoC) sensor controller. The sensor circuit210may include one or more light source drivers212, such as LED drivers. An LED driver may regulate an amount of electric power delivered to the sensors114. The electric signals generated by the light source driver(s)212may be selectively routed to the sensors114via a block of sensor connectors206. The block of sensor connectors206are programmable by the logic circuit240and/or the master computing device118in embodiments. Specifically, the block of sensor connectors206may include a set of switches. In some implementations, the logic circuit240has a number of pre-set configurations of switches to be selected depending on the processing task being implemented, such as delivering an unprocessed substrate to a processing chamber, transferring a partially processed substrate between different processing chambers, retrieving a fully processed chamber, and the like. In some implementations, the optical drivers output optical (rather than electric) signals to the sensors114. In such implementations, the block of sensor connectors206include a set of optical connectors and switches to deliver a pre-configured amount of optical power to each (or some) of the sensors114. For example, the sensor connectors206may include one or more demultiplexers to split a driving (optical or electric) signal produced by one or more of the light source drivers212and deliver each one of the split signals to the respective sensor head. The sensor heads202-1. . .202-noutput respective optical signals (TX) in an embodiment. The light detectors204-1. . .204-nmay receive signals (RX) output by the respective sensor heads202. In some implementations, the RX signals are generated by the respective TX signals upon reflection from the surface of the substrate112. In other implementations, the RX signals are TX signals propagated (over air) from sensor heads202to light detectors204. Each of the light detectors204may be capable of detecting an event associated with propagation of light from the sensor head202. Such events may be associated with reflection of light from the substrate, termination of the TX signal detection due to occlusion by the substrate, restoration of the TX signal detection due to departure of the substrate, and so on. In some implementations, the RX signals generated by the light detectors204are optical signals. For example, the RX signals may represent an amount of light emitted through an end of a first optical fiber (sensor head202) and subsequently recaptured through an end of a second optical fiber (light detector204). In some implementations, the RX signals are electric signals generated by a photoelectric element (within a light detector204) under the influence of the incident optical TX signals. The RX signals may be received and processed by one or more amplifiers214. In some implementations, a single amplifier214receives RX signals from all sensors114. In some implementations, multiple amplifiers214receive RX signals, with some or all of the amplifiers214receiving RX signals from multiple sensors114. In those implementations, where light detectors204are photoelement-based detectors, the amplifiers214are electronic amplifiers. In those implementations where light detectors204are optical detectors, the amplifiers214are optical amplifiers. In the latter case, the sensor circuit210may include additional components to transform optical RX signals to electric signals. The amplified, by the amplifier(s)214, RX signals may be further processed by an analog-to-digital converter (ADC)216. Digital signals output by the ADC216are received by the logic circuit240in embodiments. The signals may be received by the logic circuit240via an isolation circuit220. The isolation circuit may prevent backpropagation of electric signals from the logic circuit240to the sensor circuit210and/or further to the sensors114to prevent spurious noises of the logic circuit240from affecting accuracy of optical sensing including preparation of TX signals, detecting and processing of the RX signals. The logic circuit240may perform processing of data received from the sensor circuit210as well as providing configurable functionality of the sensor circuit210. The logic circuit240may include a processing device242, e.g., a field programmable gate array (FPGA), or some other processor. The logic circuit240may further include an integrated circuit244to facilitate communication between the sensor controller150and outside computing devices, such as the master computing device118or other computing devices on the same network to which the sensor controller150may be connected. The integrated circuit244is an application-specific integrated circuit (ASIC)244in some embodiments. In some implementations, the sensor controller150communicates, via appropriate ASIC244, with the master computing device118(or other network computing devices) using an EtherCAT data exchange protocol. In some implementations, the sensor controller150communicates with the master computing device118using some other fieldbus protocols. For example, the sensor controller150may communicate, via ASIC244, with the master computing device118using AS-Interface, Interbus, Profibus, or any other suitable fieldbus protocol. The ASIC244may be configurable and may be customized to define the profile of the sensor controller150(e.g., as a node on the EtherCAT network) to determine how the sensor controller150exchanges data with the master node of the network (e.g., the master computing device118), depending on the functionality currently provided by the sensor controller150. The processing device242(e.g., an FPGA or any other processor) may include hardware (an array of logic gates and one or more memory devices) and software to set up and control operations of the sensor circuit210and sensors114. The processing device242may be fully customizable. Upon powering-up, the processing device242may implement a default configuration of the sensor circuit210, including configuring the light source drivers212and the amplifiers214. During operations of the sensor controller150, the processing device242may receive data generated by the sensors114, processed and digitized by the sensor circuit210. The processing device242may output information to the master computing device118representative of the position of the substrate112on the robot blade110. Depending on a processing task being implemented (e.g., delivery of a substrate into a specific processing chamber or transfer between specific processing chambers), the processing device242may be reconfigured during run time (“on the fly”) using various pre-set configurations stored in a memory accessible to the processing device242. For example, based on the processing task being a delivery of the substrate into a chemical vapor deposition chamber, the master computing device118may communicate (via ASIC244) to the processing device242an instruction to reconfigure the sensor controller150into a first pre-set configuration corresponding to substrate delivery to the vapor deposition chamber. As another example, at a later time, when the substrate is being transferred for processing in a plasma environment of an etching chamber, the master computing device118may communicate to the processing device242another instruction to reconfigure the sensor controller150into a second pre-set configuration corresponding to substrate delivery to the etching chamber. The sensor controller150may be equipped with a power source, which in some implementations may include a power circuit230such as an ISO DC/DC power converter. In some implementations, the power converter converts a 12V or 24V (used by the sensor circuit210) power signal into a 3.3V power signal used by the logic circuit240. In other implementations, different input and output voltages may be used. In some implementations, the power converters may be bidirectional converters. Various components shown inFIG.2, communicate via a number of communication interfaces and protocols (as indicated schematically inFIG.2), such as the synchronous serial peripheral interface (SPI) is a serial communication interface, the I2C serial bus, peripheral input/output (PIO) interface, general purpose input/output (GPIO) interface, dual-port memory interface (DPM), and so on. The integrated circuit illustrated inFIG.2is capable of generating data and providing inputs about substrates (e.g., wafers), process kits, diagnostic tools, and any other objects delivered to or already present inside various chambers of the manufacturing machine100. For example, the integrated circuit may provide various characteristics of different types of processed and unprocessed wafers, films, combinations of wafers and/or films, and the like. The characteristics can include position (including presence or absence,) size, orientation, uniformity, thickness, chemical, physical and optical properties, and the like. Additionally, the integrated circuit may provide data about a variety of algorithms for delivery and/or handling of substrates (or other objects delivered into the processing chambers). In addition to generating data to accurately place a substrate into a process chamber, the integrated circuit controller illustrated inFIG.2can be extended/adapted to provide sensor inputs to the substrate handling control system for automated substrate handling calibration, in situ substrate handling monitoring and diagnostics, and other similar functions where the sensors may detect the robot body and/or select features with vertical, horizontal, or angled beams. FIG.3illustrates an exemplary architecture of the logic circuit240of the integrated circuit architecture200capable of providing precision optical detection of substrate positioning, in accordance with some implementations of the present disclosure. The logic circuit240includes a processing device242(e.g., an FPGA) that may use various integration technologies to implement an embedded system360. The embedded system360integrates an embedded processor362in an embodiment, which may be a hard-core (e.g., ARM® SoC) or a soft-core (e.g. Nios®) processor. The embedded system360may further include an on-chip random access memory (RAM)364, a dual-ported memory366for fast memory operations, a general-purpose input-output (GPIO) module368, as well as other components not explicitly depicted (e.g., system clock). The embedded system360may be coupled to a custom logic370, a non-volatile memory372(e.g., serial flash memory or any other type of non-volatile memory), and a synchronous random-access memory (SDRAM)373. The embedded system360may be coupled to JTAG interface374for programming and debugging. Before the sensor controller150is powered up, the software for the embedded processor362and configuration files for the processing device242initially reside in the non-volatile memory372. During boot-up, the software stored in the non-volatile memory372is used to configure the processing device242to instantiate the embedded system360and custom HDL logic370. Then the embedded processor362in the embedded system360fetches the controller software from the non-volatile memory372, and starts the application logic for the embedded system360. The application and the libraries may be written to external memory, such as synchronous dynamic RAM (SDRAM)373(or the on-chip RAM364). The custom logic370may be a software component that implements application-specific functionality of the sensor controller150. The custom logic370may be written in a programming language (e.g., C or C++) and converted (using an appropriate compilator) into a hardware-description language (HDL). During operations of the sensor controller150, the data received from the sensor circuit210may be processed by the custom logic370or the embedded processor362and communicated to the master computing device118via the ASIC244. The data communicated by the custom logic370may include (but not be limited to) some of the following: indications of events associated with the TX and/or RX output/detected by sensors114(e.g., arrival or departure of the substrate), including exact types of the events detected, indications of times when the detected events occurred, identification of the channels (e.g., of the specific sensors114) used to detect the events, and the like. In some implementations, when a reconfiguration (reprogramming) instruction received from the master computing device118is received by the ASIC244, the ASIC244may send instructions to the embedded processor362to reconfigure the application stored in on-chip RAM364or SDRAM373to change one or more settings of the application (e.g., to reflect a new type of a task executed by the robot108or new parameters for detecting events by sensors114). In some implementations, when a reconfiguration (reprogramming) instruction received from the master computing device118is received by the ASIC244, the ASIC244may reconfigure registers in the dual-ported memory366directly to change settings of the application. FIG.4is a flow diagram of one possible implementation of a method400of accurate optical sensing of positioning of substrates transported by a moving blade, in accordance with some implementations of the present disclosure. Method400may be performed using systems and components shown inFIGS.1-3or any combination thereof. Method400may be performed by the integrated sensor controller150. Some of the blocks of method400may be optional. Some or all blocks of the method400are performed responsive to instructions from the processing device242of the sensor controller150, in some implementations. In some implementations, some or all of the blocks of method400are performed responsive to instructions from the master computing device118, e.g., one or more processing devices (e.g. central processing units) of the master computing device118coupled to one or more memory devices. Method400may be performed while the manufacturing system (such as the manufacturing machine100) is performing a production process on multiple substrates. In some implementations, the method400may be implemented when a substrate is being transported to or from the processing chamber, the load-lock chamber, the transfer chamber, and the like, by a robot blade of a robot, for example while the robot blade110is transporting the substrate from the loading station102through the transfer chamber104and towards the processing chamber106. For example, the robot108may extend the robot blade110from the transfer chamber104into the loading station102and deliver (through a transfer port) the substrate for processing (position116) to the processing chamber106. The robot blade110may subsequently withdraw back into the transfer chamber104. The precision optical detection of substrate positioning may be performed while the substrate is inside the loading station102, while the substrate is inside the transfer chamber104, and/or while the substrate is inside the processing chamber106. The precision optical detection of substrate positioning may be performed while the robot blade110implements a standard delivery or retrieval procedure, without slowing down the robot blade's motion. Accordingly, the precision optical detection of substrate positioning may be performed without delaying the manufacturing process. The method400may involve the integrated sensor controller150(alone or in communication with the master computing device118) generating, e.g., by one or more light source drivers, a driving signal (block410). The light source drivers may be optical drivers (e.g., drivers generating light signals) or electric drivers (e.g., drivers generating electric signals to be delivered to light sources powered by electricity). Correspondingly, the optical or electric driving signals may be used to produce (e.g., by an optical or electronic demultiplexer) a plurality of output driving signals (block420). Method400may continue with delivering each of the plurality of output driving signals to a respective one of a plurality of sensors (block430). For example, the output driving signals may be delivered to one or more sensor heads202. Method400may further include receiving (e.g., by the amplifier214), one or more first signals from one or more sensors (e.g., from light detectors204) associated with various optical events representative of a position of a substrate within a device manufacturing machine (block440). Such events may include a direct light from a sensor head202striking a light detector204, the direct light being shielded (occluded) from the light detector by the substrate. Such events may further include a light reflected by (or transmitted through) the substrate striking (or being shielded from) the light detector, or any other optical event representative of the position of the substrate. In some implementations, the first signals may be optical signals (e.g., corresponding to light captured by optical fiber detectors204). In some implementations, the first signals may be electric signals (e.g., corresponding to signals produced by photodetectors204). Method400may continue with generating (e.g., by the amplifier214) and based on the received first signal(s), one or more second signals (block450). The second signals may be amplified first signals and may be of the same type as the first signals. For example, in those implementations, where the first signals are optical signals, the amplifiers214may be optical amplifiers and the generated second signals may likewise be optical signals. In those implementations, where the first signals are electric signals the amplifiers214may be electric signal multipliers and the generated second signals may be electric signals. In some implementations, where the first signal are optical signals, the amplifiers214may be optical amplifiers but may additionally include optical-to-electric signal converters, so that the generated second signals may be electric signals. At block460, the generated second signals may be received by an analog-to-digital converter (e.g., ADC216), which (at block470), may generate, based on the second signals, one or more third signals. The generated third signals may be received by the processing device (e.g., the processing device242). In some implementations, the third signals may be transmitted through an isolation circuit220configured to prevent noise and other spurious signals from the logic circuit240from affecting the circuitry of the sensor circuit210. At block480, the third signals may be used by the processing device to obtain information about the position of the substrate. The processing device may be able to extract, from the third signals, the data indicative of (one or more) underlying optical events, such as the type of the event (e.g., light incidence, occlusion, reflection, transmission, and the like), the timing of the event, the channel (e.g., the identity of the sensor that detected the event) the location of the event (e.g., based on the known location of the identified sensor), and so on. Based on this data, the processing device may obtain information about the exact location of the substrate relative to the robot blade. In some implementations, such information may be obtained based, in part, on the known location (and dynamics) of the robot blade, which may be obtained from the blade control module120residing on the master computing device118, or some other computing device available on the network (e.g., EtherCAT network). In some implementations, method400may continue with the processing device providing the information about the position of the substrate to the master computing device118(or to another computing device hosting the blade control module120) so that the blade control module can compensate for the error in the substrate positioning, e.g., by adjusting the trajectory of the blade so that the substrate arrives at its intended correct destination. In some implementations, method400may include receiving, by the processing device, reprogramming instructions to change a setting of one of the circuits or elements of the sensor circuit210, such as the amplifier214, one or more light source drivers212, and/or one or more sensors114. FIG.5depicts a block diagram of an example processing device500operating in accordance with one or more aspects of the present disclosure and capable of accurate optical sensing of substrates transported on a moving blade into a processing chamber, in accordance with some implementations of the present disclosure. The processing device500may be the computing device118ofFIG.1Aor a microcontroller152ofFIG.1B, in one implementation. Example processing device500may be connected to other processing devices in a LAN, an intranet, an extranet, and/or the Internet. The processing device500may be a personal computer (PC), a set-top box (STB), a server, a network router, switch or bridge, or any device capable of executing a set of instructions (sequential or otherwise) that specify actions to be taken by that device. Further, while only a single example processing device is illustrated, the term “processing device” shall also be taken to include any collection of processing devices (e.g., computers) that individually or jointly execute a set (or multiple sets) of instructions to perform any one or more of the methods discussed herein. Example processing device500may include a processor502(e.g., a CPU), a main memory504(e.g., read-only memory (ROM), flash memory, dynamic random access memory (DRAM) such as synchronous DRAM (SDRAM), etc.), a static memory506(e.g., flash memory, static random access memory (SRAM), etc.), and a secondary memory (e.g., a data storage device518), which may communicate with each other via a bus530. Processor502represents one or more general-purpose processing devices such as a microprocessor, central processing unit, or the like. More particularly, processor502may be a complex instruction set computing (CISC) microprocessor, reduced instruction set computing (RISC) microprocessor, very long instruction word (VLIW) microprocessor, processor implementing other instruction sets, or processors implementing a combination of instruction sets. Processor502may also be one or more special-purpose processing devices such as an application specific integrated circuit (ASIC), a field programmable gate array (FPGA), a digital signal processor (DSP), network processor, or the like. In accordance with one or more aspects of the present disclosure, processor502may be configured to execute instructions implementing method400of accurate optical sensing of positioning of substrates transported by a moving blade. Example processing device500may further comprise a network interface device508, which may be communicatively coupled to a network520. Example processing device500may further comprise a video display510(e.g., a liquid crystal display (LCD), a touch screen, or a cathode ray tube (CRT)), an alphanumeric input device512(e.g., a keyboard), an input control device514(e.g., a cursor control device, a touch-screen control device, a mouse), and a signal generation device516(e.g., an acoustic speaker). Data storage device518may include a computer-readable storage medium (or, more specifically, a non-transitory computer-readable storage medium)528on which is stored one or more sets of executable instructions522. In accordance with one or more aspects of the present disclosure, executable instructions522may comprise executable instructions implementing method400of accurate optical sensing of positioning of substrates transported by a moving blade. Executable instructions522may also reside, completely or at least partially, within main memory504and/or within processing device502during execution thereof by example processing device500, main memory504and processor502also constituting computer-readable storage media. Executable instructions522may further be transmitted or received over a network via network interface device508. While the computer-readable storage medium528is shown inFIG.5as a single medium, the term “computer-readable storage medium” should be taken to include a single medium or multiple media (e.g., a centralized or distributed database, and/or associated caches and servers) that store the one or more sets of operating instructions. The term “computer-readable storage medium” shall also be taken to include any medium that is capable of storing or encoding a set of instructions for execution by the machine that cause the machine to perform any one or more of the methods described herein. The term “computer-readable storage medium” shall accordingly be taken to include, but not be limited to, solid-state memories, and optical and magnetic media. It should be understood that the above description is intended to be illustrative, and not restrictive. Many other implementation examples will be apparent to those of skill in the art upon reading and understanding the above description. Although the present disclosure describes specific examples, it will be recognized that the systems and methods of the present disclosure are not limited to the examples described herein, but may be practiced with modifications within the scope of the appended claims. Accordingly, the specification and drawings are to be regarded in an illustrative sense rather than a restrictive sense. The scope of the present disclosure should, therefore, be determined with reference to the appended claims, along with the full scope of equivalents to which such claims are entitled. The implementations of methods, hardware, software, firmware or code set forth above may be implemented via instructions or code stored on a machine-accessible, machine readable, computer accessible, or computer readable medium which are executable by a processing element. “Memory” includes any mechanism that provides (i.e., stores and/or transmits) information in a form readable by a machine, such as a computer or electronic system. For example, “memory” includes random-access memory (RAM), such as static RAM (SRAM) or dynamic RAM (DRAM); ROM; magnetic or optical storage medium; flash memory devices; electrical storage devices; optical storage devices; acoustical storage devices, and any type of tangible machine-readable medium suitable for storing or transmitting electronic instructions or information in a form readable by a machine (e.g., a computer). Reference throughout this specification to “one implementation” or “an implementation” means that a particular feature, structure, or characteristic described in connection with the implementation is included in at least one implementation of the disclosure. Thus, the appearances of the phrases “in one implementation” or “in an implementation” in various places throughout this specification are not necessarily all referring to the same implementation. Furthermore, the particular features, structures, or characteristics may be combined in any suitable manner in one or more implementations. In the foregoing specification, a detailed description has been given with reference to specific exemplary implementations. It will, however, be evident that various modifications and changes may be made thereto without departing from the broader spirit and scope of the disclosure as set forth in the appended claims. The specification and drawings are, accordingly, to be regarded in an illustrative sense rather than a restrictive sense. Furthermore, the foregoing use of implementation, implementation, and/or other exemplarily language does not necessarily refer to the same implementation or the same example, but may refer to different and distinct implementations, as well as potentially the same implementation. The words “example” or “exemplary” are used herein to mean serving as an example, instance, or illustration. Any aspect or design described herein as “example” or “exemplary” is not necessarily to be construed as preferred or advantageous over other aspects or designs. Rather, use of the words “example” or “exemplary” is intended to present concepts in a concrete fashion. As used in this application, the term “or” is intended to mean an inclusive “or” rather than an exclusive “or.” That is, unless specified otherwise, or clear from context, “X includes A or B” is intended to mean any of the natural inclusive permutations. That is, if X includes A; X includes B; or X includes both A and B, then “X includes A or B” is satisfied under any of the foregoing instances. In addition, the articles “a” and “an” as used in this application and the appended claims should generally be construed to mean “one or more” unless specified otherwise or clear from context to be directed to a singular form. Moreover, use of the term “an implementation” or “one implementation” or “an implementation” or “one implementation” throughout is not intended to mean the same implementation or implementation unless described as such. Also, the terms “first,” “second,” “third,” “fourth,” etc. as used herein are meant as labels to distinguish among different elements and may not necessarily have an ordinal meaning according to their numerical designation. | 40,875 |
11862500 | DETAILED DESCRIPTION In the following description, for the purposes of explanation, numerous specific details are set forth in order to provide a thorough understanding of various embodiments or implementations of the invention. As used herein “embodiments” and “implementations” are interchangeable words that are non-limiting examples of devices or methods employing one or more of the inventive concepts disclosed herein. It is apparent, however, that various embodiments may be practiced without these specific details or with one or more equivalent arrangements. In other instances, well-known structures and devices are shown in block diagram form in order to avoid unnecessarily obscuring various embodiments. Further, various embodiments may be different, but do not have to be exclusive. For example, specific shapes, configurations, and characteristics of an embodiment may be used or implemented in another embodiment without departing from the inventive concepts. Unless otherwise specified, the illustrated embodiments are to be understood as providing features of varying detail of some ways in which the inventive concepts may be implemented in practice. Therefore, unless otherwise specified, the features, components, modules, layers, films, panels, regions, and/or aspects, etc. (hereinafter individually or collectively referred to as “elements”), of the various embodiments may be otherwise combined, separated, interchanged, and/or rearranged without departing from the inventive concepts. The use of cross-hatching and/or shading in the accompanying drawings is generally provided to clarify boundaries between adjacent elements. As such, neither the presence nor the absence of cross-hatching or shading conveys or indicates any preference or requirement for particular materials, material properties, dimensions, proportions, commonalities between illustrated elements, and/or any other characteristic, attribute, property, etc., of the elements, unless specified. Further, in the accompanying drawings, the size and relative sizes of elements may be exaggerated for clarity and/or descriptive purposes. When an embodiment may be implemented differently, a specific process order may be performed differently from the described order. For example, two consecutively described processes may be performed substantially at the same time or performed in an order opposite to the described order. Also, like reference numerals denote like elements. When an element, such as a layer, is referred to as being “on,” “connected to,” or “coupled to” another element or layer, it may be directly on, connected to, or coupled to the other element or layer or intervening elements or layers may be present. When, however, an element or layer is referred to as being “directly on,” “directly connected to,” or “directly coupled to” another element or layer, there are no intervening elements or layers present. To this end, the term “connected” may refer to physical, electrical, and/or fluid connection, with or without intervening elements. Further, the D1-axis, the D2-axis, and the D3-axis are not limited to three axes of a rectangular coordinate system, such as the x, y, and z-axes, and may be interpreted in a broader sense. For example, the D1-axis, the D2-axis, and the D3-axis may be perpendicular to one another, or may represent different directions that are not perpendicular to one another. For the purposes of this disclosure, “at least one of X, Y, and Z” and “at least one selected from the group consisting of X, Y, and Z” may be construed as X only, Y only, Z only, or any combination of two or more of X, Y, and Z, such as, for instance, XYZ, XYY, YZ, and ZZ. As used herein, the term “and/or” includes any and all combinations of one or more of the associated listed items. Although the terms “first,” “second,” etc. may be used herein to describe various types of elements, these elements should not be limited by these terms. These terms are used to distinguish one element from another element. Thus, a first element discussed below could be termed a second element without departing from the teachings of the disclosure. Spatially relative terms, such as “beneath,” “below,” “under,” “lower,” “above,” “upper,” “over,” “higher,” “side” (e.g., as in “sidewall”), and the like, may be used herein for descriptive purposes, and, thereby, to describe one elements relationship to another element(s) as illustrated in the drawings. Spatially relative terms are intended to encompass different orientations of an apparatus in use, operation, and/or manufacture in addition to the orientation depicted in the drawings. For example, if the apparatus in the drawings is turned over, elements described as “below” or “beneath” other elements or features would then be oriented “above” the other elements or features. Thus, the exemplary term “below” can encompass both an orientation of above and below. Furthermore, the apparatus may be otherwise oriented (e.g., rotated 90 degrees or at other orientations), and, as such, the spatially relative descriptors used herein interpreted accordingly. The terminology used herein is for the purpose of describing particular embodiments and is not intended to be limiting. As used herein, the singular forms, “a,” “an,” and “the” are intended to include the plural forms as well, unless the context clearly indicates otherwise. Moreover, the terms “comprises,” “comprising,” “includes,” and/or “including,” when used in this specification, specify the presence of stated features, integers, steps, operations, elements, components, and/or groups thereof, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof. It is also noted that, as used herein, the terms “substantially,” “about,” and other similar terms, are used as terms of approximation and not as terms of degree, and, as such, are utilized to account for inherent deviations in measured, calculated, and/or provided values that would be recognized by one of ordinary skill in the art. Various embodiments are described herein with reference to sectional and/or exploded illustrations that are schematic illustrations of idealized embodiments and/or intermediate structures. As such, variations from the shapes of the illustrations as a result, for example, of manufacturing techniques and/or tolerances, are to be expected. Thus, embodiments disclosed herein should not necessarily be construed as limited to the particular illustrated shapes of regions, but are to include deviations in shapes that result from, for instance, manufacturing. In this manner, regions illustrated in the drawings may be schematic in nature and the shapes of these regions may not reflect actual shapes of regions of a device and, as such, are not necessarily intended to be limiting. Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure is a part. Terms, such as those defined in commonly used dictionaries, should be interpreted as having a meaning that is consistent with their meaning in the context of the relevant art and should not be interpreted in an idealized or overly formal sense, unless expressly so defined herein. FIG.1is a schematic view of an embodiment of an apparatus for manufacturing a display device constructed according to the principles of the invention.FIG.2is a perspective view of a portion of an embodiment of the chucking device ofFIG.1.FIG.3is a plan view of the chucking device ofFIG.2.FIG.4is a cross-sectional view taken along line IV-IV′ ofFIG.3. FIGS.1to4, an apparatus1for manufacturing a display device may include a movable support in the form of a chucking device CD and a substrate processing device. The chucking device CD may be a device for fixing a target substrate SUB on a support member in the form of a chuck plate CP, and the substrate processing device may be a device for performing manufacturing processes on the target substrate SU,B which is mounted on the chuck plate CP by the chucking device CD. The substrate processing device may be, for example, a deposition device, such as deposition device DD ofFIG.1, an etching device, a cleaning device, a heat treatment device, a laser processing device, a coating device, an inspection device, etc., but embodiments are not limited thereto. In the illustrated embodiments, the deposition device DD for depositing a thin film on the target substrate SUB is illustrated as an example of the substrate processing device. The deposition device DD may be a device used in a process for manufacturing the display device. For example, the deposition device DD may be used in a process of forming a plurality of thin films included in a liquid crystal display, a field emission display, a plasma display, and an electro-luminescence display. The target substrate SUB may be an insulating substrate or a substrate including a plurality of thin film structures disposed on the insulating substrate. The target substrate SUB may include an upper surface SUBa on which a thin film is formed in the deposition device DD by material deposited thereon, and a rear surface SUBb which is opposite to the upper surface SUBa. Examples of methods of forming the thin film on the target substrate SUB include physical vapor deposition (PVD) methods such as a vacuum evaporation method, ion plating method, and a sputtering method, and chemical vapor deposition (CVD) methods by gas reaction. Hereinafter, the vacuum evaporation method will be described, but embodiments of the deposition device DD are not limited thereto. The deposition device DD may include a deposition source DC in which the material to be deposited is stored, and a nozzle NZ that has a passage through which the material to be deposited is injected. A storage space in which the material to be deposited is stored may be formed inside the deposition source DC. For example, the material to be deposited may be an organic material. Specifically, the material to be deposited may include an organic light emitting material, a hole injection/hole transport material, an electron injection/electron transport material of an organic light emitting display. The material to be deposited, which is an organic material, may be vaporized and then discharged toward the target substrate SUB through the nozzle NZ. An example of a method by which the material to be deposited is vaporized includes heating. For example, a heating coil may be formed on an inner wall of the deposition material, and a current may be applied to the heating coil to generate heat. However, the method of vaporizing the material to be deposited is not limited to heating. The chucking device CD and the deposition device DD may be located in different chambers. For example, the chucking device CD may be located in a loading chamber CH1, and the deposition device DD may be located in a deposition chamber CH2. The internal space of the loading chamber CH1may be defined as a loading space LS, and the internal space of the deposition chamber CH2may be defined as a deposition space DS. Also, the loading space LS and the deposition space DS may be spatially connected to each other by a connection space CS disposed therebetween. The connection space CS is a connection passage through which the chuck plate CP loaded with the target substrate SUB in the loading space LS moves to the deposition space DS The chuck plate CP loaded with the target substrate SUB on which the material is to be deposited in the deposition space DS moves to the loading space LS through the connection passage formed by connection space CS. The apparatus1for manufacturing the display device may include a first gate G1which is disposed opposite to a first direction DR1of the loading space LS and configured to enable the target substrate SUB to be drawn in or out from the outside, and a second gate G2which is disposed toward the first direction DR1of the loading space LS and connected to the connection space CS. The gates could be reversed such that second gate G2may be disposed toward the first direction DR1of the connection space CS. The apparatus1for manufacturing the display device may further include a third gate G3which is disposed in the first direction DR1of the loading space LS and connected to the deposition space DS. The third gate G3may be disposed in the opposition direction of the first direction DR1of the deposition space DS. In the deposition process, a vacuum atmosphere may be formed in the loading space LS and the deposition space DS in order to prevent foreign substances or the like from being attached to the target substrate SUB and stably deposit the material to be deposited. To this end, the apparatus1for manufacturing the display device may further include vacuum pumps VM1and VM2and vacuum tubes VP1and VP2. The vacuum pumps VM1and VM2may include a first vacuum pump VM1providing the vacuum atmosphere in the loading space LS and a second vacuum pump VM2providing the vacuum atmosphere in the deposition space DS. The first vacuum pump VM1may be connected to the loading space LS through the first vacuum tube VP1, and the second vacuum pump VM2may be connected to the deposition space DS through the second vacuum tube VP2.FIG.1illustrates that the vacuum atmosphere is provided in the loading spaces LS and the deposition spaces DS by two different vacuum pumps VM1and VM2, but the embodiments are not limited thereto, and in the loading space LS and deposition space DS, the vacuum atmosphere may also be provided by one vacuum pump. The chucking device CD may include the chuck plate CP, a pressure-sensitive chuck PSC, an electrostatic support, which may be in the form of an electrostatic chuck ESC, a base unit BS, a support SP, and an elevating device SD. The target substrate SUB may be mounted on the chuck plate CP. The chuck plate CP, may include a plurality of openings OP passing through a chuck frame CF, with the chuck frame CF surrounding the plurality of openings OP. The chuck plate CP may have a cuboid appearance, but embodiments are not limited thereto, and may, e.g., have a cylindrical shape and other polyprism shapes. The opening OP may be a through hole penetrating the chuck frame CF. The shape of each opening OP may be a cuboid, but embodiments are not limited thereto. The size of each opening OP may be substantially the same, but embodiments are not limited thereto. The openings OP may have different sizes from each other. The shape and size of the opening OP may be variously set according to of the particular design of the display device. The chuck plate CP may include a first area overlapping an area of the target substrate SUB in which the material is to be deposited in the deposition process, and a second area surrounding the first area and overlapping an area of the target substrate SUB in which the material is not to be deposited. The first and second areas may be provided in the form of a deposition area DA and a non-deposition area NDA, respectively. Each opening OP may be included in the deposition area DA. The chuck frame CF positioned between the openings OP may be included in the non-deposition area NDA, but embodiments are not limited thereto, and may be included in the deposition area DA depending on the size, shape, or other specifications of the target substrate SUB to be mounted. For example, a portion of the chuck frame CF positioned between the deposition areas DA adjacent to each other may be included in the non-deposition area NDA. Another portion of the chuck frame CF positioned between the plurality of openings OP corresponding to the area to be used for the same display device in the target substrate SUB may be included in the deposition area DA. Adhesive patterns, which may be in the form of pressure-sensitive adhesive chucks and/or pressure-sensitive chucks PSC, may be disposed on the chuck frame CF included in the non-deposition area NDA. The target substrate SUB mounted on the chuck plate CP may be formed with a micro pattern by performing various processes such as a deposition process, an exposure process, and an etching process. The pressure-sensitive chuck PSC may fix and/or attach the target substrate SUB to the chuck plate CP so that the position of the target substrate SUB is not changed during the various processes. The pressure-sensitive chuck PSC may include a pressure-sensitive pad, a pressure-sensitive sheet, pressure-sensitive rubber, or the like with adhesion. A rear surface of the pressure-sensitive chuck PSC is fixed and/or attached to the chuck plate CP, and an upper surface of the pressure-sensitive chuck PSC may be fixed and/or attached to the target substrate SUB. Respective pressure-sensitive chucks PSCs are spaced apart from each other, and the upper surfaces of the pressure-sensitive chucks PSCs may be located on substantially the same plane. In addition, the respective pressure-sensitive chucks PSCs may have substantially the same shape and size. When the deposition area DA includes one opening OP, the plurality of pressure-sensitive chucks PSC may be disposed on the chuck frame CF surrounding the opening OP. When the deposition area DA includes a plurality of openings OPs, the pressure-sensitive chucks PSCs may not be disposed on a portion of the chuck frame CF located between the openings OPs. If the pressure-sensitive chucks PSCs are disposed in the deposition area DA including the plurality of openings OPs, the pressure-sensitive material contained in the pressure-sensitive chuck PSC is melted in a process performed at a high temperature and generates foreign substances such as spots on the target substrate SUB, which causes defects in the display device. The pressure-sensitive chucks PSCs according to the principles and embodiments of the invention may not be disposed in the deposition area DA, but rather may be disposed in the non-decription area NDA surrounding the deposition area DA, thereby avoiding generation of foreign substances on the target substrate. In a plan view, the electrostatic chuck ESC may be disposed in each opening OP included in the chuck plate CP. The electrostatic chuck ESC may overlap each opening OP, and may be configured to move reciprocally in a third direction DR3to pass through the opening OP. The electrostatic chuck ESC is connected to a power supply unit PW and may receive power from the power supply unit PW to adsorb and fix the target substrate SUB using electrostatic force. The upper surface of the electrostatic chuck ESC may contact the rear surface SUBb of the target substrate SUB to fix the target substrate SUB. Specifically, when a voltage is applied to the electrostatic chuck ESC, the electrostatic chuck ESC may fix the target substrate SUB since the voltage of the electrostatic chuck ESC causes an opposite potential to be charged to the target substrate SUB and an attraction force is generated by the charged potential of the target substrate SUB and the voltage of the electrostatic chuck ESC. The electrostatic chuck ESC may have a substantially flat plate shape. The shape and size of each electrostatic chuck ESC may correspond to the shape and size of the opening OP in which the corresponding electrostatic chuck ESC may be disposed. In an embodiment, the shape of the electrostatic chuck ESC is substantially the same as the shape of the opening OP, but the size of the electrostatic chuck ESC is smaller than that of the opening OP. For example, a first width W1, which is the length of a long side of one opening OP, may be greater than a second width W2, which is the length of a long side of the electrostatic chuck ESC. Also, the plurality of electrostatic chucks ESC may include an electrostatic chuck ESC having a shape extending in a first direction DR1as shown at ESC1inFIG.3and an electrostatic chuck ESC having a shape extending in a second direction DR2as shown at ESC2inFIG.3. The elevating device SD may be coupled to the lower portion of the electrostatic chuck ESC and may move the electrostatic chuck ESC reciprocally through the opening OP in the third direction DR3. At this time, the upper surface of each electrostatic chuck ESC may move while maintaining substantially the same plane. In an embodiment, two or more elevating devices SD may be provided, and each may be coupled to each electrostatic chuck ESC. For example, the elevating device SD may include a servo motor or a cylinder, but embodiments are not limited thereto. The electrostatic chuck ESC overlapping the opening OP in the plan view may move reciprocally back and forth through the opening OP. The upper surface of the electrostatic chuck ESC may move to a position lower than the rear surface of the chuck plate CP. In addition, the lower surface of the electrostatic chuck ESC may move to a position higher than the upper surface of the pressure-sensitive chuck PSC. The operation of the elevating device SD that moves the electrostatic chuck ESC in the third direction DR3may be controlled by a control unit CT. The control unit CT may operate the elevating device SD to move the electrostatic chuck ESC through the opening OP such that the target substrate SUB is disposed on and/or pressed against the upper surface of the pressure-sensitive chuck PSC to attach the target substrate SUB to the pressure-sensitive chuck PSC. The elevating device SD may be coupled to the base unit BS disposed at the bottom. That is, the base unit BS may support the electrostatic chuck ESC and the elevating device SD that moves the electrostatic chuck ESC. In an embodiment, a support SP may be disposed in the first direction DR1on opposite sides of the base unit BS. The support SP may support the chuck plate CP during the chucking process. The upper surface of the support SP comes into contact with the chuck plate CP, and may include a substantially flat surface. The apparatus1for manufacturing the display device may chuck (fix) the target substrate SUB on the pressure-sensitive chuck PSC and/or the chuck plate CP using the electrostatic chuck ESC, which contacts the rear surface SUBb of the target substrate SUB rather than the upper surface SUBa of the target substrate SUB, thereby preventing the damage to the target substrate SUB and/or elements of the target substrate SUB disposed on the upper surface SUBa. In addition, foreign substances may be prevented and/or reduced from being attached to the upper surface SUBa of the target substrate SUB. FIG.5is a flowchart of an embodiment of a method for manufacturing a display device according to the principles of the invention.FIGS.6to12are schematic views of an apparatus for manufacturing a display device at some of process steps of the method ofFIG.5. Hereinafter, an example method for manufacturing a display device using the apparatus1ofFIG.1will be described with reference toFIGS.5to12. Referring toFIG.5, the method for manufacturing a display device may include the steps of preparing a target substrate, a chuck plate with a pressure-sensitive chuck disposed on an upper surface, and an electrostatic chuck positioned above the chuck plate in a loading space (S100), placing and fixing a target substrate on the electrostatic chuck (S200), attaching the target substrate to the pressure-sensitive chuck by lowering the electrostatic chuck (S300), continuing to lower the electrostatic chuck to place the upper surface of the electrostatic chuck below the rear surface of the chuck plate (S400), moving the chuck plate to a deposition space and depositing a material on the target substrate in the deposition space (S500), moving the target substrate to a loading space and placing the target substrate on a support in a loading space (S600), and separating the target substrate from the pressure-sensitive chuck by lifting the electrostatic chuck (S700). First, the step S100of preparing the target substrate SUB, the chuck plate CP with the pressure-sensitive chuck PSC disposed on its upper surface, and the electrostatic chuck ESC positioned above the chuck plate CP in the loading chamber CH1may be performed. The loading chamber CHL the target substrate SUB, the pressure-sensitive chuck PSC, the chuck plate CP, and the electrostatic chuck ESC have been described above with reference toFIGS.1to4, and will be omitted below to avoid redundancy. Referring toFIGS.5,6and7, the step S200of placing and fixing the target substrate SUB on the electrostatic chuck ESC may be performed. At least a portion of the rear surface SUBb of the target substrate SUB may contact the electrostatic chuck ESC. A voltage may be applied to the electrostatic chuck ESC by a power supply unit PW. As described above, when the voltage is applied to the electrostatic chuck ESC, an electrostatic force is generated and the target substrate SUB may be adsorbed to and/or fixed to the electrostatic chuck ESC by the adsorption force caused by the electrostatic force. After the target substrate SUB is disposed on the electrostatic chuck ESC, while the first gate G1and the second gate G2are closed, a vacuum atmosphere may be formed in the loading space LS through the first vacuum pump VM1. All processes performed below may be performed under vacuum atmosphere. When the rear surface SUBb of the target substrate SUB is fixed in contact with the electrostatic chuck ESC, the step S300of chucking and/or attaching the target substrate SUB to the pressure-sensitive chuck PSC by lowering the electrostatic chuck ESC may be performed. The step of lowering the electrostatic chuck ESC may be performed by operating the elevating device SD through the control unit CT. The electrostatic chuck ESC may be lowered until the rear surface SUBb of the target substrate SUB contacts the upper surface of the pressure-sensitive chuck PSC. In this case, the upper surface of the electrostatic chuck ESC and the upper surface of the pressure-sensitive chuck PSC may be positioned on substantially the same plane. Even after the rear surface SUBb of the target substrate SUB comes into contact with the upper surface of the pressure-sensitive chuck PSC, the electrostatic chuck ESC may be forced to descend downwardly, in a direction opposite the third direction DR3, by the elevating device SD. Through this, airtight chucking between the target substrate SUB and the pressure-sensitive chuck PSC may be performed. Referring toFIGS.5,8and9, when the target substrate SUB is chucked and/or attached to the pressure-sensitive chuck PCS, the step S400of continuing to lower the electrostatic chuck ESC so that the upper surface of the electrostatic chuck ESC is located below the rear surface of the chuck plate CP may be performed. This may also be performed by operating the elevating device SD through the control unit CT. At this time, the power supply unit PW may stop applying the voltage to the electrostatic chuck ESC, but embodiments are not limited thereto, and the power supply unit PW may continue to apply the voltage to the electrostatic chuck ESC for airtight chucking between the target substrate SUB and the pressure-sensitive chuck PCS. Due to the voltage applied to the electrostatic chuck ESC, an electrostatic force may be maintained to keep adhesive force between the target substrate SUB and the electrostatic chuck ESC. The electrostatic chuck ESC having the electrostatic force, which may function as the adhesive force between the target substrate SUB and the electrostatic chuck ESC, may press the target substrate SUB in a direction opposing the third direction DR3for airtight chucking between the target substrate SUB and the pressure-sensitive chuck PCS. During lowering of the electrostatic chuck ESC, when the application of the voltage to the electrostatic chuck ESC is not stopped, the elevating device SD may receive a load greater than that of when the application of the voltage to the electrostatic chuck ESC is stopped. In addition, even if the application of the voltage to the electrostatic chuck ESC is stopped, the electrostatic force may remain between the target substrate SUB and the electrostatic chuck ESC, and the remaining electrostatic force may allow the target substrate SUB to be pressed in the direction opposing the third direction DR3for airtight chucking between the target substrate SUB and the pressure-sensitive chuck PCS when electrostatic chuck ESC descends. When the upper surface of the electrostatic chuck ESC moves to a position lower than the upper surface of the pressure-sensitive chuck PSC, the target substrate SUB may be bent locally around the opening OP of the chuck plate CP due to adhesion with the electrostatic chuck ESC. Specifically, an area of the target substrate SUB chucked to the electrostatic chuck ESC may move in the direction opposing the third direction DR3relatively to other areas of the target substrate SUB. Through this, the target substrate SUB may be forced in the direction opposing the third direction DR3to perform airtight chucking between the pressure-sensitive chuck PSC and the target substrate SUB. The electrostatic chuck ESC and the target substrate SUB may be maintained to be chucked until the electrostatic chuck ESC descends to a predetermined position, and then a bending portion of the target substrate SUB may be separated and restored to a flat shape again, and the electrostatic chuck ESC may continue to descend to a lower position. In a subsequent process, the chuck plate CP may move to one side in the first direction DR. At this time, in order to facilitate the movement of the chuck plate CP, the electrostatic chuck ESC may descend until the upper surface is located below the rear surface of the chuck plate CP. In addition, the electrostatic chuck ESC may descend until the upper surface is located below the upper surface of the support SP. Referring toFIGS.5and10, after the step S400of continuing to descend the electrostatic chuck ESC so that the electrostatic chuck ESC is located below the rear surface of the chuck plate CP, the step S500of moving the chuck plate CP to the deposition space DS and depositing the material on the target substrate SUB may be performed. The deposition process may be performed in the deposition space DS inside the deposition chamber CH2. The chuck plate CP may be transferred from the loading space LS to the deposition space DS via the connection space CS by a transfer unit. The chuck plate CP may be rotated 180° so that the upper surface SUBa of the target substrate SUB faces the deposition device DD in the direction opposing the third direction DR3. The step of rotating the chuck plate CP at 180° may be performed in the deposition space DS, but embodiments are not limited thereto, and may also be performed in the loading space LS or the connection space CS. When the chuck plate CP on which the target substrate SUB is fixed enters the deposition space DS, while the third gate G3is closed, a vacuum atmosphere may be generated in the deposition space DS by the second vacuum pump VM2. When the vacuum atmosphere is generated in the deposition space DS, the material may be deposited on the upper surface SUBa of the target substrate SUB by the deposition device DD. In an embodiment, the material to be deposited is stored in the deposition source DC of the deposition device DD and then vaporized to be sprayed through the nozzle NZ toward the upper surface SUBa of the target substrate SUB. Referring toFIGS.5and11, after the step S500of depositing the material on the upper surface SUBa of the target substrate SUB, the step S600of moving the target substrate SUB to the loading space LS and placing the target substrate SUB on the support SP in the loading space LS may be performed. In order to perform another process on the target substrate SUB on which deposition is performed, it is required to separate the target substrate SUB from the chuck plate CP. For this purpose, the chuck plate CP on which the target substrate SUB is fixed may return from the deposition space DS to the loading space LS. The step of separating the target substrate SUB from the chuck plate CP may be performed using the chucking device CD, but embodiments are not limited thereto and the step of separating the target substrate SUB from the chuck plate CP may be performed using other devices. When the chuck plate CP on which the target substrate SUB is fixed is mounted on the support SP, the electrostatic chuck ESC may ascend toward the chuck plate CP in the third direction DR3. The upper surface of the electrostatic chuck ESC may contact the rear surface SUBb of the target substrate SUB and positioned on substantially the same plane as the upper surface of the electrostatic chuck ESC. The elevating device SD may ascend the electrostatic chuck ESC under the control of the control unit CT. A voltage may be applied to the electrostatic chuck ESC to fix the electrostatic chuck ESC to the target substrate SUB and/or to separate the target substrate SUB from the chuck plate CP. The voltage applied to the electrostatic chuck ESC may be applied before the upper surface of the electrostatic chuck ESC comes into contact with the rear surface SUBb of the target substrate SUB, but embodiments are not limited thereto. In addition, the voltage applied to the electrostatic chuck ESC may also be applied after the upper surface of the electrostatic chuck ESC comes into contact with the rear surface SUBb of the target substrate SUB. Referring toFIGS.5and12, after the step S600is performed, the step S700of separating the target substrate SUB from the pressure-sensitive chuck PSC by lifting the electrostatic chuck ESC may be performed. When the upper surface of the electrostatic chuck ESC moves to a position higher than the upper surface of the pressure-sensitive chuck PSC, the target substrate SUB may be bent locally around the opening OP of the chuck plate CP due to adhesion between the target substrate SUB and the pressure-sensitive chuck PSC and the pressure from the electrostatic chuck ESC. Specifically, an area of the target substrate SUB chucked to the electrostatic chuck ESC may move in the third direction DR3relatively to other areas of the target substrate SUB. Through this, the target substrate SUB may be forced in the third direction DR3to weaken the adhesion between the pressure-sensitive chuck PSC and the target substrate SUB. The electrostatic chuck ESC and the target substrate SUB may be coupled and fixed together until the electrostatic chuck ESC ascends to a predetermined position. Thereafter, the pressure-sensitive chuck PSC and the target substrate SUB are separated from each other so that the bending portion of the target substrate SUB is restored to a flat shape again and the electrostatic chuck ESC and the target substrate SUB may ascend to a higher position as shown inFIG.6. At this time, the pressure-sensitive chuck PSC may not be separated from the chuck plate CP. In an embodiment, the adhesion between the pressure-sensitive chuck PSC and the chuck plate CP may be greater than the adhesion between the pressure-sensitive chuck PSC and the target substrate SUB. In addition, even if the upper surface of the electrostatic chuck ESC ascends while coming into contact with the rear surface SUBb of the target substrate SUB, the chuck plate CP may not ascend due to the load of the chuck plate CP itself which is greater than the adhesion between the pressure-sensitive chuck PSC and the target substrate SUB. When the target substrate SUB is separated from the pressure-sensitive chuck PSC, a voltage is continuously applied to the electrostatic chuck ESC, so that the target substrate SUB may be stably separated while being fixed to the electrostatic chuck ESC. Hereinafter, another embodiment of the apparatus for manufacturing the display device will be described. In the following embodiments, description of substantially the same configuration as that of the embodiment described above will be omitted or simplified to avoid redundancy, and differences will be mainly described. FIG.13is a schematic view of another embodiment of an apparatus for manufacturing a display device constructed according to the principles of the invention. Referring toFIG.13, an apparatus1_1for manufacturing a display device is different from the apparatus1ofFIG.1in that each separated electrostatic chuck ESC_1may move in a third direction DR3by one elevating device SD_1. In the apparatus1_1, the electrostatic chuck ESC_1may move reciprocally in the corresponding openings OPs in the third direction. The upper surface of the electrostatic chuck ESC_1may move to a position lower than the rear surface of the chuck plate CP. In addition, the lower surface of the electrostatic chuck ESC_1may move to a position higher than the upper surface of the pressure-sensitive chuck PSC. The operation of the elevating device SD_1that moves the electrostatic chuck ESC_1in the third direction DR3may be controlled by a control unit CT. The elevating device SD_1may be coupled to a base unit BS disposed at the bottom. That is, the base unit BS may support the electrostatic chuck ESC_1and the elevating device SD_1that moves the electrostatic chuck ESC_1. The apparatus1_1may chuck (fix) the target substrate SUB on the pressure-sensitive chuck PSC and/or the chuck plate CP using the electrostatic chuck ESC contacting the rear surface SUBb of the target substrate SUB rather than the upper surface SUBa of the target substrate SUB, thereby preventing the damage to the target substrate SUB and/or elements of the target substrate SUB disposed on the upper surface SUBa. In addition, foreign substances may be prevented and/or reduced from being attached to the upper surface SUBa of the target substrate SUB. FIG.14is a schematic view of still another embodiment of an apparatus for manufacturing a display device constructed according to the principles of the invention. Referring toFIG.14, an apparatus1_2for manufacturing a display device is different from the apparatus1ofFIG.1in that an elevating device SD_2is included in and/or coupled to a first support SP1_2and to reciprocally move and support a chuck plate CP in a third direction DR3. An electrostatic chuck ESC may be coupled to the second support SP2_2disposed at the bottom. The second support SP2_2may support the electrostatic chuck ESC during a chucking process. The second support SP2_2may include a wiring for applying a voltage provided from a power supply unit PW to the electrostatic chuck ESC. The chuck plate CP may be supported by a first support SP1_2disposed at a lower portion. The chuck plate CP may move in a direction substantially normal to the surface of the electrostatic chuck ESC, which may be the third direction DR3, through the elevating device SD_2included in the first support SP1_2. As the chuck plate CP moves in the third direction DR3, the electrostatic chuck ESC may move reciprocally in the opening OP of the chuck plate CP. The rear surface of the chuck plate CP may move to a position higher than the upper surface of the electrostatic chuck ESC. In addition, the lower surface of the electrostatic chuck ESC may move to a position higher than the upper surface of the pressure-sensitive chuck PSC. The operation of the elevating device SD_2that moves the electrostatic chuck ESC in the third direction DR3may be controlled by a control unit CT. The apparatus1_2for manufacturing the display device may chuck (fix) the target substrate SUB on the pressure-sensitive chuck PSC and/or the chuck plate CP using the electrostatic chuck ESC contacting the rear surface SUBb of the target substrate SUB rather than the upper surface SUBa of the target substrate SUB, thereby preventing the damage to the target substrate SUB and/or elements of the target substrate SUB disposed on the upper surface SUBa. In addition, foreign substances may be prevented and/or reduced from being attached to the upper surface SUBa of the target substrate SUB. Although certain embodiments and implementations have been described herein, other embodiments and modifications will be apparent from this description. Accordingly, the inventive concepts are not limited to such embodiments, but rather to the broader scope of the appended claims and various obvious modifications and equivalent arrangements as would be apparent to a person of ordinary skill in the art. | 40,660 |
11862501 | DESCRIPTION OF EMBODIMENTS Hereinafter, one embodiment of an electrostatic chuck, a substrate fixing device and a manufacturing method of a substrate fixing device of the present disclosure will be described in detail with reference to the drawings. Note that, the present invention is not limited to the embodiment. FIG.1is a perspective view showing a configuration of a substrate fixing device100according to an embodiment. The substrate fixing device100shown inFIG.1has a structure where an electrostatic chuck120is bonded to a base plate110. The base plate110is a square member of metal such as aluminum, for example. The base plate110is abase member for fixing the electrostatic chuck120. The base plate110is attached to a semiconductor manufacturing device, for example, and causes the substrate fixing device100to function as a semiconductor holding device configured to hold a wafer. The electrostatic chuck120has a plurality of (four, inFIG.1) ceramic substrates aligned side by side, and is configured to adsorb an adsorption object such as a wafer to surfaces of the ceramic substrates by using an electrostatic force. The electrostatic chuck120is bonded to the base plate110by a silicone adhesive, for example. The plurality of ceramic substrates constituting the electrostatic chuck120is arranged adjacent to each other, and a sprayed portion is formed at a boundary of the adjacent ceramic substrates by spraying aluminum oxide (alumina). FIG.2is a schematic view showing a section taken along an I-I line ofFIG.1. As shown inFIG.2, the substrate fixing device100is constituted by bonding the electrostatic chuck120to the base plate110via an adhesive layer130. The base plate110is a metal member having a thickness of about 20 to 50 mm where a cooling water channel111becoming a flow path of cooling water is formed therein. The base plate110is configured to cool the electrostatic chuck120by cooling water introduced from an outside of the substrate fixing device100into the cooling water channel111. The electrostatic chuck120is cooled, so that the adsorption object such as a wafer adsorbed to the electrostatic chuck120is cooled. Note that, the base plate110may have a cooling gas channel becoming a flow path of a cooling gas, instead of the cooling water channel111. For example, the base plate110may have a coolant passage through which a coolant such as cooling water and cooling gas passes. Also, the base plate110may be integrated with a heater configured to heat the electrostatic chuck120by a heat-generating electrode. Thereby, the base plate110can control a temperature of the electrostatic chuck120by heating from the heater and cooling from the coolant passage and can heat the adsorption object adsorbed to the electrostatic chuck120to a desired temperature. The electrostatic chuck120has a plurality of ceramic substrates including ceramic substrates121aand121b, and a sprayed portion123. In each of the ceramic substrates121aand121b, electrodes122aand122bare each embedded. The ceramic substrates121aand121bare each formed by firing a green sheet prepared using aluminum oxide, for example. At this time, by stacking and firing the green sheet and the electrodes122aand122b, the ceramic substrates121aand121bhaving the electrodes122aand122bembedded therein are formed. A thickness of each of the ceramic substrates121aand121bis, for example, about 3 to 7 mm, and preferably 4 to 5 mm. The ceramic substrates121aand121bare bonded to the base plate110with being adjacent to each other. Specifically, lower surfaces of the ceramic substrates121aand121bare bonded to an upper surface of the base plate110by the adhesive layer130. A peripheral edge portion of an upper surface of each of the ceramic substrates121aand121bis formed with a step, and the steps of the ceramic substrates121aand121bface each other to form a groove portion at a boundary portion of the ceramic substrates121aand121b. In the groove portion, the sprayed portion123is formed. The electrodes122aand122bare each embedded in each of the ceramic substrates121aand121b, and generate an electrostatic force when a voltage is applied, thereby adsorbing the adsorption object to the upper surfaces of the ceramic substrates121aand121b. The electrodes122aand122bof the ceramic substrates121aand121bare single electrodes with the same polarity. Thereby, for example, it is possible to adsorb an insulating substrate such as a glass substrate. However, the electrodes122aand122bof the adjacent ceramic substrates121aand121bmay also be configured as dipole electrodes with different polarities. The sprayed portion123is formed by spraying aluminum oxide (alumina), for example, into the groove portion formed by the facing steps of the peripheral edge portions of the upper surfaces of the ceramic substrates121aand121b. The sprayed portion123may also be formed by spraying yttrium oxide (yttria), for example, instead of alumina. In a case where the ceramic substrates121aand121bare formed of oxide or nitride other than alumina, the sprayed portion123may also be formed by spraying the same oxide or nitride as the material of the ceramic substrates121aand121b. Since the groove portion in which the sprayed portion123is formed has a sectional shape where a depth from the upper surfaces of the ceramic substrates121aand121bis 0.2 to 1 mm and a width is 1 to 2 mm, the sprayed portion123also has a sectional shape where a thickness is 0.2 to 1 mm and a width is 1 to 2 mm. Since side ends of the electrodes122aand122bare positioned on an inner side spaced by 1 to 2 mm from side surfaces of the ceramic substrates121aand121b, the sprayed portion123and the electrodes122aand122bdo not overlap each other, as seen from above. Since upper surfaces of the electrodes122aand122bare positioned at a depth spaced by 0.6 to 1.5 mm from the upper surfaces of the ceramic substrates121aand121b, the sprayed portion123and the electrodes122aand122bdo not overlap each other, as seen from side. The sprayed portion123seals the upper of the adjacent side surfaces of the ceramic substrates121aand121b, thereby preventing components of the adhesive from seeping from the adhesive layer130to the upper surfaces of the ceramic substrates121aand121b. Specifically, the sprayed portion123prevents components of the adhesive from seeping to the adsorption surface of the electrostatic chuck120, thereby preventing the adsorption object adsorbed on the adsorption surface from being defaced. The adhesive layer130is a layer of a silicone resin-based adhesive (silicone adhesive), and bonds the lower surface of the electrostatic chuck120to the upper surface of the base plate110. Specifically, the adhesive layer130bonds the lower surfaces of the plurality of ceramic substrates including the ceramic substrates121aand121bto the upper surface of the base plate110. The silicone adhesive that forms the adhesive layer130is also attached to the facing side surfaces of the adjacent ceramic substrates121aand121b. However, since the sprayed portion123is formed above the facing side surfaces of the adjacent ceramic substrates121aand121b, the components of the adhesive do not seep from the adhesive attached to the facing side surfaces of the ceramic substrates121aand121bto the upper surfaces of the ceramic substrates121aand121b. Subsequently, a manufacturing method of the substrate fixing device100configured as described above is described with reference to a flowchart shown inFIG.3. First, a plurality of ceramic substrates121that constitutes the electrostatic chuck120is prepared (step S101). Specifically, a plurality of green sheets where aluminum oxide is a main material is prepared, and an electrode122is formed on one surface of the green sheet. The electrode122may also be formed by screen printing a metal paste on the surface of the green sheet, for example. Then, the plurality of green sheets is stacked and sintered to prepare the ceramic substrate121. The ceramic substrate121has a layer of the electrode122formed therein, as shown inFIG.4, for example. A thickness of the ceramic substrate121is, for example, about 3 to 7 mm, and preferably 4 to 5 mm. The electrode122is formed at a depth of 0.8 to 1.7 mm from the upper surface of the ceramic substrate121, for example. In a polishing process to be described later, since the upper surface of the ceramic substrate121is polished together with the sprayed portion123, the electrode122shown inFIG.4is formed at a deeper position from the upper surface of the ceramic substrate121than the electrode122upon completion of the substrate fixing device100. Also, the side end of the electrode122is positioned on an inner side of 1 to 2 mm from the side surface of the ceramic substrate121, for example. When the plurality of (for example, four) ceramic substrates121is prepared, a step is formed at a peripheral edge portion of one surface of each of the ceramic substrates121(step S102). Specifically, for example, as shown inFIG.5, one side of the upper surface of the ceramic substrate121is formed with a step125having a dimension that does not overlap the electrode122, as seen from above and side. Specifically, a depth of the step125is, for example, 0.4 to 1.2 mm, and a width of a bottom surface of the step125is, for example, 0.5 to 1 mm. The step125is formed above a side surface of the ceramic substrate121, which is adjacent to another ceramic substrate121when the ceramic substrate121is bonded to the base plate110. Therefore, for example, when two side surfaces of the ceramic substrate121are adjacent to other ceramic substrates121, the step125is each formed above the two side surfaces. The plurality of ceramic substrates121each having the step125is bonded to the base plate110by the silicone adhesive (step S103). Specifically, for example, as shown inFIG.6, the ceramic substrates121aand121bare bonded with being aligned side by side on the upper surface of the base plate110by the silicone adhesive. The silicone adhesive that is used for bonding forms the adhesive layer130between the base plate110and the ceramic substrates121aand121b. The adjacent ceramic substrates121aand121bare arranged so that the steps125formed at the peripheral edge portions of the upper surfaces thereof face each other, and are bonded to the base plate110, and the groove portion126is formed by the facing steps125of the ceramic substrates121aand121b. Specifically, in the state where the plurality of ceramic substrates121is bonded to the base plate110, the groove portion126is formed at the boundary portion of the adjacent ceramic substrates121. Since the groove portion is formed by the facing steps125, a depth thereof is, for example, 0.4 to 1.2 mm, which is the same as the step125, and a width of a bottom surface is two times as large as the step125, for example, 1 to 2 mm. When the plurality of ceramic substrates121is bonded to the base plate110, the silicone adhesive leaked from the adhesive layer130to the bottom surface of the groove portion126is removed (step S104). Specifically, when the ceramic substrates121are bonded to the base plate110, some of the silicone adhesive is attached to the side surfaces of the ceramic substrates121and is pressed by the side surfaces of the adjacent ceramic substrates121, so that it is leaked to the bottom surface of the groove portion126. The silicone adhesive leaked to the bottom surface of the groove portion126is removed. At the same time, the silicone adhesive leaked from the lower surfaces of the ceramic substrates121to the outer peripheral portion of the upper surface of the base plate110is also removed. Then, alumina praying of spraying melted alumina particles into the groove portion126is performed (step S105). Specifically, melted and softened alumina particles are sprayed into the groove portion126and cooled and solidified, so that the sprayed portion123is formed as shown inFIG.7. The sprayed portion123seals the boundary portion of the adjacent ceramic substrates121aand121bin the vicinity of the upper surfaces of the ceramic substrates121aand121b. For this reason, the sprayed portion123prevents components of the silicone adhesive attached to the side surfaces of the ceramic substrates121aand121bfrom seeping to the upper surfaces of the ceramic substrates121aand121b. Note that, the material to be sprayed is not limited to alumina. For example, when yttria is sprayed to form the sprayed portion123, a plasma resistance of the sprayed portion123can be improved. Specifically, in a case where the substrate fixing device100is used for plasma etching of a wafer, for example, the ceramic substrates121and the sprayed portion123are exposed to the plasma. When the sprayed portion123is formed by spraying yttria, corrosion of the sprayed portion123due to the plasma can be suppressed. In addition, in a case where the ceramic substrates121are formed of oxide or nitride other than alumina, the sprayed portion123may also be formed by spraying the same oxide or nitride as the material of the ceramic substrates121. In this way, it is possible to reduce a temperature difference between the ceramic substrates121and the sprayed portion123, and to suppress lowering in heat-equalizing performance of the electrostatic chuck120having the ceramic substrates121and the sprayed portion123. After performing the alumina spraying, the surface of the sprayed portion123is polished together with the upper surfaces of the ceramic substrates121(step S106). Specifically, for example, as shown inFIG.8, a portion P having a thickness of, for example, 0.2 mm from the upper surfaces of the ceramic substrates121aand121bis polished, so that the upper surface of the sprayed portion123becomes flush with the upper surfaces of the ceramic substrates121aand121b. Specifically, the upper surfaces of the plurality of ceramic substrates121and the upper surface of the sprayed portion123are flush with each other, so that the adsorption surface of the electrostatic chuck120becomes a continuous planar surface. Since the upper portion of the sprayed portion123is polished together with the upper parts of the ceramic substrates121, a thickness of the sprayed portion123after the polishing becomes, for example, 0.2 to 1 mm. Then, as required, embossing processing is performed or a groove is formed on the adsorption surface of the electrostatic chuck120(i.e., the upper surfaces of the ceramic substrates121and the sprayed portion123), so that the substrate fixing device100having the electrostatic chuck120is completed. Since the substrate fixing device100has the electrostatic chuck120where the plurality of ceramic substrates121are aligned side by side, the substrate fixing device can adsorb and fix a relatively large-scale adsorption object. In addition, the sprayed portion123is formed at the boundary of the plurality of ceramic substrates121, so that the components of the silicone adhesive bonding the ceramic substrates121to the base plate110do not seep to the adsorption surface of the electrostatic chuck120. As a result, a smudge is prevented from being generated on the adsorption surface of the electrostatic chuck120, so that the adsorption object can be prevented from being defaced. Further, since the sprayed portion123is formed at the boundary of the plurality of ceramic substrates that constitutes the electrostatic chuck120, the temperature of the adsorption surface of the electrostatic chuck120can be made uniform, so that lowering in the heat-equalizing performance can be prevented. Specifically, when the substrate fixing device100having the sprayed portion123formed by the alumina spraying is placed on a hot plate of 60° C., a specific example of changes in temperature of the ceramic substrates121and the sprayed portion123is shown inFIG.9. As shown inFIG.9, the temperature difference between the ceramic substrate121and the sprayed portion123for each elapsed time after the substrate fixing device100is mounted on the hot plate of 60° C. is within a range of 0.1 to 0.4° C. Specifically, the temperature difference between the ceramic substrates121and the sprayed portion123constituting the electrostatic chuck120is small, and the temperature of the adsorption surface is uniform. For this reason, it is possible to equally heat the adsorption object adsorbed on the adsorption surface, so that it is possible to suppress lowering in heat-equalizing performance. As described above, according to the present embodiment, for the electrostatic chuck where the plurality of ceramic substrates is formed aligned side by side, the sprayed portion is formed by spraying alumina to the boundary of the adjacent ceramic substrates. For this reason, the boundary of the adjacent ceramic substrates on the adsorption surface of the electrostatic chuck is sealed, so that when the electrostatic chuck is bonded to the base plate by the silicone adhesive, the components of the silicone adhesive do not seep to the adsorption surface of the electrostatic chuck and the defacement of the adsorption object can be prevented. In addition, since the ceramic substrates and the sprayed portion constitute the adsorption surface of the electrostatic chuck, the temperature of the adsorption surface becomes uniform, so that lowering in heat-equalizing performance can be suppressed. In other words, it is possible to prevent defacement of the adsorption object without lowering the heat-equalizing performance. In the above embodiment, the sprayed portion123is formed at the boundary of the adjacent ceramic substrates121. However, the boundary of the ceramic substrates121may also be filled by PVD (Physical Vapor Deposition) or resin filling, instead of the spraying. Specifically, the boundary of the adjacent ceramic substrates121may be filled with, for example, yttrium oxide by PVD or may be filled with epoxy resin. In this way, the filled portion is formed at the boundary of the adjacent ceramic substrates121by the spraying, PVD or resin filling, so that the components of the silicone adhesive do not seep to the adsorption surface of the electrostatic chuck120, and therefore, the defacement of the adsorption object can be prevented. Further, in the embodiment, the square ceramic substrates121are arranged side by side, so that the electrostatic chuck120having a square adsorption surface is constituted. However, the shape of the electrostatic chuck120is not limited thereto. Specifically, fan-shaped ceramic substrates may be arranged side by side to constitute an electrostatic chuck having a circular adsorption surface. Also in this case, a peripheral edge portion corresponding to a radius of the fan shape of each ceramic substrate is formed with a step, and a groove portion formed by the facing steps of the adjacent ceramic substrates can be formed with a sprayed portion by alumina spraying, for example. This disclosure further encompasses various exemplary embodiments, for example, described below.[1] A manufacturing method of a substrate fixing device, the manufacturing method comprising: arranging side by side a plurality of ceramic substrates, each of which having a step formed at a peripheral edge portion of one surface and an electrode embedded therein, on a base plate so that the steps face each other; and filling a groove portion formed by the facing steps of the adjacent ceramic substrates.[2] The manufacturing method according to [1], wherein the filling comprises spraying oxide or nitride into the groove portion.[3] The manufacturing method according to [2], further comprising: polishing a surface of a sprayed portion formed by the spraying and one surface of each of the plurality of ceramic substrates. | 19,702 |
11862502 | In the figures:100: transfer substrate;200: controller;300: first electromagnetic portion;400: infrared emitting portion;500: second magnetic portion;600: semiconductor;800, sliding ball;900: target substrate;310: first electromagnetic baffle;510: suction disk;520: second magnetic baffle;530: driving electromagnetic baffle. DETAILED DESCRIPTION In order to enable those skilled in the art to better understand objects, technical solutions, and advantages of the disclosure, the solutions of the disclosure will be further described below through implementations with reference to the accompanying drawings. It will be appreciated that the implementations are described herein for the purpose of explaining the disclosure rather than limiting the disclosure. In the implementations and the scope of the disclosure, the article “a”, “an”, or “the” may generally represents one or more, unless otherwise specified. In addition, if there are descriptions on “first”, “second” and the like in implementations of the disclosure, the terms “first”, “second”, and the like are for descriptive purposes, and cannot be understood as indicating or implying relatively importance of technical features indicated or implicitly indicating the number of the technical features. Therefore, the features defined with “first”, “second”, or the like may explicitly or implicitly include at least one of the features. In addition, the technical solutions of various implementations can be combined with each other, if the combined implementations can be achieved by a person of ordinary skill in the art. When technical solutions of various implementations contradicts or the combined implementations cannot be realized, it should be considered that such combination of technical solutions does not exist and fall within the scope of protection claimed by the disclosure. In at least one implementation,FIG.1is a schematic view illustrating an operating state of a device for semiconductor transfer according to the disclosure. As illustrated inFIG.1, the device for semiconductor transfer includes a transfer substrate100, a controller200disposed on the transfer substrate100, multiple first electromagnetic portions300disposed on the transfer substrate100and electrically coupled to the controller200, multiple infrared emitting portions400, and multiple second magnetic portions500. Each infrared emitting portion is disposed on a surface of a corresponding first electromagnetic portion300and electrically coupled to the controller200. Each second magnetic portion500is movably disposed in a corresponding first electromagnetic portion300and configured to pick up a corresponding semiconductor600. The semiconductor600has magnetism. The transfer substrate100is capable of being moved to be above a target substrate900. The infrared emitting portion400is configured to emit infrared signals to position the semiconductor600on the target substrate900. The controller200is configured to output a first control current to the first electromagnetic portion300to cause the first electromagnetic portion300to generate an electromagnetic force, to control the second magnetic portion500to adjust a position of the picked-up semiconductor relative to a welding position on the target substrate, where adjusting the position of the picked-up semiconductor includes horizontal adjustment. In at least one implementation, the controller200is further configured to output a second control current to the second magnetic portion500, to cause the second magnetic portion500to pick up the semiconductor from the target substrate or place the semiconductor on the target substrate. FIG.2is a bottom view illustrating a device for semiconductor transfer according to the disclosure. Each first electromagnetic portion300includes multiple first electromagnetic baffles310that are movably disposed on the transfer substrate100. Each two adjacent first electromagnetic baffles310of the first electromagnetic portion300are perpendicular to each other and not directly connected. As illustrated inFIG.2, the first electromagnetic portion300includes four first electromagnetic baffles310. The four first electromagnetic baffles310are arranged around the second magnetic portion500. Since a distance between any one of the first electromagnetic baffles310and the second magnetic portion500is equal to that between another of the first electromagnetic baffles310and the second magnetic portion500, the second magnetic portion500disposed in the first electromagnetic portion300can move horizontally by means of magnetic force. As one example, continuing to refer toFIG.2, each second magnetic portion500includes a driving electromagnetic baffle530disposed on the transfer substrate and electrically coupled to the controller200, a suction disk510magnetically coupled to the driving electromagnetic baffle530, and multiple second magnetic baffles520fixedly arranged around the suction disk510. The second magnetic baffle520is configured to generate a magnetic force with the driving electromagnetic baffle530or the first electromagnetic baffle310, so as to drive the suction disk510to move back and forth in a vertical direction or a horizontal direction. As another example, the suction disk510is electrically coupled to the controller200and is controlled by the controller200to pick up the semiconductor600from the target substrate900or place the semiconductor600on the target substrate900. In one example, four second magnetic baffles520are disposed. Each two adjacent second magnetic baffles520are perpendicular to each other. Two opposite second magnetic baffles520mutually repel. For example, if the electromagnetic polarity of one second magnetic baffle520is N pole, the electromagnetic polarity of the other second magnetic baffle520is N pole. In one example, when it is necessary to pick up the semiconductors600from the target substrate, the transfer substrate100can be controlled to be moved to be above the target substrate, and then the infrared emitting portion400emits infrared signals to position the semiconductor600on the target substrate. It can be understood that the target substrate is correspondingly provided with an infrared receiver (not illustrated in the figures). After receiving the infrared signals emitted by the infrared emitting portion400, the infrared receiver feeds back position information of the semiconductor600on the target substrate. After the position of the semiconductor600is determined accurately, the transfer substrate100moves to the determined position. Thereafter, the controller200controls an output of a second control current to the second magnetic portion500, such that the driving electromagnetic baffle530in the second magnetic portion500is energized. The second magnetic baffle may be a permanent magnet, which is adsorbed on the driving electromagnetic baffle under the normal (open-circuit) condition. When it is necessary to enable the second magnetic baffle520to move downward, the controller200can output the second control current to cause that the driving electromagnetic baffle530and the second magnetic baffle520repel each other (changing a direction of the current can change the magnetic field of the electromagnet). Therefore, the driving electromagnetic baffle530can drive the second magnetic baffles520together with the suction disk to move downward (i.e., to move toward the semiconductor600on the target substrate). After the second magnetic baffles520approach the target substrate900and the suction disk510picks up the semiconductor600on the target substrate, the controller200controls the driving electromagnetic baffle530to be deenergized. It can be understood that the controller200can output another second control current having a different current direction to generate a magnetic field having two opposite electromagnetic polarities, so as to attract the second magnetic baffles. That is, after the semiconductor600is picked up, the second magnetic baffles520are re-adsorbed on the driving electromagnetic baffle530. It should be noted that the movement of the transfer substrate100and the infrared emitting portion400emitting infrared signals are both controlled by the controller200. The controller may be a current and logic controller. Furthermore, when the picked-up semiconductor600needs to be transferred to the target substrate, to accurately place the semiconductor600on the target substrate, for example, to accurately place the semiconductor600at the welding position on the target substrate, after the semiconductor600is positioned by the infrared emitting portion400and the infrared receiver on the target substrate, the controller200outputs a first control current to the first electromagnetic portion300, to cause the first electromagnetic portion300to be energized to generate an electromagnetic force, such that the second magnetic portion disposed in the first electromagnetic portion is moved horizontally. Therefore, a horizontal position of the semiconductor600relative to the target substrate can be adjusted, which can ensure that the semiconductor600can be accurately placed at the welding position on the target substrate. In one example, continuing to refer toFIG.2, the first electromagnetic baffles in the first electromagnetic portion300may be electrically coupled to the controller200separately, and thus the controller200can output first control currents of different intensities to the first electromagnetic baffles, respectively. For example, if it is necessary to adjust the semiconductor to the left by a distance, the controller can output a first control current to a first electromagnetic baffle310on the left side of the first electromagnetic portion, to allow the first electromagnetic baffle310on the left side of the first electromagnetic portion to attract the second magnetic portion500to the left by a distance. After the distance is adjusted, the controller controls the first electromagnetic baffle on the left side of the first electromagnetic portion to be deenergized. Similarly, when the semiconductor needs to be adjusted in other horizontal directions, the controller can output a first control current to another first electromagnetic baffle, such that the horizontal position of the semiconductor relative to the target substrate can be adjusted. After the horizontal position of the semiconductor600relative to the target substrate900is adjusted by means of the first electromagnetic portion300, the semiconductor600picked up by the second magnetic portion500and the welding position on the target substrate900are substantially at a same position on different horizontal planes. Thereafter, the controller200can output another second control current to the second magnetic portion500, to cause the driving electromagnetic baffle530to be energized, such that the second magnetic portion500can drive the semiconductor600to move downward (i.e. to move toward the target substrate900). After the second magnetic portion500approaches the target substrate900, the controller enables that the suction disk510cannot pick up the semiconductor600(the suction disk can be coupled to the controller separately), so that the semiconductor600can be accurately placed at the welding position on the target substrate900, and thus the transfer of the semiconductor600is completed. In can be understood that after the semiconductor600is transferred, it is possible to detect by an external device whether the semiconductor600is placed at the welding position on the target substrate900. If it is detected that the semiconductor600does not be placed at the welding position (i.e., there is a deviation between the position of the semiconductor600on the target substrate900and the welding position), the controller200can output yet another second control current to the second magnetic portion500so that the second magnetic portion500can pick up the semiconductor600again. The foregoing describes the process of picking up the semiconductor by the second magnetic portion in detail, which will not be repeated herein. Thereafter, the controller200controls the infrared emitting portion400to re-position the welding position on the target substrate900, to correct the deviation. In one example, the controller200outputs another first control current to the first electromagnetic portion300, such that the first electromagnetic portion300is energized and generates an electromagnetic force to cause the second magnetic portion500to drive the semiconductor600to be moved horizontally, to adjust a horizontal position of the semiconductor600, thereby correcting the deviation of the position of the semiconductor600relative to the welding position. Finally, the controller200outputs yet another second control current to the second magnetic portion500, to allow the second magnetic portion500to re-place the semiconductor600at the welding position, such that the correction of the position of the semiconductor600is completed. In at least one implementation, the transfer substrate100is provided with a sliding rail (not illustrated in the figures), and the first electromagnetic baffle310and the driving electromagnetic baffle530each are provided with a sliding ball800. The first electromagnetic baffle310and the driving electromagnetic baffle530are slidably coupled with the transfer substrate100, respectively. The sliding ball800is adsorbed on the sliding rail by magnetic force, and can slide freely on the sliding rail. It can be understood that the first electromagnetic baffle310does not slide in normal use. When it needs to adjust or move the position of the second magnetic portion500, the first electromagnetic baffle310may be moved away. As one example, the suction disk510is a magnet. The controller200controls the suction disk510to be energized to pick up the semiconductor600from the target substrate900. The semiconductor600is a magnetic semiconductor and can be attracted with the suction disk510. Similarly, when it is necessary to place the semiconductor on the target substrate900, the controller can control the suction disk to be deenergized or output a reverse magnetic field to enable the semiconductor to be separated from the suction disk, to place the semiconductor600on the target substrate900. As another example, the suction disk510is a gas adsorption device, such as a chuck. The controller200can also control the chuck to pick up or place the semiconductor600. Furthermore, the suction disk510can also be implemented as a manipulator. The manipulator can also pick up or place the semiconductor600. It should be understood that the suction disk510can also be achieved in many other manners to pick up or place the semiconductor600. In one example, the number of the first electromagnetic baffles310is the same as that of the second magnetic baffles520. Each first electromagnetic baffle310is arranged in parallel with a corresponding second magnetic baffle520. For example, when there are four first electromagnetic baffles310, four second electromagnetic baffles are provided correspondingly. In addition, parallel first electromagnetic baffle310and second magnetic baffle520repel each other. For example, if the polarity of the second magnetic baffle520is S pole, the polarity of the first electromagnetic baffle310outside the second magnetic baffle520is S pole. The first electromagnetic baffle310and the driving electromagnetic baffle530are electromagnets, each of which is composed of a magnetic core and a coil and can generate a magnetic field when a current flows to the coil. The second magnetic baffle520is an electromagnet or a permanent magnet. The permanent magnet refers to a magnet that can keep high remanence for a long time under the open-circuit condition. After being energized, the first electromagnetic baffle310or the driving electromagnetic baffle530causes the second magnetic baffles520to move in different directions by electromagnetic force. The infrared emitting portion400includes an infrared emitter (not illustrated in the figures). The infrared emitter can be arranged to be detachably coupled to the first electromagnetic portion300, to facilitate use and real-time adjustment of the infrared positioning of the semiconductor600on the target substrate900. As illustrated inFIG.3andFIG.4, the following illustrates an application scenario, to describe the operating process of the device for semiconductor transfer of the disclosure in more detail. 1. The target substrate includes a first target substrate910and a second target substrate920. The first target substrate is a growth substrate on which semiconductors600to be transferred are grown. The second target substrate is a substrate to be transferred that can receive the semiconductors to be transferred600. The second target substrate is provided with a welding position at which the semiconductor to be transferred600is welded. 2. When it is necessary to pick up the semiconductor600from the first target substrate, the controller200controls the transfer substrate100to be moved to be above the first target substrate. The controller200controls the infrared emitting portion400to emit infrared signals, to position the semiconductor600on the first target substrate. After the positioning is completed, the transfer substrate100is moved to the positioned position. The controller200outputs a second control current to the driving electromagnetic baffle530, such that the driving electromagnetic baffle530generates an electromagnetic force to drive the second magnetic baffles520to move downward, to pick up the semiconductor600from the first target substrate910. After the second magnetic portion picks up the semiconductor600, the controller200disables output of the second control current, and the second magnetic baffles520move upward to be adsorbed on the driving electromagnetic baffle, to complete the pick-up of the semiconductor600. 3. When it is necessary to transfer the picked up semiconductor600to the second target substrate, the controller200controls the transfer substrate100to be moved to be above the second target substrate. Thereafter, the controller200controls the infrared emitting portion400to position the welding position on the second target substrate (it can be understood that an infrared receiver is also provided at the welding position). After the positioning is completed, the controller200outputs a second control current to the driving electromagnetic baffle530, to cause the second magnetic baffles520to move downward, to place the semiconductor600at a corresponding welding position on the second target substrate, to complete the transfer of the semiconductor600. 4. The position of the semiconductor600transferred to the second target substrate is detected. If it is detected that there is a deviation between the position of the semiconductor600and the welding position, the deviation between the position of the semiconductor600and the welding position needs to be corrected. The controller200can output a second control current to the driving electromagnetic baffle530, to cause the suction disk510to pick up the semiconductor600from the second target substrate. Thereafter, the infrared emitting portion400re-positions the welding position on the second target substrate. After a new position is positioned, the controller200outputs a first control current to the first electromagnetic portion300to cause the first electromagnetic portion300to generate an electromagnetic force, to adjust a horizontal position of the second magnetic portion500provided therein. After the adjustment is completed, the controller200controls the driving electromagnetic baffle530to be energized to cause the second magnetic baffle520to re-place the semiconductor600on the second target substrate, to correct the position of the semiconductor600. In at least one implementation, an apparatus for semiconductor transfer is further provided according to the above device for semiconductor transfer. The apparatus include a target substrate. In one example, the target substrate is provided with an infrared receiver for feeding back position information of a semiconductor on the target substrate. The infrared receiver feeds back the position information of the semiconductor on the target substrate to the infrared emitting portion after receiving infrared signals emitted by the infrared emitting portion, to accurately determine the position of the semiconductor. In one example, the target substrate includes a first target substrate and a second target substrate. Semiconductors to be transferred are grown on the first target substrate. The second target substrate is configured to receive the semiconductors to be transferred, and electrodes corresponding to the semiconductors to be transferred are arranged on the second target substrate. In actual use, the transfer substrate picks up the semiconductor to be transferred from the first target substrate and then transfers the semiconductor to be transferred to corresponding electrodes at the welding position on the second target substrate for welding, thereby realizing the transfer of the semiconductor. The foregoing describes the transfer process in detail, which will not be repeated herein. In at least one implementation, a method for semiconductor transfer is further provided according to the device for semiconductor transfer described above. FIG.5is a flow chart illustrating a method for semiconductor transfer according to the disclosure. As illustrated inFIG.5, the method begins at S100. At S100, a transfer substrate is controlled to be moved to be above a target substrate. At S200, a semiconductor on the target substrate is positioned by emitting infrared signals by an infrared emitting portion. At S300, a controller outputs a first control current to a first electromagnetic portion, to cause the first electromagnetic portion to generate an electromagnetic force to control a second magnetic portion to adjust a position of the picked-up semiconductor relative to a welding position on the target substrate, where adjusting the position of the picked-up semiconductor includes horizontal adjustment. In at least one implementation, prior to the operations at S300, the following can be conducted. At S210, the controller outputs a second control current to a second magnetic portion, to cause the second magnetic portion to pick up the semiconductor from the target substrate or place the semiconductor on the target substrate. According to implementations, continuing to refer toFIG.1, when it is necessary to pick up the semiconductors600from the target substrate, the transfer substrate100can be controlled to be moved to be above the target substrate, and then the infrared emitting portion400emits infrared signals to position the semiconductor600on the target substrate. It can be understood that the target substrate is correspondingly provided with an infrared receiver (not illustrated in the figures). After receiving the infrared signals emitted by the infrared emitting portion400, the infrared receiver feeds back position information of the semiconductor600on the target substrate. After the position of the semiconductor600is determined accurately, the transfer substrate100moves to the determined position. Thereafter, the controller200controls an output of a second control current to the second magnetic portion500, such that the driving electromagnetic baffle530in the second magnetic portion500is energized. The second magnetic baffle may be a permanent magnet, which is adsorbed on the driving electromagnetic baffle under the normal (open-circuit) condition. When it is necessary to enable the second magnetic baffle520to move downward, the controller200can output the second control current to cause that the driving electromagnetic baffle530and the second magnetic baffle520repel each other (changing a direction of the current can change the magnetic field of the electromagnet). Therefore, the driving electromagnetic baffle530can drive the second magnetic baffles520together with the suction disk to move downward (i.e., to move toward the semiconductor600on the target substrate). After the second magnetic baffles520approach the target substrate900and the suction disk510picks up the semiconductor600on the target substrate, the controller200controls the driving electromagnetic baffle530to be deenergized. It can be understood that the controller200can output another second control current having a different current direction to generate a magnetic field having two opposite electromagnetic polarities, so as to attract the second magnetic baffles. That is, after the semiconductor600is picked up, the second magnetic baffles520are re-adsorbed on the driving electromagnetic baffle530. It should be noted that the movement of the transfer substrate100and the infrared emitting portion emitting infrared signals are both controlled by the controller200. The controller may be a current and logic controller. Furthermore, when the picked-up semiconductor600needs to be transferred to the target substrate, to accurately place the semiconductor600on the target substrate, for example, to accurately place the semiconductor600at the welding position on the target substrate, after the semiconductor600is positioned by the infrared emitting portion400and the infrared receiver on the target substrate, the controller200outputs a first control current to the first electromagnetic portion300, to cause the first electromagnetic portion300to be energized to generate an electromagnetic force, such that the second magnetic portion disposed in the first electromagnetic portion is moved horizontally. Therefore, a horizontal position of the semiconductor600relative to the target substrate can be adjusted, which can ensure that the semiconductor600can be accurately placed at the welding position on the target substrate. In one example, continuing to refer toFIG.2, the first electromagnetic baffles in the first electromagnetic portion300may be electrically coupled to the controller200separately, and thus the controller200can output first control currents of different intensities to the first electromagnetic baffles, respectively. For example, if it is necessary to adjust the semiconductor to the left by a distance, the controller can output a first control current to a first electromagnetic baffle310on the left side of the first electromagnetic portion, to allow the first electromagnetic baffle310on the left side of the first electromagnetic portion to attract the second magnetic portion500to the left by a distance. After the distance is adjusted, the controller controls the first electromagnetic baffle on the left side of the first electromagnetic portion to be deenergized. Similarly, when the semiconductor needs to be adjusted in other horizontal directions, the controller can output a first control current to another first electromagnetic baffle, such that the horizontal position of the semiconductor relative to the target substrate can be adjusted. After the horizontal position of the semiconductor600relative to the target substrate900is adjusted by means of the first electromagnetic portion300, the semiconductor600picked up by the second magnetic portion500and the welding position on the target substrate900are substantially at a same position on different horizontal planes. Thereafter, the controller200can output another second control current to the second magnetic portion500, to cause the driving electromagnetic baffle530to be energized, such that the second magnetic portion500can drive the semiconductor600to move downward (i.e. to move toward the target substrate900). After the second magnetic portion500approaches the target substrate900, the controller enables that the suction disk510cannot pick up the semiconductor600(the suction disk can be coupled to the controller separately), so that the semiconductor600can be accurately placed at the welding position on the target substrate900, and thus the transfer of the semiconductor600is completed. According to the device, apparatus, and method for semiconductor transfer provided herein, the transfer substrate is controlled to be moved to be above the target substrate. The infrared emitting portion emits infrared signals to position the semiconductor on the target substrate. After the second magnetic portion picks up the semiconductor from the target substrate, the controller outputs the first control current to the first electromagnetic portion to cause the first electromagnetic portion to generate an electromagnetic force, to control the second magnetic portion to adjust a position of the picked up semiconductor relative to the welding position on the target substrate, where adjusting the position of the picked-up semiconductor includes horizontal adjustment. In this way, it is possible to ensure the accurate alignment of the semiconductor and the target substrate in the transfer process. The device for semiconductor transfer provided herein can accurately pick up semiconductors with aid of an infrared function, and can also adjust the horizontal position of the semiconductors by magnetic force after picking up the semiconductor, thereby providing accurate positioning for the semiconductor when the semiconductor needs to be welded on the target substrate and avoiding inaccuracy of welding of the semiconductor. Those skilled in the art will easily think of other implementations of the disclosure after considering the specification and practicing the disclosure herein. The disclosure is intended to cover any variations, usages, or adaptive changes of the disclosure. These variations, usages, or adaptive changes follow the general principles of the disclosure and include common knowledge or conventional technical means in the technical field not disclosed in this disclosure. The description and embodiments are merely regarded as exemplary, and the scope and spirit of the disclosure depend on the claims. | 30,103 |
11862503 | DETAILED DESCRIPTION Embodiments of the invention are described herein with reference to the drawing figures. Persons of ordinary skill in the art will appreciate that the description and figures illustrate rather than limit the invention and that in general the figures are not drawn to scale for clarity of presentation. Such skilled persons will also realize that many more embodiments are possible by applying the inventive principles contained herein and that such embodiments fall within the scope of the invention which is not to be limited except by the appended claims. Some drawing figures may describe process flows for building devices. These process flows, which may be a sequence of steps for building a device, may have many structures, numerals and labels that may be common between two or more adjacent steps. In such cases, some labels, numerals and structures used for a certain step's figure may have been described in the previous steps' figures. Some embodiments of the invention may provide a new method for semiconductor device fabrication that may be highly desirable for custom products. Some embodiments of the invention may suggest the use of a re-programmable antifuse in conjunction with ‘Through Silicon Via’ to construct a new type of configurable logic, or as usually called, FPGA devices. Some embodiments of the invention may provide a solution to the challenge of high mask-set cost and low flexibility that exists in the current common methods of semiconductor fabrication. An additional illustrated advantage of some embodiments of the present invention may be that it could reduce the high cost of manufacturing the many different mask sets needed in order to provide a commercially viable logic family with a range of products each with a different set of master slices. Some embodiments of the invention may improve upon the prior art in many respects, including, for example, the structuring of the semiconductor device and methods related to the fabrication of semiconductor devices. Some embodiments of the invention may reflect the motivation to save on the cost of masks with respect to the investment that would otherwise have been necessary to put in place a commercially viable set of master slices. Some embodiments of the invention may also provide the ability to incorporate various types of memory blocks in the configurable device. Some embodiments of the invention may provide a method to construct a configurable device with the desired amount of logic, memory, I/Os, and analog functions. In addition, some embodiments of the invention may allow the use of repeating logic tiles that provide a continuous terrain of logic. Some embodiments of the invention may use a modular approach to construct various configurable systems with Through-Silicon-Via (TSV). Once a standard size and location of TSV has been defined one could build various configurable logic dies, configurable memory dies, configurable I/O dies and configurable analog dies which could be connected together to construct various configurable systems. In fact, these embodiments of the invention may allow mixing and matching among configurable dies, fixed function dies, and dies manufactured in different processes. Moreover in accordance with an embodiment of the invention, the integrated circuit system may include an I/O die that may be fabricated utilizing a different process than the process utilized to fabricate the configurable logic die. Further in accordance with an embodiment of the invention, the integrated circuit system may include at least two logic dies connected by the use of Through-Silicon-Via and wherein some of the Through-Silicon-Vias may be utilized to carry the system bus signal. Additionally there is a growing need to reduce the impact of inter-chip interconnects. In fact, interconnects may be now dominating IC performance and power. One solution to shorten interconnect may be to use a 3D IC. Currently, the only known way for general logic 3D IC is to integrate finished device one on top of the other by utilizing Through-Silicon-Vias as now called TSVs. The problem with TSVs may be that their large size, usually a few microns each, may severely limit the number of connections that can be made. Some embodiments of the invention may provide multiple alternatives to constructing a 3D IC wherein many connections may be made less than one micron in size, thus enabling the use of 3D IC technology for most device applications. Additionally some embodiments of the invention may offer new device alternatives by utilizing the proposed 3D IC technology FIG.1is a drawing illustration of a programmable device layers structure according to an alternative embodiment of the invention. In this alternative embodiment, there are two layers including antifuses. The first may be designated to configure the logic terrain and, in some cases, may also configure the logic clock distribution. The first antifuse layer could also be used to manage some of the power distribution to save power by not providing power to unused circuits. This layer could also be used to connect some of the long routing tracks and/or connections to the inputs and outputs of the logic cells. The device fabrication of the example shown inFIG.1may start with the semiconductor substrate, such as monocrystalline silicon substrate802, comprising the transistors used for the logic cells and also the first antifuse layer programming transistors. Thereafter, logic fabric/first antifuse layer804may be constructed, which may include multiple layers, such as Metal 1, dielectric, Metal 2, and sometimes Metal 3. These layers may be used to construct the logic cells and often I/O and other analog cells. In this alternative embodiment of the invention, a plurality of first antifuses may be incorporated in the isolation layer between metal 1 and metal 2 or in the isolation layer between metal 2 and metal 3 and the corresponding programming transistors could be embedded in the silicon substrate802being underneath the first antifuses. Interconnection layer806could include multiple layers of long interconnection tracks for power distribution and clock networks, or a portion thereof, in addition to structures already fabricated in the first few layers, for example, logic fabric/first antifuse layer804. Second antifuse layer807could include many layers, including the antifuse configurable interconnection fabric. It might be called the short interconnection fabric, too. If metal 6 and metal 7 are used for the strips of this configurable interconnection fabric then the second antifuse may be embedded in the dielectric layer between metal 6 and metal 7. The programming transistors and the other parts of the programming circuit could be fabricated afterward and be on top of the configurable interconnection fabric programming transistors810. The programming element could be a thin film transistor or other alternatives for over oxide transistors as was mentioned previously. In such case the antifuse programming transistors may be placed over the antifuse layer, which may thereby enable the configurable interconnect in second antifuse layer807or logic fabric/first antifuse layer804. It should be noted that in some cases it might be useful to construct part of the control logic for the second antifuse programming circuits, in the base layers such as silicon substrate802and logic fabric/first antifuse layer804. The final step may include constructing the connection to the outside812. The connection could be pads for wire bonding, soldering balls for flip chip, optical, or other connection structures such as those connection structures for TSV. In another alternative embodiment of the invention the antifuse programmable interconnect structure could be designed for multiple use. The same structure could be used as a part of the interconnection fabric, or as a part of the PLA logic cell, or as part of a Read Only Memory (ROM) function. In an FPGA product it might be desirable to have an element that could be used for multiple purposes. Having resources that could be used for multiple functions could increase the utility of the FPGA device. FIG.1Ais a drawing illustration of a programmable device layers structure according to another alternative embodiment of the invention. In this alternative embodiment, there may be an additional circuit of Foundation layer814connected by through silicon via connections816to the fabric/first antifuse layer804logic or antifuses. This underlying device of circuit of Foundation layer814may provide the programming transistor for the logic fabric/first antifuse layer804. In this way, the programmable device substrate diffusion, such as primary silicon layer802A, may not be prone to the cost penalty of the programming transistors for the logic fabric/first antifuse layer804. Accordingly the programming connection of the logic fabric/first antifuse layer804may be directed downward to connect to the underlying programming device of Foundation layer814while the programming connection to the second antifuse layer807may be directed upward to connect to the programming circuit programming transistors810. This could provide less congestion of the circuit internal interconnection routes. FIG.1Ais a cut illustration of a programmable device, with two antifuse layers. The programming transistors for the first logic fabric/first antifuse layer804could be prefabricated on Foundation layer814, and then, utilizing “smart-cut”, a single crystal, or mono-crystalline, transferred silicon layer1404may be transferred on which the primary programmable logic of primary silicon layer802A may be fabricated with advanced logic transistors and other circuits. Then multi-metal layers are fabricated including a lower layer of antifuses in logic fabric/first antifuse layer804, interconnection layer806and second antifuse layer807with its configurable interconnects. For the second antifuse layer807the programming transistors810could be fabricated also utilizing a second “smart-cut” layer transfer. The term layer transfer in the use herein may be defined as the technological process or method that enables the transfer of very fine layers of crystalline material onto a mechanical support, wherein the mechanical support may be another layer or substrate of crystalline material. For example, the “SmartCut” process, also used herein as the term ‘ion-cut’ process, together with wafer bonding technology, may enable a “Layer Transfer” whereby a thin layer of a single or mono-crystalline silicon wafer may be transferred from one wafer or substrate to another wafer or substrate. Other specific layer transfer processes may be described or referenced herein. The terms monocrystalline or mono-crystalline in the use herein of, for example, monocrystalline or mono-crystalline layer, material, or silicon, may be defined as “a single crystal body of crystalline material that contains no large-angle boundaries or twin boundaries as in ASTM F1241, also called monocrystal” and “an arrangement of atoms in a solid that has perfect periodicity (that is, no defects)” as in the SEMATECH dictionary. The terms single crystal and monocrystal are equivalent in the SEMATECH dictionary. The term single crystal in the use herein of, for example, single crystal silicon layer, single crystal layer, may be equivalently defined as monocrystalline. The term via in the use herein may be defined as “an opening in the dielectric layer(s) through which a riser passes, or in which the walls are made conductive; an area that provides an electrical pathway [connection path] from one metal layer to the metal layer above or below,” as in the SEMATECH dictionary. The term through silicon via (TSV) in the use herein may be defined as an opening in a silicon layer(s) through which an electrically conductive riser passes, and in which the walls are made isolative from the silicon layer; a riser that provides an electrical pathway [connection path] from one metal layer to the metal layer above or below. The term through layer via (TLV) in the use herein may be defined as an opening in a layer transferred layer(s) through which an electrically conductive riser passes, wherein the riser may pass through at least one isolating region, for example, a shallow trench isolation (STI) region in the transferred layer, may typically have a riser diameter of less than 200 nm, a riser that provides an electrical pathway [connection path] from one metal layer to the metal layer above or below. In some cases, a TLV may additionally pass thru an electrically conductive layer, and the walls may be made isolative from the conductive layer. The reference808in subsequent figures can be any one of a vast number of combinations of possible preprocessed wafers or layers containing many combinations of transfer layers that fall within the scope of the invention. The term “preprocessed wafer or layer” may be generic and reference number808when used in a drawing figure to illustrate an embodiment of the present invention may represent many different preprocessed wafer or layer types including but not limited to underlying prefabricated layers, a lower layer interconnect wiring, a base layer, a substrate layer, a processed house wafer, an acceptor wafer, a logic house wafer, an acceptor wafer house, an acceptor substrate, target wafer, preprocessed circuitry, a preprocessed circuitry acceptor wafer, a base wafer layer, a lower layer, an underlying main wafer, a foundation layer, an attic layer, or a house wafer. FIG.1Bis a drawing illustration of a generalized preprocessed wafer or layer808. The wafer or layer808may have preprocessed circuitry, such as, for example, logic circuitry, microprocessors, MEMS, circuitry comprising transistors of various types, and other types of digital or analog circuitry including, but not limited to, the various embodiments described herein. Preprocessed wafer or layer808may have preprocessed metal interconnects and may include copper or aluminum. The metal layer or layers of interconnect may be constructed of lower (less than about 400° C.) thermal damage resistant metals such as, for example, copper or aluminum, or may be constructed with refractory metals such as tungsten to provide high temperature utility at greater than about 400° C. The preprocessed metal interconnects may be designed and prepared for layer transfer and electrical coupling from preprocessed wafer or layer808to the layer or layers to be transferred. FIG.1Cis a drawing illustration of a generalized transfer layer809prior to being attached to preprocessed wafer or layer808. Transfer layer809may be attached to a carrier wafer or substrate during layer transfer. Preprocessed wafer or layer808may be called a target wafer, acceptor substrate, or acceptor wafer. The acceptor wafer may have acceptor wafer metal connect pads or strips designed and prepared for electrical coupling to transfer layer809. Transfer layer809may be attached to a carrier wafer or substrate during layer transfer. Transfer layer809may have metal interconnects designed and prepared for layer transfer and electrical coupling to preprocessed wafer or layer808. The metal interconnects now on transfer layer809may include copper or aluminum. Electrical coupling from transferred layer809to preprocessed wafer or layer808may utilize through layer vias (TLVs) as the connection path. Transfer layer809may be comprised of single crystal silicon, or mono-crystalline silicon, or doped mono-crystalline layer or layers, or other semiconductor, metal, and insulator materials, layers; or multiple regions of single crystal silicon, or mono-crystalline silicon, or doped mono-crystalline silicon, or other semiconductor, metal, or insulator materials. FIG.1Dis a drawing illustration of a preprocessed wafer or layer808A created by the layer transfer of transfer layer809on top of preprocessed wafer or layer808. The top of preprocessed wafer or layer808A may be further processed with metal interconnects designed and prepared for layer transfer and electrical coupling from preprocessed wafer or layer808A to the next layer or layers to be transferred. FIG.1Eis a drawing illustration of a generalized transfer layer809A prior to being attached to preprocessed wafer or layer808A. Transfer layer809A may be attached to a carrier wafer or substrate during layer transfer. Transfer layer809A may have metal interconnects designed and prepared for layer transfer and electrical coupling to preprocessed wafer or layer808A. FIG.1Fis a drawing illustration of a preprocessed wafer or layer808B created by the layer transfer of transfer layer809A on top of preprocessed wafer or layer808A. The top of preprocessed wafer or layer808B may be further processed with metal interconnects designed and prepared for layer transfer and electrical coupling from preprocessed wafer or layer808B to the next layer or layers to be transferred. FIG.1Gis a drawing illustration of a generalized transfer layer809B prior to being attached to preprocessed wafer or layer808B. Transfer layer809B may be attached to a carrier wafer or substrate during layer transfer. Transfer layer809B may have metal interconnects designed and prepared for layer transfer and electrical coupling to preprocessed wafer or layer808B. FIG.1His a drawing illustration of preprocessed wafer or layer808C created by the layer transfer of transfer layer809B on top of preprocessed wafer or layer808B. The top of preprocessed wafer or layer808C may be further processed with metal interconnect designed and prepared for layer transfer and electrical coupling from preprocessed wafer or layer808C to the next layer or layers to be transferred. FIG.1Iis a drawing illustration of preprocessed wafer or layer808C, a 3D IC stack, which may comprise transferred layers809A and809B on top of the original preprocessed wafer or layer808. Transferred layers809A and809B and the original preprocessed wafer or layer808may include transistors of one or more types in one or more layers, metallization such as, for example, copper or aluminum in one or more layers, interconnections to and between layers above and below, and interconnections within the layer. The transistors may be of various types that may be different from layer to layer or within the same layer. The transistors may be in various organized patterns. The transistors may be in various pattern repeats or bands. The transistors may be in multiple layers involved in the transfer layer. The transistors may be junction-less transistors or recessed channel array transistors. Transferred layers809A and809B and the original preprocessed wafer or layer808may further comprise semiconductor devices such as resistors and capacitors and inductors, one or more programmable interconnects, memory structures and devices, sensors, radio frequency devices, or optical interconnect with associated transceivers. Transferred layers809A and809B and the original preprocessed wafer or layer808may further include isolation layers, such as, for example, silicon and/or carbon containing oxides and/or low-k dielectrics and/or polymers, which may facilitate oxide to oxide wafer or substrate bonding and may electrically isolate, for example, one layer, such as transferred layer809A, from another layer, such as preprocessed wafer or layer808. The terms carrier wafer or carrier substrate may also be called holder wafer or holder substrate. The terms carrier wafer or substrate used herein may be a wafer, for example, a monocrystalline silicon wafer, or a substrate, for example, a glass substrate, used to hold, flip, or move, for example, other wafers, layers, or substrates, for further processing. The attachment of the carrier wafer or substrate to the carried wafer, layer, or substrate may be permanent or temporary. This layer transfer process can be repeated many times, thereby creating preprocessed wafers comprising many different transferred layers which, when combined, can then become preprocessed wafers or layers for future transfers. This layer transfer process may be sufficiently flexible that preprocessed wafers and transfer layers, if properly prepared, can be flipped over and processed on either side with further transfers in either direction as a matter of design choice. The thinner the transferred layer, the smaller the through layer via (TLV) diameter obtainable, due to the potential limitations of manufacturable via aspect ratios. Thus, the transferred layer may be, for example, less than about 2 microns thick, less than about 1 micron thick, less than about 0.4 microns thick, less than about 200 nm thick, or less than about 100 nm thick. The TLV diameter may be less than about 400 nm, less than about 200 nm, less than about 80 nm, less than about 40 nm, or less than about 20 nm. The thickness of the layer or layers transferred according to some embodiments of the present invention may be designed as such to match and enable the best obtainable lithographic resolution capability of the manufacturing process employed to create the through layer vias or any other structures on the transferred layer or layers. In many of the embodiments of the invention, the layer or layers transferred may be of a crystalline material, for example, mono-crystalline silicon, and after layer transfer, further processing, such as, for example, plasma/RIE or wet etching, may be done on the layer or layers that may create islands or mesas of the transferred layer or layers of crystalline material, for example, mono-crystalline silicon, the crystal orientation of which has not changed. Thus, a mono-crystalline layer or layers of a certain specific crystal orientation may be layer transferred and then processed whereby the resultant islands or mesas of mono-crystalline silicon have the same crystal specific orientation as the layer or layers before the processing. After this processing, the resultant islands or mesas of crystalline material, for example, mono-crystalline silicon, may be still referred to herein as a layer, for example, mono-crystalline layer, layer of mono-crystalline silicon, and so on. Persons of ordinary skill in the art will appreciate that the illustrations inFIG.1through II are exemplary only and are not drawn to scale. Such skilled persons will further appreciate that many variations may be possible such as, for example, the preprocessed wafer or layer808may act as a base or substrate layer in a wafer transfer flow, or as a preprocessed or partially preprocessed circuitry acceptor wafer in a wafer transfer process flow. Moreover, layer transfer techniques, such as ‘ion-cut’ that may form a layer transfer demarcation plane by ion implantation of hydrogen molecules or atoms, or any other layer transfer technique described herein or utilized in industry, may be utilized in the generalizedFIG.1flows and applied throughout herein. Furthermore, metal interconnect strips may be formed on the acceptor wafer and/or transferred layer to assist the electrical coupling of circuitry between the two layers, and may utilize TLVs. Many other modifications within the scope of the illustrated embodiments of the invention described herein will suggest themselves to such skilled persons after reading this specification. Thus the invention is to be limited only by the appended claims. A technology for such underlying circuitry may be to use the “SmartCut” process. The “SmartCut” process is a well understood technology used for fabrication of SOI wafers. The “SmartCut” process, together with wafer bonding technology, may enable a “Layer Transfer” whereby a thin layer of a single or mono-crystalline silicon wafer may be transferred from one wafer to another wafer. The “Layer Transfer” could be done at less than about 400° C. and the resultant transferred layer could be even less than about 100 nm thick. The transferred layer thickness may typically be about 100 nm, and may be a thin as about 5 nm in currently demonstrated fully depleted SOI (FDSOI) wafer manufacturing by Soitec. In most applications described herein in this invention the transferred layer thickness may be less than about 400 nm and may be less than about 200 nm for logic applications. The process with some variations and under different names may be commercially available by two companies, namely, Soitec (Crolles, France) and SiGen—Silicon Genesis Corporation (San Jose, CA). A room temperature wafer bonding process utilizing ion-beam preparation of the wafer surfaces in a vacuum has been recently demonstrated by Mitsubishi Heavy Industries Ltd., Tokyo, Japan. This process may allow for room temperature layer transfer. Alternatively, other technology may also be used. For example, other technologies may be utilized for layer transfer as described in, for example, IBM's layer transfer method shown at IEDM 2005 by A. W. Topol, et. al. The IBM's layer transfer method employs a SOI technology and utilizes glass handle wafers. The donor circuit may be high-temperature processed on an SOI wafer, temporarily bonded to a borosilicate glass handle wafer, backside thinned by chemical mechanical polishing of the silicon and then the Buried Oxide (BOX) is selectively etched off. The now thinned donor wafer may be subsequently aligned and low-temperature oxide-to-oxide bonded to the acceptor wafer topside. A low temperature release of the glass handle wafer from the thinned donor wafer may be performed, and then through bond via connections may be made. Additionally, epitaxial liftoff (ELO) technology as shown by P. Demeester, et. al, of IMEC in Semiconductor Science Technology 1993 may be utilized for layer transfer. ELO may make use of the selective removal of a very thin sacrificial layer between the substrate and the layer structure to be transferred. The to-be-transferred layer of GaAs or silicon may be adhesively ‘rolled’ up on a cylinder or removed from the substrate by utilizing a flexible carrier, such as, for example, black wax, to bow up the to-be-transferred layer structure when the selective etch, such as, for example, diluted Hydrofluoric (HF) Acid, may etch the exposed release layer, such as, for example, silicon oxide in SOI or AlAs. After liftoff, the transferred layer may then be aligned and bonded to the acceptor substrate or wafer. The manufacturability of the ELO process for multilayer layer transfer use was recently improved by J. Yoon, et. al., of the University of Illinois at Urbana-Champaign as described in Nature May 20, 2010. Canon developed a layer transfer technology called ELTRAN—Epitaxial Layer TRANsfer from porous silicon. ELTRAN may be utilized. The Electrochemical Society Meeting abstract No. 438 from year 2000 and the JSAP International July 2001 paper show a seed wafer being anodized in an HF/ethanol solution to create pores in the top layer of silicon, the pores may be treated with a low temperature oxidation and then high temperature hydrogen annealed to seal the pores. Epitaxial silicon may then be deposited on top of the porous silicon and then oxidized to form the SOI BOX. The seed wafer may be bonded to a handle wafer and the seed wafer may be split off by high pressure water directed at the porous silicon layer. The porous silicon may then be selectively etched off leaving a uniform silicon layer. FIG.14is a drawing illustration of a layer transfer process flow. In another illustrative embodiment of the invention, “Layer-Transfer” may be used for construction of the underlying circuitry of Foundation layer814. Wafer1402may include a monocrystalline silicon wafer that was processed to construct the underlying circuitry. The wafer1402could be of the most advanced process or more likely a few generations behind. It could include the programming circuits of Foundation layer814and other useful structures and may be a preprocessed CMOS silicon wafer, or a partially processed CMOS, or other prepared silicon or semiconductor substrate. Wafer1402may also be called an acceptor substrate or a target wafer. An oxide layer1412may then be deposited on top of the wafer1402and thereafter may be polished for better planarization and surface preparation. A donor wafer1406may then be brought in to be bonded to wafer1402. The surfaces of both donor wafer1406and wafer1402may be pre-processed for low temperature bonding by various surface treatments, such as an RCA pre-clean that may comprise dilute ammonium hydroxide or hydrochloric acid, and may include plasma surface preparations to lower the bonding energy and enhance the wafer to wafer bond strength. The donor wafer1406may be pre-prepared for “SmartCut” by an ion implant of an atomic species, such as H+ ions, at the desired depth to prepare the SmartCut line1408. SmartCut line1408may also be called a layer transfer demarcation plane, shown as a dashed line. The SmartCut line1408or layer transfer demarcation plane may be formed before or after other processing on the donor wafer1406. Donor wafer1406may be bonded to wafer1402by bringing the donor wafer1406surface in physical contact with the wafer1402surface, and then applying mechanical force and/or thermal annealing to strengthen the oxide to oxide bond. Alignment of the donor wafer1406with the wafer1402may be performed immediately prior to the wafer bonding. Acceptable bond strengths may be obtained with bonding thermal cycles that do not exceed about 400° C. After bonding the two wafers a SmartCut step may be performed to cleave and remove the top portion1414of the donor wafer1406along the SmartCut line1408. The cleaving may be accomplished by various applications of energy to the SmartCut line1408, or layer transfer demarcation plane, such as a mechanical strike by a knife or jet of liquid or jet of air, or by local laser heating, by application of ultrasonic or megasonic energy, or other suitable methods. The result may be a 3D wafer1410which may include wafer1402with a transferred silicon layer1404of mono-crystalline silicon, or multiple layers of materials. Transferred silicon layer1404may be polished chemically and mechanically to provide a suitable surface for further processing. Transferred silicon layer1404could be quite thin at the range of about 50-200 nm. The described flow may be called “layer transfer”. Layer transfer may be commonly utilized in the fabrication of SOI—Silicon On Insulator—wafers. For SOI wafers the upper surface may be oxidized so that after “layer transfer” a buried oxide—BOX—may provide isolation between the top thin mono-crystalline silicon layer and the bulk of the wafer. The use of an implanted atomic species, such as Hydrogen or Helium or a combination, to create a cleaving plane as described above may be referred to in this document as “SmartCut” or “ion-cut” and may be generally the illustrated layer transfer method. Persons of ordinary skill in the art will appreciate that the illustrations inFIG.14are exemplary only and are not drawn to scale. Such skilled persons will further appreciate that many variations may be possible such as, for example, a heavily doped (greater than 1e20 atoms/cm3) boron layer or silicon germanium (SiGe) layer may be utilized as an etch stop either within the ion-cut process flow, wherein the layer transfer demarcation plane may be placed within the etch stop layer or into the substrate material below, or the etch stop layers may be utilized without an implant cleave process and the donor wafer may be, for example, etched away until the etch stop layer is reached. Such skilled persons will further appreciate that the oxide layer within an SOI or GeOI donor wafer may serve as the etch stop layer, and hence one edge of the oxide layer may function as a layer transfer demarcation plane. Moreover, the dose and energy of the implanted specie or species may be uniform across the surface area of the wafer or may have a deliberate variation, including, for example, a higher dose of hydrogen at the edges of a monocrystalline silicon wafer to promote cleaving. Many other modifications within the scope of the illustrated embodiments of the invention will suggest themselves to such skilled persons after reading this specification. Thus the invention is to be limited only by the appended claims. Now that a “layer transfer” process may be used to bond a thin mono-crystalline silicon layer transferred silicon layer1404on top of the preprocessed wafer1402, a standard process could ensue to construct the rest of the desired circuits as illustrated inFIG.1A, starting with primary silicon layer802A on the transferred silicon layer1404. The lithography step may use alignment marks on wafer1402so the following circuits of primary silicon layer802A and logic fabric/first antifuse layer804and so forth could be properly connected to the underlying circuits of Foundation layer814. An aspect that should be accounted for is the high temperature that may be needed for the processing of circuits of primary silicon layer802A. The pre-processed circuits on wafer1402may need to withstand this high temperature associated with the activation of the semiconductor transistors of primary silicon layer802A fabricated on the transferred silicon layer1404. Those circuits on wafer1402may include transistors and local interconnects of poly-crystalline silicon (polysilicon or poly) and some other type of interconnection that could withstand high temperature such as tungsten. A processed wafer that can withstand subsequent processing of transistors on top at high temperatures may be a called the “Foundation” or a foundation wafer, layer or circuitry. An illustrated advantage of using layer transfer for the construction of the underlying circuits may include having the transferred silicon layer1404be very thin which may enable the through silicon via connections816, or through layer vias (TLVs), to have low aspect ratios and be more like normal contacts, which could be made very small and with minimum area penalty. The thin transferred layer may also allow conventional direct through-layer alignment techniques to be performed, thus increasing the density of through silicon via connections816. An additional alternative embodiment of the invention is where the foundation wafer1402layer may be pre-processed to carry a plurality of back bias voltage generators. A known challenge in advanced semiconductor logic devices may be die-to-die and within-a-die parameter variations. Various sites within the die might have different electrical characteristics due to dopant variations and such. The parameters that can affect the variation may include the threshold voltage of the transistor. Threshold voltage variability across the die may be mainly due to channel dopant, gate dielectric, and critical dimension variability. This variation may become profound in sub 45 nm node devices. The usual implication may be that the design should be done for the worst case, resulting in a quite significant performance penalty. Alternatively complete new designs of devices are being proposed to solve this variability problem with significant uncertainty in yield and cost. A possible solution may be to use localized back bias to drive upward the performance of the worst zones and allow better overall performance with minimal additional power. The foundation-located back bias could also be used to minimize leakage due to process variation. FIG.5Ais a topology drawing illustration of back bias circuitry. The foundation wafer1402layer may carry back bias circuits1711to allow enhancing the performance of some of the zones1710on the primary device which otherwise will have lower performance. FIG.5Bis a drawing illustration of back bias circuits. A back bias level control circuit1720may be controlling the oscillators1727and1729to drive the voltage generators1721. The negative voltage generator1725may generate the desired negative bias which may be connected to the primary circuit by connection1723to back bias the N-channel Metal-Oxide-Semiconductor (NMOS) transistors1732on the primary silicon transferred silicon layer1404. The positive voltage generator1726may generate the desired negative bias which may be connected to the primary circuit by connection1724to back bias the P-channel Metal-Oxide-Semiconductor (PMOS) transistors1734on the primary silicon transferred silicon layer1404. The setting of the proper back bias level per zone may be done in the initiation phase. It could be done by using external tester and controller or by on-chip self test circuitry. As an example, a non volatile memory may be used to store the per zone back bias voltage level so the device could be properly initialized at power up. Alternatively a dynamic scheme could be used where different back bias level(s) are used in different operating modes of the device. Having the back bias circuitry in the foundation allows better utilization of the primary device silicon resources and less distortion for the logic operation on the primary device. FIG.5Cillustrates an alternative circuit function that may fit well in the “Foundation.” In many IC designs it may be desired to integrate power control to reduce either voltage to sections of the device or to substantially totally power off these sections when those sections may not be needed or in an almost ‘sleep’ mode. In general such power control may be best done with higher voltage transistors. Accordingly a power control circuit cell17C02may be constructed in the Foundation. Such power control circuit cell17C02may have its own higher voltage supply and control or regulate supply voltage for sections17C10and17C08in the “Primary” device. The control may come from the primary device17C16and be managed by control circuit17C04in the Foundation. In another alternative the foundation substrate wafer1402could additionally carry SRAM cells as illustrated inFIG.6. The SRAM cells1802pre-fabricated on the underlying substrate wafer1402could be connected1812to the primary logic circuit1806,1808built on transferred silicon layer1404. As mentioned before, the layers built on transferred silicon layer1404could be aligned to the pre-fabricated structure on the underlying substrate wafer1402so that the logic cells could be properly connected to the underlying RAM cells. FIG.7Ais a drawing illustration of an underlying I/O. The foundation wafer1402could also be preprocessed to carry the I/O circuits or part of it, such as the relatively large transistors of the output drive1912. Additionally TSV in the foundation could be used to bring the I/O connection1914all the way to the back side of the foundation. FIG.7Bis a drawing illustration of a side “cut” of an integrated device according to an embodiment of the present invention. The Output Driver may be illustrated by PMOS and NMOS output transistors19B06coupled through TSV19B10to connect to a backside pad or pad bump19B08. The connection material used in the foundation wafer1402can be selected to withstand the temperature of the following process constructing the full device on transferred silicon layer1404as illustrated inFIG.1A—802,804,806,807,810,812, such as tungsten. The foundation could also carry the input protection circuit1916connecting the pad or pad bump19B08to the primary silicon circuitry, such as input logic1920, in the primary circuits or buffer1922. An additional embodiment may use TSVs in the foundation such as TSV19B10to connect between wafers to form 3D Integrated Systems. In general each TSV may take a relatively large area, typically a few square microns. When the need is for many TSVs, the overall cost of the area for these TSVs might be high if the use of that area for high density transistors is substantially precluded. Pre-processing these TSVs on the donor wafer on a relatively older process line may significantly reduce the effective costs of the 3D TSV connections. The connection1924to the primary silicon circuitry, such as input logic1920, could be then made at the minimum contact size of few tens of square nanometers, which may be two orders of magnitude lower than the few square microns needed by the TSVs. Those of ordinary skill in the art will appreciate thatFIG.7Bis for illustration only and is not drawn to scale. Such skilled persons will understand there are many alternative embodiments and component arrangements that could be constructed using the inventive principles shown and thatFIG.7Bis not limiting in any way. FIG.19Cdemonstrates a 3D system including three dice19C10,19C20and19C30coupled together with TSVs19C12,19C22and19C32similar to TSV19B10as described in association withFIG.7A. The stack of three dice may utilize TSV in the Foundations19C12,19C22, and19C32for the 3D interconnect which may allow for minimum effect or silicon area loss of the Primary silicon19C14,19C24and19C34connected to their respective Foundations with minimum size via connections. The three die stacks may be connected to a PC Board using bumps19C40connected to the bottom die TSVs19C32. Those of ordinary skill in the art will appreciate thatFIG.7Cis for illustration only and is not drawn to scale. Such skilled persons will understand there are many alternative embodiments and component arrangements that could be constructed using the inventive principles shown and thatFIG.7Cis not limiting in any way. For example, a die stack could be placed in a package using flip chip bonding or the bumps19C40could be replaced with bond pads and the part flipped over and bonded in a conventional package with bond wires. FIG.7Dillustrates a 3D IC processor and DRAM system. A well known problem in the computing industry is the “memory wall” that may relate to the speed the processor can access the DRAM. The prior art proposed solution was to connect a DRAM stack using TSV directly on top of the processor and use a heat spreader attached to the processor back to remove the processor heat. But in order to do so, a special via needs to go “through DRAM” so that the processor I/Os and power could be connected. Having many processor-related ‘through-DRAM vias” may lead to a few severe potential disadvantages. First, it may reduce the usable silicon area of the DRAM by a few percent. Second, it may increase the power overhead by a few percent. Third, it may require that the DRAM design be coordinated with the processor design which may be very commercially challenging. The embodiment ofFIG.7Dillustrates one solution to mitigate the above mentioned disadvantages by having a foundation with TSVs as illustrated inFIGS.7B and19C. The use of the foundation and primary structure may enable the connections of the processor without going through the DRAM. InFIG.7Dthe processor I/Os and power may be coupled from the face-down microprocessor active area19D14—the primary layer, by vias19D08through heat spreader substrate19D04to an interposer19D06. Heat spreader19D12, heat spreader substrate19D04, and heat sink19D02may be used to spread the heat generated on the microprocessor active area19D14. TSVs19D22through the Foundation19D16may be used for the connection of the DRAM stack19D24. The DRAM stack may include multiple thinned DRAM chips19D18interconnected by TSV19D20. Accordingly the DRAM stack may not need to pass through the processor I/O and power planes and could be designed and produced independent of the processor design and layout. The thinned DRAM chip19D18substantially closest to the Foundation19D16may be designed to connect to the Foundation TSVs19D22, or a separate ReDistribution Layer (or RDL, not shown) may be added in between, or the Foundation19D16could serve that function with preprocessed high temperature interconnect layers, such as Tungsten, as described previously. And the processor's active area may not be compromised by having TSVs through it as those are done in the Foundation19D16. Alternatively the Foundation TSVs19D22could be used to pass the processor I/O and power to the heat spreader substrate19D04and to the interposer19D06while the DRAM stack would be coupled directly to the microprocessor active area19D14. Persons of ordinary skill in the art will appreciate that many more combinations are possible within the scope of the disclosed embodiments illustrating the invention. FIG.7Eillustrates another embodiment of the present invention wherein the DRAM stack19D24may be coupled by wire bonds19E24to an RDL (ReDistribution Layer)19E26that may couple the DRAM to the Foundation vias19D22, and thus may couple them to the face-down microprocessor active area19D14. In yet another embodiment, custom SOI wafers may be used where NuVias19F00may be processed by the wafer supplier. NuVias19F00may be conventional TSVs that may be 1 micron or larger in diameter and may be preprocessed by an SOI wafer vendor. This is illustrated inFIG.7Fwith handle wafer19F02and Buried Oxide (BOX)19F01. The handle wafer19F02may typically be many hundreds of microns thick, and the BOX19F01may typically be a few hundred nanometers thick. The Integrated Device Manufacturer (IDM) or foundry may then process NuContacts19F03to connect to the NuVias19F00. NuContacts may be conventionally dimensioned contacts etched through the thin silicon19F05and the BOX19F01of the SOI and filled with metal. The NuContact diameter DNuContact19F04, inFIG.7Fmay then be processed having diameters in the tens of nanometer range. The prior art of construction with bulk silicon wafers19G00as illustrated inFIG.7Gtypically may have a TSV diameter, DTSV_prior_art19G02, in the micron range. The reduced dimension of NuContact DNuContact19F04inFIG.7Fmay have implications for semiconductor designers. The use of NuContacts may provide reduced die size penalty of through-silicon connections, reduced handling of very thin silicon wafers, and reduced design complexity. The arrangement of TSVs in custom SOI wafers can be based on a high-volume integrated device manufacturer (IDM) or foundry's request, or may be based on a commonly agreed industry standard. A process flow as illustrated inFIG.7Hmay be utilized to manufacture these custom SOI wafers. Such a flow may be used by a wafer supplier. A silicon donor wafer19H04may be taken and its surface19H05may be oxidized. An atomic species, such as, for example, hydrogen, may then be implanted at a certain depth19H06. Oxide-to-oxide bonding as described in other embodiments may then be used to bond this wafer with an acceptor wafer19H08having pre-processed NuVias19H07. The NuVias19H07may be constructed with a conductive material, such as tungsten or doped silicon, which can withstand high-temperature processing. An insulating barrier, such as, for example, silicon oxide, may be utilized to electrically isolate the NuVias19H07from the silicon of the acceptor wafer19H08. Alternatively, the wafer supplier may construct NuVias19H07with silicon oxide. The integrated device manufacturer or foundry may etch out the silicon oxide after the high-temperature (more than about 400° C.) transistor fabrication may be complete and may replace this oxide with a metal such as copper or aluminum. This process may allow a low-melting point, but highly conductive metal, such as, for example, copper or aluminum to be used. Following the bonding, a portion19H10of the silicon donor wafer19H04may be cleaved at19H06and then chemically mechanically polished as described in other embodiments. FIG.7Jdepicts another technique to manufacture custom SOI wafers. A standard SOI wafer with substrate19J01, BOX19F01, and top silicon layer19J02may be taken and NuVias19F00may be formed from the back-side up to the oxide layer. This technique might have a thicker BOX19F01than a standard SOI process. FIG.7Idepicts how a custom SOI wafer may be used for 3D stacking of a processor19I09and a DRAM19I10. In this configuration, a processor's power distribution and I/O connections may pass from the substrate19I12, go through the DRAM19I10and then connect onto the processor19I09. The above described technique inFIG.7Fmay result in a small contact area on the DRAM active silicon, which may be very convenient for this processor-DRAM stacking application. The transistor area lost on the DRAM die due to the through-silicon connection19I13and19I14may be very small due to the tens of nanometer diameter of NuContact19I13in the active DRAM silicon. It may be difficult to design a DRAM when large areas in its center may be blocked by large through-silicon connections. Having small size through-silicon connections may help tackle this issue. Persons of ordinary skill in the art will appreciate that this technique may be applied to building processor-SRAM stacks, processor-flash memory stacks, processor-graphics-memory stacks, any combination of the above, and any other combination of related integrated circuits such as, for example, SRAM-based programmable logic devices and their associated configuration ROM/PROM/EPROM/EEPROM devices, ASICs and power regulators, microcontrollers and analog functions, etc. Additionally, the silicon on insulator (SOI) may be a material such as polysilicon, GaAs, GaN, Ge, etc. on an insulator. Such skilled persons will appreciate that the applications of NuVia and NuContact technology are extremely general and the scope of the illustrated embodiments of the invention is to be limited only by the appended claims. FIG.8is a drawing illustration of the second layer transfer process flow. The primary processed wafer2002may include all the prior layers—814,802,804,806, and807. Layer2011may include metal interconnect for said prior layers. An oxide layer2012may then be deposited on top of the wafer2002and then be polished for better planarization and surface preparation. A donor wafer2006(or cleavable wafer as labeled in the drawing) may be then brought in to be bonded to2002. The donor wafer2006may be pre-processed to include the semiconductor layers2019which may be later used to construct the top layer of progranmming transistors810as an alternative to the TFT transistors. The donor wafer2006may also be prepared for “SmartCut” by ion implant of an atomic species, such as H+, at the desired depth to prepare the SmartCut line2008. After bonding the two wafers a SmartCut step may be performed to pull out the top portion2014of the donor wafer2006along the ion-cut layer/plane2008. This donor wafer may now also be processed and reused for more layer transfers. The result may be a 3D wafer2010which may include wafer2002with an added transferred layer2004of single crystal silicon pre-processed to carry additional semiconductor layers. The transferred layer2004could be quite thin at the range of about 10-200 nm. Utilizing “SmartCut” layer transfer may provide single crystal semiconductors layer on top of a pre-processed wafer without heating the pre-processed wafer to more than 400° C. There may be a few alternative methods to construct the top transistors precisely aligned to the underlying pre-fabricated layers such as pre-processed wafer or layer808, utilizing “SmartCut” layer transfer and not exceeding the temperature limit, typically about 400° C., of the underlying pre-fabricated structure, which may include low melting temperature metals or other construction materials such as, for example, aluminum or copper. As the layer transfer may be less than about 200 nm thick, then the transistors defined on it could be aligned precisely to the top metal layer of the pre-processed wafer or layer808as may be needed and those transistors may have state of the art layer to layer misalignment capability, for example, less than about 40 nm misalignment or less than about 4 nm misalignment, as well as through layer via, or layer to layer metal connection, diameters of less than about 50 nm, or even less than about 20 nm. The thinner the transferred layer, the smaller the through layer via diameter obtainable, due to the potential limitations of manufacturable via aspect ratios. The transferred layer may be, for example, less than about 2 microns thick, less than about 1 micron thick, less than about 0.4 microns thick, less than about 200 nm thick, or less than about 100 nm thick. One alternative method may be to have a thin layer transfer of single crystal silicon which will be used for epitaxial Ge crystal growth using the transferred layer as the seed for the germanium. Another alternative method may be to use the thin layer transfer of mono-crystalline silicon for epitaxial growth of GexSi1-x. The percent Ge in Silicon of such layer may be determined by the transistor specifications of the circuitry. Prior art have presented approaches whereby the base silicon may be used to crystallize the germanium on top of the oxide by using holes in the oxide to drive crystal or lattice seeding from the underlying silicon crystal. However, it may be very hard to do such on top of multiple interconnection layers. By using layer transfer a mono-crystalline layer of silicon crystal may be constructed on top, allowing a relatively easy process to seed and crystallize an overlying germanium layer. Amorphous germanium could be conformally deposited by CVD at about 300° C. and a pattern may be aligned to the underlying layer, such as the pre-processed wafer or layer808, and then encapsulated by a low temperature oxide. A short microsecond-duration heat pulse may melt the Ge layer while keeping the underlying structure below about 400° C. The Ge/Si interface may start the crystal or lattice epitaxial growth to crystallize the germanium or GexSi1-x layer. Then implants may be made to form Ge transistors and activated by laser pulses without damaging the underlying structure taking advantage of the low activation temperature of dopants in germanium. FIG.10A-10Hare drawing illustrations of the formation of planar top source extension transistors.FIG.10Aillustrates the layer transferred on top of preprocessed wafer or layer808after the smart cut wherein the N+2104may be on top. Then the top transistor source22B04and drain22B06may be defined by etching away the N+ from the region designated for gates22B02, leaving a thin more lightly doped N+ layer for the future source and drain extensions, and the isolation region22B08between transistors. Utilizing an additional masking layer, the isolation region22B08may be defined by an etch substantially all the way to the top of pre-processed wafer or layer808to provide substantially full isolation between transistors or groups of transistors. Etching away the N+ layer between transistors may be helpful as the N+ layer is conducting. This step may be aligned to the top of the pre-processed wafer or layer808so that the formed transistors could be properly connected to metal layers of the pre-processed wafer or layer808. Then a highly conformal Low-Temperature Oxide22C02(or Oxide/Nitride stack) may be deposited and etched resulting in the structure illustrated inFIG.10C.FIG.10Dillustrates the structure following a self-aligned etch step in preparation for gate formation22D02, thereby forming the source and drain extensions22D04.FIG.10Eillustrates the structure following a low temperature microwave oxidation technique, such as, for example, the TEL SPA (Tokyo Electron Limited Slot Plane Antenna) oxygen radical plasma, that may grow or deposit a low temperature Gate Dielectric22E02to serve as the MOSFET gate oxide, or an atomic layer deposition (ALD) technique may be utilized. Alternatively, the gate structure may be formed by a high k metal gate process flow as follows. Following an industry standard HF/SC1/SC2 clean protocol to create an atomically smooth surface, a high-k gate dielectric22E02may be deposited. The semiconductor industry has chosen Hafnium-based dielectrics as the leading material of choice to replace SiO2 and Silicon oxynitride. The Hafnium-based family of dielectrics may include hafnium oxide and hafnium silicate/hafnium silicon oxynitride. Hafnium oxide, HfO2, may have a dielectric constant twice as much as that of hafnium silicate/hafnium silicon oxynitride (HfSiO/HfSiON k˜15). The choice of the metal may affect proper device performance. A metal replacing N+ poly as the gate electrode may need to have a work function of about 4.2 eV for the device to operate properly and at the right threshold voltage. Alternatively, a metal replacing P+ poly as the gate electrode may need to have a work function of about 5.2 eV to operate properly. The TiAl and TiAlN based family of metals, for example, could be used to tune the work function of the metal from about 4.2 eV to about 5.2 eV. FIG.10Fillustrates the structure following deposition, mask, and etch of metal gate22F02. For example, to improve transistor performance, a targeted stress layer to induce a higher channel strain may be employed. A tensile nitride layer may be deposited at low temperature to increase channel stress for the NMOS devices illustrated inFIG.10. A PMOS transistor may be constructed via the above process flow by changing the initial P− wafer or epi-formed P− on N+ layer2104to an N− wafer or an N− on P+ epi layer; and the N+ layer2104to a P+ layer. Then a compressively stressed nitride film would be deposited post metal gate formation to improve the PMOS transistor performance. Finally a thick oxide22G02may be deposited and contact openings may be masked and etched preparing the transistors to be connected as illustrated inFIG.10G. This thick or any low-temperature oxide in this document may be deposited via Chemical Vapor Deposition (CVD), Physical Vapor Deposition (PVD), or Plasma Enhanced Chemical Vapor Deposition (PECVD) techniques. This flow may enable the formation of mono-crystalline top MOS transistors that could be connected to the underlying multi-metal layer semiconductor device without exposing the underlying devices and interconnects metals to high temperature. These transistors could be used as programming transistors of the Antifuse on second antifuse layer807, coupled to the pre-processed wafer or layer808to create a monolithic 3D circuit stack, or for other functions in a 3D integrated circuit. These transistors can be considered “planar transistors,” meaning that the current flow in the transistor channel is substantially in the horizontal direction, and may be substantially between drain and source. The horizontal direction may be defined as the direction being parallel to the largest area of surface (‘face’) of the substrate or wafer that the transistor may be built or layer transferred onto. These transistors, as well as others herein this document wherein the current flow in the transistor channel is substantially in the horizontal direction, can also be referred to as horizontal transistors, horizontally oriented transistors, or lateral transistors. In some embodiments of the invention the horizontal transistor may be constructed in a two-dimensional plane where the source and the drain may be within the same monocrystalline layer. Additionally, the gates of transistors described herein that include gates on 2 or more sides of the transistor channel may be referred to as side gates. A gate may be an electrode that regulates the flow of current in a transistor, for example, a metal oxide semiconductor transistor. An additional advantage of this flow is that the SmartCut H+, or other atomic species, implant step may be done prior to the formation of the MOS transistor gates avoiding potential damage to the gate function. If needed the top layer of the pre-processed wafer or layer808could include a back-gate22F02-1whereby gate22F02may be aligned to be directly on top of the back-gate22F02-1as illustrated inFIG.10H. The back gate22F02-1may be formed from the top metal layer in the pre-processed wafer or layer808and may utilize the oxide layer deposited on top of the metal layer for the wafer bonding (not shown) to act as a gate oxide for the back gate. According to some embodiments of the invention, during a normal fabrication of the device layers as illustrated inFIG.1, every new layer may be aligned to the underlying layers using prior alignment marks. Sometimes the alignment marks of one layer could be used for the alignment of multiple layers on top of it and sometimes the new layer may also have alignment marks to be used for the alignment of additional layers put on top of it in the following fabrication step. So layers of logic fabric/first antifuse layer804may be aligned to layers of802, layers of interconnection layer806may be aligned to layers of logic fabric/first antifuse layer804and so forth. An advantage of the described process flow may be that the layer transferred may be thin enough so that during the following patterning step as described in connection toFIG.10B, the transferred layer may be aligned to the alignment marks of the pre-processed wafer or layer808or those of underneath layers such as layers806,804,802, or other layers, to form the 3D IC. Therefore the back-gate22F02-1which may be part of the top metal layer of the pre-processed wafer or layer808would be precisely underneath gate22F02as all the layers may be patterned as being aligned to each other. In this context alignment precision may be highly dependent on the equipment used for the patterning steps. For processes of 45 nm and below, overlay alignment of better than 5 nm may be usually needed. The alignment requirement may only get tighter with scaling where modern steppers now can do better than about 2 nm. This alignment requirement can be orders of magnitude better than what could be achieved for TSV based 3D IC systems as described below in relation toFIG.12where even 0.5 micron overlay alignment may be extremely hard to achieve. Connection between top-gate and back-gate would be made through a top layer via, or TLV. This may allow further reduction of leakage as both the gate22F02and the back-gate22F02-1could be connected together to better shut off the transistor22G20. As well, one could create a sleep mode, a normal speed mode, and fast speed mode by dynamically changing the threshold voltage of the top gated transistor by independently changing the bias of the back-gate22F02-1 The term alignment mark in the use herein may be defined as “an image selectively placed within or outside an array for either testing or aligning, or both [ASTM F127-84], also called alignment key and alignment target,” as in the SEMATECH dictionary. The alignment mark may, for example, be within a layer, wafer, or substrate of material processing or to be processed, and/or may be on a photomask or photoresist image, or may be a calculated position within, for example, a lithographic wafer stepper's software or memory. An additional aspect of this technique for forming top transistors may be the size of the via, or TLV, used to connect the top transistors22G20to the metal layers in pre-processed wafer and layer808underneath. The general rule of thumb may be that the size of a via should be larger than one tenth the thickness of the layer that the via is going through. Since the thickness of the layers in the structures presented inFIG.12may be usually more than 50 micron, the TSV used in such structures may be about 10 micron on the side. The thickness of the transferred layer inFIG.10Amay be less than 100 nm and accordingly the vias to connect top transistors22G20to the metal layers in pre-processed wafer and layer808underneath could have diameters of less than about 10 nm. As the process may be scaled to smaller feature sizes, the thickness of the transferred layer and accordingly the size of the via to connect to the underlying structures could be scaled down. For some advanced processes, the end thickness of the transferred layer could be made below about 10 nm. Another alternative for forming the planar top transistors with source and drain extensions may be to process the prepared wafer ofFIG.9as shown inFIG.11A-11G.FIG.11Aillustrates the layer transferred on top of pre-processed wafer or layer808after the smart cut wherein the N+2104may be on top, the P−2106, and P+2108. The oxide layers used to facilitate the wafer to wafer bond are not shown. Then the substrate P+ source29B04contact opening and transistor isolation29B02may be masked and etched as shown inFIG.11B. Utilizing an additional masking layer, the isolation region29C02may be defined by etch substantially all the way to the top of the pre-processed wafer or layer808to provide substantially full isolation between transistors or groups of transistors inFIG.11C. Etching away the P+ layer between transistors may be helpful as the P+ layer may be conducting. Then a Low-Temperature Oxide29C04may be deposited and chemically mechanically polished. Then a thin polish stop layer29C06such as low temperature silicon nitride may be deposited resulting in the structure illustrated inFIG.11C. Source29D02, drain29D04and self-aligned Gate29D06may be defined by masking and etching the thin polish stop layer29C06and then a sloped N+ etch as illustrated inFIG.11D. The sloped (30-90 degrees, 45 is shown) etch or etches may be accomplished with wet chemistry or plasma etching techniques. This process may form angular source and drain extensions29D08.FIG.11Eillustrates the structure following deposition and densification of a low temperature based Gate Dielectric29E02, or alternatively a low temperature microwave plasma oxidation of the silicon surfaces, or an atomic layer deposited (ALD) gate dielectric, to serve as the MOSFET gate oxide, and then deposition of a gate material29E04, such as aluminum or tungsten. Alternatively, a high-k metal gate (HKMG) structure may be formed as follows. Following an industry standard HF/SC1/SC2 cleaning to create an atomically smooth surface, a high-k gate dielectric29E02may be deposited. The semiconductor industry has chosen Hafnium-based dielectrics as the leading material of choice to replace SiO2and Silicon oxynitride. The Hafnium-based family of dielectrics includes hafnium oxide and hafnium silicate/hafnium silicon oxynitride. Hafnium oxide, HfO2, has a dielectric constant twice as much as that of hafnium silicate/hafnium silicon oxynitride (HfSiO/HfSiON k˜15). The choice of the metal may affect proper device performance. A metal replacing N+ poly as the gate electrode may need to have a work function of about 4.2 eV for the device to operate properly and at the right threshold voltage. Alternatively, a metal replacing P+ poly as the gate electrode may need to have a work function of about 5.2 eV to operate properly. The TiAl and TiAlN based family of metals, for example, could be used to tune the work function of the metal from about 4.2 eV to about 5.2 eV. FIG.11Fillustrates the structure following a chemical mechanical polishing of the gate material29E04, thus forming metal gate29E04, and utilizing the nitride polish stop layer29C06. A PMOS transistor could be constructed via the above process flow by changing the initial P− wafer or epi-formed P− on N+ layer2104to an N− wafer or an N− on P+ epi layer; and the N+ layer2104to a P+ layer. Similarly, layer2108may be changed from P+ to N+ if the substrate contact option was used. Finally a thick oxide29G02may be deposited and contact openings may be masked and etched preparing the transistors to be connected, for example, as illustrated inFIG.11G. This figure also illustrates the layer transfer silicon via29G04masked and etched to provide interconnection of the top transistor wiring to the lower layer808interconnect wiring29G06. This flow may enable the formation of mono-crystalline top MOS transistors that may be connected to the underlying multi-metal layer semiconductor device without exposing the underlying devices and interconnects metals to high temperature. These transistors may be used as programming transistors of the antifuses on second antifuse layer807, to couple with the pre-processed wafer or layer808to form monolithic 3D ICs, or for other functions in a 3D integrated circuit. These transistors can be considered to be “planar transistors”. These transistors can also be referred to as horizontal transistors or lateral transistors. An additional illustrated advantage of this flow may be that the SmartCut H+, or other atomic species, implant step may be done prior to the formation of the MOS transistor gates avoiding potential damage to the gate function. Additionally, an accumulation mode (fully depleted) MOSFET transistor may be constructed via the above process flow by changing the initial P− wafer or epi-formed P− on N+ layer2104to an N− wafer or an N− epi layer on N+. Additionally, a back gate similar to that shown inFIG.10Hmay be utilized. Another class of devices that may be constructed partly at high temperature before layer transfer to a substrate with metal interconnects and may then be completed at low temperature after a layer transfer may be a junction-less transistor (JLT). For example, in deep sub-micron processes copper metallization may be utilized, so a high temperature would be above about 400° C., whereby a low temperature would be about 400° C. and below. The junction-less transistor structure may avoid the sharply graded junctions that may be needed as silicon technology scales, and may provide the ability to have a thicker gate oxide for an equivalent performance when compared to a traditional MOSFET transistor. The junction-less transistor may also be known as a nanowire transistor without junctions, or gated resistor, or nanowire transistor as described in a paper by Jean-Pierre Colinge, et. al., published in Nature Nanotechnology on Feb. 21, 2010. The junction-less transistors may be constructed whereby the transistor channel is a thin solid piece of evenly and heavily doped single crystal silicon. The doping concentration of the channel may be identical to that of the source and drain. The considerations may include that the nanowire channel be thin and narrow enough to allow for full depletion of the carriers when the device is turned off, and the channel doping be high enough to allow a reasonable current to flow when the device is on. These considerations may lead to tight process variation boundaries for channel thickness, width, and doping for a reasonably obtainable gate work function and gate oxide thickness. One of the challenges of a junction-less transistor device is turning the channel off with minimal leakage at a zero gate bias. As an embodiment of the invention, to enhance gate control over the transistor channel, the channel may be doped unevenly; whereby the heaviest doping may be closest to the gate or gates and the channel doping may be lighter the farther away from the gate electrode. One example may be where the center of a 2, 3, or 4 gate sided junction-less transistor channel is more lightly doped than the edges towards the gates. This may enable much lower off currents for the same gate work function and control. The junction-less transistor channel may be constructed with even, graded, or discrete layers of doping. The channel may be constructed with materials other than doped mono-crystalline silicon, such as poly-crystalline silicon, or other semi-conducting, insulating, or conducting material, such as graphene or other graphitic material, and may be in combination with other layers of similar or different material. For example, the center of the channel may include a layer of oxide, or of lightly doped silicon, and the edges towards the gates more heavily doped single crystal silicon. This may enhance the gate control effectiveness for the off state of the junction-less transistor, and may also increase the on-current due to strain effects on the other layer or layers in the channel. Strain techniques may also be employed from covering and insulator material above, below, and surrounding the transistor channel and gate. Lattice modifiers may also be employed to strain the silicon, such as an embedded SiGe implantation and anneal. The cross section of the transistor channel may be rectangular, circular, or oval shaped, to enhance the gate control of the channel. Alternatively, to optimize the mobility of the P-channel junction-less transistor in the 3D layer transfer method, the donor wafer may be rotated 90 degrees with respect to the acceptor wafer prior to bonding to facilitate the creation of the P-channel in the <110> silicon plane direction. To construct an n-type 4-sided gated junction-less transistor a silicon wafer may be preprocessed to be used for layer transfer as illustrated inFIG.18A-18G. These processes may be at temperatures above about 400 degrees Centigrade as the layer transfer to the processed substrate with metal interconnects has yet to be done. As illustrated inFIG.18A, an N− wafer5600A may be processed to have a layer of N+5604A, by implant and activation, by an N+ epitaxial growth, or may be a deposited layer of heavily N+ doped polysilicon. A gate oxide5602A may be grown before or after the implant, to a thickness about half of the final top-gate oxide thickness.FIG.18Bis a drawing illustration of the pre-processed wafer made ready for a layer transfer by an implant5606of an atomic species, such as H+, preparing the “cleaving plane”5608in the N− region5600A of the substrate, and plasma or other surface treatments to prepare the oxide surface for wafer oxide to oxide bonding. Another wafer may be prepared as above without the H+ implant and the two are bonded as illustrated inFIG.18C, to transfer the pre-processed single crystal N− silicon with N+ layer and half gate oxide, on top of a similarly pre-processed, but not cleave implanted, N− wafer5600with N+ layer5604and oxide5602. The top wafer may be cleaved and removed from the bottom wafer. This top wafer may now also be processed and reused for more layer transfers to form the resistor layer. The remaining top wafer N− and N+ layers may be chemically and mechanically polished to a very thin N+ silicon layer5610as illustrated inFIG.18D. This thin N+ silicon layer5610may be on the order of 5 to 40 nm thick and will eventually form the junction-less transistor channel, or resistor, that may be gated on four sides. The two ‘half’ gate oxides5602,5602A may now be atomically bonded together to form the gate oxide5612, which may eventually become the top gate oxide of the junction-less transistor inFIG.18E. A high temperature anneal may be performed to remove any residual oxide or interface charges. Alternatively, the wafer that becomes the bottom wafer inFIG.18Cmay be constructed wherein the N+ layer5604may be formed with heavily doped polysilicon and the half gate oxide5602may be deposited or grown prior to layer transfer. The bottom wafer N+ silicon or polysilicon layer5604may eventually become the top-gate of the junction-less transistor. As illustrated inFIG.18EtoFIG.18G, the wafer may be conventionally processed, at temperatures higher than about 400° C. as necessary, in preparation to layer transfer the junction-less transistor structure to the processed ‘house’ wafer808. A thin oxide may be grown to protect the resistor silicon thin N+ silicon layer5610top, and then parallel wires, resistors5614, of repeated pitch of the thin resistor layer may be masked and etched as illustrated inFIG.18Eand then the photoresist is removed. The thin oxide, if present, may be striped in a dilute hydrofluoric acid (HF) solution and a conventional gate oxide5616may be grown and polysilicon5618, doped or undoped, may be deposited as illustrated inFIG.18F. The polysilicon may be chemically and mechanically polished (CMP'ed) flat and a thin oxide5620may be grown or deposited to facilitate a low temperature oxide to oxide wafer bonding in the next step. The polysilicon5618may be implanted for additional doping either before or after the CMP. This polysilicon5618, may eventually become the bottom and side gates of the junction-less transistor.FIG.18Gis a drawing illustration of the wafer being made ready for a layer transfer by an implant5606of an atomic species, such as H+, preparing the “cleaving plane”5608G in the N− region5600of the substrate and plasma or other surface treatments to prepare the oxide surface for wafer oxide to oxide bonding. The acceptor wafer808with logic transistors and metal interconnects may be prepared for a low temperature oxide to oxide wafer bond with surface treatments of the top oxide and the two are bonded as illustrated inFIG.18H. The top donor wafer may be cleaved and removed from the bottom acceptor wafer808and the top N− substrate may be removed by CMP (chemical mechanical polish). A metal interconnect strip5622in the house808may be also illustrated inFIG.18H. FIG.18Iis a top view of a wafer at the same step asFIG.18Hwith two cross-sectional views I and II. The N+ layer5604, which may eventually form the top gate of the resistor, and the top gate oxide5612may gate one side of the resistor5614line, and the bottom and side gate oxide5616with the polysilicon bottom and side gates5618may gate the other three sides of the resistor5614line. The logic house wafer808may have a top oxide layer5624that may also encase the top metal interconnect strip5622, to an extent shown as dotted lines in the top view. InFIG.18J, a polish stop layer5626of a material such as oxide and silicon nitride may be deposited on the top surface of the wafer, and isolation openings5628may be masked and etched to the depth of the house808oxide layer5624to fully isolate transistors. The isolation openings5628may be filled with a low temperature gap fill oxide, and chemically and mechanically polished (CMP'ed) flat. The top gate5630may be masked and etched as illustrated inFIG.18K, and then the etched openings5629may be filled with a low temperature gap fill oxide deposition, and chemically and mechanically (CMP'ed) polished flat, then an additional oxide layer may be deposited to enable interconnect metal isolation. The contacts may be masked and etched. The gate contact5632may be masked and etched, so that the contact etches through the top gate5630layer, and during the metal opening mask and etch process the gate oxide may be etched and the top gate5630and bottom gate5618gates may be connected together. The contacts5634to the two terminals of the resistor5614may be masked and etched. And then the through vias5636to the house wafer808and metal interconnect strip5622may be masked and etched. As illustrated inFIG.18M, the metal lines5640may be mask defined and etched, filled with barrier metals and copper interconnect, and CMP'ed in a normal metal interconnect scheme, thereby completing the contact via5632simultaneous coupling to the top gate5630and bottom gate5618gates, the two terminal contacts5634of the resistor5614, and the through via to the house wafer808metal interconnect strip5622. This flow may enable the formation of a mono-crystalline 4-sided gated junction-less transistor that could be connected to the underlying multi-metal layer semiconductor device without exposing the underlying devices to high temperature. Alternatively, as illustrated inFIG.36A to36J, an n-channel 4-sided gated junction-less transistor (JLT) may be constructed that is suitable for 3D IC manufacturing. 4-sided gated JLTs can also be referred to as gate-all around JLTs or silicon nano-wire JLTs. As illustrated inFIG.36A, a P− (shown) or N− substrate donor wafer9600may be processed to include wafer sized layers of N+ doped silicon9602and9606, and wafer sized layers of n+ SiGe9604and9608. Layers9602,9604,9606, and9608may be grown epitaxially and are carefully engineered in terms of thickness and stoichiometry to keep the defect density due to the lattice mismatch between Si and SiGe low. The stoichiometry of the SiGe may be unique to each SiGe layer to provide for different etch rates as will be utilized later. Some techniques for achieving the defect density low include keeping the thickness of the SiGe layers below the critical thickness for forming defects. The top surface of donor wafer9600may be prepared for oxide wafer bonding with a deposition of an oxide. These processes may be done at temperatures above about 400° C. as the layer transfer to the processed substrate with metal interconnects may have yet to be done. A wafer sized layer denotes a continuous layer of material or combination of materials that may extend across the wafer to the full extent of the wafer edges and may be about uniform in thickness. If the wafer sized layer may include dopants, then the dopant concentration may be substantially the same in the x and y direction across the wafer, but may vary in the z direction perpendicular to the wafer surface. As illustrated inFIG.36B, a layer transfer demarcation plane9699(shown as a dashed line) may be formed in donor wafer9600by hydrogen implantation or other layer transfer methods as previously described. As illustrated inFIG.36C, both the donor wafer9600and acceptor wafer9610top layers and surfaces may be prepared for wafer bonding as previously described and then donor wafer9600may be flipped over, aligned to the acceptor wafer9610alignment marks (not shown) and bonded together at a low temperature (less than about 400° C.). Oxide9613from the donor wafer and the oxide of the surface of the acceptor wafer9610may thus be atomically bonded together are designated as oxide9614. As illustrated inFIG.36D, the portion of the P− donor wafer9600that may be above the layer transfer demarcation plane9699may be removed by cleaving and polishing, etching, or other low temperature processes as previously described. A CMP process may be used to remove the remaining P− layer until the N+ silicon layer9602is reached. This process of an ion implanted atomic species, such as Hydrogen, forming a layer transfer demarcation plane, and subsequent cleaving or thinning, may be called ‘ion-cut’. Acceptor wafer9610may have similar meanings as wafer808previously described with reference toFIG.1. As illustrated inFIG.36E, stacks of N+ silicon and n+ SiGe regions that may become transistor channels and gate areas may be formed by lithographic definition and plasma/RIE etching of N+ silicon layers9602&9606and n+ SiGe layers9604&9608. The result may be stacks of n+ SiGe9616and N+ silicon9618regions. The isolation between stacks may be filled with a low temperature gap fill oxide9620and chemically and mechanically polished (CMP'ed) flat. This may fully isolate the transistors from each other. The stack ends may be exposed in the illustration for clarity of understanding. As illustrated inFIG.36F, eventual ganged or common gate area9630may be lithographically defined and oxide etched. This may expose the transistor channels and gate area stack sidewalls of alternating N+ silicon9618and n+ SiGe9616regions to the eventual ganged or common gate area9630. The stack ends may be exposed in the illustration for clarity of understanding. As illustrated inFIG.36G, the exposed n+ SiGe regions9616may be removed by a selective etch recipe that does not attack the N+ silicon regions9618. This may create air gaps between the N+ silicon regions9618in the eventual ganged or common gate area9630. Such etching recipes are described in “High performance 5 nm radius twin silicon nanowire MOSFET(TSNWFET): Fabrication on bulk Si wafer, characteristics, and reliability,” inProc. IEDM Tech. Dig.,2005, pp. 717-720 by S. D. Suk, et. al. The n+ SiGe layers farthest from the top edge may be stoichiometrically crafted such that the etch rate of the layer (now region) farthest from the top (such as n+ SiGe layer9608) may etch slightly faster than the layer (now region) closer to the top (such as n+ SiGe layer9604), thereby equalizing the eventual gate lengths of the two stacked transistors. The stack ends are exposed in the illustration for clarity of understanding. As illustrated inFIG.36H, an example step of reducing the surface roughness, rounding the edges, and thinning the diameter of the N+ silicon regions9618that are exposed in the ganged or common gate area may utilize a low temperature oxidation and subsequent HF etch removal of the oxide just formed. This may be repeated multiple times. Hydrogen may be added to the oxidation or separately utilized atomically as a plasma treatment to the exposed N+ silicon surfaces. The result may be a rounded silicon nanowire-like structure to form the eventual transistor gated channel9636. These methods of reducing surface roughness of silicon may be utilized in combination with other embodiments of the invention. The stack ends are exposed in the illustration for clarity of understanding. As illustrated inFIG.36Ia low temperature based gate dielectric9611may be deposited and densified to serve as the junction-less transistor gate oxide. Alternatively, a low temperature microwave plasma oxidation of the eventual transistor gated channel9636silicon surfaces may serve as the JLT gate oxide or an atomic layer deposition (ALD) technique may be utilized to form the HKMG gate oxide as previously described. Then deposition of a low temperature gate material, such as P+ doped amorphous silicon, may be performed. Alternatively, a HKMG gate structure may be formed as described previously. A CMP may be performed after the gate material deposition, thus forming gate electrode9612. The stack ends may be exposed in the illustration for clarity of understanding. FIG.36Jshows the complete JLT transistor stack formed inFIG.36Iwith the oxide removed for clarity of viewing and a cross-sectional cut I ofFIG.36I. Gate electrode9612and gate dielectric9611may surround the transistor gated channel9636and each ganged transistor stack may be isolated from one another by oxide9622. The source and drain connections of the transistor stacks can be made to the N+ Silicon9618and n+ SiGe9616regions that may not be covered by the gate electrode9612. Contacts to the 4-sided gated JLT's source, drain, and gate may be made with conventional Back end of Line (BEOL) processing as described previously and coupling from the formed JLTs to the acceptor wafer may be accomplished with formation of a through layer via (TLV) connection to an acceptor wafer metal interconnect pad. This flow may enable the formation of a mono-crystalline silicon channel 4-sided gated junction-less transistor that may be formed and connected to the underlying multi-metal layer semiconductor device without exposing the underlying devices to a high temperature. A p channel 4-sided gated JLT may be constructed as above with the N+ silicon layers9602and9608formed as P+ doped, and the metals/materials of gate electrode9612may be of appropriate work function to shutoff the p channel at a gate voltage of zero. While the process flow shown inFIG.36A to36FandFIG.36H to36Jillustrates the example steps involved in forming a four-sided gated JLT with 3D stacked components, it is conceivable to one skilled in the art that changes to the process can be made. For example, process steps and additional materials/regions to add strain to JLTs may be added. Moreover, N+ SiGe layers9604and9608may instead be comprised of p+ SiGe or undoped SiGe and the selective etchant formula adjusted. Furthermore, more than two layers of chips or circuits can be 3D stacked. Also, there are many methods to construct silicon nanowire transistors. These methods may be described in “High performance and highly uniform gate-all-around silicon nanowire MOSFETs with wire size dependent scaling,”Electron Devices Meeting(IEDM), 2009IEEE International, vol., no., pp. 1-4, 7-9 Dec. 2009 by Bangsaruntip, S.; Cohen, G. M.; Majumdar, A.; et al. (“Bangsaruntip”) and in “High performance 5 nm radius twin silicon nanowire MOSFET(TSNWFET): Fabrication on bulk Si wafer, characteristics, and reliability,” inProc. IEDM Tech. Dig.,2005, pp. 717-720 by S. D. Suk, S.-Y. Lee, S.-M. Kim, et al. (“Suk”). Contents of these publications are incorporated in this document by reference. The techniques described in these publications can be utilized for fabricating four-sided gated JLTs. Alternatively, an n-type 3-sided gated junction-less transistor may be constructed as illustrated inFIG.19AtoFIG.19G. A silicon wafer is preprocessed to be used for layer transfer as illustrated inFIG.19AandFIG.19B. These processes may be at temperatures above about 400° C. as the layer transfer to the processed substrate with metal interconnects is yet to be done. As illustrated inFIG.19A, an N− wafer5700may be processed to have a layer of N+5704, by implant and activation, by an N+ epitaxial growth, or may be a deposited layer of heavily N+ doped polysilicon. A screen oxide5702may be grown before the implant to protect the silicon from implant contamination and to provide an oxide surface for later wafer to wafer bonding.FIG.19Bis a drawing illustration of the pre-processed wafer made ready for a layer transfer by an implant5707of an atomic species, such as H+, preparing the “cleaving plane”5799in the N− region of N− wafer5700, or the donor substrate, and plasma or other surface treatments to prepare the oxide surface for wafer oxide to oxide bonding. The acceptor wafer or house808with logic transistors and metal interconnects may be prepared for a low temperature oxide to oxide wafer bond with surface treatments of the top oxide and the two may be bonded as illustrated inFIG.19C. The top donor wafer may be cleaved and removed from the bottom acceptor wafer808and the top N− substrate may be chemically and mechanically polished (CMP'ed) into the N+ layer5704to form the top gate layer of the junction-less transistor. A metal interconnect layer/strip5706in the acceptor wafer or house808is also illustrated inFIG.19C. For illustration simplicity and clarity, the donor wafer oxide layer screen oxide5702will not be drawn independent of the acceptor wafer or house808oxides inFIG.19DthroughFIG.19G. A thin oxide may be grown to protect the thin transistor silicon5704layer top, and then the transistor channel elements5708may be masked and etched as illustrated inFIG.19Dand then the photoresist may be removed. The thin oxide may be stripped in a dilute HF solution and a low temperature based Gate Dielectric may be deposited and densified to serve as the junction-less transistor gate oxide5710. Alternatively, a low temperature microwave plasma oxidation of the silicon surfaces may serve as the junction-less transistor gate oxide5710or an atomic layer deposition (ALD) technique, such as described herein HKMG processes, may be utilized. Then deposition of a low temperature gate material5712, such as doped or undoped amorphous silicon as illustrated inFIG.19E, may be performed. Alternatively, a high-k metal gate structure may be formed as described previously. The gate material5712may be then masked and etched to define the top and side gate5714of the transistor channel elements5708in a crossing manner, generally orthogonally as shown inFIG.19F. Then the entire structure may be covered with a Low Temperature Oxide5716, the oxide planarized with chemical mechanical polishing, and then contacts and metal interconnects may be masked and etched as illustratedFIG.19G. The gate contact5720may connect to the top and side gate5714. The two transistor channel terminal contacts5722may independently connect to transistor element5708on each side of the top and side gate5714. The through via5724may connect the transistor layer metallization to the acceptor wafer or house808at metal interconnect layer/strip5706. This flow may enable the formation of mono-crystalline 3-sided gated junction-less transistor that may be formed and connected to the underlying multi-metal layer semiconductor device without exposing the underlying devices to a high temperature. Alternatively, an n-type 3-sided gated thin-side-up junction-less transistor may be constructed as follows inFIG.20AtoFIG.20G. A thin-side-up transistor, for example, a junction-less thin-side-up transistor, may have the thinnest dimension of the channel cross-section facing up (when oriented horizontally), that face being parallel to the silicon base substrate largest area surface or face. Previously and subsequently described junction-less transistors may have the thinnest dimension of the channel cross section oriented vertically and perpendicular to the silicon base substrate surface. A silicon wafer may be preprocessed to be used for layer transfer, as illustrated inFIG.20AandFIG.20B. These processes may be at temperatures above about 400° C. as the layer transfer to the processed substrate with metal interconnects is yet to be done. As illustrated inFIG.20A, an N− wafer5800may be processed to have a layer of N+5804, by ion implantation and activation, by an N+ epitaxial growth, or may be a deposited layer of heavily N+ doped polysilicon. A screen oxide5802may be grown before the implant to protect the silicon from implant contamination and to provide an oxide surface for later wafer to wafer bonding.FIG.20Bis a drawing illustration of the pre-processed wafer made ready for a layer transfer by an implant5803of an atomic species, such as H+, preparing the “cleaving plane”5807in the N− region of N− wafer5800, or the donor substrate, and plasma or other surface treatments to prepare the oxide surface for wafer oxide to oxide bonding. The acceptor wafer808with logic transistors and metal interconnects may be prepared for a low temperature oxide to oxide wafer bond with surface treatments of the top oxide and the two may be bonded as illustrated inFIG.20C. The top donor wafer may be cleaved and removed from the bottom acceptor wafer808and the top N− substrate may be chemically and mechanically polished (CMP'ed) into the N+ layer5804to form the junction-less transistor channel layer.FIG.20Calso illustrates the deposition of a CMP and plasma etch stop layer5805, such as low temperature SiN on oxide, on top of the N+ layer5804. A metal interconnect layer5806in the acceptor wafer or house808is also shown inFIG.20C. For illustration simplicity and clarity, the donor wafer oxide layer screen oxide5802will not be drawn independent of the acceptor wafer or house808oxide inFIG.20DthroughFIG.20G. The transistor channel elements5808may be masked and etched as illustrated inFIG.20Dand then the photoresist may be removed. As illustrated inFIG.20E, a low temperature based Gate Dielectric may be deposited and densified to serve as the junction-less transistor gate oxide5810. Alternatively, a low temperature microwave plasma oxidation of the silicon surfaces may serve as the junction-less transistor gate oxide5810or an atomic layer deposition (ALD) technique may be utilized. Then deposition of a low temperature gate material5812, such as P+ doped amorphous silicon may be performed. Alternatively, a high-k metal gate structure may be formed as described previously. As illustrated inFIG.20F, gate material5812may be then masked and etched to define the top and side gate5814of the transistor channel elements5808. As illustrated inFIG.20G, the entire structure may be covered with a Low Temperature Oxide5816, the oxide planarized with chemical mechanical polishing (CMP), and then contacts and metal interconnects may be masked and etched. The gate contact5820may connect to the transistor top and side gate5814(i.e., in front of and behind the plane of the other elements shown inFIG.20G). The two transistor channel terminal contacts5822per transistor may independently connect to the transistor channel element5808on each side of the top and side gate5814. The through via5824may connect the transistor layer metallization to the acceptor wafer or house808interconnect5806. This flow may enable the formation of mono-crystalline 3-gated sided thin-side-up junction-less transistor that may be formed and connected to the underlying multi-metal layer semiconductor device without exposing the underlying devices to a high temperature. Persons of ordinary skill in the art will appreciate that the illustrations inFIG.19AthroughFIG.19GandFIG.20AthroughFIG.20Gare exemplary only and are not drawn to scale. Such skilled persons will further appreciate that many variations may be possible, for example, the process described in conjunction withFIG.19AthroughFIG.19Gcould be used to make a junction-less transistor where the channel is taller than its width or that the process described in conjunction withFIG.20AthroughFIG.20Gcould be used to make a junction-less transistor that is wider than its height. Many other modifications within the scope of the illustrated embodiments of the invention will suggest themselves to such skilled persons after reading this specification. Thus the invention is to be limited only by the appended claims. Alternatively, a 1-sided gated junction-less transistor can be constructed as shown inFIG.24A-C. A thin layer of heavily doped silicon, such as transferred doped layer6500, may be transferred on top of the acceptor wafer or house808using layer transfer techniques described previously wherein the donor wafer oxide layer6501may be utilized to form an oxide to oxide bond with the top of the acceptor wafer or house808. The transferred doped layer6500may be N+ doped for an n-channel junction-less transistor or may be P+ doped for a p-channel junction-less transistor. As illustrated inFIG.24B, oxide isolation6506may be formed by masking and etching transferred doped layer6500, thus forming the N+ doped region6503. Subsequent deposition of a low temperature oxide which may be chemical mechanically polished to form transistor isolation between N+ doped regions6503. The channel thickness, i.e. thickness of N+ doped regions6503, may also be adjusted at this step. A low temperature gate dielectric6504and gate metal6505may be deposited or grown as previously described and then photo-lithographically defined and etched. As shown inFIG.24C, a low temperature oxide6508may then be deposited, which also may provide a mechanical stress on the channel for improved carrier mobility. Contact openings6510may then be opened to various terminals of the junction-less transistor. Persons of ordinary skill in the art will appreciate that the processing methods presented above are illustrative only and that other embodiments of the inventive principles described herein are possible and thus the scope if the invention is only limited by the appended claims. A family of vertical devices can also be constructed as top transistors that are precisely aligned to the underlying pre-fabricated acceptor wafer or house808. These vertical devices have implanted and annealed single crystal silicon layers in the transistor by utilizing the “SmartCut” layer transfer process that may not exceed the temperature limit of the underlying pre-fabricated structure. For example, vertical style MOSFET transistors, floating gate flash transistors, floating body DRAM, thyristor, bipolar, and Schottky gated JFET transistors, as well as memory devices, can be constructed. Junction-less transistors may also be constructed in a similar manner. The gates of the vertical transistors or resistors may be controlled by memory or logic elements such as MOSFET, DRAM, SRAM, floating flash, anti-fuse, floating body devices, etc. that are in layers above or below the vertical device, or in the same layer. As an example, a vertical gate-all-around n-MOSFET transistor construction is described below. The donor wafer preprocessed for the general layer transfer process is illustrated inFIG.15. A P− wafer3902may be processed to have a “buried” layer of N+3904, by either implant and activation, or by shallow N+ implant and diffusion. This process may be followed by depositing a P− epi growth (epitaxial growth) layer3906and finally an additional N+ layer3908may be processed on top. This N+ layer3908could again be processed, by implant and activation, or by N+ epi growth. FIG.15Bis a drawing illustration of the pre-processed donor wafer which may be made ready for a conductive bond layer transfer by a deposition of a conductive barrier layer3910such as TiN or TaN on top of N+ layer3908and an implant of an atomic species, such as H+, preparing the SmartCut cleaving plane3912in the lower part of the N+3904region. As shown inFIG.15C, the acceptor wafer may be prepared with an oxide pre-clean and deposition of a conductive barrier layer3916and Al—Ge eutectic layer3914. Al—Ge eutectic layer3914may form an Al—Ge eutectic bond with the conductive barrier layer3910during a thermo-compressive wafer to wafer bonding process as part of the layer-transfer-flow, thereby transferring the pre-processed single crystal silicon with N+ and P− layers. Thus, a conductive path may be made from the house808top metal layer metal lines/strips3920to the now bottom N+ layer3908of the transferred donor wafer. Alternatively, the Al—Ge eutectic layer3914may be made with copper and a copper-to-copper or copper-to-barrier layer thermo-compressive bond may be formed. Likewise, a conductive path from donor wafer to house808may be made by house top metal lines/strips3920of copper with barrier metal thermo-compressively bonded with the copper layer of conductive barrier layer3910directly, where a majority of the bonded surface is donor copper to house oxide bonds and the remainder of the surface may be donor copper to house808copper and barrier metal bonds. Additionally, a vertical gate all around junction-less transistor may be constructed as illustrated in at leastFIG.17A-17C. The donor wafer preprocessed for the general layer transfer process is illustrated inFIG.17.FIG.17Ais a drawing illustration of a pre-processed wafer that may be used for a layer transfer. An N− wafer5402may be processed to have a layer of N+5404, by ion implantation and activation, or an N+ epitaxial growth.FIG.17Bis a drawing illustration of the pre-processed wafer that may be made ready for a conductive bond layer transfer by a deposition of a conductive barrier layer5410such as TiN or TaN and by an implant of an atomic species, such as H+, preparing the SmartCut cleaving plane5412in the lower part of the N+5404region. The acceptor wafer or house808may also be prepared with an oxide pre-clean and deposition of a conductive barrier layer5416and Al and Ge layers to form a Ge—Al eutectic bond, Al—Ge eutectic layer5414, during a thermo-compressive wafer to wafer bonding as part of the layer-transfer-flow, thereby transferring the pre-processed single crystal silicon ofFIG.17Bwith an N+ layer5404, on top of acceptor wafer or house808, as illustrated inFIG.17C. The N+ layer5404may be polished to remove damage from the cleaving procedure. Thus, a conductive path may be made from the acceptor wafer or house808top metal layers/lines5420to the N+ layer5404of the transferred donor wafer. Alternatively, the Al—Ge eutectic layer5414may be made with copper and a copper-to-copper or copper-to-barrier layer thermo-compressive bond may be formed. Likewise, a conductive path from donor wafer to acceptor wafer or house808may be made by house top metal layers/lines5420of copper with associated barrier metal thermo-compressively bonded with the copper layer5420directly, where a majority of the bonded surface may be donor copper to house oxide bonds and the remainder of the surface may be donor copper to acceptor wafer or house808copper and barrier metal bonds. Recessed Channel Array Transistors (RCATs) may be another transistor family that can utilize layer transfer and etch definition to constmct a low-temperature monolithic 3D Integrated Circuit. The recessed channel array transistor may sometimes be referred to as a recessed channel transistor. Two types of RCAT device structures are shown inFIG.25. These were described by J. Kim, et al. at the Symposium on VLSI Technology, in2003and2005. Note that this prior art of J. Kim, et al. is for a single layer of transistors and no layer transfer techniques were ever employed. Their work also used high-temperature processes such as source-drain activation anneals, wherein the temperatures were above 400° C. In contrast, some embodiments of the invention employ this transistor family in a two-dimensional plane. Transistors in this document, such as, for example, junction-less, recessed channel array, or depletion, with the source and the drain in the same two dimensional planes may be considered planar transistors. The terms horizontal transistors, horizontally oriented transistors, or lateral transistors may also refer to planar transistors. Additionally, the gates of transistors in some embodiments of the invention that include gates on two or more sides of the transistor channel may be referred to as side gates. A layer stacking approach to construct 3D integrated circuits with standard RCATs is illustrated inFIG.26A-F. For an n-channel MOSFET, a p− silicon wafer6700may be the starting point. A buried layer of n+Si6702may then be implanted as shown inFIG.26A, resulting in p− layer6703that may be at the surface of the donor wafer. An alternative may be to implant a shallow layer of n+Si and then epitaxially deposit a layer of p− Si, thus forming p− layer6703. To activate dopants in the n+ layer6702, the wafer may be annealed, with standard annealing procedures such as thermal, or spike, or laser anneal. An oxide layer6701may be grown or deposited, as illustrated inFIG.26B. Hydrogen may be implanted into the p silicon wafer6700to enable a “smart cut” process, as indicated inFIG.26Bas a dashed line for hydrogen cleave plane6704. A layer transfer process may be conducted to attach the donor wafer inFIG.26Bto a pre-processed circuits acceptor wafer808as illustrated inFIG.26C. The hydrogen cleave plane6704may now be utilized for cleaving away the remainder of the p silicon wafer6700. After the cut, chemical mechanical polishing (CMP) may be performed. Oxide isolation regions6705may be formed and an etch process may be conducted to form the recessed channel6706as illustrated inFIG.26D. This etch process may be further customized so that corners are rounded to avoid high field issues. A gate dielectric6707may then be deposited, either through atomic layer deposition or through other low-temperature oxide formation procedures described previously. A metal gate6708may then be deposited to fill the recessed channel, followed by a CMP and gate patterning as illustrated inFIG.26E. A low temperature oxide6709may be deposited and planarized by CMP. Contacts6710may be formed to connect to all electrodes of the transistor as illustrated inFIG.26F. This flow may enable the formation of a low temperature RCAT monolithically on top of pre-processed circuitry808. A p-channel MOSFET may be formed with an analogous process. The p and n channel RCATs may be utilized to form a monolithic 3D CMOS circuit library as described later. A planar n-channel junction-less recessed channel array transistor (JLRCAT) suitable for a 3D IC may be constructed. The JLRCAT may provide an improved source and drain contact resistance, thereby allowing for lower channel doping, and the recessed channel may provide for more flexibility in the engineering of channel lengths and characteristics, and increased immunity from process variations. As illustrated inFIG.60A, an N− substrate donor wafer15100may be processed to include wafer sized layers of N+ doping15102, and N− doping15103across the wafer. The N+ doped layer15102may be formed by ion implantation and thermal anneal. In addition, N− doped layer15103may have additional ion implantation and anneal processing to provide a different dopant level than N− substrate donor wafer15100. N− doped layer15103may also have graded N− doping to mitigate transistor performance issues, such as, for example, short channel effects, after the formation of the JLRCAT. The layer stack may alternatively be formed by successive epitaxially deposited doped silicon layers of N+ doping15102and N− doping15103, or by a combination of epitaxy and implantation. Annealing of implants and doping may utilize optical annealing techniques or types of Rapid Thermal Anneal (RTA or spike) or flash anneal. As illustrated inFIG.60B, the top surface of N− substrate donor wafer15100layers stack fromFIG.60Amay be prepared for oxide wafer bonding with a deposition of an oxide to form oxide layer15101on top of N− doped layer15103. A layer transfer demarcation plane (shown as dashed line)15104may be formed by hydrogen implantation, co-implantation such as hydrogen and helium, or other methods as previously described. As illustrated inFIG.60C, both the N− substrate donor wafer15100and acceptor substrate808may be prepared for wafer bonding as previously described and then low temperature (less than about 400° C.) aligned and oxide to oxide bonded. Acceptor substrate808, as described previously, may include, for example, transistors, circuitry, metal, such as, for example, aluminum or copper, interconnect wiring, and through layer via metal interconnect strips or pads. The portion of the N− substrate donor wafer15100and N+ doped layer15102that is below the layer transfer demarcation plane15104may be removed by cleaving or other processes as previously described, such as, for example, ion-cut or other methods. Oxide layer15101, N− doped layer15103, and N+ doped layer15122may have been layer transferred to acceptor wafer808. Now JLRCAT transistors may be formed with low temperature (less than about 400° C.) processing and may be aligned to the acceptor wafer808alignment marks (not shown). As illustrated inFIG.60D, the transistor isolation regions15105may be formed by mask defining and then plasma/RIE etching N+ doped layer15122, and N− doped layer15103to the top of oxide layer15101or into oxide layer15101. A low-temperature gap fill oxide may be deposited and chemically mechanically polished, with the oxide remaining in isolation regions15105. Recessed channel15106may be mask defined and etched through N+ doped layer15122and partially into N− doped layer15103. The recessed channel15106surfaces and edges may be smoothed by processes such as, for example, wet chemical, plasma/RIE etching, low temperature hydrogen plasma, or low temperature oxidation and strip techniques, to mitigate high field and other effects. These process steps may form isolation regions15105, N+ source and drain regions15132and N− channel region15123. As illustrated inFIG.60E, a gate dielectric15107may be formed and a gate metal material may be deposited. The gate dielectric15107may be an atomic layer deposited (ALD) gate dielectric that may be paired with a work function specific gate metal in the industry standard high k metal gate process schemes described previously. Or the gate dielectric15107may be formed with a low temperature oxide deposition or low temperature microwave plasma oxidation of the silicon surfaces and then a gate metal material such as, for example, tungsten or aluminum may be deposited. The gate metal material may be chemically mechanically polished, and the gate area defined by masking and etching, thus forming gate electrode15108. As illustrated inFIG.60F, a low temperature thick oxide15109may be deposited and planarized, and source, gate, and drain contacts, and through layer via (not shown) openings may be masked and etched, thereby preparing the transistors to be connected via metallization. Thus gate contact15111may connect to gate electrode15108, and source & drain contacts15110may connect to N+ source and drain regions15132. Thru layer vias (not shown) may be formed to connect to the acceptor substrate connect strips (not shown) as described herein. Persons of ordinary skill in the art will appreciate that the illustrations inFIG.60AthroughFIG.60Fare exemplary only and are not drawn to scale. Such skilled persons will further appreciate that many variations may be possible such as, for example, a p-channel JLRCAT may be formed with changing the types of dopings appropriately. Moreover, the N− substrate donor wafer15100may be p type as well as the n type described above. Further, N− doped layer15103may include multiple layers of different doping concentrations and gradients to fine tune the eventual JLRCAT channel for electrical performance and reliability characteristics, such as, for example, off-state leakage current and on-state current. Furthermore, isolation regions15105may be formed by a hard mask defined process flow, wherein a hard mask stack, such as, for example, silicon oxide and silicon nitride layers, or silicon oxide and amorphous carbon layers. Moreover, CMOS JLRCATs may be constructed with n-JLRCATs in one mono-crystalline silicon layer and p-JLRCATs in a second mono-crystalline layer, which may include different crystalline orientations of the mono-crystalline silicon layers, such as, for example, <100>, <111> or <551>, and may include different contact silicides for substantially optimum contact resistance to p or n type source, drains, and gates. Furthermore, a back-gate or double gate structure may be formed for the JLRCAT and may utilize techniques described elsewhere in this document. Many other modifications within the scope of the illustrated embodiments of the invention will suggest themselves to such skilled persons after reading this specification. Thus the invention is to be limited only by the appended claims. An n-channel Trench MOSFET transistor suitable for a 3D IC may be constructed. The trench MOSFET may provide an improved drive current and the channel length can be tuned without area penalty. The trench MOSFET can be formed utilizing layer transfer techniques. 3D memory device structures may also be constructed in layers of mono-crystalline silicon and utilize the pre-processing of a donor wafer by forming wafer sized layers of various materials without a process temperature restriction, then layer transferring the pre-processed donor wafer to the acceptor wafer, followed by some example processing steps, and repeating this procedure multiple times, and then processing with either low temperature (below about 400° C.) or high temperature (greater than about 400° C.) after the final layer transfer to form memory device structures, such as, for example, transistors or memory bit cells, on or in the multiple transferred layers that may be physically aligned and may be electrically coupled to the acceptor wafer. The term memory cells may also describe memory bit cells in this document. Novel monolithic 3D Dynamic Random Access Memories (DRAMs) may be constructed in the above manner. Some embodiments of this present invention utilize the floating body DRAM type. Floating-body DRAM may be a next generation DRAM being developed by many companies such as Innovative Silicon, Hynix, and Toshiba. These floating-body DRAMs store data as charge in the floating body of an SOI MOSFET or a multi-gate MOSFET. Further details of a floating body DRAM and its operation modes can be found in U.S. Pat. Nos. 7,541,616, 7,514,748, 7,499,358, 7,499,352, 7,492,632, 7,486,563, 7,477,540, and 7,476,939, besides other literature. A monolithic 3D integrated DRAM can be constructed with floating-body transistors. Prior art for constructing monolithic 3D DRAMs used planar transistors where crystalline silicon layers were formed with either selective epi technology or laser recrystallization. Both selective epi technology and laser recrystallization may not provide perfectly single crystal silicon and often require a high thermal budget. A description of these processes is given in Chapter 13 of the book entitled “Integrated Interconnect Technologies for 3D Nanoelectronic Systems” by Bakir and Meindl. FIG.95A-Jdescribes an alternative process flow to construct a horizontally-oriented monolithic 3D DRAM. This monolithic 3D DRAM utilizes the floating body effect and independently addressable double-gate transistors. One mask is utilized on a “per-memory-layer” basis for the monolithic 3D DRAM concept shown inFIG.95A-J, while other masks may be shared between different layers. Independently addressable double-gated transistors provide an increased flexibility in the programming, erasing and operating modes of floating body DRAMs. The process flow may include several steps that occur in the following sequence.Step (A): Peripheral circuits22702with tungsten (W) wiring may be constructed. Isolation, such as oxide22701, may be deposited on top of peripheral circuits22702and tungsten word line (WL) wires22703may be constructed on top of oxide22701. WL wires22703may be coupled to the peripheral circuits22702through metal vias (not shown). Above WL wires22703and filling in the spaces, oxide layer22704may be deposited and may be chemically mechanically polished (CMP) in preparation for oxide-oxide bonding.FIG.95Aillustrates the structure after Step (A).Step (B):FIG.95Bshows a drawing illustration after Step (B). A p− Silicon wafer22706may have an oxide layer22708grown or deposited above it. Following this, hydrogen may be implanted into the p− Silicon wafer at a certain depth indicated by dashed lines as hydrogen plane22710. Alternatively, some other atomic species such as Helium could be (co-)implanted. This hydrogen implanted p− Silicon wafer22706may form the top layer22712. The bottom layer22714may include the peripheral circuits22702with oxide layer22704, WL wires22703and oxide22701. The top layer22712may be flipped and bonded to the bottom layer22714using oxide-to-oxide bonding of oxide layer22704to oxide layer22708.Step (C):FIG.95Cillustrates the structure after Step (C). The stack of top and bottom wafers after Step (B) may be cleaved at the hydrogen plane22710using either an anneal, a sideways mechanical force or other means of cleaving or thinning the top layer22712described elsewhere in this document. A CMP process may then be conducted. At the end of this step, a single-crystal p− Si layer22706′ may exist atop the peripheral circuits, and this has been achieved using layer-transfer techniques.Step (D):FIG.95Dillustrates the structure after Step (D). Using lithography and then ion implantation or other semiconductor doping methods such as plasma assisted doping (PLAD), n+ regions22716and p− regions22718may be formed on the transferred layer of p− Si after Step (C).Step (E):FIG.95Eillustrates the structure after Step (E). An oxide layer22720may be deposited atop the structure obtained after Step (D). A first layer of Si/SiO222722may be formed atop the peripheral circuits22702, oxide22701, WL wires22703, oxide layer22704and oxide layer22708.Step (F):FIG.95Fillustrates the structure after Step (F). Using procedures similar to Steps (B)-(E), additional Si/SiO2layers22724and22726may be formed atop Si/SiO2layer22722. A rapid thermal anneal (RTA) or spike anneal or flash anneal or laser anneal may be done to activate all implanted or doped regions within Si/SiO2layers22722,22724and22726(and possibly also the peripheral circuits22702). Alternatively, the Si/SiO2layers22722,22724and22726may be annealed layer-by-layer as soon as their implantations or dopings are done using an optical anneal system such as a laser anneal system. A CMP polish/plasma etch stop layer (not shown), such as silicon nitride, may be deposited on top of the topmost Si/SiO2layer, for example third Si/SiO2layer22726.Step (G):FIG.95Gillustrates the structure after Step (G). Lithography and etch processes may be utilized to make an exemplary structure as shown inFIG.95G, thus forming n+ regions22717, p− regions22719, and associated oxide regions.Step (H):FIG.95Hillustrates the structure after Step (H). Gate dielectric22728may be deposited and then an etch-back process may be employed to clear the gate dielectric from the top surface of WL wires22703. Then gate electrode22730may be deposited such that an electrical coupling may be made from WL wires22703to gate electrode22730. A CMP may be done to planarize the gate electrode22730regions such that the gate electrode22730may form many separate and electrically disconnected regions. Lithography and etch may be utilized to define gate regions over the p− silicon regions (e.g. p− Si regions22719after Step (G)). Note that gate width could be slightly larger than p− region width to compensate for overlay errors in lithography. A silicon oxide layer may be deposited and planarized. For clarity, the silicon oxide layer is shown transparent in the figure.Step (I):FIG.95Iillustrates the structure after Step (I). Bit-line (BL) contacts22734may be formed by etching and deposition. These BL contacts may be shared among all layers of memory.Step (J):FIG.95Jillustrates the structure after Step (J). Bit Lines (BLs)22736may be constructed. SL contacts (not shown) can be made into stair-like structures using techniques described in “Bit Cost Scalable Technology with Punch and Plug Process for Ultra High Density Flash Memory,”VLSI Technology,2007IEEE Symposium on, vol., no., pp. 14-15, 12-14 Jun. 2007 by Tanaka, H.; Kido, M.; Yahashi, K.; Oomura, M.; et al., following which contacts can be constructed to them. Formation of stair-like structures for SLs could be done in steps prior to Step (J) as well. A floating-body DRAM has thus been constructed, with (1) horizontally-oriented transistors, (2) some of the memory cell control lines, e.g., source-lines SL, constructed of heavily doped silicon and embedded in the memory cell layer, (3) side gates simultaneously deposited over multiple memory layers and independently addressable, and (4) monocrystalline (or single-crystal) silicon layers obtained by layer transfer techniques such as ion-cut. WL wires22703need not be on the top layer of the peripheral circuits22702, they may be integrated. WL wires22703may be constructed of another high temperature resistant material, such as NiCr. Novel monolithic 3D memory technologies utilizing material resistance changes may be constructed in a similar manner. There may be many types of resistance-based memories including phase change memory, Metal Oxide memory, resistive RAM (RRAM), memristors, solid-electrolyte memory, ferroelectric RAM, MRAM, etc. Background information on these resistive-memory types may be given in “Overview of candidate device technologies for storage-class memory,”IBM Journal of Research and Development, vol. 52, no. 4.5, pp. 449-464, July 2008 by Burr, G. W., et. al. The contents of this document are incorporated in this specification by reference. As illustrated inFIGS.37A to37M, a resistance-based 3D memory with one additional masking step per memory layer may be constructed that is suitable for 3D IC manufacturing. This 3D memory may utilize double gated MOSFET select transistors and may have a resistance-based memory element in series with the select transistor. As illustrated inFIG.37A, a silicon substrate with peripheral circuitry10302may be constructed with high temperature (greater than about 400° C.) resistant wiring, such as, for example, Tungsten. The peripheral circuitry substrate10302may include memory control circuits as well as circuitry for other purposes and of various types, such as, for example, analog, digital, RF, or memory. The peripheral circuitry substrate10302may include circuits that can withstand an additional rapid-thermal-anneal (RTA) or flash anneal and still remain operational and retain good performance. For this purpose, the peripheral circuits may be formed such that they have been subject to a weak RTA or no RTA for activating dopants. The top surface of the peripheral circuitry substrate10302may be prepared for oxide wafer bonding with a deposition of a silicon oxide layer10304, thus forming acceptor wafer10314. As illustrated inFIG.37B, a mono-crystalline silicon donor wafer10312may be, for example, processed to include a wafer sized layer of P− doping (not shown) which may have a different dopant concentration than the P− substrate10306. The P− doping layer may be formed by ion implantation and thermal anneal. A screen oxide layer10308may be grown or deposited prior to the implant to protect the silicon from implant contamination and to provide an oxide surface for later wafer to wafer bonding. A layer transfer demarcation plane10310(shown as a dashed line) may be formed in donor wafer10312within the P− substrate10306or the P− doping layer (not shown) by hydrogen implantation or other methods as previously described. Both the donor wafer10312and acceptor wafer10314may be prepared for wafer bonding as previously described and then bonded at the surfaces of oxide layer10304and oxide layer10308, at a low temperature (less than about 400° C. suitable for lowest stresses), or a moderate temperature (less than about 900° C.). As illustrated inFIG.37C, the portion of the P− layer (not shown) and the P− substrate10306that are above the layer transfer demarcation plane10310may be removed by cleaving and polishing, or other processes as previously described, such as ion-cut or other methods, thus forming the remaining mono-crystalline silicon P− layer10306′. Remaining P− layer10306′ and oxide layer10308may have been layer transferred to acceptor wafer10314. The top surface of P− layer10306′ may be chemically or mechanically polished smooth and flat. Transistors or portions of transistors may be formed and aligned to the acceptor wafer10314alignment marks (not shown). As illustrated inFIG.37D, N+ silicon regions10316may be lithographically defined and N type species, such as, for example, Arsenic, may be ion implanted into P− layer10306′. This implantation also may form remaining regions of P− silicon10318. As illustrated inFIG.37E, oxide layer10320may be deposited to prepare the surface for later oxide to oxide bonding, leading to the formation of the first Si/SiO2 layer10323that may include silicon oxide layer10320, N+ silicon regions10316, and P− silicon regions10318. As illustrated inFIG.37F, additional Si/SiO2 layers, such as, for example. second Si/SiO2 layer10325and third Si/SiO2 layer10327, may each be formed as described inFIGS.37A to37E. Oxide layer10329may be deposited. After substantially all the numbers of memory layers are constructed, a rapid thermal anneal (RTA) or flash anneal may be conducted to activate the dopants in substantially all of the memory layers10323,10325,10327and in the peripheral circuitry substrate10302. Alternatively, optical anneals, such as, for example, a laser based anneal, may be performed. As illustrated inFIG.37G, oxide layer10329, third Si/SiO2 layer10327, second Si/SiO2 layer10325and first Si/SiO2 layer10323may be lithographically defined and plasma/RIE etched to form a portion of the memory cell structure. The etching may result in regions of P− silicon10318′, which forms the transistor channels, and N+ regions10316′, which may form the source, drain and local source lines. Thus, these transistor elements or portions may have been defined by a common lithography step, which also may be described as a single lithography step, same lithography step, or one lithography step. As illustrated inFIG.37H, a gate dielectric and gate electrode material may be deposited, planarized with a chemical mechanical polish (CMP), and then lithographically defined and plasma/RIE etched to form gate dielectric regions10328which may be either self-aligned to and covered by gate electrodes10330(shown), or cover substantially the entire silicon/oxide multi-layer structure. The gate electrode10330and gate dielectric10328stack may be sized and aligned such that P− regions10318′ are substantially completely covered. The gate stack including gate electrode10330and gate dielectric10328may be formed with a gate dielectric, such as thermal oxide, and a gate electrode material, such as, for example, poly-crystalline silicon. Alternatively, the gate dielectric may be an atomic layer deposited (ALD) material that may be paired with a work function specific gate metal according to industry standard high k metal gate process schemes described previously. Moreover, the gate dielectric may be formed with a rapid thermal oxidation (RTO), a low temperature oxide deposition or low temperature microwave plasma oxidation of the silicon surfaces and then a gate electrode such as tungsten or aluminum may be deposited. SiO2 regions10322, the result from the etching of the three Si/SiO2 layers inFIG.37G, are denoted. As illustrated inFIG.37I, the entire structure may be covered with a gap fill oxide10332, which may be planarized with chemical mechanical polishing. The oxide10332is shown transparent in the figure for clarity in illustration. Also shown are word-line regions (WL)10350, which may be coupled with and composed of gate electrodes10330, and source-line regions (SL)10352, composed of indicated N+ regions10316′. As illustrated inFIG.37J, bit-line (BL) contacts10334may be lithographically defined, then etched with, for example, plasma/RIE, through oxide10332, the three N+ regions10316′, and the associated oxide vertical isolation regions to connect substantially all memory layers vertically. BL contacts10334may then be processed by a photoresist removal. Resistance change material10338, such as, for example, hafnium oxide, may then be deposited, for example, with atomic layer deposition (ALD). The electrode for the resistance change memory element may then be deposited by ALD to form the BL contact/electrode10334. The excess deposited material may be polished to planarity at or below the top of oxide10332. Each BL contact/electrode10334with resistive change material10338may be shared among substantially all layers of memory, shown as three layers of memory inFIG.37J. As illustrated inFIG.37K, BL metal lines10336may be formed and connected to the associated BL contacts10334with resistive change material10338. Contacts and associated metal interconnect lines (not shown) may be formed for the WL and SL at the memory array edges. A through layer via (not shown) may be formed to electrically couple the BL, SL, and WL metallization to the acceptor wafer10314peripheral circuitry via an acceptor wafer metal connect pad (not shown). FIG.37L1is a cross section cut II view ofFIG.37L, while FIG.37L2is a cross-sectional cut III view ofFIG.37L. FIG.37L2shows BL metal line10336, oxide10332, BL contact/electrode10334, resistive change material10338, WL regions10350, gate dielectric10328, P− regions10318′, N+ regions10316′, and peripheral circuitry substrate10302. The BL contact/electrode10334may couple to one side, N+ regions10326, of the three levels of resistive change material10338. The other side of the resistive change material10338may be coupled to N+ regions10316′. The P− regions10318′ with associated N+ regions10316′ and10326on each side may form the source, channel, and drain of the select transistor. FIG.37L2shows BL metal lines10336, oxide10332, gate electrode10330, gate dielectric10328, P− regions10318′, interlayer oxide regions (‘ox’), and peripheral circuitry substrate10302. The gate electrode10330may be common to all six P− regions10318′ and may control the six double gated MOSFET select transistors. As illustrated inFIG.37M, a single exemplary double gated MOSFET select transistor on the first Si/SiO2 layer10323may include P− region10318′ (functioning as the transistor channel), N+ region10316′ and N+ region10326(functioning as source and drain), and two gate electrodes10330with associated gate dielectrics10328. The transistor may be electrically isolated from beneath by oxide layer10308. The above flow may enable the formation of a resistance-based 3D memory with one additional masking step per memory layer constructed by layer transfers of wafer sized doped mono-crystalline silicon layers and may be connected to an underlying multi-metal layer semiconductor device. Persons of ordinary skill in the art will appreciate that the illustrations inFIGS.37A through37Mare exemplary only and are not drawn to scale. Such skilled persons will further appreciate that many variations may be possible such as, for example, the transistors may be of another type, such as RCATs. Additionally, the contacts may utilize doped poly-crystalline silicon, or other conductive materials. Moreover, the stacked memory layer may be connected to a periphery circuit that may be above the memory stack. Further, Si/SiO2 layers10323,10325and10327may be annealed layer-by-layer as soon as their associated implantations are complete by using a laser anneal system. Many other modifications within the scope of the illustrated embodiments of the invention will suggest themselves to such skilled persons after reading this specification. Thus the invention is to be limited only by the appended claims. Charge trap NAND (Negated AND) memory devices may be another form of popular commercial non-volatile memories. Charge trap device may store their charge in a charge trap layer, wherein this charge trap layer then may influence the channel of a transistor. Background information on charge-trap memory can be found in “Integrated Interconnect Technologies for3D Nanoelectronic Systems”, Chapter 13, Artech House, 2009 by Bakir and Meindl (hereinafter Bakir), “A Highly Scalable 8-Layer 3D Vertical-Gate (VG) TFT NAND Flash Using Junction-Free Buried Channel BE-SONOS Device,” Symposium on VLSI Technology, 2010 by Hang-Ting Lue, et al. and “Introduction to Flash memory,” Proc. IEEE 91, 489-502 (2003) by R. Bez, et al. Work described in Bakir utilized selective epitaxy, laser recrystallization, or polysilicon to form the transistor channel, which can result in less than satisfactory transistor performance. The architectures shown inFIG.38following may be relevant for any type of charge-trap memory. As illustrated inFIG.38AtoFIG.38G, a charge trap based 3D memory with zero additional masking steps per memory layer 3D memory may be constructed that may be suitable for 3D IC manufacturing. This 3D memory may utilize NAND strings of charge trap junction-less transistors with junction-less select transistors constructed in mono-crystalline silicon. As illustrated inFIG.38A, a silicon substrate with peripheral circuitry10602may be constructed with high temperature (e.g., greater than about 400° C.) resistant wiring, such as, for example, Tungsten. The peripheral circuitry substrate10602may include memory control circuits as well as circuitry for other purposes and of various types, such as, for example, analog, digital, RF, or memory. The peripheral circuitry substrate10602may include peripheral circuits that can withstand an additional rapid-thermal-anneal (RTA) or flash anneal and still remain operational and retain good performance. For this purpose, the peripheral circuits may be formed such that they have been subject to a weak RTA or no RTA for activating dopants. The top surface of the peripheral circuitry substrate10602may be prepared for oxide wafer bonding with a deposition of a silicon oxide layer10604, thus forming acceptor substrate10614. As illustrated inFIG.38B, a mono-crystalline silicon donor wafer10612may be processed to include a wafer sized layer of N+ doping (not shown) which may have a different dopant concentration than the N+ substrate10606. The N+ doping layer may be formed by ion implantation and thermal anneal. A screen oxide layer10608may be grown or deposited prior to the implant to protect the silicon from implant contamination and to provide an oxide surface for later wafer to wafer bonding. A layer transfer demarcation plane10610(shown as a dashed line) may be formed in donor wafer10612within the N+ substrate10606or the N+ doping layer (not shown) by hydrogen implantation or other methods as previously described. Both the donor wafer10612and acceptor substrate10614may be prepared for wafer bonding as previously described and then bonded at the surfaces of oxide layer10604and oxide layer10608, at a low temperature (e.g., less than about 400° C. suitable for lowest stresses), or a moderate temperature (e.g., less than about 900° C.). As illustrated inFIG.38C, the portion of the N+ layer (not shown) and the N+ wafer substrate10606that may be above the layer transfer demarcation plane10610may be removed by cleaving and polishing, or other processes as previously described, such as ion-cut or other methods, thus forming the remaining mono-crystalline silicon N+ layer10606′. Remaining N+ layer10606′ and oxide layer10608may have been layer transferred to acceptor substrate10614. The top surface of N+ layer10606′ may be chemically or mechanically polished smooth and flat. Oxide layer10620may be deposited to prepare the surface for later oxide to oxide bonding. This bonding may now form the first Si/SiO2 layer10623including silicon oxide layer10620, N+ silicon layer10606′, and oxide layer10608. As illustrated inFIG.38D, additional Si/SiO2 layers, such as, for example, second Si/SiO2 layer10625and third Si/SiO2 layer10627, may each be formed as described inFIG.38AtoFIG.38C. Oxide layer10629may be deposited to electrically isolate the top N+ silicon layer. As illustrated inFIG.38E, oxide layer10629, third Si/SiO2 layer10627, second Si/SiO2 layer10625and first Si/SiO2 layer10623may be lithographically defined and plasma/RIE etched to form a portion of the memory cell structure, which may now include regions of N+ silicon10626and oxide10622. Thus, these transistor elements or portions may have been defined by a common lithography step, which also may be described as a single lithography step, same lithography step, or one lithography step. As illustrated inFIG.38F, a gate stack may be formed with growth or deposition of a charge trap gate dielectric layer, such as thermal oxide and silicon nitride layers (ONO: Oxide-Nitride-Oxide), and a gate metal electrode layer, such as doped or undoped poly-crystalline silicon. The gate metal electrode layer may then be planarized with chemical mechanical polishing. Alternatively, the charge trap gate dielectric layer may include silicon or III-V nano-crystals encased in an oxide. The select transistor area10638may include a non-charge trap dielectric. The gate metal electrode regions10630and gate dielectric regions10628of both the NAND string area10636and select transistor area10638may be lithographically defined and plasma/RIE etched. As illustrated inFIG.38G, the entire structure may be covered with a gap fill oxide10632, which may be planarized with chemical mechanical polishing. The gap fill oxide10632is shown transparent in the figure for clarity in illustration. Select metal lines10646may be formed and connected to the associated select gate contacts10634. Contacts and associated metal interconnect lines (not shown) may be formed for the WL and SL at the memory array edges. Word-line regions (WL)10636, gate metal electrode regions10630, and bit-line regions (BL)10652including indicated N+ silicon regions10626, are shown. Source regions10644may be formed by a trench contact etch and filled to couple to the N+ silicon regions on the source end of the NAND string10636. A through layer via (not shown) may be formed to electrically couple the BL, SL, and WL metallization to the acceptor substrate10614peripheral circuitry via an acceptor wafer metal connect pad (not shown). This flow may enable the formation of a charge trap based 3D memory with zero additional masking steps per memory layer constructed by layer transfers of wafer sized doped layers of mono-crystalline silicon and this 3D memory may be connected to an underlying multi-metal layer semiconductor device. Persons of ordinary skill in the art will appreciate that the illustrations inFIG.38AthroughFIG.38Gare exemplary only and are not drawn to scale. Such skilled persons will further appreciate that many variations may be possible such as, for example, BL or SL contacts may be constructed in a staircase manner as described previously. Moreover, the stacked memory layer may be connected to a periphery circuit that may be above the memory stack. Additionally, each tier of memory could be configured with a slightly different donor wafer N+ layer doping profile. Further, the memory could be organized in a different manner, such as BL and SL interchanged, or where buried wiring for the memory array may be below the memory layers but above the periphery. Additional types of 3D charge trap memories may be constructed by layer transfer of mono-crystalline silicon; for example, those found in “A Highly Scalable 8-Layer 3D Vertical-Gate (VG) TFT NAND Flash Using Junction-Free Buried Channel BE-SONOS Device,” Symposium on VLSI Technology, 2010 by Hang-Ting Lue, et al., and “Multi-layered Vertical Gate NAND Flash overcoming stacking limit for terabit density storage”, Symposium on VLSI Technology, 2009 by W. Kim, S. Choi, et al. Many other modifications within the scope of the illustrated embodiments of the invention will suggest themselves to such skilled persons after reading this specification. Thus the invention is to be limited only by the appended claims. Floating gate (FG) memory devices may be another form of popular commercial non-volatile memories. Floating gate devices may store their charge in a conductive gate (FG) that may be nominally isolated from unintentional electric fields, wherein the charge on the FG then influences the channel of a transistor. Background information on floating gate flash memory can be found in “Introduction to Flash memory”, Proc. IEEE 91, 489-502 (2003) by R. Bez, et al. The architectures shown inFIG.39andFIG.40may be relevant for any type of floating gate memory. As illustrated inFIG.39AtoFIG.39G, a floating gate based 3D memory with two additional masking steps per memory layer may be constructed that is suitable for 3D IC manufacturing. This 3D memory may utilize NAND strings of floating gate transistors constructed in mono-crystalline silicon. As illustrated inFIG.39A, a P− substrate donor wafer10700may be processed to include a wafer sized layer of P− doping10704. The P-doped layer10704may have the same or a different dopant concentration than the P− substrate donor wafer10700. The P− doped layer10704may have a vertical dopant gradient. The P− doped layer10704may be formed by ion implantation and thermal anneal. A screen oxide10701may be grown before the implant to protect the silicon from implant contamination and to provide an oxide surface for later wafer to wafer bonding. As illustrated inFIG.39B, the top surface of P− substrate donor wafer10700may be prepared for oxide wafer bonding with a deposition of an oxide or by thermal oxidation of the P− doped layer10704to form oxide layer10702, or a re-oxidation of implant screen oxide10701. A layer transfer demarcation plane10799(shown as a dashed line) may be formed in P− substrate donor wafer10700or P− doped layer10704(shown) by hydrogen implantation10707or other methods as previously described. Both the P− substrate donor wafer10700and acceptor wafer10710may be prepared for wafer bonding as previously described and then bonded, for example, at a low temperature (less than about 400° C.) to minimize stresses. The portion of the P− doped layer10704and the P− substrate donor wafer10700that are above the layer transfer demarcation plane10799may be removed by cleaving and polishing, or other processes as previously described, such as ion-cut or other methods. As illustrated inFIG.39C, the remaining P− doped layer10704′, and oxide layer10702may have been layer transferred to acceptor wafer10710. Acceptor wafer10710may include peripheral circuits such that they can withstand an additional rapid-thermal-anneal (RTA) or flash anneal and may still remain operational and retain good performance. For this purpose, the peripheral circuits may be formed such that they have been subjected to a weak RTA or no RTA for activating dopants. Also, the peripheral circuits may utilize a refractory metal such as, for example, tungsten that can withstand high temperatures greater than about 400° C. The top surface of P− doped layer10704′ may be chemically or mechanically polished smooth and flat. Transistors may be formed and aligned to the acceptor wafer10710alignment marks (not shown). As illustrated inFIG.39Da partial gate stack may be formed with growth or deposition of a tunnel oxide10722, such as, for example, thermal oxide, and a FG gate metal material10724, such as, for example, doped or undoped poly-crystalline silicon. Shallow trench isolation (STI) oxide regions (not shown) may be lithographically defined and plasma/RIE etched to at least the top level of oxide layer10702, thus removing regions of P− doped layer10704′ of mono-crystalline silicon and forming P− doped regions10720. A gap-fill oxide may be deposited and CMP'ed flat to form conventional STI oxide regions (not shown). As illustrated inFIG.39E, an inter-poly oxide layer, such as silicon oxide and silicon nitride layers (ONO: Oxide-Nitride-Oxide), and a Control Gate (CG) gate metal material, such as doped or undoped poly-crystalline silicon, may be deposited. The gate stacks10728may be lithographically defined and plasma/RIE etched, thus substantially removing regions of CG gate metal material, inter-poly oxide layer, FG gate metal material10724, and tunnel oxide10722. This removal may result in the gate stacks10728including CG gate metal regions10726, inter-poly oxide regions10725, FG gate metal regions10724′, and tunnel oxide regions10722′. For example, only one gate stack10728is annotated with region tie lines for clarity in illustration. A self-aligned N+ source and drain implant may be performed to create inter-transistor source and drains10734and end of NAND string source and drains10730. The entire structure may be covered with a gap fill oxide10750, which may be planarized with chemical mechanical polishing. The oxide surface may be prepared for oxide to oxide wafer bonding as previously described. This bonding may now form the first tier of memory transistors10742including oxide10750, gate stacks10728, inter-transistor source and drains10734, end of NAND string source and drains10730, P− silicon regions10720, and oxide layer10702. As illustrated inFIG.39F, the transistor layer formation, bonding to acceptor wafer10710oxide10750, and subsequent transistor formation as described inFIG.39AtoFIG.39Dmay be repeated to form the second tier10744of memory transistors on top of the first tier of memory transistors10742. After substantially all the memory layers are constructed, a rapid thermal anneal (RTA) or flash anneal may be conducted to activate the dopants in substantially all of the memory layers and in the acceptor wafer10710peripheral circuits. Alternatively, optical anneals, such as, for example, a laser based anneal, may be performed. As illustrated inFIG.39G, source line (SL) ground contact10748and bit line contact10749may be lithographically defined, etched with plasma/RIE through oxide10750, end of NAND string source and drains10730, and P− regions10720of each memory tier, and the associated oxide vertical isolation regions to connect substantially all memory layers vertically. SL ground contact10748and bit line contact10749may then be processed by a photoresist removal. Metal or heavily doped poly-crystalline silicon may be utilized to fill the contacts and metallization utilized to form BL and SL wiring (not shown). The gate stacks10728may be connected with a contact and metallization to form the word-lines (WLs) and WL wiring (not shown). A through layer via (not shown) may be formed to electrically couple the BL, SL, and WL metallization to the acceptor substrate10710peripheral circuitry via an acceptor wafer metal connect pad (not shown). This flow may enable the formation of a floating gate based 3D memory with two additional masking steps per memory layer constructed by layer transfers of wafer sized doped layers of mono-crystalline silicon and this 3D memory may be connected to an underlying multi-metal layer semiconductor device. Persons of ordinary skill in the art will appreciate that the illustrations inFIG.39AthroughFIG.39Gare exemplary only and are not drawn to scale. Such skilled persons will further appreciate that many variations may be possible such as, for example, BL or SL select transistors may be constructed within the process flow. Moreover, the stacked memory layer may be connected to a periphery circuit that is above the memory stack. Additionally, each tier of memory could be configured with a slightly different donor wafer P− layer doping profile. Further, the memory could be organized in a different manner, such as BL and SL interchanged, or where buried wiring for the memory array may be below the memory layers but above the periphery. Many other modifications within the scope of the illustrative embodiments of the invention will suggest themselves to such skilled persons after reading this specification. Thus the invention is to be limited only by the appended claims. As illustrated inFIG.40AtoFIG.40H, a floating gate based 3D memory with one additional masking step per memory layer 3D memory may be constructed that can be suitable for 3D IC manufacturing. This 3D memory may utilize 3D floating gate junction-less transistors constructed in mono-crystalline silicon. As illustrated inFIG.40A, a silicon substrate with peripheral circuitry10802may be constructed with high temperature (greater than about 400° C.) resistant wiring, such as, for example, Tungsten. The peripheral circuitry substrate10802may include memory control circuits as well as circuitry for other purposes and of various types, such as, for example, analog, digital, RF, or memory. The peripheral circuitry substrate10802may include peripheral circuits that can withstand an additional rapid-thermal-anneal (RTA) or flash anneal and still remain operational and retain good performance. For this purpose, the peripheral circuits may be formed such that they may have been subject to a weak RTA or no RTA for activating dopants. The top surface of the peripheral circuitry substrate10802may be prepared for oxide wafer bonding with a deposition of a silicon oxide layer10804, thus forming acceptor wafer10814. As illustrated inFIG.40B, a mono-crystalline N+ doped silicon donor wafer10812may be processed to include a wafer sized layer of N+ doping (not shown) which may have a different dopant concentration than the N+ substrate10806. The N+ doping layer may be formed by ion implantation and thermal anneal. A screen oxide layer10808may be grown or deposited prior to the implant to protect the silicon from implant contamination and to provide an oxide surface for later wafer to wafer bonding. A layer transfer demarcation plane10810(shown as a dashed line) may be formed in donor wafer10812within the N+ substrate10806or the N+ doping layer (not shown) by hydrogen implantation or other methods as previously described. Both the donor wafer10812and acceptor wafer10814may be prepared for wafer bonding as previously described and then may be bonded at the surfaces of oxide layer10804and oxide layer10808, at a low temperature (e.g., less than about 400° C. suitable for lowest stresses), or a moderate temperature (e.g., less than about 900° C.). As illustrated inFIG.40C, the portion of the N+ layer (not shown) and the N+ wafer substrate10806that are above the layer transfer demarcation plane10810may be removed by cleaving and polishing, or other processes as previously described, such as ion-cut or other methods, thus forming the remaining mono-crystalline silicon N+ layer10806′. Remaining N+ layer10806′ and oxide layer10808may have been layer transferred to acceptor wafer10814. The top surface of N+ layer10806′ may be chemically or mechanically polished smooth and flat. Transistors or portions of transistors may be formed and aligned to the acceptor wafer10814alignment marks (not shown). As illustrated inFIG.40D, N+ regions10816may be lithographically defined and then etched with plasma/RIE, thus removing regions of N+ layer10806′ and stopping on or partially within oxide layer10808. As illustrated inFIG.40E, a tunneling dielectric10818may be grown or deposited, such as thermal silicon oxide, and a floating gate (FG) material10828, such as doped or undoped poly-crystalline silicon, may be deposited. The structure may be planarized by chemical mechanical polishing to approximately the level of the N+ regions10816. The surface may be prepared for oxide to oxide wafer bonding as previously described, such as a deposition of a thin oxide. This bonding may now form the first memory layer10823including future FG regions10828, tunneling dielectric10818, N+ regions10816and oxide layer10808. As illustrated inFIG.40F, the N+ layer formation, bonding to an acceptor wafer, and subsequent memory layer formation as described inFIG.40A to108Emay be repeated to form the second layer of memory10825on top of the first memory layer10823. A layer of oxide10829may then be deposited. As illustrated inFIG.40G, FG regions10838may be lithographically defined and then etched with, for example, plasma/RIE, removing portions of oxide layer10829, future FG regions10828and oxide layer10808on the second layer of memory10825and future FG regions10828on the first memory layer10823, thus stopping on or partially within oxide layer10808of the first memory layer10823. As illustrated inFIG.40H, an inter-poly oxide layer10850, such as, for example, silicon oxide and silicon nitride layers (ONO: Oxide-Nitride-Oxide), and a Control Gate (CG) gate material10852, such as, for example, doped or undoped poly-crystalline silicon, may be deposited. The surface may be planarized by chemical mechanical polishing leaving a thinned oxide layer10829′. As shown in the illustration, this results in the formation of 4 horizontally oriented floating gate memory bit cells with N+ junction-less transistors. Contacts and metal wiring to form well-know memory access/decoding schemes may be processed and a through layer via (TLV) may be formed to electrically couple the memory access decoding to the acceptor substrate peripheral circuitry via an acceptor wafer metal connect pad. This flow may enable the formation of a floating gate based 3D memory with one additional masking step per memory layer constructed by layer transfer of wafer sized doped layers of mono-crystalline silicon and this 3D memory may be connected to an underlying multi-metal layer semiconductor device. Persons of ordinary skill in the art will appreciate that the illustrations inFIG.40AthroughFIG.40Hare exemplary only and are not drawn to scale. Such skilled persons will further appreciate that many variations may be possible such as, for example, memory cell control lines could be built in a different layer rather than the same layer. Moreover, the stacked memory layers may be connected to a periphery circuit that may be above the memory stack. Additionally, each tier of memory could be configured with a slightly different donor wafer N+ layer doping profile. Further, the memory could be organized in a different manner, such as BL and SL interchanged, or these architectures could be modified into a NOR flash memory style, or where buried wiring for the memory array may be below the memory layers but above the periphery. Many other modifications within the scope of the illustrative embodiments of the invention will suggest themselves to such skilled persons after reading this specification. It may be desirable to place the peripheral circuits for functions such as, for example, memory control, on the same mono-crystalline silicon or polysilicon layer as the memory elements or string rather than reside on a mono-crystalline silicon or polysilicon layer above or below the memory elements or string on a 3D IC memory chip. However, that memory layer substrate thickness or doping may preclude proper operation of the peripheral circuits as the memory layer substrate thickness or doping provides a fully depleted transistor channel and junction structure, such as, for example, FD-SOI. Moreover, for a 2D IC memory chip constructed on, for example, an FD-SOI substrate, wherein the peripheral circuits for functions such as, for example, memory control, must reside and properly function in the same semiconductor layer as the memory element, a fully depleted transistor channel and junction structure may preclude proper operation of the periphery circuitry, but may provide many benefits to the memory element operation and reliability. Also, the NAND string source-drain regions may be formed separately from the select and periphery transistors. Furthermore, persons of ordinary skill in the art will appreciate that the process steps and concepts of forming regions of thicker silicon for the memory periphery circuits may be applied to many memory types, such as, for example, charge trap, resistive change, DRAM, SRAM, and floating body DRAM. The monolithic 3D integration concepts described in this patent application can lead to novel embodiments of poly-crystalline silicon based memory architectures. While the following concepts inFIG.41are explained by using resistive memory architectures as an example, it will be clear to one skilled in the art that similar concepts can be applied to the NAND flash, charge trap, and DRAM memory architectures and process flows described previously in this patent application. As illustrated inFIG.41, an alternative embodiment of a resistance-based 3D memory with zero additional masking steps per memory layer may be constructed with methods that are suitable for 3D IC manufacturing. This 3D memory may utilize poly-crystalline silicon junction-less transistors that may have either a positive or a negative threshold voltage, a resistance-based memory element in series with a select or access transistor, and may have the periphery circuitry layer formed or layer transferred on top of the 3D memory array. A silicon oxide layer11032may be deposited or grown on top of silicon substrate11002. A layer of N+ doped poly-crystalline or amorphous silicon (not shown) may be deposited. The N+ doped poly-crystalline or amorphous silicon layer may be deposited using a chemical vapor deposition process, such as LPCVD or PECVD, or other process methods, and may be deposited doped with N+ dopants, such as, for example, Arsenic or Phosphorous, or may be deposited un-doped and subsequently doped with, such as, for example, ion implantation or PLAD (PLasma Assisted Doping) techniques. Silicon Oxide may then be deposited or grown (not shown). This oxide may now form the first Si/SiO2 layer comprised of N+ doped poly-crystalline or amorphous silicon layer and silicon oxide layer. Additional Si/SiO2 layers, such as, for example, second Si/SiO2 layer and third Si/SiO2 layer, may each be formed. Oxide layer may be deposited to electrically isolate the top N+ doped poly-crystalline or amorphous silicon layer. A Rapid Thermal Anneal (RTA) or flash anneal may be conducted to crystallize the N+ doped poly-crystalline silicon or amorphous silicon layers of first Si/SiO2 layer, second Si/SiO2 layer, and third Si/SiO2 layer, forming crystallized N+ silicon layers. Alternatively, an optical anneal, such as, for example, a laser anneal, could be performed alone or in combination with the RTA or other annealing processes. Temperatures during this step could be as high as about 700° C., and could even be as high as, for example, 1400° C. Since there may be no circuits or metallization underlying these layers of crystallized N+ silicon, very high temperatures (such as, for example, 1400° C.) can be used for the anneal process, leading to very good quality poly-crystalline silicon with few grain boundaries and very high carrier mobilities approaching those of mono-crystalline crystal silicon. Oxide layer, third Si/SiO2 layer, second Si/SiO2 layer and first Si/SiO2 layer may be lithographically defined and plasma/RIE etched to form a portion of the memory cell structure, which may now include multiple layers of regions of crystallized N+ silicon11026(previously crystallized N+ silicon layers) and oxide10032. Thus, these transistor elements or portions may have been defined by a common lithography step, which also may be described as a single lithography step, same lithography step, or one lithography step. A gate dielectric and gate electrode material may be deposited, planarized with a chemical mechanical polish (CMP), and then lithographically defined and plasma/RIE etched to form gate dielectric regions11028which may either be self-aligned to and covered by gate electrodes11030(shown), or cover the entire crystallized N+ silicon regions and oxide regions multi-layer structure. The gate stack including gate electrode and gate dielectric regions may be formed with a gate dielectric, such as thermal oxide, and a gate electrode material, such as poly-crystalline silicon. Alternatively, the gate dielectric may be an atomic layer deposited (ALD) material that may be paired with a work function specific gate metal according to industry standard high k metal gate process schemes described previously. Additionally, the gate dielectric may be formed with a rapid thermal oxidation (RTO), a low temperature oxide deposition or low temperature microwave plasma oxidation of the silicon surfaces and then a gate electrode such as tungsten or aluminum may be deposited. The entire structure may be covered with a gap fill oxide, which may be planarized with chemical mechanical polishing. Bit-line (BL) contacts, not shown for clarity, may be lithographically defined, etched with, for example, plasma/RIE, through oxide11032, the three crystallized N+ silicon regions11026, and the associated oxide vertical isolation regions11022to connect substantially all memory layers vertically. BL contacts may then be processed by a photoresist removal. Resistance change material11038, such as hafnium oxides or titanium oxides, may then be deposited, for example, with atomic layer deposition (ALD). The electrode for the resistance change memory element may then be deposited by ALD to form the electrode/BL contact. The excess deposited material may be polished to planarity at or below the top of oxide. Each BL contact with resistive change material may be shared among substantially all layers of memory. As illustrated inFIG.41, peripheral circuits11078may be constructed and then layer transferred, using methods described previously such as, for example, ion-cut with replacement gates, to the memory array. Thru layer vias (not shown) may be formed to electrically couple the periphery circuitry to the memory array BL (11036), WL (using gate electrode material11030), SL (regions11052) and other connections such as, for example, power and ground. Alternatively, the periphery circuitry may be formed and directly aligned to the memory array and silicon substrate11002utilizing the layer transfer of wafer sized doped layers and subsequent processing, such as, for example, the junction-less, Recess Channel Array Transistor (RCAT), V-groove, or bipolar transistor formation flows as previously described. This flow may enable the formation of a resistance-based multi-layer or 3D memory array with zero additional masking steps per memory layer, which may utilize poly-crystalline silicon junction-less transistors and may have a resistance-based memory element in series with a select transistor, and may be constructed by layer transfers of wafer sized doped poly-crystalline silicon layers, and this 3D memory array may be connected to an overlying multi-metal layer semiconductor device or periphery circuitry. Persons of ordinary skill in the art will appreciate that the illustrations inFIG.41are exemplary only and are not drawn to scale. Such skilled persons will further appreciate that many variations may be possible such as, for example, the RTAs and/or optical anneals of the N+ doped poly-crystalline or amorphous silicon layers may be performed after each Si/SiO2 layer may be formed. Additionally, N+ doped poly-crystalline or amorphous silicon layer may be doped P+, or with a combination of dopants and other polysilicon network modifiers to enhance the RTA or optical annealing crystallization and subsequent crystallization, and lower the N+ silicon layer resistivity. Moreover, doping of each crystallized N+ layer may be slightly different to compensate for interconnect resistances. Further, each gate of the double gated 3D resistance based memory may be independently controlled for better control of the memory cell. Furthermore, by proper choice of materials for memory layer transistors and memory layer wires (e.g., by using tungsten and other materials that withstand high temperature processing for wiring), standard CMOS transistors may be processed at high temperatures (e.g., greater than about 400° C.) to form the periphery circuits11078. Many other modifications within the scope of the illustrated embodiments of the invention will suggest themselves to such skilled persons after reading this specification. Thus the invention is to be limited only by the appended claims. An alternative embodiment of this present invention may be a monolithic 3D DRAM we call NuDRAM. It may utilize layer transfer and cleaving methods described in this document. It may provide high-quality single crystal silicon at low effective thermal budget, leading to considerable advantage over prior art. An illustration of a NuDRAM constructed with partially depleted SOI transistors is given inFIG.33A-F.FIG.33Adescribes the first step in the process. A p− wafer9201may have an oxide layer9202grown over it.FIG.33Bshows the next step in the process. Hydrogen H+ may be implanted into the wafer at a certain depth in the p− wafer9201. P− wafer9201may have a top layer of p doping of a differing concentration than that of the bulk of p− wafer9201, and that layer may be transferred. The final position of the hydrogen is depicted by the dotted line as hydrogen plane9203.FIG.33Cdescribes the next step in the process. A wafer with DRAM peripheral circuits9204may be prepared. This wafer may have transistors that have not seen RTA or flash anneal processes. Alternatively, a weak or partial RTA for the peripheral circuits may be used. Multiple levels of tungsten interconnect to connect together transistors in9204may be prepared. The wafer fromFIG.33Bmay be flipped and attached to the wafer with DRAM peripheral circuits9204using oxide-to-oxide bonding. The wafer may then be cleaved at the hydrogen plane9203using any cleave method described in this document. After cleave, the cleaved surface may be polished with CMP.FIG.33Dshows the next step in the process. A step of masking, etching, and low temperature oxide deposition may be performed, to define rows of diffusion, isolated by said oxide. The rows of diffusion and isolation may be aligned with the underlying peripheral circuits9204. After forming isolation regions, partially depleted SOI (PD-SOI) transistors may be constructed with formation of a gate dielectric9207, a gate electrode9205, and then patterning and etch of9207and9205followed by formation of ion implanted source/drain regions9208. Note that no Rapid Thermal Anneal (RTA) may be done at this step to activate the implanted source/drain regions9208. The masking step inFIG.33Dmay be aligned to the underlying peripheral circuits9204. An oxide layer9206may be deposited and polished with CMP.FIG.33Eshows the next step of the process. A second Partial Depleted Silicon On Insulator (PD-SOI) transistor layer9209may be formed atop the first PD-SOI transistor layer using steps similar toFIG.33A-D. These may be repeated multiple times to form the multilayer 3D DRAM. An RTA or flash anneal to activate dopants and crystallize polysilicon regions in substantially all the transistor layers may then be conducted. The next step of the process is described inFIG.33F. Via holes9210may be masked and may be etched to word-lines and source and drain connections through substantially all of the layers in the stack. Note that the gates of transistors9213are connected together to form word-lines in a similar fashion toFIG.89. Via holes may then be filled with a metal such as tungsten. Alternatively, heavily doped polysilicon may be used. Multiple layers of interconnects and vias may be constructed to form Bit-Lines9211and Source-Lines9212to complete the DRAM array. Array organization of the NuDRAM described inFIG.33may be similar to those depicted inFIG.89. An alternative method whereby to build both ‘n’ type and ‘p’ type transistors on the same layer may be to partially process the first phase of transistor formation on the donor wafer with normal CMOS processing including a ‘dummy gate’, a process known as gate-last transistors or process, or gate replacement transistors or process, or replacement gate transistors or process. In some embodiments of the invention, a layer transfer of the mono-crystalline silicon may be performed after the dummy gate is completed and before the formation of a replacement gate. Processing prior to layer transfer may have no temperature restrictions and the processing during and after layer transfer may be limited to low temperatures, generally, for example, below about 400° C. The dummy gate and the replacement gate may include various materials such as silicon and silicon dioxide, or metal and low k materials such as TiALN and HfO2. An example may be the high-k metal gate (HKMG) CMOS transistors that have been developed for the 45 nm, 32 nm, 22 nm, and future CMOS generations. Intel and TSMC may have shown the advantages of a ‘gate-last’ approach to construct high performance HKMG CMOS transistors (C, Auth et al., VLSI 2008, pp 128-129 and C. H. Jan et al, 2009 IEDM p. 647). As illustrated inFIG.27A, a bulk silicon donor wafer7000may be processed in the normal state of the art HKMG gate-last manner up to the step prior to where CMP exposure of the polysilicon dummy gates takes place.FIG.27Aillustrates a cross section of the bulk silicon donor wafer7000, the isolation7002between transistors, the polysilicon7004and gate oxide7005of both n-type and p-type CMOS dummy gates, their associated source and drains7006for NMOS and7007for PMOS, and the interlayer dielectric (ILD)7008. These structures ofFIG.27Aillustrate completion of the first phase of transistor formation. At this step, or alternatively just after a CMP of ILD7008to expose the polysilicon dummy gates or to planarize the ILD7008and not expose the dummy gates, an implant of an atomic species7010, such as, for example, H+, may prepare the cleave plane7012in the bulk of the donor substrate for layer transfer suitability, as illustrated inFIG.27B. The donor wafer7000may be now temporarily bonded to carrier substrate7014at interface7016as illustrated inFIG.27Cwith a low temperature process that may facilitate a low temperature release. The carrier substrate7014may be a glass substrate to enable state of the art optical alignment with the acceptor wafer. A temporary bond between the carrier substrate7014and the donor wafer7000at interface7016may be made with a polymeric material, such as polyimide DuPont HD3007, which can be released at a later step by laser ablation, Ultra-Violet radiation exposure, or thermal decomposition. Alternatively, a temporary bond may be made with uni-polar or bi-polar electrostatic technology such as, for example, the Apache tool from Beam Services Inc. The donor wafer7000may then be cleaved at the cleave plane7012and may be thinned by chemical mechanical polishing (CMP) so that the transistor isolation7002may be exposed at the donor layer face7018as illustrated inFIG.27D. Alternatively, the CMP could continue to the bottom of the junctions to create a fully depleted SOI layer. As shown inFIG.27E, the thin mono-crystalline donor layer face7018may be prepared for layer transfer by a low temperature oxidation or deposition of an oxide7020, and plasma or other surface treatments to prepare the oxide surface7022for wafer oxide-to-oxide bonding. Similar surface preparation may be performed on the808acceptor wafer in preparation for oxide-to-oxide bonding. A low temperature (for example, less than about 400° C.) layer transfer flow may be performed, as illustrated inFIG.27E, to transfer the thinned and first phase of transistor formation pre-processed HKMG transistor silicon layer7001with attached carrier substrate7014to the acceptor wafer808. Acceptor wafer808may include metallization comprising metal strips7024to act as landing pads for connection between the circuits formed on the transferred layer with the underlying circuits of layer or layer within acceptor wafer808. As illustrated inFIG.27F, the carrier substrate7014may then be released using a low temperature process such as laser ablation. The bonded combination of acceptor wafer808and HKMG transistor silicon layer7001may now be ready for normal state of the art gate-last transistor formation completion. As illustrated inFIG.27G, the ILD7008may be chemical mechanically polished to expose the top of the polysilicon dummy gates. The dummy polysilicon gates may then be removed by etching and the hi-k gate dielectric7026and the PMOS specific work function metal gate7028may be deposited. The PMOS work function metal gate may be removed from the NMOS transistors and the NMOS specific work function metal gate7030may be deposited. An aluminum overfill7032may be performed on both NMOS and PMOS gates and the metal CMP'ed. As illustrated inFIG.27H, a dielectric layer7031may be deposited and the normal gate contact7034and source/drain7036contact formation and metallization may now be performed to connect the transistors on that mono-crystalline layer and to connect to the acceptor wafer808top metal strip7024with through via7040providing connection through the transferred layer from the donor wafer to the acceptor wafer. The top metal layer may be formed to act as the acceptor wafer landing strips for a repeat of the above process flow to stack another preprocessed thin mono-crystalline layer of two-phase formed transistors. The above process flow may also be utilized to construct gates of other types, such as, for example, doped polysilicon on thermal oxide, doped polysilicon on oxynitride, or other metal gate configurations, as ‘dummy gates,’ may perform a layer transfer of the thin mono-crystalline layer, replace the gate electrode and gate oxide, and then proceed with low temperature interconnect processing. An alternative layer transfer method may be utilized, such as, for example, SOI wafers with etchback of the bulk silicon to the buried oxide layer, in place of an ion-cut layer transfer scheme. Alternatively, the carrier substrate7014may be a silicon wafer, and infra-red light and optics could be utilized for alignments.FIG.28A-Gillustrate the use of a carrier wafer.FIG.28Aillustrates the first step of preparing transistors with dummy gate transistors8202on first donor wafer8206A. The first step may complete the first phase of transistor formation. FIG.28Billustrates forming a cleave line8208by implant8216of atomic particles such as H+. FIG.28Cillustrates permanently bonding the first donor wafer8206A to a second donor wafer8226. The permanent bonding may be oxide-to-oxide wafer bonding as described previously. FIG.28Dillustrates the second donor wafer8226acting as a carrier wafer after cleaving the first donor wafer off; leaving a thin layer8206of first donor wafer8206A with the now buried dummy gate transistors8202. FIG.28Eillustrates forming a second cleave line8218in the second donor wafer8226by implant8246of atomic species such as, for example, H+. FIG.28Fillustrates the second layer transfer step to bring the dummy gate transistors8202ready to be permanently bonded to the house808. For simplicity of the explanation, the steps of surface layer preparation done for each of these bonding steps have been left out. FIG.28Gillustrates the house808with the dummy gate transistors8202on top after cleaving off the second donor wafer and removing the layers on top of the dummy gate transistors. Now the flow may proceed to replace the dummy gates with the final gates, form the metal interconnection layers, and continue the 3D fabrication process. An alternative layer transfer method may be utilized, such as, for example, SOI wafers with etchback of the bulk silicon to the buried oxide layer, in place of an ion-cut layer transfer scheme. An illustrative alternative may be available when using the carrier wafer flow. In this flow we can use the two sides of the transferred layer to build NMOS on one side and PMOS on the other side. Proper timing of the replacement gate step in such a flow could enable full performance transistors properly aligned to each other. Compact 3D library cells may be constructed from this process flow. FIG.29Lis a top view drawing illustration of a repeating generic cell83L00as a building block for forming gate array, of two NMOS transistors83L04with shared diffusion83L05overlaying ‘face down’ two PMOS transistors83L02with shared diffusion. The NMOS transistors gates may overlay the PMOS transistors gates83L10and the overlayed gates may be connected to each other by via83L12. The Vdd power line83L06could run as part of the face down generic structure with connection to the upper layer using vias83L20. The diffusion connection83L08may be using the face down metal generic structure83L17and brought up by vias83L14,83L16,83L18. FIG.29L1is a drawing illustration of the generic cell83L00which may be customized by custom NMOS transistor contacts83L22,83L24and custom metal83L26to form a double inverter. The Vss power line83L25may run on top of the NMOS transistors. FIG.29L2is a drawing illustration of the generic cell83L00which may be customized to a NOR function, FIG.29L3is a drawing illustration of the generic cell83L00which may be customized to a NAND function and FIG.29L4is a drawing illustration of the generic cell83L00which may be customized to a multiplexer function. Accordingly generic cell83L00could be customized to substantially provide the logic functions, such as, for example, NAND and NOR functions, so a generic gate array using array of generic cells83L00could be customized with custom contacts vias and metal layers to any logic function. Thus, the NMOS, or n-type, transistors may be formed on one layer and the PMOS, or p-type, transistors may be formed on another layer, and connection paths may be formed between the n-type and p-type transistors to create Complementary Metal-Oxide-Semiconductor (CMOS) logic cells. Additionally, the n-type and p-type transistors layers may reside on the first, second, third, or any other of a number of layers in the 3D structure, substantially overlaying the other layer, and any other previously constructed layer. Another alternative, with reference toFIG.27and description, is illustrated inFIG.27B-1whereby the implant of an atomic species7010, such as, for example, H+, may be screened from the sensitive gate areas7003by first masking and etching a shield implant stopping layer of a dense material7050, for example 5000 angstroms of Tantalum, and may be combined with 5,000 angstroms of photoresist7052. This implant may create a segmented cleave plane7012in the bulk of the donor wafer silicon wafer and additional polishing may be applied to provide a smooth bonding surface for layer transfer suitability. The above flows, whether single type transistor donor wafer or complementary type transistor donor wafer, could be repeated multiple times to build a multi-level 3D monolithic integrated system. These flows could also provide a mix of device technologies in a monolithic 3D manner. For example, device I/O or analog circuitry such as, for example, phase-locked loops (PLL), clock distribution, or RF circuits could be integrated with CMOS logic circuits via layer transfer, or bipolar circuits could be integrated with CMOS logic circuits, or analog devices could be integrated with logic, and so on. Prior art shows alternative technologies of constructing 3D devices. The most common technologies are, either using thin film transistors (TFT) to construct a monolithic 3D device, or stacking prefabricated wafers and then using a through silicon via (TSV) to connect the prefabricated wafers. The TFT approach may be limited by the performance of thin film transistors while the stacking approach may be limited by the relatively large lateral size of the TSV via (on the order of a few microns) due to the relatively large thickness of the 3D layer (about 60 microns) and accordingly the relatively low density of the through silicon vias connecting them. According to many embodiments of the present invention that construct 3D IC based on layer transfer techniques, the transferred layer may be a thin layer of less than about 0.4 micron. This 3D IC with transferred layer according to some embodiments of the present invention may be in sharp contrast to TSV based 3D ICs in the prior art where the layers connected by TSV may be more than 5 microns thick and in most cases more than 50 microns thick. The alternative process flows presented may provide true monolithic 3D integrated circuits. It may allow the use of layers of single crystal silicon transistors with the ability to have the upper transistors aligned to the underlying circuits as well as those layers aligned each to other and only limited by the Stepper capabilities. Similarly the contact pitch between the upper transistors and the underlying circuits may be compatible with the contact pitch of the underlying layers. While in the best current stacking approach the stack wafers are a few microns thick, the alternative process flows presented may suggest very thin layers of typically 100 nm, but recent work has demonstrated layers about 20 nm thin. Accordingly the presented alternatives allow for true monolithic 3D devices. This monolithic 3D technology may provide the ability to integrate with full density, and to be scaled to tighter features, at the same pace as the semiconductor industry. Additionally, true monolithic 3D devices may allow the formation of various sub-circuit structures in a spatially efficient configuration with higher performance than 2D equivalent structures. Illustrated below are some examples of how a 3D ‘library’ of cells may be constructed in the true monolithic 3D fashion. Another compact 3D library may be constructed whereby one or more layers of metal interconnect may be allowed between the NMOS and PMOS devices and one or more of the devices may be constructed vertically. A compact 3D CMOS 8 Input NAND cell may be constructed as illustrated inFIG.23AthroughFIG.23G. The NAND-8 cell schematic and 2D layout is illustrated inFIG.23A. The eight PMOS transistor6301sources6311may be tied together and to V+ supply and the PMOS drains6313may be tied together and to the NMOS A drain and to the output Y. Inputs A to H may be tied to one PMOS gate and one NMOS gate. Input A may be tied to the PMOS A gate and NMOS A gate, input B may be tied to the PMOS B gate and NMOS B gate, and so forth through input H may be tied to the PMOS H gate and NMOS H gate. The eight NMOS transistors6302may be coupled in series between the output Y and the PMOS drains6313and ground. The structure built in 3D described below will take advantage of these connections in the 3rd dimension. The topside view of the 3D NAND-8 cell, with no metal shown and with horizontal NMOS and PMOS devices, is illustrated inFIG.23B, the cell X cross sectional views is illustrated inFIG.23C, and the Y cross sectional view is illustrated inFIG.23D. The NAND-8 cell with vertical PMOS and horizontal NMOS devices are shown inFIG.23Efor topside view,23F for the X cross section view, and23H for the Y cross sectional view. The same reference numbers are used for analogous structures in the embodiment shown inFIG.23BthroughFIG.23Dand the embodiment shown inFIG.23EthroughFIG.23G. The eight PMOS transistor6301sources6311may be tied together in the PMOS silicon layer and to the V+ supply metal6316in the PMOS metal 1 layer through P+ to Metal contacts. The NMOS A drain and the PMOS A drain may be tied6313together with a through P+ to N+ contact6317and to the output Y supply metal6315in PMOS metal 2, and also may be connected to substantially all of the PMOS drain contacts through PMOS metal 16315. Input A on PMOS metal 26314may be tied6303to both the PMOS A gate and the NMOS A gate with a PMOS gate on STI to NMOS gate on STI contact6314. Substantially all the other inputs may be tied to P and N gates in similar fashion. The NMOS A source and the NMOS B drain may be tied together6320in the NMOS silicon layer. The NMOS H source6312may be tied connected to the ground line6318by a contact to NMOS metal 1 and to the back plane N+ ground layer. The transistor isolation oxides6300are illustrated. Accordingly a CMOS circuit may be constructed where the various circuit cells may be built on two silicon layers achieving a smaller circuit area and shorter intra and inter transistor interconnects. As interconnects may become dominating for power and speed, packing circuits in a smaller area would result in a lower power and faster speed end device. Persons of ordinary skill in the art will appreciate that a number of different process flows have been described with exemplary logic gates and memory bit cells used as representative circuits. Such skilled persons will further appreciate that whichever flow is chosen for an individual design, a library of all the logic functions for use in the design may be created so that the cells may easily be reused either within that individual design or in subsequent ones employing the same flow. Such skilled persons will also appreciate that many different design styles may be used for a given design. For example, a library of logic cells could be built in a manner that has uniform height called standard cells as is well known in the art. Alternatively, a library could be created for use in long continuous strips of transistors called a gated array which is also known in the art. In another alternative embodiment, a library of cells could be created for use in a hand crafted or custom design as is well known in the art. For example, in yet another alternative embodiment, any combination of libraries of logic cells tailored to these design approaches can be used in a particular design as a matter of design choice, the libraries chosen may employ the same process flow if they are to be used on the same layers of a 3D IC. Different flows may be used on different levels of a 3D IC, and one or more libraries of cells appropriate for each respective level may be used in a single design. Also known in the art are computer program products that may be stored in computer readable media for use in data processing systems employed to automate the design process, more commonly known as computer aided design (CAD) software. Persons of ordinary skill in the art will appreciate the advantages of designing the cell libraries in a manner compatible with the use of CAD software. Persons of ordinary skill in the art will realize that libraries of I/O cells, analog function cells, complete memory blocks of various types, and other circuits may also be created for one or more processing flows to be used in a design and that such libraries may also be made compatible with CAD software. Many other uses and embodiments will suggest themselves to such skilled persons after reading this specification, thus the scope of the illustrated embodiments of the invention is to be limited only by the appended claims. Additionally, when circuit cells are built on two or more layers of thin silicon as shown above, and enjoy the dense vertical through silicon via interconnections, the metallization layer scheme to take advantage of this dense 3D technology may be improved as follows.FIG.21illustrates the prior art of silicon integrated circuit metallization schemes. The conventional transistor silicon layer5902may be connected to the first metal layer5910through the contact5904. The dimensions of this interconnect pair of contact and metal lines generally may be at the minimum line resolution of the lithography and etch capability for that technology process node. Traditionally, this is called a ‘1×’ design rule metal layer. Usually, the next metal layer may be also at the “1×’ design rule, the metal line5912and via below5905and via above5906that connects metal line5912with5910or with5914where desired. Then the next few layers often may be constructed at twice the minimum lithographic and etch capability and called ‘2×’ metal layers, and have thicker metal for higher current carrying capability. These designs are illustrated with metal line5914paired with via5907and metal line5916paired with via5908inFIG.21. Accordingly, the metal via pairs of5918with5909, and5920with bond pad opening5922, represent the ‘4×’ metallization layers where the planar and thickness dimensions may be again larger and thicker than the 2× and 1× layers. The precise number of 1× or 2× or 4× layers may vary depending on interconnection needs and other requirements; however, the general flow may be that of increasingly larger metal line, metal space, and via dimensions as the metal layers may be farther from the silicon transistors and closer to the bond pads. The metallization layer scheme may be improved for 3D circuits as illustrated inFIG.22. The first mono- or poly-crystalline silicon device layer6024is illustrated as the NMOS silicon transistor layer from the above 3D library cells, but may also be a conventional logic transistor silicon substrate or layer. The ‘1×’ metal layers6020and6019may be connected with contact6010to the silicon transistors and vias6008and6009to each other or metal6018. The 2× layer pairs metal6018with via6007and metal6017with via6006. The 4× metal layer6016may be paired with via6005and metal6015, also at 4×. However, now via6004may be constructed in 2× design rules to enable metal line6014to be at 2×. Metal line6013and via6003may be also at 2× design rules and thicknesses. Vias6002and6001may be paired with metal lines6012and6011at the 1× minimum design rule dimensions and thickness. The through layer via6000of the illustrated PMOS layer transferred silicon6022may then be constructed at the 1× minimum design rules and provide for maximum density of the top layer. The precise numbers of 1× or 2× or 4× layers may vary depending on circuit area and current carrying metallization design rules and tradeoffs. The illustrated PMOS layer transferred silicon6022may be, for example, any of the low temperature devices illustrated herein. When a transferred layer is not optically transparent to shorter wavelength light, and hence not able to detect alignment marks and images to a nanometer or tens of nanometer resolution, due to the transferred layer or its carrier or holder substrate's thickness, infra-red (IR) optics and imaging may be utilized for alignment purposes. However, the resolution and alignment capability may not be satisfactory. In some embodiments of the present invention, alignment windows may be created that allow use of the shorter wavelength light, for example, for alignment purposes during layer transfer flows. As illustrated inFIG.42A, a generalized process flow may begin with a donor wafer11100that may be preprocessed with layers11102of conducting, semi-conducting or insulating materials that may be formed by deposition, ion implantation and anneal, oxidation, epitaxial growth, combinations of above, or other semiconductor processing steps and methods. The donor wafer11100may also be preprocessed with a layer transfer demarcation plane11199, such as, for example, a hydrogen implant cleave plane, before or after layers11102are formed, or may be thinned by other methods previously described. Alignment windows11130may be lithographically defined, plasma/RIE etched substantially through layers11102, layer transfer demarcation plane11199, and donor wafer11100, and then filled with shorter wavelength transparent material, such as, for example, silicon dioxide, and planarized with chemical mechanical polishing (CMP). For example, donor wafer11100may be further thinned by CMP. The size and placement on donor wafer11100of the alignment windows11130may be determined based on the maximum misalignment tolerance of the alignment scheme used while bonding the donor wafer11100to the acceptor wafer11110, and the placement locations of the acceptor wafer alignment marks11190. Alignment windows11130may be processed before or after layers11102are formed. Acceptor wafer11110may be a preprocessed wafer that has fully functional circuitry or may be a wafer with previously transferred layers, or may be a blank carrier or holder wafer, or other kinds of substrates and may be called a target wafer. The acceptor wafer11110and the donor wafer11100may be, for example, a bulk mono-crystalline silicon wafer or a Silicon On Insulator (SOI) wafer or a Germanium on Insulator (GeOI) wafer. Acceptor wafer11110metal connect pads or strips11180and acceptor wafer alignment marks11190are shown. Both the donor wafer11100and the acceptor wafer11110bonding surfaces11101and11111may be prepared for wafer bonding by depositions, polishes, plasma, or wet chemistry treatments to facilitate successful wafer to wafer bonding. As illustrated inFIG.42B, the donor wafer11100with layers11102, alignment windows11130, and layer transfer demarcation plane11199may then be flipped over, high resolution aligned to acceptor wafer alignment marks11190, and bonded to the acceptor wafer11110. As illustrated inFIG.42C, the donor wafer11100may be cleaved at or thinned as described elsewhere in this document to approximately the layer transfer demarcation plane11199, leaving a portion of the donor, donor wafer portion11100′, alignment windows11130′ and the pre-processed layers11102aligned and bonded to the acceptor wafer11110. As illustrated inFIG.42D, the remaining donor wafer portion11100′ may be removed by polishing or etching and the transferred layers11102may be further processed to create donor wafer device structures11150that may be precisely aligned to the acceptor wafer alignment marks11190, and the alignment windows11130′ may be further processed into alignment window regions11131. These donor wafer device structures11150may utilize through layer vias (TLVs)11160to electrically couple the donor wafer device structures11150to the acceptor wafer metal connect pads or strips11180. As the transferred layers11102may be thin, on the order of 200 nm or less in thickness, the TLVs may be easily manufactured as a normal metal to metal via may be, and said TLV may have state of the art diameters such as nanometers or tens of nanometers. TLV11160may be drawn in the database (not shown) so that it may be positioned approximately at the center of the acceptor wafer metal connect pads or strips11180and donor wafer devices structure metal connect pads or strips, and, hence, may be away from the ends of acceptor wafer metal connect pads or strips11180and donor wafer devices structure metal connect pads or strips at distances greater than approximately the nominal layer to layer misalignment margin. Additionally, when monolithically stacking multiple layers of transistors and circuitry, there may be a practical limit on how many layers can be effectively stacked. For example, the processing time in the wafer fabrication facility may be too long or yield too risky for a stack of 8 layers, and yet it may be acceptable for creating 4 layer stacks. It therefore may be desirable to create two 4 layer sub-stacks, that may be tested and error or yield corrected with, for example, redundancy schemes described elsewhere in the document, and then stack the two 4-layer sub-stacks to create the desired 8-layer 3D IC stack. The sub-stack transferred layer and substrate or carrier substrate may not be optically transparent to shorter wavelength light, and hence not able to detect alignment marks and images to a nanometer or tens of nanometer resolution, due to the transferred layer or its carrier or holder substrate's thickness or material composition. Infra-red (IR) optics and imaging may be utilized for alignment purposes. However, the resolution and alignment capability may not be satisfactory. In some embodiments of the present invention, alignment windows may be created that allow use of the shorter wavelengths of light for alignment purposes during layer transfer flows or traditional through silicon via (TSV) flows as a method to stack and electrically couple the sub-stacks. As illustrated inFIG.61Awith cross-sectional cuts I and II, a generalized process flow utilizing a carrier wafer or substrate may begin with a donor wafer15400that may be preprocessed with multiple layers of monolithically stacked transistors and circuitry sub-stack15402by 3D IC methods, including, for example, methods such as described in general inFIG.1and in many embodiments in this document. The donor wafer15400may also be preprocessed with a layer transfer demarcation plane15499, such as, for example, a hydrogen implant cleave plane, before or after multiple layers of monolithically stacked transistors and circuitry sub-stack15402is formed, or layer transfer demarcation plane15499may represent an SOI donor wafer buried oxide, or may be preprocessed by other methods previously described, such as, for example, use of a heavily boron doped layer. Alignment windows15430may be lithographically defined and may then be plasma/RIE etched substantially through the multiple layers of monolithically stacked transistors and circuitry sub-stack15402and then may be etched to approximately the layer transfer demarcation plane15499. InFIG.61A, the alignment windows15430are shown etched past the layer transfer demarcation plane15499, but may be etched shallower than the layer transfer demarcation plane15499. The alignment windows15430may then be filled with shorter wavelength transparent material, such as, for example, silicon dioxide, and then may be planarized with chemical mechanical polishing (CMP). The size and placement on donor wafer15400of the alignment windows15430may be determined based on the maximum misalignment tolerance of the alignment scheme used while bonding the donor wafer15400to the acceptor wafer15410, and the number and placement locations of the acceptor wafer alignment marks15490. Alignment windows15430may be processed before or after each or some of the layers of the multiple layers of monolithically stacked transistors and circuitry sub-stack15402are formed. Acceptor wafer15410may be a preprocessed wafer with multiple layers of monolithically stacked transistors and circuitry sub-stack15405. Acceptor wafer15410metal connect pads or strips15480and acceptor wafer alignment marks15490are shown and may be formed in the top device layer of the multiple layers of monolithically stacked transistors and circuitry sub-stack15405(shown), or may be formed in any of the other layers of multiple layers of monolithically stacked transistors and circuitry sub-stack15405(not shown), or may be formed in the substrate portion of the acceptor wafer15410(not shown). As illustrated inFIG.61Bwith cross-sectional cut I, carrier substrate15485, such as, for example, a glass or quartz substrate, may be temporarily bonded to the donor wafer at surface15401. Some carrier substrate temporary bonding methods and materials are described elsewhere in this document. As illustrated inFIG.61Cwith cross-sectional cut I, the donor wafer15400may be substantially thinned by previously described processes, such as, for example, cleaving at the layer transfer demarcation plane15499and polishing with CMP to approximately the bottom of the STI structures. The STI structures may be in the bottom layer of the donor wafer sub-stack multiple layers of monolithically stacked transistors and circuitry sub-stack15402. Alignment windows15431may be thus formed. Both the carrier substrate15485with donor wafer sub-stack multiple layers of monolithically stacked transistors and circuitry sub-stack15402and the acceptor wafer15410bonding surfaces, donor wafer bonding surface15481and acceptor bonding surface15411, may be prepared for wafer bonding by depositions, polishes, plasma, or wet chemistry treatments to facilitate successful wafer to wafer bonding. As illustrated inFIG.61Dwith cross-sectional cut I, the carrier substrate15485with donor wafer multiple layers of monolithically stacked transistors and circuitry sub-stack15402and alignment windows15431, may then be high resolution aligned to acceptor wafer alignment marks15490, and may be bonded to the acceptor wafer15410with multiple layers of monolithically stacked transistors and circuitry sub-stack15405at acceptor bonding surface15411and donor wafer bonding surface15481. Temperature controlled and profiled wafer bonding chucks may be utilized to compensate for run-out or other across the wafer and wafer section misalignment or expansion offsets. As illustrated inFIG.61Ewith cross-sectional cut I, the carrier substrate15485may be detached with processes described elsewhere in this document, for example, with laser ablation of a polymeric adhesion layer, thus leaving alignment windows15431and the pre-processed multiple layers of monolithically stacked transistors and circuitry sub-stack15402aligned and bonded to the acceptor wafer15410with multiple layers of monolithically stacked transistors and circuitry sub-stack15405, acceptor wafer15410metal connect pads or strips15480, and acceptor wafer alignment marks15490. As illustrated inFIG.61Fwith cross-sectional cut I, the transferred multiple layers of monolithically stacked transistors and circuitry sub-stack15402may be further processed to create layer to layer or sub-stack to sub-stack connections utilizing methods including, for example, through layer vias (TLVs)15460and metallization15465to electrically couple the transferred multiple layers of monolithically stacked transistors and circuitry sub-stack15402donor wafer device structures15450to the acceptor wafer metal connect pads or strips15480. As the thickness of the transferred multiple layers of monolithically stacked transistors and circuitry sub-stack15402increases, traditional via last TSV (Thru Silicon Via) processing may be utilized to electrically couple the transferred multiple layers of monolithically stacked transistors and circuitry sub-stack15402donor wafer device structures15450to the acceptor wafer metal connect pads or strips15480. TLV15460may be drawn in the database (not shown) so that it may be positioned approximately at the center of the acceptor wafer metal connect pads or strips15480and donor wafer devices structure metal connect pads or strips, and, hence, may be away from the ends of acceptor wafer metal connect pads or strips15480and donor wafer devices structure metal connect pads or strips at distances greater than approximately the nominal layer to layer misalignment margin. Persons of ordinary skill in the art will appreciate that the illustrations inFIG.61AthroughFIG.61Fare exemplary only and are not drawn to scale. Such skilled persons will further appreciate that many variations may be possible such as, for example, the acceptor wafer15410may have alignment windows over the alignment marks formed prior to the alignment and bonding step to the donor wafer. Additionally, a via-first TSV process may be utilized on the donor wafer15400prior to the wafer to wafer bonding. Moreover, the acceptor wafer15410and the donor wafer15400may be, for example, a bulk mono-crystalline silicon wafer or a Silicon On Insulator (SOI) wafer or a Germanium on Insulator (GeOI) wafer. Further, the carrier substrate may be a silicon wafer with a layer transfer demarcation plane and utilize methods, such as permanently oxide to oxide bonding the carrier wafer to the donor wafer and then cleaving and thinning after bonding to the acceptor wafer, described elsewhere in this document, to layer transfer the donor wafer device layers or sub-stack to the acceptor wafer. Moreover, the opening size of the alignment windows15430formed may be substantially minimized by use of pre-alignment with IR or other long wavelength light, and final high resolution alignment performed through the alignment windows15430with lower wavelength light. Many other modifications within the scope of the illustrated embodiments of the invention will suggest themselves to such skilled persons after reading this specification. Thus the invention is to be limited only by the appended claims. With reference toFIG.61, it may be desirable to have the circuitry interconnection between the underlying base wafer acceptor wafer15410with multiple layers of monolithically stacked transistors and circuitry sub-stack15405and the transferred layer of the donor wafer multiple layers of monolithically stacked transistors and circuitry sub-stack15402accomplished during the stacking step and processing. A potential advantage may be that there would be no need to leave room for the TLV15460. This may be desirable if the transferred layer donor wafer multiple layers of monolithically stacked transistors and circuitry sub-stack15402includes transistor layers plus multiple layers of interconnections and when many connections may be required between the underlying acceptor wafer15410with multiple layers of monolithically stacked transistors and circuitry sub-stack15405and the overlying transferred layer donor wafer multiple layers of monolithically stacked transistors and circuitry sub-stack15402. There are multiple techniques known in the art to form electrical connection as part of the bonding process of wafers but the challenge is the misalignment between the two structures bonded. This misalignment may be associated with the process of wafer bonding. As discussed before, the misalignment between wafers of current wafer to wafer bonding equipment is about one micrometer, which may be large with respect to the desired connectivity scale density of nanometer processing. To accomplish electrical connections between the acceptor wafer and the donor wafer the acceptor wafer may have on its top surface connection pads, which may include, for example, copper or aluminum, which will be called bottom-pads. The bottom surface of the donor wafer transferred layer may also have connection pads, which may include, for example, copper or aluminum, which will be called upper-pads. The bottom-pads and upper-pads may be placed one on top of the other to form electrical connections. If the bottom-pads and upper-pads are constructed large enough, then the wafer to wafer bonding misalignment may not limit the ability to connect. And accordingly, for example, for a 1 micrometer misalignment, the connectivity limit would be on the order of one connection per 1 micron square with bottom-pads and upper-pads sizes on the order of 1 micrometer on a side. The following alternative of the invention would allow much higher vertical connectivity than the wafer to wafer bonding misalignment limits. The planning of these connection pads need to be such that regardless of the misalignment (within a given maximum limit, for example, 1 micrometer) all the desired connections would be made, while avoiding forming shorts between two active independent connection paths. FIG.62Aillustrates an exemplary portion of a wafer sized or die sized plurality of bottom-pads15502andFIG.62Billustrates an exemplary portion of a wafer sized or die sized plurality of upper-pads15504and upper-pads15505(not all pads are reference number tie-lined for clarity of the illustrations). The design may be such that for each bottom-pad15502there may be at least one upper-pad15504or upper-pad15505that bottom-pad15502may be in full contact with after the layer transfer bonding and associated misalignment of designed pads, and in no case the upper-pad15504or upper-pad15505might form a short between two bottom-pads15502. Bottom-pad space15524, the space between two adjacent bottom-pads15502, may be made larger than the size of the upper-pads15504or upper-pads15505. An illustrative directional orientation cross15508is provided forFIG.62AtoFIG.62D. It should be noted that in a similar manner as typical semiconductor device design rules, spaces and structure sizing may need to account for process variations, such as lithographic and etch variations and biases. For example, the bottom-pad space15524may need to be large enough to avoid shorts even if the sizes of some pads, for example some of upper-pads15504or upper-pads15505, turn out large within the process window range at end of process. For simplicity of the explanation, the details of such rules extension for covering all the production-acceptable variations may be ignored, as these are well known in the practice of the art. As illustrated inFIG.62A, the bottom-pads15502may be arranged in repeating patterns of rows and columns. Each bottom-pad15502may be a square with sides15520and may be spaced bottom-pad space15524to the next column pad and spaced bottom-pad space15524to the next row. The upper-pads and layout may be constructed with sets of upper-pads15504and upper-pads15505as illustrated inFIG.62B. Each set of upper-pads may be arranged in row and column with the same repetition cycle and distance as the bottom-pads15502, and may be symmetrically offset with respect to each other so that each upper-pad15505may be placed in equal distance to the four upper-pads15504that may be around said upper-pad15505. The sizing of the pads and the distance between them may be set so that when upper-pad15504lands perfectly aligned to the North-West corner of a bottom-pad15502, the corresponding (of set) upper-pad15505, which is South-East of bottom-pad15502, may land aligned to the South-East corner of the same bottom-pad15502. It should be noted, that, as has been described before, misalignment of up to 1 micrometer could happen in current wafer bonding equipment in the direction of North-South or West-East but the angular misalignment may be quite small and would be less than 1 micrometer over the substantially the entire wafer size of 300 mm. Accordingly the design rule pad sizes and spaces could be adjusted to accommodate the angular misalignment. It may be appreciated that for any misalignment in North-Sought and in West-East direction that is within the misalignment range, there will at least one of the upper-pads in the set (upper-pads15504or upper-pads15505) that may come in substantially full contact with their corresponding bottom-pad15502. If upper-pads15504fall in the space between bottom-pads15502, then upper-pads15505would be in substantially full contact with a bottom pad155002, and vice-versa. The layout structure of connections illustrated inFIG.62AandFIG.62Bmay be made as follows in exemplary steps A to E.Step A: Upper-pad side length15506may be designed and drawn as the smallest allowed by the design rules, with upper-pads15504and upper-pads15505being the smallest square allowed by the design rules.Step B: Bottom-pad space15524may be made large enough so that upper-pads15504or upper-pads15505may not electrically short two adjacent bottom-pads15502.Step C: Bottom-pads15502may be squares with sides15520, sides15520which may be equal in distance to double the distance of bottom-pad space15524.Step D: The bottom-pads15502layout structure, as illustrated inFIG.62A, may be rows of bottom-pads15502as squares sized of sides15520and spaced bottom-pad space15524, and forming columns of squares bottom-pads15502spaced by bottom-pad space15524. The horizontal and vertical repetition may then be three times the bottom-pad space15524.Step E: The upper-pads structure, as illustrated inFIG.62B, may be two sets of upper-pads15504and upper-pads15505. Each set may be rows of squares sized upper-pad side length15506and may repeat every E-W length15510, where E-W length15510may be 3 times bottom-pad space15524, and forming columns of these squares repeating every N—S length15512, where N—S length15512may be 3 times bottom-pad space15524. The two sets may be offset in both in the West-East direction and the North-South direction so that each upper-pad15505may be placed in the middle of the space between four adjacent upper-pads15504. Such a pad structure as illustrated inFIG.62AandFIG.62Bmay provide a successful electrical connection of wires between two bonded wafers so there may always be at least one successful connection between the bottom wafer pad and one of its corresponding upper wafer pads, and no undesired shorts can occur. The structure may be designed such that for every bottom-pad15502there may be a potential pair of upper-pads15504and upper-pads15505of which at least one is forming good contact. The selection of which upper-pad (upper-pad15504or upper-pad15505) to utilize for electrical connections between the two bonded wafers could be based on a chip test structure which would test which pad set has a lower resistance, or by optical methods to measure the misalignment and then select upper-pads15504or upper-pads15505according to the misalignment the appropriate pad set. An electronic circuit could be constructed to route a signal from the bottom-pads15502through the electrically connected upper-pads15504or upper-pads15505to the appropriate circuit at the upper layer, such as the transferred layer of the donor wafer multiple layers of monolithically stacked transistors and circuitry sub-stack15402. Such switch matrix would need to be designed according to the maximum misalignment error and the number of signals within that range. The programming of the switch matrix to properly connect stack layer signals could be done based on, for example, an electrically read on-chip test structure or on an optical misalignment measurement. Such electronic switch matrices are known in the art and are not detailed herein. Additionally, the misalignment compensation and reroute to properly connect stack layer signals could be done in the transferred layer (such as the transferred layer of the donor wafer multiple layers of monolithically stacked transistors and circuitry sub-stack15402) metal connection layers and misalignment compensation structures as has been described before with respect toFIG.35. Another variation of such structures could be made to meet the same requirements as the bottom-pads/upper-pads structures described inFIG.62AandFIG.62B.FIG.62Cillustrates a repeating structure of bottom-pad strips15532andFIG.62Dillustrates the matching structures of upper-pad strips15534and the offset upper-pad strips15535. The layout and design of the structures inFIG.62CandFIG.62Dmay be similar to that described forFIG.62AandFIG.62B. Persons of ordinary skill in the art will appreciate that the illustrations inFIG.62AthroughFIG.62Dare exemplary only and are not drawn to scale. Such skilled persons will further appreciate that many variations may be possible such as, for example, the acceptor wafer and donor wafer in the discussion may be sub-stacks of multiple layers of circuitry and interconnect or may be singular layers of processed or pre-processed circuitry or doped layers. Moreover, misalignment between the two layers of circuitry which are desired to be connected may be a result from more than the wafer to wafer bonding process; for example, from lithographic capability, or thermal or stress induced continental drift. Further, bottom-pad space15524may not be symmetric in North-South and East-West directions. Furthermore, the orientation of the bottom and upper pads and spaces may not be in an orthogonal or Cartesian manner as illustrated, they could be angular or of polar co-ordinate type. Moreover, sides15520of bottom-pad15502may instead be not equal to each other and bottom-pad15502may be shaped, for example, as a rectangle. Moreover, upper pad side length15506of upper-pad15504or upper-pad15505may not be equal to each other and upper-pad15504or upper-pad15505may be shaped, for example, as a rectangle. Furthermore, bottom-pad15502and upper-pad15504or upper-pad15505may be shaped in circular or oval shapes. Moreover, upper-pad15504may be sized or shaped differently than upper-pad15505. Further, shorts may be designed in to allow for example, higher current carrying pad connections. Moreover, the misalignment compensation and reroute to properly connect stack layer signals may utilize programmable switches or programmable logic, and may be tied to the electrically read on-chip test structure. Furthermore, each set of upper-pads may be non-symmetrically offset with respect to each other so that each upper-pad15505may be placed in a non-equal distance to the four upper-pads15504that may be around said upper-pad15505. Many other modifications within the scope of the illustrated embodiments of the invention will suggest themselves to such skilled persons after reading this specification. Thus the invention is to be limited only by the appended claims. There may be many ways to build the multilayer 3D IC, as some embodiments of the invention may follow. Wafers could be processed sequentially one layer at a time to include one or more transistor layers and then connect the structure of one wafer on top of the other wafer. In such case the donor wafer, for example transferred layer of the donor wafer multiple layers of monolithically stacked transistors and circuitry sub-stack15402, may be a fully processed multi-layer wafer and the placing on top of the acceptor wafer, for example acceptor wafer15410, could include flipping it over or using a carrier method to avoid flipping. In each case the non-essential substrate could be cut or etched away using layer transfer techniques such as those described before. Wafers could be processed in parallel, each one potentially utilizing a different wafer fab or process flow and then proceeding as in the paragraph directly above. One wafer could contain non repeating structures while the other one would contain repeating structures such as memory or programmable logic. In such case there are strong benefits for high connectivity between the wafers, while misalignment can be less of an issue as the repeating structure might be tolerant of such misalignment. The transferred wafer or layer, for example transferred layer of the donor wafer multiple layers of monolithically stacked transistors and circuitry sub-stack15402, could include a repeating transistors structure but subsequent to the bonding the follow-on process would align to the structure correctly as described above to keep to a minimum the overhead resulting from the wafer bonding misalignment. FIG.59describes an embodiment of the invention, wherein a memory array14902may be constructed on a piece of silicon and peripheral transistors14904may be stacked atop the memory array14902. The peripheral transistors14904may be constructed well-aligned with the underlying memory array14902using any of the schemes described in this document. For example, the peripheral transistors may be junction-less transistors, recessed channel transistors or they could be formed with one of the repeating layout schemes described in this document. Through-silicon connections14906may connect the memory array14902to the peripheral transistors14904. The memory array may be DRAM memory, SRAM memory, flash memory, some type of resistive memory or in general, could be any memory type that may be commercially available. An additional use for the high density of TLVs11160inFIG.42D, or any such TLVs in this document, may be to thermally conduct heat generated by the active circuitry from one layer to another connected by the TLVs, such as, for example, donor layers and device structures to acceptor wafer or substrate. TLVs11160may also be utilized to conduct heat to an on chip thermoelectric cooler, heat sink, or other heat removing device. A portion of TLVs on a 3D IC may be utilized primarily for electrical coupling, and a portion may be primarily utilized for thermal conduction. In many cases, the TLVs may provide utility for both electrical coupling and thermal conduction. FIG.64illustrates a 3D integrated circuit. Two mono-crystalline silicon layers,16004and16016are shown. Silicon layer16016could be thinned down from its original thickness, and its thickness could be in the range of approximatelylum to approximately 50 um. Silicon layer16004may include transistors which could have gate electrode region16014, gate dielectric region16012, and shallow trench isolation (STI) regions16010. Silicon layer16016may include transistors which could have gate electrode region16034, gate dielectric region16032, and shallow trench isolation (STI) regions16030. A through-silicon via (TSV)16018could be present and may have a surrounding dielectric region16020. Wiring layers for silicon layer16004are indicated as16008and wiring dielectric is indicated as16006. Wiring layers for silicon layer16016are indicated as16038and wiring dielectric is indicated as16036. The heat removal apparatus, which could include a heat spreader and a heat sink, is indicated as16002. The heat removal problem for the 3D integrated circuit shown inFIG.64may be immediately apparent. The silicon layer16016is far away from the heat removal apparatus16002, and it may be difficult to transfer heat between silicon layer16016and heat removal apparatus16002. Furthermore, wiring dielectric regions16006do not conduct heat well, and this increases the thermal resistance between silicon layer16016and heat removal apparatus16002. FIG.65illustrates a 3D integrated circuit that could be constructed, for example, using techniques described herein and in US Patent Application 2011/0121366 and U.S. patent application Ser. No. 13/099,010. Two mono-crystalline silicon layers,16104and16116are shown. Silicon layer16116could be thinned down from its original thickness, and its thickness could be in the range of approximately 3 nm to approximately 1 um. Silicon layer16104may include transistors which could have gate electrode region16114, gate dielectric region16112, and shallow trench isolation (STI) regions16110. Silicon layer16116may include transistors which could have gate electrode region16134, gate dielectric region16132, and shallow trench isolation (STI) regions16122. It can be observed that the STI regions16122can go right through to the bottom of silicon layer16116and provide good electrical isolation. This, however, can cause challenges for heat removal from the STI surrounded transistors since STI regions16122may typically be insulators that do not conduct heat well. Therefore, the heat spreading capabilities of silicon layer16116with STI regions16122may be low. A through-layer via (TLV)16118could be present and may include its dielectric region16120. Wiring layers for silicon layer16104are indicated as16108and wiring dielectric is indicated as16106. Wiring layers for silicon layer16116are indicated as16138and wiring dielectric is indicated as16136. The heat removal apparatus, which could include a heat spreader and a heat sink, is indicated as16102. The heat removal problem for the 3D integrated circuit shown inFIG.65may be immediately apparent. The silicon layer16116is far away from the heat removal apparatus16102, and it may be difficult to transfer heat between silicon layer16116and heat removal apparatus16102. Furthermore, wiring dielectric regions16106do not conduct heat well, and this increases the thermal resistance between silicon layer16116and heat removal apparatus16102. The heat removal challenge may be further exacerbated by the poor heat spreading properties of silicon layer16116with STI regions16122. FIG.66andFIG.67illustrate how the power or ground distribution network of a 3D integrated circuit could assist heat removal.FIG.66illustrates an exemplary power distribution network or structure of the 3D integrated circuit. The 3D integrated circuit, could, for example, be constructed with two silicon layers16204and16216. The heat removal apparatus16202could include a heat spreader and a heat sink. The power distribution network or structure could consist of a global power grid16210that takes the supply voltage (denoted as VDD) from power pads and transfers it to local power grids16208and16206, which then transfer the supply voltage to logic cells or gates such as16214and16215. Vias16218and16212, such as the previously described TSV or TLV, could be used to transfer the supply voltage from the global power grid16210to local power grids16208and16206. The 3D integrated circuit could have similar distribution networks, such as for ground and other supply voltages, as well. Typically, many contacts may be made between the supply and ground distribution networks and silicon layer16204. As a result there may exist a low thermal resistance between the power/ground distribution network and the heat removal apparatus16202. Since power/ground distribution networks are typically constructed of conductive metals and could have low effective electrical resistance, they could have a low thermal resistance as well. Each logic cell or gate on the 3D integrated circuit (such as, for example 16214) is typically connected to VDD and ground, and therefore could have contacts to the power and ground distribution network. These contacts could help transfer heat efficiently (i.e. with low thermal resistance) from each logic cell or gate on the 3D integrated circuit (such as, for example 16214) to the heat removal apparatus16202through the power/ground distribution network and the silicon layer16204. FIG.67illustrates an exemplary NAND gate16320or logic cell and shows how all portions of this logic cell or gate could be located with low thermal resistance to the VDD or ground (GND) contacts. The NAND gate16320could consist of two pMOS transistors16302and two nMOS transistors16304. The layout of the NAND gate16320is indicated in16322. Various regions of the layout include metal regions16306, poly regions16308, n type silicon regions16310, p type silicon regions16312, contact regions16314, and oxide regions16324. pMOS transistors in the layout are indicated as16316and nMOS transistors in the layout are indicated as16318. It can be observed that substantially all parts of the exemplary NAND gate16320could have low thermal resistance to VDD or GND contacts since they are physically very close to them. Thus, substantially all transistors in the NAND gate16320can be maintained at desirable temperatures if the VDD or ground contacts are maintained at desirable temperatures. While the previous paragraph describes how an existing power distribution network or structure can transfer heat efficiently from logic cells or gates in 3D-ICs to their heat sink, many techniques to enhance this heat transfer capability will be described herein. These embodiments of the invention can provide several benefits, including lower thermal resistance and the ability to cool higher power 3D-ICs. As well, thermal contacts may provide mechanical stability and structural strength to low-k Back End Of Line (BEOL) structures, which may need to accommodate shear forces, such as from CMP and/or cleaving processes. These techniques may be useful for different implementations of 3D-ICs, including, for example, monolithic 3D-ICs and TSV-based 3D-ICs. FIG.68describes an embodiment of the invention, where the concept of thermal contacts is described. Two mono-crystalline silicon layers,16404and16416may have transistors. Silicon layer16416could be thinned down from its original thickness, and its thickness could be in the range of approximately 3 nm to approximately 1 um. Mono-crystalline silicon layer16404could have STI regions16410, gate dielectric regions16412, gate electrode regions16414and several other regions required for transistors (not shown). Mono-crystalline silicon layer16416could have STI regions16430, gate dielectric regions16432, gate electrode regions16434and several other regions required for transistors (not shown). Heat removal apparatus16402may include, for example, heat spreaders and heat sinks. In the example shown inFIG.68, mono-crystalline silicon layer16404is closer to the heat removal apparatus16402than other mono-crystalline silicon layers such as mono-crystalline silicon layer16416. Dielectric regions16406and16446could be used to electrically insulate wiring regions such as16422and16442respectively. Through-layer vias for power delivery16418and their associated dielectric regions16420are shown. A thermal contact16424can be used that connects the local power distribution network or structure, which may include wiring layers16442used for transistors in the silicon layer16404, to the silicon layer16404. Thermal junction region16426can be either a doped or undoped region of silicon, and further details of thermal junction region16426will be given inFIG.69. The thermal contact such as16424can be placed close to the corresponding through-layer via for power delivery16418; this helps transfer heat efficiently from the through-layer via for power delivery16418to thermal junction region16426and silicon layer16404and ultimately to the heat removal apparatus16402. For example, the thermal contact16424could be located within approximately 2 um distance of the through-layer via for power delivery16418in the X-Y plane (the through-layer via direction is considered the Z plane inFIG.68). While the thermal contact such as16424is described above as being between the power distribution network or structure and the silicon layer closest to the heat removal apparatus, the thermal contact could also be placed between the ground distribution network and the silicon layer closest to the heat sink. Furthermore, more than one thermal contact16424can be placed close to the through-layer via for power delivery16418. These thermal contacts can improve heat transfer from transistors located in higher layers of silicon such as16416to the heat removal apparatus16402. While mono-crystalline silicon has been mentioned as the transistor material in this paragraph, other options are possible including, for example, poly-crystalline silicon, mono-crystalline germanium, mono-crystalline III-V semiconductors, graphene, and various other semiconductor materials with which devices, such as transistors, may be constructed within. Moreover, thermal contacts and vias need not be stacked in a vertical line through multiple stacks, layers, strata of circuits. Thermal contacts and vias may include materials such as sp2 carbon as conducting and sp3 carbon as non-conducting of electrical current. FIG.69describes an embodiment of the invention, where various implementations of thermal junctions and associated thermal contacts are illustrated. P-wells in CMOS integrated circuits are typically biased to ground and N-wells are typically biased to the supply voltage VDD. This makes the design of thermal contacts and thermal junctions non-obvious. A thermal contact16504between the power (VDD) distribution network and a P-well16502can be implemented as shown in N+ in P-well thermal junction and contact example16508, where an n+ doped region thermal junction16506may be formed in the P-well region at the base of the thermal contact16504. The n+ doped region thermal junction16506may ensure that a reverse biased p-n junction can be formed in N+ in P-well thermal junction and contact example16508and makes the thermal contact viable (i.e. not highly conductive) from an electrical perspective. The thermal contact16504could be formed of a conductive material such as copper, aluminum or some other material. A thermal contact16514between the ground (GND) distribution network and a P-well16512may be implemented as shown in P+ in P-well thermal junction and contact example16518, where a p+ doped region thermal junction16516may be formed in the P-well region at the base of the thermal contact16514. The p+ doped region thermal junction16516makes the thermal contact viable (i.e. not highly conductive) from an electrical perspective. The p+ doped region thermal junction16516and the P-well16512would typically be biased at ground potential. A thermal contact16524between the power (VDD) distribution network and an N-well16522can be implemented as shown in N+ in N-well thermal junction and contact example16528, where an n+ doped region thermal junction16526may be formed in the N-well region at the base of the thermal contact16524. The n+ doped region thermal junction16526makes the thermal contact viable (i.e. not highly conductive) from an electrical perspective. Both the n+ doped region thermal junction16526and the N-well16522would typically be biased at VDD potential. A thermal contact16534between the ground (GND) distribution network and an N-well16532can be implemented as shown in P+ in N-well thermal junction and contact example16538, where a p+ doped region thermal junction16536may be formed in the N-well region at the base of the thermal contact16534. The p+ doped region thermal junction16536makes the thermal contact viable (i.e. not highly conductive) from an electrical perspective due to the reverse biased p-n junction formed in P+ in N-well thermal junction and contact example16538. Note that the thermal contacts, a heat removal connection, may be designed to conduct negligible electricity, and the current flowing through them may be several orders of magnitude lower than the current flowing through a transistor when it is switching. Therefore, the thermal contacts, a heat removal connection, can be considered to be designed to conduct heat and conduct negligible (or no) electricity. Thermal contacts may include materials such as carbon nano-tubes. Thermal contacts and vias may include materials such as sp2 carbon as conducting and sp3 carbon as non-conducting of electrical current. Moreover, thermal contacts and vias need not be stacked in a vertical line through multiple stacks, layers, strata of circuits. FIG.70describes an embodiment of the invention, where an additional type of thermal contact structure is illustrated. The embodiment shown inFIG.70could also function as a decoupling capacitor to mitigate power supply noise. It could consist of a thermal contact16604, an electrode16610, a dielectric16606and P-well16602. The dielectric16606may be electrically insulating, and could be optimized to have high thermal conductivity. Dielectric16606could be formed of materials, such as, for example, hafnium oxide, silicon dioxide, other high k dielectrics, carbon, carbon based material, or various other dielectric materials with electrical conductivity below 1 nano-amp per square micron. A thermal connection may be defined as the combination of a thermal contact and a thermal junction. The thermal connections illustrated inFIG.69,FIG.70and other figures in this patent application may be designed into a chip to remove heat (conduct heat), and may be designed to not conduct electricity. Essentially, a semiconductor device comprising power distribution wires is described wherein some of said wires have a thermal connection designed to conduct heat to the semiconductor layer but the wires do not substantially conduct electricity through the thermal connection to the semiconductor layer. Thermal contacts similar to those illustrated inFIG.69andFIG.70can be used in the white spaces of a design, i.e. locations of a design where logic gates or other useful functionality are not present. These thermal contacts connect white-space silicon regions to power and/or ground distribution networks. Thermal resistance to the heat removal apparatus can be reduced with this approach. Connections between silicon regions and power/ground distribution networks can be used for various device layers in the 3D stack, and need not be restricted to the device layer closest to the heat removal apparatus. A Schottky contact or diode may also be utilized for a thermal contact and thermal junction. Thermal contacts and vias may include materials such as sp2 carbon as conducting and sp3 carbon as non-conducting of electrical current. Moreover, thermal contacts and vias need not be stacked in a vertical line through multiple stacks, layers, strata of circuits. FIG.71illustrates an embodiment of the invention wherein the layout of the 3D stackable 4 input NAND gate can be modified so that all parts of the gate are at desirable, such as sub-100° C., temperatures during chip operation. Inputs to the gate are denoted as A, B, C and D, and the output is denoted as OUT. Various sections of the 4 input NAND gate could include the metal 1 regions17306, gate regions17308, N-type silicon regions17310, P-type silicon regions17312, contact regions17314, and oxide isolation regions17316. An additional thermal contact17320(whose implementation can be similar to those described inFIG.69andFIG.70) can be added to the layout to keep the temperature of region17318under desirable limits (by reducing the thermal resistance from region17318to the GND distribution network). Several other techniques can also be used to make the layout shown inFIG.71more desirable from a thermal perspective. FIG.72illustrates an embodiment of the invention wherein the layout of the 3D stackable transmission gate can be modified so that substantially all parts of the gate are at desirable, such as sub-100° C., temperatures during chip operation. Inputs to the gate are denoted as A and A′. Various sections of the transmission gate could include metal 1 regions17506, gate regions17508, N-type silicon regions17510, P-type silicon regions17512, contact regions17514, and oxide isolation regions17516. Additional thermal contacts, such as, for example17520and17522(whose implementation can be similar to those described inFIG.69andFIG.70) can be added to the layout to keep the temperature of the transmission gate under desirable limits (by reducing the thermal resistance to the VDD and GND distribution networks). Several other techniques can also be used to make the layout shown inFIG.72more desirable from a thermal perspective. The thermal path techniques illustrated withFIG.71andFIG.72are not restricted to logic cells such as transmission gates and NAND gates, and can be applied to a number of cells such as, for example, SRAMs, CAMs, multiplexers and many others. Furthermore, the techniques illustrated withFIG.71andFIG.72can be applied and adapted to various techniques of constructing 3D integrated circuits and chips, including those described in pending US Patent Application 2011/0121366 and U.S. patent application Ser. No. 13/099,010, now U.S. Pat. Nos. 8,362,480 and 8,581,349. Furthermore, techniques illustrated withFIG.71andFIG.72(and other similar techniques) need not be applied to all such gates on the chip, but could be applied to a portion of gates of that type, such as, for example, gates with higher activity factor, lower threshold voltage, or higher drive current. Moreover, thermal contacts and vias need not be stacked in a vertical line through multiple stacks, layers, strata of circuits. When a chip is typically designed, a cell library consisting of various logic cells such as NAND gates, NOR gates and other gates may be created, and the chip design flow proceeds using this cell library. It will be clear to one skilled in the art that a cell library may be created wherein each cell's layout can be optimized from a thermal perspective and based on heat removal criteria such as maximum allowable transistor channel temperature (i.e. where each cell's layout can be optimized such that substantially all portions of the cell may have low thermal resistance to the VDD and GND contacts, and such, to the power bus and the ground bus.). While concepts in this patent application have been described with respect to 3D-ICs with two stacked device layers, those of ordinary skill in the art will appreciate that it can be valid for 3D-ICs with more than two stacked device layers. As layers may be stacked in a 3D IC, the power density per unit area typically increases. The thermal conductivity of mono-crystalline silicon is poor at 150 W/m-K and silicon dioxide, the most common electrical insulator in modern silicon integrated circuits, may have a very poor thermal conductivity at 1.4 W/m-K. If a heat sink is placed at the top of a 3D IC stack, then the bottom chip or layer (farthest from the heat sink) has the poorest thermal conductivity to that heat sink, since the heat from that bottom layer may travel through the silicon dioxide and silicon of the chip(s) or layer(s) above it. As illustrated inFIG.43, a heat spreader layer11205may be deposited on top of a thin silicon dioxide layer11203which may be deposited on the top surface of the interconnect metallization layers11201of substrate11202. Heat spreader layer11205may include Plasma Enhanced Chemical Vapor Deposited Diamond Like Carbon (PECVD DLC), which may have a thermal conductivity of about 1000 W/m-K, or another thermally conductive material, such as Chemical Vapor Deposited (CVD) graphene (about 5000 W/m-K) or copper (about 400 W/m-K). Heat spreader layer11205may be of thickness about 20 nm up to about 1 micron. The illustrated thickness range may be about 50 nm to 100 nm and the illustrated electrical conductivity of the heat spreader layer11205may be an insulator to enable minimum design rule diameters of the future through layer vias. If the heat spreader is electrically conducting, the TLV openings may need to be somewhat enlarged to allow for the deposition of a non-conducting coating layer on the TLV walls before the conducting core of the TLV is deposited. Alternatively, if the heat spreader layer11205is electrically conducting, it may be masked and etched to provide the landing pads for the through layer vias and a large grid around them for heat transfer, which could also be used as the ground plane or as power and ground straps for the circuits above and below it. Oxide layer11204may be deposited (and may be planarized to fill any gaps in the heat transfer layer) to prepare for wafer to wafer oxide bonding. Acceptor substrate11214may include substrate11202, interconnect metallization layers11201, thin silicon dioxide layer11203, heat spreader layer11205, and oxide layer11204. The donor substrate11206or wafer may be processed with wafer sized layers of doping as previously described, in preparation for forming transistors and circuitry (such as, for example, junction-less, RCAT, V-groove, and bipolar) after the layer transfer. A screen oxide layer11207may be grown or deposited prior to the implant or implants to protect the silicon from implant contamination, if implantation is utilized, and to provide an oxide surface for later wafer to wafer bonding. A layer transfer demarcation plane11299(shown as a dashed line) may be formed in donor substrate11206by hydrogen implantation, ‘ion-cut’ method, or other methods as previously described. Donor wafer11212may include donor substrate11206, layer transfer demarcation plane11299, screen oxide layer11207, and any other layers (not shown) in preparation for forming transistors as discussed previously. Both the donor wafer11212and acceptor substrate11214may be prepared for wafer bonding as previously described and then bonded at the surfaces of oxide layer11204and oxide layer11207, at a low temperature (less than about 400° C.). The portion of donor substrate11206that is above the layer transfer demarcation plane11299may be removed by cleaving and polishing, or other processes as previously described, such as ion-cut or other methods, thus forming the remaining transferred layers11206′. Alternatively, donor wafer11212may be constructed and then layer transferred, using methods described previously such as, for example, ion-cut with replacement gates (not shown), to the acceptor substrate11214. Now transistors or portions of transistors may be formed and aligned to the acceptor wafer alignment marks (not shown) and through layer vias formed as previously described. Thus, a 3D IC with an integrated heat spreader may be constructed. As illustrated inFIG.44A, a set of power and ground grids, such as bottom transistor layer power and ground grid11307and top transistor layer power and ground grid11306, may be connected by through layer power and ground vias11304and thermally coupled to the electrically non-conducting heat spreader layer11305. If the heat spreader is an electrical conductor, then it could either, for example, only be used as a ground plane, or a pattern should be created with power and ground strips in between the landing pads for the TLVs. The density of the power and ground grids and the through layer vias to the power and ground grids may be designed to substantially improve a certain overall thermal resistance for substantially all the circuits in the 3D IC stack. Bonding oxides11310, printed wiring board11300, package heat spreader11325, bottom transistor layer11302, top transistor layer11312, and heat sink11330are shown. Thus, a 3D IC with an integrated heat sink, heat spreaders, and through layer vias to the power and ground grid may be constructed. As illustrated inFIG.44B, thermally conducting material, such as PECVD DLC, may be formed on the sidewalls of the 3D IC structure ofFIG.44Ato form sidewall thermal conductors11360for sideways heat removal. Bottom transistor layer power and ground grid11307, top transistor layer power and ground grid11306, through layer power and ground vias11304, heat spreader layer11305, bonding oxides11310, printed wiring board11300, package heat spreader11325, bottom transistor layer11302, top transistor layer11312, and heat sink11330may be shown. FIG.54Aillustrates a packaging scheme used for several high-performance microchips. A silicon chip13802may be attached to an organic substrate13804using solder bumps13808. The organic substrate13804, in turn, may be connected to an FR4 printed wiring board (also called board)13806using solder bumps13812. The co-efficient of thermal expansion (CTE) of silicon may be about 3.2 ppm/K, the CTE of organic substrates is typically ˜17 ppm/K and the CTE of the FR4 printed wiring board material is typically ˜17 ppm/K. Due to this large mismatch between CTE of the silicon chip13802and the organic substrate13804, the solder bumps13808may be subjected to stresses, which can cause defects and cracking in solder bumps13808. To avoid this potential cause of defects and cracking, underfill material13810may be dispensed between solder bumps. While underfill material13810can prevent defects and cracking, it can cause other challenges. Firstly, when solder bump sizes are reduced or when high density of solder bumps is required, dispensing underfill material may become difficult or even impossible, since underfill cannot flow in small spaces. Secondly, underfill may be hard to remove once dispensed. As a result, if a chip on a substrate is found to have defects, removing the chip and replacing with another chip may be difficult. Hence, production of multi-chip substrates may be difficult. Thirdly, underfill can cause the stress, due to the mismatch of CTE between the silicon chip13802and the organic substrate13804, to be more efficiently communicated to the low k dielectric layers may present between on-chip interconnects. FIG.54Billustrates a packaging scheme used for many low-power microchips. A silicon chip13814may be directly connected to an FR4 substrate13816using solder bumps13818. Due to the large difference in CTE between the silicon chip13814and the FR4 substrate13816, underfill13820may be dispensed many times between solder bumps. As mentioned previously, underfill may bring with it challenges related to difficulty of removal and to the stress communicated to the chip low k dielectric layers. In both of the packaging types described inFIG.55AandFIG.55Band also many other packaging methods available in the literature, the mismatch of co-efficient of thermal expansion (CTE) between a silicon chip and a substrate, or between a silicon chip and a printed wiring board, may be a serious issue in the packaging industry. A technique to solve this problem without the use of underfill may be advantageous as an illustration. FIG.55A-Fdescribes an embodiment of this present invention, where use of underfill may be avoided in the packaging process of a chip constructed on a silicon-on-insulator (SOI) wafer. Although this embodiment of the present invention is described with respect to one type of packaging scheme, it will be clear to one skilled in the art that the invention may be applied to other types of packaging. The process flow for the SOI chip could include the following steps that occur in sequence from Step (A) to Step (F). When the same reference numbers are used in different drawing figures (amongFIG.55A-F), they are used to indicate analogous, similar or identical structures to enhance the understanding of the present invention by clarifying the relationships between the structures and embodiments presented in the various diagrams—particularly in relating analogous, similar or identical functionality to different physical structures.Step (A) is illustrated inFIG.55A. An SOI wafer with transistors constructed on silicon layer13906may have a buried oxide layer13904atop silicon layer/substrate13902. Interconnect layers13908, which may include metals such as aluminum or copper and insulators such as silicon oxide or low k dielectrics, may be constructed as well.Step (B) is illustrated inFIG.55B. A temporary carrier wafer13912can be attached to the structure shown inFIG.55Ausing a temporary bonding adhesive13910. The temporary carrier wafer13912may be constructed with a material, such as, for example, glass or silicon. The temporary bonding adhesive13910may include, for example, a polyimide.Step (C) is illustrated inFIG.55C. The structure shown inFIG.55Bmay be subjected to a selective etch process, such as, for example, a Potassium Hydroxide etch, (potentially combined with a back-grinding process) where silicon layer/substrate13902may be removed using the buried oxide layer13904as an etch stop. Once the buried oxide layer13904may be reached during the etch step, the etch process may be stopped. The etch chemistry may be selected such that it etches silicon but does not etch the buried oxide layer13904appreciably. The buried oxide layer13904may be polished with CMP to ensure a planar and smooth surface.Step (D) is illustrated inFIG.55D. The structure shown inFIG.55Cmay be bonded to an oxide-coated carrier wafer having a co-efficient of thermal expansion (CTE) similar to that of the organic substrate used for packaging. This oxide-coated carrier wafer as described may be called a CTE matched carrier wafer henceforth in this document. The bonding step may be conducted using oxide-to-oxide bonding of buried oxide layer13904to the oxide coating13916of the CTE matched carrier wafer13914. The CTE matched carrier wafer13914may include materials, such as, for example, copper, aluminum, organic materials, copper alloys and other materials.Step (E) is illustrated inFIG.55E. The temporary carrier wafer13912may be detached from the structure at the surface of the interconnect layers13908by removing the temporary bonding adhesive13910. This detachment may be done, for example, by shining laser light through the glass temporary carrier wafer13912to ablate or heat the temporary bonding adhesive13910.Step (F) is illustrated inFIG.55F. Solder bumps13918may be constructed for the structure shown inFIG.55E. After dicing, this structure may be attached to organic substrate13920. This organic substrate13920may then be attached to a printed wiring board13924, such as, for example, an FR4 substrate, using solder bumps13922. The conditions for choosing the CTE matched carrier wafer13914for this embodiment of the present invention include the following. Firstly, the CTE matched carrier wafer13914can have a CTE close to that of the organic substrate13920. For example, the CTE of the CTE matched carrier wafer13914should be within about 10 ppm/K of the CTE of the organic substrate13920. Secondly, the volume of the CTE matched carrier wafer13914can be much higher than the silicon layer13906. For example, the volume of the CTE matched carrier wafer13914may be greater than about 5 times the volume of the silicon layer13906. When this volume mismatch happens, the CTE of the combination of the silicon layer13906and the CTE matched carrier wafer13914may be close to that of the CTE matched carrier wafer13914. If these two conditions may be met, the issues of co-efficient of thermal expansion mismatch described previously may be ameliorated, and a reliable packaging process may be obtained without underfill being used. The organic substrate13920typically may have a CTE of about 17 ppm/K and the printed wiring board13924typically may be constructed of FR4 which has a CTE of about 18 ppm/K. If the CTE matched carrier wafer is constructed of an organic material having a CTE of about 17 ppm/K, it can be observed that issues of co-efficient of thermal expansion mismatch described previously are ameliorated, and a reliable packaging process may be obtained without underfill being used. If the CTE matched carrier wafer is constructed of a copper alloy having a CTE of about 17 ppm/K, it can be observed that issues of co-efficient of thermal expansion mismatch described previously may be ameliorated, and a reliable packaging process may be obtained without underfill being used. If the CTE matched carrier wafer may be constructed of an aluminum alloy material having a CTE of about 24 ppm/K, it can be observed that issues of co-efficient of thermal expansion mismatch described previously are ameliorated, and a reliable packaging process may be obtained without underfill being used. Silicon layer13906, buried oxide layer13904, interconnect layers13908may be regions atop silicon layer/substrate13902. FIG.56A-Fdescribes an embodiment of this present invention, where use of underfill may be avoided in the packaging process of a chip constructed on a bulk-silicon wafer. Although this embodiment of the present invention is described with respect to one type of packaging scheme, it will be clear to one skilled in the art that the invention may be applied to other types of packaging. The process flow for the silicon chip could include the following steps that occur in sequence from Step (A) to Step (F). When the same reference numbers may be used in different drawing figures (amongFIG.56A-F), they may be used to indicate analogous, similar or identical structures to enhance the understanding of the present invention by clarifying the relationships between the structures and embodiments presented in the various diagrams—particularly in relating analogous, similar or identical functionality to different physical structures.Step (A) is illustrated inFIG.56A. A bulk-silicon wafer with transistors constructed on silicon layer14006may have a buried p+ silicon layer14004atop silicon layer/substrate14002. Interconnect layers14008, which may include metals such as aluminum or copper and insulators such as silicon oxide or low k dielectrics, may be constructed. The buried p+ silicon layer14004may be constructed with a process, such as, for example, an ion-implantation and thermal anneal, or an epitaxial doped silicon deposition.Step (B) is illustrated inFIG.56B. A temporary carrier wafer14012may be attached to the structure shown inFIG.56Ausing a temporary bonding adhesive14010. The temporary carrier wafer14012may be constructed with a material, such as, for example, glass or silicon. The temporary bonding adhesive14010may include, for example, a polyimide.Step (C) is illustrated inFIG.56C. The structure shown inFIG.56Bmay be subjected to a selective etch process, such as, for example, ethylenediamine pyrocatechol (EDP) (potentially combined with a back-grinding process) where silicon layer/substrate14002may be removed using the buried p+ silicon layer14004as an etch stop. Once the buried p+ silicon layer14004may be reached during the etch step, the etch process may be stopped. The etch chemistry may be selected such that the etch process stops at the p+ silicon buried layer. The buried p+ silicon layer14004may then be polished away with CMP and planarized. Following this, an oxide layer14098may be deposited.Step (D) is illustrated inFIG.56D. The structure shown inFIG.56Cmay be bonded to an oxide-coated carrier wafer having a co-efficient of thermal expansion (CTE) similar to that of the organic substrate used for packaging. The oxide-coated carrier wafer as described may be called a CTE matched carrier wafer henceforth in this document. The bonding step may be conducted using oxide-to-oxide bonding of oxide layer14098to the oxide coating14016of the CTE matched carrier wafer14014. The CTE matched carrier wafer14014may include materials, such as, for example, copper, aluminum, organic materials, copper alloys and other materials.Step (E) is illustrated inFIG.56E. The temporary carrier wafer14012may be detached from the structure at the surface of the interconnect layers14008by removing the temporary bonding adhesive14010. This detachment may be done, for example, by shining laser light through the glass temporary carrier wafer14012to ablate or heat the temporary bonding adhesive14010.Step (F) is illustrated usingFIG.56F. Solder bumps14018may be constructed for the structure shown inFIG.56E. After dicing, this structure may be attached to organic substrate14020. This organic substrate may then be attached to a printed wiring board14024, such as, for example, an FR4 substrate, using solder bumps14022. There may be two illustrative conditions while choosing the CTE matched carrier wafer14014for this embodiment of the invention. Firstly, the CTE matched carrier wafer14014may have a CTE close to that of the organic substrate14020. Illustratively, the CTE of the CTE matched carrier wafer14014may be within about 10 ppm/K of the CTE of the organic substrate14020. Secondly, the volume of the CTE matched carrier wafer14014may be much higher than the silicon layer14006. Illustratively, the volume of the CTE matched carrier wafer14014may be, for example, greater than about 5 times the volume of the silicon layer14006. When this happens, the CTE of the combination of the silicon layer14006and the CTE matched carrier wafer14014may be close to that of the CTE matched carrier wafer14014. If these two conditions are met, the issues of co-efficient of thermal expansion mismatch described previously may be ameliorated, and a reliable packaging process may be obtained without underfill being used. Silicon layer14006, buried p+ silicon layer14004, and interconnect layers14008may also be regions that are atop silicon layer/substrate14002. The organic substrate14020typically has a CTE of about 17 ppm/K and the printed wiring board14024typically may be constructed of FR4 which has a CTE of about 18 ppm/K. If the CTE matched carrier wafer may be constructed of an organic material having a CTE of 17 ppm/K, it can be observed that issues of co-efficient of thermal expansion mismatch described previously are ameliorated, and a reliable packaging process may be obtained without underfill being used. If the CTE matched carrier wafer may be constructed of a copper alloy having a CTE of about 17 ppm/K, it can be observed that issues of co-efficient of thermal expansion mismatch described previously are ameliorated, and a reliable packaging process may be obtained without underfill being used. If the CTE matched carrier wafer may be constructed of an aluminum alloy material having a CTE of about 24 ppm/K, it can be observed that issues of co-efficient of thermal expansion mismatch described previously may be ameliorated, and a reliable packaging process may be obtained without underfill being used. WhileFIG.55A-FandFIG.56A-Fdescribe methods of obtaining thinned wafers using buried oxide and buried p+ silicon etch stop layers respectively, it will be clear to one skilled in the art that other methods of obtaining thinned wafers exist. Hydrogen may be implanted through the back-side of a bulk-silicon wafer (attached to a temporary carrier wafer) at a certain depth and the wafer may be cleaved using a mechanical force. Alternatively, a thermal or optical anneal may be used for the cleave process. An ion-cut process through the back side of a bulk-silicon wafer could therefore be used to thin a wafer accurately, following which a CTE matched carrier wafer may be bonded to the original wafer. It will be clear to one skilled in the art that other methods to thin a wafer and attach a CTE matched carrier wafer exist. Other methods to thin a wafer include, but not limited to, CMP, plasma etch, wet chemical etch, or a combination of these processes. These processes may be supplemented with various metrology schemes to monitor wafer thickness during thinning. Carefully timed thinning processes may also be used. FIG.57describes an embodiment of this present invention, where multiple dice, such as, for example, dice14124and14126may be placed and attached atop packaging substrate14116. Packaging substrate14116may include packaging substrate high density wiring layers14114, packaging substrate vias14120, packaging substrate-to-printed-wiring-board connections14118, and printed wiring board14122. Die-to-substrate connections14112may be utilized to electrically couple dice14124and14126to the packaging substrate high density wiring levels14114of packaging substrate14116. The dice14124and14126may be constructed using techniques described withFIG.55A-FandFIG.56A-Fbut may be attached to packaging substrate14116rather than organic substrate13920or14020. Due to the techniques of construction described inFIG.55A-FandFIG.56A-Fbeing used, a high density of connections may be obtained from each die, such as14124and14126, to the packaging substrate14116. By using a packaging substrate14116with packaging substrate high density wiring levels14114, a large density of connections between multiple dice14124and14126may be realized. This may open up several opportunities for system design. In one embodiment of this invention, unique circuit blocks may be placed on different dice assembled on the packaging substrate14116. In another embodiment, contents of a large die may be split among many smaller dice to reduce yield issues. In yet another embodiment, analog and digital blocks could be placed on separate dice. It will be obvious to one skilled in the art that several variations of these concepts are possible. The illustrative enabler for all these ideas may be the fact that the CTEs of the dice are similar to the CTE of the packaging substrate, so that a high density of connections from the die to the packaging substrate may be obtained, and provide for a high density of connection between dice.14102denotes a CTE matched carrier wafer,14104and14106are oxide layers,14108represents transistor regions,14110represents a multilevel wiring stack,14112represents die-to-substrate connections,14116represents the packaging substrate,14114represents the packaging substrate high density wiring levels,14120represents vias on the packaging substrate,14118denotes packaging substrate-to-printed-wiring-board connections and14122denotes a printed wiring board. As well, the independent formation of each transistor layer may enable the use of materials other than silicon to construct transistors. For example, a thin III-V compound quantum well channel such as InGaAs and InSb may be utilized on one or more of the 3D layers described above by direct layer transfer or deposition and the use of buffer compounds such as GaAs and InAlAs to buffer the silicon and III-V lattice mismatches. This feature may enable high mobility transistors that can be optimized independently for p and n-channel use, solving the integration difficulties of incorporating n and p III-V transistors on the same substrate, and also the difficulty of integrating the III-V transistors with conventional silicon transistors on the same substrate. For example, the first layer silicon transistors and metallization generally cannot be exposed to temperatures higher than about 400° C. The III-V compounds, buffer layers, and dopings generally may need processing temperatures above that 400° C. threshold. By use of the pre deposited, doped, and annealed layer donor wafer formation and subsequent donor to acceptor wafer transfer techniques described above and illustrated, for example, inFIG.14,FIG.8, andFIG.11, III-V transistors and circuits may be constructed on top of silicon transistors and circuits without damaging said underlying silicon transistors and circuits. As well, any stress mismatches between the dissimilar materials to be integrated, such as silicon and III-V compounds, may be mitigated by the oxide layers, or specialized buffer layers, that may be vertically in-between the dissimilar material layers. Additionally, this may now enable the integration of optoelectronic elements, communication, and data path processing with conventional silicon logic and memory transistors and silicon circuits. Another example of a material other than silicon that the independent formation of each transistor layer may enable is Germanium. It also should be noted that the 3D programmable system, where the logic fabric may be sized by dicing a wafer of tiled array as illustrated inFIG.12, could utilize the ‘monolithic’ 3D techniques related toFIG.14in respect to the ‘Foundation,’ or toFIGS.22and29in respect to the Attic, to add IO or memories as presented inFIG.11. So while in many cases constructing a 3D programmable system using TSV could be possible there might be cases where it will be better to use the ‘Foundation’ or ‘Attic”. When a substrate wafer, carrier wafer, or donor wafer may be thinned by a ion-cut & cleaving method in this document, there may be other methods that may be employed to thin the wafer. For example, a boron implant and anneal may be utilized to create a layer in the silicon substrate to be thinned that will provide a wet chemical etch stop plane. A dry etch, such as a halogen gas cluster beam, may be employed to thin a silicon substrate and then smooth the silicon surface with an oxygen gas cluster beam. Additionally, these thinning techniques may be utilized independently or in combination to achieve the proper thickness and defect free surface as may be needed by the process flow. FIG.96A-Fshows a procedure using etch-stop layer controlled etch-back for layer transfer. The process flow inFIG.96A-Fmay include several steps in the following sequence:Step (A): A silicon dioxide layer23204may be deposited above the generic bottom layer23202.FIG.96Aillustrates the structure after Step (A).Step (B): SOI wafer23206may be implanted with n+ near its surface to form an n+Si layer23208. The buried oxide (BOX) of the SOI wafer may be silicon dioxide layer23205.FIG.96Billustrates the structure after Step (B).Step (C): A p− Si layer23210may be epitaxially grown atop the n+Si layer23208. A silicon dioxide layer23212may be grown/deposited atop the p− Si layer23210. An anneal (such as a rapid thermal anneal RTA or spike anneal or laser anneal) may be conducted to activate dopants.FIG.96Cillustrates the structure after Step (C). Alternatively, the n+Si layer23208and p− Si layer23210can be formed by a buried layer implant of n+Si in a p− SOI wafer.Step (D): The top layer wafer shown after Step (C) may be flipped and bonded atop the bottom layer wafer using oxide-to-oxide bonding.FIG.96Dillustrates the structure after Step (D).Step (E): An etch process that etches Si but does not etch silicon dioxide may be utilized to etch through the p− Si layer of SOI wafer23206. The buried oxide (BOX) of silicon dioxide layer23205therefore acts as an etch stop.FIG.96Eillustrates the structure after Step (E).Step (F): Once the etch stop of silicon dioxide layer23205is substantially reached, an etch or CMP process may be utilized to etch the silicon dioxide layer23205till the n+ silicon layer23208may be reached. The etch process for Step (F) may be preferentially chosen so that it etches silicon dioxide but does not attack Silicon.FIG.96Fillustrates the structure after Step (F). At the end of the process shown inFIG.96A-F, the desired regions may be layer transferred atop the bottom layer23202. WhileFIG.96A-Fshows an etch-stop layer controlled etch-back using a silicon dioxide etch stop layer, other etch stop layers such as SiGe or p+Si can be utilized in alternative process flows. As well, n+Si layer23208and p− Si layer23210may be doped differently or may include other layers in combination with other embodiments herein. Alternatively, according to an embodiment of this present invention, surface non-planarities may be removed or reduced by treating the cleaved surface of the wafer or substrate in a hydrogen plasma at less than about 400° C. The hydrogen plasma source gases may include, for example, hydrogen, argon, nitrogen, hydrogen chloride, water vapor, methane, and so on. Hydrogen anneals at about 1100° C. are known to reduce surface roughness in silicon. By having a plasma, the temperature requirement can be reduced to less than about 400° C. A tool that might be employed is the TEL SPA tool. Alternatively, according to another embodiment of this present invention, a thin film, such as, for example, a Silicon oxide or photosensitive resist, may be deposited atop the cleaved surface of the wafer or substrate and etched back. The etchant that may be required for this etch-back process may have approximately equal etch rates for both silicon and the deposited thin film. This etchant could reduce non-planarities on the wafer surface. Alternatively, Gas Cluster Ion Beam technology may be utilized for smoothing surfaces after cleaving along an implanted plane of hydrogen or other atomic species. FIG.58A-Kdescribes an alternative embodiment of this invention, wherein a process flow is described in which a side gated monocrystalline Finfet may be formed with lithography steps shared among many wafers. The distinguishing characteristic of the Finfet is that the conducting channel is wrapped by a thin metal or semiconductor, such as silicon, “fin”, which may form the gate of the device. The thickness of the fin (measured in the direction from source to drain) determines the effective channel length of the device. Finfet may be used somewhat generically to describe any fin-based, multigate transistor architecture regardless of number of gates. The process flow for the silicon chip may include the following steps that may occur in sequence from Step (A) to Step (J). When the same reference numbers are used in different drawing figures, they are used to indicate analogous, similar or identical structures to enhance the understanding of the embodiments of the invention by clarifying the relationships between the structures and embodiments presented in the various diagrams—particularly in relating analogous, similar or identical functionality to different physical structures.Step (A) is illustrated inFIG.58A. An n− Silicon wafer/substrate14602may be taken.Step (B) is illustrated inFIG.58B. P type dopant, such as, for example, Boron ions, may be implanted into the n− Silicon wafer/substrate14604ofFIG.58B. A thermal anneal, such as, for example, rapid, furnace, spike, flash, or laser may then be done to activate dopants. Following this, a lithography and etch process may be conducted to define n− silicon region14604and p− silicon region14690. Regions with n− silicon, similar in structure and formation to p− silicon region14690, where p-Finfets may be fabricated, are not shown.Step (C) is illustrated inFIG.58C. Gate dielectric regions14610and gate electrode regions14608may be formed by oxidation or deposition of a gate dielectric, then deposition of a gate electrode, polishing with CMP, and then lithography and etch. The gate electrode regions14608may be, for example, doped polysilicon. Alternatively, various hi-k metal gate (HKMG) materials could be utilized for gate dielectric and gate electrode as described previously. N+ dopants, such as, for example, Arsenic, Antimony or Phosphorus, may then be implanted to form source and drain regions of the Finfet. The n+ doped source and drain regions may be indicated as14606.FIG.58Dshows a cross-section ofFIG.58Calong the AA′ direction. P− doped region14698can be observed, as well as n+ doped source and drain regions14606, gate dielectric regions14610, gate electrode regions14608, and n− silicon region14604.Step (D) is illustrated inFIG.58E. Oxide regions14612, for example, silicon dioxide, may be formed by deposition and may then be planarized and polished with CMP such that the oxide regions14612cover n+ silicon region14604, n+ doped source and drain regions14606, gate electrode regions14608, p− doped region14698, and gate dielectric regions14610.Step (E) is illustrated inFIG.58F. The structure shown inFIG.58Emay be further polished with CMP such that portions of oxide regions14612, gate electrode regions14608, gate dielectric regions14610, p− doped regions14698, and n+ doped source and drain regions14606are polished. Following this, a silicon dioxide layer may be deposited over the structure.Step (F) is illustrated inFIG.58G. Hydrogen H+ may be implanted into the structure at a certain depth creating hydrogen plane14614indicated by dotted lines.Step (G) is illustrated inFIG.58H. A silicon wafer14618may have an oxide layer14616, for example, silicon dioxide, deposited atop it.Step (H) is illustrated inFIG.58I. The structure shown inFIG.58Hmay be flipped and bonded atop the structure shown inFIG.58Gusing oxide-to-oxide bonding.Step (I) is illustrated inFIG.58JandFIG.58K. The structure shown inFIG.58Jmay be cleaved at hydrogen plane14614using a sideways mechanical force. Alternatively, a thermal anneal, such as, for example, furnace or spike, could be used for the cleave process. Following the cleave process, CMP processes may be done to planarize surfaces.FIG.58Jshows silicon wafer14618having an oxide layer14616and patterned features transferred atop it. These patterned features may include gate dielectric regions14624, gate electrode regions14622, n+ silicon region14620, p− silicon region14696and silicon dioxide regions14626. These patterned features may be used for further fabrication, with contacts, interconnect levels and other steps of the fabrication flow being completed.FIG.58Kshows the n+ silicon region14604on n− Silicon wafer/substrate (not shown) having patterned transistor layers. These patterned transistor layers may include gate dielectric regions14632, gate electrode regions14630, n+ silicon regions14628, p− silicon region14694, and silicon dioxide regions14634. The structure inFIG.58Kmay be used for transferring patterned layers to other substrates similar to the one shown inFIG.58Husing processes similar to those described inFIG.58G-K. For example, a set of patterned features created with lithography steps once (such as the one shown inFIG.58F) may be layer transferred to many wafers, thereby removing the requirement for separate lithography steps for each wafer. Lithography cost can be reduced significantly using this approach. Implanting hydrogen through the gate dielectric regions14610inFIG.58Gmay not degrade the dielectric quality, since the area exposed to implant species may be small (a gate dielectric is typically about 2 nm thick, and the channel length is typically leass than about 20 nm, so the exposed area to the implant species is about 40 sq. inn). Additionally, a thermal anneal or oxidation after the cleave may repair the potential implant damage. Also, a post-cleave CMP polish to remove the hydrogen rich plane within the gate dielectric may be performed. An alternative embodiment of the invention may involve forming a dummy gate transistor structure, as previously described for the replacement gate process, for the structure shown inFIG.58J. Post cleave, the gate electrode regions14622and the gate dielectric regions14624materials may be etched away and then the trench may be filled with a replacement gate dielectric and a replacement gate electrode. In an alternative embodiment of the invention described inFIG.58B-K, the substrate silicon wafer14618inFIG.58B-Kmay be a wafer with one or more pre-fabricated transistor and interconnect layers. Low temperature (less than about 400° C.) bonding and cleave techniques as previously described may be employed. In that scenario, 3D stacked logic chips may be formed with fewer lithography steps. Alignment schemes similar to those described previously may be used. In general logic devices may include varying quantities of logic elements, varying amounts of memories, and varying amounts of I/O. The continuous array of the prior art may allow defining various die sizes out of the same wafers and accordingly varying amounts of logic, but it may be far more difficult to vary the three-way ratio between logic, I/O, and memory. In addition, there may exist different types of memories such as SRAM, DRAM, Flash, and others, and there may exist different types of JI/such as SerDes. Some applications might need still other functions such as processor, DSP, analog functions, and others. Some embodiments of the invention may enable a different approach. Instead of trying to put substantially all of these different functions onto one programmable die, which may need a large number of very expensive mask sets, it may use Through-Silicon Via to construct configurable systems. The technology of “Package of integrated circuits and vertical integration” has been described in U.S. Pat. No. 6,322,903 issued to Oleg Siniaguine and Sergey Savastiouk on Nov. 27, 2001. Accordingly some embodiments of the invention may suggest the use of a continuous array of tiles focusing each one on a single, or very few types of, function. The target system may then be constructed using desired number of tiles of desired type stacked on top of each other and electrically connected with TSVs or monolithic 3D approaches, thus, a 3D Configurable System may result. FIG.2Ais a drawing illustration of one reticle site on a wafer comprising tiles of programmable logic1101denoted FPGA. Such wafer may be a continuous array of programmable logic.1102are potential dicing lines to support various die sizes and the amount of logic to be constructed from one mask set. This die could be used as a base1202A,1202B,1202C or1202D of the 3D system as inFIG.3. In one embodiment of this invention these dies may carry mostly logic, and the desired memory and I/O may be provided on other dies, which may be connected by means of Through-Silicon Via. It should be noted that in some cases it may be desired not to have metal lines, even if unused, in the dicing streets1102. In such case, at least for the logic dies, one may use dedicated masks to allow connection over the unused potential dicing lines to connect the individual tiles according to the desired die size. The actual dicing lines may also be called streets. It should be noted that in general the lithography projected over surface of the wafer may be done by repeatedly projecting a reticle image over the wafer in a “step-and-repeat” manner. In some cases it might be possible to consider differently the separation between repeating tile1101within a reticle image vs. tiles that relate to two projections. For simplicity this description will use the term wafer but in some cases it will apply, for example, only to tiles with one reticle. The repeating tile1101could be of various sizes. For FPGA applications it may be reasonable to assume tile1101to have an edge size between about 0.5 mm to about 1 mm which may allow good balance between the end-device size and acceptable relative area loss due to the unused potential dice lines1102. Potential dice lines may be area regions of the processed wafer where the layers and structures on the wafer may be arranged such that the wafer dicing process may optimally proceed. For example, the potential dice lines may be line segments that surround a desired potential product die wherein the majority of the potential dice line may have no structures and may have a die seal edge structure to protect the desired product die from damages as a result of the dicing process. The dicing process can be accomplished by scribing and breaking, by mechanical sawing (normally with a machine called a dicing saw) or by laser cutting. There may be many illustrative advantages for a uniform repeating tile structure ofFIG.2Awhere a programmable device could be constructed by dicing the wafer to the desired size of programmable device. Yet it may be still helpful that the end-device may act as a complete integrated device rather than just as a collection of individual tiles1101.FIG.12illustrates a wafer3600carrying an array of tile3601with potential dice lines3602to be diced along actual dice lines3612to construct an end-device3611of 3×3 tiles. The end-device3611may be bounded by the actual dice lines3612. FIG.13is a drawing illustration of an end-device3611comprising 9 tiles3701[(0,0) to (2,2)] such as tile3601. Each tile3701may contain a tiny micro control unit—MCU3702. The micro control unit could have a common architecture such as an8051with its own program memory and data memory. The MCUs in each tile may be used to load the FPGA tile3701with its programmed function and substantially all its initialization for proper operation of the device. The MCU of each tile may be connected (for example, MCU-MCU connections3714,3706, &3704) with a fixed electrical connection so to be controlled by the tile west of it or the tile south of it, in that order of priority. So, for example, the MCU3702-11may be controlled by MCU3702-01. The MCU3702-01may have no MCU west of it so it may be controlled by the MCU south of it, MCU3702-00, through connection3714. Accordingly the MCU3702-00which may be in south-west corner may have no tile MCU to control it through connection3706or connection3704and it may therefore be the master control unit of the end-device. FIG.14illustrates a simple control connectivity utilizing a slightly modified Joint Test Action Group (JTAG)-based MCU architecture to support such a tiling approach. These MCU connections may be made with a fixed electrical connection, such as, for example, a metallized via, during the manufacturing process. Each MCU may have two Time-Delay-Integration (TDI) inputs, TDI3816from the device on its west side and TDIb3814from the MCU on its south side. As long as the input from its west side TDI3816is active it may be the controlling input, otherwise the TDIb3814from the south side may be the controlling input. Again in this illustration the MCU at the south-west corner tile3800may take control as the master. Its control inputs3802may be used to control the end-device and through this MCU at the south-west corner tile3800it may spread to substantially all other tiles. In the structure illustrated inFIG.14the outputs of the end-device3611may be collected from the MCU of the tile at the north-east corner3820at the TDO output3822. These MCUs and their connectivity would be used to load the end-device functions, initialize the end-device, test the end-device, debug the end-device, program the end-device clocks, and provide substantially all other desired control functions. Once the end-device has completed its set up or other control and initialization functions such as testing or debugging, these MCUs could be then utilized for user functions as part of the end-device operation and may be connected electrically or configured with programmable connections. An additional advantage for this construction of a tiled FPGA array with MCUs may be in the construction of an SoC with embedded FPGA function. A single tile3601could be connected to an SoC using Through Silcon Vias (TSVs) and accordingly may provide a self-contained embedded FPGA function. Clearly, the same scheme can be modified to use the East/North (or any other combination of orthogonal directions) to encode effectively an identical priority scheme. FIG.2Bis a drawing illustration of an alternative reticle site on a wafer comprising tiles of Structured ASIC1100B. Such wafer may be, for example, a continuous array of configurable logic.1102are potential dicing lines to support various die sizes and the amount of logic to be constructed. This die could be used as a base1202A,1202B,1202C or1202D of the 3D system as inFIG.3. FIG.2Cis a drawing illustration of another reticle site on a wafer comprising tiles of RAM1100C. Such wafer may be a continuous array of memories. The die diced out of such wafer may be a memory die component of the 3D integrated system. It might include, for example, an antifuse layer or other form of configuration technique to function as a configurable memory die. Yet it might be constructed as a multiplicity of memories connected by a multiplicity of Through Silicon Vias to the configurable die, which may also be used to configure the raw memories of the memory die to the desired function in the configurable system. FIG.2Dis a drawing illustration of another reticle site on a wafer including tiles of DRAM1100D. Such wafer may be a continuous array of DRAM memories. FIG.2Eis a drawing illustration of another reticle site on a wafer comprising tiles of microprocessor or microcontroller cores1100E. Such wafer may be a continuous array of Processors. FIG.2Fis a drawing illustration of another reticle site on a wafer including tiles of I/Os1100F. This could include groups of SerDes. Such a wafer may be a continuous tile of I/Os. The die diced out of such wafer may be an I/O die component of a 3D integrated system. It could include an antifuse layer or other form of configuration technique such as SRAM to configure these I/Os of the configurable I/O die to their function in the configurable system. Yet it might be constructed as a multiplicity of I/O connected by a multiplicity of Through Silicon Vias to the configurable die, which may also be used to configure the raw I/Os of the I/O die to the desired function in the configurable system. I/O circuits may be a good example of where it could be illustratively advantageous to utilize an older generation process. Usually, the process drivers may be SRAM and logic circuits. It often may take longer to develop the analog function associated with I/O circuits, SerDes circuits, PLLs, and other linear functions. Additionally, while there may be an advantage to using smaller transistors for the logic functionality, I/Os may need stronger drive and relatively larger transistors and may enable higher operating voltages. Accordingly, using an older process may be more cost effective, as the older process wafer might cost less while still performing effectively. An additional function that it might be advantageous to pull out of the programmable logic die and onto one of the other dies in the 3D system, connected by Through-Silicon-Vias, may be the Clock circuits and their associated PLL, DLL, and control clock circuits and distribution. These circuits may often be area consuming and may also be challenging in view of noise generation. They also could in many cases be more effectively implemented using an older process. The Clock tree and distribution circuits could be included in the I/O die. Additionally the clock signal could be transferred to the programmable die using the Through-Silicon-Vias (TSVs) or by optical means. A technique to transfer data between dies by optical means was presented for example in U.S. Pat. No. 6,052,498 assigned to Intel Corp. Alternatively an optical clock distribution could be used. There may be new techniques to build optical guides on silicon or other substrates. An optical clock distribution may be utilized to minimize the power used for clock signal distribution and may enable low skew and low noise for the rest of the digital system. Having the optical clock constructed on a different die and then connected to the digital die by means of Through-Silicon-Vias or by optical means, make it very practical, when compared to the prior art of integrating optical clock distribution with logic on the same die. Alternatively the optical clock distribution guides and potentially some of the support electronics such as the conversion of the optical signal to electronic signal could be integrated by using layer transfer and smart cut approaches as been described before inFIGS.4and8. The optical clock distribution guides and potentially some of the support electronics could be first built on the ‘Foundation’ wafer1402and then a thin layer transferred silicon layer1404may be transferred on top of it using the ion-cut flow, so substantially all the following construction of the primary circuit would take place afterward. The optical guide and its support electronics would be able to withstand the high temperatures necessary for the processing of transistors on transferred silicon layer1404. And as related toFIG.8, the optical guide, and the proper semiconductor structures on which at a later stage the support electronics would be processed, could be pre-built on semiconductor layer2019. Using, for example, the ion-cut flow semiconductor layer2019may be then transferred on top of a fully processed wafer808. The optical guide may be able to withstand the ion implant for the ion-cut to form the ion-cut layer/plane2008while the support electronics may be finalized in flows similar to the ones presented in, for example,FIGS.9-11, and15to35. Thus, the landing target for the clock signal may need to accommodate the about 1 micron misalignment of the transferred layer2004to the prefabricated primary circuit and its upper layer808. Such misalignment could be acceptable for many designs. Alternatively, for example, only the base structure for the support electronics may be pre-fabricated on semiconductor layer2019and the optical guide may be constructed after the layer transfer along with finalized flows of the support electronics using flows similar to the ones presented in, for example,FIGS.9-11, and15to35. Alternatively, the support electronics could be fabricated on top of a fully processed wafer808by using flows similar to the ones presented in, for example,FIGS.9-11, and15to35. Then an additional layer transfer on top of the support electronics may be utilized to construct the optical wave guides at low temperature. Having wafers dedicated to each of these functions may support high volume generic product manufacturing. Then, similar to Lego® blocks, many different configurable systems could be constructed with various amounts of logic memory and I/O. In addition to the alternatives presented inFIG.2AthroughFIG.2Fthere many other useful functions that could be built and that could be incorporated into the 3D Configurable System. Examples of such may be image sensors, analog, data acquisition functions, photovoltaic devices, non-volatile memory, and so forth. An additional function that would fit well for 3D systems using TSVs, as described, may be a power control function. In many cases it may be desired to shut down power at times to a portion of the IC that is not currently operational. Using controlled power distribution by an external die connected by TSVs may be illustratively advantageous as the power supply voltage to this external die could be higher because it may be using an older process. Having a higher supply voltage allows easier and better control of power distribution to the controlled die. Those components of configurable systems could be built by one vendor, or by multiple vendors, who may agree on a standard physical interface to allow mix-and-match of various dies from various vendors. The construction of the 3D Programmable System could be done for the general market use or custom-tailored for a specific customer. Another illustrative advantage of some embodiments of this invention may be an ability to mix and match various processes. It might be illustratively advantageous to use memory from a leading edge process, while the I/O, and maybe an analog function die, could be used from an older process of mature technology (e.g., as discussed above). FIG.3AthroughFIG.3Eillustrates integrated circuit systems. An integrated circuit system that may include configurable die could be called a Configurable System.FIG.3AthroughFIG.3Eare drawings illustrating integrated circuit systems or Configurable Systems with various options of die sizes within the 3D system and alignments of the various dies.FIG.3Epresents a 3D structure with some lateral options. In such case a few dies1204E,1206E,1208E may be placed on the same underlying die1202E allowing relatively smaller die to be placed on the same mother die. For example die1204E could be a SerDes die while die1206E could be an analog data acquisition die. It could be advantageous to fabricate these die on different wafers using different process and then integrate them into one system. When the dies are relatively small then it might be useful to place them side by side (such asFIG.3E) instead of one on top of the other (FIG.3A-3D). The Through Silicon Via technology is constantly evolving. In the early generations such via would be 10 microns in diameter. Advanced work now demonstrating Through Silicon Via with less than a about 1-micron diameter. Yet, the density of connections horizontally within the die may typically still be far denser than the vertical connection using Through Silicon Via. In another alternative of the present invention the logic portion could be broken up into multiple dies, which may be of the same size, to be integrated to a 3D configurable system. Similarly it could be advantageous to divide the memory into multiple dies, and so forth, with other functions. Recent work on 3D integration may show effective ways to bond wafers together and then dice those bonded wafers. This kind of assembly may lead to die structures such as shown inFIG.3AorFIG.3D. Alternatively for some 3D assembly techniques it may be better to have dies of different sizes. Furthermore, breaking the logic function into multiple vertically integrated dies may be used to reduce the average length of some of the heavily loaded wires such as clock signals and data buses, which may, in turn, improve performance. An additional variation of the present invention may be the adaptation of the continuous array (presented in relation to at leastFIG.2A-2F) to the general logic device and even more so for the 3D IC system. Lithography limitations may pose considerable concern to advanced device design. Accordingly regular structures may be highly desirable and layers may be constructed in a mostly regular fashion and in most cases with one orientation at a time. Additionally, highly vertically-connected 3D IC system could be most efficiently constructed by separating logic memories and I/O into dedicated layers.FIG.30Aillustrates a repeating pattern of the logic cells. In such a case, the repeating logic pattern8402could be made full reticle size.FIG.30Billustrates the same repeating logic pattern8402, repeating the device, array, cells, etc. many more times to substantially fully fill a reticle. The multiple masks used to construct the logic terrain could be used for multiple logic layers within one 3D IC and for multiple ICs. Such a repeating structure may include the logic P and N transistors, their corresponding contact layers, and even the landing strips for connecting to the underlying layers. The interconnect layers on top of these logic terrain could be made custom per design or partially custom depending on the design methodology used. The custom metal interconnect may leave the logic terrain unused in the dicing streets area. Alternatively a dicing-streets mask could be used to etch away the unused transistors in the streets area8404as illustrated inFIG.30C. The continuous logic terrain could use any transistor style including the various transistors previously presented. An additional advantage to some of the 3D layer transfer techniques previously presented may be the option to pre-build, in high volume, transistor terrains for further reduction of 3D custom IC manufacturing costs. Similarly a memory terrain could be constructed as a continuous repeating memory structure with a fully populated reticle. The non-repeating elements of most memories may be the address decoder and sometimes the sense circuits. Those non repeating elements may be constructed using the logic transistors of the underlying or overlying layer. FIG.30D-Gare drawing illustrations of an SRAM memory terrain.FIG.30Dillustrates a conventional 6 transistor SRAM bit cell8420controlled by Word Line (WL)8422and Bit Lines (BL, BLB)8424,8426. The SRAM bit cell may be specially designed to be very compact. The generic continuous array8430may be a reticle step field sized terrain of SRAM bit cells8420wherein the transistor layers and even the Metal 1 layer may be used by substantially all designs.FIG.30Eillustrates such continuous array8430wherein a 4×4 memory block8432may be defined by custom etching the cells around it8434. The memory may be customized by custom metal masks such metal 2 and metal 3. To control the memory block the Word Lines8438and the Bit Lines8436may be connected by through layer vias to the logic terrain underneath or above it. FIG.30Fillustrates a logic structure8450that may be constructed on the logic terrain to drive the Word Lines8452.FIG.30Gillustrates the logic structure8460that may be constructed on the logic terrain to drive the Bit Lines8462.FIG.30Galso illustrates the read sense circuit8468that may read the memory content from the bit lines8462. In a similar fashion, other memory structures may be constructed from the uncommitted memory terrain using the uncommitted logic terrain close to the intended memory structure. In a similar fashion, other types of memory, such as flash or DRAM, may include the memory terrain. Furthermore, the memory terrain may be etched away at the edge of the projected die borders to define dicing streets similar to that indicated inFIG.30Cfor a logic terrain. As illustrated inFIG.73A, the custom dicing line masking and etch referred to in theFIG.30Cdiscussion to create multiple thin strips of streets area8404for etching may be shaped to created chamfered block corners18302of custom blocks18304to relieve stress. Custom blocks18304may include functions, blocks, arrays, or devices of architectures such as logic, FPGA, I/O, or memory. As illustrated inFIG.73B, this custom function etching and chamfering may extend through the BEOL metallization of one device layer of the 3DIC stack as shown in first structure18350, or extend through the entire 3DIC stack to the bottom substrate and shown in second structure18370, or may truncate at the isolation of any device layer in the 3D stack as shown in third structure18360. The cross sectional view of an exemplary 3DIC stack may include second layer BEOL dielectric18326, second layer interconnect metallization18324, second layer transistor layer18322, substrate layer BEOL dielectric18316, substrate layer interconnect metallization18314, substrate transistor layer18312, and substrate18310. Passivation of the edge created by the custom function etching may be accomplished as follows. If the custom function etched edge is formed on a layer or strata that is not the topmost one, then it may be passivated or sealed by filling the etched out area with dielectric, such as a Spin-On-Glass (SOG) method, and CMPing flat to continue to the next 3DIC layer transfer. As illustrated inFIG.73C, the topmost layer custom function etched edge may be passivated with an overlapping layer or layers of material including, for example, oxide, nitride, or polyimide. Oxide may be deposited over custom function etched block edge18380and may be lithographically defined and etched to overlap the custom function etched block edge18380shown as oxide structure18384. Silicon nitride may be deposited over wafer and oxide structure18384, and may be lithographically defined and etched to overlap the custom function etched block edge18380and oxide structure18384, shown as nitride structure18386. In such way a single expensive mask set can be used to build many wafers for different memory sizes and finished through another mask set that is used to build many logic wafers that can be customized by few metal layers. Person skilled in the art will recognize that it is now possible to assemble a true monolithic 3D stack of mono-crystalline silicon layers or strata with high performance devices using advanced lithography that repeatedly reuse same masks, with only few custom metal masks for each device layer. Such person will also appreciate that one can stack in the same way a mix of disparate layers, some carrying transistor array for general logic and other carrying larger scale blocks such as memories, analog elements, Field Programmable Gate Array (FPGA), and I/O. Moreover, such a person would also appreciate that the custom function formation by etching may be accomplished with masking and etching processes such as, for example, a hard-mask and Reactive Ion Etching (RIE), or wet chemical etching, or plasma etching. Furthermore, the passivation or sealing of the custom function etching edge may be stair stepped so to enable improved sidewall coverage of the overlapping layers of passivation material to seal the edge Constructing 3D ICs utilizing multiple layers of different function may combine 3D layers using the layer transfer techniques according to some embodiments of the invention, with substantially fully prefabricated devices connected by industry standard TSV techniques. Yield repair for random logic may be an embodiment of the invention. The 3D IC techniques presented may allow the construction of a very complex logic 3D IC by using multiple layers of logic. In such a complex 3D IC, enabling the repair of random defects common in IC manufacturing may be highly desirable. Repair of repeating structures is known and commonly used in memories and will be presented in respect toFIG.16. Another alternative may be a repair for random logic leveraging the attributes of the presented 3D IC techniques and Direct Write eBeam technology such as, for example, technologies offered by Advantest, Fujitsu Microelectronics and Vistec. FIG.31Aillustrates an exemplary 3D logic IC structured for repair. The illustrated 3D logic IC may include three logic layers8602,8612,8622and an upper layer of repair logic8632. In each logic layer substantially all primary outputs, the Flip Flop (FF) outputs, may be fed to the upper layer of repair logic8632, the repair layer. The upper layer of repair logic8632initially may include a repeating structure of uncommitted logic transistors similar to those ofFIGS.76and78. The circuitry of logic layer8602may be constructed on SOI wafers so that the performance of logic layer8602may more closely match logic layers8612,8622and layer of repair logic8632. At the fabrication, the 3D IC wafer may go through a full scan test. If a fault is detected, a yield repair process may be applied. Using the design data base, repair logic may be built on the upper layer of repair logic8632. The repair logic may have access to substantially all the primary outputs as they are all available on the top layer. Accordingly, those outputs needed for the repair may be used in the reconstruction of the exact logic found to be faulty. The reconstructed logic may include some enhancement such as drive size or metal wires strength to compensate for the longer lines going up and then down. The repair logic, as a de-facto replacement of the faulty logic ‘cone,’ may be built using the uncommitted transistors on the top layer. The top layer may be customized with a custom metal layer defined for each die on the wafer by utilizing the direct write eBeam. The repair flow may also be used for performance enhancement. If the wafer test includes timing measurements, a slow performing logic ‘cone’ could be replaced in a similar manner to a faulty logic ‘cone’ described previously, e.g., in the preceding paragraph. FIG.31Bis a drawing illustration of a 3D IC wherein the scan chains are designed so each is confined to one layer. This confinement may allow testing of each layer as it is fabricated and could be useful in many ways. For example, after a circuit layer is completed and then tested showing very bad yield, then the wafer could be removed and not continued for building additional 3D circuit layers on top of bad base. Alternatively, a design may be constructed to be very modular and therefore the next transferred circuit layer could include replacement modules for the underlying faulty base layer similar to what was suggested in respect toFIG.16. The elements of the present invention related toFIGS.31A and31Bmay need testing of the wafer during the fabrication phase, which might be of concern in respect to debris associated with making physical contact with a wafer for testing if the wafer may be probed when tested.FIG.31Cis a drawing illustration of an embodiment which may provide for contact-less automated self-testing. A contact-less power harvesting element might be used to harvest the electromagnetic energy directed at the circuit of interest by a coil base antenna86C02, an RF to DC conversion circuit86C04, and a power supply unit86C06to generate the necessary supply voltages to run the self-test circuits and the various 3D IC circuits86C08to be tested. Alternatively, a tiny photo voltaic cell86C10could be used to convert light beam energy to electric current which may be converted by the power supply unit86C06to the needed voltages. Once the circuits are powered, a Micro Control Unit86C12could perform a full scan test of all existing 3D IC circuits86C08. The self-test could be full scan or other BIST (Built In Self-Test) alternatives. The test result could be transmitted using wireless radio module86C14to abase unit outside of the 3D IC wafer. Such contact less wafer testing could be used for the test as was referenced in respect toFIG.31AandFIG.31Bor for other application such as wafer to wafer or die to wafer integration using TSVs. Alternative uses of contact-less testing could be applied to various combinations of the present invention. One example is where a carrier wafer method may be used to create a wafer transfer layer whereby transistors and the metal layers connecting them to form functional electronic circuits are constructed. Those functional circuits could be contactlessly tested to validate proper yield, and, if appropriate, actions to repair or activate built-in redundancy may be done. Then using layer transfer, the tested functional circuit layer may be transferred on top of another processed wafer808, and may then be connected by utilizing one of the approaches presented before. An additional advantage of this yield repair design methodology may be the ability to reuse logic layers from one design to another design. For example, a 3D IC system may be designed wherein one of the layers may comprise a WiFi transceiver receiver. And such circuit may now be needed for a completely different 3D IC. It might be advantageous to reuse the same WiFi transceiver receiver in the new design by just having the receiver as one of the new 3D IC design layers to save the redesign effort and the associated NRE (non-recurring expense) for masks and etc. The reuse could be applied to many other functions, allowing the 3D IC to resemble an old way of integrating functions—the PC (printed circuit) Board. For such a concept to work well, a connectivity standard for the connection of wires up and down may be desirable. Another application of these concepts could be the use of the upper layer to modify the clock timing by adjusting the clock of the actual device and its various fabricated elements. Scan circuits could be used to measure the clock skew and report it to an external design tool. The external design tool could construct the timing modification that would be applied by the clock modification circuits. A direct write ebeam could then be used to form the transistors and circuitry on the top layer to apply those clock modifications for a better yield and performance of the 3D IC end product. An alternative approach to increase yield of complex systems through use of 3D structure is to duplicate the same design on two layers vertically stacked on top of each other and use BIST techniques similar to those described in the previous sections to identify and replace malfunctioning logic cones. This approach may prove particularly effective repairing very large ICs with very low yields at the manufacturing stage using one-time, or hard to reverse, repair structures such as, for example, antifuses or Direct-Write e-Beam customization. Triple Modular Redundancy (TMR) at the logic cone level can also function as an effective field repair method, though it may really create a high level of redundancy that can mask rather than repair errors due to delayed failure mechanisms or marginally slow logic cones. If factory repair is used to make sure all the equivalent logic cones on each layer test functional before the 3D IC is shipped from the factory, the level of redundancy may be even higher. The cost of having three layers versus having two layers, with or without a repair layer may be factored into determining an embodiment for any application. An alternative TMR approach may be shown in exemplary 3D IC12700inFIG.45.FIG.45illustrates substantially identical Layers labeled Layer 1, Layer 2 and Layer 3 separated by dashed lines in the figure. Layer 1, Layer 2 and Layer 3 may each include one or more circuit layers and are bonded together to form 3D IC12700using techniques known in the art. Layer 1 may include Layer 1 Logic Cone12710, flip-flop12714, and majority-of-three (MAJ3) gate12716. Layer 2 may include Layer 2 Logic Cone12720, flip-flop12724, and MAJ3 gate12726. Layer 3 may include Layer 3 Logic Cone12730, flip-flop12734, and MAJ3 gate12736. The logic cones12710,12720and12730all may perform a substantially identical logic function. The flip-flops12714,12724and12734may be illustratively scan flip-flops. If a Repair Layer is present (not shown inFIG.45), then the flip-flop8702ofFIG.32may be used to implement repair of a defective logic cone before 3D IC12700may be shipped from the factory. The MAJ3 gates12716,12726and12736may compare the outputs from the three flip-flops12714,12724and12734and output a logic value consistent with the majority of the inputs: specifically if two or three of the three inputs equal logic-0, then the MAJ3 gate may output logic-0; and if two or three of the three inputs equal logic-1, then the MAJ3 gate may output logic-1. Thus if one of the three logic cones or one of the three flip-flops is defective, the correct logic value may be present at the output of all three MAJ3 gates. One illustrative advantage of the embodiment ofFIG.45may be that Layer 1, Layer 2 or Layer 3 can all be fabricated using all or nearly all of the same masks. Another illustrative advantage may be that MAJ3 gates12716,12726and12736can also effectively function as a Single Event Upset (SEU) filter for high reliability or radiation tolerant applications as described in Rezgui cited above. Another TMR approach is shown in exemplary 3D IC12800inFIG.46. In this embodiment, the MAJ3 gates may be placed between the logic cones and their respective flip-flops. Present inFIG.46are substantially identical Layers labeled Layer 1, Layer 2 and Layer 3 separated by dashed lines in the figure. Layer 1, Layer 2 and Layer 3 may each include one or more circuit layers and may be bonded together to form 3D IC12800using techniques known in the art. Layer 1 may include Layer 1 Logic Cone12810, flip-flop12814, and majority-of-three (MAJ3) gate12812. Layer 2 may include Layer 2 Logic Cone12820, flip-flop12824, and MAJ3 gate12822. Layer 3 may include Layer 3 Logic Cone12830, flip-flop12834, and MAJ3 gate12832. The logic cones12810,12820and12830all may perform a substantially identical logic function. The flip-flops12814,12824and12834may be illustratively scan flip-flops. If a Repair Layer is present (not shown inFIG.46), then the flip-flop8702ofFIG.32may be used to implement repair of a defective logic cone before 3D IC12800is shipped from the factory. The MAJ3 gates12812,12822and12832may compare the outputs from the three logic cones12810,12820and12830and may output a logic value which may be consistent with the majority of the inputs. Thus if one of the three logic cones is defective, the correct logic value may be present at the output of all three MAJ3 gates. One illustrative advantage of the embodiment ofFIG.46is that Layer 1, Layer 2 or Layer 3 can all be fabricated using all or nearly all of the same masks. Another illustrative advantage may be that MAJ3 gates12716,12726and12736can also effectively function as a Single Event Transient (SET) filter for high reliability or radiation tolerant applications as described in Rezgui cited above. Another TMR embodiment is shown in exemplary 3D IC12900inFIG.47. In this embodiment, the MAJ3 gates may be placed between the logic cones and their respective flip-flops.FIG.47illustrates substantially identical Layers labeled Layer 1, Layer 2 and Layer 3 separated by dashed lines in the figure. Layer 1, Layer 2 and Layer 3 may each include one or more circuit layers and may be bonded together to form 3D IC12900using techniques known in the art. Layer 1 may include Layer 1 Logic Cone12910, flip-flop12914, and majority-of-three (MAJ3) gates12912and12916. Layer 2 may include Layer 2 Logic Cone12920, flip-flop12924, and MAJ3 gates12922and12926. Layer 3 may include Layer 3 Logic Cone12930, flip-flop12934, and MAJ3 gates12932and12936. The logic cones12910,12920and12930all may perform a substantially identical logic function. The flip-flops12914,12924and12934may be illustratively scan flip-flops. If a Repair Layer is present (not shown inFIG.47), then the flip-flop8702ofFIG.32may be used to implement repair of a defective logic cone before 3D IC12900is shipped from the factory. The MAJ3 gates12912,12922and12932may compare the outputs from the three logic cones12910,12920and12930and output a logic value consistent with the majority of the inputs. Similarly, the MAJ3 gates12916,12926and12936may compare the outputs from the three flip-flops12914,12924and12934and output a logic value consistent with the majority of the inputs. Thus if one of the three logic cones or one of the three flip-flops is defective, the correct logic value will be present at the output of all six of the MAJ3 gates. One illustrative advantage of the embodiment ofFIG.47is that Layer 1, Layer 2 or Layer 3 can all be fabricated using all or nearly all of the same masks. Another illustrative advantage may be that MAJ3 gates12716,12726and12736also effectively function as a Single Event Transient (SET) filter while MAJ3 gates12716,12726and12736may also effectively function as a Single Event Upset (SEU) filter for high reliability or radiation tolerant applications as described in Rezgui cited above. Some embodiments of the invention can be applied to a large variety of commercial as well as high-reliability aerospace and military applications. The ability to fix defects in the factory with Repair Layers combined with the ability to automatically fix delayed defects (by masking them with three layer Triple Modular Redundancy (TMR) embodiments or replacing faulty circuits with two layer replacement embodiments) may allow the creation of much larger and more complex three dimensional systems than may be possible with conventional two dimensional integrated circuit (IC) technology. These various aspects of the present invention can be traded off against the cost requirements of the target application. In order to reduce the cost of a 3D IC according to some embodiments of the present invention, it may be desirable to use the same set of masks to manufacture each Layer. This can be done by creating an identical structure of vias in an appropriate pattern on each layer and then offsetting it by a desired amount when aligning Layer 1 and Layer 2. FIG.48Aillustrates a via pattern13000constructed on Layer 1 of 3D ICs like 11900, 12100, 12200, 12300, 12400, 12500 and 12600 of U.S. Pat. No. 8,273,610, incorporated herein by reference. At a minimum the metal overlap pad at each via location13002,13004,13006and13008may be present on the top and bottom metal layers of Layer 1. Via pattern13000may occur in proximity to each repair or replacement multiplexer on Layer 1 where via metal overlap pads13002and13004(labeled L1/D0 for Layer 1 input D0 in the figure) may be coupled to the D0 multiplexer input at that location, and via metal overlap pads13006and13008(labeled L1/D1 for Layer 1 input D1 in the figure) may be coupled to the D1 multiplexer input. Similarly,FIG.48Billustrates a substantially identical via pattern13010which may be constructed on Layer 2 of 3D ICs like 11900, 12100, 12200, 12300, 12400, 12500 and 12600 of U.S. Pat. No. 8,273,610, incorporated herein by reference. At a minimum the metal overlap pad at each via location13012,13014,13016and13018may be present on the top and bottom metal layers of Layer 2. Via pattern13010may occur in proximity to each repair or replacement multiplexer on Layer 2 where via metal overlap pads13012and13014(labeled L2/D0 for Layer 2 input D0 in the figure) may be coupled to the D0 multiplexer input at that location, and via metal overlap pads13016and13018(labeled L2/D1 for Layer 2 input D1 in the figure) may be coupled to the D1 multiplexer input. FIG.48Cillustrates a top view where via patterns13000and13010may be aligned offset by one interlayer interconnection pitch. The interlayer interconnects may be TSVs or some other interlayer interconnect technology.FIG.48Cmay illustrate via metal overlap pads13002,13004,13006,13008,13012,13014,13016and13018as previously discussed. InFIG.48C, Layer 2 may be offset by one interlayer connection pitch to the right relative to Layer 1. This offset may cause via metal overlap pads13004and13018to physically overlap with each other. Similarly, this offset may cause via metal overlap pads13006and13012to physically overlap with each other. If Through Silicon Vias or other interlayer vertical coupling points are placed at these two overlap locations (using a single mask), then multiplexer input D1 of Layer 2 may be coupled to multiplexer input D0 of Layer 1 and multiplexer input D0 of Layer 2 may be coupled to multiplexer input D1 of Layer 1. This may be precisely the interlayer connection topology necessary to realize the repair or replacement of logic cones and functional blocks in, for example, the embodiments described with respect toFIGS.121A and123of the parent application. FIG.48Dillustrates a side view of a structure employing the technique described in conjunction withFIGS.48A,48B and48C.FIG.48Dillustrates an exemplary 3D IC generally indicated by13020including two instances of Layer13030stacked together with the top instance labeled Layer 2 and the bottom instance labeled Layer 1 in the figure. Each instance of Layer13020may include an exemplary transistor13031, an exemplary contact13032, exemplary metal 113033, exemplary via 113034, exemplary metal 213035, exemplary via 213036, and exemplary metal 313037. The dashed oval labeled13000may indicate the part of the Layer 1 corresponding to via pattern13000inFIGS.48A and48C. Similarly, the dashed oval labeled13010may indicate the part of the Layer 2 corresponding to via pattern13010inFIGS.48B and48C. An interlayer via such as TSV13040in this example may be shown coupling the signal D1 of Layer 2 to the signal D0 of Layer 1. A second interlayer via, not shown since it is out of the plane ofFIG.48D, may couple the signal D01 of Layer 2 to the signal D1 of Layer 1. As can be seen inFIG.48D, while Layer 1 may be identical to Layer 2, Layer 2 can be offset by one interlayer via pitch allowing the TSVs to correctly align to each layer while for example, only a single interlayer via mask may make the correct interlayer connections. As previously discussed, in some embodiments of the present invention it may be desirable for the control logic on each Layer of a 3D IC to know which layer it is in. It may also be desirable to use all of the same masks for each of the Layers. In an embodiment using the one interlayer via pitch offset between layers to correctly couple the functional and repair connections, a different via pattern can be placed in proximity to the control logic to exploit the interlayer offset and uniquely identify each of the layers to its control logic. FIG.49Aillustrates a via pattern13100which may be constructed on Layer 1 of 3D ICs like 11900, 12100, 12200, 12300, 12400, 12500 and 12600 of U.S. Pat. No. 8,273,610, incorporated herein by reference. At a minimum the metal overlap pad at each via location13102,13104, and13106may be present on the top and bottom metal layers of Layer 1. Via pattern13100may occur in proximity to control logic on Layer 1. Via metal overlap pad13102may be coupled to ground (labeled L1/G in the figure for Layer 1 Ground). Via metal overlap pad13104may be coupled to a signal named ID (labeled L1/ID in the figure for Layer 1 ID). Via metal overlap pad13106may be coupled to the power supply voltage (labeled L1/V in the figure for Layer 1 VCC). FIG.49Billustrates a via pattern13110which may be constructed on Layer 1 of 3D ICs like 11900, 12100, 12200, 12300, 12400, 12500 and 12600 of U.S. Pat. No. 8,273,610, incorporated herein by reference. At a minimum the metal overlap pad at each via location13112,13114, and13116may be present on the top and bottom metal layers of Layer 2. Via pattern13110may occur in proximity to control logic on Layer 2. Via metal overlap pad13112may be coupled to ground (labeled L2/G in the figure for Layer 2 Ground). Via metal overlap pad13114may be coupled to a signal named ID (labeled L2/ID in the figure for Layer 2 ID). Via metal overlap pad13116may be coupled to the power supply voltage (labeled L2/V in the figure for Layer 2 VCC). FIG.49Cillustrates a top view where via patterns13100and13110may be aligned offset by one interlayer interconnection pitch. The interlayer interconnects may be TSVs or some other interlayer interconnect technology.FIG.48Cillustrates via metal overlap pads13102,13104,13106,13112,13114, and13016as previously discussed. InFIG.48C, Layer 2 may be offset by one interlayer connection pitch to the right relative to Layer 1. This offset may cause via metal overlap pads13104and13112to physically overlap with each other. Similarly, this offset may cause via metal overlap pads13106and13114to physically overlap with each other. If Through Silicon Vias or other interlayer vertical coupling points may be placed at these two overlap locations (using a single mask) then the Layer 1 ID signal may be coupled to ground and the Layer 2 ID signal may be coupled to VCC. This configuration may allow the control logic in Layer 1 and Layer 2 to uniquely know their vertical position in the stack. Persons of ordinary skill in the art will appreciate that the metal connections between Layer 1 and Layer 2 may typically be much larger including larger pads and numerous TSVs or other interlayer interconnections. This increased size may make alignment of the power supply nodes easy and ensures that L1/V and L2/V may both be at the positive power supply potential and that L1/G and L2/G may both be at ground potential. Several embodiments of the invention may utilize Triple Modular Redundancy (TMR) distributed over three Layers. In such embodiments it may be desirable to use the same masks for all three Layers. FIG.50Aillustrates a via metal overlap pattern13200including a 3×3 array of TSVs (or other interlayer coupling technology). The TMR interlayer connections may occur in the proximity of a majority-of-three (MAJ3) gate typically fanning in or out from either a flip-flop or functional block. Thus at each location on each of the three layers, the function f(X0, X1, X2)=MAJ3(X0, X1, X2) may be implemented where X0, X1 and X2 are the three inputs to the MAJ3 gate. For purposes of this discussion, the X0 input may always be coupled to the version of the signal generated on the same layer as the MAJ3 gate and the X1 and X2 inputs come from the other two layers. In via metal overlap pattern13200, via metal overlap pads13202,13212and13216may be coupled to the X0 input of the MAJ3 gate on that layer, via metal overlap pads13204,13208and13218may be coupled to the X1 input of the MAJ3 gate on that layer, and via metal overlap pads13206,13210and13214may be coupled to the X2 input of the MAJ3 gate on that layer. FIG.50Billustrates an exemplary 3D IC generally indicated by13220having three Layers labeled Layer 1, Layer 2 and Layer 3 from bottom to top. Each layer may include an instance of via metal overlap pattern13200in the proximity of each MAJ3 gate used to implement a TMR related interlayer coupling. Layer 2 may be offset one interlayer via pitch to the right relative to Layer 1 while Layer 3 may be offset one interlayer via pitch to the right relative to Layer 2. The illustration inFIG.50Bmay be an abstraction. While it may correctly show the two interlayer via pitch offsets in the horizontal direction, a person of ordinary skill in the art will realize that each row of via metal overlap pads in each instance of via metal overlap pattern13200may be horizontally aligned with the same row in the other instances. Thus there may be three locations where a via metal overlap pad can be aligned on all three layers.FIG.50Bshows three interlayer vias13230,13240and13250placed in those locations coupling Layer 1 to Layer 2 and three more interlayer vias13232,13242and13252placed in those locations coupling Layer 2 to Layer 3. The same interlayer via mask may be used for both interlayer via fabrication steps. Thus the interlayer vias13230and13232may be vertically aligned and couple together the Layer 1 X2 MAJ3 gate input, the Layer 2 X0 MAJ3 gate input, and the Layer 3 X1 MAJ3 gate input. Similarly, the interlayer vias13240and13242may be vertically aligned and couple together the Layer 1 X1 MAJ3 gate input, the Layer 2 X2 MAJ3 gate input, and the Layer 3 X0 MAJ3 gate input. Finally, the interlayer vias13250and13252may be vertically aligned and couple together the Layer 1 X0 MAJ3 gate input, the Layer 2 X1 MAJ3 gate input, and the Layer 3 X2 MAJ3 gate input. Since the X0 input of the MAJ3 gate in each layer may be driven from that layer, each driver may be coupled to a different MAJ3 gate input on each layer preventing drivers from being shorted together and the each MAJ3 gate on each layer may receive inputs from each of the three drivers on the three Layers. Some embodiments of the invention can be applied to a large variety of commercial as well as high-reliability aerospace and military applications. The ability to fix defects in the factory with Repair Layers combined with the ability to automatically fix delayed defects (by masking them with three layer TMR embodiments or replacing faulty circuits with two layer replacement embodiments) may allow the creation of much larger and more complex three dimensional systems than may be possible with conventional two dimensional integrated circuit (IC) technology. These various aspects of the present invention can be traded off against the cost requirements of the target application. For example, a 3D IC targeted at inexpensive consumer products where cost may be a dominant consideration might do factory repair to maximize yield in the factory but not include any field repair circuitry to minimize costs in products with short useful lifetimes. A 3D IC aimed at higher end consumer or lower end business products might use factory repair combined with two layer field replacement. A 3D IC targeted at enterprise class computing devices which balance cost and reliability might skip doing factory repair and use TMR for both acceptable yields as well as field repair. A 3D IC targeted at high reliability, military, aerospace, space, or radiation-tolerant applications might do factory repair to ensure that all three instances of every circuit may be fully functional and use TMR for field repair as well as SET and SEU filtering. Battery operated devices for the military market might add circuitry to allow the device to operate, for example, only one of the three TMR layers to save battery life and include a radiation detection circuit which automatically switches into TMR mode when needed if the operating environment may change. Many other combinations and tradeoffs may be possible within the scope of the illustrated embodiments of the invention. It is worth noting that many of the principles of the invention may also applicable to conventional two dimensional integrated circuits (2D ICs). For example, an analogous of the two layer field repair embodiments could be built on a single layer with both versions of the duplicate circuitry on a single 2D IC employing the same cross connections between the duplicate versions. A programmable technology like, for example, fuses, antifuses, flash memory storage, etc., could be used to effect both factory repair and field repair. Similarly, analogous versions of some of the TMR embodiments may have unique topologies in 2D ICs as well as in 3D ICs which may also improve the yield or reliability of 2D IC systems if implemented on a single layer. Some embodiments of the invention may be to use the concepts of repair and redundancy layers to implement extremely large designs that extend beyond the size of a single reticle, up to and inclusive of a full wafer. This concept of Wafer Scale Integration (“WSI”) was attempted in the past by companies such as Trilogy Systems and was abandoned because of extremely low yield. The ability of some of the embodiments of the invention is to effect multiple repairs by using a repair layer, or use of masking multiple faults by using redundancy layers, the result may be to make WSI with very high yield a viable option. One embodiment of the invention may improve WSI by using the Continuous Array (CA) concept described herein this document. In the case of WSI, however, the CA may extend beyond a single reticle and may potentially span the whole wafer. A custom mask may be used to define unused parts of the wafer which may be etched away. Particular care must be taken when a design such as WSI crosses reticle boundaries. Alignment of features across a reticle boundary may be worse than the alignment of features within the reticle, and WSI designs must accommodate this potential misalignment. One way of addressing this is to use wider than minimum metal lines, with larger than minimum pitches, to cross the reticle boundary, while using a full lithography resolution within the reticle. Another embodiment of the invention uses custom reticles for location on the wafer, creating a partial of a full custom design across the wafer. As in the previous case, wider lines and coarser line pitches may be used for reticle boundary crossing. In substantially all WSI embodiments yield-enhancement may be achieved through fault masking techniques such as TMR, or through repair layers, as illustrated in FIG. 24 through FIG. 44 of U.S. patent application Ser. No. 13/098,997. In another variation on the WSI invention one can selectively replace blocks on one layer with blocks on the other layer to provide speed improvement rather than to effect logical repair. In another variation on the WSI invention one can use vertical stacking techniques as illustrated in FIG. 12A-12E of U.S. patent application Ser. No. 13/098,997 to flexibly provide variable amounts of specialized functions, and I/O in particular, to WSI designs. FIG.16is a drawing illustration of a 3D IC system with redundancy. It illustrates a 3D IC programmable system including: first programmable layer4100of 3×3 tiles4102, overlaid by second programmable layer4110of 3×3 tiles4112, overlaid by third programmable layer4120of 3×3 tiles4122. Between a tile and its neighbor tile in the layer there may be many programmable connections4104. The programmable element4106could include, for example, antifuse, pass transistor controlled driver, floating gate flash transistor, or similar electrically programmable element. An example of a commercial anti-fuse may be the oxide fuse of Kilopass Technology. Each inter-tile connection4104may have a branch out programmable connection4105connected to inter-layer vertical connection4140. The end product may be designed so that at least one layer such as second programmable layer4110can be left for redundancy. When the end product programmable system may be programmed for the end application, each tile can run its own Built-in Test, for example, by using its own MCU. A tile detected to have a defect may be replaced by the tile in the redundancy layer, such as second programmable layer4110. The replacement may be done by the tile that may be at the same location but in the redundancy layer and therefore it may have an acceptable impact on the overall product functionality and performance. For example, if tile (1,0,0) has a defect then tile (1,0,1) may be programmed to have exactly the same function and may replace tile (1,0,0) by properly setting the inter tile programmable connections. Therefore, if defective tile (1,0,0) was supposed to be connected to tile (2,0,0) by connection4104with programmable element4106, then programmable element4106may be turned off and programmable elements4116,4117,4107will be turned on instead. A similar multilayer connection structure may be used for any connection in or out of a repeating tile. So if the tile has a defect, the redundant tile of the redundant layer may be programmed to the defected tile functionality and the multilayer inter tile structure may be activated to disconnect the faulty tile and connect the redundant tile. The inter layer vertical connection4140could be also used when tile (2,0,0) is defective to insert tile (2,0,1), of the redundant layer, instead. In such case (2,0,1) may be programmed to have exactly the same function as tile (2,0,0), programmable element4108may be turned off and programmable elements4118,4117,4107may be turned on instead. This testing could be done from off chip rather than a BIST MCU. An additional embodiment of the invention may be a modified TSV (Through Silicon Via) flow. This flow may be for wafer-to-wafer TSV and may provide a technique whereby the thickness of the added wafer may be reduced to about 1 micrometer (micron).FIG.34AtoFIG.34Dillustrate such a technique. The first wafer9302may be the base on top of which the ‘hybrid’ 3D structure may be built. A second wafer top substrate wafer9304may be bonded on top of the first wafer9302. The new top wafer may be face-down so that the electrical circuits9305may be face-to-face with the first wafer9302circuits9303. The bond may be oxide-to-oxide in some applications or copper-to-copper in other applications. In addition, the bond may be by a hybrid bond wherein some of the bonding surface may be oxide and some may be copper. After bonding, the top substrate wafer9304may be thinned down to about 60 micron in a conventional back-lap and CMP process.FIG.34Billustrates the now thinned top wafer9306bonded to the first wafer9302. The next step may include a high accuracy measurement of the top wafer9306thickness. Then, using a high power 1-4 MeV H+ implant, a cleave plane9310may be defined in the top wafer9306. The cleave plane9310may be positioned about 1 micron above the bond surface as illustrated inFIG.34C. This process may be performed with a special high power implanter such as, for example, the implanter used by SiGen Corporation for their PV (PhotoVoltaic) application. Having the accurate measure of the top wafer9306thickness and the highly controlled implant process may enable cleaving most of the top wafer9306out thereby leaving a very thin layer9312of about 1 micron, bonded on top of the first wafer9302as illustrated inFIG.34D. An advantage of this process flow may be that an additional wafer with circuits could now be placed and bonded on top of the bonded structure9322in a similar manner. But first a connection layer may be built on the back of thin layer9312to allow electrical connection to the bonded structure9322circuits. Having the top layer thinned to a single micron level may allow such electrical connection metal layers to be fully aligned to the top wafer thin layer9312electrical circuits9305and may allow the vias through the back side of top thin layer9312to be relatively small, of about 100 nm in diameter. The thinness of the top thin layer9312may enable the modified TSV to be at the level of 100 nm vs. the 5 microns necessary for TSVs that need to go through 50 microns of silicon. Unfortunately the misalignment of the wafer-to-wafer bonding process may still be quite significant at about +1-0.5 micron. Accordingly, as described elsewhere in this document in relation toFIG.75, a landing pad of about 1×1 microns may be used on the top of the first wafer9302to connect with a small metal contact on the face of the top substrate wafer9304while using copper-to-copper bonding. This process may represent a connection density of about 1 connection per 1 square micron. It may be desirable to increase the connection density using a concept as illustrated in FIG. 80 of U.S. Pat. No. 8,273,610, incorporated herein by reference, and the associated explanations. In the modified TSV case, it may be much more challenging to do so because the two wafers being bonded may be fully processed and once bonded, only very limited access to the landing strips may be available. However, to construct a via, etching through all layers may be needed.FIG.35illustrates a method and structures to address these issues. FIG.35Aillustrates four metal landing strips9402exposed at the upper layer of the first wafer9302. The landing strips9402may be oriented East-West at a length9406of the maximum East-West bonding misalignment Mx plus a delta D, which will be explained later. The pitch of the landing strip may be twice the minimum pitch Py of this upper layer of the first wafer9302,9403may indicate an unused potential room for an additional metal strip. FIG.35Billustrates landing strips9412,9413exposed at the top of the second wafer thin layer9312.FIG.35Balso shows two columns of landing strips, namely, A and B going North to South. The length of these landing strips may be 1.25Py. The two wafers9302and top wafer thin layer9312may be bonded copper-to-copper and the landing strips ofFIG.35AandFIG.35Bmay be designed so that the bonding misalignment does not exceed the maximum misalignment Mx in the East-West direction and My in the North-South direction. The landing strips9412and9413ofFIG.35Bmay be designed so that they may never unintentionally short to landing strips9402of94A and that either row A landing strips9412or row B landing strips9413may achieve full contact with landing strips9402. The delta D may be the size from the East edge of landing strips9413of row B to the West edge of A landing strips9412. The number of landing strips9412and9413ofFIG.35Bmay be designed to cover theFIG.35Alanding strips9402plus My to cover maximum misalignment error in the North-South direction. Substantially all the landing strips9412and9413ofFIG.35Bmay be routed by the internal routing of the top wafer thin layer9312to the bottom of the wafer next to the transistor layers. The location on the bottom of the wafer is illustrated inFIG.34Das the upper side of the9322structure. Now new vias9432may be formed to connect the landing strips to the top surface of the bonded structure using conventional wafer processing steps.FIG.35Cillustrates all the via connections routed to the landing strips ofFIG.35B, arranged in row A9432and row B9433. In addition, the vias9436for bringing in the signals may also be processed. All these vias may be aligned to the top wafer thin layer9312. As illustrated inFIG.35C, a metal mask may now be used to connect, for example, four of the vias9432and9433to the four vias9436using metal strips9438. This metal mask may be aligned to the top wafer thin layer9312in the East-West direction. This metal mask may also be aligned to the top wafer thin layer9312in the North-South direction but with a special offset that is based on the bonding misalignment in the North-South direction. The length of the metal structure metal strips9438in the North South direction may be enough to cover the worst case North-South direction bonding misalignment. It should be stated again that embodiments of the invention could be applied to many applications other than programmable logic such a Graphics Processor which may include many repeating processing units. Other applications might include general logic design in 3D ASICs (Application Specific Integrated Circuits) or systems combining ASIC layers with layers comprising at least in part other special functions. Persons of ordinary skill in the art will appreciate that many more embodiments and combinations are possible by employing the inventive principles contained herein and such embodiments will readily suggest themselves to such skilled persons. Thus the invention is not to be limited in any way except by the appended claims. Yet another alternative to implement 3D redundancy to improve yield by replacing a defective circuit may be by the use of Direct Write E-beam instead of a programmable connection. An additional variation of the programmable 3D system may comprise a tiled array of programmable logic tiles connected with I/O structures that may be pre-fabricated on the base wafer1402ofFIG.4. Additional flexibility and reuse of masks may be achieved by utilizing, for example, only a portion of the full reticle exposure. Modern steppers may allow covering portions of the reticle and hence projecting only a portion of the reticle. Accordingly a portion of a mask set may be used for one function while another portion of that same mask set would be used for another function. For example, let the structure ofFIG.13represent the logic portion of the end device of a 3D programmable system. On top of that 3×3 programmable tile structure I/O structures could be built utilizing process techniques according to, for example,FIG.22orFIG.11. There may be a set of masks where various portions may provide for the overlay of different I/O structures; for example, one portion including simple I/Os, and another of Serializer/Deserializer (Ser/Des) I/Os. Each set may be designed to provide tiles of I/O that substantially perfectly overlay the programmable logic tiles. Then out of these two portions on one mask set, multiple variations of end systems could be produced, including one with all nine tiles as simple I/Os, another with SerDes overlaying tile (0,0) while simple I/Os may be overlaying the other eight tiles, another with SerDes overlaying tiles (0,0), (0,1) and (0,2) while simple I/Os may be overlaying the other 6 tiles, and so forth. In fact, if properly designed, multiples of layers could be fabricated one on top of the other offering a large variety of end products from a limited set of masks. Persons of ordinary skill in the art will appreciate that this technique can have applicability beyond programmable logic and may profitably be employed in the construction of many 3D ICs and 3D systems. Thus the scope of the invention is only to be limited by the appended claims. In yet an additional alternative illustrative embodiment of the invention, the 3D antifuse Configurable System, may also include a Programming Die. In some cases of FPGA products, and primarily in antifuse-based products, there may be an external apparatus that may be used for the programming the device. In many cases it may be a user convenience to integrate this programming function into the FPGA device. This may result in a significant die overhead as the programming process may need higher voltages as well as control logic. The programmer function could be designed into a dedicated Programming Die. Such a Programmer Die could include the charge pump, to generate the higher programming voltage, and a controller with the associated programming to program the antifuse configurable dies within the 3D Configurable circuits, and the programming check circuits. The Programming Die might be fabricated using a lower cost older semiconductor process. An additional advantage of this 3D architecture of the Configurable System may be a high volume cost reduction option wherein the antifuse layer may be replaced with a custom layer and, therefore, the Programming Die could be removed from the 3D system for a more cost effective high volume production. It will be appreciated by persons of ordinary skill in the art, that some embodiments of the invention may be using the term antifuse as used as the common name in the industry, but it may also refer, according to some embodiments, to any micro element that functions like a switch, meaning a micro element that initially may have highly resistive-OFF state, and electronically it could be made to switch to a very low resistance-ON state. It could also correspond to a device to switch ON-OFF multiple times—a re-programmable switch. As an example there may be new technologies being developed, such as the electro-statically actuated Metal-Droplet micro-switch introduced by C. J. Kim of UCLA micro & nano manufacturing lab, which may be compatible for integration onto CMOS chips. It will be appreciated by persons skilled in the art that the present invention may not be limited to antifuse configurable logic and it can be applicable to other non-volatile configurable logic. An example for such application is the Flash based configurable logic. Flash programming may also need higher voltages, and having the programming transistors and the programming circuits in the base diffusion layer may reduce the overall density of the base diffusion layer. Using various illustrative embodiments of the invention may be useful and could allow a higher device density. It may therefore be suggested to build the programming transistors and the programming circuits, not as part of the diffusion layer, but according to one or more illustrative embodiments of the invention. In high volume production, one or more custom masks could be used to replace the function of the Flash programmiing and accordingly may save the need to add on the programming transistors and the programming circuits. Unlike metal-to-metal antifuses that could be placed as part of the metal interconnection, Flash circuits may need to be fabricated in the base diffusion layers. As such it might be less efficient to have the programming transistor in a layer far above. An illustrative alternative embodiment of the invention may be to use Through-Silicon-Via816to connect the configurable logic device and its Flash devices to an underlying structure of Foundation layer814including the programming transistors. In this document, various terms may have been used while generally referring to the element. For example, “house” may refer to the first mono-crystalline layer with its transistors and metal interconnection layer or layers. This first mono-crystalline layer may have also been referred to as the main wafer and sometimes as the acceptor wafer and sometimes as the base wafer. Some embodiments of the invention may include alternative techniques to build IC (Integrated Circuit) devices including techniques and methods to construct 3D IC systems. Some embodiments of the invention may enable device solutions with far less power consumption than prior art. These device solutions could be very useful for the growing application of mobile electronic devices and mobile systems, such as, for example, mobile phones, smart phone, and cameras. For example, incorporating the 3D IC semiconductor devices according to some embodiments of the invention within these mobile electronic devices and mobile systems could provide superior mobile units that could operate much more efficiently and for a much longer time than with prior art technology. Smart mobile systems may be greatly enhanced by complex electronics at a limited power budget. The 3D technology described in the multiple embodiments of the invention would allow the construction of low power high complexity mobile electronic systems. For example, it would be possible to integrate into a small form function a complex logic circuit with high density high speed memory utilizing some of the 3D DRAM embodiments of the invention and add some non-volatile 3D NAND charge trap or RRAM described in some embodiments of the invention. In U.S. application Ser. No. 12/903,862, filed by some of the inventors and assigned to the same assignee, a 3D micro display and a 3D image sensor are presented. Integrating one or both of these with complex logic and or memory could be very effective for mobile system. Additionally, mobile systems could be customized to some specific market applications by integrating some embodiments of the invention. Moreover, utilizing 3D programmable logic or 3D gate array as had been described in some embodiments of the invention could be very effective in forming flexible mobile systems. The need to reduce power to allow effective use of limited battery energy and also the lightweight and small form factor derived by highly integrating functions with low waste of interconnect and substrate could be highly benefitted by the redundancy and repair idea of the 3D monolithic technology as has been presented in embodiments of the invention. This unique technology could enable a mobile device that would be lower cost to produce or would require lower power to operate or would provide a lower size or lighter carry weight, and combinations of these 3D monolithic technology features may provide a competitive or desirable mobile system. Another unique market that may be addressed by some of the embodiments of the invention could be a street corner camera with supporting electronics. The 3D image sensor described in the Ser. No. 12/903,862 application would be very effective for day/night and multi-spectrum surveillance applications. The 3D image sensor could be supported by integrated logic and memory such as, for example, a monolithic 3D IC with a combination of image processing and image compression logic and memory, both high speed memory such as 3D DRAM and high density non-volatile memory such as 3D NAND or RRAM or other memory, and other combinations. This street corner camera application would require low power, low cost, and low size or any combination of these features, and could be highly benefitted from the 3D technologies described herein. 3D ICs according to some embodiments of the invention could enable electronic and semiconductor devices with much a higher performance as a result from the shorter interconnect as well as semiconductor devices with far more complexity via multiple levels of logic and providing the ability to repair or use redundancy. The achievable complexity of the semiconductor devices according to some embodiments of the invention could far exceed what may be practical with the prior art technology. These potential advantages could lead to more powerful computer systems and improved systems that have embedded computers. Some embodiments of the invention may enable the design of state of the art electronic systems at a greatly reduced non-recurring engineering (NRE) cost by the use of high density 3D FPGAs or various forms of 3D array base ICs with reduced custom masks as described previously. These systems could be deployed in many products and in many market segments. Reduction of the NRE may enable new product family or application development and deployment early in the product lifecycle by lowering the risk of upfront investment prior to a market being developed. The above potential advantages may also be provided by various mixes such as reduced NRE using generic masks for layers of logic and other generic masks for layers of memories and building a very complex system using the repair technology to overcome the inherent yield limitation. Another form of mix could be building a 3D FPGA and add on it 3D layers of customizable logic and memory so the end system could have field programmable logic on top of the factory customized logic. There may be many ways to mix the many innovative elements to form 3D IC to support the need of an end system, including using multiple devices wherein more than one device incorporates elements of embodiments of the invention. An end system could benefit from a memory device utilizing embodiments of the invention 3D memory integrated together with a high performance 3D FPGA integrated together with high density 3D logic, and so forth. Using devices that can use one or multiple elements according to some embodiments of the invention may allow for better performance or lower power and other illustrative advantages resulting from the use of some embodiments of the invention to provide the end system with a competitive edge. Such end system could be electronic based products or other types of systems that may include some level of embedded electronics, such as, for example, cars, and remote controlled vehicles. Commercial wireless mobile communications have been developed for almost thirty years, and play a special role in today's information and communication technology Industries. The mobile wireless terminal device has become part of our life, as well as the Internet, and the mobile wireless terminal device may continue to have a more important role on a worldwide basis. Currently, mobile (wireless) phones are undergoing much development to provide advanced functionality. The mobile phone network is a network such as a GSM, GPRS, or WCDMA, 3G and 4G standards, and the network may allow mobile phones to communicate with each other. The base station may be for transmitting (and receiving) information to the mobile phone. A typical mobile phone system may include, for example, a processor, a flash memory, a static random access memory, a display, a removable memory, a radio frequency (RF) receiver/transmitter, an analog base band (ABB), a digital base band (DBB), an image sensor, a high-speed bi-directional interface, a keypad, a microphone, and a speaker. A typical mobile phone system may include a multiplicity of an element, for example, two or more static random access memories, two or more displays, two or more RF receiver/transmitters, and so on. Conventional radios used in wireless communications, such as radios used in conventional cellular telephones, typically may include several discrete RF circuit components. Some receiver architectures may employ superhetrodyne techniques. In a superhetrodyne architecture an incoming signal may be frequency translated from its radio frequency (RF) to a lower intermediate frequency (IF). The signal at IF may be subsequently translated to baseband where further digital signal processing or demodulation may take place. Receiver designs may have multiple IF stages. The reason for using such a frequency translation scheme is that circuit design at the lower IF frequency may be more manageable for signal processing. It is at these IF frequencies that the selectivity of the receiver may be implemented, automatic gain control (AGC) may be introduced, etc. A mobile phone's need of a high-speed data communication capability in addition to a speech communication capability has increased in recent years. In GSM (Global System for Mobile communications), one of European Mobile Communications Standards, GPRS (General Packet Radio Service) has been developed for speeding up data communication by allowing a plurality of time slot transmissions for one time slot transmission in the GSM with the multiplexing TDMA (Time Division Multiple Access) architecture. EDGE (Enhanced Data for GSM Evolution) architecture provides faster communications over GPRS. 4th Generation (4G) mobile systems aim to provide broadband wireless access with nominal data rates of 100 Mbit/s. 4G systems may be based on the 3GPP LTE (Long Term Evolution) cellular standard, WiMax or Flash-OFDM wireless metropolitan area network technologies. The radio interface in these systems may be based on all-IP packet switching, MIMO diversity, multi-carrier modulation schemes, Dynamic Channel Assignment (DCA) and channel-dependent scheduling. Prior art such as U.S. application Ser. No. 12/871,984 may provide a description of a mobile device and its block-diagram. It is understood that the use of specific component, device and/or parameter names (such as those of the executing utility/logic described herein) are for example only and not meant to imply any limitations on the invention. The invention may thus be implemented with different nomenclature/terminology utilized to describe the components/devices/parameters herein, without limitation. Each term utilized herein is to be given its broadest interpretation given the context in which that term is utilized. For example, as utilized herein, the following terms are generally defined: (1) Mobile computing/communication device (MCD): is a device that may be a mobile communication device, such as a cell phone, or a mobile computer that performs wired and/or wireless communication via a connected wireless/wired network. In some embodiments, the MCD may include a combination of the functionality associated with both types of devices within a single standard device (e.g., a smart phones or personal digital assistant (PDA)) for use as both a communication device and a computing device. A block diagram representation of an exemplary mobile computing device (MCD) is illustrated inFIG.63, within which several of the features of the described embodiments may be implemented. MCD15600may be a desktop computer, a portable computing device, such as a laptop, personal digital assistant (PDA), a smart phone, and/or other types of electronic devices that may generally be considered processing devices. As illustrated, MCD15600may include at least one processor or central processing unit (CPU)15602which may be connected to system memory15606via system interconnect/bus15604. CPU15602may include at least one digital signal processing unit (DSP). Also connected to system interconnect/bus15604may be input/output (I/O) controller15615, which may provide connectivity and control for input devices, of which pointing device (or mouse)15616and keyboard15617are illustrated. JI/controller15615may also provide connectivity and control for output devices, of which display15618is illustrated. Additionally, a multimedia drive15619(e.g., compact disk read/write (CDRW) or digital video disk (DVD) drive) and USB (universal serial bus) port15620are illustrated, and may be coupled to I/O controller15615. Multimedia drive15619and USB port15620may enable insertion of a removable storage device (e.g., optical disk or “thumb” drive) on which data/instructions/code may be stored and/or from which data/instructions/code may be retrieved. MCD15600may also include storage15622, within/from which data/instructions/code may also be stored/retrieved. MCD15600may further include a global positioning system (GPS) or local position system (LPS) detection component15624by which MCD15600may be able to detect its current location (e.g., a geographical position) and movement of MCD15600, in real time. MCD15600may include a network/communication interface15625, by which MCD15600may connect to one or more second communication devices15632or to wireless service provider server15637, or to a third party server15638via one or more access/external communication networks, of which a wireless Communication Network15630is provided as one example and the Internet15636is provided as a second example. It is appreciated that MCD15600may connect to third party server15638through an initial connection with Communication Network15630, which in turn may connect to third party server15638via the Internet15636. In addition to the above described hardware components of MCD15600, various features of the described embodiments may be completed/supported via software (or firmware) code or logic stored within system memory15606or other storage (e.g., storage15622) and may be executed by CPU15602. Thus, for example, illustrated within system memory15606are a number of software/firmware/logic components, including operating system (OS)15608(e.g., Microsoft Windows® or Windows Mobile®, trademarks of Microsoft Corp, or GNU®/Linux®, registered trademarks of the Free Software Foundation and The Linux Mark Institute, and AIX®, registered trademark of International Business Machines), and word processing and/or other application(s)15609. Also illustrated are a plurality (four illustrated) software implemented utilities, each providing different one of the various functions (or advanced features) described herein. Including within these various functional utilities are: Simultaneous Text Waiting (STW) utility15611, Dynamic Area Code Pre-pending (DACP) utility15612, Advanced Editing and Interfacing (AEI) utility15613and Safe Texting Device Usage (STDU) utility15614. In actual implementation and for simplicity in the following descriptions, each of these different functional utilities are assumed to be packaged together as sub-components of a general MCD utility15610, and the various utilities are interchangeably referred to as MCD utility15610when describing the utilities within the figures and claims. For simplicity, the following description will refer to a single utility, namely MCD utility15610. MCD utility15610may, in some embodiments, be combined with one or more other software modules, including for example, word processing application(s)15609and/or OS15608to provide a single executable component, which then may provide the collective functions of each individual software component when the corresponding combined code of the single executable component is executed by CPU15602. Each separate utility111/112/113/114is illustrated and described as a standalone or separate software/firmware component/module, which provides specific functions, as described below. As a standalone component/module, MCD utility15610may be acquired as an off-the-shelf or after-market or downloadable enhancement to existing program applications or device functions, such as voice call waiting functionality (not shown) and user interactive applications with editable content, such as, for example, an application within the Windows Mobile® suite of applications. In at least one implementation, MCD utility15610may be downloaded from a server or website of a wireless provider (e.g., wireless provider server15637) or a third party server15638, and either installed on MCD15600or executed from the wireless provider server15637or third party server156138. CPU15602may execute MCD utility15610as well as OS15608, which, in one embodiment, may support the user interface features of MCD utility15610, such as generation of a graphical user interface (GUI), where required/supported within MCD utility code. In several of the described embodiments, MCD utility15610may generate/provide one or more GUIs to enable user interaction with, or manipulation of, functional features of MCD utility15610and/or of MCD15600. MCD utility15610may, in certain embodiments, enable certain hardware and firmware functions and may thus be generally referred to as MCD logic. Some of the functions supported and/or provided by MCD utility15610may be enabled as processing code/instructions/logic executing on DSP/CPU15602and/or other device hardware, and the processor thus may complete the implementation of those function(s). Among, for example, the software code/instructions/logic provided by MCD utility15610, and which are specific to some of the described embodiments of the invention, may be code/logic for performing several (one or a plurality) of the following functions: (1) Simultaneous texting during ongoing voice communication providing a text waiting mode for both single number mobile communication devices and multiple number mobile communication devices; (2) Dynamic area code determination and automatic back-filling of area codes when a requested/desired voice or text communication is initiated without the area code while the mobile communication device is outside of its home-base area code toll area; (3) Enhanced editing functionality for applications on mobile computing devices; (4) Automatic toggle from manual texting mode to voice-to-text based communication mode on detection of high velocity movement of the mobile communication device; and (5) Enhanced e-mail notification system providing advanced e-mail notification via (sender or recipient directed) texting to a mobile communication device. Utilizing monolithic 3D IC technology described herein and in related application Ser. Nos. 12/903,862, 12/903,847, 12/904,103 and 13/041,405 significant power and cost could be saved. Most of the elements in MCD15600could be integrated in one 3D IC. Some of the MCD15600elements may be logic functions which could utilize monolithic 3D transistors such as, for example, RCAT or Gate-Last. Some of the MCD15600elements are storage devices and could be integrated on a 3D non-volatile memory device, such as, for example, 3D NAND or 3D RRAM, or volatile memory such as, for example, 3D DRAM or SRAM formed from RCAT or gate-last transistors, as been described herein. Storage 15622 elements formed in monolithic 3D could be integrated on top or under a logic layer to reduce power and space. Keyboard15617could be integrated as a touch screen or combination of image sensor and some light projection and could utilize structures described in some of the above mentioned related applications. The Network Comm Interface15625could utilize another layer of silicon optimized for RF and gigahertz speed analog circuits or even may be integrated on substrates, such as GaN, that may be a better fit for such circuits. As more and more transistors might be integrated to achieve a high complexity 3D IC system there might be a need to use some embodiments of the invention such as what were called repair and redundancy so to achieve good product yield. Some of the system elements including non-mobile elements, such as the 3rd Party Server15638, might also make use of some embodiments of the 3D IC inventions including repair and redundancy to achieve good product yield for high complexity and large integration. Such large integration may reduce power and cost of the end product which is most attractive and most desired by the system end-use customers. Some embodiments of the 3D IC invention could be used to integrate many of the MCD15600blocks or elements into one or a few devices. As various blocks get tightly integrated, much of the power required to transfer signals between these elements may be reduced and similarly costs associated with these connections may be saved. Form factor may be compacted as the space associated with the individual substrate and the associated connections may be reduced by use of some embodiments of the 3D IC invention. For mobile device these may be very important competitive advantages. Some of these blocks might be better processed in different process flow or wafer fab location. For example the DSP/CPU15602is a logic function that might use a logic process flow while the storage15622might better be done using a NAND Flash technology process flow or wafer fab. An important advantage of some of the embodiments of the monolithic 3D inventions may be to allow some of the layers in the 3D structure to be processed using a logic process flow while another layer in the 3D structure might utilize a memory process flow, and then some other function the modems of the GPS15624might use a high speed analog process flow or wafer fab. As those diverse functions may be structured in one device onto many different layers, these diverse functions could be very effectively and densely vertically interconnected. Some embodiments of the invention may include alternative techniques to build IC (Integrated Circuit) devices including techniques and methods to construct 3D IC systems. Some embodiments of the invention may enable device solutions with far less power consumption than prior art, or with more functionality in a smaller physical footprint. These device solutions could be very useful for the growing application of Autonomous in vivo Electronic Medical (AEM) devices and AEM systems such as ingestible “camera pills,” implantable insulin dispensers, implantable heart monitoring and stimulating devices, and the like. One such ingestible “camera pill” is the Philips' remote control “iPill”. For example, incorporating the 3D IC semiconductor devices according to some embodiments of the invention within these AEM devices and systems could provide superior autonomous units that could operate much more effectively and for a much longer time than with prior art technology. Sophisticated AEM systems may be greatly enhanced by complex electronics with limited power budget. The 3D technology described in many of the embodiments of the invention would allow the construction of a low power high complexity AEM system. For example it would be possible to integrate into a small form function a complex logic circuit with high density high speed memory utilizing some of the 3D DRAM embodiments herein and to add some non-volatile 3D NAND charge trap or RRAM described in embodiments herein. Also in another application Ser. No. 12/903,862 filled by some of the inventors and assigned to the same assignee a 3D micro display and a 3D image sensor are presented. Integrating one or both to complex logic and or memory could be very effective for retinal implants. Additional AEM systems could be customized to some specific market applications. Utilizing 3D programmable logic or 3D gate array as has been described in some embodiments herein could be very effective. The need to reduce power to allow effective use of battery and also the light weight and small form factor derived by highly integrating functions with low waste of interconnect and substrate could benefit from the redundancy and repair idea of the 3D monolithic technology as has been presented in some of the inventive embodiments herein. This unique technology could enable disposable AEM devices that would be at a lower cost to produce and/or would require lower power to operate and/or would require lower size and/or lighter to carry and combination of these features to form a competitive or desirable AEM system. 3D ICs according to some embodiments of the invention could also enable electronic and semiconductor devices with a much higher performance due to the shorter interconnect as well as semiconductor devices with far more complexity via multiple levels of logic and providing the ability to repair or use redundancy. The achievable complexity of the semiconductor devices according to some embodiments of the invention could far exceed what may be practical with the prior art technology. These advantages could lead to more powerful computer systems and improved systems that have embedded computers. Some embodiments of the invention may also enable the design of state of the art AEM systems at a greatly reduced non-recurring engineering (NRE) cost by the use of high density 3D FPGAs or various forms of 3D array based ICs with reduced custom masks as described in some inventive embodiments herein. These systems could be deployed in many products and in many market segments. Reduction of the NRE may enable new product family or application development and deployment early in the product lifecycle by lowering the risk of upfront investment prior to a market being developed. The above advantages may also be provided by various mixes such as reduced NRE using generic masks for layers of logic and other generic masks for layers of memories and building a very complex system using the repair technology to overcome the inherent yield limitation. Another form of mix could be building a 3D FPGA and add on it 3D layers of customizable logic and memory resulting in an end system that may have field programmable logic on top of the factory customized logic. There may be many ways to mix the many innovative elements herein to form a 3D IC to support the needs of an end system, including using multiple devices wherein more than one device incorporates elements of embodiments of the invention. An end system could benefit from memory devices utilizing embodiments of the invention of 3D memory together with high performance 3D FPGA together with high density 3D logic and so forth. Using devices that can use one or multiple elements according to some embodiments of the invention may allow for better performance or lower power and other illustrative advantages resulting from the use of some embodiments of the invention to provide the end system with a competitive edge. Such end system could be electronic based products or other types of medical systems that may include some level of embedded electronics, such as, for example, AEM devices that combine multi-function monitoring, multi drug dispensing, sophisticated power-saving telemetrics for communication, monitoring and control, etc. AEM devices have been in use since the1980sand have become part of our lives, moderating illnesses and prolonging life. A typical AEM system may include a logic processor, signal processor, volatile and non-volatile memory, specialized chemical, optical, and other sensors, specialized drug reservoirs and release mechanisms, specialized electrical excitation mechanisms, and radio frequency (RF) or acoustic receivers/transmitters. It may also include additional electronic and non-electronic sub-systems that may require additional processing resources to monitor and control, such as propulsion systems, immobilization systems, heating, ablation, etc. Prior art such as U.S. Pat. No. 7,567,841 or U.S. Pat. No. 7,365,594 provide example descriptions of such autonomous in-vivo electronic medical devices and systems. It is understood that the use of specific component, device and/or parameter names described herein are for example only and not meant to imply any limitations on the invention. The invention may thus be implemented with different nomenclature/terminology utilized to describe the components/devices/parameters herein, without limitation. Each term utilized herein is to be given its broadest interpretation given the context in which that term is utilized. For example, as utilized herein, the following are generally defined: AEM device: An Autonomous in-vivo Electronic Medical (AEM) device19100, illustrated inFIG.74, may include a sensing subsystem19150, a processor19102, a communication controller19120, an antenna subsystem19124, and a power subsystem19170, all within a biologically-benign encapsulation19101. Other subsystems an AEM may include some or all of therapy subsystem19160, propulsion subsystem19130, immobilization system19132, an identifier element (ID)19122that uniquely identifies every instance of an AEM device, one or more signal processors19104, program memory19110, data memory19112and non-volatile storage19114. The sensing subsystem19150may include one or more of optical sensors, imaging cameras, biological or chemical sensors, as well as gravitational or magnetic ones. The therapy subsystem19160may include one or more of drug reservoirs, drug dispensers, drug refill ports, electrical or magnetic stimulation circuitry, and ablation tools. The power subsystem19170may include a battery and/or an RF induction pickup circuitry that allows remote powering and recharge of the AEM device. The antenna subsystem19124may include one or more antennae, operating either as an array or individually for distinct functions. The unique ID191222can operate through the communication controller19120as illustrated inFIG.74, or independently as an RFID tag. In addition to the above described hardware components of AEM device19100, various features of the described embodiments may be completed/supported via software (or firmware) code or logic stored within program memory19110or other storage (e.g., data memory19112) and executed by processor19102and signal processors19104. Such software may be custom written for the device, or may include standard software components that are commercially available from software vendors. One example of AEM device is a so-called “camera pill” that may be ingested by the patient and capture images of the digestive tract as it is traversed, and transmits the images to external equipment. Because such traversal may take an hour or more, a large number of images may need to be transmitted, possibly depleting its power source before the traversal through the digestive tract is completed. The ability to autonomously perform high quality image comparison and transmit only images with significant changes is important, yet often limited by the compute resources on-board the AEM device. Another example of an AEM device is a retinal implant, which may have severe size limitations in order to minimize the device's interference with vision. Similarly, cochlear implants may also impose strict size limitations. Those size limitations may impose severe constraints on the computing power and functionality available to the AEM device. Many AEM devices may be implanted within the body through surgical procedures, and replacing their power supply may require surgical intervention. There is a strong interest in extending the battery life as much as possible through lowering the power consumption of the AEM device. Utilizing monolithic 3D IC technology described here and in related application Ser. Nos. 12/903,862, 12/903,847, 12/904,103 13/098,997, and 13/041,405 significant power, physical footprint, and cost could be saved. Many of the elements in AEM device19100could be integrated in one 3D IC. Some of these elements are mostly logic functions which could use, for example, RCAT transistors or Gate-Last transistors. Some of the AEM device19100elements may be storage devices and could be integrated on another 3D non-volatile memory device, such as, for example, 3D NAND as has been described herein. Alternatively the storage elements, for example, program memory19110, data memory19112and non-volatile storage19114, could be integrated on top of or under a logic layer or layers to reduce power and space. Communication controller19120could similarly utilize another layer of silicon optimized for RF. Specialized sensors can be integrated on substrates, such as InP or Ge, that may be a better fit for such devices. As more and more transistors might be integrated into high complexity 3D IC systems there might be a need to use elements of the inventions such as what are described herein as repair and redundancy methods and techniques to achieve good product yield. Some of the external systems communication with AEM devices might also make use of some embodiments of the 3D IC invention including repair and redundancy to achieve good product yield for high complexity and large integration. Such large integration may reduce power and cost of the end product which may be attractive to end customers. The 3D IC invention could be used to integrate many of these blocks into one or multiple devices. As various blocks get tightly integrated much of the power required to communicate between these elements may be reduced, and similarly, costs associated with these connections may be saved, as well as the space associated with the individual substrate and the associated connections. For AEM devices these may be very important competitive advantages. Some of these blocks might be better processed in a different process flow and or with a different substrate. For example, processor19102is a logic function that might use a logic process flow while the non-volatile storage19114might better be done using NAND Flash technology. An important advantage of some of the monolithic 3D embodiments of the invention may be to allow some of the layers in the 3D structure to be processed using a logic process flow while others might utilize a memory process flow, and then some other function such as, for example, the communication controller19120might use a high speed analog flow. Additionally, as those functions may be structured in one device on different layers, they could be very effectively be vertically interconnected. To improve the contact resistance of very small scaled contacts, the semiconductor industry employs various metal silicides, such as, for example, cobalt silicide, titanium silicide, tantalum silicide, and nickel silicide. The current advanced CMOS processes, such as, for example, 45 nm, 32 nm, and 22 nm, employ nickel silicides to improve deep submicron source and drain contact resistances. Background information on silicides utilized for contact resistance reduction can be found in “NiSi Salicide Technology for Scaled CMOS,” H. Iwai, et. al., Microelectronic Engineering, 60 (2002), pp 157-169; “Nickel vs. Cobalt Silicide integration for sub-50 nm CMOS”, B. Froment, et. al., IMEC ESS Circuits, 2003; and “65 and 45-nm Devices—an Overview”, D. James, Semicon West, July 2008, ctr_024377. To achieve the lowest nickel silicide contact and source/drain resistances, the nickel on silicon can be heated to about 450° C. Thus it may be desirable to enable low resistances for process flows in this document where the post layer transfer temperature exposures may remain under about 400° C. due to metallization, such as, for example, copper and aluminum, and low-k dielectrics being present. For junction-less transistors (JLTs), in particular, forming contacts can be a challenge. This may be because the doping of JLTs should be kept low (below about 0.5-5×1019/cm3or so) to enable good transistor operation but should be kept high (above about 0.5-5×1019/cm3or so) to enable low contact resistance. A technique to obtain low contact resistance at lower doping values may therefore be desirable. One such embodiment of the invention may be by utilizing silicides with different work-functions for n type JLTs than for p type JLTs to obtain low resistance at lower doping values. For example, high work function materials, including, such materials as, Palladium silicide, may be used to make contact to p-type JLTs and lower work-function materials, including, such as, Erbium silicide, may be used to make contact to n-type JLTs. These types of approaches are not generally used in the manufacturing of planar inversion-mode MOSFETs. This may be due to separate process steps and increased cost for forming separate contacts to n type and p type transistors on the same device layer. However, for 3D integrated approaches where p-type JLTs may be stacked above n-type JLTs and vice versa, it can be not costly to form silicides with uniquely optimized work functions for n type and p type transistors. Furthermore, for JLTs where contact resistance may be an issue, the additional cost of using separate silicides for n type and p type transistors on the same device layer may be acceptable. The example process flow shown below may form a Recessed Channel Array Transistor (RCAT) with low contact resistance, but this or similar flows may be applied to other process flows and devices, such as, for example, S-RCAT, JLT, V-groove, JFET, bipolar, and replacement gate flows. A planar n-channel Recessed Channel Array Transistor (RCAT) with metal silicide source & drain contacts suitable for a 3D IC may be constructed. As illustrated inFIG.51A, a P− substrate donor wafer13302may be processed to include wafer sized layers of N+ doping13304, and P− doping13301across the wafer. The N+ doped layer13304may be formed by ion implantation and thermal anneal. In addition, P− doped layer13301may have additional ion implantation and anneal processing to provide a different dopant level than P− substrate donor wafer13302. P− doped layer13301may also have graded P− doping to mitigate transistor performance issues, such as, for example, short channel effects, after the RCAT may be formed. The layer stack may alternatively be formed by successive epitaxially deposited doped silicon layers of P− doping13301and N+ doping13304, or by a combination of epitaxy and implantation. Annealing of implants and doping may utilize optical annealing techniques or types of Rapid Thermal Anneal (RTA or spike) or flash anneal. As illustrated inFIG.51B, a silicon reactive metal, such as, for example, Nickel or Cobalt, may be deposited onto N+ doped layer13304and annealed, utilizing anneal techniques such as, for example, RTA, flash anneal, thermal, or optical, thus forming metal silicide layer13306. The top surface of P− substrate donor wafer13302may be prepared for oxide wafer bonding with a deposition of an oxide to form oxide layer13308. As illustrated inFIG.51C, a layer transfer demarcation plane (shown as dashed line)13399may be formed by hydrogen implantation or other methods as previously described. As illustrated inFIG.51DP− substrate donor wafer13302with layer transfer demarcation plane13399, P− doped layer13301, N+ doped layer13304, metal silicide layer13306, and oxide layer13308may be temporarily bonded to carrier or holder substrate13312with a low temperature process that may facilitate a low temperature release. The carrier or holder substrate13312may be a glass substrate to enable state of the art optical alignment with the acceptor wafer. A temporary bond between the carrier or holder substrate13312and the P− substrate donor wafer13302may be made with a polymeric material, such as, for example, polyimide DuPont HD3007, which can be released at a later step by laser ablation, Ultra-Violet radiation exposure, or thermal decomposition, shown as adhesive layer13314. Alternatively, a temporary bond may be made with uni-polar or bi-polar electrostatic technology such as, for example, the Apache tool from Beam Services Inc. As illustrated inFIG.51E, the portion of the P− substrate donor wafer13302that is below the layer transfer demarcation plane13399may be removed by cleaving or other processes as previously described, such as, for example, ion-cut or other methods. The remaining donor wafer P− doped layer13301may be thinned by chemical mechanical polishing (CMP) so that the P− layer13316may be formed to the desired thickness. Oxide layer13318may be deposited on the exposed surface of P− layer13316. As illustrated inFIG.51F, both the P− substrate donor wafer13302and acceptor substrate13310or wafer may be prepared for wafer bonding as previously described and then low temperature (less than about 400° C.) aligned and oxide to oxide bonded. Acceptor substrate13310, as described previously, may include, for example, transistors, circuitry, metal, such as, for example, aluminum or copper, interconnect wiring, and through layer via metal interconnect strips or pads. The carrier or holder substrate13312may then be released using a low temperature process such as, for example, laser ablation. Oxide layer13318, P− layer13316, N+ doped layer13304, metal silicide layer13306, and oxide layer13308may have been layer transferred to acceptor substrate13310. The top surface of oxide layer13308may be chemically or mechanically polished. Now RCAT transistors can be formed with low temperature (less than about 400° C.) processing and aligned to the acceptor substrate13310alignment marks (not shown). As illustrated inFIG.51G, the transistor isolation regions13322may be formed by mask defining and then plasma/RIE etching oxide layer13308, metal silicide layer13306, N+ doped layer13304, and P− layer13316to the top of oxide layer13318. A low-temperature gap fill oxide may be deposited and chemically mechanically polished, with the oxide remaining in isolation regions13322. Then the recessed channel13323may be mask defined and etched. The recessed channel surfaces and edges may be smoothed by wet chemical or plasma/RIE etching techniques to mitigate high field effects. These process steps may form oxide regions13324, metal silicide source and drain regions13326, N+ source and drain regions13328and P− channel region13330. As illustrated inFIG.51H, a gate dielectric13332may be formed and a gate metal material may be deposited. The gate dielectric13332may be an atomic layer deposited (ALD) gate dielectric that may be paired with a work function specific gate metal in the industry standard high k metal gate process schemes described previously. Or the gate dielectric13332may be formed with a low temperature oxide deposition or low temperature microwave plasma oxidation of the silicon surfaces and then a gate material such as, for example, tungsten or aluminum, may be deposited. The gate material may be chemically mechanically polished, and the gate area defined by masking and etching, thus forming gate electrode13334. As illustrated inFIG.51I, a low temperature thick oxide13338may be deposited and source, gate, and drain contacts, and through layer via (not shown) openings may be masked and etched preparing the transistors to be connected via metallization. Thus gate contact13342may connect to gate electrode13334, and source & drain contacts13336may connect to metal silicide source and drain regions13326. Persons of ordinary skill in the art will appreciate that the illustrations inFIG.51AthroughFIG.51Iare exemplary only and are not drawn to scale. Such skilled persons will further appreciate that many variations may be possible such as, for example, the temporary carrier substrate may be replaced by a carrier wafer and a permanently bonded carrier wafer flow such as described inFIG.40may be employed. Many other modifications within the scope of illustrated embodiments of the invention will suggest themselves to such skilled persons after reading this specification. Thus the invention is to be limited only by the appended claims. With the high density of layer to layer interconnection and the formation of memory devices & transistors that are enabled by embodiments in this document, novel FPGA (Field Programmable Gate Array) programming architectures and devices may be employed to create cost, area, and performance efficient 3D FPGAs. The pass transistor, or switch, and the memory device that may control the ON or OFF state of the pass transistor may reside in separate layers and may be connected by through layer vias (TLVs) to each other and the routing network metal lines, or the pass transistor and memory devices may reside in the same layer and TLVs may be utilized to connect to the network metal lines. As illustrated inFIG.52A, acceptor wafer13400may be processed to include logic circuits, analog circuits, and other devices, with metal interconnection and a metal configuration network to form the base FPGA. Acceptor wafer13400may also include configuration elements such as, for example, switches, pass transistors, memory elements, programming transistors, and may contain a foundation layer or layers as described previously. As illustrated inFIG.52B, donor wafer13402may be preprocessed with a layer or layers of pass transistors or switches or partially formed pass transistors or switches. The pass transistors may be constructed utilizing the partial transistor process flows described previously, such as, for example, RCAT or JLT or others, or may utilize the replacement gate techniques, such as, for example, CMOS or CMOS N over P or gate array, with or without a carrier wafer, as described previously. Donor wafer13402and acceptor substrate13400and associated surfaces may be prepared for wafer bonding as previously described. As illustrated inFIG.52C, donor wafer13402and acceptor substrate13400may be bonded at a low temperature (less than about 400° C.) and a portion of donor wafer13402may be removed by cleaving and polishing, or other processes as previously described, such as, for example, ion-cut or other methods, thus forming the remaining pass transistor layer13402′. Now transistors or portions of transistors may be formed or completed and may be aligned to the acceptor substrate13400alignment marks (not shown) as described previously. Thru layer vias (TLVs)13410may be formed as described previously and as well as interconnect and dielectric layers. Thus acceptor substrate with pass transistors13400A may be formed, which may include acceptor substrate13400, pass transistor layer13402′, and TLVs13410. As illustrated inFIG.52D, memory element donor wafer13404may be preprocessed with a layer or layers of memory elements or partially formed memory elements. The memory elements may be constructed utilizing the partial memory process flows described previously, such as, for example, RCAT DRAM, JLT, or others, or may utilize the replacement gate techniques, such as, for example, CMOS gate array to form SRAM elements, with or without a carrier wafer, as described previously, or may be constructed with non-volatile memory, such as, for example, R-RAM or FG Flash as described previously. Memory element donor wafer13404and acceptor substrate with pass transistors13400A and associated surfaces may be prepared for wafer bonding as previously described. As illustrated inFIG.52E, memory element donor wafer13404and acceptor substrate with pass transistors13400A may be bonded at a low temperature (less than about 400° C.) and a portion of memory element donor wafer13404may be removed by cleaving and polishing, or other processes as previously described, such as, for example, ion-cut or other methods, thus forming the remaining memory element layer13404′. Now memory elements & transistors or portions of memory elements & transistors may be formed or completed and may be aligned to the acceptor substrate with pass transistors13400A alignment marks (not shown) as described previously. Memory to switch through layer vias13420and memory to acceptor through layer vias13430as well as interconnect and dielectric layers may be formed as described previously. Thus acceptor substrate with pass transistors and memory elements13400B may be formed, which may include acceptor substrate13400, pass transistor layer13402′, TLVs13410, memory to switch through layer vias13420, memory to acceptor through layer vias13430, and memory element layer13404′. As illustrated inFIG.52F, a simple schematic of illustrative elements of acceptor substrate with pass transistors and memory elements13400B may be shown. An exemplary memory element13440residing in memory element layer13404′ may be electrically coupled to exemplary pass transistor gate13442, residing in pass transistor layer13402′, with memory to switch through layer vias13420. The pass transistor source13444, residing in pass transistor layer13402′, may be electrically coupled to FPGA configuration network metal line13446, residing in acceptor substrate13400, with TLV13410A. The pass transistor drain13445, residing in pass transistor layer13402′, may be electrically coupled to FPGA configuration network metal line13447, residing in acceptor substrate13400, with TLV13410B. The memory element13440may be programmed with signals from off chip, or above, within, or below the memory element layer13404′. The memory element13440may also include an inverter configuration, wherein one memory cell such as, for example, a FG Flash cell, may couple the gate of the pass transistor to power supply Vcc if turned on, and another FG Flash device may couple the gate of the pass transistor to ground if turned on. Thus, FPGA configuration network metal line13446, which may be carrying the output signal from a logic element in acceptor substrate13400, may be electrically coupled to FPGA configuration network metal line13447, which may route to the input of a logic element elsewhere in acceptor substrate13400. Persons of ordinary skill in the art will appreciate that the illustrations inFIG.52AthroughFIG.52Fare exemplary only and are not drawn to scale. Such skilled persons will further appreciate that many variations may be possible such as, for example, the memory element layer13404′ may be constructed below pass transistor layer13402′. Additionally, the pass transistor layer13402′ may include control and logic circuitry in addition to the pass transistors or switches. Moreover, the memory element layer13404′ may comprise control and logic circuitry in addition to the memory elements. Further, the pass transistor element may instead be a transmission gate, or may be an active drive type switch. Many other modifications within the scope of the illustrated embodiments of the invention will suggest themselves to such skilled persons after reading this specification. Thus the invention is to be limited only by the appended claims. The pass transistor, or switch, and the memory device that controls the ON or OFF state of the pass transistor may reside in the same layer and TLVs may be utilized to connect to the network metal lines. As illustrated inFIG.53A, acceptor substrate13500or wafer may be processed to include logic circuits, analog circuits, and other devices, with metal interconnection, such as copper or aluminum wiring, and a metal configuration network to form the base FPGA. Acceptor substrate13500may also include configuration elements such as, for example, switches, pass transistors, memory elements, programming transistors, and may contain a foundation layer or layers as described previously. As illustrated inFIG.53B, donor wafer13502may be preprocessed with a layer or layers of pass transistors or switches or partially formed pass transistors or switches. The pass transistors may be constructed utilizing the partial transistor process flows described previously, such as, for example, RCAT or JLT or others, or may utilize the replacement gate techniques, such as, for example, CMOS or CMOS N over P or CMOS gate array, with or without a carrier wafer, as described previously. Donor wafer13502may be preprocessed with a layer or layers of memory elements or partially formed memory elements. The memory elements may be constructed utilizing the partial memory process flows described previously, such as, for example, RCAT DRAM or others, or may utilize the replacement gate techniques, such as, for example, CMOS gate array to form SRAM elements, with or without a carrier wafer, as described previously. The memory elements may be formed simultaneously with the pass transistor, for example, such as, for example, by utilizing a CMOS gate array replacement gate process where a CMOS pass transistor and SRAM memory element, such as a 6-transistor cell, may be formed, or an RCAT pass transistor formed with an RCAT DRAM memory. Donor wafer13502and acceptor substrate13500and associated surfaces may be prepared for wafer bonding as previously described. As illustrated inFIG.53C, donor wafer13502and acceptor substrate13500may be bonded at a low temperature (less than about 400° C.) and a portion of donor wafer13502may be removed by cleaving and polishing, or other processes as previously described, such as, for example, ion-cut or other methods, thus forming the remaining pass transistor & memory layer13502′. Now transistors or portions of transistors and memory elements may be formed or completed and may be aligned to the acceptor substrate13500alignment marks (not shown) as described previously. Thru layer vias (TLVs)13510may be formed as described previously. Thus acceptor substrate with pass transistors and memory elements13500A may be formed, which may include acceptor substrate13500, pass transistor & memory element layer13502′, and TLVs13510. It may be desirable to construct 2DICs with regions or 3DICs with layers or strata that may be of dissimilar materials, such as, for example, mono-crystalline silicon based state of the art (SOA) CMOS circuits integrated with, on a 2DIC wafer or integrated in a 3DIC stack, InP optoelectronic circuits, such as, for example, sensors, imagers, displays. These dissimilar materials may include substantially different crystal materials, for example, mono-crystalline silicon and InP. This heterogeneous integration has traditionally been difficult and may result from the substrate differences. The SOA CMOS circuits may be typically constructed at state of the art wafer fabs on large diameter, such as 300 mm, silicon wafers, and the desired SOA InP technology may be made on 2 to 4 inch diameter InP wafers at a much older wafer fab. FIG.75illustrates an embodiment of the invention wherein sub-threshold circuits may be stacked above or below a logic chip layer. The 3DIC illustrated inFIG.75may include input/output interconnect19408, such as, for example, solder bumps and a packaging substrate19402, logic layer19406, and sub-threshold circuit layer19404. The 3DIC may place logic layer19406above sub-threshold circuit layer19404and they may be connected with through layer vias (TLVs) as described elsewhere herein. Alternatively, the logic and sub-threshold layers may be swapped in position, for example, logic layer19406may be a sub-threshold circuit layer and sub-threshold circuit layer19404may be a logic layer. The sub-threshold circuit layer19404may include repeaters of a chip with level shifting of voltages done before and after each repeater stage or before and after some or all of the repeater stages in a certain path are traversed. Alternatively, the sub-threshold circuit layer may be used for SRAM. Alternatively, the sub-threshold circuit layer may be used for some part of the clock distribution, such as, for example, the last set of buffers driving latches in a clock distribution. Although the term sub-threshold is used for describing elements inFIG.75, it will be obvious to one skilled in the art that similar approaches may be used when supply voltage for the stacked layers is slightly above the threshold voltage values and may be utilized to increase voltage toward the end of a clock cycle for a better latch. In addition, the sub-threshold circuit layer stacked above or below the logic layer may include optimized transistors that may have lower capacitance, for example, if it is used for clock distribution purposes. FIG.76illustrates an embodiment of the invention, wherein monolithic 3D DRAM constructed with lithography steps shared among multiple memory layers may be stacked above or below a logic chip. DRAM, as well as SRAM and floating body DRAM, may be considered volatile memory, whereby the memory state may be substantially lost when supply power is removed. Monolithic 3D DRAM constructed with lithography steps shared among multiple memory layers (henceforth called M3DDRAM-LSSAMML) could be constructed using techniques, for example, described in co-pending published patent application 2011/0121366 (FIG.98A-HtoFIG.100A-L). One configuration for 3D stack M3DDRAM-LSSAMML and logic19710may include logic chip19704, M3DDRAM-LSSAMML chip19706, solder bumps19708, and packaging substrate19702. M3DDRAM-LSSAMML chip19706may be placed above logic chip19704, and logic chip19704may be coupled to packaging substrate19702via solder bumps19708. A portion of or substantially the entirety of the logic chip19704and the M3DDRAM-LSSAMML chip19706may be processed separately on different wafers and then stacked atop each other using, for example, through-silicon via (TSV) stacking technology. This stacking may be done at the wafer-level or at the die-level or with a combination. Logic chip19704and the M3DDRAM-LSSAMML chip19706may be constructed in a monocrystalline layer or layers respectively. Another configuration for 3D stack M3DDRAM-LSSAMML and logic19720may include logic chip19716, M3DDRAM-LSSAMML chip19714, solder bumps19718and packaging substrate19712. Logic chip19716may be placed above M3DDRAM-LSSAMML chip19714, and M3DDRAM-LSSAMML chip19714may be coupled to packaging substrate19712via solder bumps19718. A portion of or substantially the entirety of the logic chip19716and the M3DDRAM-LSSAMML chip19714may be processed separately on different wafers and then stacked atop each other using, for example, through-silicon via (TSV) stacking technology. This stacking may be done at the wafer-level or at the die-level or with a combination. The transistors in the monocrystalline layer or layers may be horizontally oriented, i.e., current flowing in substantially the horizontal direction in transistor channels, substantially between drain and source, which may be parallel to the largest face of the substrate or wafer. The source and drain of the horizontally oriented transistors may be within the same monocrystalline layer. A transferred monocrystalline layer may have a thickness of less than about 150 nm. FIG.77A-Gillustrates an embodiment of the invention, wherein logic circuits and logic regions, which may be constructed in a monocrystalline layer, may be monolithically stacked with monolithic 3D DRAM constructed with lithography steps shared among multiple memory layers (M3DDRAM-LSSAMML), the memory layers or memory regions may be constructed in a monocrystalline layer or layers. The process flow for the silicon chip may include the following steps that may be in sequence from Step (1) to Step (5). When the same reference numbers are used in different drawing figures (amongFIG.77A-G), they may be used to indicate analogous, similar or identical structures to enhance the understanding of the invention by clarifying the relationships between the structures and embodiments presented in the various diagrams—particularly in relating analogous, similar or identical functionality to different physical structures.Step (1): This may be illustrated withFIG.77A-C.FIG.77Aillustrates a three-dimensional view of an exemplary M3DDRAM-LSSAMML that may be constructed using techniques described in patent application 2011/0121366 (FIG.98A-HtoFIG.100A-L).FIG.77Billustrates a cross-sectional view along the II direction ofFIG.77AwhileFIG.77Cillustrates a cross-sectional view along the III direction ofFIG.77A. The legend ofFIG.77A-Cmay include gate dielectric19802, conductive contact19804, silicon dioxide19806(nearly transparent for illustrative clarity), gate electrode19808, n+ doped silicon19810, silicon dioxide19812, and conductive bit lines19814. The conductive bit lines19814may include metals, such as copper or aluminum, in their construction. The M3DDRAM-LSSAMML may be built on top of and coupled with vertical connections to peripheral circuits19800as described in patent application 2011/0092030. The DRAM may operate using the floating body effect. Further details of this constructed M3DDRAM-LSSAMML are provided in patent application 2011/0121366 (FIG.98A-HtoFIG.100A-L).Step (2): This may be illustrated withFIG.77D. Activated p Silicon layer19816and activated n+ Silicon layer19818may be transferred atop the structure shown inFIG.77Ausing a layer transfer technique, such as, for example, ion-cut. P Silicon layer19816and n+ Silicon layer19818may be constructed from monocrystalline silicon. Further details of layer transfer techniques and procedures are provided in patent application 2011/0121366. A transferred monocrystalline layer, such as silicon layer19818, may have a thickness of less than about 150 nm.Step (3): This may be illustrated withFIG.77E. The p Silicon layer19816and the n+ Silicon layer19818that were shown inFIG.77Dmay be lithographically defined and then etched to form monocrystalline semiconductor regions including p Silicon regions19820and n+ Silicon regions19822. Silicon dioxide19824(nearly transparent for illustrative clarity) may be deposited and then planarized for dielectric isolation amongst adjacent monocrystalline semiconductor regions.Step (4): This may be illustrated withFIG.77F. The p Silicon regions19820and the n+ Silicon regions19822ofFIG.77Emay be lithographically defined and etched with a carefully tuned etch recipe, thus forming a recessed channel structure such as shown inFIG.77Fand may include n+ source and drain Silicon regions19826, p channel Silicon regions19828, and oxide regions19830(nearly transparent for illustrative clarity). Clean processes may then be used to produce a smooth surface in the recessed channel.Step (5): This may be illustrated withFIG.77G. A low temperature (less than about 400° C.) gate dielectric and gate electrode, such as hafnium oxide and TiAlN respectively, may be deposited into the etched regions inFIG.77F. A chemical mechanical polish process may be used to planarize the top of the gate stack. Then a lithography and etch process may be used to form the pattern shown inFIG.77G, thus forming recessed channel transistors that may include gate dielectric regions19836, gate electrode regions19832, silicon dioxide regions19840(nearly transparent for illustrative clarity), n+ Silicon source and drain regions19834, and p Silicon channel and body regions19838. A recessed channel transistor for logic circuits and logic regions may be formed monolithically atop a M3DDRAM-LSSAMML using the procedure shown in Step (1) to Step (5). The processes described in Step (1) to Step (5) do not expose the M3DDRAM-LSSAMML, and its associated metal bit lines19814, to temperatures greater than about 400° C. Persons of ordinary skill in the art will appreciate that the illustrations inFIG.77AthroughFIG.77Gare exemplary only and are not drawn to scale. Such skilled persons will further appreciate that many variations may be possible such as, for example, the recessed channels etched inFIG.77Fmay instead be formed before p Silicon layer19816and n+ Silicon layer19818may be etched to form the dielectric isolation and p Silicon regions19820and n+ Silicon regions19822. Moreover, various types of logic transistors can be stacked atop the M3DDRAM-LSSAMML without exposing the M3DDRAM-LSSAMML to temperatures greater than about 400° C., such as, for example, junction-less transistors, dopant segregated Schottky source-drain transistors, V-groove transistors, and replacement gate transistors. This is possible using procedures described in patent application 2011/0121366 (FIG.98A-HtoFIG.100A-L). The memory regions may have horizontally oriented transistors and vertical connections between the memory and logic layers may have a radius of less than about 100 nm. These vertical connections may be vias, such as, for example, thru layer vias (TLVs), through the monocrystalline silicon layers connecting the stacked layers, for example, logic circuit regions within one monocrystalline layer to memory regions within another monocrystalline layer. Additional (eg. third or fourth) monocrystalline layers that may have memory regions may be added to the stack. Decoders and other driver circuits of said memory may be part of the stacked logic circuit layer or logic circuit regions. The memory regions may have replacement gate transistors, recessed channel transistors (RCATs), side-gated transistors, junction-less transistors or dopant-segregated Schottky Source-Drain transistors, which may be constructed using techniques described in patent applications 20110121366 and 13/099,010. Many other modifications within the scope of the illustrated embodiments of the invention will suggest themselves to such skilled persons after reading this specification. Thus the invention is to be limited only by the appended claims. FIG.78illustrates an embodiment of the invention wherein different configurations for stacking embedded memory with logic circuits and logic regions may be realized. One stack configuration19910may include embedded memory solution19906made in a monocrystalline layer monolithically stacked atop the logic circuits19904made in a monocrystalline layer using monolithic 3D technologies and vertical connections described in patent applications 20110121366 and 13/099,010. Logic circuits19904may include metal layer or layers which may include metals such as copper or aluminum. Stack configuration19910may include input/output interconnect19908, such as, for example, solder bumps and a packaging substrate19902. Another stack configuration19920may include the logic circuits19916monolithically stacked atop the embedded memory solution19914using monolithic 3D technologies described in patent applications 20110121366 and 13/099,010. Embedded memory solution19914may include metal layer or layers which may include metals such as copper or aluminum. Stack configuration19920may include an input/output interconnect19918, such as, for example, solder bumps and a packaging substrate19912. The embedded memory solutions19906and19914may be a volatile memory, for example, SRAM. In this case, the transistors in SRAM blocks associated with embedded memory solutions19906and19914may be optimized differently than the transistors in logic circuits19904and19916, and may, for example, have different threshold voltages, channel lengths and/or other parameters. The embedded memory solutions19906and19914, if constructed, for example, as SRAM, may have, for example, just one device layer with 6 or 8 transistor SRAM. Alternatively, the embedded memory solutions19906and19914may have two device layers with pMOS and nMOS transistors of the SRAM constructed in monolithically stacked device layers using techniques described patent applications 20110121366 and 13/099,010. The transistors in the monocrystalline layer or layers may be horizontally oriented, i.e., current flowing in substantially the horizontal direction in transistor channels, substantially between drain and source, which may be parallel to the largest face of the substrate or wafer. The source and drain of the horizontally oriented transistors may be within the same monocrystalline layer. A transferred monocrystalline layer, such as logic circuits19904, may have a thickness of less than about 150 nm. Persons of ordinary skill in the art will appreciate that the illustrations inFIG.78are exemplary only and are not drawn to scale. Such skilled persons will further appreciate that many variations may be possible such as, for example, the embedded memory solutions19906and19914, if constructed, for example, as SRAM, may be built with three monolithically stacked device layers for the SRAM with architectures similar to “The revolutionary and truly 3-dimensional 25F2 SRAM technology with the smallest S3 stacked single-crystal Si) cell, 0.16 um2, and SSTFT (stacked single-crystal thin film transistor) for ultra high density SRAM”, Symposium on VLSI Technology, 2004 by Soon-Moon Jung, et al. but implemented with technologies described in patent applications 20110121366 and 13/099,010. Moreover, the embedded memory solutions19906and19914may be embedded DRAM constructed with stacked capacitors and transistors. Further, the embedded memory solutions19906and19914may be embedded DRAM constructed with trench capacitors and transistors. Moreover, the embedded memory solutions19906and19914may be capacitor-less floating-body RAM. Further, the embedded memory solutions19906and19914may be a resistive memory, such as RRAM, Phase Change Memory or MRAM. Furthermore, the embedded memory solutions19906and19914may be a thyristor RAM. Moreover, the embedded memory solutions19906and19914may be a flash memory. Furthermore, embedded memory solutions19906and19914may have a different number of metal layers and different sizes of metal layers compared to those in logic circuits19904and19916. This is because memory circuits typically perform well with fewer numbers of metal layers (compared to logic circuits). Many other modifications within the scope of the illustrated embodiments of the invention described herein will suggest themselves to such skilled persons after reading this specification. Thus the invention is to be limited only by the appended claims. Many of the configurations described withFIG.78may represent an integrated device that may have a first monocrystalline layer that may have logic circuit layers and/or regions and a second monolithically stacked monocrystalline layer that may have memory regions. The memory regions may have horizontally oriented transistors and vertical connections between the memory and logic layers may have a radius of less than 100 nm. These vertical connections may be vias, such as, for example, thru layer vias (TLVs), through the monocrystalline silicon layers connecting the stacked layers, for example, logic circuit regions within one monocrystalline layer to memory regions within another monocrystalline layer. Additional (eg. third or fourth) monocrystalline layers that may have memory regions may be added to the stack. Decoders and other driver circuits of said memory may be part of the stacked logic circuit layer or logic circuit regions. The memory regions may have replacement gate transistors, recessed channel transistors (RCATs), side-gated transistors, junction-less transistors or dopant-segregated Schottky Source-Drain transistors, which may be constructed using techniques described in patent applications 20110121366 and 13/099,010. FIG.79A-Cillustrates an embodiment of the invention, wherein a horizontally-oriented monolithic 3D DRAM array may be constructed and may have a capacitor in series with a transistor selector. No mask may utilized on a “per-memory-layer” basis for the monolithic 3D DRAM shown inFIG.79A-C, and substantially all other masks may be shared among different layers. The process flow may include the following steps which may be in sequence from Step (A) to Step (H). When the same reference numbers are used in different drawing figures (amongFIG.79A-C), the reference numbers may be used to indicate analogous, similar or identical structures to enhance the understanding of the invention by clarifying the relationships between the structures and embodiments presented in the various diagrams—particularly in relating analogous, similar or identical functionality to different physical structures.Step (A): Peripheral circuits20002, which may include high temperature wiring, made with metals such as, for example, tungsten, and which may include logic circuit regions, may be constructed. Oxide layer (eventually part of oxide layer20011) may be deposited above peripheral circuits20002.Step (B): N+ Silicon wafer may have an oxide layer (eventually part of oxide layer20011) grown or deposited above it. Hydrogen may be implanted into the n+ Silicon wafer to a certain depth indicated by hydrogen plane. Alternatively, some other atomic species, such as Helium, may be (co-)implanted. Thus, top layer may be formed. The bottom layer may include the peripheral circuits20002with oxide layer. The top layer may be flipped and bonded to the bottom layer using oxide-to-oxide bonding to form top and bottom stack.Step (C): The top and bottom stack may be cleaved at the hydrogen plane using methods including, for example, a thermal anneal or a sideways mechanical force. A CMP process may be conducted. Thus n+ Silicon layer may be formed. A layer of silicon oxide may be deposited atop the n+ Silicon layer. At the end of this step, a single-crystal n+ Silicon layer may exist atop the peripheral circuits20002, and this has been achieved using layer-transfer techniques.Step (D): Using methods similar to Step (B) and (C), multiple n+ silicon layers20028(now including n+ Silicon layer) may be formed with associated silicon oxide layers20026.Step (E): Lithography and etch processes may then be utilized to make a structure as shown in the figure. The etch of multiple n+ silicon layers and associated silicon oxide layers may stop on oxide layer or may extend into and etch a portion of oxide layer (not shown). Thus exemplary patterned oxide regions20026and patterned n+ silicon regions20028may be formed.Step (F): A gate dielectric, such as, for example, silicon dioxide or hafnium oxides, and gate electrode, such as, for example, doped amorphous silicon or TiALN, may be deposited and a CMP may be done to planarize the gate stack layers. Lithography and etch may be utilized to define the gate regions, thus gate dielectric regions20032and gate electrode regions20030may be formed.Step (G):FIG.79Aillustrates the structure after Step (G). A trench, for example two of which may be placed as shown inFIG.79A, may be formed by lithography, etch and clean processes. A high dielectric constant material and then a metal electrode material may be deposited and polished with CMP. The metal electrode material may substantially fill the trenches. Thus high dielectric constant regions20038and metal electrode regions20036may be formed, which may substantially reside inside the exemplary two trenches. The high dielectric constant regions20038may be include materials such as, for example, hafnium oxide, titanium oxide, niobium oxide, zirconium oxide and any number of other possible materials with dielectric constants greater than or equal to 4. The DRAM capacitors may be defined by having the high dielectric constant regions20038in between the surfaces or edges of metal electrode regions20036and the associated stacks of n+ silicon regions20028.Step (H):FIG.79Billustrates the structure after Step (H). A silicon oxide layer20027may then be deposited and planarized. The silicon oxide layer is shown transparent in the figure for clarity. Bit Lines20040may then be constructed. Contacts may then be made to Bit Lines, Word Lines and Source Lines of the memory array at its edges. Source Line contacts can be made into stair-like structures using techniques described in “Bit Cost Scalable Technology with Punch and Plug Process for Ultra High Density Flash Memory,” VLSI Technology, 2007 IEEE Symposium on, vol., no., pp. 14-15, 12-14 Jun. 2007 by Tanaka, H.; Kido, M.; Yahashi, K.; Oomura, M.; et al., following which contacts can be constructed to them. Formation of stair-like structures for Source Lines could be done in steps prior to Step (H) as well. Vertical connections, for example, with TLVs, may be made to peripheral circuits20002(not shown). FIG.79Cshow cross-sectional views of the exemplary memory array alongFIG.79Bplanes II respectively. Multiple junction-less transistors in series with capacitors constructed of high dielectric constant materials such as high dielectric constant regions20038can be observed inFIG.79C. A procedure for constructing a monolithic 3D DRAM has thus been described, with (1) horizontally-oriented transistors, (2) some of the memory cell control lines—e.g., source-lines SL, constructed of heavily doped silicon and embedded in the memory cell layer, (3) side gates simultaneously deposited over multiple memory layers for transistors, and (4) monocrystalline (or single-crystal) silicon layers obtained by layer transfer techniques such as ion-cut. The transistors in the monocrystalline layer or layers may be horizontally oriented, i.e., current flowing in substantially the horizontal direction in transistor channels, substantially between drain and source, which may be parallel to the largest face of the substrate or wafer. The source and drain of the horizontally oriented transistors may be within the same monocrystalline layer. A transferred monocrystalline layer, such as n+ Silicon layer, may have a thickness of less than about 150 nm. Persons of ordinary skill in the art will appreciate that the illustrations inFIG.79AthroughFIG.79Care exemplary only and are not drawn to scale. Such skilled persons will further appreciate that many variations may be possible such as, for example, layer transfer techniques other than the described hydrogen implant and ion-cut may be utilized. Moreover, whileFIG.79A-FIG.79Cdescribed the procedure for forming a monolithic 3D DRAM with substantially all lithography steps shared among multiple memory layers, alternative procedures could be used. For example, procedures similar to those described inFIG.33A-K,FIG.34A-LandFIG.35A-Fof patent application Ser. No. 13/099,010, now U.S. Pat. No. 8,581,349, may be used to construct a monolithic 3D DRAM. The memory regions may have horizontally oriented transistors and vertical connections between the memory and logic/periphery layers may have a radius of less than 100 nm. These vertical connections may be vias, such as, for example, thru layer vias (TLVs), through the monocrystalline silicon layers connecting the stacked layers, for example, logic circuit regions within one monocrystalline layer to memory regions within another monocrystalline layer. Additional (e.g. third or fourth) monocrystalline layers that may have memory regions may be added to the stack. Decoders and other driver circuits of said memory may be part of the stacked logic circuit layer or logic circuit regions. Many other modifications within the scope of the illustrated embodiments of the invention will suggest themselves to such skilled persons after reading this specification. Thus the invention is to be limited only by the appended claims. Over the past few years, the semiconductor industry has been actively pursuing floating-body RAM technologies as a replacement for conventional capacitor-based DRAM or as a replacement for embedded DRAM/SRAM. In these technologies, charge may be stored in the body region of a transistor instead of having a separate capacitor. This could have several potential advantages, including lower cost due to the lack of a capacitor, easier manufacturing and potentially scalability. There are many device structures, process technologies and operation modes possible for capacitor-less floating-body RAM. Some of these are included in “Floating-body SOI Memory: The Scaling Tournament”, Book Chapter of Semiconductor-On-Insulator Materials for Nanoelectronics Applications, pp. 393-421, Springer Publishers, 2011 by M. Bawedin, S. Cristoloveanu, A. Hubert, K. H. Park and F. Martinez (“Bawedin”). FIG.80shows a prior art illustration of capacitor-based DRAM and capacitor-less floating-body RAM. A capacitor-based DRAM cell20106may be schematically illustrated and may include transistor20102coupled in series with capacitor20104. The transistor20102may serve as a switch for the capacitor20104, and may be ON while storing or reading charge in the capacitor20104, but may be OFF while not performing these operations. One illustrative example capacitor-less floating-body RAM cell20118may include transistor source and drain regions20112, gate dielectric20110, gate electrode20108, buried oxide20116and silicon region20114. Charge may be stored in the transistor body region20120. Various other structures and configurations of floating-body RAM may be possible, and are not illustrated inFIG.80. In many configurations of floating-body RAM, a high (electric) field mechanism such as impact ionization, tunneling or some other phenomenon may be used while writing data to the memory cell. High-field mechanisms may be used while reading data from the memory cell. The capacitor-based DRAM cell20106may often operate at much lower electric fields compared to the floating-body RAM cell20118. FIG.81A-81Billustrates some of the potential challenges associated with possible high field effects in floating-body RAM. The Y axis of the graph shown inFIG.81Amay indicate current flowing through the cell during the write operation, which may, for example, consist substantially of impact ionization current. While impact ionization may be illustrated as the high field effect inFIG.81A, some other high field effect may alternatively be present. The X axis of the graph shown inFIG.81Bmay indicate some voltage applied to the memory cell. While using high field effects to write to the cell, some challenges may arise. At low voltages20220, not enough impact ionization current may be generated while at high voltages20222, the current generated may be exponentially higher and may damage the cell. The device may therefore work only at a narrow range of voltages20224. A challenge of having a device work across a narrow range of voltages is illustrated withFIG.81B. In a memory array, for example, there may be millions or billions of memory cells, and each memory individual cell may have its own range of voltages between which it operates safely. Due to variations across a die or across a wafer, it may not be possible to find a single voltage that works well for substantially all members of a memory array. In the plot shown inFIG.81B, four different memory cells may have their own range of “safe” operating voltages20202,20204,20206and20208. Thus, it may not be possible to define a single voltage that can be used for writing substantially all cells in a memory array. While this example described the scenario with write operation, high field effects may make it potentially difficult to define and utilize a single voltage for reading substantially all cells in a memory array. Solutions to this potential problem may be required. FIG.82illustrates an embodiment of the invention that describes how floating-body RAM chip20310may be managed wherein some memory cells within floating-body RAM chip20310may have been damaged due to mechanisms, such as, for example, high-field effects after multiple write or read cycles. For example, a cell rewritten a billion times may have been damaged more by high field effects than a cell rewritten a million times. As an illustrative example, floating-body RAM chip20310may include nine floating-body RAM blocks,20301,20302,20303,20304,20305,20306,20307,20308and20309. If it is detected, for example, that memory cells in floating-body RAM block20305may have degraded due to high-field effects and that redundancy and error control coding schemes may be unable to correct the error, the data within floating-body RAM block20305may be remapped in part or substantially in its entirety to floating-body RAM block20308. Floating-body RAM block20305may not be used after this remapping event. FIG.83illustrates an embodiment of the invention wherein an exemplary methodology for implementing the bad block management scheme may be described with respect toFIG.82. For example, during a read operation20400, if the number of errors increases beyond a certain threshold20410, an algorithm may be activated. The first step of this algorithm may be to check or analyze the causation or some characteristic of the errors, for example, if the errors may be due to soft-errors or due to reliability issues because of high-field effects. Soft-errors may be transient errors and may not occur again and again in the field, while reliability issues due to high-field effects may occur again and again (in multiple conditions), and may occur in the same field or cell. Testing circuits may be present on the die, or on another die, which may be able to differentiate between soft errors and reliability issues in the field by utilizing the phenomenon or characteristic of the error in the previous sentence or by some other method. If the error may result from floating-body RAM reliability20420, the contents of the block may be mapped and transferred to another block as described with respect toFIG.82and this block may not be reused again20430. Alternatively, the bad block management scheme may use error control coding to correct the bad data20440. As well, if the number of bit errors detected in20410does not cross a threshold, then the methodology may use error control coding to correct the bad data20450. In all cases, the methodology may provide the user data about the error and correction20460. The read operation may end20499. FIG.84illustrates an embodiment of the invention wherein wear leveling techniques and methodology may be utilized in floating body RAM. As an illustrative example, floating-body RAM chip20510may include nine floating-body RAM blocks20501,20502,20503,20504,20505,20506,20507,20508and20509. While writing data to floating-body RAM chip20510, the writes may be controlled and mapped by circuits that may be present on the die, or on another die, such that substantially all floating-body RAM blocks, such as20501-20509, may be exposed to an approximately similar number of write cycles. The leveling metric may utilize the programming voltage, total programming time, or read and disturb stresses to accomplish wear leveling, and the wear leveling may be applied at the cell level, or at a super-block (groups of blocks) level. This wear leveling may avoid the potential problem wherein some blocks may be accessed more frequently than others. This potential problem typically limits the number of times the chip can be written. There are several algorithms used in flash memories and hard disk drives that perform wear leveling. These techniques could be applied to floating-body RAM due to the high field effects which may be involved. Using these wear leveling procedures, the number of times a floating body RAM chip can be rewritten (i.e. its endurance) may improve. FIG.85A-Billustrates an embodiment of the invention wherein incremental step pulse programming techniques and methodology may be utilized for floating-body RAM. The Y axis of the graph shown inFIG.85Amay indicate the voltage used for writing the floating-body RAM cell or array and the X axis of the graph shown inFIG.85Amay indicate time during the writing of a floating-body RAM cell or array. Instead of using a single pulse voltage for writing a floating-body RAM cell or array, multiple write voltage pulses, such as, initial write pulse20602, second write pulse20606and third write pulse20610, may be applied to a floating-body RAM cell or array. Write voltage pulses such as, initial write pulse20602, second write pulse20606and third write pulse20610, may have differing voltage levels and time durations (‘pulse width’), or they may be similar. A “verify” read may be conducted after every write voltage pulse to detect if the memory cell has been successfully written with the previous write voltage pulse. A “verify” read operation may include voltage pulses and current reads. For example, after initial write pulse20602, a “verify” read operation20604may be conducted. If the “verify” read operation20604has determined that the floating-body RAM cell or array has not finished storing the data, a second write pulse20606may be given followed by a second “verify” read operation20608. Second write pulse20606may be of a higher voltage and/or time duration (shown) than that of initial write pulse20602. If the second “verify” read operation20608has determined that the floating-body RAM cell or array has not finished storing the data, a third write pulse20610may be given followed by a third “verify” read operation20612. Third write pulse20610may be of a higher voltage and/or time duration (shown) than that of initial write pulse20602or second write pulse20606. This could continue until a combination of write pulse and verify operations indicate that the bit storage is substantially complete. The potential advantage of incremental step pulse programming schemes may be similar to those described with respect toFIG.80andFIG.81A-81Bas they may tackle the cell variability and other issues, such as effective versus applied write voltages. FIG.85Billustrates an embodiment of the invention wherein an exemplary methodology for implementing a write operation using incremental step pulse programming scheme may be described with respect toFIG.85A. AlthoughFIG.85Billustrates an incremental step pulse programming scheme where subsequent write pulses may have higher voltages, the flow may be general and may apply to cases, for example, wherein subsequent write pulses may have higher time durations. Starting a write operation20620, a write voltage pulse of voltage V1may be given20630to the floating-body RAM cell or array, following which a verify read operation may be conducted20640. If the verify read indicates that the bit of the floating-body RAM cell or array has been written20650satisfactorily, the write operation substantially completes20699. Otherwise, the write voltage pulse magnitude may be increased (+ΔV1shown)20660and further write pulses and verify read pulses may be given20630to the memory cell. This process may repeat until the bit is written satisfactorily. Persons of ordinary skill in the art will appreciate that the illustrations inFIG.85AthroughFIG.85Bare exemplary only and are not drawn to scale. Such skilled persons will further appreciate that many variations may be possible such as, for example, pulses may utilize delivered current rather than measured or effective voltage, or some combination thereof. Moreover, multiple write pulses before a read verify operation may be done. Further, write pulses may have more complex shapes in voltage and time, such as, for example, ramped voltages, soaks or holds, or differing pulse widths. Furthermore, the write pulse may be of positive or negative voltage magnitude and there may be a mixture of unipolar or bipolar pulses within each pulse train. The write pulse or pulses may be between read verify operations. Further, ΔV1may be of polarity to decrease the write program pulse voltage V1magnitude. Moreover, an additional ‘safety’ write pulse may be utilized after the last successful read operation. Further, the verify read operation may utilize a read voltage pulse that may be of differing voltage and time shape than the write pulse, and may have a different polarity than the write pulse. Furthermore, the write pulse may be utilized for verify read purposes. Many other modifications within the scope of the illustrated embodiments of the invention described herein will suggest themselves to such skilled persons after reading this specification. Thus the invention is to be limited only by the appended claims. FIG.86illustrates an embodiment of the invention wherein optimized and possibly different write voltages may be utilized for different dice across a wafer. As an illustrative example, wafer20700may include dice20702,20704,20706,20708,20710,20712,20714,20716,20718,20720,20722and20724. Due to variations in process and device parameters across wafer20700, which may be induced by, for example, manufacturing issues, each die, for example die20702, on wafer20700may suitably operate at its own optimized write voltage. The optimized write voltage for die20702may be different than the optimized write voltage for die20704, and so forth. During, for example, the test phase of wafer20700or individual dice, such as, for example, die20702, tests may be conducted to determine the optimal write voltage for each die. This optimal write voltage may be stored on the floating body RAM die, such as die20702, by using some type of non-volatile memory, such as, for example, metal or oxide fuse-able links, or intentional damage programming of floating-body RAM bits, or may be stored off-die, for example, on a different die within wafer20700. Using an optimal write voltage for each die on a wafer may allow higher-speed, lower-power and more reliable floating-body RAM chips. Persons of ordinary skill in the art will appreciate that the illustrations inFIG.86are exemplary only and are not drawn to scale. Such skilled persons will further appreciate that many variations may be possible such as, for example, whileFIG.86discussed using optimal write voltages for each die on the wafer, each wafer in a wafer lot may have its own optimal write voltage that may be determined, for example, by tests conducted on circuits built on scribe lines of wafer20700, a ‘dummy’ mini-array on wafer20700, or a sample of floating-body RAM dice on wafer20700. Moreover, interpolation or extrapolation of the test results from, such as, for example, scribe line built circuits or floating-body RAM dice, may be utilized to calculate and set the optimized programming voltage for untested dice. For example, optimized write voltages may be determined by testing and measurement of die20702and die20722, and values of write voltages for die20708and die20716may be an interpolation calculation, such as, for example, to a linear scale. Many other modifications within the scope of the illustrated embodiments of the invention described herein will suggest themselves to such skilled persons after reading this specification. Thus the invention is to be limited only by the appended claims. FIG.87illustrates an embodiment of the invention wherein optimized for different parts of a chip (or die) write voltages may be utilized. As an illustrative example, wafer20800may include chips20802,20804,20806,20808,20810,20812,20814,20816,20818,20820,20822and20824. Each chip, such as, for example, chip20812, may include a number of different parts or blocks, such as, for example, blocks20826,20828,20830,20832,20834,20836,20838,20840and20842. Each of these different parts or blocks may have its own optimized write voltage that may be determined by measurement of test circuits which may, for example, be built onto the memory die, within each block, or on another die. This optimal write voltage may be stored on the floating body RAM die, such as die20802, by using some type of non-volatile memory, such as, for example, metal or oxide fuse-able links, or intentional damage programming of floating-body RAM bits, or may be stored off-die, for example, on a different die within wafer20800, or may be stored within a block, such as block20826. FIG.88illustrates an embodiment of the invention wherein write voltages for floating-body RAM cells may be substantially or partly based on the distance of the memory cell from its write circuits. As an illustrative example, memory array portion20900may include bit-lines20910,20912,20914and20916and may include memory rows20902,20904,20906and20908, and may include write driver circuits20950. The memory row20902with memory cells may be farthest away from the write driver circuits20950, and so, due to the large currents of floating-body RAM operation, may suffer a large IR drop along the wires. The memory row20908with memory cells may be closest to the write driver circuits20950and may have a low IR drop. Due to the IR drops, the voltage delivered to each memory cell of a row may not be the same, and may be significantly different. To tackle this issue, write voltages delivered to memory cells may be adjusted based on the distance from the write driver circuits. When the JR drop value may be known to be higher, which may be the scenario for memory cells farther away from the write driver circuits, higher write voltages may be used. When the IR drop may be lower, which may be the scenario for memory cells closer to the write driver circuits, lower write voltages may be used. Write voltages may be tuned based on temperature at which a floating body RAM chip may be operating. This temperature based adjustment of write voltages may be useful since required write currents may be a function of the temperature at which a floating body RAM device may be operating. Furthermore, different portions of the chip or die may operate at different temperatures in, for example, an embedded memory application. Another embodiment of the invention may involve modulating the write voltage for different parts of a floating body RAM chip based on the temperatures at which the different parts of a floating body RAM chip operate. Refresh can be performed more frequently or less frequently for the floating body RAM by using its temperature history. This temperature history may be obtained by many methods, including, for example, by having reference cells and monitoring charge loss rates in these reference cells. These reference cells may be additional cells placed in memory arrays that may be written with known data. These reference cells may then be read periodically to monitor charge loss and thereby determine temperature history. InFIG.82toFIG.88, various techniques to improve floating-body RAM were described. Many of these techniques may involve addition of additional circuit functionality which may increase control of the memory arrays. This additional circuit functionality may be henceforth referred to as ‘controller circuits’ for the floating-body RAM array, or any other memory management type or memory regions described herein.FIG.89A-Cillustrates an embodiment of the invention where various configurations useful for controller functions are outlined.FIG.89Aillustrates a configuration wherein the controller circuits21002may be on the same chip21006as the memory arrays21004.FIG.89Billustrates a 3D configuration21012wherein the controller circuits may be present in a logic layer21008that may be stacked below the floating-body RAM layer21010. As well,FIG.89Billustrates an alternative 3D configuration21014wherein the controller circuits may be present in a logic layer21018that may be stacked above a floating-body RAM array21016. 3D configuration21012and alternative 3D configuration21014may be constructed with 3D stacking techniques and methodologies, including, for example, monolithic or TSV.FIG.89Cillustrates yet another alternative configuration wherein the controller circuits may be present in a separate chip21020while the memory arrays may be present in floating-body chip21022. The configurations described inFIG.89A-Cmay include input-output interface circuits in the same chip or layer as the controller circuits. Alternatively, the input-output interface circuits may be present on the chip with floating-body memory arrays. The controller circuits in, for example,FIG.89, may include memory management circuits that may extend the useable endurance of said memory, memory management circuits that may extend the proper functionality of said memory, memory management circuits that may control two independent memory blocks, memory management circuits that may modify the voltage of a write operation, and/or memory management circuits that may perform error correction and so on. Memory management circuits may include hardwired or soft coded algorithms. FIG.90A-Billustrates an embodiment of the invention wherein controller functionality and architecture may be applied to applications including, for example, embedded memory. As an illustrated inFIG.90A, embedded memory application die21198may include floating-body RAM blocks21104,21106,21108,21110and21112spread across embedded memory application die21198and logic circuits or logic regions21102. In an embodiment of the invention, the floating-body RAM blocks21104,21106,21108,21110and21112may be coupled to and controlled by a central controller21114. As illustrated inFIG.90B, embedded memory application die21196may include floating-body RAM blocks21124,21126,21128,21130and21132and associated memory controller circuits21134,21136,21138,21140and21142respectively, and logic circuits or logic regions21144. In an embodiment of the invention, the floating-body RAM blocks21124,21126,21128,21130and21132may be coupled to and controlled by associated memory controller circuits21134,21136,21138,21140and21142respectively. FIG.91illustrates an embodiment of the invention wherein cache structure21202may be utilized in floating body RAM chip21206which may have logic circuits or logic regions21244. The cache structure21202may have shorter block sizes and may be optimized to be faster than the floating-body RAM blocks21204. For example, cache structure21202may be optimized for faster speed by the use of faster transistors with lower threshold voltages and channel lengths. Furthermore, cache structure21202may be optimized for faster speed by using different voltages and operating conditions for cache structure21202than for the floating-body RAM blocks21204. Persons of ordinary skill in the art will appreciate that the illustrations inFIG.80throughFIG.91are exemplary only and are not drawn to scale. Such skilled persons will further appreciate that many variations may be possible such as, for example, many types of floating body RAM may be utilized and the invention may not be limited to any one particular configuration or type. For example, monolithic 3D floating-body RAM chips, 2D floating-body RAM chips, and floating-body RAM chips that might be 3D stacked with through-silicon via (TSV) technology may utilize the techniques illustrated withFIG.80toFIG.91. Many other modifications within the scope of the illustrated embodiments of the invention described herein will suggest themselves to such skilled persons after reading this specification. Thus the invention is to be limited only by the appended claims. Refresh may be a key constraint with conventional capacitor-based DRAM. Floating-body RAM arrays may require better refresh schemes than capacitor-based DRAM due to the lower amount of charge they may store. Furthermore, with an auto-refresh scheme, floating-body RAM may be used in place of SRAM for many applications, in addition to being used as an embedded DRAM or standalone DRAM replacement. FIG.92illustrates an embodiment of the invention wherein a dual-port refresh scheme may be utilized for capacitor-based DRAM. A capacitor-based DRAM cell21300may include capacitor21310, select transistor21302, and select transistor21304. Select transistor21302may be coupled to bit-line21320at node21306and may be coupled to capacitor21310at node21312. Select transistor21304may be coupled to bit-line21321at node21308and may be coupled to capacitor21310at node21312. Refresh of the capacitor-based DRAM cell21300may be performed using the bit-line21321connected to node21308, for example, and leaving the bit-line21320connected to node21306available for read or write, i.e., normal operation. This may tackle the key challenge that some memory arrays may be inaccessible for read or write during refresh operations. Circuits required for refresh logic may be placed on a logic region located either on the same layer as the memory, or on a stacked layer in the 3DIC. The refresh logic may include an access monitoring circuit that may allow refresh to be conducted while avoiding interference with the memory operation. The memory or memory regions may, for example, be partitioned such that one portion of the memory may be refreshed while another portion may be accessed for normal operation. The memory or memory regions may include a multiplicity of memory cells such as, for example, capacitor-based DRAM cell21300. Persons of ordinary skill in the art will appreciate that the illustrations inFIG.92are exemplary only and are not drawn to scale. Such skilled persons will further appreciate that many variations may be possible such as, for example, a dual-port refresh scheme may be used for standalone capacitor based DRAM, embedded capacitor based DRAM that may be on the same chip or on a stacked chip, and monolithic 3D DRAM with capacitors. Moreover, refresh of the capacitor-based DRAM cell21300may be performed using the bit-line21320connected to node21306and leaving the bit-line21321connected to node21308available for read or write. Many other modifications within the scope of the illustrated embodiments of the invention described herein will suggest themselves to such skilled persons after reading this specification. Thus the invention is to be limited only by the appended claims. Other refresh schemes may be used for monolithic 3D DRAMs and for monolithic 3D floating-body RAMs similar to those described in US patent application 2011/0121366 and inFIG.79of this patent application. For example, refresh schemes similar to those described in “The ideal SoC memory: 1T-SRAMTM,” Proceedings of the ASIC/SOC Conference, pp. 32-36, 2000 by Wingyu Leung, Fu-Chieh Hsu and Jones, M.-E may be used for any type of floating-body RAM. Alternatively, these types of refresh schemes may be used for monolithic 3D DRAMs and for monolithic 3D floating body RAMs similar to those described in US patent application 2011/0121366 and inFIG.79of this patent application. Refresh schemes similar to those described in “Autonomous refresh of floating body cells”, Proceedings of the Intl. Electron Devices Meeting, 2008 by Ohsawa, T.; Fukuda, R.; Higashi, T.; et al. may be used for monolithic 3D DRAMs and for monolithic 3D floating body RAMs similar to those described in US patent application 2011/0121366 and inFIG.79of this patent application. FIG.93illustrates an embodiment of the invention in which a double gate device may be used for monolithic 3D floating-body RAM wherein one of the gates may utilize tunneling for write operations and the other gate may be biased to behave like a switch. As an illustrative example, nMOS double-gate DRAM cell21400may include first n+ region21402, second n+ region21410, oxide regions21404(partially shown for illustrative clarity), gate dielectric region21408and associated gate electrode region21406, gate dielectric region21416and associated gate electrode region21414, and p-type channel region21412. nMOS double-gate DRAM cell21400may be formed utilizing the methods described inFIG.79of this patent application. For example, the gate stack including gate electrode region21406and gate dielectric region21408may be designed and electrically biased during write operations to allow tunneling into the p-type channel region21412. The gate dielectric region21408thickness may be engineered to be thinner than the mean free path for trapping, so that trapping phenomena may be reduced or substantially eliminated. Persons of ordinary skill in the art will appreciate that the illustrations inFIG.93are exemplary only and are not drawn to scale. Such skilled persons will further appreciate that many variations may be possible such as, for example, a pMOS transistor may be used in place of or in complement to nMOS double gate DRAM cell21400. Moreover, nMOS double gate DRAM cell21400may be used such that one gate may be used for refresh operations while the other gate may be used for standard write and read operations. Furthermore, nMOS double-gate DRAM cell21400may be formed by method such as described in U.S. patent application 20110121366. Many other modifications within the scope of the illustrated embodiments of the invention described herein will suggest themselves to such skilled persons after reading this specification. Thus the invention is to be limited only by the appended claims. FIG.94Aillustrates a conventional chip with memory wherein peripheral circuits21506may substantially surround memory arrays21504, and logic circuits or logic regions21502may be present on the die. Memory arrays21504may need to be organized to have long bit-lines and word-lines so that peripheral circuits21506may be small and the chip's array efficiency may be high. Due to the long bit-lines and word-lines, the energy and time needed for refresh operations may often be unacceptably high. FIG.94Billustrates an embodiment of the invention wherein peripheral circuits may be stacked monolithically above or below memory arrays using techniques described in patent application 2011/0121366, such as, for example, monolithic 3D stacking of memory and logic layers. Memory array stack21522may include memory array layer21508which may be monolithically stacked above peripheral circuit layer21510. Memory array stack21524may include peripheral circuits21512which may be monolithically stacked above memory array layer21514. Memory array stack21522and Memory array stack21524may have shorter bit-lines and word-lines than the configuration shown inFIG.94Asince reducing memory array size may not increase die size appreciably (since peripheral circuits may be located underneath the memory arrays). This may allow reduction in the time and energy needed for refresh. FIG.94Cillustrates an embodiment of the invention wherein peripheral circuits may be monolithically stacked above and below memory array layer21518using techniques described in US patent application 2011/0121366, such as, for example, monolithic 3D stacking of memory and logic layers including vertical connections. 3D IC stack21500may include peripheral circuit layer21520, peripheral circuit layer21516, and memory array layer21518. Memory array layer21518may be monolithically stacked on top of peripheral circuit layer21516and then peripheral circuit layer21520may then be monolithically stacked on top of memory array layer21518. This configuration may have shorter bit-lines and word-lines than the configuration shown inFIG.94Aand may allow shorter bit-lines and word-lines than the configuration shown inFIG.94B. 3D IC stack21500may allow reduction in the time and energy needed for refresh. A transferred monocrystalline layer, such as, for example, memory array layer21518and peripheral circuit layer21520, may have a thickness of less than about 150 nm. Persons of ordinary skill in the art will appreciate that the illustrations inFIG.94AthroughFIG.94Care exemplary only and are not drawn to scale. Such skilled persons will further appreciate that many variations may be possible such as, for example, 3D IC stack may include, for example, two memory layers as well as two logic layers. Many other modifications within the scope of the illustrated embodiments of the invention described herein will suggest themselves to such skilled persons after reading this specification. Thus the invention is to be limited only by the appended claims. Some embodiments of the invention may include alternative techniques to build IC (Integrated Circuit) devices including techniques and methods to construct 3D IC systems. Some embodiments of the invention may enable device solutions with far less power consumption than prior art. These device solutions could be very useful for the growing application of mobile electronic devices and mobile systems, such as, for example, mobile phones, smart phone, and cameras. For example, incorporating the 3D IC semiconductor devices according to some embodiments of the invention within these mobile electronic devices and mobile systems could provide superior mobile units that could operate much more efficiently and for a much longer time than with prior art technology. Smart mobile systems may be greatly enhanced by complex electronics at a limited power budget. The 3D technology described in the multiple embodiments of the invention would allow the construction of low power high complexity mobile electronic systems. For example, it would be possible to integrate into a small form function a complex logic circuit with high density high speed memory utilizing some of the 3D DRAM embodiments of the invention and add some non-volatile 3D NAND charge trap or RRAM described in some embodiments of the invention. The need to reduce power to allow effective use of limited battery energy and also the lightweight and small form factor derived by highly integrating functions with low waste of interconnect and substrate could be highly benefitted by the redundancy and repair idea of the 3D monolithic technology as has been presented in embodiments of the invention. This unique technology could enable a mobile device that would be lower cost to produce or would require lower power to operate or would provide a lower size or lighter carry weight, and combinations of these 3D monolithic technology features may provide a competitive or desirable mobile system. 3D ICs according to some embodiments of the invention could enable electronic and semiconductor devices with much a higher performance as a result from the shorter interconnect as well as semiconductor devices with far more complexity via multiple levels of logic and providing the ability to repair or use redundancy. The achievable complexity of the semiconductor devices according to some embodiments of the invention could far exceed what may be practical with the prior art technology. These potential advantages could lead to more powerful computer systems and improved systems that have embedded computers. Commercial wireless mobile communications have been developed for almost thirty years, and play a special role in today's information and communication technology Industries. The mobile wireless terminal device has become part of our life, as well as the Internet, and the mobile wireless terminal device may continue to have a more important role on a worldwide basis. Currently, mobile (wireless) phones are undergoing much development to provide advanced functionality. The mobile phone network is a network such as a GSM, GPRS, or WCDMA, 3G and 4G standards, and the network may allow mobile phones to communicate with each other. The base station may be for transmitting (and receiving) information to the mobile phone. A typical mobile phone system may include, for example, a processor, a flash memory, a static random access memory, a display, a removable memory, a radio frequency (RF) receiver/transmitter, an analog base band (ABB), a digital base band (DBB), an image sensor, a high-speed bi-directional interface, a keypad, a microphone, and a speaker. A typical mobile phone system may include a multiplicity of an element, for example, two or more static random access memories, two or more displays, two or more RF receiver/transmitters, and so on. Conventional radios used in wireless communications, such as radios used in conventional cellular telephones, typically may include several discrete RF circuit components. Some receiver architectures may employ superhetrodyne techniques. In a super heterodyne architecture an incoming signal may be frequency translated from its radio frequency (RF) to a lower intermediate frequency (IF). The signal at IF may be subsequently translated to baseband where further digital signal processing or demodulation may take place. Receiver designs may have multiple IF stages. The reason for using such a frequency translation scheme is that circuit design at the lower IF frequency may be more manageable for signal processing. It is at these IF frequencies that the selectivity of the receiver may be implemented, automatic gain control (AGC) may be introduced, etc. A mobile phone's need of a high-speed data communication capability in addition to a speech communication capability has increased in recent years. In GSM (Global System for Mobile communications), one of European Mobile Communications Standards, GPRS (General Packet Radio Service) has been developed for speeding up data communication by allowing a plurality of time slot transmissions for one time slot transmission in the GSM with the multiplexing TDMA (Time Division Multiple Access) architecture. EDGE (Enhanced Data for GSM Evolution) architecture provides faster communications over GPRS. 4th Generation (4G) mobile systems aim to provide broadband wireless access with nominal data rates of 100 Mbit/s. 4G systems may be based on the 3GPP LTE (Long Term Evolution) cellular standard, WiMax or Flash-OFDM wireless metropolitan area network technologies. The radio interface in these systems may be based on all-IP packet switching, MIMO diversity, multi-carrier modulation schemes, Dynamic Channel Assignment (DCA) and channel-dependent scheduling. Prior art such as U.S. application Ser. No. 12/871,984 may provide a description of a mobile device and its block-diagram. It is understood that the use of specific component, device and/or parameter names (such as those of the executing utility/logic described herein) are for example only and not meant to imply any limitations on the invention. The invention may thus be implemented with different nomenclature/terminology utilized to describe the components/devices/parameters herein, without limitation. Each term utilized herein is to be given its broadest interpretation given the context in which that term is utilized. For example, as utilized herein, the following terms are generally defined: (1) Mobile computing/communication device (MCD): is a device that may be a mobile communication device, such as a cell phone, or a mobile computer that performs wired and/or wireless communication via a connected wireless/wired network. In some embodiments, the MCD may include a combination of the functionality associated with both types of devices within a single standard device (e.g., a smart phones or personal digital assistant (PDA)) for use as both a communication device and a computing device. Some embodiments of the invention may include alternative techniques to build IC (Integrated Circuit) devices including techniques and methods to construct 3D IC systems. Some embodiments of the invention may enable device solutions with far less power consumption than prior art, or with more functionality in a smaller physical footprint. These device solutions could be very useful for the growing application of Autonomous in vivo Electronic Medical (AEM) devices and AEM systems such as ingestible “camera pills,” implantable insulin dispensers, implantable heart monitoring and stimulating devices, and the like. One such ingestible “camera pill” is the Philips' remote control “iPill”. For example, incorporating the 3D IC semiconductor devices according to some embodiments of the invention within these AEM devices and systems could provide superior autonomous units that could operate much more effectively and for a much longer time than with prior art technology. Sophisticated AEM systems may be greatly enhanced by complex electronics with limited power budget. The 3D technology described in many of the embodiments of the invention would allow the construction of a low power high complexity AEM system. For example it would be possible to integrate into a small form function a complex logic circuit with high density high speed memory utilizing some of the 3D DRAM embodiments herein and to add some non-volatile 3D NAND charge trap or RRAM described in embodiments herein. Also in another application 12/903,862 filed by some of the inventors and assigned to the same assignee a 3D micro display and a 3D image sensor are presented. Integrating one or both to complex logic and or memory could be very effective for retinal implants. Additional AEM systems could be customized to some specific market applications. 3D ICs according to some embodiments of the invention could also enable electronic and semiconductor devices with a much higher performance due to the shorter interconnect as well as semiconductor devices with far more complexity via multiple levels of logic and providing the ability to repair or use redundancy. The achievable complexity of the semiconductor devices according to some embodiments of the invention could far exceed what may be practical with the prior art technology. These advantages could lead to more powerful computer systems and improved systems that have embedded computers. It will also be appreciated by persons of ordinary skill in the art that the invention is not limited to what has been particularly shown and described hereinabove. For example, drawings or illustrations may not show n or p wells for clarity in illustration. Moreover, transistor channels illustrated or discussed herein may include doped semiconductors, but may instead include undoped semiconductor material. Further, any transferred layer or donor substrate or wafer preparation illustrated or discussed herein may include one or more undoped regions or layers of semiconductor material. Rather, the scope of the invention includes both combinations and sub-combinations of the various features described herein above as well as modifications and variations which would occur to such skilled persons upon reading the foregoing description. Thus the invention is to be limited only by the appended claims. | 469,631 |
11862504 | MODE FOR CARRYING OUT THE INVENTION The mask-integrated surface protective tape of the present invention is used for the method of obtaining a semiconductor chip by dividing and singulating a semiconductor wafer with plasma dicing. As described below, by using the mask-integrated surface protective tape of the present invention, a photolithography process prior to the plasma dicing step becomes unnecessary, whereby production costs of the semiconductor chips and the semiconductor products can be largely suppressed. <<Mask-Integrated Surface Protective Tape>> The mask-integrated surface protective tape of the present invention has at least a substrate film and a mask material layer. The mask material layer may be provided directly on the substrate film, or may be provided on the substrate film through a temporary-adhesive layer (that is, the substrate film and the mask material layer may be provided facing each other across the temporary-adhesive layer). Note, in the present invention and the present specification, that a tape in which a temporary-adhesive layer is provided on a substrate film without a mask material layer is referred to simply as a surface protective tape, while a tape having a mask material layer is referred to as a mask-integrated surface protective tape. In order to protect a patterned surface (front surface) of the semiconductor wafer at the time of backgrinding of the semiconductor wafer, the mask-integrated surface protective tape of the present invention is used to laminate it on the patterned surface. Accordingly, performances are required, including the same adhesion property as an ordinary semiconductor wafer-processing surface protective tape. In particular, the mask-integrated surface protective tape has a function of protecting a semiconductor device formed on the patterned surface of the semiconductor wafer. Specifically, at the wafer-thinning step (backgrinding step) which is a post-step, the semiconductor wafer is supported by the patterned face, and the backing-face of the semiconductor wafer is ground. Therefore, the mask-integrated surface protective tape needs to withstand a load in grinding. For this reason, the mask-integrated surface protective tape is different from a mere resist film or the like, and has: the thickness enough to coat the device formed on the patterned face; and the pressing resistance which is low, and has: a high adhesiveness that can adhere tightly to the device, so that the infiltration of dusts, grinding water, and the like, in grinding, is not occurred. In addition to the above, the mask-integrated surface protective tape of the present invention is suitable for a plasma dicing method, and can eliminate the need for a mask formation by photolithography process in production of the semiconductor chip using a plasma dicing method. In particular, the mask-integrated surface protective tape of the present invention allows production of a semiconductor chip including at least the following Steps (a) to (d) in the steps of the production of the semiconductor chip, and is preferably applied to said steps of the production of the semiconductor chip. [Steps (a) to (d)](a) A step of, in the state of having laminated the mask-integrated surface protective tape on the side of a patterned surface of a semiconductor wafer, grinding the backing-face of the semiconductor wafer; laminating a wafer-fixing tape on the backing-face side of the ground semiconductor wafer; and supporting and fixing the wafer to a ring frame;(b) a step of, after peeling the substrate firm or integrally peeling both the substrate film and the temporary-adhesive layer from the mask-integrated surface protective tape, thereby to expose the mask material layer on top, forming an opening by cutting a portion of the mask material layer corresponding to a street of the semiconductor wafer with a laser;(c) a plasma-dicing step of segmentalizing the semiconductor wafer at the street with SF6plasma, and thereby for singulating the semiconductor wafer into semiconductor chips; and(d) an ashing step of removing the mask material layer with O2plasma. Hereinafter, the substrate film, the mask material layer (mask material), and the temporary-adhesive layer are explained in this order. <Substrate Film> The substrate film may have a single layer structure, or may be a laminate body in which multiple layers are laminated. As for the resin or polymer component which constitutes the substrate film, use can be made of any of resins or polymer components to be used in a conventional semiconductor wafer-processing surface protective tape. Examples thereof include polyolefin resins, polyester resins, (meth)acrylic resins and furthermore polyphenylene sulfide, polyether imide, polyimide, polycarbonate, polyurethane, and rubber. They may be a single substance or a mixture of two or more kinds. Examples of the polyolefin resins include a polyolefin resin selected from polyethylene, polypropylene, and ethylene/propylene copolymer, each of which is preferable in the present invention. Meanwhile, polyethylene and polypropylene, other than homo-polyethylene and homo-polypropylene, ordinarily contain α-olefin as a copolymer component in order to adjust its density. In particular, with respect to polyethylene, the content of α-olefin in the polyethylene is generally 5% by mole or less. The polyethylene is classified into, depending on its density (specific gravity) and the like, a high density polyethylene (HDPE), a low density polyethylene (LDPE), a very low density polyethylene (VLDPE), a linear low density polyethylene (LLDPE) and an ultra-high molecular weight polyethylene (UHMW-PE). Examples of polypropylene include homo-polypropylene, random-polypropylene, block-polypropylene, and the like. Examples of the polyethylene resins, other than the above-described ones, include polystyrene or its copolymers, polybutene-1, poly-4-methylpentene-1, ethylene/vinyl acetate copolymer, ethylene/(meth)acrylic acid or/(meth)acrylic acid copolymer; homo-polymer or co-polymer of α-olefin, such as ionomer; a mixture of these polymers, and the like. Examples of the polyester resin include polyethylene terephthalate (PET), polytrimethylene terephthalate (PTT), polybutylene terephthalate (PBT), polyethylene naphthalate (PEN), and polybutylene naphthalate (PBN). In the present invention, the substrate film preferably has at least a polyolefin resin layer, and the polyolefin resin is more preferably polyolefin and is still more preferably a low-density polyolefin. Further, in a case where the substrate film is a laminate body in which plural layers are laminated, one of preferable materials is: a laminate body composed of a low density polyethylene layer and an ethylene/vinyl acetate copolymer layer; a laminate body composed of a polypropylene layer and a polyethylene terephthalate layer; or a laminate body composed of a polyolefin resin layer, a polyethylene terephthalate layer and a polyethylene naphthalate layer. The foregoing substrate film can be produced using a general extrusion method. In the case where the substrate film is obtained by laminating various resins, these are produced by a co-extrusion method, a lamination method or the like. At this time, as conventionally practiced in the ordinary production method of the laminate film, an adhesion material layer may be provided between resins. In the present invention, the thickness of the substrate film is preferably from 20 to 200 μm from the viewpoints of strength-elongation characteristics and radiolucency. <Mask Material Layer> The mask material layer is a layer that protects a front surface of the semiconductor wafer (patterned surface in particular) from etching (dicing) by irradiation of plasma, such as SF6, in the plasma dicing step, and moreover is a layer that allows a high-precision division of the semiconductor wafer by selectively etching (dicing) only a street portion of the semiconductor wafer which has been removed in the opening step. In the present invention, since the mask material layer is used in a way such that it is laminated on a patterned surface of the semiconductor wafer, the mask material layer has performances including a temporary-adhesion property as is the case with a temporary-adhesive layer in the ordinary semiconductor wafer-processing surface protective tape. In the present invention, of the above-described Step (b), in a step of cutting by laser, of the exposed mask material layer on top, a portion of the mask material layer corresponding to the street of the semiconductor wafer, thereby to form an opening of the street of the semiconductor wafer, a laser light is irradiated. The laser light to be irradiated is not particularly limited, as exemplified by CO2laser (gas laser of carbon dioxide), YAG laser (solid laser using yttrium, aluminum and garnet), a semiconductor laser, and the like. In the present invention, in particular, a laser having a UV wavelength region of 355 nm which is the third harmonic of YAG laser may be preferably used. Specifically, since this laser has very high absorption ratio for various materials and does not put a thermal stress, this laser can be used for microfabrication requiring high quality. Further, since a beam diameter thereof can be narrowed when compared to a long wave laser, more microscopic processing can be performed, so that this laser can be preferably applied to the present invention. Therefore, in the present invention, a parallel ray transmittance of the mask material layer at a wavelength region of 355 nm is 30% or less. When the parallel ray absorption ratio is more than 30%, the mask material layer has an insufficient laser light absorption. That is, one of the problems in the opening step of the street portion of the semiconductor wafer is that a laser irradiation needs several times for opening, so that a processing is extended for a long time of period, and another problem is that the mask material layer melts and becomes a residue thereof due to an energy input of the excessive laser light, and as a result, the residue remains on the surface of the semiconductor wafer and degrades a processing quality. [Resin] As for the resin that constitutes the mask material layer, any resins may be used. However, it is preferred that a resin which is used as a temporary-adhesive which constitutes a temporary adhesive layer in an ordinary semiconductor wafer processing-surface protective tape. As for the above-described resin that is used as a temporary-adhesive, a resin composed of (meth)acrylic copolymer is preferred. Note, in the present invention and the present specification, that the term “(meth)acryl” collectively means “acryl” and “methacryl” and may be either one of “acryl” and “methacryl”, or may be a mixture thereof. For example, (meth)acrylic acid ester means acrylic acid ester and/or methacrylic acid ester. Therefore, in the present invention, it is preferable for the mask material layer, to contain (meth)acrylic copolymer. Meanwhile, the expression “to contain (meth)acrylic copolymer” means to embrace an embodiment in which the (meth)acrylic copolymer is present in the state of being reacted with a curing agent. The (meth)acrylic copolymer may be a copolymer of two or more kinds of different (meth)acrylic esters, and therefore may be a copolymer of (meth)acrylic ester and a monomer having an ethylenically unsaturated group, which includes (meth)acrylic acid and (meth)acrylic acid amide. Herein, examples of the monomer having an ethylenically unsaturated group other than the above monomers include (meth)acrylic nitrile, styrene, ethylene, propylene, butylene, butadiene, vinyl alcohol, vinyl acetate, vinyl chloride, maleic acid (esters and acid anhydride are also included), and the like. In the present invention, as the above-described polymer, it is preferred that a copolymer of two or more kinds of monomers selected from (meth)acrylic acid esters and (meth)acrylic acids. Further, as a polymer that is contained in a resin that constitutes the mask material layer, it may be one kind of copolymer, or a mixture of plural kinds of copolymers. Although the (meth)acrylic acid ester may be a (meth)acrylic acid alkyl ester or a (meth)acrylic acid aryl ester, and the (meth)acrylic acid alkyl ester is preferable. Further, the number of carbon atoms in the alcohol moiety (ester forming-alcohol) of the (meth)acrylic acid ester is preferably from 1 to 20, more preferably from 1 to 15, and further preferably from 1 to 12. Meanwhile, the alcohol moiety of the (meth)acrylic acid ester may have a substituent. Examples of the (meth)acrylic acid ester include methyl (meth)acrylate, ethyl (meth)acrylate, n-propyl (meth)acrylate, iso-propyl (meth)acrylate, n-butyl (meth)acrylate, t-butyl (meth)acrylate, n-hexyl (meth)acrylate, cyclohexyl (meth)acrylate, n-octyl (meth)acrylate, 2-ethylhexyl (meth)acrylate, decyl (meth)acrylate, dodecyl (meth)acrylate, and 2-hydroxyethyl (meth)acrylate. A proportion of the (meth)acrylic acid ester component of the total monomer component of the (meth)acrylic copolymer is preferably 70% or more, more preferably 80% or more, and further more preferably 90% or more. Further, in a case where the proportion of the (meth)acrylic acid ester component of the total monomer component of the (meth)acrylic copolymer is not 100% by mole, it is preferable that the remaining monomer component is a monomer component (i.e. (meth)acrylic acid and the like) existing in the form of (meth)acryloyl group polymerized as a polymerizable group. Further, the proportion of the (meth)acrylic acid ester component having a functional group (for example, hydroxyl group) reacting with a curing agent described below, of the total monomer component of the (meth)acrylic copolymer is preferably 1% by mole or more, more preferably 2% by mole or more, further more preferably 5% by mole or more, and still further more preferably 10% by mole or more. Note that, the proportion of the (meth)acrylic acid ester component having a functional group reacting with the curing agent is preferably 35% by mole or less, more preferably 25% by mole or less. The mass-average molecular weight of these polymers is normally about 300,000 to 1,000,000. Herein, the mass-average molecular weight can be measured as a polystyrene conversion molecular weight by Gel Permeation Chromatography (GPC). The content (content converted to the state before reacting with a curing agent) of the (meth)acrylic copolymer in the mask material layer is preferably 80% by mass or more, more preferably 90% by mass or more, and still more preferably from 95 to 99.9% by mass. [Curing Agent] The (meth)acrylic copolymer in the mask material layer is preferably cured and it is preferable for the mask material layer-forming composition, to contain a curing agent in addition to the (meth)acrylic copolymer. The curing agent is used to adjust an adhesive force and a cohesion force by reacting it with a functional group which the (meth)acrylic copolymer has. As the curing agent, examples thereof include: an epoxy compound having 2 or more epoxy groups in the molecule (hereinafter, also referred to as “epoxy-based curing agent”), such as 1,3-bis(N,N-diglycidyl aminomethyl)cyclohexane, 1,3-bis(N,N-diglycidyl aminomethyl)toluene, 1,3-bis(N,N-diglycidyl aminomethyl)benzene, N,N,N′,N′-tetraglycidyl-m-xylenediamine, ethylene glycol diglycidyl ether, or terephthalic acid diglycidyl ester acrylate; an isocyanate compound having 2 or more isocyanate groups in the molecule (hereinafter, also referred to as “isocyanate-based curing agent”), such as 2,4-tolylenediisocyanate, 2,6-tolylenediisocyanate, 1,3-xylylenediisocyanate, 1,4-xylylenediisocyanate, diphenylmethane-4,4′-isocyanate, hexamethylene diisocyanate, isophorone diisocyanate, or an adduct type of these; an aziridine compound having 2 or more aziridinyl groups in the molecule (aziridine-based curing agent), such as tetramethylol-tri-β-aziridinyl propionate, trimethylol-tri-β-aziridinyl propionate, trimethylolpropane-tri-β-aziridinyl propionate, trimethylolpropane-tri-β-(2-methylaziridine)propionate, tris-2,4,6-(1-aziridinyl)-1,3,5-triazine, tris[1-(2-methyl)-aziridinyl]phosphine oxide, or hexa[1-(2-methyl)-aziridinyl]triphosphatriazine; and the like. An addition amount of the curing agent may be adjusted depending on a desired adhesion force, and is suitably from 0.1 to 5.0 mass parts with respect to 100 mass parts of the (meth)acrylic copolymer. In the mask material layer of the mask-integrated surface protective tape of the present invention, the curing agent is in a state of having reacted with the (meth)acrylic copolymer. <Radiation-Curable Mask Material Layer> As the mask material layer, any one of the radiation-curable type mask material layer whose mask material is cured by irradiation of the radiation, or the non-radiation-curable type mask material layer may be workable. In the present invention, in any case of a substrate film or a temporary-adhesive layer provided on the substrate film, since peeling can be easily performed while leaving only a mask material layer on the patterned surface of the semiconductor wafer by making the mask material layer radiation-curable, it is preferable for the mask material layer to be of radiation-curable type. Herein, the non-radiation-curable type is also called as a pressure-sensitive type as is the case with a temporary-adhesive. This type of the mask material layer is composed of the above-described resin and a resin cured by the curing agent and means not to contain a component having an ethylenically unsaturated group that cures by irradiation of radiation. In a case of a radiation-curable type mask material layer, in the above-described Step (b), it becomes easy to leave only the mask material layer from the mask-integrated surface protective tape on the semiconductor wafer surface. Specifically, an interlayer-peeling property between the mask material layer and the layer having contact with this mask material layer (a substrate film, or in a case of the surface protective tape, a temporary-adhesive layer of the surface protective tape) is improved by irradiating a radiation from the side of the substrate film of the mask-integrated surface protective tape thereby to cure the mask material layer, so that the peeling of the surface protective tape from the mask-integrated surface protective tape becomes easy. This is thought to be caused in a manner such that a mask material layer is 3-dimensionally reticulated by exposure to radiation, so that a temporary-adhesion power is lowered, and thereby a strong adhesion to a layer having contact with the mask material layer, for example, to a temporary-adhesive layer, is released, and as a result, it becomes possible to peel easily from the layer having contact with the mask material layer, for example, the temporary-adhesive layer, of the mask-integrated surface protective tape. However, it is preferable that the adhesion power between the mask material layer and the substrate film or the temporary-adhesive layer which contact with the mask material layer becomes lower by exposure to radiation than the adhesion power between the mask material layer and a patterned surface of the semiconductor wafer. In the present invention and the present specification, the term “radiation” is a concept including both a light beam, such as ultraviolet, and an ionizing radiation, such as an electron beam. The radiation for use in the present invention is preferably ultraviolet. In order to make the mask material layer radiation-curable, the mask material layer should be made to have a property of being cured and 3-dimensionally reticulated by radiation as is the case with a radiation-curable type temporary-adhesive of the ordinarily semiconductor wafer-processing surface protective tape. In order to make the mask material layer radiation-curable, broadly (1) the mask material layer should contain a resin (polymer) having an ethylenically unsaturated group (radiation-polymerizable carbon-carbon double bond which is also called as an ethylenically double bond) in the side chain, or (2) the mask material layer should contain a low molecular weight compound having at least two ethylenically unsaturated double bonds in the molecule (this compound includes an oligomer and hereinafter, is also called as a radiation-polymerizable low molecular weight compound), together with a resin (polymer) to be used in the above-described pressure-sensitive type. In the present invention, although any of the above-described methods (1) and (2) is effective, the method (1) is preferable. Examples of an ethylenically unsaturated group includes: a vinyl group, an allyl group, a styryl group, a (meth)acryloyloxy group, a (meth)acryloylamino group, and the like. [(1) Resin Having Ethylenically Unsaturated Group in Side Chain] The resin having an ethylenically unsaturated group in the side chain can be obtained by reacting a copolymer having a reactive functional group (α), such as a hydroxyl group, at the side chain, and a compound having a functional group (β), such as an isocyanate group, that reacts with the reactive functional group (α) and further having an ethylenically unsaturated group. Representative examples of the compound having the reactive functional group (β) and the ethylenically unsaturated group include 2-(meth)acryloyloxyethyl isocyanate. Examples of the above-described functional groups (α) and (β) include a carboxyl group, a hydroxyl group, an amino group, a mercapto group, a cyclic acid anhydride group, an epoxy group, an isocyanate group (—N═C═O) and the like. Herein, the cyclic acid anhydride group is a group having a cyclic acid anhydride structure. As a combination of the above-described functional groups (α) and (β), for example, in a case of a nucleophilic substitution reaction, one is a nucleophile and another is an electrophile. The resin having an ethylenically unsaturated group in the side chain is preferably a resin composed of a (meth)acrylic copolymer. As the (meth)acrylic copolymer, at least in a unit structure obtained from a (meth)acrylic acid ester, a polymer having a unit structure having an ethylenically unsaturated group in the alcohol moiety of the ester is preferable. Further, it is preferable for the above-described (meth)acrylic copolymer to have, in addition to the unit structure, a recurring unit obtained from a (meth)acrylic acid ester or a (meth)acrylic acid, each of which has no ethylenically unsaturated group in the alcohol moiety thereof, and a monomer having another ethylenically unsaturated group. Of these co-polymers, it is preferable to have a recurring unit obtained from a (meth)acrylic acid ester and/or (meth)acrylic acid. In particular, it is preferable to have a recurring unit obtained from a (meth)acrylic acid alkyl ester in which the number of carbon atoms in the alcohol moiety thereof is from 8 to 12. Of the monomer components that constitute the (meth)acrylic copolymer having an ethylenically unsaturated group in the side chain, the ratio of the alkyl (meth)acrylate component having the number of carbon atoms of 8 to 12 is preferably from 45 to 85% by mole, and more preferably from 50 to 80% by mole. As the resin having an ethylenically unsaturated group in the side chain, those described in paragraphs [0020] to [0036] of Japanese Patent No. 6034522 are preferable. In the present specification, the contents described in said paragraphs [0020] to [0036] are preferably incorporated therein by reference. [(2) Radiation-Polymerizable Low Molecular Weight Compound] As for the radiation polymerizable low molecular weight compound described above, use may be widely applicable of: trimethylolpropane triacrylate, tetramethylolmethane tetraacrylate, pentaerythritol triacrylate, pentaerythritol tetraacrylate, dipentaerythritol mono-hydroxypentaacrylate, dipentaerythritol hexaacrylate, 1,4-butyleneglycol diacrylate, 1,6-hexanediol diacrylate, polyethyleneglycol diacrylate, and acrylate-based compounds, such as oligo-ester acrylates, and the like. Further, in addition to the acrylate-based compounds, use can be also made of a urethane acrylate-based oligomer. The urethane acrylate-based oligomer is obtained by conducting reaction of an acrylate or methacrylate having a hydroxy group (for example, 2-hydroxyethyl acrylate, 2-hydroxyethyl methacrylate, 2-hydroxypropyl acrylate, 2-hydroxypropyl methacrylate, polyethyleneglycol acrylate, polyethyleneglycol methacrylate, and the like) with a urethane prepolymer having an isocyanate group at the end thereof, which is obtained by conducting reaction of a polyol compound, such as a polyester type- or a polyether type-polyol, and a polyvalent isocyanate compound (for example, 2,4-tolylene diisocyanate, 2,6-tolylene diisocyanate, 1,3-xylylene diisocyanate, 1,4-xylylene diisocyanate, diphenyl methane-4,4′-diisocyanate, and the like). As a blending ratio of the (meth)acrylic copolymer and the radiation-polymerizable low molecular weight compound, the radiation-polymerizable low molecular weight compound is desirably blended in the range of 50 to 200 mass parts and preferably 50 to 150 mass parts, with respect to 100 mass parts of the (meth)acrylic copolymer. When the mixing ratio is in this range, the adhesiveness (or the adhesion power) to the mask material layer after irradiation with radiation can be lowered greatly. [Photoradical Polymerization Initiator] In order to subject the mask material layer to polymerization and curing by radiation, the use of a photoradical polymerization initiator allows an effective progress of polymerization reaction, which is preferable. Examples of the photoradical polymerization initiator include an alkyl phenone type polymerization initiator, a diaryl ketone type polymerization initiator, a diacyl type polymerization initiator, an acyl phosphine oxide type polymerization initiator, an oxime ester type polymerization initiator, a halogenated alkyl-substituted-1,3,5-triazine type polymerization initiator, and 2,4,5-triaryl imidazole dimer (lophine dimer). In the present invention, it is preferable to use an alkyl- or cycloalkyl-phenone having a hydroxyl group at α-position. As the photoradical polymerization initiator, for example, use can be made of: isopropylbenzoin ether, isobutylbenzoin ether, benzophenone, Michler's ketone, chlorothioxanthone, benzyl methyl ketal, α-hydroxycyclohexyl phenyl ketone, 2-hydroxymethylphenyl propane, and the like. By adding at least one of these compounds to the mask material layer, a polymerization reaction can be efficiently progressed. [Curing Agent] Even in the resin that forms a radiation-curable type mask material layer, it is preferable for this resin to have been cured by a curing agent. In particular, in the case where this resin is a resin having an ethylenically unsaturated group in the side chain, it is preferable to obtain a cured resin by containing the curing agent in a mask material layer-forming composition. As the curing agent, those exemplified in a case where the curing agent is of pressure-sensitive type are preferable. The content of the curing agent is appropriately from 0.1 to 5.0 parts by mass, with respect to 100 parts by mass of the resin containing the curing agent before curing, for example, (meth)acrylic copolymer. That is, in the mask material layer of the mask-integrated surface protective tape of the present invention, a curing agent is in a state of having reacted with the resin before curing, such as (meth)acrylic copolymer. [Ultraviolet-Absorbing Constituent] In the present invention, the parallel ray absorption ratio in the wavelength region of 355 nm of the mask material layer is preferably 30% or less. In order to adjust the parallel ray absorption ratio in the wavelength region of 355 nm of the mask material layer to 30% or less, it is preferable for the mask material layer to contain an ultraviolet-absorbing constituent. As the ultraviolet-absorbing constituent, an ultraviolet absorber or an ultraviolet-absorbing polymer is more preferable, to contain in the mask material layer. (Ultraviolet Absorber) Since the ultraviolet absorber is excellent in compatibility to the resin, it has a high transparency, and has high absorption performance to a laser light in the ultraviolet region in a small amount thereof, thus it can be preferably used in the present invention. It is preferable for the mask material layer to contain at least one kind of ultraviolet absorber having a triazine skeleton, a benzophenone skeleton, a benzotriazole skeleton or a benzoate skeleton. As the ultraviolet absorber, examples of the compound having a triazine skeleton include 2,4-bis[2-hydroxy-4-butoxyphenyl]-6-(2,4-dibutoxyphenyl)-1,3,5-triazine, 2,4-bis(2,4-dimethylphenyl)-6-(2-hydroxy-4-n-octyloxyphenyl)-1,3,5-triazine, 2-(2,4-dihydroxyphenyl)-4,6-bis(2,4-dimethylphenyl)-1,3,5-triazine, 2-(2,4-dihydroxyphenyl)-4,6-diphenyl-1,3,5-triazine, and 2-(2-hydroxy-4-methoxyphenyl)-4,6-diphenyl-1,3,5-triazine. Examples of the compound having a benzophenone skeleton include 2,4-dihyroxybenzophenone, 2,2′-dihydroxy-4,4′-dimethoxybenzophenone, 2-hydroxy-4-methoxybenzophenone, 2-hydroxy-4-n-octyloxybenzophenone, and 2,2′,4,4′-tetrahydroxybenzophenone. Examples of the compound having a benzotriazole skeleton include 2-(2-hydroxy-5-t-butylphenyl)-2H-benzotriazole, 2-(2H-benzotriazole-2-yl)-4,6-bis(1-methyl-1-phenylethyl)phenol, and 2-(2H-benzotriazole-2-yl)-6-(1-methyl-1-phenylethyl)-4-(1,1,3,3-tetramethylbutyl)phenol. Examples of the compound having a benzoate skeleton include 2,4-di-t-butylphenyl-3,5-di-t-butyl-4-hydroxybenzoate, and 2,4-di-t-butylphenyl-4′-hydroxy-3′,5′-di-t-butylbenzoate. As the ultraviolet absorber, use may be made of a commercially available product. Examples thereof include ADEKA STAB LA series (LA-24, LA-29, LA-31, LA-32, LA-36, LA-F70, 1413) (each trade name) manufactured by ADEKA K.K., TINUVIN P, TINUVIN 234, TINUVIN 326, TINUVIN 329, TINUVIN 213, TINUVIN 571, TINUVIN 1577ED, CHIMAS SORB 81, TINUVIN 120 (each trade name) and the like, each of which are manufactured by BASF Corporation. One kind or a combination of two or more kinds of the ultraviolet absorber may be used. The addition amount of the ultraviolet absorber may be adjusted according to a desired laser absorption performance. The content of the ultraviolet absorber in the mask material layer is preferably from 0.1 to 5.0 parts by mass, with respect to 100 parts by mass of the resin, i.e. (meth)acrylic copolymer. (Ultraviolet-Absorbing Polymer) In order for the mask material layer to have high laser absorptivity, it is preferable for the mask material layer to contain an ultraviolet-absorbing polymer. With any of the ultraviolet-absorbing polymers, an ultraviolet-absorbing performance is given to the polymer itself, by using a polymerizable monomer having an ultraviolet-absorbing group for one of repeating units (segments) obtained from a copolymerizable monomer that constitute the polymer molecule. The above-described ultraviolet-absorbing polymer has no problem, such as elution or bleed-out of the ultraviolet-absorbing constituent, as compared to a structure in which an ultraviolet absorber has been kneaded with and blended into a general-purpose polymer. As the ultraviolet-absorbing polymer, those having an ultraviolet-absorbing skeleton in the side chain are preferred. Examples of the ultraviolet-absorbing skeleton include those exemplified in the ultraviolet absorber. In the present invention, a benzotriazole skeleton, a benzophenone skeleton, or a triazine skeleton is preferable. The ultraviolet-absorbing polymer having an ultraviolet-absorbing skeleton in the side chain is obtained by polymerizing a monomer having any of these skeletons, for example, at least one (meth)acrylic monomer selected from the (meth)acrylate compounds having any of these skeleton in the alcohol moiety thereof. Therefore, in the present invention, the ultraviolet-absorbing polymer is preferably a (meth)acrylic polymer having an ultraviolet-absorbing skeleton selected from at least any one of a benzotriazole skeleton, a benzophenone skeleton and a triazine skeleton in the side chain thereof. The ultraviolet-absorbing polymer is obtained by polymerizing a (meth)acrylic acid ester compound (monomer) having an ultraviolet-absorbing skeleton in an alcohol moiety of the (meth)acrylic acid ester compound. In polymerizing, such an ultraviolet-absorbing monomer, use may be made of one kind or a combination of two or more kinds of the ultraviolet-absorbing monomer. Preferable compounds as an ultraviolet-absorbing monomer are represented by any of the following formulae (I) to (VII). In formulas, R designates a hydrogen atom or a methyl group, and R1to R4each independently designate a substituent. m1 is an integer of 0 to 3, m2 is an integer of 0 to 4, n1 is an integer of 0 to 4, n2 is an integer of 0 to 3, and n3 is an integer of 0 to 5. L1designates a single bond or a divalent linking group, and L2designates an alkylene group. Herein, the amino group includes —NH2, an alkyl amino group, an aryl amino group, and a heterocyclic amino group. Examples of the substituent for R1to R4include a halogen atom, an alkyl group, a cycloalkyl group, an aryl group, a heterocyclic group, an alkoxy group, an aryloxy group, a heterocyclic oxy group, an alkylthio group, an arylthio group, a heterocyclic thio group, a hydroxyl group, a mercapto group, an amino group, an acyl group, an acylamino group, a sulfonamide group, a carbamoyl group, a sulfinamoyl group, an acyloxy group, an alkoxycarbonyl group, an aryloxycarbonyl group, a sulfonyl group, a carboxy group, a sulfo group, and a nitro group. R3and R4each are preferably an alkyl group, an aryl group, an alkoxy group, an aryloxy group or an amino group. The divalent linking group for L1designates —O—, —S—, —SO2—, —N(Ra)—, —C(═O)—, an alkylene group, an arylene group, a divalent heterocyclic group, and a combination of these groups. Herein, Ra designates a hydrogen atom or a substituent. Herein, examples of the combination of these groups include —C(═O)—O—, —O—C(═O)—, —N(Ra)—C(═O)—, —C(═O)—N(Ra)—, -alkylene-O—, —O-alkylene-O—, -alkylene-S—, -alkylene-N(Ra)—, -arylene-O—, —O-arylene-O—, -arylene-S—, and -arylene-N(Ra)—. The number of carbon atoms of the alkylene group for L2is preferably 1 to 20, more preferably 2 to 18, and further preferably 2 to 8. Examples thereof include methylene, ethylene, propylene, trimethylene, butylene, hexylene, and octylene. Meanwhile, preferable compounds of any of the ultraviolet absorbers can be represented by any of the same formulas as any of the above-described formulas (I) to (VII) from each of which -L1-L2-O—C(═O)—C(R)═CH2is eliminated. Examples of these ultraviolet-absorbing monomers include 2-[3-(2H-1,2,3-benzotriazole-2-yl)-4-hydroxyphenyl]ethyl methacrylate, 2-[2-(2-hydroxy-4-octyloxyphenyl)-2H-1,2,3-benzotriazole-5-yl-oxy]ethyl methacrylate, 2-[2-hydroxy-5-(methacryloyloxymethyl)phenyl]-2H-benzotriazole, 2-(4,6-dipheny-1,3,5-triazine-2-yl)-5-[2-(acryloyloxy)ethoxy]phenol, 2-(4,6-dipheny-1,3,5-triazine-2-yl)-5-[2-(methacryloyloxy)ethoxy]phenol, and the like. Other monomer constituents that can be copolymerized with the above-described ultraviolet-absorbing monomers are not particularly limited and may be adequately selected and used. Examples thereof include (meth)acrylic acid alkyl esters, such as methyl (meth)acrylate, ethyl (meth)acrylate, propyl (meth)acrylate, isopropyl (meth)acrylate, butyl (meth)acrylate, isobutyl (meth)acrylate, t-butyl (meth)acrylate, 2-ethylhexyl (meth)acrylate, octyl (meth)acrylate, nonyl (meth)acrylate, lauryl (meth)acrylate, and stearyl (meth)acrylate. Further, examples thereof include hydroxyl group-containing unsaturated monomers, such as hydroxyethyl (meth)acrylate, hydroxypropylethtyl (meth)acrylate, and hydroxybutyl (meth)acrylate. The proportion of the ultraviolet-absorbing monomer constituent of the total monomer constituents that constitute the ultraviolet-absorbing polymer is preferably 50% by mass or more. The mass average molecular weight of the ultraviolet-absorbing polymer is preferably from about 10,000 to about 200,000. As the ultraviolet-absorbing polymer, use may be made of a commercially available product. Examples thereof include VANARESIN UVA-5080, VANARESIN UVA-5080 (OHV20), VANARESIN UVA-7075, VANARESIN UVA-7075 (OHV20), VANARESIN UVA-55T, VANARESIN UVA-55MHB, VANARESIN UVA-73T, NEWCOAT UVA-101, NEWCOAT UVA-102, NEWCOAT UVA-103 and NEWCOAT UVA-104 (each trade name, manufactured by Shin-Nakamura Chemical Co., Ltd.). In the present invention, the ultraviolet-absorbing polymer may be used as a base resin without any other base resins. In other words, the ultraviolet-absorbing polymer may be used alone as a resin that constitutes the mask material layer. Note, in the present invention, that a resin itself having an ethylenycally unsaturated group in the side chain may have an ultraviolet-absorbing skeleton in the side chain. Herein, when added and to be used to the base resin, for example, a (meth)acrylic copolymer, the content of the ultraviolet-absorbing polymer may be adjusted according to a desired laser absorption performance and the content thereof is appropriately from 5.0 to 50.0 parts by mass with respect to 100 parts by mass of the base resin, for example, a (meth)acrylic copolymer. The thickness of the mask material layer is preferably from 5 to 100 μm and more preferably from 5 to 40 μm, from the viewpoint of removal speed in plasma ashing. <Temporary-Adhesive Layer> The mask-integrated surface protective tape of the present invention has at least a substrate film and a mask material layer, and the mask material layer is provided directly on the substrate film or provided on the substrate film through a temporary-adhesive layer. In the present invention, the mask material layer is preferably provided on the substrate film through a temporary-adhesive layer. In other words, the mask material layer is arranged above the temporary-adhesive layer of the surface protective tape. The temporary-adhesive layer takes a role in protection of the patterned surface together with a mask material layer by covering an asperity (or an unevenness) of the device formed on the patterned surface to enhance adhesion property to the patterned surface. In order to make the mask-integrated surface protective tape withstand a load of the wafer-thinning step, it is preferable that the adhesion property of the temporary-adhesive layer to a mask material layer or a substrate film in the wafer-thinning step is high. On the other hand, after the wafer-thinning step, because the temporary-adhesive layer is integrally peeled with the substrate film3aafrom the mask material layer, it is preferable that the adhesion property of the temporary-adhesive layer to the mask material layer is low (high peeling property is preferable). As for the temporary-adhesive that constitutes the temporary-adhesive layer, use may be made of: temporary-adhesives that can be used in a conventional surface protective tape for processing a semiconductor wafer. The temporary-adhesive may be a radiation-curable type temporary-adhesive or a pressure-sensitive type temporary-adhesive. In a case where the mask material layer is a radiation-curable type, a pressure-sensitive type temporary-adhesive is preferred, while in a case where the mask material layer is a pressure-sensitive type, a radiation-curable type temporary-adhesive is preferred. Therefore, in the present invention, because it is preferable for the mask material layer to be a radiation-curable type, a pressure-sensitive type temporary-adhesive is preferred. The description of the mask material layer is applied to the temporary-adhesive without any change, except for the parallel ray transmittance in the wave length region of 355 nm of the mask material layer being 30% or less and the use of the ultraviolet-absorbing constituent to be used for this purpose. However, in the present invention, an ultraviolet-absorbing constituent may be contained in the temporary-adhesive layer. In this case, the content of the ultraviolet-absorbing constituent in the temporary-adhesive layer is preferably an amount to be more than 30% in terms of parallel ray absorption rate in the wavelength region of 355 nm, and it is more preferable for the temporary-adhesive layer not to contain the ultraviolet-absorbing constituent. The thickness of the temporary-adhesive layer is preferably from 5 to 100 μm from the viewpoints of more increasing protective ability of the device or the like formed on the patterned surface thereof, and more increasing adhesion to the patterned surface of the semiconductor wafer. Meanwhile, depending on the type of devices, since the asperity of the patterned surface of the semiconductor wafer is roughly from about several micro-meters to about 15 μm, the thickness of the temporary-adhesive layer is more preferably from 5 to 30 μm. Further, depending on the type of devices, the thickness of the temporary-adhesive layer is preferably equal to or more than that of the mask material layer and it is more preferable that the temporary-adhesive layer is thicker than the mask material layer. Of the mask-integrated surface protective tape of the present invention, the mask-integrated surface protective tape having a temporary-adhesive layer has a constitution as shown in fragmentaryFIGS.1(b) and1(c). In the fragmentaryFIGS.1(b) and1(c), a mask-integrated surface protective tape3has a temporary-adhesive layer3abon a substrate film3aa, and further has a mask material layer3bon the temporary-adhesive layer3ab. Herein, a tape composed of the substrate film3aaand the temporary-adhesive layer3abis a surface protective tape3a. Note, in the fragmentaryFIGS.1(b) and1(c), that in a case where the mask-integrated surface protective tape3does not have any temporary-adhesive layer3ab, a part of the surface protective tape3aacts as a substrate film3a. In the present invention, the mask material layer and the temporary-adhesive layer may contain constituents other than a resin, a curing agent and a photoradical polymerization initiator, each of which is to be used in a conventional surface protective tape for processing a semiconductor wafer. <<Method of Producing a Semiconductor Wafer>> In the present invention, a semiconductor wafer is preferably produced, particularly, through the following Steps, including Steps (a) to (d). [Steps](a) A step of, in the state of having laminated the mask-integrated surface protective tape on the side of a patterned surface of a semiconductor wafer, grinding the backing-face of the semiconductor wafer; laminating a wafer-fixing tape on the backing-face side of the ground semiconductor wafer; and supporting and fixing the wafer to a ring frame;(b) A step of, after peeling the substrate firm or integrally peeling both the substrate film and the temporary-adhesive layer from the mask-integrated surface protective tape, thereby to expose the mask material layer on top, forming an opening by cutting a portion of the mask material layer corresponding to a street of the semiconductor wafer with a laser;(c) A plasma-dicing step of segmentalizing the semiconductor wafer at the street with SF6plasma, and thereby for singulating the semiconductor wafer into semiconductor chips; and(d) An ashing step of removing the mask material layer with O2plasma. In the method of producing a semiconductor wafer according to the present invention, the use of the mask-integrated surface protective tape of the present invention may allow the production of the semiconductor wafer, through steps including the above-described Steps (a) to (d). In the method of producing a semiconductor chip applied to the mask-integrated surface protective tape of the present invention, the following Step (e), after the Step (d), is preferably included. When the production method includes the following Step (e), the following Step (f) is preferably included after the Step (e):(e) A step of picking up the semiconductor chip from the wafer-fixing tape; and(f) A step of transiting the picked-up semiconductor chip to a die bonding step. Regarding the production method of the semiconductor chip using the mask-integrated surface protective tape of the present invention (hereinafter, referred to simply as “a production method applied to the present invention”), a preferable embodiment thereof is described below with reference to drawings. However, the present invention is not limited to the following embodiments, except for those specified in the present invention. Further, the form shown in each drawing is a schematic view for facilitating the understanding of the present invention. Therefore, regarding the size, the thickness, the relative magnitude relationship and the like of each component, the large one or the small one is sometimes changed for the purpose of illustration, and the form does not show a real relation as it is. Further, the present invention is not limited to outer forms and shapes shown in these figures, except for the requirements defined by the present invention. Preferable embodiments of the production method applied to the present invention may be classified into first and second embodiments, as described below. Note that, as the apparatus, the materials and the like to be used in the following embodiments, use may be made of: an ordinary apparatus, materials and the like which have been conventionally used in the processing of the semiconductor wafer, unless otherwise specified. The conditions of use for those can be appropriately set and optimized in accordance with the intended use within a range of an ordinary method for using. Further, omitted are duplicated descriptions about the materials, structures, methods, effects, and the like, which are common to each embodiment. First Embodiment [FIG.1(a) to FIG.5(b)] The first embodiment of a production method applied to the present invention is described with reference toFIG.1(a)toFIG.5(b). Note that since these figures are schematic views showing a layer structure as described above, these do not reflect realistically the thickness of each of the substrate film, the temporary-adhesive layer, and the mask material layer. Explanation of the already-described mask-integrated surface protective tape is applied to the substrate film and the thickness of each layer. A semiconductor wafer1has a patterned face2on the surface S of which a circuit or the like of the semiconductor device is formed (seeFIG.1(a)). On this patterned surface2, a mask-integrated surface protective tape3in which a mask material layer3bhas been further provided on a temporary-adhesive layer3abof a surface protective tape3ain which the temporary-adhesive layer3abhas been provided on a substrate film3aa, is laminated (seeFIG.1(b)), whereby a semiconductor wafer1whose patterned surface2is covered with the mask-integrated surface protective tape3is obtained (seeFIG.1(c)). Herein, the fragmentaryFIGS.1(b) and1(c)show the surface protective tape3ahaving on the substrate film through the temporary-adhesive layer. In this case, the surface protective tape3ais composed of the substrate film3aaand the temporary-adhesive layer3ab. In the present invention, a mask-integrated surface protective tape3having the mask material layer provided directly on the substrate film is also included in the substrate film provided directly on the temporary-adhesive layer. In this tape, since the mask-integrated surface protective tape does not have any temporary-adhesive layer directly on the substrate film,3ain the fragmentaryFIGS.1(b) and1(c)indicates a substrate film. Therefore, in the following explanation, with respect to the mask material layer directly on the substrate film, the expressions “surface protective tape3a” and “surface protective tape” should be read as “substrate film3a” and “surface protective tape”, respectively. Then, the backing-face B of the semiconductor wafer1is ground by a wafer-grinding apparatus M1, to thin a thickness of the semiconductor wafer1(seeFIG.2(a)). On the ground backing-face B, a wafer-fixing tape4is laminated (seeFIG.2(b)), to support and fix the wafer to a ring frame F (seeFIG.2(c)). The surface protective tape3aof the mask-integrated surface protective tape3is peeled off from the semiconductor wafer1, while leaving the mask material layer3bon the semiconductor wafer1(seeFIG.3(a)), so that the mask material layer3bis exposed (uncovered) (seeFIG.3(b)). Further, laser L is irradiated from the surface S side toward a plurality of streets (not shown) appropriately formed in a grid pattern or the like onto the patterned face2, thereby to remove a portion corresponding to a street of the mask material layer3b, so that streets of the semiconductor wafer are opened (seeFIG.3(c)). For the laser irradiation with which the mask material layer3bis cut, use can be made of a laser irradiator for irradiating an ultraviolet or infrared laser light. In this laser irradiator, a laser irradiation part capable of freely moving along the street of the semiconductor wafer1is arranged, so that the laser can be irradiated, with the laser having an output controlled appropriately for removing the mask material layer3b. Meanwhile, the laser is not particularly limited to CO2and YAG lasers. However, in particular, a laser having a UV wavelength region of 355 nm which is the third harmonic of YAG laser may be preferably used in the present invention. Specifically, since this laser has very high absorption rate for various materials and does not put a thermal stress, this laser can be used for microfabrication requiring high quality. Further, since a beam diameter thereof can be narrowed when compared to a long wave laser, more microscopic processing can be performed, so that this laser can be preferably applied to the present invention. Then, a treatment with the plasma P1of SF6gas is carried out from the surface S side, thereby to etch the semiconductor wafer1which is exposed at the street portion (seeFIG.4(a)), and the semiconductor wafer is divided into individual chips7, which results in singulation (seeFIG.4(b)). After that, ashing with the plasma P2of O2gas is carried out (seeFIG.4(c)), thereby to remove the mask material layer3bremaining on the surface S (seeFIG.5(a)). Then, at last, the singulated chip7is knocked up by a pin M2, and is picked up by adsorption with a collet M3(seeFIG.5(b)). Herein, a process of etching of Si of the semiconductor wafer with the use of SF6gas is also called as a BOSCH process. This process allows a reaction of the exposed Si and a F (fluorine) atom formed from a plasmarized SF6, thereby to remove the exposed Si as silicon tetrafluoride (SiF4), which is also called as reactive ion etching (RIE). On the other hand, the removal with the O2plasma is a method which is also used as plasma cleaner in the course of a semiconductor production process, and is also called as ashing (ash-making), which is one of means for removal of the organic substance. This method is carried out, in order to clean an organic substance deposit (residue) remaining on a semiconductor device surface. Then, the materials to be used in the method described above are described. Note that the materials described below are those which can be used in all of the mask-integrated surface protective tape of the present invention and therefore are not limited to the case of using the mask-integrated surface protective tape of the present invention in the above described method. The semiconductor wafer1is a silicon wafer, on its one side, having the patterned face2on which the circuit or the like of the semiconductor device is formed. The patterned face2is a face on which the circuit or the like of the semiconductor device is formed, which has a street in a planar view. The wafer-fixing tape4is required to hold the semiconductor wafer1and to have resistance to plasma which is sustainable even if the wafer-fixing tape is subjected to the plasma dicing step. Further, in the picking-up step, a good picking-up property and also an expansion property and the like in some cases are required. As the foregoing wafer-fixing tape4, a tape similar to the surface protective tape3amay be used. Further, use may be made of any of known dicing tapes to be used in a conventional plasma dicing method, which are generally called as a dicing tape. Further, the use can be also made of a dicing die-bonding tape, in which an adhesive for die-bonding is laminated between the temporary-adhesive layer and the substrate film, in order to make it easy to transit to the dicing die-bonding step after picking-up. In order to carry out the plasma dicing and the plasma ashing, use can be made of a plasma-etching apparatus. The plasma-etching apparatus is an apparatus, which is capable of subjecting the semiconductor wafer1to dry etching, and in which a sealed treatment space is made in a vacuum chamber, to place the semiconductor wafer1on the side of the electrode for a high-frequency wave. A gas for plasma generation is supplied from the side of a gas-supplying electrode provided facing the electrode for high-frequency wave. If a high-frequency voltage is applied to the electrode for a high-frequency wave, plasma is generated between the gas-supplying electrode and the electrode for a high-frequency wave. Therefore, the resultant plasma is used. By circulating a refrigerant in a heat-producing electrode for high-frequency wave, it is possible to prevent a temperature elevation of the semiconductor wafer1due to the heat of this plasma. In accordance with the method of producing the semiconductor chip (the method of processing the semiconductor wafer), any photolithographic step or the like becomes unnecessary, which is provided with a resist to be used in the conventional plasma dicing process, by giving a mask function in the plasma dicing to the surface protective tape (substrate film) protecting the patterned face. In particular, by using the surface protective tape, a technique becomes unnecessary, in which a high level of alignment, such as printing and transferring, is required for the mask formation. Therefore the mask-integrated surface protective tape of the present invention can be easily laminated on the semiconductor wafer surface, and a mask can be easily formed by the laser equipment. Further, the mask material layer3bcan be removed with O2plasma, and therefore removal of the mask portion can be carried out by the same apparatus as the plasma dicing apparatus. In addition, the plasma dicing is carried out from the patterned face2side (surface S side), and therefore it is not necessary to turn the chip upside down before the picking-up operation. From these reasons, the facilities can be simplified, and process costs can be considerably suppressed. Second Embodiment [FIG.6(a) to6(c)] This embodiment is different from the first embodiment in the point that the second embodiment contains a step of curing the mask material layer and the temporary-adhesive layer by irradiating the mask-integrated surface protective tape3with a radiation, such as an ultraviolet light or the like, prior to the step of peeling-off the surface protective tape3ain the first embodiment. Other steps are the same as in the first embodiment. Note, in the present invention, that not the temporary-adhesive layer, but the mask material layer is preferably cured. Specifically, after laminating the mask-integrated surface protective tape3on the surface S side of the semiconductor wafer1, and laminating the wafer-fixing tape4on the ground backing-face B side of the semiconductor wafer1, and supporting and fixing it to the ring frame F (seeFIG.2(c),FIG.6(a)), ultraviolet UV is irradiated from the surface S side toward the mask-integrated surface protective tape3(seeFIG.6(b)). Then, after curing the mask material layer3bof the mask-integrated surface protective tape3, the surface protective tape3ais removed (seeFIG.6(c)), whereby the mask material layer3bis uncovered. Then, this step is transited to a step of cutting, with a laser L, a portion of the mask material layer3bcorresponding to the street. Meanwhile, the ultraviolet irradiation is performed by irradiating an ultraviolet light entirely to the mask-integrated surface protective tape from the substrate film side so that the integrated irradiation would be 500 mJ/cm2. A high-pressure mercury lamp is preferably used for the ultraviolet irradiation. In the mask-integrated surface protective tape that can be used in this embodiment, at variation with the mask-integrated surface protective tape3described in the first embodiment, use is made of a material which is capable of being cured with a radiation, such as an ultraviolet ray or the like, in the mask material layer3b. By curing the mask material layer3bwith the ultraviolet light or the like, peeling-off of the surface protective tape3afrom mask material layer3bis made easily performed. Each of the above-described embodiments is an example of the present invention and therefore the present invention is not limited to these embodiments. Accordingly, addition, deletion, modification and the like of a known process may be made in each process to the extent of no departure from the scope of the present invention. EXAMPLES The present invention will be described in more detail based on examples given below, but the invention is not meant to be limited by these. Example 1 <Production of a Mask-Integrated Surface Protective Tape> An (meth)acrylic copolymer (mass-average molecular weight: 400,000, hydroxyl value: 0 mg-KOH/g, acid value: 48.8 mg-KOH/g, Tg: −23° C.) was synthesized by mixing 20 mol % of acrylic acid, 70 mol % of butyl acrylate and 10 mol % of methyl acrylate and was subjecting to polymerization in ethyl acetate solution. To this (meth)acrylic copolymer solution, 2.0 parts by mass of TETRAD-X (manufactured by Mitsubishi Gas Chemical Company, Inc., epoxy-based curing agent) as a curing agent, was blended, with respect to 100 parts by mass of the copolymer, to obtain a temporary-adhesive composition A. Were mixed 1 mol % of methacrylic acid, 78 mol % of 2-ethylhexyl acrylate and 21 mol % of 2-hydroxyethyl acrylate. The mixture was subjected to polymerization in an ethyl acetate solution, to obtain a solution of (meth)acrylic copolymer having a mass-average molecular weight of 700,000. To the obtained copolymer, 2-methaclyroyloxyethyl isocyanate (trade name: KARENZ MOI, manufactured by Showa Denko K.K.) was adjoined, to obtain a (meth)acrylic copolymer containing an ethylenically unsaturated group (mass-average molecular weight: 700,000, double bond amount: 0.90 meq/g, hydroxyl group value: 33.5 mg-KOH/g, acid value: 5.5 mg-KOH/g, Tg: −68° C.). To 100 mass parts of this ethylenically unsaturated group-containing (meth)acrylic copolymer, 1.0 mass part of COLONATE L (isocyanate-based curing agent, manufactured by Nippon Polyurethane Industry Co., Ltd.) as a curing agent, 2.0 mass parts of IRGACURE 184 (manufactured by BASF) as a photopolymerization initiator, and 0.75 mass parts of LA-F70 (ultraviolet absorber of triazine skeleton, manufactured by ADEKA K.K.) as a ultraviolet absorber, were blended, to obtain a mask material layer-forming composition B. The above-described temporary-adhesive composition A was coated on a peeling liner so that a thickness after drying would be 30 μm, and the formed temporary-adhesive layer3abwas laminated on a substrate film3aaof a 100 μm-thick low density polyethylene (LDPE) film, to obtain a surface protective tape3ahaving a thickness of 130 μm. Further, the mask material layer-forming composition B was coated on a peeling liner so that the thickness after drying would be 10 μm, to form a mask material layer3b, and then laminated the thus-formed mask material layer3bon the surface of the temporary-adhesive layer exposed by peeling the peeling liner of the above-described surface protective tape3a, whereby to produce a 140 μm-total thick ultraviolet curable mask-integrated surface protective tape3. <Production of Semiconductor Chips> The above-obtained ultraviolet curable mask-integrated surface protective tape was laminated on the surface of a silicon wafer (diameter: 8 inches) having thereon scribe lines (streets) using a laminator DR8500III (trade name, manufactured by Nitto Seiki Co., Ltd.). After that, the face (wafer backing-face) opposite to the surface on which the above-described mask-integrated surface protective tape was laminated, was ground using DGP8760 (trade name, manufactured by DISCO Corporation) until a thickness of the wafer would be 50 μm. The ground wafer was mounted on a dicing tape (wafer-fixing tape) from the wafer backing-face side using RAD-2700F (trade name, manufactured by Lintec Corporation), and was supported and fixed to a ring frame (Step(a)). After fixed the ring frame, by irradiating an ultraviolet ray of 500 mJ/cm2from the ultraviolet curable mask-integrated surface protective tape side using a high pressure mercury lamp, an adhesive force between the mask material layer3band the surface protective tape3awas decreased, and only the surface protective tape3awas peeled while leaving only the mask material layer3bon the wafer. Then, the mask material layer on the scribe lines was removed by a YAG laser having a wavelength region of 355 nm, to form an opening on the scribe lines (Step (b)). After that, the silicon wafer was subjected to a plasma irradiation with a SF6gas as a plasma-generating gas from the mask material layer side at an etching speed of 15 μm/min for 5 minutes. By this plasma dicing, the wafer was cut and divided into individual chips (Step(c)). Then, the chips were subjected to ashing with an O2gas as a plasma-generating gas at an etching speed of 1.5 μm/min for 10 minutes, thereby to remove the mask material layer3b(Step(d)). After that, an ultraviolet ray was irradiated (irradiation dose: 200 mJ/cm2) from the dicing tape side, thereby to decrease an adhesive force of the dicing tape, and chips were picked up. Example 2 A mask-integrated surface protective tape was prepared in the same manner as in Example 1, except that the blend amount of LA-F70 (ultraviolet absorber of triazine skeleton, manufactured by ADEKA K.K.) as a ultraviolet absorber for the mask material layer-forming composition B used in Example 1 was changed from 0.75 parts by mass to 1.5 parts by mass. Thus, semiconductor chips were produced in the same manner as in Example 1. Example 3 A mask-integrated surface protective tape was prepared in the same manner as in Example 1, except that LA-F70 (ultraviolet absorber of triazine skeleton, manufactured by ADEKA K.K.) as a ultraviolet absorber for the mask material layer-forming composition B used in Example 1 was changed to LA-31 (ultraviolet absorber of triazole skeleton, manufactured by ADEKA K.K.) as a ultraviolet absorber, and that the blend amount of the ultraviolet absorber was changed from 0.75 parts by mass to 1.0 parts by mass. Thus, semiconductor chips were produced in the same manner as in Example 1. Example 4 The mask material layer-forming composition B used in Example 1 was coated, without providing any temporary-adhesive layer3abformed in Example 1, on a peeling liner, so that a thickness after drying would be 10 μm, thereby to form a mask material layer3b. By laminating the thus-formed mask material layer3bdirectly on the substrate film used in Example 1 (the thickness 100 μm of a LDPE film), an ultraviolet curable mask-integrated surface protective tape having a total thickness of 110 μm was prepared. Thus, semiconductor chips were produced in the same manner as in Example 1. Comparative Example 1 A mask-integrated surface protective tape was prepared in the same manner as in Example 1, except that, instead of the mask material layer-forming composition B used in Example 1, a mask material layer-forming composition was prepared and used, without addition of any ultraviolet absorber. Thus, semiconductor chips were produced in the same manner as in Example 1. Comparative Example 2 A mask-integrated surface protective tape was prepared in the same manner as in Example 1, except that LA-F70 (ultraviolet absorber of triazine skeleton, manufactured by ADEKA K.K.) as a ultraviolet absorber for the mask material layer-forming composition B used in Example 1 was changed to LA-31 (ultraviolet absorber of triazole skeleton, manufactured by ADEKA K.K.) as a ultraviolet absorber, and that the blend amount of the ultraviolet absorber was changed from 0.75 parts by mass to 0.25 parts by mass. Thus, semiconductor chips were produced in the same manner as in Example 1. Herein, in Comparative Examples 2, 3, 4 and 5, the parallel ray transmittance (%) of the ultraviolet absorbing material is too high to be outside of the range prescribed for the present invention. In this regard, the content of the ultraviolet absorbing material (for example, an ultraviolet absorbing polymer) has been changed to reduce it. This is because a small amount of said content results in a value “to give the parallel ray transmittance (%) that is too high (or the parallel ray absorption ratio (100%-transmittance) that is too low)”. Comparative Example 3 A mask-integrated surface protective tape was prepared in the same manner as in Example 1, except that the blend amount of LA-F70 (ultraviolet absorber of triazine skeleton, manufactured by ADEKA K.K.) as a ultraviolet absorber for the mask material layer-forming composition B used in Example 1 was changed from 0.75 parts by mass to 0.5 parts by mass. Thus, semiconductor chips were produced in the same manner as in Example 1. Example 5 A mask-integrated surface protective tape was prepared in the same manner as in Example 1, except that LA-F70 (ultraviolet absorber having a triazine skeleton, manufactured by ADEKA K.K.) that was an ultraviolet absorber for the mask material layer-forming composition B used in Example 1 was replaced with VANARESIN UVA-5080 (manufactured by Shin-Nakamura Chemical Co., Ltd., mass-average molecular weight: 40,000 to 60,000, Tg: 80° C.) of the ultraviolet absorbing polymer having a triazine skeleton in the side chain, and that the blend amount thereof was changed from 0.75 parts by mass to 5.0 parts by mass. Thus, semiconductor chips were produced in the same manner as in Example 1. Example 6 A mask-integrated surface protective tape was prepared in the same manner as in Example 1, except that LA-F70 (ultraviolet absorber having a triazine skeleton, manufactured by ADEKA K.K.) that was an ultraviolet absorber for the mask material layer-forming composition B used in Example 1 was replaced with VANARESIN UVA-5080 (manufactured by Shin-Nakamura Chemical Co., Ltd., mass-average molecular weight: 40,000 to 60,000, Tg: 80° C.) of the ultraviolet absorbing polymer having a triazole skeleton in the side chain, and that the blend amount thereof was changed from 0.75 parts by mass to 10.0 parts by mass. Thus, semiconductor chips were produced in the same manner as in Example 1. Example 7 A mask-integrated surface protective tape was prepared in the same manner as in Example 1, except that LA-F70 (ultraviolet absorber having a triazine skeleton, manufactured by ADEKA K.K.) that was an ultraviolet absorber for the mask material layer-forming composition B used in Example 1 was replaced with VANARESIN UVA-7075 (manufactured by Shin-Nakamura Chemical Co., Ltd., mass-average molecular weight: 30,000 to 50,000, Tg: 75° C.) of the ultraviolet absorbing polymer having a triazole skeleton in the side chain, and that the blend amount thereof was changed from 0.75 parts by mass to 7.5 parts by mass. Thus, semiconductor chips were produced in the same manner as in Example 1. Example 8 The mask material layer-forming composition used in Example 5 was coated, without providing any temporary-adhesive layer3abformed in Example 1, on a peeling liner, so that a thickness after drying would be 10 μm, thereby to form a mask material layer3b. By laminating the thus-formed mask material layer3bdirectly on the substrate film (the thickness 100 μm of a LDPE film) used in Example 1, an ultraviolet curable mask-integrated surface protective tape having a total thickness of 110 μm was prepared. Thus, semiconductor chips were produced in the same manner as in Example 1. Comparative Example 4 A mask-integrated surface protective tape was prepared in the same manner as in Example 7, except that the blend amount of VANARESIN UVA-7075 [manufactured by Shin-Nakamura Chemical Co., Ltd., mass-average molecular weight: 30,000 to 50,000, Tg: 75° C.] of the ultraviolet absorbing polymer having a triazole skeleton in the side chain, which polymer was used in Example 7, was changed from 7.5 parts by mass to 3.0 parts by mass. Thus, semiconductor chips were produced in the same manner as in Example 1. Comparative Example 5 A mask-integrated surface protective tape was prepared in the same manner as in Example 5, except that the blend amount of VANARESIN UVA-7075 [manufactured by Shin-Nakamura Chemical Co., Ltd., mass-average molecular weight: 30,000 to 50,000, Tg: 75° C.] of the ultraviolet absorbing polymer having a triazole skeleton in the side chain, which polymer was used in Example 5, was changed from 5.0 parts by mass to 2.5 parts by mass. Thus, semiconductor chips were produced in the same manner as in Example 1. Herein, LA-F70 and LA-31 of the ultraviolet absorbers (each manufactured by ADEKA K.K.), and VANARESIN UVA-5080 and VANARESIN UVA-7075 of the ultraviolet absorbing polymers (each manufactured by Shin-Nakamura Chemical Co., Ltd.) have the following chemical structures, respectively. <Characteristics and Performance Evaluation> The parallel ray absorption rate of each mask material layer3bso obtained was measured and calculated as in the following Test Example 1. Further, in Examples 1 to 3 and 5 to 7, and Comparative Examples 1 to 5, a peeling property evaluation of the surface protective tape3ato be peeled was performed as in the following Test Example 2. Furthermore, in Examples 4 and 8, a peeling property evaluation of the substrate film3ato be peeled was performed as in the following Test Example 2. Further, evaluations of both a cutting property at the wafer street portion and a removal property of the mask material layer, of each mask-integrated surface protective tape, thus-prepared in Examples 1 to 8 and Comparative Examples 1 to 5, were performed as in the following Test Examples 3 and 4. [Test Example 1] Evaluation of Parallel Ray Transmittance Rate of the Mask Material Layer The parallel ray transmittance rate of the mask material layer at wavelength region of 355 nm was measured by the following method. With respect to each of the mask material layers formed on a release liner, which were obtained by Examples and Comparative Examples, a parallel ray transmittance rate at the wavelength region of 355 nm from the backing side of the release liner without the mask material layer formed, was measured, using an ultraviolet and visible spectrophotometer UV-1800 (manufactured by Shimadzu Corporation). This instrument is an instrument having a light receiving section of integrating sphere system by which a total light transmittance can be measured. However, the parallel ray transmittance can be measured, by distancing the fixed position of the sample from a light entrance window of the integrating sphere by 70 mm. Meanwhile, the parallel ray transmittance of the mask material layer is a value obtained by measurement at the thickness of the mask material layer thus prepared. [Test Example 2] Peeling Property Evaluation of the Surface Protective Tape or Substrate Film The force (peel force) required when each surface protective tape in Examples 1 to 3, 5 to 7 and Comparative Examples 1 to 5 and each substrate film in Examples 4 and 8 were peeled off in the Step (b) of the above-described production steps of the semiconductor chip was evaluated according to evaluation criteria. Meanwhile, evaluation of the peeling property of the above-described surface protective tape and substrate film was conducted using RAD-2700F (trade name, manufactured by Lintech Corporation). —Criterion for Evaluation of Peeling Property of the Surface Protective Tape or Substrate Film— ⊙: Only the surface protective tape or substrate film could be simply peeled with a weak force (1.5 kgf or less). ∘: A strongish force was required for peeling (2.5 kgf or less), but only the surface protective tape or substrate film could be peeled. x: The surface protective tape or substrate film could not be peeled. Alternatively, the surface protective tape or substrate film was peeled together with the mask material layer. [Test Example 3] Cutting Property of the Wafer Street Portion with Laser Irradiation In the above-described Step (c) of the production steps of the semiconductor chip, by irradiating a YAG laser of 355 nm to the mask material layer in each of Examples and Comparative Examples, a portion of the mask material layer corresponding to the street was removed, and a cutting property at the time of opening of the semiconductor wafer street was evaluated according to the following criterion. Specifically, a laser light was irradiated, using a Galvanometer scanner, by focusing the third harmonic wave of YAG laser (355 nm) having an average output of 2.5 W and a cyclic frequency of 1 kHz on a silicon wafer surface to 25 μm diameter with a f 0 lens. The laser irradiation was scanned at a speed of 2.5 mm/sec and a portion of the mask material layer corresponding to a street was removed by repeating the laser irradiation once per line, thereby to evaluate a cutting property at the time of opening the street of the semiconductor wafer. —Evaluation Criterion of Cutting Property of Wafer Street Portion by Laser Irradiation— ⊙: Opening of the street was possible, and a residue of the mask material layer was not formed. ∘: Opening of the street was possible, but a residue of the mask material layer was formed. Δ: Opening of the street was possible in more than half thereof, but the part where the mask material layer could not be removed, occurred. x: The mask material layer could not be removed, so that opening of the street was impossible. [Test Example 4] Removal Property Evaluation of the Mask Material Layer by O2Plasma Ashing In the Step (d) of the above-described production steps of the semiconductor chips, presence or absence of the residue of the mask material of the mask material layer after O2plasma ashing (ashing for 10 minutes at the etching speed of 1.5 μm/min) in each of Examples and Comparative Examples, was examined in 3-dimensional information (magnifying power of 400 times) in a range of 640 μm in horizontal size by 480 μm in vertical size of the face, using a laser microscope (trade name: VK-X100, manufactured by Keyence Corporation). —Criterion for Removal Property Evaluation of the Mask Material Layer— ∘: No residue of the mask material layer is observed (absence of residue). x: The residue of the mask material layer is apparently observed (presence of residue) The results obtained in the Test Examples 1 to 4 are shown in Tables 1 and 2. Note that Comparative Example 1 in Table 2 is identical to Comparative Example 1 in Table 1. Herein, the expression “-” means unused. TABLE 1Ex. 1Ex. 2Ex. 3Ex. 4CEx 1CEx 2CEx. 3Layer structure:PresencePresencePresenceAbsencePresencePresencePresencepresence orabsence ofthe temporary-adhesive layerUltraviolet-LA-F70LA-F70LA-31LA-F70—LA-31LA-F70absorbingmaterialParallel ray27%10%21%27%95%65%35%transmittance (%)at 355 nmPeeling◯◯◯⊙◯◯◯property ofthe surfaceprotective tapeor substrate filmCutting◯⊙◯◯XXΔproperty ofthe waferstreet portionwith laserirradiationPresence or◯◯◯◯◯◯◯absence ofthe maskagent removalby plasma Remarks: ‘Ex’ means Example according to this invention; and ‘CEx’ means Comparative Example. TABLE 2Ex. 5Ex. 6Ex. 7Ex. 8CEx 1CEx.4CEx.5Layer structure:PresencePresencePresenceAbsencePresencePresencePresencepresence orabsence ofthe temporary-adhesive layerUltraviolet-UVA-5080UVA-5080UVA-7075UVA-5080—UVA-7075UVA-5080absorbingmaterialParallel ray29%12%22%29%95%67%37%transmittance (%)at 355 nmPeeling◯◯◯⊙◯◯◯property ofthe surfaceprotective tapeor substrate filmCutting◯⊙◯◯XXΔproperty ofthe waferstreet portionwith laserirradiationPresence or◯◯◯◯◯◯◯absence ofthe maskagent removalby plasma From the results of each Test Example in the Examples 1 to 8 and Comparative Examples 1 to 5, it is found that a mask can be formed simply, without causing any adhesive deposit (or any adhesive residue), by using the mask-integrated surface protective tape of the present invention at the time of processing a semiconductor wafer to produce a semiconductor chip, and by laminating the mask-integrated surface protective tape3on a patterned surface of the semiconductor wafer, and only by peeling the surface protective tape3a, or in a case of having the mask material layer3bdirectly on the substrate film, only by peeling the substrate film3a, from the thus-laminated mask-integrated surface protective tape3. Furthermore, it is found that an opening of the street of the semiconductor wafer is formed, without any problem, with a laser irradiation, by using the mask-integrated surface protective tape of the present invention, and further the mask material layer3bcan be removed with more certainty, by an O2plasma, whereby occurrence of defective chips can be highly suppressed. In contrast to the above, in Comparative Examples 1 to 5 in which the parallel ray transmittance of the mask material layer in a wavelength region of 355 nm was more than 30%, the cuttability at the time of opening the street portion of the semiconductor wafer by laser irradiation became worse, according to more than 30%. Having described our invention as related to the present embodiments, it is our intention that the invention not be limited by any of the details of the description, unless otherwise specified, but rather be construed broadly within its spirit and scope as set out in the accompanying claims. | 78,795 |
11862505 | DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT A processing apparatus of an embodiment of the present invention will be described below with reference to the drawings. Referring toFIG.1, a processing apparatus denoted by numeral2totally includes a wafer cassette table8on which a wafer cassette6in which plural wafers are housed is placed, a wafer carrying-out unit10that carries out a wafer from the wafer cassette6placed on the wafer cassette table8, and a wafer table12that supports the wafer carried out by the wafer carrying-out unit10. InFIGS.2A and2B, a wafer4for which processing is executed by the processing apparatus2is illustrated. In a front surface4aof the wafer4, a device region18in which plural devices14such as an IC and LSI are marked out by planned dividing lines16in a lattice manner and an outer circumferential surplus region20that surrounds the device region18are included. InFIG.2A, a boundary22between the device region18and the outer circumferential surplus region20is illustrated by a two-dot chain line for convenience. However, actually the line that indicates the boundary22does not exist. As illustrated inFIG.2B, a beveled part24is formed in the outer circumferential surplus region20of the wafer4. Furthermore, a notch26that indicates a crystal orientation is formed at a circumferential edge of the wafer4. As illustrated inFIG.3, in the wafer cassette6, plural wafers4are housed at intervals in an upward-downward direction in the state in which the front surfaces4aare oriented upward. The wafer cassette table8of the present embodiment has a top plate28on which the wafer cassette6is placed and a support plate30that supports the top plate28. The top plate28may be capable of rising and lowering and raising-lowering means that raises or lowers the top plate28and positions it to desired height may be disposed. The description will be continued with reference toFIG.3. The wafer carrying-out unit10includes a Y-axis movable component32that can move in a Y-axis direction depicted by an arrow Y inFIG.3and a Y-axis feed mechanism34that moves the Y-axis movable component32in the Y-axis direction. The Y-axis feed mechanism34has a ball screw36that is coupled to a lower end of the Y-axis movable component32and extends in the Y-axis direction and a motor38that rotates the ball screw36. The Y-axis feed mechanism34converts rotational motion of the motor38to linear motion by the ball screw36and transmits the linear motion to the Y-axis movable component32to move the Y-axis movable component32in the Y-axis direction along a pair of guide rails40that extend in the Y-axis direction. An X-axis direction depicted by an arrow X inFIG.3is a direction orthogonal to the Y-axis direction and a Z-axis direction depicted by an arrow Z inFIG.3is the upward-downward direction orthogonal to the X-axis direction and the Y-axis direction. An XY plane defined by the X-axis direction and the Y-axis direction is substantially horizontal. As illustrated inFIG.3, the wafer carrying-out unit10of the present embodiment includes a conveying arm42and a hand44that is disposed at a tip of the conveying arm42and supports the wafer4housed in the wafer cassette6. The conveying arm42is disposed over an upper surface of the Y-axis movable component32and is driven by an appropriate drive source (not illustrated) such as an air drive source or electric drive source. This drive source drives the conveying arm42and positions the hand44to an optional position in each direction of the X-axis direction, the Y-axis direction, and the Z-axis direction. In addition, the drive source inverts the hand44upside down. Referring toFIG.4, it is preferable that the hand44be a Bernoulli pad on which a negative pressure is generated by a jet of air and that supports the wafer4in a contactless manner. The hand44of the present embodiment has a C-shape as a whole and plural air jet ports46connected to a compressed air supply source (not illustrated) are formed in a single surface of the hand44. Plural guide pins48are annexed to the outer circumferential edge of the hand44at intervals in the circumferential direction. Each guide pin48is configured to be movable in a radial direction of the hand44. As illustrated inFIG.3andFIG.4, after positioning the hand44to the side of the back surface4b(lower side) of the wafer4in the wafer cassette6placed on the wafer cassette table8, the wafer carrying-out unit10jets compressed air from the air jet ports46of the hand44to generate a negative pressure on a single surface side of the hand44by the Bernoulli effect, and sucks and supports the wafer4from the side of the back surface4bin a contactless manner by the hand44. Horizontal movement of the wafer4sucked and supported by the hand44is restricted by the respective guide pins48. Then, the wafer carrying-out unit10carries out the wafer4sucked and supported by the hand44from the wafer cassette6by moving the Y-axis movable component32and the conveying arm42. As illustrated inFIG.4, the wafer carrying-out unit10of the present embodiment includes a notch detecting unit50that detects the position of the notch26of the wafer4. The notch detecting unit50includes, for example, a configuration including a light emitting element52and a light receiving element54disposed at an interval from each other in the upward-downward direction and a drive source (not illustrated) that rotates at least one of the guide pins48of the hand44. The light emitting element52and the light receiving element54can be annexed to the Y-axis movable component32or a conveyance route with the interposition of an appropriate bracket (not illustrated). Furthermore, when the guide pin48rotates by the above-described drive source, the wafer4sucked and supported by the hand44rotates due to the rotation of the guide pin48. It is preferable that the outer circumferential surface of the guide pin48rotated by the drive source be formed of appropriate synthetic rubber in order to surely transmit the rotation from the guide pin48to the wafer4. The notch detecting unit50can detect the position of the notch26by rotating the wafer4by the drive source through the guide pin48in the state in which the wafer4is sucked and supported by the hand44and the outer circumference of the wafer4is positioned between the light emitting element52and the light receiving element54. This makes it possible to adjust an orientation of the wafer4to an optional orientation. As illustrated inFIG.3, the wafer table12is disposed adjacent to the wafer carrying-out unit10. The wafer table12of the present embodiment includes an annular support part56that supports the outer circumferential surplus region20of the wafer4and causes the part on the inside relative to the outer circumferential surplus region20to be contactless and a frame support part58that is disposed around the outer circumference of the annular support part56and supports an annular frame64(seeFIG.5) to be described later. Plural suction holes60disposed at intervals in the circumferential direction are formed in the upper surface of the annular support part56and each suction hole60is connected to suction means (not illustrated). The part on the inside in the radial direction relative to the annular support part56in the wafer table12is a circular recess62that is hollow downward. When the hand44inverts by 180° to invert the front and back sides of the wafer4and the wafer4is placed on the wafer table12in the state in which the front surface4aof the wafer4is oriented downward, the outer circumferential surplus region20of the wafer4is supported by the annular support part56and the device region18of the wafer4is located in the recess62. Thus, although the wafer4is placed on the wafer table12in the state in which the front surface4a, on which the devices14are formed, is oriented downward, the devices14do not get contact with the wafer table12and therefore damage to the devices14is prevented. Furthermore, the wafer table12prevents deviation of the position of the wafer4by actuating the suction means and generating a suction force for each suction hole60to suck and hold the outer circumferential surplus region20after supporting the outer circumferential surplus region20by the annular support part56. Referring toFIG.5, the processing apparatus2further includes a frame housing unit66that houses plural ring-shaped annular frames64in which an opening part64athat houses the wafer4is formed, a frame carrying-out unit68that carries out the annular frame64from the frame housing unit66, and a frame table70that supports the annular frame64carried out by the frame carrying-out unit68. As illustrated inFIG.5, the frame housing unit66of the present embodiment includes a housing72, a rising-lowering plate74disposed to be capable of rising and lowering in the housing72, and raising-lowering means (not illustrated) that raises and lowers the rising-lowering plate74. A Z-axis guide component78that extends in the Z-axis direction is disposed on the side surface of the housing72on the far side in the X-axis direction inFIG.5. The rising-lowering plate74is supported by the Z-axis guide component78in such a manner as to be capable of rising and lowering and the raising-lowering means that raises and lowers the rising-lowering plate74is disposed inside the Z-axis guide component78. It suffices for the raising-lowering means to be, for example, a configuration having a ball screw that is coupled to the rising-lowering plate74and extends in the Z-axis direction and a motor that rotates this ball screw. A door76to which a handle76ais annexed is disposed at the side surface of the housing72on the near side in the X-axis direction inFIG.5. In the frame housing unit66, the annular frames64can be housed inside the housing72by grasping the handle76aand opening the door76. Furthermore, an opening part80is made at an upper end of the housing72. As illustrated inFIG.5, the annular frames64are housed in such a manner as to be stacked over the upper surface of the rising-lowering plate74inside the housing72. The annular frame64at the uppermost level in the plural annular frames64stacked is carried out from the opening part80of the housing72by the frame carrying-out unit68. Furthermore, when the annular frame64is carried out from the opening part80, the frame housing unit66raises the rising-lowering plate74as appropriate by the raising-lowering means and positions the annular frame64at the uppermost level to the position from which the annular frame64can be carried out by the frame carrying-out unit68. The description will be continued with reference toFIG.5. The frame carrying-out unit68includes an X-axis guide component82that is fixed to an appropriate bracket (not illustrated) and extends in the X-axis direction, an X-axis movable component84supported by the X-axis guide component82movably in the X-axis direction, an X-axis feed mechanism (not illustrated) that moves the X-axis movable component84in the X-axis direction, a Z-axis movable component86supported by the X-axis movable component84movably in the Z-axis direction, and a Z-axis feed mechanism (not illustrated) that moves the Z-axis movable component86in the Z-axis direction. It suffices for the X-axis feed mechanism of the frame carrying-out unit68to be a configuration having a ball screw that is coupled to the X-axis movable component84and extends in the X-axis direction and a motor that rotates this ball screw. It suffices for the Z-axis feed mechanism to be a configuration having a ball screw that is coupled to the Z-axis movable component86and extends in the Z-axis direction and a motor that rotates this ball screw. The Z-axis movable component86of the frame carrying-out unit68has a holding part88that holds the annular frame64. The holding part88of the present embodiment has a rectangular substrate90and plural suction pads92disposed on the lower surface of the substrate90. Each suction pad92is connected to suction means (not illustrated). The frame carrying-out unit68sucks and holds the annular frame64at the uppermost level housed in the frame housing unit66by the suction pads92of the holding part88and thereafter moves the X-axis movable component84and the Z-axis movable component86. Thereby, the frame carrying-out unit68carries out the sucked and held annular frame64at the uppermost level from the frame housing unit66. As illustrated inFIG.5, the frame table70is supported by a Z-axis guide component94in such a manner as to be capable of rising and lowering between a lowering position illustrated by solid lines and a rising position illustrated by two-dot chain lines. An appropriate drive source (for example, an air drive source or an electric drive source) that raises and lowers the frame table70between the lowering position and the rising position is annexed to the Z-axis guide component94. In the frame table70, the annular frame64carried out by the frame carrying-out unit68is received at the lowering position. As illustrated inFIG.1andFIG.5, the processing apparatus2includes a tape sticking unit98(seeFIG.1) that is disposed over the frame table70and sticks a tape96to the annular frame64, a tape-attached frame conveying unit100(seeFIG.5) that conveys the annular frame64to which the tape96is stuck (hereinafter, often referred to as “tape-attached annular frame64′”) to the wafer table12and positions the opening part64aof the annular frame64to the one surface of the wafer4supported by the wafer table12and places the tape-attached annular frame64′ on the wafer table12, and a tape pressure bonding unit102(seeFIG.1) that executes pressure bonding of the tape96of the tape-attached annular frame64′ to the one surface of the wafer4. Referring toFIG.6AandFIG.6B, the tape sticking unit98of the present embodiment includes a roll tape support part104that supports a roll tape96R into which the tape96before use is wound, a tape take-up part106that takes up the tape96used, a tape pull-out part108that pulls out the tape96from the roll tape96R, a pressure bonding part110that executes pressure bonding of the pulled-out tape96to the annular frame64, and a cutting part112that cuts the tape96protruding to the outer circumference of the annular frame64along the annular frame64. As illustrated inFIG.6AandFIG.6B, the roll tape support part104includes a support roller114supported by an appropriate bracket (not illustrated) rotatably around an axis line that extends in the X-axis direction. By the support roller114, the roll tape96R in which release paper116for protecting an adhesive surface of the tape96is annexed to the adhesive surface of the tape96and that is wound into a circular cylindrical shape is supported. The tape take-up part106includes a take-up roller118supported by an appropriate bracket (not illustrated) rotatably around an axis line that extends in the X-axis direction and a motor (not illustrated) that rotates the take-up roller118. As illustrated inFIG.6AandFIG.6B, the tape take-up part106takes up the tape96used in which a circular opening part120corresponding to the part stuck to the annular frame64is formed by rotating the take-up roller118by the motor. The description will be continued with reference toFIG.6AandFIG.6B. The tape pull-out part108includes a pull-out roller122disposed below the support roller114of the roll tape support part104, a motor (not illustrated) that rotates the pull-out roller122, and a driven roller124that rotates in association with the rotation of the pull-out roller122. The tape pull-out part108pulls out the tape96sandwiched by the pull-out roller122and the driven roller124from the roll tape96R by rotating the driven roller124together with the pull-out roller122by the motor. The release paper116is separated from the tape96that has passed between the pull-out roller122and the driven roller124and the separated release paper116is taken up by a release paper take-up part126. The release paper take-up part126of the present embodiment has a release paper take-up roller128disposed over the driven roller124and a motor (not illustrated) that rotates the release paper take-up roller128. Furthermore, the tape96from which the release paper116has been separated goes through a guide roller130disposed at an interval from the pull-out roller122in the Y-axis direction and is guided to the take-up roller118. The pressure bonding part110includes a pressing roller132disposed movably in the Y-axis direction and a Y-axis feed mechanism (not illustrated) that moves the pressing roller132in the Y-axis direction. The Y-axis feed mechanism of the pressure bonding part110can be configured from an appropriate drive source (for example, an air drive source or an electric drive source). As illustrated inFIG.6AandFIG.6B, the cutting part112includes a Z-axis guide component134that is fixed to an appropriate bracket (not illustrated) and extends in the Z-axis direction, a Z-axis movable component136supported by the Z-axis guide component134movably in the Z-axis direction, and a Z-axis feed mechanism (not illustrated) that moves the Z-axis movable component136in the Z-axis direction. It suffices for the Z-axis feed mechanism of the cutting part112to be a configuration having a ball screw that is coupled to the Z-axis movable component136and extends in the Z-axis direction and a motor that rotates this ball screw. Furthermore, the cutting part112includes a motor138fixed to the lower surface of the tip of the Z-axis movable component136and an arm piece140rotated by the motor138around an axis line that extends in the Z-axis direction. To the lower surface of the arm piece140, first and second drooping pieces142aand142bare annexed at an interval from each other. A circular cutter144is supported by the first drooping piece142arotatably around an axis line orthogonal to the Z-axis direction. A holding-down roller146is supported by the second drooping piece142brotatably around an axis line orthogonal to the Z-axis direction. The tape sticking unit98pulls out the tape96that has not been used by the pull-out roller122and the driven roller124before the frame table70that has received the annular frame64from the frame carrying-out unit68is positioned from the lowering position (a position illustrated inFIG.6A) to the rising position (a position illustrated inFIG.6B). Then, the frame table70is positioned to the rising position to such an extent that the tape96can be pressed against the annular frame64by the pressing roller132of the pressure bonding part110, and the annular frame64is brought into contact with the pressing roller132with the interposition of the tape96. Then, the pressing roller132is rolled in the Y-axis direction while the adhesive surface of the tape96is pressed against the annular frame64by the pressing roller132. This can execute the pressure bonding of the tape96pulled out from the roll tape96R by the tape pull-out part108to the annular frame64. After the tape96is pressure-bonded to the annular frame64, the tape sticking unit98lowers the Z-axis movable component136of the cutting part112by the Z-axis feed mechanism to press the cutter144against the tape96on the annular frame64and hold down the annular frame64by the holding-down roller146from over the tape96. Subsequently, the tape sticking unit98rotates the arm piece140by the motor138and causes the cutter144and the holding-down roller146to move to draw a circle along the annular frame64. This can cut the tape96that protrudes to the outer circumference of the annular frame64along the annular frame64. Furthermore, because the annular frame64is held down by the holding-down roller146from over the tape96, deviation of the position of the annular frame64and the tape96is prevented when the tape96is being cut. Then, after the frame table70is lowered, the tape96used in which the circular opening part120corresponding to the part stuck to the annular frame64is formed is taken up by the tape take-up part106. As illustrated inFIG.5, the tape-attached frame conveying unit100includes a Y-axis guide component148that is fixed to an appropriate bracket (not illustrated) and extends in the Y-axis direction, a Y-axis movable component150supported by the Y-axis guide component148movably in the Y-axis direction, a Y-axis feed mechanism (not illustrated) that moves the Y-axis movable component150in the Y-axis direction, a Z-axis movable component152supported by the Y-axis movable component150movably in the Z-axis direction, and a Z-axis feed mechanism (not illustrated) that moves the Z-axis movable component152in the Z-axis direction. It suffices for the Y-axis feed mechanism of the tape-attached frame conveying unit100to be a configuration having a ball screw that is coupled to the Y-axis movable component150and extends in the Y-axis direction and a motor that rotates this ball screw. It suffices for the Z-axis feed mechanism to be a configuration having a ball screw that is coupled to the Z-axis movable component152and extends in the Z-axis direction and a motor that rotates this ball screw. The Z-axis movable component152of the tape-attached frame conveying unit100has a holding part154that holds the tape-attached annular frame64′. The holding part154of the present embodiment has a rectangular substrate156and plural suction pads158disposed on the lower surface of the substrate156. Each suction pad158is connected to suction means (not illustrated). The tape-attached frame conveying unit100sucks and holds the upper surface of the tape-attached annular frame64′ supported by the frame table70in the state in which the adhesive surface of the tape96is oriented downward by the respective suction pads158of the holding part154, and moves the Y-axis movable component150and the Z-axis movable component152. Thereby, the tape-attached frame conveying unit100conveys the tape-attached annular frame64′ sucked and held by the holding part154from the frame table70to the wafer table12, and positions the opening part64aof the annular frame64to the one surface of the wafer4supported by the wafer table12and places the tape-attached annular frame64′ on the wafer table12. The tape pressure bonding unit102will be described with reference toFIG.7toFIG.9. As illustrated inFIG.7, the tape pressure bonding unit102includes an upper chamber160disposed over the wafer table12, a lower chamber162in which the wafer table12is housed, and a raising-lowering mechanism164that raises and lowers the upper chamber160and generates a closed state in which the upper chamber160is brought into contact with the lower chamber162and an opened state in which the upper chamber160is separated from the lower chamber162. The tape pressure bonding unit102further includes a vacuum part166that sets the upper chamber160and the lower chamber162to a vacuum state in the closed state and an opening-to-atmosphere part168that opens the upper chamber160and the lower chamber162to the atmosphere. As illustrated inFIG.7, the upper chamber160of the present embodiment includes a circular top plate170and a circular cylindrical sidewall172that droops from the circumferential edge of the top plate170. The raising-lowering mechanism164that can be configured from an appropriate actuator such as an air cylinder is mounted on the upper surface of the top plate170. In a housing space defined by the lower surface of the top plate170and the inner circumferential surface of the sidewall172, a pressing roller174for pressing the tape96of the tape-attached annular frame64′ against the one surface of the wafer4supported by the wafer table12, a support piece176that supports the pressing roller174rotatably, and a Y-axis feed mechanism178that moves the support piece176in the Y-axis direction are disposed. The Y-axis feed mechanism178has a ball screw180that is coupled to the support piece176and extends in the Y-axis direction and a motor182that rotates the ball screw180. Furthermore, the Y-axis feed mechanism178converts rotational motion of the motor182to linear motion by the ball screw180and transmits the linear motion to the support piece176to move the support piece176along a pair of guide rails184that extend in the Y-axis direction. As illustrated inFIG.7, the lower chamber162has a circular cylindrical sidewall186. The upper part of the sidewall186is opened and the lower part of the sidewall186is closed. A connection opening188is formed in the sidewall186. The vacuum part166that can be configured from an appropriate vacuum pump is connected to the connection opening188through a flow path190. The opening-to-atmosphere part168that can be configured from an appropriate valve capable of opening the flow path190to the atmosphere is disposed on the flow path190. In the state in which the tape96of the tape-attached annular frame64′ is positioned to the one surface of the wafer4supported by the wafer table12, the tape pressure bonding unit102lowers the upper chamber160by the raising-lowering mechanism164and brings the lower end of the sidewall172of the upper chamber160into contact with the upper end of the sidewall186of the lower chamber162to set the upper chamber160and the lower chamber162to the closed state. In addition, the tape pressure bonding unit102brings the pressing roller174into contact with the tape-attached annular frame64′. Subsequently, the tape pressure bonding unit102actuates the vacuum pump that configures the vacuum part166in the state in which the valve that configures the opening-to-atmosphere part168is closed, to set the inside of the upper chamber160and the lower chamber162to a vacuum state. Thereafter, as illustrated inFIG.8andFIG.9, the tape pressure bonding unit102rolls the pressing roller174in the Y-axis direction by the Y-axis feed mechanism178to thereby execute pressure bonding of the tape96to the one surface of the wafer4and generate a frame unit U. In the present embodiment, the pressure bonding of the wafer4and the tape96is executed in the state in which the inside of the upper chamber160and the lower chamber162is set to the vacuum state. Thus, when the opening-to-atmosphere part168is opened after the tape96is pressure-bonded, the tape96is pressed against the wafer4by the atmospheric pressure. Due to this, the tape96gets close contact with the one surface of the wafer4. As illustrated inFIG.1andFIG.10, the processing apparatus2further includes frame unit carrying-out means192that carries out, from the wafer table12, the frame unit U in which the tape96of the tape-attached annular frame64′ and the one surface of the wafer4are pressure-bonded by the tape pressure bonding unit102and a beveled part removing unit194that cuts and removes, in a ring manner, the beveled part24formed in the outer circumferential surplus region20from the wafer4of the frame unit U carried out by the frame unit carrying-out means192. The processing apparatus2includes also beveled part-free unit carrying-out means196(seeFIG.1) that carries out the beveled part-free unit resulting from the removal of the beveled part24, in a ring manner, from the beveled part removing unit194and a frame cassette table200(seeFIG.1) on which a frame cassette198that houses the beveled part-free unit carried out by the beveled part-free unit carrying-out means196is placed. As illustrated inFIG.10, the frame unit carrying-out means192of the present embodiment includes a frame unit holding part202including a wafer holding part202athat holds the wafer4and a frame holding part202bthat holds the annular frame64and a conveying part206that conveys the frame unit holding part202to a temporary placement table204. The wafer holding part202aof the frame unit holding part202includes a circular substrate208and a circular suction adhesion piece210mounted on the lower surface of the substrate208. Plural suction holes (not illustrated) are formed in the lower surface of the suction adhesion piece210and each suction hole is connected to suction means (not illustrated). The frame holding part202bincludes plural (in the present embodiment, four) protruding pieces212that protrude outward in the radial direction from the circumferential edge of the substrate208of the wafer holding part202awith the interposition of intervals in the circumferential direction and suction pads214annexed to the lower surfaces of the protruding pieces212. Each suction pad214is connected to suction means (not illustrated). The conveying part206includes an X-axis guide component216that is fixed to an appropriate bracket (not illustrated) and extends in the X-axis direction, an X-axis movable component218supported by the X-axis guide component216movably in the X-axis direction, and an X-axis feed mechanism (not illustrated) that moves the X-axis movable component218in the X-axis direction. The conveying part206further includes a Z-axis movable component220supported by the X-axis movable component218movably in the Z-axis direction, a Z-axis feed mechanism (not illustrated) that moves the Z-axis movable component220in the Z-axis direction, a Y-axis movable component222supported by the Z-axis movable component220movably in the Y-axis direction, and a Y-axis feed mechanism (not illustrated) that moves the Y-axis movable component222in the Y-axis direction. The substrate208of the wafer holding part202ais coupled to the tip of the Y-axis movable component222. It suffices for each of the X-axis, Y-axis, and Z-axis feed mechanisms of the conveying part206to be a configuration having a ball screw and a motor that rotates the ball screw. It is preferable for the frame unit carrying-out means192to include a two-dimensional movement mechanism that two-dimensionally moves the frame unit holding part202in the horizontal direction and an imaging part224that images the outer circumference of the wafer4of the frame unit U held by the frame unit holding part202. In the present embodiment, the frame unit holding part202two-dimensionally moves in the horizontal direction in the XY plane by the X-axis feed mechanism and the Y-axis feed mechanism of the conveying part206, and the two-dimensional movement mechanism is configured by the conveying part206. Furthermore, the imaging part224of the present embodiment is disposed between the wafer table12and the temporary placement table204and the outer circumference of the wafer4of the frame unit U held by the frame unit holding part202is imaged from the lower side of the wafer4. The frame unit carrying-out means192actuates the conveying part206in the state in which the wafer4is sucked and held from the side of the back surface4b(side of the tape96) by the suction adhesion piece210of the wafer holding part202aand the annular frame64is sucked and held by the suction pads214of the frame holding part202b. Thereby, the frame unit carrying-out means192carries out the frame unit U held by the frame unit holding part202from the wafer table12. Furthermore, the frame unit carrying-out means192of the present embodiment measures the coordinates of at least three points at the outer circumference of the wafer4by actuating the conveying part206that configures the two-dimensional movement mechanism and imaging, by the imaging part224, at least three places at the outer circumference of the wafer4of the frame unit U held by the frame unit holding part202, and obtains the center coordinates of the wafer4on the basis of the measured coordinates of the three points. Then, the frame unit carrying-out means192makes the center of the wafer4correspond with the center of the temporary placement table204and temporarily places the frame unit U on the temporary placement table204. As illustrated inFIG.10, the temporary placement table204is disposed at an interval from the wafer table12in the X-axis direction. The temporary placement table204of the present embodiment includes an annular support part226that supports the outer circumferential surplus region20of the wafer4of the frame unit U and causes the part on the inside relative to the outer circumferential surplus region20to be contactless and a frame support part228that is disposed around the outer circumference of the annular support part226and supports the annular frame64. The part on the inside in the radial direction relative to the annular support part226is a circular recess230that is hollow downward. It is preferable that the frame support part228of the temporary placement table204include a heater (not illustrated) and the tape96be softened by heating the tape96of the frame unit U temporarily placed on the temporary placement table204by the heater and the tape96be brought into closer contact with the root of the beveled part24. The processing apparatus2of the present embodiment includes a temporary placement table conveying part232that conveys the temporary placement table204in the Y-axis direction. The temporary placement table conveying part232includes a Y-axis guide component234that extends in the Y-axis direction, a Y-axis movable component236supported by the Y-axis guide component234movably in the Y-axis direction, and a Y-axis feed mechanism238that moves the Y-axis movable component236in the Y-axis direction. The temporary placement table204is fixed to the upper part of the Y-axis movable component236. The Y-axis feed mechanism238has a ball screw240that is coupled to the Y-axis movable component236and extends in the Y-axis direction and a motor242that rotates the ball screw240. Furthermore, the temporary placement table conveying part232converts rotational motion of the motor242to linear motion by the ball screw240and transmits the linear motion to the Y-axis movable component236to convey the temporary placement table204in the Y-axis direction together with the Y-axis movable component236. As illustrated inFIG.1andFIG.10, the beveled part removing unit194includes a laser beam irradiation unit244that irradiates the base of the beveled part24formed at the outer circumference of the wafer4with a laser beam to form a cut groove or a modified layer inside of the wafer, a first raising-lowering table246(seeFIG.1) that holds and raises the frame unit U temporarily placed on the temporary placement table204and moves in the X-axis direction to position the frame unit U to the laser beam irradiation unit244, and a separating part248that separates the beveled part24from the cut groove or the modified layer into a ring manner. As illustrated inFIG.10, the laser beam irradiation unit244includes a housing250disposed adjacent to the temporary placement table204in the X-axis direction, a laser oscillator (not illustrated) that is housed in the housing250and emits a laser beam, and a light collector252that collects the laser beam emitted by the laser oscillator and irradiates the base of the beveled part24formed at the outer circumference of the wafer4with the laser beam. The laser beam irradiation unit244further includes a suction nozzle254that sucks debris generated when the wafer4is irradiated with the laser beam and suction means (not illustrated) connected to the suction nozzle254. The light collector252extends upward from the upper surface of the housing250with an inclination toward the side of the suction nozzle254. Due to this, dropping of debris generated in the irradiation with the laser beam onto the light collector252is suppressed. Furthermore, the suction nozzle254extends upward from the upper surface of the housing250with an inclination toward the side of the light collector252. As illustrated inFIG.11, the laser beam irradiation unit244irradiates the base part (a part slightly closer to the inside than the outer circumferential edge of the wafer4) of the beveled part24formed at the outer circumference of the wafer4with a laser beam LB while rotating the frame unit U held by the first raising-lowering table246, to form a ring-shaped cut groove256along the base part of the beveled part24by ablation processing or form a modified layer into a ring manner along the base part of the beveled part24. Furthermore, in the case of forming the cut groove256, the laser beam irradiation unit244sucks debris generated due to the ablation processing by the suction nozzle254. As illustrated inFIG.1, the first raising-lowering table246is disposed over the temporary placement table204movably in the X-axis direction and movably in the Z-axis direction. Referring toFIGS.12A to12C, the first raising-lowering table246includes an X-axis guide component258that is fixed to an appropriate bracket (not illustrated) and extends in the X-axis direction, an X-axis movable component260supported by the X-axis guide component258movably in the X-axis direction, an X-axis feed mechanism (not illustrated) that moves the X-axis movable component260in the X-axis direction, a Z-axis movable component262supported by the X-axis movable component260movably in the Z-axis direction, and a Z-axis feed mechanism (not illustrated) that moves the Z-axis movable component262in the Z-axis direction. It suffices for each of the X-axis and Z-axis feed mechanisms of the first raising-lowering table246to be a configuration having a ball screw and a motor that rotates the ball screw. A support shaft264that extends downward is rotatably supported by the lower surface of the tip of the Z-axis movable component262. A motor266that rotates the support shaft264around an axis line extending in the Z-axis direction is attached to the upper surface of the tip of the Z-axis movable component262. A circular holding piece268is fixed to the lower end of the support shaft264. As illustrated inFIG.12B, a wafer suction adhesion chuck400with a circular shape and plural frame suction adhesion chucks402disposed around the wafer suction adhesion chuck400are mounted on the lower surface of the holding piece268. A diameter of the wafer suction adhesion chuck400is slightly smaller than that of the device region18of the wafer4. The plural frame suction adhesion chucks402are disposed on a circular circumference corresponding to a size of the annular frame64at intervals in the circumferential direction. Furthermore, the wafer suction adhesion chuck400and the frame suction adhesion chucks402are formed of a porous material and are connected to suction means (not illustrated). The first raising-lowering table246sucks and holds, by the wafer suction adhesion chuck400, the wafer4of the frame unit U in which the tape96has been heated by the heater of the frame support part228of the temporary placement table204and the tape96is in close contact with the root of the beveled part24, and sucks and holds the annular frame64by the frame suction adhesion chucks402. Thereafter, the first raising-lowering table246moves the Z-axis movable component262and the X-axis movable component260to raise the frame unit U sucked and held by the holding piece268and move the frame unit U in the X-axis direction and position it to the laser beam irradiation unit244. Furthermore, when the wafer4is irradiated with the laser beam LB by the laser beam irradiation unit244, the first raising-lowering table246actuates the motor266to rotate the frame unit U sucked and held by the holding piece268. Moreover, the first raising-lowering table246moves the frame unit U in which the cut groove256or the modified layer is formed at the base of the beveled part24in the X-axis direction and the Z-axis direction and temporarily places it on the temporary placement table204. As illustrated inFIGS.12A to12C, the beveled part removing unit194of the present embodiment has a cut groove detecting unit404that detects the cut groove256formed through the irradiation of the base of the beveled part24formed at the outer circumference of the wafer4with the laser beam LB. The cut groove detecting unit404includes an annular illuminating part406disposed in the lower surface of the holding piece268of the first raising-lowering table246and a light receiving part408disposed adjacent to the first raising-lowering table246. As illustrated inFIG.12C, the diameter of the illuminating part406is almost the same as that of the cut groove256and the illuminating part406is located above the cut groove256when the frame unit U is held by the holding piece268. Furthermore, the light receiving part408is supported by the X-axis guide component258through a bracket410and the light receiving part408is located below the cut groove256when the frame unit U is held by the holding piece268. Moreover, in the cut groove detecting unit404, the cut groove256is detected by receiving light of the illuminating part406by the light receiving part408while rotating the frame unit U held by the first raising-lowering table246. More specifically, the cut groove detecting unit404detects whether or not the cut groove256has reached the back surface4bfrom the front surface4aof the wafer4, i.e. whether or not the wafer4has been completely cut. When the cut groove256has reached the back surface4bfrom the front surface4aof the wafer4and the wafer4has been completely cut, the light of the illuminating part406passes through the cut groove256and reaches the light receiving part408. Therefore, the amount of light received by the light receiving part408becomes comparatively large. The light of the illuminating part406is transmitted through the tape96and therefore the amount of light received by the light receiving part408is not affected by the tape96. On the other hand, when the cut groove256has not reached the back surface4bfrom the front surface4aof the wafer4and an incompletely-cut part that has not been completely cut exists in the wafer4, the light of the illuminating part406is blocked by the incompletely-cut part. Therefore, the amount of light received by the light receiving part408becomes comparatively small when the incompletely-cut part is located above the light receiving part408. Thus, the cut groove detecting unit404determines that the wafer4has been completely cut when the amount of light received by the light receiving part408is equal to or larger than a predetermined threshold over the whole circumference of the cut groove256. Conversely, the cut groove detecting unit404determines that the wafer4has not been completely cut when a region about which the amount of light received by the light receiving part408is smaller than the above-described threshold exists. In an example illustrated inFIG.13, the amount of light received by the light receiving part408is equal to or larger than a threshold T1in a region in which the rotation angle of the wafer4is 0° to θ1 and a region in which it is θ2 to 360°. However, the amount of light received by the light receiving part408is smaller than the threshold T1in a region in which the rotation angle of the wafer4is θ1 to θ2. Therefore, it is determined that an incompletely-cut part exists in the wafer4. The cut groove detecting unit404may include, instead of the above-described light receiving part408, a camera that images the cut groove256from the lower side when the frame unit U is held by the holding piece268, and it is also possible to detect whether or not the cut groove256has reached the back surface4bfrom the front surface4aof the wafer4on the basis of an image of the cut groove256imaged by the camera. As illustrated inFIG.1, the separating part248is disposed at an interval from the first raising-lowering table246in the Y-axis direction in the movable range of the temporary placement table204in the Y-axis direction. Referring toFIG.14AandFIG.16, the separating part248includes ultraviolet irradiation parts270(seeFIG.14A) that irradiate the tape96corresponding to the cut groove256with ultraviolet to reduce the adhesive force of the tape96and a second raising-lowering table272(seeFIG.14A) that sucks and holds the inside of the wafer4in such a manner that the beveled part24is exposed from the outer circumference, and supports the annular frame64. The separating part248further includes a separator274(seeFIG.14A) that acts on the beveled part24and separates the beveled part24into a ring manner and a discard part276(seeFIG.16) by which the separated beveled part24is discarded. As illustrated inFIG.14A, the separating part248of the present embodiment includes a Z-axis guide component278that is fixed to an appropriate bracket (not illustrated) and extends in the Z-axis direction, a Z-axis movable component280supported by the Z-axis guide component278movably in the Z-axis direction, and a Z-axis feed mechanism (not illustrated) that moves the Z-axis movable component280in the Z-axis direction. It suffices for the Z-axis feed mechanism to be a configuration having a ball screw that is coupled to the Z-axis movable component280and extends in the Z-axis direction and a motor that rotates this ball screw. A support piece282is supported and a support shaft286is rotatably supported by the lower surface of the tip of the Z-axis movable component280. The above-described second raising-lowering table272is coupled to the support shaft286. A motor284that rotates the second raising-lowering table272together with the support shaft286is attached to the upper surface of the tip of the Z-axis movable component280. A pair of the above-described ultraviolet irradiation parts270are annexed to the support piece282of the present embodiment at an interval in the Y-axis direction. The second raising-lowering table272is circular and the diameter of the second raising-lowering table272is slightly smaller than that of the device region18of the wafer4. Plural suction holes (not illustrated) are formed in the lower surface of the second raising-lowering table272and each suction hole is connected to suction means. Furthermore, the above-described separator274is mounted on the support piece282. The separator274includes a pair of movable pieces288disposed on the lower surface of the support piece282at an interval movably in the longitudinal direction of the support piece282and a pair of a feed mechanism290that move the pair of movable pieces288. Each of the pair of feed mechanisms290can be configured from an appropriate actuator such as an air cylinder or an electric cylinder. The separator274includes a pair of clamping rollers292aand292bsupported by each movable piece288at an interval in the upward-downward direction and Z-axis feed mechanisms294that move the upper clamping roller292ain the Z-axis direction. The Z-axis feed mechanisms294can be configured from an appropriate actuator such as an air cylinder or an electric cylinder. The respective clamping rollers292aand292bare supported by the movable piece288rotatably around an axis line that extends in the X-axis direction. A pressing roller298is mounted to the upper clamping roller292awith the interposition of a support shaft296. Referring toFIG.16, the discard part276includes a belt conveyor300that conveys the separated beveled part24and a dust box302in which the beveled part24conveyed by the belt conveyor300is housed. The belt conveyor300is positioned by an appropriate actuator (not illustrated) to a collection position (a position illustrated by solid lines inFIG.16) at which the belt conveyor300horizontally extends substantially and a standby position (a position illustrated by two-dot chain lines inFIG.16) at which the belt conveyor300vertically extends substantially. A door304to which a handle304ais annexed is disposed at the side surface of the dust box302on the near side in the X-axis direction inFIG.16. A crusher (not illustrated) that crushes the collected beveled part24is attached inside the dust box302. In the dust box302, by grasping the handle304aand opening the door304, crushed waste of the collected beveled part24housed in the dust box302can be taken out. When the temporary placement table204on which the frame unit U in which the cut groove256is formed at the base of the beveled part24is temporarily placed is positioned below the separating part248by the temporary placement table conveying part232, as illustrated inFIG.15, the separating part248sucks and holds the side of the back surface4bof the wafer4of the frame unit U by the second raising-lowering table272and clamps the annular frame64by the clamping rollers292aand292bof the separator274. Then, the separating part248executes irradiation with ultraviolet from the pair of ultraviolet irradiation parts270and reduces the adhesive force of the tape96stuck to the beveled part24. In addition, the separating part248rotates, by the motor284, the frame unit U together with the support shaft286and the second raising-lowering table272relative to the separator274while pressing the beveled part24downward by the pressing rollers298. Thereby, the separating part248separates the beveled part24from the frame unit U. The separated beveled part24is conveyed to the dust box302by the belt conveyor300and is collected. When the beveled part24is separated, the separator274may be rotated relative to the frame unit U. As illustrated inFIG.14andFIG.15, the beveled part removing unit194of the present embodiment has a removal detecting unit412that detects whether or not the beveled part24has been removed. The removal detecting unit412is disposed adjacent to the ultraviolet irradiation part270. The removal detecting unit412has a main body414supported by the support piece282and a light emitting part416and a light receiving part418that are both mounted on the lower surface of the main body414. As illustrated inFIG.15, the light emitting part416executes irradiation with light L1toward the region in which the beveled part24has existed for the frame unit U that is held by the second raising-lowering table272and from which the beveled part24has been removed. Furthermore, the light receiving part418receives reflected light L2arising from reflection of the light L1of the light emitting part416at the beveled part24that remains without being removed. Moreover, in the removal detecting unit412, the region in which the beveled part24has existed is irradiated with the light L1from the light emitting part416while the frame unit U that is held by the second raising-lowering table272and from which the beveled part24has been removed is rotated, and whether or not the beveled part24has been completely removed is detected depending on whether or not the amount of light received by the light receiving part418is smaller than a predetermined threshold. When the beveled part24has been removed, the tape96is irradiated with the light L1of the light emitting part416. Therefore, the reflected light L2hardly exists and the amount of light received by the light receiving part418becomes comparatively small. On the other hand, when at least part of the beveled part24remains without being removed, the light L1of the light emitting part416is reflected by the beveled part24that remains and therefore the amount of light received by the light receiving part418becomes comparatively large. Thus, the removal detecting unit412determines that the beveled part24has been completely removed when the amount of light received by the light receiving part418is smaller than the predetermined threshold over the whole circumference of the wafer4. Conversely, the removal detecting unit412determines that at least part of the beveled part24remains without being removed when a region about which the amount of light received by the light receiving part418is equal to or larger than the predetermined threshold exists. As illustrated inFIG.1, the beveled part-free unit carrying-out means196is disposed adjacent to the beveled part removing unit194. Referring toFIG.17andFIG.18, the beveled part-free unit carrying-out means196of the present embodiment includes an inversion mechanism308(seeFIG.17) that includes a frame holding part306that faces the beveled part-free unit supported by the second raising-lowering table272and holds the annular frame64and moves toward the frame cassette table200and inverts the frame holding part306, a beveled part-free unit support part310(seeFIG.18) that supports the beveled part-free unit that is inverted by the inversion mechanism308and in which the front surface4aof the wafer4is oriented upward, and a pushing part312(seeFIG.18) that causes the beveled part-free unit supported by the beveled part-free unit support part310to enter the frame cassette198placed on the frame cassette table200and be housed therein. As illustrated inFIG.17, the inversion mechanism308includes a Y-axis guide component314that extends in the Y-axis direction, a Y-axis movable component316supported by the Y-axis guide component314movably in the Y-axis direction, a Y-axis feed mechanism (not illustrated) that moves the Y-axis movable component316in the Y-axis direction, an arm318supported by the Y-axis movable component316movably in the Z-axis direction, and a Z-axis feed mechanism (not illustrated) that moves the arm318in the Z-axis direction. It suffices for each of the Y-axis and Z-axis feed mechanisms of the inversion mechanism308to be a configuration having a ball screw and a motor that rotates the ball screw. The above-described frame holding part306is supported by the arm318in such a manner as to be capable of vertically inverting. In addition, a motor320that vertically inverts the frame holding part306is attached to the arm318. The frame holding part306of the present embodiment includes a substrate324rotatably supported by the arm318through a pair of rotating shafts322and plural suction pads326annexed to a single surface of the substrate324. Each suction pad326is connected to suction means (not illustrated). Furthermore, one rotating shaft322is coupled to the motor320. In the state in which the suction pads326are oriented upward, the inversion mechanism308sucks and holds, by the suction pads326, the lower surface of the annular frame64of a beveled part-free unit U′ supported by the second raising-lowering table272and receives the beveled part-free unit U′ from the second raising-lowering table272. Furthermore, the inversion mechanism308inverts the frame holding part306by the motor320to orient the front surface4aof the wafer4upward, and then moves the beveled part-free unit U′ held by the frame holding part306toward the frame cassette table200by moving the Y-axis movable component316. As illustrated inFIG.18, the beveled part-free unit support part310of the present embodiment includes a pair of support plates328supported through an appropriate bracket (not illustrated) movably in the X-axis direction and interval adjusting means (not illustrated) that adjusts the interval between the pair of support plates328in the X-axis direction. The interval adjusting means can be configured from an appropriate actuator such as an air cylinder or an electric cylinder. A heater (not illustrated) is mounted on the pair of support plates328that support the beveled part-free unit U′. In the state in which the interval between the pair of support plates328is narrowed, the pair of support plates328heat the tape96of the beveled part-free unit U′ by the heater and thereby eliminate slack and wrinkles of the tape96caused due to the removal of the beveled part24. The description will be continued with reference toFIG.18. The pushing part312of the present embodiment includes a Y-axis guide component330that extends in the Y-axis direction, a Y-axis movable component332supported by the Y-axis guide component330movably in the Y-axis direction, and a Y-axis feed mechanism (not illustrated) that moves the Y-axis movable component332in the Y-axis direction. The Y-axis movable component332has a base part334supported by the Y-axis guide component330, a support column336that extends upward from the upper surface of the base part334, and a pressing piece338annexed to the upper end of the support column336. It suffices for the Y-axis feed mechanism of the pushing part312to be a configuration having a ball screw that is coupled to the Y-axis movable component332and extends in the Y-axis direction and a motor that rotates this ball screw. As illustrated inFIG.19, the beveled part-free unit support part310expands the interval between the pair of support plates328by the interval adjusting means before receiving the beveled part-free unit U′, and then receives the beveled part-free unit U′ held by the suction pads326. Then, when the beveled part-free unit support part310has received the beveled part-free unit U′, the pushing part312moves the Y-axis movable component332in the Y-axis direction by the Y-axis feed mechanism and thereby causes, by the pressing piece338, the beveled part-free unit U′ supported by the beveled part-free unit support part310to enter the frame cassette198placed on the frame cassette table200and be housed therein. In the frame cassette198illustrated inFIG.1andFIG.19, plural beveled part-free units U′ are housed at intervals in the upward-downward direction. As illustrated inFIG.18andFIG.19, the frame cassette table200includes a placement part340on which the frame cassette198is placed and a raising-lowering part342that raises and lowers the placement part340and positions it to an optional height. It suffices for the raising-lowering part342to be a configuration having a ball screw that is coupled to the placement part340and extends in the Z-axis direction and a motor that rotates this ball screw. Next, description will be made about a processing method in which, by using the above-described processing apparatus2, the dicing tape96is stuck to the wafer4in which the beveled part24is formed in the outer circumferential surplus region20to integrate the wafer4with the annular frame64and the beveled part24is cut to be removed in a ring manner from the wafer4. In the present embodiment, first, as illustrated inFIG.1andFIG.3, a wafer cassette placement step of placing the wafer cassette6in which plural wafers4are housed on the wafer cassette table8is executed. In the wafer cassette6, plural wafers4are housed at intervals in the upward-downward direction in the state in which the front surfaces4aare oriented upward. Furthermore, as illustrated inFIG.1andFIG.5, a frame housing step of housing plural ring-shaped annular frames64in which the opening part64athat houses the wafer4is formed in the frame housing unit66is executed. The frame housing step may be executed before the wafer cassette placement step or may be executed after the wafer cassette placement step. In the frame housing step, after the rising-lowering plate74of the frame housing unit66is lowered to an optional position, the handle76ais grasped and the door76is opened, and the plural annular frames64are stacked over the upper surface of the rising-lowering plate74to be housed. Furthermore, the height of the rising-lowering plate74is adjusted as appropriate and the annular frame64at the uppermost level is positioned to a position from which the annular frame64can be carried out by the frame carrying-out unit68. After the wafer cassette placement step and the frame housing step are executed, a wafer carrying-out step of carrying out the wafer4from the wafer cassette6placed on the wafer cassette table8is executed. Referring toFIG.3, in the wafer carrying-out step, first, the Y-axis feed mechanism34of the wafer carrying-out unit10is actuated and the Y-axis movable component32is positioned near the wafer cassette table8. Subsequently, the conveying arm42is driven and the hand44in which the air jet ports46are oriented upward is positioned to the side of the back surface4b(lower side) of the wafer4in the wafer cassette6. When the hand44is positioned to the side of the back surface4bof the wafer4, a gap is made between the back surface4bof the wafer4and the hand44and each guide pin48is positioned outside in the radial direction. Next, compressed air is jetted from the air jet ports46of the hand44to generate a negative pressure on a single surface side of the hand44by the Bernoulli effect, and the wafer4is sucked and supported from the side of the back surface4bby the hand44in a contactless manner. Subsequently, each guide pin48is moved inward in the radial direction and horizontal movement of the wafer4sucked and supported by the hand44is restricted by the respective guide pins48. Then, the Y-axis movable component32and the conveying arm42of the wafer carrying-out unit10are moved and the wafer4sucked and supported by the hand44is carried out from the wafer cassette6. It is preferable to execute a notch detection step of detecting the position of the notch26of the wafer4after executing the wafer carrying-out step. In the notch detection step, as illustrated inFIG.4, the outer circumference of the wafer4sucked and supported by the hand44is positioned between the light emitting element52and the light receiving element54of the notch detecting unit50. Next, by rotating the wafer4by the drive source through the guide pin48, the position of the notch26of the wafer4is detected. This makes it possible to adjust the orientation of the wafer4to an optional orientation. After the notch detection step is executed, a wafer support step of supporting the wafer4carried out by the wafer carrying-out unit10by the wafer table12is executed. Referring toFIG.3, in the wafer support step, first, the hand44of the wafer carrying-out unit10is inverted upside down to orient the front surface4aof the wafer4downward. Subsequently, the Y-axis movable component32and the conveying arm42of the wafer carrying-out unit10are moved and the outer circumferential surplus region20of the front surface4aof the wafer4sucked and supported by the hand44is brought into contact with the annular support part56of the wafer table12. At this time, the device region18of the front surface4aof the wafer4is located in the recess62of the wafer table12. Therefore, the devices14do not get contact with the wafer table12and damage to the devices14is prevented. Next, the outer circumferential surplus region20of the front surface4aof the wafer4is sucked and held by actuating the suction means of the wafer table12and generating a suction force for each suction hole60. Subsequently, the suction support of the wafer4by the hand44is released and the hand44is separated from the wafer table12. In this manner, the wafer4is transferred from the wafer carrying-out unit10to the wafer table12. Because the wafer4transferred to the wafer table12is sucked and held by each suction hole60, the position of the wafer4does not deviate. Furthermore, after the wafer cassette placement step and the frame housing step are executed, a frame carrying-out step of carrying out the annular frame64from the frame housing unit66is executed concurrently with the wafer carrying-out step and the wafer support step. Referring toFIG.5, in the frame carrying-out step, first, the X-axis movable component84and the Z-axis movable component86of the frame carrying-out unit68are moved and the suction pads92of the holding part88are brought into contact with the upper surface of the annular frame64at the uppermost level housed in the frame housing unit66. Next, the annular frame64at the uppermost level is sucked and held by the suction pads92by actuating the suction means of the frame carrying-out unit68and generating a suction force for the suction pads92. Then, the X-axis movable component84and the Z-axis movable component86of the frame carrying-out unit68are moved and the annular frame64at the uppermost level sucked and held by the suction pads92of the holding part88is carried out from the frame housing unit66. After the frame carrying-out step is executed, a frame support step of supporting the annular frame64carried out by the frame carrying-out unit68by the frame table70is executed. The description will be continued with reference toFIG.5. In the frame support step, first, the X-axis movable component84and the Z-axis movable component86of the frame carrying-out unit68are moved and the annular frame64sucked and held by the suction pads92is brought into contact with the upper surface of the frame table70. At this time, the frame table70is positioned to the lowering position (a position illustrated by solid lines inFIG.5) in advance. Subsequently, the suction force of the suction pads92of the frame carrying-out unit68is deactivated to place the annular frame64on the frame table70. Then, the X-axis movable component84and the Z-axis movable component86of the frame carrying-out unit68are moved and the holding part88is separated from the upper side of the frame table70. After the frame support step is executed, a tape sticking step of sticking the tape96to the annular frame64is executed. Referring toFIG.6AandFIG.6B, in the tape sticking step, first, before the frame table70is moved from the lowering position (a position illustrated inFIG.6A) to the rising position (a position illustrated inFIG.6B) with which the tape96can be stuck to the annular frame64, the tape96is pulled out from the roll tape96R and the tape96from which the release paper116has been separated is positioned above the frame table70. The adhesive surface of the tape96located above the frame table70is oriented downward. Next, the frame table70is raised to such an extent that the tape96can be pressed against the annular frame64from the upper side by the pressing roller132of the pressure bonding part110of the tape sticking unit98. Then, the pressing roller132is rolled in the Y-axis direction while the adhesive surface of the tape96is pressed against the annular frame64by the pressing roller132. Thereby, the tape96pulled out from the roll tape96R by the tape pull-out part108can be pressure-bonded to the annular frame64. Subsequently, the cutter144and the holding-down roller146of the cutting part112of the tape sticking unit98are lowered to press the cutter144against the tape96on the annular frame64and hold down the annular frame64by the holding-down roller146from over the tape96. Next, the arm piece140is rotated by the motor138and the cutter144, and the holding-down roller146are moved to draw a circle along the annular frame64. Thereby, the tape96that protrudes to the outer circumference of the annular frame64can be cut along the annular frame64. Furthermore, because the annular frame64is held down by the holding-down roller146from over the tape96, deviation of the position of the annular frame64and the tape96is prevented when the tape96is being cut. The tape96used in which the circular opening part120is formed is taken up by the tape take-up part106. After the tape sticking step is executed, a tape-attached frame conveyance step of conveying the annular frame64to which the tape96is stuck to the wafer table12and positioning the opening part64aof the annular frame64to the back surface4bof the wafer4supported by the wafer table12and placing the tape-attached annular frame64′ on the wafer table12is executed. In the tape-attached frame conveyance step, first, the frame table70is moved from the rising position to the lowering position. Subsequently, the Y-axis movable component150and the Z-axis movable component152of the tape-attached frame conveying unit100(seeFIG.5) are moved and the respective suction pads158of the holding part154of the tape-attached frame conveying unit100are brought into contact with the upper surface of the tape-attached annular frame64′ (seeFIG.7) supported by the frame table70in the state in which the adhesive surface of the tape96is oriented downward. Next, the upper surface of the tape-attached annular frame64′ is sucked and held by the suction pads158by actuating the suction means of the tape-attached frame conveying unit100and generating a suction force for the suction pads158. Subsequently, the Y-axis movable component150and the Z-axis movable component152of the tape-attached frame conveying unit100are moved, and the tape-attached annular frame64′ sucked and held by the suction pads158is carried out from the frame table70. Next, the tape-attached annular frame64′ sucked and held by the suction pads158of the tape-attached frame conveying unit100is conveyed to the wafer table12. Then, as illustrated inFIG.7, the opening part64aof the annular frame64is positioned to the back surface4bof the wafer4supported by the wafer table12, and the tape-attached annular frame64′ is brought into contact with the frame support part58of the wafer table12. At this time, the adhesive surface of the tape96of the tape-attached annular frame64′ is oriented downward and the back surface4bof the wafer4is oriented upward and faces the adhesive surface of the tape96. Subsequently, the suction force of the suction pads158of the tape-attached frame conveying unit100is deactivated to place the tape-attached annular frame64′ on the frame support part58of the wafer table12. Then, the Y-axis movable component150and the Z-axis movable component152of the tape-attached frame conveying unit100are moved and the holding part154is separated from the upper side of the wafer table12. After the tape-attached frame conveyance step is executed, a tape pressure bonding step of executing pressure bonding of the tape96of the tape-attached annular frame64′ to the back surface4bof the wafer4is executed. Referring toFIG.7toFIG.9, in the tape pressure bonding step, first, the upper chamber160is lowered by the raising-lowering mechanism164of the tape pressure bonding unit102and the lower end of the sidewall172of the upper chamber160is brought into contact with the upper end of the sidewall186of the lower chamber162. Thereby, the upper chamber160and the lower chamber162are set to the closed state. In addition, the pressing roller174is brought into contact with the tape-attached annular frame64′. Thereupon, as illustrated inFIG.8, the back surface4bof the wafer4is brought into contact with the adhesive surface of the tape96of the tape-attached annular frame64′. Next, the vacuum part166of the tape pressure bonding unit102is actuated in the state in which the opening-to-atmosphere part168is closed, and the inside of the upper chamber160and the lower chamber162is set to a vacuum state. Subsequently, as illustrated inFIG.8andFIG.9, pressure bonding of the tape96to the back surface4bof the wafer4is executed by rolling the pressing roller174of the tape pressure bonding unit102in the Y-axis direction. Thereby, the frame unit U in which the back surface4bof the wafer4and the tape96are pressure-bonded can be generated. Next, the opening-to-atmosphere part168is opened and the tape96is brought into close contact with the back surface4bof the wafer4. Then, the upper chamber160is raised by the raising-lowering mechanism164. Due to the setting of the inside of the upper chamber160and the lower chamber162to the vacuum state, the suction force for the wafer4by the wafer table12is lost. However, when the upper chamber160and the lower chamber162are set to the closed state, the back surface4bof the wafer4is brought into contact with the adhesive surface of the tape96of the tape-attached annular frame64′. Thus, the position of the wafer4does not deviate in the tape pressure bonding step. After the tape pressure bonding step is executed, a frame unit carrying-out step of carrying out, from the wafer table12, the frame unit U in which the tape96of the tape-attached annular frame64′ and the back surface4bof the wafer4are pressure-bonded is executed. Referring toFIG.5, in the frame unit carrying-out step, first, the conveying part206of the frame unit carrying-out means192is actuated and the lower surface of the suction adhesion piece210of the wafer holding part202aof the frame unit holding part202is brought into contact with the tape96on the side of the back surface4bof the wafer4. In addition, the suction pads214of the frame holding part202bare brought into contact with the annular frame64. Subsequently, a suction force is generated for the suction adhesion piece210of the wafer holding part202aand the suction pads214of the frame holding part202band the wafer4is sucked and held from the side of the back surface4b(side of the tape96) by the suction adhesion piece210of the wafer holding part202a. In addition, the annular frame64is sucked and held by the suction pads214of the frame holding part202b. Next, the suction holding of the wafer4by the wafer table12is released. Then, the conveying part206is actuated and the frame unit U held by the frame unit holding part202is carried out from the wafer table12. After the frame unit carrying-out step is executed, a temporary placement step of making the center of the wafer4correspond with the center of the temporary placement table204and temporarily placing the frame unit U on the temporary placement table204is executed. Referring toFIG.10, in the temporary placement step, first, the frame unit U held by the frame unit holding part202is positioned above the imaging part224. Subsequently, the conveying part206that configures the two-dimensional movement mechanism of the frame unit carrying-out means192is actuated and at least three places at the outer circumference of the wafer4of the frame unit U held by the frame unit holding part202are imaged by the imaging part224. Thereby, the coordinates of at least three points at the outer circumference of the wafer4are measured. Next, the center coordinates of the wafer4are obtained based on the measured coordinates of the three points. Subsequently, the conveying part206is actuated and the center of the wafer4is positioned to the center of the annular support part226of the temporary placement table204, and the outer circumferential surplus region20of the front surface4aof the wafer4is brought into contact with the upper surface of the annular support part226of the temporary placement table204. In addition, the lower surface of the annular frame64is brought into contact with the upper surface of the frame support part228of the temporary placement table204. At this time, the front surface4aof the wafer4is oriented downward. However, because the device region18is located in the recess230of the temporary placement table204, the devices14do not get contact with the temporary placement table204and damage to the devices14is prevented. Next, the suction holding of the wafer4by the wafer holding part202ais released and the suction holding of the annular frame64by the frame holding part202bis released, to transfer the frame unit U from the frame unit carrying-out means192to the temporary placement table204. Subsequently, the heater of the frame support part228is actuated to heat the tape96of the frame unit U temporarily placed on the temporary placement table204by the heater. Due to this, the tape96softens and is brought into close contact with the root of the beveled part24. After the temporary placement step is executed, a beveled part removal step of cutting and removing, in a ring manner, the beveled part24formed in the outer circumferential surplus region20from the wafer4of the frame unit U carried out by the frame unit carrying-out means192is executed. Referring toFIG.1,FIG.10, andFIGS.12A to12C, in the beveled part removal step, first, the X-axis movable component260and the Z-axis movable component262of the first raising-lowering table246of the beveled part removing unit194are moved. Thereby, the lower surface of the wafer suction adhesion chuck400is brought into contact with the side of the back surface4bof the wafer4(side of the tape96) of the frame unit U temporarily placed on the temporary placement table204and the lower surfaces of the frame suction adhesion chucks402are brought into contact with the upper surface of the annular frame64. Next, a suction force is generated for the wafer suction adhesion chuck400and the frame suction adhesion chucks402. Thereby, the wafer4of the frame unit U is sucked and held by the wafer suction adhesion chuck400and the annular frame64is sucked and held by the frame suction adhesion chucks402. Subsequently, the X-axis movable component260and the Z-axis movable component262of the first raising-lowering table246are actuated, and, as illustrated inFIG.11, the frame unit U sucked and held by the holding piece268is positioned above the laser beam irradiation unit244. Next, the focal point of the laser beam LB is positioned to the base of the beveled part24of the wafer4of the frame unit U. Subsequently, while the holding piece268and the frame unit U are rotated by the motor266of the first raising-lowering table246, the base of the beveled part24of the wafer4is irradiated with the laser beam LB. This can execute ablation processing for the base of the beveled part24of the wafer4and form the ring-shaped cut groove256. Alternatively, a modified layer (not illustrated) may be formed into a ring manner inside the wafer4along the outer circumference of the wafer4by the irradiation with the laser beam. Furthermore, when the wafer4is irradiated with the laser beam LB, the suction means of the laser beam irradiation unit244is actuated to generate a suction force for the suction nozzle254, and debris generated due to the ablation processing is sucked by the suction nozzle254. After the ring-shaped cut groove256is formed at the base of the beveled part24of the wafer4, whether or not the cut groove256has reached the back surface4bfrom the front surface4aof the wafer4is detected by the cut groove detecting unit404. The detection of the cut groove256is executed by measuring the amount of light received by the light receiving part408while rotating the frame unit U held by the first raising-lowering table246. When a region about which the amount of light received by the light receiving part408is smaller than the predetermined threshold exists, it is determined that a part at which the cut groove256has not reached the back surface4bfrom the front surface4aof the wafer4, i.e. an incompletely-cut part at which the wafer4has not been completely cut, exists. When it is determined that the incompletely-cut part exists, the incompletely-cut part of the wafer4is irradiated with the laser beam LB by the laser beam irradiation unit244to execute ablation processing again. On the other hand, when the amount of light received by the light receiving part408is equal to or larger than the predetermined threshold over the whole circumference of the cut groove256, it is determined that the whole circumference of the cut groove256has reached the back surface4bfrom the front surface4aof the wafer4and the wafer4has been completely cut. As above, in the present embodiment, whether the wafer4has been completely cut by the cut groove256is checked after the cut groove256is formed, and ablation processing is executed again if the wafer4has not been completely cut. Therefore, conveyance of the frame unit U to the next step in the state in which an incompletely-cut part exists in the wafer4is prevented. Next, the X-axis movable component260and the Z-axis movable component262of the first raising-lowering table246are moved and the outer circumferential surplus region20of the front surface4aof the wafer4of the frame unit U sucked and held by the holding piece268is brought into contact with the upper surface of the annular support part226of the temporary placement table204. In addition, the lower surface of the annular frame64is brought into contact with the upper surface of the frame support part228of the temporary placement table204. Subsequently, the suction force of the holding piece268of the first raising-lowering table246is deactivated to transfer the frame unit U from the first raising-lowering table246to the temporary placement table204. Next, the temporary placement table204that has received the frame unit U is positioned below the separating part248of the beveled part removing unit194by the temporary placement table conveying part232(seeFIG.10). At this time, the belt conveyor300of the discard part276is positioned to the standby position. Subsequently, the second raising-lowering table272of the separating part248is lowered and the lower surface of the second raising-lowering table272is brought into contact with the tape96of the part of the back surface4bof the wafer4. Next, a suction force is generated at the lower surface of the second raising-lowering table272and the side of the back surface4bof the wafer4of the frame unit U is sucked and held by the second raising-lowering table272. Subsequently, the second raising-lowering table272that sucks and holds the wafer4of the frame unit U is raised to separate the frame unit U from the temporary placement table204. In addition, the temporary placement table204is moved to the lower side of the first raising-lowering table246. Next, as illustrated inFIG.15, the pair of feed mechanisms290and the Z-axis feed mechanisms294of the separator274are actuated and the annular frame64is clamped in the upward-downward direction by the upper and lower clamping rollers292aand292b. Furthermore, the belt conveyor300of the discard part276is positioned from the standby position to the collection position. Subsequently, irradiation with ultraviolet from the pair of ultraviolet irradiation parts270is executed to reduce the adhesive force of the tape96sticking to the beveled part24. In addition, while the beveled part24is pressed downward by the pressing rollers298, the frame unit U is rotated together with the support shaft286and the second raising-lowering table272relative to the separator274by the motor284. This can separate the beveled part24from the frame unit U. The beveled part24that has dropped from the frame unit U is conveyed to the dust box302by the belt conveyor300and is collected. When the beveled part24is separated, the separator274may be rotated relative to the frame unit U. After the beveled part24is separated from the frame unit U, whether or not the beveled part24has been removed is detected by the removal detecting unit412. The removal detection of the beveled part24is executed by irradiating the region in which the beveled part24has existed with the light L1from the light emitting part416and measuring the amount of light received by the light receiving part418while rotating the wafer4that is held by the second raising-lowering table272and from which the beveled part24has been removed. When a region about which the amount of light received by the light receiving part418is equal to or larger than the predetermined threshold exists, it is determined that at least part of the beveled part24remains without being removed. In this case, work of separating the beveled part24from the frame unit U by the separating part248is executed again. On the other hand, when the amount of light received by the light receiving part418is smaller than the predetermined threshold over the whole circumference of the wafer4, it is determined that the beveled part24has been completely removed. As above, in the present embodiment, whether the beveled part24has been completely removed is checked after the beveled part24is removed by the separating part248, and removal work of the beveled part24by the separating part248is executed again if the beveled part24has not been completely removed. Therefore, conveyance of the frame unit U to the next step in the state in which the beveled part24remains in the frame unit U is prevented. After the beveled part removal step is executed, a beveled part-free unit carrying-out step of carrying out the beveled part-free unit U′ resulting from the removal of the beveled part24from the beveled part removing unit194is executed. In the beveled part-free unit carrying-out step, first, the belt conveyor300of the discard part276of the beveled part removing unit194is positioned from the collection position to the standby position. Next, the frame holding part306of the inversion mechanism308(seeFIG.17) of the beveled part-free unit carrying-out means196is positioned below the beveled part-free unit U′ sucked and held by the second raising-lowering table272. Subsequently, the arm318is raised in the state in which the suction pads326of the frame holding part306are oriented upward and the suction pads326of the frame holding part306are brought into contact with the lower surface side of the annular frame64of the beveled part-free unit U′ in the state in which the beveled part-free unit U′ is supported by the second raising-lowering table272and the front surface4aof the wafer4is oriented downward. Next, a suction force is generated for the suction pads326of the frame holding part306and the annular frame64of the beveled part-free unit U′ is sucked and held by the suction pads326. Subsequently, the suction holding of the beveled part-free unit U′ by the second raising-lowering table272is released. Thereby, the beveled part-free unit U′ is transferred from the second raising-lowering table272of the beveled part removing unit194to the frame holding part306of the beveled part-free unit carrying-out means196. After the beveled part-free unit carrying-out step is executed, a beveled part-free unit housing step of housing the beveled part-free unit U′ carried out by the beveled part-free unit carrying-out means196is executed. In the beveled part-free unit housing step, first, the inversion mechanism308of the beveled part-free unit carrying-out means196is inverted upside down and the beveled part-free unit U′ sucked and held by the frame holding part306is inverted upside down. Due to this, the beveled part-free unit U′ is located under the frame holding part306and the front surface4aof the wafer4is oriented upward. Next, the Y-axis movable component316and the arm318of the inversion mechanism308are moved and the beveled part-free unit U′ is brought into contact with the upper surfaces of the pair of support plates328of the beveled part-free unit support part310. At this time, the interval between the pair of support plates328is narrowed by the interval adjusting means, and the pair of support plates328are in close contact with each other. Subsequently, the suction holding of the beveled part-free unit U′ by the frame holding part306is released to place the beveled part-free unit U′ on the pair of support plates328. Next, slack and wrinkles of the tape96caused due to the removal of the beveled part24are eliminated by actuating the heater mounted on each support plate328and heating the tape96of the beveled part-free unit U′. Then, the beveled part-free unit U′ is sucked and held and is raised by the frame holding part306again. Next, after the interval between the pair of support plates328is enlarged by the interval adjusting means, the beveled part-free unit U′ is placed on the upper surfaces of the support plates328. Then, as illustrated inFIG.19, the beveled part-free unit U′ supported by the beveled part-free unit support part310is pushed by the pressing piece338of the pushing part312and the beveled part-free unit U′ is caused to enter the frame cassette198placed on the frame cassette table200and is housed therein. The configuration of the embodiment is as above. In the processing apparatus2of the present embodiment, work of sticking the dicing tape96to the wafer4in which the beveled part24is formed in the outer circumferential surplus region20to integrate the wafer4with the annular frame64is easy. In addition, it is easy to cut the beveled part24and remove it from the wafer4and the productivity becomes favorable. The present invention is not limited to the details of the above described preferred embodiment. The scope of the invention is defined by the appended claims and all changes and modifications as fall within the equivalence of the scope of the claims are therefore to be embraced by the invention. | 87,598 |
11862506 | DETAILED DESCRIPTION Hereinafter, embodiments of the substrate processing system, the vacuum substrate transfer module, and the substrate transfer method will be described in detail with reference to the accompanying drawings. Further, the substrate processing system, the vacuum substrate transfer module, and the substrate transfer method to be described below are not limited by the following embodiments. In order to increase the number of substrates that can be processed per unit time, it may be an option to increase the number of substrate processing modules that process the substrates. However, as the number of the substrate processing modules increases, a substrate processing system, which includes a plurality of substrate processing modules, a vacuum transfer module, a load lock module, an atmospheric substrate transfer module, and the like, becomes larger in size. When the size of the substrate processing system is increased, the installation area (footprint) of the substrate processing system in a facility such as a clean room is increased, which makes it difficult to arrange a plurality of substrate processing systems. Therefore, there is a demand for reducing the installation area of the substrate processing system. Accordingly, the present disclosure provides a technique for reducing the installation area of the substrate processing system. (Configuration of Substrate Processing System1) FIG.1is a plan view illustrating an example of a configuration of a substrate processing system1according to an embodiment.FIG.2is an example of a cross sectional view taken along a broken line II-II of the substrate processing system1shown inFIG.1.FIG.3is an example of a cross sectional view taken along a broken line III-III of the substrate processing system1shown inFIG.2.FIG.4is an example of a cross sectional view taken along a broken line IV-IV of the substrate processing system1shown inFIG.2. InFIG.1, some internal components of devices are illustrated transparently for easier understanding. The substrate processing system1includes a main body10and a control device (CD)100that controls the main body10. The main body10includes a vacuum substrate transfer module11, at least one (plurality in the example ofFIG.1) substrate processing module12, at least one (plurality in the example ofFIG.1) load lock module13, an atmospheric substrate transfer module17, and at least one (plurality in the example ofFIG.1) load port18. The substrate processing module12is an example of a first external module, and the load lock module13is an example of a second external module. The vacuum substrate transfer module11includes a first vacuum substrate transfer module111and a second vacuum substrate transfer module112. The first vacuum substrate transfer module111has a first transfer space1110for transferring the substrate W under a vacuum atmosphere. The first vacuum substrate transfer module111is arranged adjacent to the atmospheric substrate transfer module17and the plurality of substrate processing modules12. In the present embodiment, the first vacuum substrate transfer module111has a substantially rectangular shape in a plan view and has first to fourth sidewalls. The atmospheric substrate transfer module17is arranged adjacent to the first sidewall of the first vacuum substrate transfer module111. The first vacuum substrate transfer module111does not communicate with the atmospheric substrate transfer module17. Each of the second sidewall and the third sidewall of the first vacuum substrate transfer module111is perpendicular to the first sidewall, and two substrate processing modules12are installed on each of the second sidewall and the third sidewall. The second vacuum substrate transfer module112is arranged under the first transfer space1110. The second vacuum substrate transfer module112has a second transfer space1120for transferring the substrate W under a vacuum atmosphere. In the present embodiment, the second vacuum substrate transfer module112has a substantially rectangular shape in a plan view and has first to fourth sidewalls. The first sidewall of the second vacuum substrate transfer module112is located opposite to the atmospheric substrate transfer module17, and at least one load lock module13is installed on the first sidewall of the second vacuum substrate transfer module112. The second transfer space1120communicates with the first transfer space1110. The first transfer space1110and the second transfer space1120may be integrally formed or separately formed. The external dimensions (outside dimension or overall size) of the second vacuum substrate transfer module112are smaller than the external dimensions of the first vacuum substrate transfer module111in a plan view (when viewed from the top-down view ofFIGS.1to4). In the present embodiment, for example, as shown inFIG.1, a lateral dimension W2of the second vacuum substrate transfer module112is equal to or smaller than a lateral dimension W1of the first vacuum substrate transfer module111. In the present embodiment, for example, as shown inFIG.2, a depth dimension D2of the second vacuum substrate transfer module112is smaller than a depth direction dimension D1of the first vacuum substrate transfer module111. A transfer robot110is provided in the second transfer space1120of the second vacuum substrate transfer module112. The transfer robot110is an example of a vacuum substrate transfer robot. The transfer robot110has an arm provided with an end effector for holding the substrate W at the tip end thereof. The transfer robot110is configured to transfer the substrate W between the respective substrate processing modules12and the first transfer space1110by moving the arm thereof. In the present embodiment, the transfer robot110horizontally transfers the substrate W between the respective substrate processing modules12and the first transfer space1110at a first height h1. Further, the transfer robot110is configured to transfer the substrate W between the first transfer space1110and the second transfer space1120by moving the arm thereof. In the present embodiment, the transfer robot110vertically transfers the substrate W between the first height h1in the first transfer space1110and a second height h2in the second transfer space1120. Furthermore, the transfer robot110is configured to transfer the substrate W between the second transfer space1120and the respective load lock modules13by moving the arm thereof. In the present embodiment, the transfer robot110horizontally transfers the substrate W between the second transfer space1120and the respective load lock modules13at the second height h2. The interior of the first vacuum substrate transfer module111and the interior of the second vacuum substrate transfer module112of the vacuum substrate transfer module11may be maintained in a vacuum atmosphere (for example, a predetermined pressure lower than an atmospheric pressure, which may be referred to as “low pressure” in some cases described below). A plurality of gate valves G1are installed on the sidewalls of the first vacuum substrate transfer module111. In the present embodiment, two substrate transfer openings are formed in each of the second sidewall and the third sidewall of the first vacuum substrate transfer module111. The gate valves G1are installed at the substrate transfer openings, respectively. Each gate valve G1is disposed between the first vacuum substrate transfer module111and one substrate processing module12, so that the first vacuum substrate transfer module111can be connected to (communicates with) the corresponding substrate processing module12. The gate valve G1is an example of a first substrate transfer gate. In the example ofFIG.1, although a case where the four substrate processing modules12are connected to the first vacuum substrate transfer module111is illustrated, the number of the substrate processing modules12connected to the first vacuum substrate transfer module111may be three or less or may be five or more. Each substrate processing module12performs processing such as etching or film formation on the substrate W. In the present embodiment, the substrate processing module12performs plasma processing on the substrate W under a vacuum atmosphere. The substrate processing modules12may perform the same process or different processes in a manufacturing process. For example, as shown inFIGS.1to3, a plurality of gate valves G2are installed on a side surface of the second vacuum substrate transfer module112. In the present embodiment, two substrate transfer openings are formed in the first sidewall of the second vacuum substrate transfer module112. The gate valves G2are installed at the substrate transfer openings, respectively. Each gate valve G2is disposed between the second vacuum substrate transfer module112and one load lock module13, so that the second vacuum substrate transfer module112can be connected to (communicate with) the corresponding load lock module13. The gate valve G2is an example of a second substrate transfer gate. In the present embodiment, the plurality of load lock modules13are disposed under the first vacuum substrate transfer module111and between the second vacuum substrate transfer module112and the atmospheric substrate transfer module17. In the examples ofFIGS.1to3, although a case where the two load lock modules13are connected to the second vacuum substrate transfer module112is illustrated, the number of the load lock modules13connected to the second vacuum substrate transfer module112may be one or may be three or more. Further, gate valves G3are installed on the load lock modules13, respectively. Each gate valve G3is disposed between the atmospheric substrate transfer module17and one load lock module13. In the present embodiment, for example, as shown inFIG.2, each gate valve G3is arranged at the same height as the gate valve G2installed on the corresponding load lock module13. The gate valve G3is an example of a third substrate transfer gate. In the present embodiment, the load lock module13has a substantially rectangular shape in a plan view and has first to fourth sidewalls. The second sidewall is located opposite to the first sidewall. A substrate transfer opening is formed in the first sidewall of the load lock module13, and the gate valve G2is installed at the substrate transfer opening. Further, a substrate transfer opening is formed in the second sidewall of the load lock module13, and the gate valve G3is installed at the substrate transfer opening. After the substrate W is transferred from the atmospheric substrate transfer module17into the load lock module13via the gate valve G3, the corresponding substrate transfer opening is closed by driving the gate valve G3. Then, a pressure in the load lock module13may be lowered from the atmospheric pressure to a predetermined low pressure by an exhaust device (not shown). Then, the corresponding substrate transfer opening is opened by driving the gate valve G2, and the substrate W in the load lock module13is transferred into the second vacuum substrate transfer module112. Further, in a state in which the interior of the load lock module13is maintained at the low pressure (that is, in a vacuum atmosphere), the substrate W is transferred from the second vacuum substrate transfer module112to the load lock module13through the substrate transfer opening corresponding to the gate valve G2, and thereafter the corresponding substrate transfer opening is closed by driving the gate valve G2. Then, a gas (for example, air) may be supplied into the load lock module13using a gas supply device (not shown), thereby increasing the pressure in the load lock module13from the low pressure to the atmospheric pressure. Then, the substrate transfer opening corresponding to the gate valve G3is opened by driving the gate valve G3, and the substrate W in the load lock module13is transferred into the atmospheric substrate transfer module17. On a sidewall of the atmospheric substrate transfer module17that is opposite to the sidewall of the atmospheric substrate transfer module17to which the load lock module13is connected, the plurality of load ports18are installed. A front opening unified pod (FOUP) for accommodating a plurality of substrates W is connected (mounted) to each load port18. A transfer robot171is provided in the atmospheric substrate transfer module17. The transfer robot171is an example of an atmospheric substrate transfer robot. The transfer robot171is configured to transfer the substrate W between the atmospheric substrate transfer module17and the load lock module13through the substrate transfer opening corresponding to the gate valve G3. Further, the transfer robot171is configured to transfer the substrate W between the FOUP connected to the load port18and the load lock module13. A guide rail170is provided on the sidewall of the atmospheric substrate transfer module17to which the load lock module13is connected. The transfer robot171moves back and forth in the atmospheric substrate transfer module17along the guide rail170. For example, as shown inFIG.2, a fan filter unit (FFU)75is provided on an upper portion of the atmospheric substrate transfer module17. The FFU175supplies air, from which particles and the like are removed (hereinafter referred to as “clean air”), into the atmospheric substrate transfer module17from the upper portion of the atmospheric substrate transfer module17. A perforated floor176is provided at a bottom portion of the atmospheric substrate transfer module17, and an exhaust device (ED)177for exhausting clean air in the atmospheric substrate transfer module17is connected to the bottom of the atmospheric substrate transfer module17below the perforated floor176. The clean air supplied from the FFU175is exhausted by the exhaust device177through the perforated floor176, so that a downflow of the clean air is formed in the atmospheric substrate transfer module17. As a result, it is possible to suppress particles and the like from swirling upward in the atmospheric substrate transfer module17. In addition, the exhaust device177may control a pressure in the atmospheric substrate transfer module17such that the interior of the atmospheric substrate transfer module17has a positive pressure. As a result, it is possible to suppress external particles and the like from entering the atmospheric substrate transfer module17. The control device100includes a memory, a processor, and an input/output interface. The memory stores data such as recipes, and programs. For example, the memory may include a random access memory (RAM), a read only memory (ROM), a hard disk drive (HDD), a solid state drive (SSD), or the like. The processor executes a program read from the memory to control each unit of the main body10through the input/output interface based on the data such as the recipe stored in the memory. The processor may be a central processing unit (CPU) or a digital signal processor (DSP). As described above, in the present embodiment, the second vacuum substrate transfer module112is disposed under the first vacuum substrate transfer module111and has an outer diameter smaller than that of the first vacuum substrate transfer module111in a plan view. The load lock module13is connected to the side surface of the second vacuum substrate transfer module112. As a result, the installation area of the substrate processing system1can be reduced as compared with the case where the load lock module13is disposed between the first vacuum substrate transfer module111and the atmospheric substrate transfer module17. (Transfer Method of Substrate W) FIG.5is a flowchart showing an example of a substrate transfer method.FIGS.6to9are cross-sectional views showing an example of the substrate processing system1when the substrate W is transferred. The process illustrated inFIG.5is realized by controlling each unit of the main body10by the control device100. AlthoughFIG.5shows a procedure for transferring the substrate W from the substrate processing module12to the FOUP, a procedure for transferring the substrate W from the FOUP to the substrate processing module12can be realized by performing the procedure ofFIG.5in the reverse order. First, the gate valve G1is driven to open the substrate transfer opening corresponding thereto. Then, in an atmosphere (e.g., the vacuum atmosphere) where a pressure is lower than the atmospheric pressure, the transfer robot110transfers the substrate W from the inside of the substrate processing module12into the first transfer space1110through the substrate transfer opening corresponding to the gate valve G1(step S10). Step S10is an example of “(a) step.” Then, the gate valve G1is driven to close the substrate transfer opening corresponding thereto. For example, in step S10, the transfer robot110horizontally transfers the substrate W from the inside of the substrate processing module12to the first transfer space1110at the first height h1through the substrate transfer opening corresponding to the gate valve G1, as shown inFIG.6. The first height h1is, for example, the height from the bottom surface of the second vacuum substrate transfer module112. Next, in the atmosphere where the pressure is lower than the atmospheric pressure, the transfer robot110vertically transfers the substrate W from the first height h1in the first transfer space1110to the second height h2in the second transfer space1120(step S11). Step S11is an example of “(b) step.” Then, the gate valve G2is driven to open the substrate transfer opening corresponding thereto. Further, before the substrate transfer opening corresponding to the gate valve G2is opened, the pressure inside the load lock module13is almost the same as the pressure (e.g., a vacuum atmosphere) inside the vacuum substrate transfer module11. Next, in the atmosphere where the pressure is lower than the atmospheric pressure, the transfer robot110transfers the substrate W from the second transfer space1120into the load lock module13through the substrate transfer opening corresponding to the gate valve G2(step S12). Step S12is an example of “(c) step.” Then, the transfer robot110retracts only the end effector from the load lock module13after placing the substrate W on a substrate support portion in the load lock module13. For example, in step S12, the transfer robot110horizontally transfers the substrate W from the inside of the second transfer space1120to the inside of the load lock module13at the second height h2through the substrate transfer opening corresponding to the gate valve G2, as shown inFIG.7. The first height h1is higher than the second height h2. The second height h2is, for example, the height from the bottom surface of the second vacuum substrate transfer module112. Next, for example, as shown inFIG.8, the gate valve G2is driven to close the substrate transfer opening corresponding thereto, and the pressure in the load lock module13is increased to the atmospheric pressure by a gas supply device (not shown) (step S13). Then, the gate valve G3is driven to open the substrate transfer opening corresponding thereto. Next, for example, as shown inFIG.9, in an atmospheric pressure atmosphere, the transfer robot171transfers the substrate W from the load lock module13into the atmospheric substrate transfer module17through the substrate transfer opening corresponding to the gate valve G3(step S14). In step S14, the transfer robot171transfers the substrate W between the load lock module13and the atmospheric substrate transfer module17at the second height h2through the substrate transfer opening corresponding to the gate valve G3. Step S14is an example of “(d) step.” Next, under the atmospheric pressure atmosphere, the transfer robot171transfers the substrate W from the atmosphere substrate transfer module17into the FOUP (step S15). Then, the process shown in the flowchart ofFIG.5is completed. The first embodiment has been described above. As described above, the substrate processing system1in the present embodiment includes the substrate processing module12, the atmospheric substrate transfer module17, the first vacuum substrate transfer module111, the second vacuum substrate transfer module112, the load lock module13, and a transfer robot110. The first vacuum substrate transfer module111has the first transfer space1110and is disposed adjacent to the atmospheric substrate transfer module17and the substrate processing module12. The second vacuum substrate transfer module112has the second transfer space1120communicating with the first transfer space1110and is disposed under the first vacuum substrate transfer module111. The external dimensions of the second vacuum substrate transfer module112are smaller than the external dimensions of the first vacuum substrate transfer module111in a plan view. The load lock module13is disposed between the atmospheric substrate transfer module17and the second vacuum substrate transfer module112. The transfer robot110is disposed in the second transfer space1120and is configured to transfer the substrate W between the first transfer space1110and the substrate processing module12at the first height h1. Further, the transfer robot110is configured to transfer the substrate W between the first transfer space1110and the second transfer space1120. Further, the transfer robot110is configured to transfer the substrate W between the second transfer space1120and the load lock module13at the second height h2different from the first height h1. Therefore, the installation area of the substrate processing system1can be reduced. Further, in the first embodiment described above, the second vacuum substrate transfer module112is disposed under the first vacuum substrate transfer module111, and the first height h1is higher than the second height h2. Therefore, the load lock module13can be easily disposed between the vacuum substrate transfer module11and the atmospheric substrate transfer module17. Further, in the first embodiment described above, the transfer robot110is disposed in the second transfer space1120. Therefore, the first vacuum substrate transfer module111can be made smaller. Further, the substrate processing system1according to the first embodiment described above further includes the transfer robot171that is disposed in the atmospheric substrate transfer module17and is configured to transfer the substrate W between the atmospheric substrate transfer module17and the load lock module13. Therefore, the substrate W can be transferred between the atmospheric substrate transfer module17and the load lock module13. Further, in the first embodiment described above, the transfer robot171is configured to transfer the substrate W between the atmospheric substrate transfer module17and the load lock module13at the second height h2. Therefore, the substrate W can be transferred between the atmospheric board transfer module17and the load lock module13that is connected to the second vacuum substrate transfer module112disposed under the first vacuum substrate transfer module111. Further, the vacuum substrate transfer module11in the first embodiment described above includes the first vacuum substrate transfer module111, the second vacuum substrate transfer module112, and the transfer robot110. The first vacuum substrate transfer module111has the first transfer space1110. The second vacuum substrate transfer module112has the second transfer space1120communicating with the first transfer space1110and is disposed under the first vacuum substrate transfer module111. The external dimensions of the second vacuum substrate transfer module112are smaller than the external dimensions of the first vacuum substrate transfer module111in a plan view. The transfer robot110is disposed in the first transfer space1110or the second transfer space1120. Further, the transfer robot110transfers the substrate W between the first transfer space1110and the substrate processing module12at the first height h1, transfers the substrate W between the first transfer space1110and the second transfer space1120, and transfers the substrate W between the second transfer space1120and the load lock module13at the second height h2different from the first height h1. Therefore, the installation area of the substrate processing system1including the vacuum substrate transfer module11can be reduced. Further, the substrate transfer method in the first embodiment described above includes (a) transferring the substrate W between the first vacuum substrate transfer module111and the substrate processing module12at the first height h1in a vacuum atmosphere, (b) transferring the substrate W between the first vacuum substrate transfer module111and the second vacuum substrate transfer module112in a vacuum atmosphere, the second vacuum substrate transfer module112being disposed under the first vacuum substrate transfer module111and having the external dimensions smaller than the external dimensions of the first vacuum substrate transfer module111in a plan view, (c) transferring the substrate W between the second vacuum substrate transfer module112and the load lock module13at the second height h2different from the height h1in a vacuum atmosphere, the load lock module13being disposed between the second vacuum substrate transfer module112and the atmospheric substrate transfer module17, and (d) transferring the substrate W between the load lock module13and the atmospheric substrate transfer module17in an atmospheric pressure atmosphere. Therefore, the substrate W can be transferred in the substrate processing system1having a small installation area. OTHER EMBODIMENTS The technique described in the present disclosure is not limited to the above-described embodiment and can be modified in various ways within the scope of the present disclosure. For example, in the above-described embodiment, the transfer robot110is disposed in the second transfer space1120of the second vacuum substrate transfer module112. However, the present disclosure is not limited thereto. For example, as another embodiment, the transfer robot110may be disposed in the first transfer space1110of the first vacuum substrate transfer module111as shown in an example ofFIG.10. Even with such a configuration, the transfer robot110can transfer the substrate W among the respective substrate processing modules12, the first transfer space1110, the second transfer space1120, and the respective load lock modules13. Further, in the above-described embodiment, the second vacuum substrate transfer module112is disposed under the first vacuum substrate transfer module111. However, the present disclosure is not limited thereto. For example, as another embodiment, the second vacuum substrate transfer module112may be disposed on the first vacuum substrate transfer module111as shown in an example ofFIG.11. In the example ofFIG.11, the transfer robot110is disposed in the second transfer space1120of the second vacuum substrate transfer module112, and the load lock module13is also disposed on the first vacuum substrate transfer module111. Even with such a configuration, the installation area of the substrate processing system1can be reduced. Alternatively, for example, in the substrate processing system1shown inFIG.11, the transfer robot110may be disposed in the first transfer space1110of the first vacuum substrate transfer module111as shown in an example ofFIG.12. Further, in the above-described embodiment, the plurality of load lock modules13are disposed under the first vacuum substrate transfer module111. However, the present disclosure is not limited thereto. For example, as another embodiment, at least one load lock module13may be disposed on and under the first vacuum substrate transfer module111. In this case, the second vacuum substrate transfer module112is disposed on and under the first vacuum substrate transfer module111. The second transfer space1120of the second vacuum substrate transfer module112disposed on the first vacuum substrate transfer module111communicates with the first transfer space1110of the first vacuum substrate transfer module111. Further, the second transfer space1120of the second vacuum substrate transfer module112disposed on the first vacuum substrate transfer module111communicates with the interior of the load lock module13disposed on the first vacuum substrate transfer module111. Further, the second transfer space1120in the second vacuum substrate transfer module112disposed under the first vacuum substrate transfer module111communicates with the first transfer space1110of the first vacuum substrate transfer module111. In addition, the second transfer space1120of the second vacuum substrate transfer module112disposed under the first vacuum substrate transfer module111communicates with the interior of the load lock module13disposed under the first vacuum substrate transfer module111. Further, in the above-described embodiment, the substrate W is transferred among the vacuum substrate transfer module11, the plurality of load lock modules13, and the atmospheric substrate transfer module17. However, the present disclosure is not limited thereto. As another embodiment, an edge ring in addition to the substrate W can be transferred among the vacuum substrate transfer module11, the plurality of load lock modules13, and the atmospheric substrate transfer module17. In this case, the transfer robot110and the transfer robot171transfer the edge ring in addition to the substrate W. Each substrate processing module12is provided with a stage on which the substrate W is placed, and the stage includes the edge ring so as to surround the substrate W. Since the edge ring is consumed through processing such as etching of the substrate W, the edge ring is replaced at a predetermined timing. The presently disclosed embodiments are considered in all respects to be illustrative and are not restrictive. The above-described embodiments can be embodied in various forms. Further, the above-described embodiments may be omitted, replaced, or changed in various forms without departing from the scope of the appended claims and the gist thereof. | 30,226 |
11862507 | EMBODIMENT FOR CARRYING OUT THE INVENTION Next, an embodiment of the present invention will be described with reference to drawings.FIG.1is a perspective view showing a configuration of the robot system100according to an embodiment of the present invention.FIG.2is a perspective view showing a configuration of the robot1in detail.FIG.3is a block diagram showing a configuration of a part of the robot system100.FIG.4AandFIG.4Bare graphs showing the respective current values of the electric motors for driving the respective parts of the robot1.FIG.5AandFIG.5Bare graphs showing the respective position deviations of the electric motors for driving the respective parts of the robot1. The robot system100shown inFIG.1is a system that allows the robot1to work in a work space such as a clean room. The robotic system100is applied to a semiconductor processing system (not shown). In the semiconductor processing system, various predetermined processes are performed on the wafer2to be processed. The robot system100is used to transport the wafer2between various devices included in the semiconductor processing system. The robot system100includes the robot1, the controller (control part)5, and the positional displacement detection device8. The robot1functions as a wafer transfer robot for conveying a wafer stored in a storage device6. In this embodiment, the robot1is achieved by a SCARA type horizontal articulated robot. SCARA is an abbreviation for Selective Compliance Assembly Robot Arm. As shown inFIG.2, the robot1includes a hand (holding part)10, a manipulator11, and a posture detector12. The hand10, which is a kind of end effector, is generally formed in a V-shape or a U-shape in a plan view. The hand10is supported by a tip of the manipulator11(specifically, a second link16which will be described later). The hand10rotates around a fourth axis c4extending in the vertical direction with respect to the second link16. The manipulator11mainly includes a base13, a lifting shaft14, and a plurality of links (a first link15and the second link16). The base13is fixed to the ground (for example, a floor of the clean room). The base13functions as a base member that supports the lifting shaft14. The lifting shaft14moves in the vertical direction with respect to the base13. With such lifting, the heights of the first link15, the second link16, and the hand10can be changed. The lifting shaft14, with respect to base13, rotates around a first axis c1extending in the vertical direction. Accordingly, the posture of the first link15(and second link and the hand10) supported by the lifting shaft14can be changed within a horizontal plane. The first link15is supported on top of the lifting shaft14. The first link15, with respect to the lifting shaft14, rotates around a second axis c2extending in the vertical direction. Accordingly, a posture of the first link15can be changed within the horizontal plane. The second link16is supported by a tip of the first link15. The second link16, with respect to the first link15, rotates around a third axis c3extending in the vertical direction. Accordingly, a posture of the second link16can be changed within the horizontal plane. The robot1of this embodiment includes actuators that individually rotate each part (the lifting shaft14, the first link15, the second link16, and the hand10) included in the robot around their respective axes. Each actuator is configured as an electric motor3shown inFIG.3. Each electric motor3is electrically connected to the control device5via a drive device such as a driver (not shown) or the like. The controller5outputs control commands (commanded rotation position) or the like to the driver to control the rotation of the electric motor3. The posture detector12includes a plurality of rotation sensors12a. For example, an encoder constitutes the rotation sensors12a. Each rotation sensor12adetects a rotation position of each electric motor3that drives the hand10, the first link15, and the second link16, respectively. Each rotation sensor12ais electrically connected to the controller5and transmits the detected rotation position to the controller5. The controller5is configured as a known computer including a CPU, a ROM, a RAM, an auxiliary storage device, etc. The auxiliary storage device is configured as, for example, an HDD, an SSD, etc. The auxiliary storage device stores robot control programs, etc. for controlling the robot1. The robot control programs include a slip determination program for realize the steps of the slip determination method of the present invention. The controller5outputs the commanded rotation position, or the like to each electric motor3that drives each part of the above described robot1in accordance with a predetermined operation program, a movement command that is input from the user, or the like. The controller5controls to move the hand10to a predetermined command position. The positional displacement detection device8is constituted by, for example, a pre-aligner (wafer aligner). As shown inFIG.1, the positional displacement detection device8includes a rotating base81and a line sensor8. The rotating base81, can allow the wafer2to be rotated by an electric motor (not shown), etc. The rotating base81rotates with the wafer2placed thereon. The rotating base81is formed, for example, in a columnar shape. The line sensor82is constituted by, for example, a transmissive sensor including a light emitting part and a light receiving part. The light emitting part and light receiving part are arranged so as to face each other, at a predetermined interval in the vertical direction. The line sensor82emits the detection light through the light emitting part arranged in a radial direction of the rotating base81, and receives the detected light through the light receiving part provided below the light emitting part. The detected light may be, for example, laser light. When the wafer2is placed on the rotating base81, its outer edge is located between the light emitting part and the light receiving part. The line sensor82is electrically connected to, for example, the controller5. The line sensor82transmits a detection result of the light receiving part to the controller5. The change in the detection result of the light receiving part when the rotating base81rotates depends on a shape of the outer edge of the wafer2. With the shape of such outer edge, the positional displacement in which the center of the wafer2is displaced from a center of the rotating base81can be detected. Therefore, in the positional displacement detection device8, the detecting reference position of the positional displacement is the center of the rotating base81. The controller5acquires the actual positional displacement amount of the wafer2based on the detection result of the light receiving part. Next, taking the determination when the wafer is taken out as an example, the determination of slip occurrence by the robot system100of this embodiment will be described in detail. The slip of the wafer2is prone to occur when the wafer is taken out. Incidentally, the determination of slip occurrence by the robot system100of this embodiment can be performed at any timing in the process in which the robot1transporting the wafer2by the hand10. That is, the transfer of the wafer2by the robot1can be considered to be a series of operations from the removal of the wafer2at one location by the hand10to the placement of the wafer2at another location. Whether or not slippage occurs can be determined at any timing from the start to the end of the series of operations. Depending on the process performed on the wafer2, the surface of the wafer2may have adhesiveness. For example, when the wafer2is removed from the storage device6by the robot1, the wafer2may appear to try to stay there as if it is be stuck to the storage device6. As a result, slippage occurs between the wafer2and the hand10as the wafer2is taken out by the hand10, and the position of the wafer2relative to the hand10is displaced. The robot system100of this embodiment, during operation of the robot1, uses the controller5to monitor information. The information relate to the current flowing through each of the electric motor3for driving each part of the robot1, the position of the electric motor3, the position deviation, the velocity and the acceleration of the electric motor3, the velocity deviation, and the acceleration deviation or the like. In the following description, the position, the velocity and the acceleration with respect to the electric motor3means a rotational position, a rotational velocity and a rotational acceleration, unless otherwise stated. The current value of each electric motor3is measured, for example, by a current sensor provided in a motor drive circuit (not shown). The position of the electric motor3can be obtained, for example, based on a measured value of the rotation sensor12adescribed above. The velocity and the acceleration of the electric motor3can be obtained, for example, by time differentiating the measured value of the rotation sensor12a. The position deviation, the speed deviation, and the acceleration deviation can be obtained by calculating a difference between the above-described position, velocity, acceleration and a target position, a target speed, a target acceleration. In the robot system100of this embodiment, when the robot1removes the wafer2from the storage device6, the controller5determines whether the wafer2slipped or not, based on the current value or the like of the electric motor3. In the following, the determination of the slip in the control device5will be described in detail taking the current value shown inFIG.4and the position deviation shown inFIG.5as an example. InFIG.4A,FIG.4BandFIG.5A,FIG.5B, graphs are shown with each value is plotted on the vertical axis and time is plotted on the horizontal axis.FIG.4A,FIG.4BandFIG.5A,FIG.5Bshow data of a predetermined period (e.g., 2, 3 seconds) when taking out the wafer2. The graphs ofFIG.4A,FIG.4BandFIG.5A,FIG.5Bare merely examples, and various waveforms may be considered depending on situations. FIG.4Ais a graph showing the current value of the electric motor3in the case where no slippage occurs.FIG.4Bis a graph showing the current value of the electric motor3when the slippage occurs. ComparingFIG.4AandFIG.4B, it can be seen that among the plurality of the electric motors3for driving each portion of the robot1, the current value of at least one of the electric motor3has changed according to whether or not slippage occurs. For example, the current waveform flowing through the electric motor3for driving the joint of the second axis c2has several spike portions in the positive direction or negative direction regardless of whether slippage occurs, but when the slippage occurs, the peaks of some spike portions are obviously increased. The controller5acquires the current flowing through the electric motor3through the current sensor described above, and monitors the current (the first step). When the instantaneously increasing current value is too excessive as shown inFIG.4B, the controller5determines that the slippage has occurred when the wafer2is taken out (the second step). The determination of whether the current value is excessive can be simply performed by comparison with a predetermined current threshold value. Alternatively, the slip may be determined by comparing waveforms. Specifically, the controller5stores a reference waveform as appropriate when no slippage is occurring, compares the obtained current waveform with the reference waveform. The controller5calculates the degree of deviation of the graph shape, and determines that slippage has occurred when the degree of deviation exceeds a threshold value. For example, the waveform inFIG.4Acan be adopted as the reference waveform. The current flowing through the electric motor3is determined by a target value of the movement of the electric motor3, and a measured value of the movement of the electric motor3. Therefore, if the occurrence of the slippage can be detected by the current, it is considered that the occurrence of the slippage can be similarly detected by the behavior of the position deviation, the velocity deviation, and the acceleration deviation of the electric motor3. FIG.5shows an example in the deviation of the rotational position.FIG.5Ais a graph showing the deviation of the rotational position when no slippage occurs.FIG.5Bis a graph showing the deviation of the rotational position when the slippage occurs. As shown inFIG.5B, when the slippage occurs, the transition of the position deviation of the electric motor3also shows characteristic behavior, such as the occurrence of large spike in the negative direction. It is considered that the occurrence of slippage can be determined by detecting the characteristic of the positional deviation using an appropriate method. Although the examination showing the waveform is omitted, similarly, it is considered that the occurrence of slippage can be determined from the velocity deviation and the acceleration deviation of the electric motor3. As a cause of the waveform such as the current value to exhibit a behavior different from normal, it is considered various other than the slippage of the wafer2. In this regard, the controller5of this embodiment only extracts the waveform of a limited period such as the current value when the wafer is taken out, and determines the presence or absence of slippage. At the time in which wafer is taken out, slippage of the wafer2is likely to occur. Therefore, erroneous determination regarding slippage can be suppressed. In this embodiment, the controller5determines the slippage of the wafer2by software based on the current value or the like of the electric motor3. Therefore, a special device such as a sensor is unnecessary, so that the configuration can be simplified. In addition, since it is not necessary to modify the hardware, it is easy to apply the present invention to an existing robot system. In the robot system100of this embodiment, the controller5determines whether or not slippage occurs as described above. If it is determined that no slippage occurs, the controller5operates the robot1so as to directly convey the wafer2from the storage device6to the unillustrated processing apparatus (the first route R1). If it is determined that slippage has occurred, the controller5operates the robot1to first transfers the wafer2from the storage device6to the positional displacement detection device8, and then transfer the wafer2from the positional displacement detection device8to the unillustrated processing apparatus (the second route R2). InFIG.1, the first route R1and the second route R2are conceptually shown by arrows. If slippage occurs in the wafer2, the position of the wafer2will be displaced respect to the hand10. When the robot1transfers the wafer2to the positional displacement detection device8according to the second route R2, a displacement occurs between the center of the placed wafer2and the rotational center of the rotating base81accordance with the above-described displacement. The size and direction of this displacement is detected by the positional displacement detection device8. The robot1, at a position capable of offsetting the acquired displacement, takes out the wafer2from the rotating base81by the hand10and transports the wafer2to the processing apparatus of the transfer destination. In this way, the slippage of the wafer2can be corrected, and the wafer2can be correctly transported to the processing apparatus in a state where there is no positional displacement. In this embodiment, since the slippage of the wafer2is detected by monitoring such as the current value of the electric motor3, it is possible to detect the slippage almost in real time. Therefore, immediately after removing the wafer2from the storage device6(e.g., the state ofFIG.1), the controller5is in a state of completing the determination of whether the slippage has occurred. When the controller5determined that slippage has occurred, the controller5can switch the transfer route of the wafer2in situ so as to transfer the wafer2to the positional displacement detection device8. If all the wafer2are transported via the positional displacement detection device8, the transfer tact time would increase greatly. However, in this embodiment, since the second route R2is adopted only when the slippage of the wafer2is detected, it is possible to prevent the unnecessary detecting of no displacement. In addition, since there is no need to specially operate the robot1to detect slippage, the increase of the transport tact time is substantially zero in the case of the first route R1. Thus, the robot system100of this embodiment can transfer the wafer2efficiently while corresponding to irregularly occurring slippage. As described above, the robot system100of this embodiment includes the robot1and the controller5. The robot1has one or more joints driven by the electric motor3, and capable of holding the wafer2by the hand10. The controller5gives commands to the robot1to control it. When the robot1holds and transports the wafer2with the hand10, the controller5determines whether or not slippage has occurred between the hand10and the wafer2based on information about the electric motor3. Accordingly, it allows immediate determination of the occurrence of slippage between the hand10of the robot1and the held wafer2without requiring a special detection device and without the need for special movements of the robot1. In the robot system100of this embodiment, the controller5determines an occurrence of slippage based on the information related to the electric motor3obtained during the predetermined period when the hand10takes out the wafer2. Accordingly, since the occurrence of slip is determined based only on the information obtained during the period in which the slippage is likely to occur, erroneous determination can be prevented. In the robot system100of this embodiment, the information for determining the presence or absence of the slippage include at least any one of the following: the current value, the position deviation, the velocity deviation, and the acceleration deviation of the electric motor3. Accordingly, it is possible to appropriately determine whether or not slippage occurs. The robot system100of this embodiment includes the positional displacement detection device8capable of detecting the positional deviation of the wafer2. The controller5controls the robot1to transport the wafer2by the first route R1that does not go through the positional displacement detection device8when it is determined that no slippage has occurred. The controller5controls the robot1to transport the wafer2by the second route R2that go through the positional displacement detection device8when it is determined that the slippage has occurred. Accordingly, the wafer2can be correctly transported efficiently while correcting the position of the wafer2according to the occurrence of the slippage. Next, a variation of the present invention will be described. In the description of the variation, members identical or similar to those of the above-described embodiment may not be described and instead the same reference signs as in the above-described embodiment are given on the drawings. In the robot system100of this variation, the controller5determines whether or not slippage has occurred as described above during the transportation of the wafer. When it is determined that no slippage has occurred, the controller5sets the transfer route of the wafer2to the first route R1. When it is determined that the slippage has occurred, the controller5sets the transfer route of the wafer2to the second route R2. The determination of whether or not the slippage has occurred can be performed based on the current value of the electric motor3, as described in the above embodiment. However, it is not limited thereto. For example, the slippage can be calculated based on an analysis result of an image obtained by photographing the wafer2being transported with a camera (not shown). The analysis of the image can be performed by the controller5or by a computer separate from the controller5. The transfer route of the wafer2can be switched based on the slippage amount instead of determining whether or not slippage has occurred. The slippage amount can be obtained by analyzing the image taken by the camera. The controller5compares the calculated slippage amount with a preset threshold value, to determine whether or not to switch the transfer route of the wafer2. When the slippage amount is equal to or less than the threshold value, since the positional deviation of the wafer2with respect to the hand10is within the allowable range, the wafer2is transported by the first route R1as originally scheduled. When the slippage amount exceeds the threshold value, the transfer route of the wafer2is changed to the second route R2. For detection of slippage of the wafer2, an optical sensor (not shown) provided on the device side can be used instead of the camera, for example. The optical sensor is disposed at an appropriate position in the transport path of the wafer2. If the slippage occurs in the wafer2, the optical sensor detects the wafer2being transported at a different timing from normal. This makes it possible to determine whether or not slippage has occurred. As the optical sensor, it is also possible to use a line sensor capable of detecting the outer edge of the wafer2being transported. In this case, the slippage amount of the wafer2can be obtained. While the preferred embodiment and the variation embodiment of the present invention have been described above, the above configuration can be changed, for example, as follows. It is not limited to the slippage when the robot1takes out the wafer2from the transfer source, the slippage when placing the wafer2to the transfer destination can also be detected. If slippage is detected when placing the wafer2to the transfer destination, it is preferable that the controller5controls the robot1to take out the wafer2placed at the transfer destination again and transfer it to the positional displacement detection device8, then place the wafer2to the transfer destination again after correcting the displacement. The controller5may determine the presence or absence of the slippage from not only one but a combination of several factors such as the current value and the position deviation or the like of the electric motor3. When the wafer2is transported by the hand10, in most cases, each of the plurality of joints is driven by the electric motor3. Therefore, it is also conceivable to determine the presence or absence of the slippage by combination of the information such as the current value in the plurality of electric motors3. In the embodiment described above, the controller5determines whether or not slippage has occurred. However, it is considered that the waveform of the current value and the like may differ between the case where the slippage of the wafer2is 1 mm and the case where the slip is 10 mm, for example. Therefore, there is leeway for quantitatively determining the size of the slippage by monitoring the current value or the like. It is also possible to make a learning model estimate the size of the slippage from the waveform by machine learning the relationship between the waveform such as the current value and the size of the occurred slippage. In the embodiment described above, the controller5determines whether or not the slippage has occurred based on the information about the electric motor. Alternatively or additionally, the controller5may estimate the slippage amount of the wafer2relative to the hand10based on the information about the electric motor. The slippage amount can be calculated based on a period in which the value relating to the information such as the current value is continuously excessive, and the amount of movement of the robot1in the period, for example. After estimating the slippage amount, the controller5may determine whether or not the slippage has occurred based on a result of comparing the obtained slippage amount with the predetermined threshold value. If automatic correction of the positional deviation is not necessary, the positional displacement detection device8can be omitted. DESCRIPTION OF THE REFERENCE NUMERALS 1robot2wafer3electric motor5controller (control part)8positional displacement detection device10hand (holding part)100robot systemR1first routeR2second route | 24,674 |
11862508 | DETAILED DESCRIPTION The following disclosure provides many different embodiments, or examples, for implementing different features of the invention. Specific examples of components and arrangements are described below to simplify the present disclosure. These are, of course, merely examples and are not intended to be limiting. For example, the formation of a first feature over or on a second feature in the description that follows may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features may be formed between the first and second features, such that the first and second features may not be in direct contact. In addition, the present disclosure may repeat reference numerals and/or letters in the various examples. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed. Further, spatially relative terms, such as “beneath,” “below,” “lower,” “above,” “upper” and the like, may be used herein for ease of description to describe one element or feature's relationship to another element(s) or feature(s) as illustrated in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The apparatus may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein may likewise be interpreted accordingly. Embodiments will be described with respect to a specific context, namely, a FinFET device and a method of forming the same. Various embodiments presented herein are discussed in the context of a FinFET device formed using a gate-last process. In other embodiments, a gate-first process may be used. Various embodiments discussed herein allow for improving a dielectric material gap-fill performance for a trench formed during a fin cut process, reducing or avoiding issues due to a seam and/or void formation in the dielectric material within the trench, reducing or avoiding shorting between contact plugs, and improving device and yield performance. In some embodiments, the trench formed during the fin cut process is filled with a plurality of dielectric materials. In some embodiments, the trench filling process may include filling the trench with a first dielectric material, partially removing the first dielectric material from the trench such that an upper portion of the trench is not filled with a dielectric material, and filling the upper portion of the trench with a second dielectric material. The second dielectric material may be same or different from the first dielectric material. FIG.1illustrates an example of a FinFET in a three-dimensional view, in accordance with some embodiments. The FinFET comprises a fin52on a substrate50(e.g., a semiconductor substrate). Isolation regions56are disposed in the substrate50, and the fin52protrudes above and from between neighboring STI regions56. Although the STI regions56are described/illustrated as being separate from the substrate50, as used herein the term “substrate” may be used to refer to just the semiconductor substrate or a semiconductor substrate inclusive of isolation regions. Additionally, although the fin52is illustrated as a single, continuous material as the substrate50, the fin52and/or the substrate50may comprise a single material or a plurality of materials. In this context, the fin52refers to the portion extending between the neighboring STI regions56. A gate dielectric layer92is along sidewalls and over a top surface of the fin52, and a gate electrode94is over the gate dielectric layer92. Source/drain regions70are disposed in opposite sides of the fin52with respect to the gate dielectric layer92and the gate electrode94.FIG.1further illustrates reference cross-sections that are used in later figures. Cross-section A-A is along a longitudinal axis of the gate electrode94and in a direction, for example, perpendicular to a direction of a current flow between the epitaxial source/drain regions70of the FinFET. Cross-section B-B is perpendicular to cross-section A-A and is along a longitudinal axis of the fin52and in a direction of, for example, the current flow between the epitaxial source/drain regions70of the FinFET. Cross-section C-C is parallel to cross-section A-A and extends through the source/drain region70of the FinFET. Subsequent figures refer to these reference cross-sections for clarity. FIGS.2,3,4,5,6,7,8A,8B,9A,9B,10A,10B,10C,10D,11A,11B,12A,12B,13A,13B,14A,14B,15A,15B,16A,16B,17A,17B,18A,18B,19A,19B,20A,20B,21A,21B,22A,22B,23A,23B,23C,24A,24B,25A,25B,26A,26B,27A,27B,28A,28B,29A, and29B are cross-sectional views of intermediate stages in the manufacturing of a FinFET device in accordance with some embodiments.FIGS.2through7illustrate cross-sectional views along the reference cross-section A-A illustrated inFIG.1, except for multiple fins.FIGS.8B-29B and23Care illustrated along the reference cross-section B-B illustrated inFIG.1, except for multiple gate structures.FIGS.10C and10Dare illustrated along the reference cross-section C-C illustrated inFIG.1, except for multiple fins and multiple source/drain regions.FIGS.8A-29Aare illustrated along the reference cross-section A-A illustrated inFIGS.8B-29B, respectively. InFIG.2, a substrate50is provided. The substrate50may be a semiconductor substrate, such as a bulk semiconductor, a semiconductor-on-insulator (SOI) substrate, or the like, which may be doped (e.g., with a p-type or an n-type dopant) or undoped. The substrate50may be a wafer, such as a silicon wafer. Generally, an SOI substrate is a layer of a semiconductor material formed on an insulator layer. The insulator layer may be, for example, a buried oxide (BOX) layer, a silicon oxide layer, or the like. The insulator layer is provided on a substrate, typically a silicon or glass substrate. Other substrates, such as a multi-layered or gradient substrate may also be used. In some embodiments, the semiconductor material of the substrate50may include silicon; germanium; a compound semiconductor including silicon carbide, gallium arsenic, gallium phosphide, indium phosphide, indium arsenide, and/or indium antimonide; an alloy semiconductor including SiGe, GaAsP, AlInAs, AlGaAs, GaInAs, GaInP, and/or GaInAsP; or combinations thereof. In some embodiments, the substrate50may have an n-type region and a p-type region (not individually illustrated). The n-type region is for forming n-type devices, such as NMOS transistors, e.g., n-type FinFETs. The p-type region is for forming p-type devices, such as PMOS transistors, e.g., p-type FinFETs. The n-type region may be physically separated from the p-type region, and any number of device features (e.g., other active devices, doped regions, isolation structures, etc.) may be disposed between the n-type region and the p-type region. InFIG.3, fins52are formed in the substrate50. The fins52are semiconductor strips. In some embodiments, the fins52may be formed in the substrate50by etching trenches in the substrate50. The etching may be any acceptable etch process, such as a reactive ion etch (RIE), neutral beam etch (NBE), a combination thereof, or the like. The etch process may be anisotropic. The fins52extend from an upper surface50tof an un-patterned portion of the substrate50. The un-patterned portion of the substrate50may be referred to as a substrate. The fins52may be formed by any suitable method. For example, the fins52may be formed using one or more photolithography processes, including double-patterning or multi-patterning processes. Generally, double-patterning or multi-patterning processes combine photolithography and self-aligned processes, allowing patterns to be created that have, for example, pitches smaller than what is otherwise obtainable using a single, direct photolithography process. For example, in one embodiment, a sacrificial layer is formed over a substrate and patterned using a photolithography process. Spacers are formed alongside the patterned sacrificial layer using a self-aligned process. The sacrificial layer is then removed, and the remaining spacers may then be used as a mask to form the fins52. InFIG.4, an insulation material54is formed over the substrate50and between neighboring fins52. The insulation material54may be an oxide, such as silicon oxide, a nitride, a combination thereof, or the like, and may be formed by a high density plasma chemical vapor deposition (HDP-CVD), a flowable CVD (FCVD) (e.g., a CVD-based material deposition in a remote plasma system and post curing to make it convert to another material, such as an oxide), a combination thereof, or the like. Other insulation materials formed by any acceptable process may be used. In the illustrated embodiment, the insulation material54is silicon oxide formed by a FCVD process. An anneal process may be performed once the insulation material is formed. In an embodiment, the insulation material54is formed such that excess insulation material54covers the fins52. Although the insulation material54is illustrated as a single layer, some embodiments may utilize multiple layers. For example, in some embodiments, a liner (not shown) may first be formed along surfaces of the substrate50and the fins52. Thereafter, a fill material, such as those discussed above may be formed over the liner. InFIG.5, a removal process is applied to the insulation material54to remove excess portions of the insulation material54over the fins52. In some embodiments, a planarization process, such as a chemical mechanical polishing (CMP) process, an etch back process, combinations thereof, or the like, may be utilized. The planarization process exposes the fins52, such that top surfaces of the fins52and the top surface of the insulation material54are substantially level or coplanar (within process variations) after the planarization process is completed. InFIG.6, the insulation material54(seeFIG.5) is recessed to form shallow trench isolation (STI) regions56. The insulation material54is recessed such that upper portions of fins52protrude from between neighboring STI regions56. Further, the top surfaces of the STI regions56may have a flat surface as illustrated, a convex surface, a concave surface (such as dishing), or a combination thereof. The top surfaces of the STI regions56may be formed flat, convex, and/or concave by an appropriate etch. The STI regions56may be recessed using an acceptable etching process, such as one that is selective to the material of the insulation material54(e.g., etches the material of the insulation material54at a faster rate than the material of the fins52). For example, a chemical oxide removal with a suitable etch process using, for example, dilute hydrofluoric (dHF) acid may be used. The process described with respect toFIGS.2through6is just one example of how the fins52may be formed. In some embodiments, the fins may be formed by an epitaxial growth process. For example, a dielectric layer can be formed over a top surface of the substrate50, and trenches can be etched through the dielectric layer to expose the underlying substrate50. Homoepitaxial structures can be epitaxially grown in the trenches, and the dielectric layer can be recessed such that the homoepitaxial structures protrude from the dielectric layer to form fins. Additionally, in some embodiments, heteroepitaxial structures can be used for the fins. For example, the fins52inFIG.5can be recessed, and a material different from the fins52may be epitaxially grown over the recessed fins52. In such embodiments, the fins comprise the recessed material as well as the epitaxially grown material disposed over the recessed material. In an even further embodiment, a dielectric layer can be formed over a top surface of the substrate50, and trenches can be etched through the dielectric layer. Heteroepitaxial structures can then be epitaxially grown in the trenches using a material different from the substrate50, and the dielectric layer can be recessed such that the heteroepitaxial structures protrude from the dielectric layer to form the fins. In some embodiments where homoepitaxial or heteroepitaxial structures are epitaxially grown, the epitaxially grown materials may be in situ doped during growth, which may obviate prior and subsequent implantations, although in situ and implantation doping may be used together. Still further, it may be advantageous to epitaxially grow a material in the n-type region of the substrate different from a material in the p-type region of the substrate50. In various embodiments, upper portions of the fins52may be formed from silicon germanium (SixGe1-x, where x can be in the range of 0 to 1), silicon carbide, pure or substantially pure germanium, a III-V compound semiconductor, a II-VI compound semiconductor, or the like. For example, the available materials for forming III-V compound semiconductor include, but are not limited to, InAs, AlAs, GaAs, InP, GaN, InGaAs, InAlAs, GaSb, AlSb, AlP, GaP, and the like. Further inFIG.6, appropriate wells (not shown) may be formed in the fins52and/or the substrate50. In some embodiments, a P well may be formed in the n-type region of the substrate50, and an N well may be formed in the p-type region of the substrate50. In some embodiments, a P well or an N well are formed in both the n-type and p-type regions of the substrate50. In the embodiments with different well types, the different implant steps for the n-type region and the p-type region of the substrate50may be achieved using a photoresist or other masks (not shown). For example, a first photoresist may be formed over the fins52and the STI regions56in both the n-type region and the p-type region of the substrate50. The first photoresist is patterned to expose the p-type region of the substrate50. The first photoresist can be formed by using a spin-on technique and can be patterned using acceptable photolithography techniques. Once the first photoresist is patterned, an n-type impurity implantation is performed in the p-type region of the substrate50, while the remaining portion of the first photoresist acts as a mask to substantially prevent n-type impurities from being implanted into the n-type region of the substrate50. The n-type impurities may be phosphorus, arsenic, antimony, or the like, implanted in the region to a dose of equal to or less than 1015cm−2, such as between about 1012cm−2and about 1015cm−2. In some embodiments, the n-type impurities may be implanted at an implantation energy of about 1 keV to about 10 keV. After the implantation, the first photoresist is removed, such as by an acceptable ashing process followed by a wet clean process. Following the implantation of the p-type region of the substrate50, a second photoresist is formed over the fins52and the STI regions56in both the p-type and n-type regions of the substrate50. The second photoresist is patterned to expose the n-type region of the substrate50. The second photoresist can be formed by using a spin-on technique and can be patterned using acceptable photolithography techniques. Once the second photoresist is patterned, a p-type impurity implantation may be performed in the n-type region of the substrate50, while the remaining portion of the second photoresist acts as a mask to substantially prevent p-type impurities from being implanted into the p-type region of the substrate50. The p-type impurities may be boron, BF2, indium, or the like, implanted in the region to a dose of equal to or less than 1015cm−2, such as between about 1012cm−2and about 1015cm−2. In some embodiments, the p-type impurities may be implanted at an implantation energy of about 1 keV to about 10 keV. After the implantation, the second photoresist may be removed, such as by an acceptable ashing process followed by a wet clean process. After performing the implantations of the n-type and p-type regions of the substrate50, an anneal process may be performed to activate the p-type and/or n-type impurities that were implanted. In some embodiments, the grown materials of epitaxial fins may be in situ doped during growth, which may obviate the implantations, although in situ doping and implantation doping may be used together. InFIG.7, a dummy dielectric layer60is formed on the fins52. The dummy dielectric layer60may be, for example, silicon oxide, silicon nitride, a combination thereof, or the like, and may be deposited or thermally grown according to acceptable techniques. Subsequently, a dummy gate layer62is formed over the dummy dielectric layer60. The dummy gate layer62may be deposited over the dummy dielectric layer60and then planarized using, for example, a CMP process. The dummy gate layer62may be a conductive material and may be selected from a group including amorphous silicon, polycrystalline-silicon (polysilicon), poly-crystalline silicon-germanium (poly-SiGe), metallic nitrides, metallic silicides, metallic oxides, metals, combinations thereof, and the like. The dummy gate layer62may be deposited by physical vapor deposition (PVD), CVD, sputter deposition, or other techniques known and used in the art for depositing conductive materials. The dummy gate layer62may be made of other materials that have a higher etching selectivity than materials of the STI regions56. It is noted that the dummy dielectric layer60is shown covering only the fins52for illustrative purposes only. In some embodiments, the dummy dielectric layer60may be deposited such that the dummy dielectric layer60covers the STI regions56, extending between the dummy gate layer62and the STI regions56. FIGS.8A,8B,9A,9B,10A,10B,10C,10D,11A,11B,12A,12B,13A,13B,14A,14B,15A,15B,16A,16B,17A,17B,18A,18B,19A,19B,20A,20B,21A,21B,22A,22B,23A,23B,23C,24A,24B,25A,25B,26A,26B,27A,27B,28A,28B,29A, and29B illustrate various additional steps in the manufacturing of a FinFET device in accordance with some embodiments.FIGS.8A,8B,9A,9B,10A,10B,10C,10D,11A,11B,12A,12B,13A,13B,14A,14B,15A,15B,16A,16B,17A,17B,18A,18B,19A,19B,20A,20B,21A,21B,22A,22B,23A,23B,23C,24A,24B,25A,25B,26A,26B,27A,27B,28A,28B,29A, and29B illustrate features in either of the n-type region and the p-type region of the substrate50. For example, the structures illustrated inFIGS.8A,8B,9A,9B,10A,10B,10C,10D,11A,11B,12A,12B,13A,13B,14A,14B,15A,15B,16A,16B,17A,17B,18A,18B,19A,19B,20A,20B,21A,21B,22A,22B,23A,23B,23C,24A,24B,25A,25B,26A,26B,27A,27B,28A,28B,29A, and29B may be applicable to both the n-type region and the p-type region of the substrate50. Differences (if any) in the structures of the n-type region and the p-type region of the substrate50are described in the text accompanying each figure. InFIGS.8A and8B, the dummy gate layer62(seeFIG.7) is patterned to form dummy gates64. The dummy gate layer62may be patterned using acceptable photolithography and etching techniques. In some embodiments, the etching techniques may include one or more anisotropic etch processes such as RIE, NBE, a combination thereof, or the like. The dummy gates64cover channel regions58of the fins52. The pattern of the patterned mask may be used to physically separate each of the dummy gates64from adjacent ones of the dummy gates64. The dummy gates64may also have a lengthwise direction substantially perpendicular to the lengthwise direction of respective one of the fins52. As described below in greater detail, the dummy gates64are sacrificial gates and are subsequently replaced by replacement gates. Accordingly, dummy gates64may also be referred to as sacrificial gates. In other embodiments, some of the dummy gates64are not replaced and remain in the final structure of the resulting FinFET device. The dummy gates64have top surfaces, which are disposed above the fins52at a height H1as measured from the top surfaces of the fins52. In some embodiments, the height H1is between about 90 nm and about 120 nm. Further inFIGS.8A and8B, gate seal spacers66may be formed on exposed surfaces of the dummy gates64and/or the fins52. A thermal oxidation or a deposition followed by an anisotropic etch may form the gate seal spacers66. The gate seal spacers66may comprise silicon oxide, silicon nitride, SiCN, SiOC, SiOCN, a combination thereof, or the like. After the formation of the gate seal spacers66, implants for lightly doped source/drain (LDD) regions (not explicitly illustrated) may be performed. In the embodiments with different device types, similar to the implants discussed above inFIG.6, a mask, such as a photoresist, may be formed over the n-type region, while exposing the p-type region, and appropriate type (e.g., p-type) impurities may be implanted into the exposed fins52in the p-type region. The mask may then be removed. Subsequently, a mask, such as a photoresist, may be formed over the p-type region, while exposing the n-type region, and appropriate type impurities (e.g., n-type) may be implanted into the exposed fins52in the n-type region. The mask may then be removed. The n-type impurities may be the any of the n-type impurities previously discussed, and the p-type impurities may be the any of the p-type impurities previously discussed. The lightly doped source/drain regions may have a dose of impurities of from about 1012cm−2to about 1016cm−2. In some embodiments, the suitable impurities may be implanted at an implantation energy of about 1 keV to about 10 keV. An anneal may be used to activate the implanted impurities. InFIGS.9A and9B, gate spacers68are formed on the gate seal spacers66along sidewalls of the dummy gates64. The gate spacers68may be formed by conformally depositing an insulating material and subsequently anisotropically etching the insulating material. The insulating material of the gate spacers68may comprise silicon oxide, silicon nitride, SiCN, SiOC, SiOCN, a combination thereof, or the like. In some embodiments, the gate spacers68may comprise a plurality of layers (not shown), such that the layers comprise different materials. In some embodiments, the gate spacers68and the gate seal spacers66may comprise a same material. In other embodiments, the gate spacers68and the gate seal spacers66may comprise different materials. It is noted that the above disclosure generally describes a process of forming spacers and LDD regions. Other processes and sequences may be used. For example, fewer or additional spacers may be utilized, different sequence of steps may be utilized (e.g., the gate seal spacers66may not be etched prior to forming the gate spacers68, yielding “L-shaped” gate seal spacers, spacers may be formed and removed, and/or the like). Furthermore, the n-type and p-type devices may be formed using a different structures and steps. For example, LDD regions for n-type devices may be formed prior to forming the gate seal spacers66while the LDD regions for p-type devices may be formed after forming the gate seal spacers66. InFIGS.10A and10B, epitaxial source/drain regions70are formed in the fins52to exert stress in the respective channel regions58, thereby improving device performance. The epitaxial source/drain regions70are formed in the fins52such that each dummy gate64is disposed between respective neighboring pairs of the epitaxial source/drain regions70. In some embodiments, the epitaxial source/drain regions70may extend into the fins52. In some embodiments, the gate spacers68are used to separate the epitaxial source/drain regions70from the dummy gates64by an appropriate lateral distance so that the epitaxial source/drain regions70do not short out subsequently formed gates of the resulting FinFET device. The epitaxial source/drain regions70in the n-type region of the substrate50may be formed by masking the p-type region of the substrate50and etching source/drain regions of the fins52in the n-type region of the substrate50to form recesses in the fins52. Then, the epitaxial source/drain regions70in the n-type region of the substrate50are epitaxially grown in the recesses. The epitaxial source/drain regions70may include any acceptable material, such as appropriate for n-type FinFETs. For example, if the fin52is silicon, the epitaxial source/drain regions70in the n-type region of the substrate50may include materials exerting a tensile strain in the channel region58, such as silicon, SiC, SiCP, SiP, a combination thereof, or the like. The epitaxial source/drain regions70in the n-type region of the substrate50may have surfaces raised from respective surfaces of the fins52and may have facets. The epitaxial source/drain regions70in the p-type region of the substrate50may be formed by masking the n-type region of the substrate50and etching source/drain regions of the fins52in the p-type region of the substrate50to form recesses in the fins52. Then, the epitaxial source/drain regions70in the p-type region of the substrate50are epitaxially grown in the recesses. The epitaxial source/drain regions70may include any acceptable material, such as appropriate for p-type FinFETs. For example, if the fin52is silicon, the epitaxial source/drain regions70in the p-type region of the substrate50may comprise materials exerting a compressive strain in the channel region58, such as SiGe, SiGeB, Ge, GeSn, a combination thereof, or the like. The epitaxial source/drain regions70in the p-type region of the substrate50may also have surfaces raised from respective surfaces of the fins52and may have facets. The epitaxial source/drain regions70and/or the fins52may be implanted with dopants, similar to the process previously discussed for forming lightly-doped source/drain regions, followed by an anneal. The epitaxial source/drain regions70may have an impurity concentration of between about 1019cm−3and about 1021cm−3. The n-type and/or p-type impurities for the epitaxial source/drain regions70may be any of the impurities previously discussed. In some embodiments, the epitaxial source/drain regions70may be in situ doped during growth. As a result of the epitaxy processes used to form the epitaxial source/drain regions70in the n-type region and the p-type region of the substrate50, upper surfaces of the epitaxial source/drain regions have facets which expand laterally outward beyond sidewalls of the fins52. In some embodiments, these facets cause adjacent epitaxial source/drain regions70of a same FinFET to merge as illustrated byFIG.10C. In other embodiments, adjacent epitaxial source/drain regions70remain separated after the epitaxy process is completed as illustrated byFIG.10D. In the embodiments illustrated inFIGS.10C and10D, the gate spacers68are formed covering a portion of the sidewalls of the fins52that extend above the STI regions56thereby blocking the epitaxial growth. In other embodiments, the spacer etch used to form the gate spacers68may be adjusted to remove the spacer material from the sidewalls of the fins52to allow the epitaxially grown region to extend to the surface of the STI region56. InFIGS.11A and11B, an interlayer dielectric (ILD)74is deposited over the structure illustrated inFIGS.10A and10B. The ILD74may be formed of a dielectric material, and may be deposited by any suitable method, such as CVD, plasma-enhanced CVD (PECVD), FCVD, a combination thereof, or the like. Dielectric materials may include Phospho-Silicate Glass (PSG), Boro-Silicate Glass (BSG), Boron-Doped Phospho-Silicate Glass (BPSG), undoped Silicate Glass (USG), a combination thereof, or the like. Other insulation materials formed by any acceptable process may be also used. In some embodiments, an etch stop layer (ESL)72is disposed between the ILD74, and the epitaxial source/drain regions70and the gate spacers68. The ESL72may comprise a dielectric material, such as, silicon nitride, silicon oxide, silicon oxynitride, a combination thereof, or the like, having a different etch rate than the material of the overlying ILD74. InFIGS.12A and12B, a planarization process, such as a CMP process, may be performed to level the top surface of the ILD74with the topmost surface of the ESL72. After performing the planarization process, a hard mask layer76is formed over the dummy gates64, the ILD74, and the ESL72. In some embodiments, the hard mask layer76may comprise one or more layers of silicon oxide, SiN, SiON, a combination thereof, or the like, and may be formed using ALD, CVD, PECVD, a combination thereof, or the like. FIGS.13A,13B,14A,14B,15A,15B,16A,16B,17A, and17Billustrate a fin cut process performed on the structure ofFIGS.12A and12Bin accordance with some embodiments. InFIGS.13A and13B, a patterning process is performed on the hard mask layer76to form a trench78in the hard mask layer76over the dummy gate64A. The trench78exposes the dummy gate64A. In some embodiments, the hard mask layer76is patterned using suitable photolithography and etching processes. The etching processes may comprise one or more wet etch processes, one or more dry etching process, combinations thereof, or the like. The etching processes may be anisotropic etching processes. In some embodiments, etchants used for etching the hard mask layer76may comprise CHxFy(with x being between 1 and 3, with y being between 1 and 3, and with x+y being equal to 4), O2, Ar, He, a combination thereof, or the like. In some embodiments, the patterning process further removes a portion of the dummy gate64A and portions of the gate seal spacers66. In such embodiments, the trench78extends below a bottom surface of the hard mask layer76. In some embodiments, the trench78has sloped sidewalls, such that a width of the trench78decreases as the trench78extends toward the dummy gate64A. In some embodiments, the trench78has a width W1at a top surface of the hard mask layer76and a depth D1as measured from the top surface of the hard mask layer76. In some embodiments, the width W1is between about 26 nm and about 30 nm. In some embodiments, the depth D1is between about 35 nm and about 50 nm. In some embodiments, a ratio of D1/W1is between about 1.17 and about 1.92. InFIGS.14A and14B, the dummy gate64A exposed by the trench78(seeFIG.13B) is removed, such that the trench78is extended toward the substrate50and exposes the dummy dielectric layer60. In some embodiments, the dummy gate64A is removed by a suitable etching process. For example, the etching process may include a dry etch process using etchant gas(es) that selectively etch the material of the dummy gate64A without etching the gate seal spacers66and the dummy dielectric layer60. In some embodiments, the etchant gases may comprise CF4, Ar, HBr, O2, He, NF3, H2, a combination thereof, or the like. The dummy dielectric layer60may be used as an etch stop layer when the dummy gate64A is etched. In some embodiments, the etching process for removing the dummy gate64A may also etch the hard mask layer76, such that a thickness of the hard mask layer76is reduced. InFIGS.15A and15B, after removing the dummy gate64A (seeFIGS.13A and13B), the dummy dielectric layer60is removed. In some embodiments, the dummy dielectric layer60may be removed using one or more suitable etching processes that selectively etch the dummy dielectric layer60without etching the gate seal spacers66and the fins52. The suitable etching processes may be one or more dry etching process, one or more wet etching process, combinations thereof, or the like. In some embodiments, etchants used for etching the dummy dielectric layer60may comprise CF4, Ar, He, a combination thereof, or the like. In some embodiments, the etching process for removing the dummy dielectric60may also etch the hard mask layer76, such that a thickness of the hard mask layer76is further reduced. InFIGS.16A and16B, after removing the dummy dielectric layer60, exposed portions of the channel regions58of the fins52are removed, such that the trench78is extended toward the substrate50. In some embodiments, the exposed portions of the channel regions58of the fins52may be removed using one or more suitable etching processes that selectively etch the material of the fins52without etching the gate seal spacers66and the STI regions56. In some embodiments, the exposed portions of the channel regions58of the fins52are removed by an anisotropic dry etch process. In some embodiments, the anisotropic dry etch process is performed using etchant gases such as SixCly, O2, HBr, Ar, He, a combination thereof, or the like. In some embodiments, after removing the exposed portions of the channel regions58of the fins52, the trench78has a depth D2as measured from a top surface of the fins52and a depth D3as measured from a top surface of the STI regions56. In some embodiments, the depth D2is between about 20 nm and about 30 nm. In some embodiments, the depth D3is between about 15 nm and about 25 nm. In some embodiments, the etching process for removing the exposed portions of the channel regions58of the fins52may also etch the hard mask layer76, such that a thickness of the hard mask layer76is further reduced. InFIGS.17A and17B, after removing the exposed portions of the channel regions58of the fins52, exposed portions of the fins52and portions of the substrate50below the exposed portions of the fins52are removed, such that the trench78is extended into the substrate50. In some embodiments, the removal process may comprise one or more suitable etching processes that selectively etch the material of the fins52without etching the gate seal spacers66and the STI regions56. In some embodiments, the suitable etching processes may comprise an anisotropic dry etch process. In some embodiments, the anisotropic dry etch process is performed using etchant gases such as O2, HBr, Ar, He, a combination thereof, or the like. In some embodiments, after removing the exposed portions of the fins52and the portions of the substrate50below the exposed portions of the fins52, the trench78has a depth D4as measured from the upper surface50tof the substrate50, a depth D5as measured from the top surface of the hard mask layer76, and a width W2at the top surface of the hard mask layer76. In some embodiments, the depth D4is between about 30 nm and about 50 nm. In some embodiments, the depth D5is between about 250 nm and about 300 nm. In some embodiments, the width W2is between about 22 nm and about 26 nm. In some embodiments, an aspect ratio of the trench78, defined as a ratio of the depth D5to the width W2(D5/W2), is between about 9.62 and about 13.6. In some embodiments, the etching process for removing the exposed portions of the fins52and the portions of the substrate50below the exposed portions of the fins52may also etch the hard mask layer76, such that a thickness of the hard mask layer76is further reduced. Further inFIGS.17A and17B, the trench78cuts each of the fins52into two disconnected portions. As described below in greater detail, the trench78is filled with one or more dielectric materials to electrically isolate the disconnected portions of the fins52. Accordingly, devices formed from the disconnected portions of the fins52are also electrically isolated. FIGS.18A,18B,19A,19B,20A,20B,21A, and21Billustrate a dielectric gap filling process performed on the trench78(seeFIGS.17A and17B) in accordance with some embodiments. InFIGS.18A and18B, a dielectric material80is deposited in the trench78(seeFIG.17B) and over the hard mask layer76. In some embodiments, the dielectric material80comprises an oxide material (such as silicon oxide, or the like), a nitride material (such as silicon nitride, or the like), an oxynitride material (such as silicon oxynitride, or the like), a combination thereof, or the like, and may be formed using ALD, CVD, PECVD, a combination thereof, or the like. In some embodiments, due to a high aspect ratio of the trench78, a seam82or void (not shown) may be formed in the dielectric material80within the trench78. In some embodiments, the seam82extends below the top surface of the fins52. InFIGS.19A and19B, in some embodiments, a planarization process is performed on the dielectric material80. The planarization process may comprise a CMP process, an etch back process, a combination thereof, or the like. In some embodiments, the planarization process exposes the dummy gates64, such that a top surface of the dielectric material80, top surfaces of the dummy gates64and the top surface of the ILD layer74are substantially level (within process variations) after the planarization process is completed. In such embodiments, the planarization process removes the hard mask layer76and portions of the ESL72over the dummy gates64. In some embodiments, the planarization process further removed portions of the dummy gates64, the gate seal spacers66, the gate spacers68, and the ILD74. In such embodiments, after performing the planarization process, the dummy gates64have top surfaces, which are disposed above the fins52at a height H2as measured from the top surfaces of the fins52. In some embodiments, the height H2is less than the height H1(seeFIG.8B). In some embodiments, the height H2is between about 80 nm and about 90 nm. InFIGS.20A and20B, in some embodiments, the dielectric material80is recessed below the top surfaces of the fins52. In the illustrated embodiment, after recessing the dielectric material80, a top surface of the dielectric material80is below a bottom surface of the adjacent epitaxial source/drain regions70. In other embodiments, the top surface of the dielectric material80may be above the bottom surface of the adjacent epitaxial source/drain regions70. In some embodiments, the dielectric material80is recessed below the top surface of the fin52to a depth D6. In some embodiments, the depth D6is between about 150 nm and about 170 nm. In some embodiments, the dielectric material80is recessed below the top surface of the STI regions56to a depth D7. In some embodiments, the depth D7is between about 120 nm and about 150 nm. In some embodiments, the recessing process comprises a suitable etching process that selectively etches the dielectric material80without significantly etching the gate seal spacers66, the dummy gates64, the ESL72, and the ILD74. The suitable etching process may include a dry etch process, a wet etch process, a combination thereof, or the like. In some embodiments, the etching process for recessing the dielectric material80is performed using etchants such as NF3, HF, NH3, a combination thereof, or the like. In some embodiments, by leaving a portion of the dielectric material80in the trench78, an aspect ratio of the unfilled portion of the trench78is reduced. The unfilled portion of the trench78has a width W3at a top of the trench78, and a depth D8as measured from the top surfaces of the dummy gates64. In some embodiments, the depth D8is between about 200 nm and about 250 nm. In some embodiments, the aspect ratio of the unfilled portion of the trench78, defined as a ratio of the depth D8to the width W3(D8/W3), is between about 9 and about 12. In some embodiments, the recessing process of the dielectric material80may also recess the ILD74, such that the top surface of the ILD74is below the top surfaces of the dummy gates64. In some embodiments, the ILD74is recessed below the top surfaces of the dummy gates64to a depth D9. In some embodiments, the depth D9is between about 15 nm and about 30 nm. In some embodiments, the recessing process also removes portions of the dummy gates64, the gate seal spacers66, the gate spacers68, and the ESL72. In such embodiments, after performing the recessing process, the dummy gates64have top surfaces, which are disposed above the fins52at a height H3as measured from the top surfaces of the fins52. In some embodiments, the height H3is less than the height H2(seeFIG.19B). In some embodiments, the height H3is between about 70 nm and about 75 nm. InFIGS.21A and21B, a dielectric material84is deposited in the trench78(seeFIG.20B), and over the ILD74and the dummy gates64. In some embodiments, the dielectric material84comprises an oxide material (such as silicon oxide, or the like), a nitride material (such as silicon nitride, or the like), an oxynitride material (such as silicon oxynitride, or the like), a combination thereof, or the like, and may be formed using ALD, CVD, a combination thereof, or the like. In some embodiments, the dielectric material80and the dielectric material84comprise different materials. In other embodiments, the dielectric material80and the dielectric material84comprise a same material. In some embodiments, by reducing the aspect ratio of the unfilled portion of the trench78as described above with reference toFIGS.20A and20B, formation of a seam or void within the trench78may be reduced. In some embodiments, by reducing the aspect ratio (D8/W3) of the unfilled portion of the trench78to be between about 9 and about 12, a seam86may be formed in the dielectric material84within the trench78(seeFIGS.20B), such that the seam86does not extend below the top surfaces of the fins52. In some embodiments, a bottommost portion of the seam86is disposed above the fins52at a height H4as measured from the top surfaces of the fins52. In some embodiments, the height H4is between about 20 nm and about 35 nm. In some embodiments, a planarization process is performed on the dielectric material84. The planarization process may comprise a CMP process, an etch back process, a combination thereof, or the like. The planarization process exposes the dummy gates64such that top surfaces of the dummy gates64and the top surface of the dielectric material84are substantially level (within process variations) after the planarization process is completed. Portions of the dielectric materials80and84disposed within the trench78(seeFIG.20B) may be also referred to as an isolation structure. In some embodiments, the planarization process also removes portions of the dummy gates64, the gate seal spacers66, the gate spacers68, and the ESL72. In such embodiments, after performing the planarization process, the dummy gates64have top surfaces, which are disposed above the fins52at a height H5as measured from the top surfaces of the fins52. In some embodiments, the height H5is less than the height H3(seeFIG.20B). In some embodiments, the height H5is between about 50 nm and about 65 nm. InFIGS.22A and22B, the dummy gates64and corresponding dummy dielectric layers60(seeFIGS.21A and21B) are removed in one or more etching steps, so that openings88are formed. In some embodiments, the dummy gates64are removed by a suitable etching process. For example, the etching process may include a dry etch process using reaction gas(es) that selectively etch the dummy gates64without etching the ILD74or the gate spacers68. The etching process may be anisotropic. Each opening88exposes channel regions58of respective fins52. Each channel region58is disposed between neighboring pairs of the epitaxial source/drain regions70. During the removal, the dummy dielectric layers60may be used as an etch stop layer when the dummy gates64are etched. Subsequently, the dummy dielectric layers60are removed by a suitable etching process. In some embodiments, the processes for removing the dummy gates64and the dummy dielectric layers60may also remove portions of the dielectric material84, the gate seal spacers66, the gate spacers68, and the ESL72. In such embodiments, a thickness of the dielectric material84over the ILD74is reduced, such that a top surface of the dielectric material84is disposed above the fins52at a height H6as measured from the top surfaces of the fins52. In some embodiments, the height H6is less than the height H5(seeFIG.21B). In some embodiments, the height H6is between about 50 nm and about 60 nm. InFIGS.23A and23B, interfacial layers90, gate dielectric layers92and gate electrodes94are formed in the openings88(seeFIGS.22A and22B) to form replacement gate stacks96.FIG.23Cillustrates a detailed view of a region98ofFIG.23B. In some embodiments, the interfacial layers90are formed in the openings88(seeFIGS.22A and22B). The interfacial layers90may comprise silicon oxide and may be formed using a chemical deposition process, such as ALD, CVD, PECVD, or the like, or using an oxidation process. In some embodiments where the interfacial layers90are formed using a deposition process, the interfacial layers90extend along exposed surfaces of the fins52, the STI regions56, and the gate seal spacers66. In some embodiments where the interfacial layers90are formed using an oxidation process, the interfacial layers90extend along exposed surfaces of the fins52, and do not extend along exposed surfaces of the STI regions56and the gate seal spacers66. In some embodiments, the gate dielectric layers92are deposited over the interfacial layers90in the openings88(seeFIGS.22A and22B). In some embodiments, the gate dielectric layers92may comprise silicon oxide, silicon nitride, or multilayers thereof, or the like. In some embodiments, the gate dielectric layers92may include a high-k dielectric material, and in these embodiments, the gate dielectric layers92may have a k value greater than about 7.0, and may include a metal oxide or a silicate of hafnium, aluminum, zirconium, lanthanum, manganese, barium, titanium, lead, and combinations thereof, or the like. The gate dielectric layers92may be formed using ALD, CVD, or the like. Further inFIGS.23A and23B, the gate electrodes94are deposited over the gate dielectric layers92and fill the remaining portions of the openings88(seeFIGS.22A and22B). Although single layer gate electrodes94are illustrated inFIG.23B, each of the gate electrodes94may comprise any number of liner layers94A, any number of work function tuning layers94B, and a conductive fill layer94C as illustrated byFIG.23C. The liner layers94A may include TiN, TiO, TaN, TaC, combinations thereof, multi-layers thereof, or the like, and may be formed using PVD, CVD, ALD, a combination thereof, or the like. In the n-type region of the substrate50, the work function tuning layers94B may include Ti, Ag, Al, TiAl, TiAlN, TiAlC, TaC, TaCN, TaSiN, TaAlC, Mn, Zr, combinations thereof, multi-layers thereof, or the like, and may be formed using PVD, CVD, ALD, a combination thereof, or the like. In the p-type region of the substrate50, the work function tuning layers94B may include TiN, WN, TaN, Ru, Co, combinations thereof, multi-layers thereof, or the like, and may be formed using PVD, CVD, ALD, a combination thereof, or the like. In some embodiments, the conductive fill layer94C may comprise Co, Ru, Al, Ag, Au, W, Ni, Ti, Cu, Mn, Pd, Re, Ir, Pt, Zr, alloys thereof, combinations thereof, multi-layers thereof, or the like, and may be formed using PVD, CVD, ALD, a combination thereof, or the like. After the filling of the openings88(seeFIGS.22A and22B), a planarization process, such as a CMP process, may be performed to remove the excess portions of the gate dielectric layers92, the gate electrodes94, and/or the interfacial layers90, which excess portions are over the top surface of the dielectric material84. The remaining portions of the gate electrodes94, the gate dielectric layers92, and the interfacial layers90thus form replacement gate stacks96of the resulting FinFETs. The gate stacks96may extend along sidewalls of the channel regions58of the fins52. In some embodiments, the planarization process may also remove portions of the dielectric material84, the gate seal spacers66, the gate spacers68, and the ESL72. In such embodiments, after performing the planarization process, the gate stacks96have top surfaces, which are disposed above the fins52at a height H7as measured from the top surfaces of the fins52. In some embodiments, the height H7is less than the height H6(seeFIG.22B). In some embodiments, the height H7is between about 40 nm and about 50 nm. The formation of the gate dielectric layers92in the n-type region and the p-type region of the substrate50may occur simultaneously such that the gate dielectric layers92in each region are formed of the same materials. In other embodiments, the gate dielectric layers92in each region may be formed by distinct processes such that the gate dielectric layers92in different regions may be formed of different materials. The formation of the conductive fill layers94C in the n-type region and the p-type region of the substrate50may occur simultaneously such that the conductive fill layers94C in each region are formed of the same materials. In other embodiments, the conductive fill layers94C in each region may be formed by distinct processes such that the conductive fill layers94C in different regions may be formed of different materials. Various masking steps may be used to mask and expose appropriate regions when using distinct processes. InFIGS.24A and24B, the gate stacks96are recessed, so that recesses100are formed directly over the gate stacks96and between opposing portions of the gate seal spacers66. In some embodiments, the recessing process comprises a suitable etching process that selectively etches the materials of the gate stacks96without significantly etching the gate seal spacers66. The suitable etching process may include a dry etch process, a wet etch process, a combination thereof, or the like. In some embodiments, the etching process for recessing the gate stacks96is performed using etchants such as CF4, CHF3, HBr, N2, H2, O2, a combination thereof, or the like. In other embodiments, the etching process for recessing the gate stacks96is performed using etchants such as deionized (DI) water with dissolved ozone (DIO3), H2SO4, NH4OH, a combination thereof, or the like. In some embodiments, after performing the recessing process, the gate stacks96have top surfaces, which are disposed above the fins52at a height H8as measured from the top surfaces of the fins52. In some embodiments, the height H8is less than the height H4(seeFIG.21B). In some embodiments, the height H8is between about 10 nm and about 20 nm. In some embodiments, the recessing process may also remove portions of the dielectric material84, the gate seal spacers66, the gate spacers68, and the ESL72. In such embodiments, a thickness of the dielectric material84over the ILD74is further reduced, such that a top surface of the dielectric material84is disposed above the fins52at a height H9as measured from the top surfaces of the fins52. In some embodiments, the height H9is less than the height H7(seeFIG.23B). In some embodiments, the height H9is between about 30 nm and about 40 nm. InFIGS.25A and25B, gate masks102comprising one or more layers of a dielectric material, such as silicon nitride, silicon oxynitride, a combination thereof, or the like, are filled in the recesses100(seeFIGS.24A and24B), followed by a planarization process to remove excess portions of the dielectric material extending over the ILD74. The planarization process may comprise a CMP process, an etching process, a combination thereof, or the like. In some embodiments, seams104may be formed in the gate masks102within the recesses100(seeFIGS.24A and24B). In some embodiments, the planarization process may also remove portions of the ILD74, the gate seal spacer66, the gate spacer68, and ESL72. In such embodiments, after performing the planarization process, the gate masks102have top surfaces, which are disposed above the fins52at a height H10as measured from the top surfaces of the fins52. In some embodiments, the height H10is less than the height H9(seeFIG.24B). In some embodiments, the height H10is between about 25 nm and about 35 nm. InFIGS.26A and26B, the ILD74and the ESL72(seeFIGS.25A and25B) are patterned to form openings106exposing the epitaxial source/drain regions70. The patterning process exposes the epitaxial source/drain regions70and the gate spacers68. In some embodiments, the patterning process comprises one or more suitable etching processes that selectively etch the materials of the ILD74and the ESL72. The suitable etching processes may include a dry etching process, a wet etching process, a combination thereof, or the like. In some embodiments, the patterning process comprises a first etching process for patterning the ILD74, followed by a second etching process for patterning the ESL72. In some embodiments, the first etching process is performed using etchants such as C4F6, C4F8, O2, CO, a combination thereof, or the like. In some embodiments, the second etching process is performed using etchants such as HF, NH3, NF3, a combination thereof, or the like. InFIGS.27A and27B, silicide layers108are formed over the epitaxial source/drain regions70through the openings106. In some embodiments, a metallic material is deposited over the epitaxial source/drain regions70. The metallic material may comprise Ti, Co, Ni, NiCo, Pt, NiPt, Ir, Ptlr, Er, Yb, Pd, Rh, Nb, a combination thereof, or the like, and may be formed using PVD, ALD, CVD, a combination thereof, or the like. Subsequently, an annealing process is performed to form the silicide layers108. In some embodiments where the epitaxial source/drain regions70comprise silicon, the annealing process causes the metallic material to react with silicon to form a silicide of the metallic material at interfaces between the metallic material and the epitaxial source/drain regions70. After forming the silicide layers108, unreacted portions of the metallic material are removed using a suitable removal process, such as a suitable etch process, for example. InFIGS.28A and28B, source/drain contacts114are formed in the openings106(seeFIGS.27A and27B). In some embodiments, the source/drain contacts114are formed by forming a liner110and a conductive material112in the openings106. The liner110may be a diffusion barrier layer, an adhesion layer, or the like. The liner110may include titanium, titanium nitride, tantalum, tantalum nitride, a combination thereof, or the like, and may be formed using PVD, sputtering, plating, a combination thereof, or the like. The conductive material112may include copper, a copper alloy, silver, gold, tungsten, cobalt, aluminum, nickel, a combination thereof, or the like, and may be formed using PVD, CVD, sputtering, plating, a combination thereof, or the like. In some embodiments, portions of the liner110and the conductive material112may penetrate into the seam86(seeFIG.27B). However, since the seam86does not extend below the top surfaces of the fins52, an amount of the penetrated material is reduced. In some embodiments, a planarization process, such as a CMP process, may be performed to remove excess portions of the liner110and the conductive material112and expose top surfaces of gate masks102. The remaining portions of the liner110and the conductive material112form the source/drain contacts114. The source/drain contacts114are electrically coupled to the respective epitaxial source/drain regions70through the silicide layers108. In some embodiments, top surfaces of the gate masks102and top surfaces of the source/drain contacts114are substantially level or coplanar (within process variations) after the planarization process is completed. In some embodiments, the planarization process also removes portions of the gate masks102, the gate seal spacers66, the gate spacers68, and the dielectric material84, such that the seam86(seeFIG.27B) in the dielectric material84is completely removed. In some embodiments, by removing the seam86(seeFIG.27B), portions of the conductive material that may have penetrated in the seam86during the formation of the source/drain contacts114are also removed. Accordingly, shorting of the source/drain contacts114disposed on opposite sides of the dielectric material84is avoided. In some embodiments, after performing the planarization process, the gate masks102have top surfaces, which are disposed above the fins52at a height H11as measured from the top surfaces of the fins52. In some embodiments, the height H11is less than the height H10(seeFIG.25B). In some embodiments, the height H11is less than or equal to the height H4(seeFIG.21B). In some embodiments, the height H11is between about 20 nm and about 30 nm. InFIGS.29A and29B, after performing the planarization process, an ILD116is deposited over the gate stacks96and the source/drain contacts114. In some embodiments, the ILD116may be formed using similar materials and methods as the ILD74described above with reference toFIGS.11A and11B, and the description is not repeated herein. In some embodiments, the ILD74and the ILD116comprise a same material. In other embodiments, the ILD74and the ILD116comprise different materials. After forming the ILD116, openings for the gate contacts118are formed through the ILD116and the gate masks102. The openings may be formed using acceptable photolithography and etching techniques. Subsequently, the gate contacts118are formed in the openings. In some embodiments, the gate contacts118are formed using similar materials and method as the source/drain contacts114described above with reference toFIGS.28A and28B, and the description is not repeated herein. Embodiments may achieve advantages. Various embodiments discussed herein allow for improving a dielectric material gap-fill performance for a trench formed during a fin cut process, reducing or avoiding issues due to a seam and/or void formation in the dielectric material within the trench, reducing or avoiding shorting between contact plugs, and improving device and yield performance. In some embodiments, the trench formed during the fin cut process is filled with a plurality of dielectric materials. In some embodiments, the trench filling process may include filling the trench with a first dielectric material, partially removing the first dielectric material from the trench such that an upper portion of the trench is not filled with a dielectric material, and filling the upper portion of the trench with a second dielectric material. The second dielectric material may be same or different from the first dielectric material. In accordance with an embodiment, a device includes a substrate, a first isolation structure and a second isolation structure over the substrate, a semiconductor fin over the substrate and between the first isolation structure and the second isolation structure, and a third isolation structure extending through the semiconductor fin and between the first isolation structure and the second isolation structure. A top surface of the semiconductor fin is above a top surface of the first isolation structure and a top surface of the second isolation structure. The third isolation structure includes a first dielectric material and a second dielectric material over the first dielectric material. An interface between the first dielectric material and the second dielectric material is below the top surface of the first isolation structure and the top surface of the second isolation structure. In an embodiment, the first dielectric material extends below a bottom surface of the first isolation structure and a bottom surface of the second isolation structure. In an embodiment, the second dielectric material extends along and is in physical contact with the top surface and sidewalls of the first isolation structure. In an embodiment, a top surface of the third isolation structure is above the top surface of the first isolation structure and the top surface of the second isolation structure. In an embodiment, a top surface of the third isolation structure is above the top surface of the semiconductor fin. In an embodiment, the device further includes a gate stack over the semiconductor fin and adjacent to the third isolation structure, a top surface of the gate stack being below a top surface of the third isolation structure. In an embodiment, the first dielectric material is different from the second dielectric material. In accordance with another embodiment, a device includes a substrate, a semiconductor fin extending from a top surface of the substrate, a gate stack extending along a top surface and sidewalls of the semiconductor fin, a source/drain region extending into the semiconductor fin adjacent to the gate stack, and an isolation structure extending into the semiconductor fin adjacent to the source/drain region. The source/drain region is interposed between the isolation structure and the gate stack. The isolation structure includes a first dielectric material and a second dielectric material over the first dielectric material. An interface between the first dielectric material and the second dielectric material is below the top surface of the semiconductor fin. In an embodiment, the first dielectric material is different from the second dielectric material. In an embodiment, the first dielectric material extends into the substrate. In an embodiment, the interface between the first dielectric material and the second dielectric material is above the top surface of the substrate. In an embodiment, a top surface of the second dielectric material is above a top surface of the gate stack. In an embodiment, the interface between the first dielectric material and the second dielectric material is below a bottom surface of the source/drain region. In an embodiment, the device further includes a spacer structure extending along a sidewall of the isolation structure, where the spacer structure is in physical contact with the second dielectric material. In accordance with yet another embodiment, a method includes forming a semiconductor fin over a substrate. A dummy gate structure is formed over the semiconductor fin. Spacers are formed on opposite sidewalls of the dummy gate structure. The dummy gate structure is removed to form a trench between the spacers. The trench exposes the semiconductor fin. An etching process is performed on the semiconductor fin to extend the trench into the semiconductor fin. The trench is filled with a first dielectric material. The first dielectric material is etched back. A second dielectric material is deposited in the trench and over the first dielectric material. In an embodiment, the etching process further extends the trench into the substrate. In an embodiment, a top surface of the first dielectric material is below a top surface of the semiconductor fin after etching back the first dielectric material. In an embodiment, the first dielectric material is different from the second dielectric material. In an embodiment, the second dielectric material has a seam within the trench. In an embodiment, the seam is removed. The foregoing outlines features of several embodiments so that those skilled in the art may better understand the aspects of the present disclosure. Those skilled in the art should appreciate that they may readily use the present disclosure as a basis for designing or modifying other processes and structures for carrying out the same purposes and/or achieving the same advantages of the embodiments introduced herein. Those skilled in the art should also realize that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and that they may make various changes, substitutions, and alterations herein without departing from the spirit and scope of the present disclosure. | 63,367 |
11862509 | DETAILED DESCRIPTION OF THE EMBODIMENTS In embodiments, shallow trench isolation (STI) structures with a width, typically referred to as a critical dimension (CD) and a target depth (TD) may be formed in a wafer substrate. STI formation in the wafer substrate is typically performed prior to fabrication of photodiodes, transistors and other devices in the substrate. The CD of STI structures significantly impacts the density of pixels on the wafer substrate and therefore, the performance of the image sensor.FIGS.4A-4Cdepict several stages in the formation of an STI structure having a width W corresponding to CD and a depth D corresponding to TD, according to embodiments. The cross-sectional schematics ofFIGS.4A-4Care each parallel to a plane, hereinafter the x-z plane, formed by orthogonal directions498X and498Z, which are each orthogonal to direction498Y.FIGS.4A-4Care best viewed together in the following description. Prior to STI structure fabrication, semiconductor substrate402may be coated with a pad oxide layer404, a pad nitride layer406and photoresist layer408sequentially deposited. In embodiments, an N-/P type P-Well implant (not shown) may be fabricated in semiconductor substrate402. In an embodiment, semiconductor substrate402is formed from silicon, although other semiconductor materials may be used, for example, bulk silicon substrate doped with n-type or p-type dopants, silicon on insulation (SOI) substrate, silicon germanium, and the like. As patterned using a lithography process with photoresist layer408, trench410is etched into semiconductor substrate402through pad nitride layer406and pad oxide layer404to a depth D1in semiconductor substrate402. In an embodiment, depth D1refers to the depth or distance into the semiconductor substrate402from planar surface412of semiconductor substrate402. Planar surface412may be a front side surface of semiconductor substrate402or a substrate top surface of semiconductor substrate402, for brevity, planar surface412or surface412will be used interchangeably hereinafter. Planar surface412is parallel to the x-y plane formed by498X and498Y, and perpendicular to direction498Z and depths described herein in relation to direction498Z. In an embodiment, etching is performed using a dry plasma etch to remove a portion of substrate material to create a trench410having depth D1ranging from approximately 10 nm to 60 nm and a width W approximately equal to the preferred STI structure CD. In embodiments, width W may range from approximately 0.1 μm to 0.2 μm. A larger CD is also contemplated. In embodiments, isotropic dry etching parameters depend on the material of semiconductor substrate402and include pressure, gas composition (e.g., oxygen O2, fluorine, SF6, CF4, CHF3, C4F8), gas generation or injection method, and generator power. After the dry etch process, photoresist layer408is removed, for example by a strip and clean process. Plasma etching damages the walls of trench410leaving dangling bonds, or trap sites that contribute to dark current noise affecting image quality. To remove plasma-induced damage, the dry plasma etching process forming the trench410having depth D1is followed by a wet etch process, as shown inFIG.4B. A wet etching process does not use the high energy ion bombardment as does the dry etch process. In embodiments, a wet etch process using KOH/IPA (potassium hydroxide/isopropyl alcohol) is performed. Parameters of etchant concentration, temperature and time are chosen to perform an etching process until trench410reaches a depth Das measured from planar surface412of semiconductor substrate402. In an embodiment, D ranges from approximately 120 nm to approximately 150 nm. In embodiments, trench410has a trench profile with a polygonal shaped cross-section in the plane formed by orthogonal directions498X and498Z. For example, trench410may have a trench profile that is generally hexagonal-shaped. In embodiments, sidewalls414of trench410are symmetrical with respect to the vertical central line411of trench410. For clarity of illustration, vertical central line is only shown inFIG.4A. In an embodiment, semiconductor substrate402is formed of crystalline silicon that has a surface orientation of <100>. The anisotropic etching characteristics of silicon result in the polygonal shaped cross-section ofFIG.4Bwith smoother sidewall and bottom surfaces. In embodiments, etching parameters are selected so sidewalls414of trench410form an angle of approximately 54 degrees with bottom416of trench410and a preferred depth of D is reached. In embodiments, the bottom416of trench410has a surface orientation of <100> and sidewalls414have a surface orientation of <111>. The wet etching process results in a trench with a width W at planar surface412, widening to a width W1at depth D1then narrowing to width W2at depth D. In embodiments, W1is determined by depth difference between depth D and D1(D−D1) based on etching parameter (e.g. etching angle at 54° degrees) and bottom width W2(which is approximately 40 nm). A wet etch process has very good selectivity to create trench410with a polygonal, or diamond shaped cross section. A wet etch alone may not be successful if, for example, there is some residue (e.g., oxide material) on surface412of semiconductor substrate402. This residue may result in a cavity that is not opened properly, a premature end to the etch process or residue material inside the cavity, for example. Opening the trench410with a dry etch process removes residue material before the wet etch process is performed. After etching, trench410may be subjected to surface treatment processes to remove some Si defects and reduce humidity at the trench surface, for example, Siconi™ and hydrogen bake. Siconi™ is a soft dry chemical etching process (e.g. plasma) that may selectively remove oxidized silicon surface defects by exposing the region to be etched to etching agents such as H2, HF3and NH3. Hydrogen bake is the subsequent surface clearing process used to remove oxide present on the silicon interface. These processes, however, do not remove all Si dangling bonds created by etching. FIG.4Cis a cross-sectional view of an STI structure418after subsequent processing steps. Trench410is filled with a dielectric material420such as oxide material using, for example, a high aspect ratio process (HARP) to deposit dielectric material into trench410, although other processes, such as chemical vapor deposition process may be used. In embodiments, dielectric material420is the same material as pad oxide layer404. In embodiments, pad nitride layer406is subsequently removed by, for example, a chemical mechanical polishing (CMP) process although other processes may be used. The deposition process may create a small protrusion428of dielectric material above trench410and above planar surface412. Protrusion428may protect STI structure418from over etching during a subsequent CMP process. In embodiments, protrusion428prevents exposure of corner320of STI structure418minimizes time-dependent dielectric breakdown (TDDB) failure and improves reliability of a device (e.g., an image sensor device) incorporating STI structure418. In embodiments, STI structure418is disposed in a P-type doped well region422. In embodiments, P-type doped well region422is an ion-implanted well region of P-type in the semiconductor substrate402or a P-type doped epitaxial layer grown on semiconductor substrate402. STI structure418and P-type doped well region422provide electrical isolation between adjacent photodiode region and pixel transistor region. In embodiments, the P-type doped well region422has at least one device or pixel transistor e.g., source follower, reset transistor, row-select transistor formed therein. In embodiments, STI structure418is further passivated by implantation forming a doped region424having opposite conductive type (e.g., boron-doped region) to photodiode region (not shown) to passivate sidewalls414of STI structure418and provide isolation between nearby photodiodes(not shown) and source/drains of device or pixel transistors. Doped region424surrounding STI structure418may be conformally formed along sidewalls and bottom surface of414. Restated, doped region424may be implanted to surround the STI structure418. In embodiments, the concentration of doped region424may be higher than the P-type doped well region422for example by at least one order of magnitude. In embodiments, the concentration of doped region424is higher than the semiconductor substrate402, for example by at least one order of magnitude. In embodiments, a surface pinning region426is formed between substrate top surface412of semiconductor substrate402and photodiode region (not shown) to passivate surface defects and reduce dark current. In embodiments, P-type doped well region422, the doped region, surface pinning region426are coupled to a ground. FIG.5shows a plan view of adjacent photodiode regions502in a pixel cell500.FIG.6Ais a cross-sectional view along line6A-6A ofFIG.5.FIG.6Bis a cross-sectional view along line6B-6B ofFIG.5.FIG.6Cis a cross-sectional view along line6C-6C ofFIG.5.FIGS.5and6A-6Care best viewed together in the following description. The plan view ofFIG.5is in the plane formed by orthogonal directions498X and498Y, which are each orthogonal to direction498Z. InFIG.5, photodiodes504, transfer transistors506and floating diffusion nodes508are formed in photodiode regions502(also referred to as active regions or photo-sensing regions) of a wafer substrate (or a semiconductor substrate). Photodiodes504and floating diffusion nodes508are doped regions having a first conductive type, e.g. N-type in the wafer substrate, and the wafer substrate is configured to have a second conductive type e.g., P-type, opposite to the first conductive type. In embodiments, transfer transistors506couple their respective photodiode504to the respective floating diffusion node508, and selectively transfer photo-generated charges from respective photodiode504to floating diffusion node508in response to a transfer signal received at respective transfer gate506. Each of photodiodes504functions as a source region to the respective transfer transistor506, and each of floating diffusion nodes508functions as a drain region to respective transfer transistor506. Although not illustrated, in embodiments, floating diffusion nodes508are coupled to reset transistor510and source-follower transistor512through metal contacts and metal interconnects the source-follower transistor512is coupled to the row select transistor514. The row select transistor514is coupled to a bitline (not shown) through metal contacts and metal interconnects. In embodiments, reset transistor510, source-follower transistor512and row select transistor514are N-channel transistors formed in pixel transistor region516of the wafer substrate. Pixel transistor region516is in between the adjacent pixel cells. In this example, source and drain regions of the reset transistor510, source-follower transistor512and row select transistor514are N-type doped regions i.e. doped regions of the first conductive type opposite to the second conductive type of the wafer substrate. Photodiodes504in photodiode regions502are electrically isolated from pixel transistor region516by STI structures518A,518B, respectively in the wafer substrate. STI structures518A and518B may be understood as corresponding to STI structure418as shown inFIG.4C. In embodiments, reset transistor510, source-follower transistor512and row select transistor514are associated with one of the photodiode regions502. For simplicity, two photodiodes per unit pixel are illustrated inFIG.5. In other embodiments, a pixel may include more or fewer photodiodes. Similarly, the illustrated pixel layout demonstrates a “four-transistor configuration,” that is, the pixel transistors for each respective pixel include a transfer transistor, reset transistor, source follower transistor, and row select transistor. In some embodiments, a pixel may be configured to a “three-transistor configuration” and include only a transfer transistor, a reset transistor, and a source follower transistor. In some embodiments, a pixel may be configured to a “five transistor configuration” and include a transfer transistor, a row select transistor, a source follower transistor, a reset transistor (and an overflow transistor or a dual floating diffusion (DFD) transistor. Thus, number of photodiodes in a pixel and the number of pixel transistors used for controlling operation of the pixel may depend on configuration of the respect pixel. FIGS.6A-6Care cross-sectional views along three sections of pixel cell500ofFIG.5. The schematics ofFIGS.6A-6Bare each parallel to a plane, hereinafter the x-z plane, formed by orthogonal directions498X and498Z, which are each orthogonal to direction498Y. The schematic ofFIG.6Cis parallel to a plane, hereinafter the y-z plane, formed by directions498Y and498Z.FIGS.6A-6Care best viewed together in the following description. FIG.6Ais a cross-sectional view along line6A-6A ofFIG.5across source-follower transistor512. A similar cross-section would be found across reset transistor510, or row select transistor514. Source-follower transistor512in pixel transistor region516is isolated from photodiodes504in photodiode regions502by STI structures518A and518B. Gate oxide layer524separates gate530of source-follower transistor512from source/drain522, formed in well region520in a semiconductor substrate532(e.g., silicon substrate or bulk substrate). In embodiments, at least a part of gate530of source-follower transistor512is disposed on the STI structures518A and STI structure518B, that is gate530of the source-follower transistor512partially overlaps STI structures518A,518B. In embodiments, the shape of the part of gate530that overlaps STI structure518A and STI structure518B is conformal to the shape or profile of dielectric material protrusion of STI structures518A and518B as illustrated inFIG.6A. Well region520is formed by implantation of second conductivity type (e.g., p-type) impurities into substrate while source/drain522is formed by implantation of first conductivity type (e.g., n-type) impurities. Doped region526may provide additional passivation and isolation between STI structure518A,518B and nearby photodiodes504, as well as between source/drains522of pixel transistors (e.g., reset transistor, source-follower or row-select transistor) in pixel transistor region516. In embodiments, doped region526is implanted with Boron ions. In embodiments, each photodiode504is an n-type region and includes a P-type pinning region528between substrate532surface412and photodiode504. P-type pinning region528passivates planar surface412defects and gives better isolation between substrate surface and a respective photodiode504, thereby reducing dark current. In embodiments, each of STI structures518A and518B have a polygonal shaped cross-section, for example a diamond shaped cross-section, along direction498X. First vertices of the polygonal shaped cross-section are at a depth D1with respect to surface412of semiconductor substrate532. Depth D1is approximately 10-60 nm corresponding to the first step of dry etching. STI structures518A and518B have an overall depth D from surface412of semiconductor substrate532of approximately 120-150 nm corresponding to the second step of wet etching. In embodiments, depth D of each of STI structures518A and518B is greater than a junction depth of source/drain522of associated pixel transistor (e.g., source-follower transistor512). In embodiments, the junction depth of source/drain522of associated pixel transistor may be 70-80 nm. The polygonal shaped cross-section also has the effect of varying the spacing between STI structures518A and518B along their depth. Proximate to planar surface412of semiconductor substrate532, the spacing between STI structure518A is width W3(first separation width). At depth D1, the spacing narrows or decreases to width W4(second separation width). At depth D from planar surface412, the spacing between STI structures518A and518B widens or increases to width W5(third separation width). In embodiments, width W5(third separation width) is greater than width W3(first separation width), and width W3(first separation width) is greater than width W4(second separation width). FIG.6Bis a cross-sectional view along line6B-6B ofFIG.5. AlthoughFIG.6Bdepicts a cross-sectional view between transistors between512and514, a similar cross-section would be found in similar areas of pixel transistor region516. Each of STI structure518A and518B has the same diamond shaped cross section at the same depths D1and D. Source/drain522of associated pixel transistor (e.g., source-follower transistor512) extends along the length of pixel transistor region516in the direction498Y. FIG.6Cis a cross-sectional view along line6C-6C ofFIG.5. As shown inFIG.6C, each of STI structures518A and518B also has an extended polygonal shaped cross-section, for example a diamond shaped profile, along direction498Y, providing effective electrical isolation between photodiodes in photodiode region and pixel transistors in pixel transistor region. In embodiments, the length of STI structure518in direction498Y is at least the same as the length of photodiode region502in direction498Y. FIG.7is a flowchart illustrating a method700for fabricating an STI structure in a semiconductor or wafer substrate of an image sensor. Method700includes steps706,708and710. In embodiments, method700also includes at least one of steps702,704,712and714. Step702includes forming a plurality of photodiodes and well implant regions in a semiconductor substrate. Photodiodes and well implant regions are implanted into a front surface of the semiconductor substrate by patterning and ion implantation. Photodiodes and well regions have opposite conductive type. In an example of step702, photodiodes are formed by implanting N-type dopants e.g., phosphorus or arsenic, into the semiconductor substrate402of P-type from planar surface412of the semiconductor substrate402forming N-type diffusion regions of photodiodes. Well regions are formed by implantation P-type dopants e.g., boron, into the semiconductor substrate402from planar surface412of the semiconductor substrate402. In another example, photodiodes are doped regions formed by implanting P-type dopants e.g., boron, into the semiconductor substrate402of N-type from planar surface412of the semiconductor substrate402forming P-type diffusion regions of photodiodes and well regions are formed by implantation N-type dopants e.g., phosphorus or arsenic, into the semiconductor substrate402from planar surface412of the semiconductor substrate. In some embodiments, well implant regions may be formed before the formation of photodiodes. Step704includes lithography patterning onto the semiconductor substrate with regions for one or more shallow trench isolation structures. In an example of step704, region of one or more STI structures are patterned onto semiconductor substrate402using a photoresist layer408with a lithography process. Step706includes a dry plasma etch to form a trench having a first trench profile at a first depth. In an example of step706, photoresist layer408defines areas in semiconductor substrate402for a dry plasma etch through pad nitride layer406, pad oxide layer404and into semiconductor substrate402to form trench410with a depth of approximately 50 nm, although the depth may range from approximately 10-60 nm. Step706defines a trench width W (first trench width) at planar surface412of semiconductor substrate402and a depth D1in semiconductor substrate402with respect to the planar surface412and provides an etching path to the trench in the semiconductor substrate preventing surface material residue forming a blockage and affecting overall etching performance. Step708includes a wet etch to etching through the trench (first trench) to a depth D with a second trench having width W1(second trench width) at depth D1and a width W2(third trench width) at depth D, where depth D is greater than depth D1with respect to planar surface412. In an example of step708, a silicon wet etch with KOH/IPA (potassium hydroxide/isopropyl alcohol) is performed until trench410reaches a depth D of approximately 120-150 nm. Depth D can be controlled exactly and constantly according to the length of time and other parameters of the wet etch. In an example, the wet etch process forms a diamond shaped trench profile wherein trench410has a base width W2of approximately 40 nm. Using a wet etching (anisotropic etching) process after the dry etching (e.g., plasma etching) process to form trench for STI structure can remove etching damage caused by initial dry etching of step706, and yield a trench for STI structures such as STI structures518A,518B with smoother sidewall surfaces, thus greatly reducing the number of trap sites at the interface between the sidewalls of the STI structure518A,518B and the semiconductor substrate, therefore minimizing the dark current issue associated with STI structure216as shown inFIG.2B. Step710includes filling the etched STI trench structure with a dielectric material. In an example of step710, trench410is filled with an oxide material using a high aspect ratio process (HARP), although other processes may be used. Step712includes ion implantation around STI structures. In an example of step712, boron ions are implanted in doped region424surrounding sidewalls of STI structure418to enhance the isolation capabilities of STI structure418as shown inFIG.4C. In another example of step712, boron ions are implanted in doped region526surrounding sidewalls of STI structures518A,518B to enhance the isolation capabilities of STI structure518A,518B between photodiodes and source/drain regions of pixel transistors as shown inFIG.6A. Step714includes chemical mechanical polishing (CMP) and forming transistors to complete pixels. In an example of step714, pad nitride layer406is removed using CMP and with subsequent processes e.g., gate formation and source/drain, floating diffusion implantation, additional structures of an image sensor are formed as shown inFIG.5. Combinations of Features Features described above as well as those claimed below may be combined in various ways without departing from the scope hereof. The following enumerated examples illustrate some possible, non-limiting combinations: (A1) A shallow trench isolation (STI) structure formed in a semiconductor substrate having a front-side surface, the STI structure having a first width W in the same plane as the front-side surface and a first depth D perpendicular to the front-side surface, to provide isolation between a photodiode region comprising a photodiode and a pixel transistor region comprising at least one transistor, the STI structure includes a trench formed in the front-side surface such that the trench extends into the semiconductor substrate to the first depth D relative to the front-side surface, said trench comprising sloped walls and a polygonal shaped cross-section between the photodiode region and the pixel transistor region, wherein a width of the trench varies along the depth of the trench from a first width W to a second width W1larger than first width W at a second depth D1then to a third width W2smaller than the first width W at the first depth D; wherein the first depth D is greater than the second depth D1with respect to the front-side surface; and a dielectric material filing the trench.(A2) In STI structure (A1), the first depth D is approximately 120-150 nm.(A3) In STI structure (A1) or (A2), the second depth D1is approximately 10-60 nm.(A4) In any of STI structures (A1)-(A3), the polygonal shaped cross section of the trench between the photodiode region and the pixel transistor region is diamond shaped.(A5) In any of STI structures (A1)-(A4), the trench has an extended polygonal shaped cross-section parallel to a length direction of photodiode region.(A6) In any of STI structures (A1)-(A5), further including a boron-doped area in said semiconductor substrate surrounding said STI structure.(B1) A method of forming a shallow trench isolation (STI) structure in a semiconductor substrate having a front-side surface and a first depth D extending from the front-side surface, the STI structure formed between a photodiode region and a pixel transistor region, defined in the semiconductor substrate, the method includes dry etching a trench to a second depth D1in the semiconductor substrate with respect to the front-side surface, the trench having a first width W at the front-side surface of the semiconductor substrate; wet etching through the trench to have sloped walls and a polygonal shaped cross-section between the photodiode region and the pixel transistor region, the polygonal shaped cross-section of the trench comprising the first width W at the front-side surface, a second width W1at the second depth D1and a third width W2at the first depth D wherein W1>W>W2and wherein D>D1; and filling the etched trench with a dielectric material.(B2) In the method of (B1), dry includes forming an oxide layer on the semiconductor substrate; forming a nitride layer on the semiconductor substrate; depositing a photoresist layer on the nitride layer that is patterned with the trench to be etched with a lithography process; and dry etching the trench into the semiconductor substrate through the nitride layer and the oxide layer to the second depth D1.(B3) In the method of (B1) or (B2), wet etching further comprises a wet etch using KOH/IPA (potassium hydroxide/isopropyl alcohol) for a period of time until the trench reaches the first depth D.(B4) In any of methods (B1)-(B3), the dielectric material is an oxide material.(B5) In any of methods (B1)-(B4), wet etching through the trench includes etching through the trench to have sloped walls and a polygonal shaped cross-section that is diamond shaped between the photodiode region and the pixel transistor region.(B6) In any of methods (B1)-(B5), further including forming a doped region in the semiconductor substrate in an area surrounding the trench, wherein forming a doped region comprises implanting boron ions around sidewalls of the trench to form the doped region having a doping concentration higher than the semiconductor substrate.(C1) A CMOS image sensor formed in a semiconductor substrate having a front-side surface includes a first photodiode region comprising at least one photodiode; a pixel transistor region comprising at least one transistor having a gate on the front-side surface and a source/drain in the semiconductor substrate adjacent to the gate; and a first shallow trench isolation (STI) structure comprising a first trench filled with a dielectric material, the first trench having a first depth D formed in the front-side surface to provide isolation between the first photodiode region and the pixel transistor region, said first trench further comprising sloped walls and a polygonal shaped cross-section between the first photodiode region and the pixel transistor region, wherein a width of the first trench varies along a depth of the first trench in the semiconductor substrate from a first width W at the front-side surface to a second width W1larger than the first width W at a second depth D1then to a third width W2smaller than the first width W at the first depth D, wherein the first depth D is greater than the second depth D1with respect to the front-side surface.(C2) In the sensor of (C1), further including a second photodiode region comprising at least one photodiode; and a second STI structure disposed between the second photodiode region and the pixel transistor region and spaced from the first STI structure, the second STI structure comprising a second trench having the first depth D filled with a dielectric and having another polygonal shaped cross-section between the second photodiode region and the pixel transistor region; wherein the pixel transistor region is disposed between the first STI structure and the second STI structure; wherein a spacing between the first STI structure and the second STI structure varies along the depths of the first STI structure and the second STI structure; where the spacing at the front-side surface has a first separation width, decreases to a second separation width at the second depth D1and increases to a third separation width at the first depth D.(C3) In the sensor of (C3), the gate of the at least one transistor partially overlaps the first and the second STI structures.(C4) In either of the sensors of (C2) or (C3), the at least one photodiode in each of the first and second photodiode regions comprises a doped region having a first conductive type, the CMOS image sensor further includes a well region of second conductive type opposite to the first conductive type disposed in the semiconductor substrate, wherein the first and the second STI structures are disposed in the well region.(C5) In any of the sensors of (C2)-(C4), a junction depth of the source/drain is less than the first depth D of the first STI structure and the second STI structure.(C6) In any of the sensors of (C2)-(C5), each of the first and second trenches has an extended polygonal shaped cross-section parallel to a length direction of photodiode region.(C7) In any of the sensors of (C1)-(C6), wherein the first depth D is approximately 120-150 nm.(C8) In any of the sensors of (C1)-(C7), the second depth D1is approximately 10-60 nm.(C9) In any of the sensors of (C1)-(C8), further comprising a boron-doped area in said semiconductor substrate surrounding said first STI structure. Changes may be made in the above methods and systems without departing from the scope hereof. It should thus be noted that the matter contained in the above description or shown in the accompanying drawings should be interpreted as illustrative and not in a limiting sense. Herein, and unless otherwise indicated: (a) the adjective “exemplary” means serving as an example, instance, or illustration, and (b) the phrase “in embodiments” is equivalent to the phrase “in certain embodiments,” and does not refer to all embodiments. The following claims are intended to cover all generic and specific features described herein, as well as all statements of the scope of the present method and system, which, as a matter of language, might be said to fall therebetween. | 30,542 |
11862510 | DETAILED DESCRIPTION A semiconductor device manufacturing method of an embodiment includes forming a first layer in a region of a first substrate excluding an outer peripheral portion thereof; forming a first semiconductor circuit above the first layer; forming a second semiconductor circuit on a second substrate different from the first substrate; forming a second layer with a predetermined width at an outer peripheral portion of the second substrate; bonding a surface of the first substrate on a side provided with the first semiconductor circuit and a surface of the second substrate on a side provided with the second semiconductor circuit; and debonding the first layer and the second layer, thereby forming the second substrate including the first semiconductor circuit and the second semiconductor circuit. Hereinafter, the present invention will be described in detail with reference to the drawings. Note that the present invention is not limited to the following embodiment. Moreover, components in the following embodiment include components easily arrived by those skilled in the art and substantially identical components. (Configuration Example of Semiconductor Device) FIG.1is a view illustrating a configuration example of a semiconductor device300according to the embodiment. As illustrated inFIG.1, the semiconductor device300includes a substrate110, semiconductor circuits131and231, and external terminals350. The substrate110may be, for example, a semiconductor substrate such as a silicon substrate, a ceramic substrate, or a Glass substrate. The substrate110is thinned by grinding, and is diced into a chip shape. A multilayer film130including the semiconductor circuit131is arranged on one surface of the substrate110. A multilayer film230including the semiconductor circuit231is arranged on the multilayer film130. For example, a thin film of silicon may be arranged on the multilayer film230. As described later, an interface between the multilayer films130and230is a bonded surface at which the multilayer films130and230are bonded to each other. At least the outermost surfaces of the multilayer films130and230include insulating layers of SiO2, SION, SiCN, etc. The semiconductor circuits131and231are, for example, flash memories such as three-dimensional NAND flash memories, capacitors or dynamic random access memories (DRAMs), and other memories. For example, the semiconductor circuits131and231may be photodiodes of image sensors, or may be logic circuits including complementary metal oxide semiconductor (CMOS) transistors. Moreover, the semiconductor circuits131and231may be the same type of circuit, or may be different circuits. The multiple external terminals350are arranged at a surface layer of the semiconductor circuit231. Some of the multiple external terminals350are connected to wiring of the semiconductor circuit131in the multilayer film130. Some other external terminals350are connected to wiring of the semiconductor circuit231in the multilayer film230. The semiconductor device300is, for example, mounted on another substrate such as a printed-circuit board. Thus, the semiconductor circuits131and231can be electrically connected to each other at least through the external terminals350. The semiconductor circuits131and231may have terminals (not illustrated) exposed at a bonded surface therebetween, and these terminals may be bonded to each other to electrically connect the semiconductor circuits131and231. The terminals directly connecting the semiconductor circuits131and231to each other are, for example, made of copper (Cu), gold (Au), or platinum (Pt). The semiconductor device300described above is manufactured in such a manner that two substrates110and210illustrated inFIGS.2A,2B,3A, and3Bare bonded to each other, for example. FIGS.2A and2Bare views illustrating a configuration example of a semiconductor device100according to the embodiment.FIG.2Ais a sectional view of the semiconductor device100, andFIG.2Bis a plan view of the semiconductor device100. Note that the multilayer film130is not illustrated inFIG.2B. As illustrated inFIGS.2A and2B, the semiconductor device100includes the substrate110, a de-bondable layer120, and the multilayer film130. The de-bondable layer120with a predetermined width is arranged at an outer peripheral portion110cof the substrate110. The de-bondable layer120is a weak layer relatively-easily cleavable by tensile stress. One end of the de-bondable layer120on an end portion (edge)110eside of the substrate110is arranged inward of the substrate110by a distance d of equal to or longer than 2.0 nm from an end portion110eof the substrate110, for example. The other end of the de-bondable layer120on a central (center) side of the substrate110, i.e., the inner peripheral diameter of the de-bondable layer120, is a distance W1. The multilayer film130has the semiconductor circuit131arranged in a device region130dwithin the distance W1of the substrate110. The multilayer film130has multiple stacked structures including the semiconductor circuit131, and as described above, at least the uppermost layer is the insulating layer. A terminal made of metal may be provided at a surface of the insulating layer in some cases. FIGS.3A and3Bare views illustrating a configuration example of a semiconductor device200according to the embodiment.FIG.3Ais a sectional view of the semiconductor device200, andFIG.3Bis a plan view of the semiconductor device200. Note that the multilayer film230is not illustrated inFIG.3B. As illustrated inFIGS.3A and3B, the semiconductor device200includes the substrate210, a de-bondable layer220, and the multilayer film230. The substrate210may be, for example, a semiconductor substrate such as a silicon substrate, a ceramic substrate, or a glass substrate. The diameter of the substrate210is, for example, substantially equal to the diameter of the substrate110. The de-bondable layer220is arranged at a predetermined depth from a surface of the substrate210in a region excluding an outer peripheral portion210c. The de-bondable layer220is, for example, a weak layer relatively-easily cleavable by tensile stress. The outermost peripheral diameter of the de-bondable layer220is a distance W2. The width of the outer peripheral portion210cof the substrate210is narrower than the width of the outer peripheral portion110cof the substrate110described above. The distance W2as the diameter of the de-bondable layer220is longer than the distance W1as the inner peripheral diameter of the de-bondable layer120described above. As described above, the de-bondable layer220is at the predetermined depth from the surface of the substrate210. For example, a silicon thin layer210tas part of the substrate210is arranged at an upper layer of the de-bondable layer220. The multilayer film230has the semiconductor circuit231arranged in a device region230dwithin the distance W2of the substrate210. The multilayer film230has multiple stacked structures including the semiconductor circuit231, and as described above, at least the uppermost layer is the insulating layer. A terminal made of metal may be provided at a surface of the insulating layer in some cases. The device region230dof the semiconductor device200has a size substantially equal to that of the device region130dof the semiconductor device100described above. (Example of Processing of Manufacturing Semiconductor Device) Next, examples of the processing of manufacturing the semiconductor devices100,200, and300of the embodiment will be described with reference toFIGS.4A to6D. FIGS.4A to4Care flow diagrams illustrating one example of the steps of the processing of manufacturing the semiconductor device100of the embodiment. As illustrated inFIG.4A, the substrate110is prepared. As illustrated inFIG.413the multilayer film130is formed on the substrate110. The semiconductor circuit131in the multilayer film130can be formed using a normal semiconductor circuit manufacturing technique. As illustrated inFIG.4C, the de-bondable layer120is formed at the outer peripheral portion.110cof the substrate110. The de-bondable layer120is formed in such a manner that a surface of the multilayer film130is roughened by polishing with a buff or corrosion with a fluorine-based etching solution, for example. At this point, a surface roughness is preferably equal to or greater than 50 nm. As described above, the processing of manufacturing the semiconductor device100of the embodiment ends. FIGS.5A to5Care flow diagrams illustrating one example of the steps of the processing of manufacturing the semiconductor device200of the embodiment. As illustrated inFIG.5A, the substrate210is prepared. As illustrated inFIG.5E, the outer peripheral portion210cof the substrate210is covered with, e.g., a resist film210p, and ions such as hydrogen ions, oxygen ions, argon ions, or helium ions are implanted (injected) to a predetermined depth of the substrate210inside the outer peripheral portion210c. Alternatively, the substrate210inside the outer peripheral portion210cis irradiated with a laser whose focal point is adjusted to the predetermined depth of the substrate210. In the case of laser irradiation, the resist film210pis not necessarily provided. The outer peripheral portion210cmay be covered with, e.g., a metal layer with high reflectance such that laser transmission is prevented. Laser light may be, for example, ultraviolet light. Pulsed laser may be irradiated. In this case, a pulse width may be, for example, a picosecond, a nanosecond, or a femtosecond. The substrate210at the predetermined depth is modified by ion implantation or laser irradiation, and turns into a weak modified layer220r. Thereafter, the substrate210is annealed to stabilize the modified layer220r, and in this manner, the de-bondable layer220is formed. By stabilization by annealing processing, cleavage of the de-bondable layer220in the middle of formation of the semiconductor circuit231can be reduced, for example. As illustrated inFIG.5C, the multilayer film230is formed on the thin layer210tof the substrate210in which the de-bondable layer220is formed. The semiconductor circuit231in the multilayer film230can be formed using a normal semiconductor circuit manufacturing technique. As described above, the processing of manufacturing the semiconductor device200of the embodiment ends. FIGS.6A to6Dare flow diagrams illustrating one example of the steps of the processing of manufacturing the semiconductor device300of the embodiment. As illustrated inFIG.6A, the substrates110and210are arranged in a state in which the multilayer films130and230formed as described above face each other. The outermost insulating lavers of the multilayer films130and230are, for example, activated by plasma processing. As illustrated inFIG.6B, the activated insulating layers contact each other, and the substrates110and210are bonded to each other by the insulating layers. When the insulating layers have, e.g., metal terminals, the terminals are also bonded to each other. A bonding technique at this point is metal bonding such as Cu—Cu bonding, Au—Au bonding, or Pt—Pt bonding. That is, in a case where the insulating layers have, e.g., the metal terminals, hybrid bonding of bonding between the insulating layers and bonding between the terminals is employed. At the substrates110and210bonded to each other, the device regions130dand230dof the multilayer films130and230are arranged at positions facing each other. That is, the semiconductor circuits131and231face each other. At the substrates110and210bonded to each other, the de-bondable layer120is bonded to a surface of the multilayer film230of the substrate210. The de-bondable layer120has surface roughness as described above, and a bonded area between the de-bondable layer120and the multilayer film230is smaller than that of a flat surface. Thus, a bonding strength between the de-bondable layer120and the multilayer film230is weaker than those in other regions. Moreover, at least part of the de-bondable layers120and220has a portion OL overlapping with each other as viewed from above. As illustrated inFIG.6C, tensile stress is applied to the de-bondable layers120and220. The tensile stress can be applied in such a manner that at least one of the substrates110and210is separated from the other one of the substrates110and210, for example. At this point, a blade may be inserted to between the substrates110and210. Alternatively, fluid spraying with a water jet or gas spraying with an air blade may be performed for a portion between the substrates110and210, for example. In this manner, the de-bondable layer120with a weak bonding strength is, for example, debonded from an end portion110eside of the substrate110, and therefore, a cleavage groove CLV is caused. The cleavage groove CLV extends inward of the substrate110along the de-bondable layer120. When reaching the portion OL at which the de-bondable layers120and220overlap with each other, the cleavage groove CLV extends toward a substrate210side, and reaches the de-bondable layer220. The cleavage groove CLV having reached the de-bondable layer220extends inward of the substrate210along the de-bondable layer220. Eventually, the de-bondable layers120and220across the entire surfaces of the substrates110and210are debonded, and the substrates110and210are separated from each other. Note that when the de-bondable layer120is debonded, the de-bondable layer120may be debonded at any of a portion inside the de-bondable layer120, a portion at an interface between the de-bondable layer120and the multilayer film130, and a portion at an interface between the de-bondable layer120and the multilayer film230. When the de-bondable layer220is debonded, the de-bondable layer220may be debonded at any of a portion inside the de-bondable layer220, a portion at an interface between the de-bondable layer220and the substrate210, and a portion at an interface between the de-bondable layer220and the thin layer210t. As illustrated inFIG.6D, the substrate110separated as described above is arranged such that the multilayer film230separated from the substrate210and including the semiconductor circuit231is on the multilayer film130including the semiconductor circuit131and the thin layer210tis on the multilayer film230. That is, the substrate110has both of the semiconductor circuits131and231. Note that part or the entirety of the debonded de-bondable layer120may be present on the multilayer film130at the outer peripheral portion110c. Moreover, part or the entirety of the debonded de-bondable layer220may be present on the thin layer210t. Thereafter, the substrate110is surface-cleaned and flattened. Thereafter, a via340and the external terminals350are formed, and therefore, the semiconductor device300is manufactured. Note that by cleaning processing and flattening processing, at least the de-bondable layers120and220are eliminated from the substrate110. Moreover, the thin layer210tand the multilayer film230are absent in a region of the substrate210separated as described above inside the outer peripheral portion210c. That is, the semiconductor circuit231is eliminated from the substrate210. Note that part or the entirety of the debonded de-bondable layer220may be present on the substrate210in the region inside the outer peripheral portion210c. Moreover, part or the entirety of the debonded de-bondable layer120may be present on the multilayer film230at the outer peripheral portion210c. Thereafter, the substrate210is re-utilized as a recycled substrate after, e.g., the cleaning processing and the flattening processing. As described above, the processing of manufacturing the semiconductor device300of the embodiment ends. Comparative Example In the processing of manufacturing a semiconductor device of a comparative example, a substrate configured such that a multilayer film is formed on a de-bondable layer formed across an entire surface of the substrate and a substrate configured such that a multilayer film is formed without a de-bondable layer are used. However, when the de-bondable layer is formed across the entire surface of the substrate, the de-bondable layer might be, in some cases, debonded in the middle of formation of a semiconductor circuit even before bonding of the substrates, and the multilayer film and the substrate might be separated from each other, for example. The semiconductor device200of the embodiment includes the de-bondable layer220arranged in the region excluding the outer peripheral portion210c. Thus, separation of the multilayer film230and the substrate210in the middle of formation of the semiconductor circuit231is reduced, for example. Thus, a yield ratio in the processing of manufacturing the semiconductor device200is improved. The semiconductor device100of the embodiment includes the de-bondable layer120having the predetermined width and arranged at the outer peripheral portion110c. Thus, after the multilayer films130and230have been bonded to each other, the substrate210can be more reliably separated. Thus, a yield ratio in the processing of manufacturing the semiconductor device300is improved. The semiconductor device300of the embodiment is manufactured by separation of the substrates110and210. Thus, separation is allowed without grinding and removing the substrate210, for example. Consequently, re-utilization of the substrate210is allowed. As a result, a cost for the processing of manufacturing the semiconductor device300can be reduced. (First Variation) Next, the processing of forming a de-bondable layer121on the substrate110in a first variation of the embodiment will be described with reference toFIGS.7A to7D. The first variation is an example in a case where a terminal140is provided at the surface of the multilayer film130. FIGS.7A to7Dare flow diagrams illustrating one example of the steps of the processing of forming the de-bondable layer121according to the first variation of the embodiment. As illustrated inFIG.7A, multiple grooves130trare formed at a surface layer portion of the multilayer film130of the substrate110. As illustrated inFIG.7B, a metal layer140mof, e.g., copper, gold, or platinum is formed on the multilayer film130interposing not-illustrated barrier metal, and the grooves130trare filled with the metal layer140m. The metal layer140mcan be formed by plating processing, for example. As illustrated inFIG.7C, a resist pattern110pis formed on the metal layer140mexcluding the outer peripheral portion110cof the substrate110, and the metal layer140mat the outer peripheral portion110cis removed by wet etching. As illustrated inFIG.7D, the metal layer140mremaining inside the outer peripheral portion110cis removed by, e.g., chemical mechanical polishing (CEP), and a terminal140is formed only in the filled grooves130tr. The de-bondable layer121having the multiple grooves130tris formed at the outer peripheral portion110c. A bonded area between the de-bondable layer121and the multilayer film230of the substrate210can be decreased by the multiple grooves130tr, and a bonding strength can be weakened. (Second Variation) Next, the de-bondable layer220arranged on the substrate210in a second variation of the embodiment will be described with reference toFIG.8. The de-bondable layer220of the second variation is different from that of the above-described embodiment in that the de-bondable layer220is arranged in a predetermined layer on the substrate210. FIG.8is a view illustrating the de-bondable layer220arranged on the substrate210according to the second variation of the embodiment. As illustrated inFIG.8, an insulating layer250is arranged on the substrate210of the second variation. A semiconductor layer260is arranged on the insulating layer250. The multilayer film230is arranged on the semiconductor layer260. The insulating layer250is, for example, a SiO2layer, and as described later, functions as a protection layer upon formation of the de-bondable layer220in the semiconductor layer260. The semiconductor layer260is, for example, a polysilicon layer or an amorphous silicon laver. The de-bondable layer220is arranged in the semiconductor layer260. In the above-described embodiment, the ions are implanted to the predetermined depth of the substrate210, or the predetermined depth of the substrate210is irradiated with the laser whose focal point is adjusted to the predetermined depth. In this manner, the de-bondable layer220is formed in the substrate210. However, as in the configuration of the second variation, the semiconductor layer260for injecting the de-bondable layer220to above the substrate210protected by the insulating layer250may be provided, and the de-bondable layer220may be formed in the semiconductor layer260. Thus, the substrate210can be protected while the de-bondable layer220can be more reliably formed in an intended layer. (Third Variation) Next, the processing of forming a de-bondable layer221on the substrate210in a third variation of the embodiment will be described with reference toFIGS.9A to9C.FIGS.9A to9Care flow diagrams illustrating one example of the steps of the processing of forming the de-bondable layer221according to the third variation of the embodiment. As illustrated inFIG.9A, an insulating layer240such as a silicon oxidized layer is, for example, formed on front and back surfaces of the substrate210, except for the region of the substrate210inside the outer peripheral portion210c. As illustrated inFIG.9B, the region of the substrate210inside the outer peripheral portion210cis anodically oxidized. Specifically, current is, for example, applied in a hydrofluoric acid ethanol solution with the substrate210serving as an anode. Thus, micropores with a diameter of several nm are formed at a surface layer portion of the substrate210, and a porous layer221pras a porous surface layer of the substrate210is formed. As illustrated inFIG.9C, the insulating layer240on the back surface of the substrate210is removed, and a surface of the porous layer221pris flattened by annealing to form the de-bondable layer221. An insulating thin layer240tsuch as a silicon oxidized layer may be formed on the de-bondable layer221. Note that the substrate210of the third variation does not have the thin layer210tof, e.g., silicon. Thus, in a case where any of the semiconductor circuits formed on the substrates110and210includes a configuration in which a diffusion layer is provided at a surface layer of a semiconductor layer, such as a CMOS transistor, such a semiconductor circuit is formed on the substrate110. (Fourth Variation) In a fourth variation, variations of the de-bondable layer provided at the outer peripheral portion will be described with reference toFIGS.10A to10C.FIGS.10A to10Care views of the variations of the de-bondable layer according to the fourth variation of the embodiment. As illustrated inFIG.10A, the de-bondable layer at the outer peripheral portion may be provided on both of the substrates110and210. That is, in addition to the de-bondable layer120of the substrate110, a de-bondable layer222may be arranged on the substrate210at a position corresponding to the de-bondable layer120of the substrate110. As in the above-described embodiment and the first variation, the de-bondable layer222can be also formed by, e.g., the processing of roughening a surface or the processing of forming grooves not filled with metal. As illustrated inFIG.10B, a gap123may be provided between the substrates110and210instead of the de-bondable layer at the outer peripheral portion. That is, at least part of the multilayer film130at the outer peripheral portion110cof the substrate110is removed, and in this manner, the gap123is formed. Thus, the substrates110and210are not bonded to each other at the outer peripheral portions110cand210c, and advantageous effects similar to those or the de-bondable layer120of the embodiment are provided. As illustrated inFIG.10C, a gap223may be also provided at the substrate210. That is, in addition to the gap123at the outer peripheral portion110cof the substrate110, the gap223is also provided at the outer peripheral portion210cof the substrate210. In this case, as in the gap123of the substrate110, at least part of the multilayer film230at the outer peripheral portion210cis removed, and in this manner, the gap223can be also formed at the substrate210. While certain embodiments have been described, these embodiments have been presented by way of example only, and are not intended to limit the scope of the inventions. Indeed, the novel embodiments described herein may be embodied in a variety of other forms; furthermore, various omissions, substitutions and changes in the form of the embodiments described herein may be made without departing from the spirit of the inventions. The accompanying claims and their equivalents are intended to cover such forms or modifications as would fall within the scope and spirit of the inventions. | 25,014 |
11862511 | DETAILED DESCRIPTION With reference toFIG.1and in accordance with embodiments of the invention, a semiconductor-on-insulator substrate includes a device layer12, a buried insulator layer14, and a handle substrate16. The device layer12is separated from the handle substrate16by the intervening buried insulator layer14and is considerably thinner than the handle substrate16. The device layer12may be comprised of a semiconductor material, such as single-crystal silicon, and may be intrinsic or lightly doped p-type, and the buried insulator layer14may be comprised of a dielectric material, such as silicon dioxide, that is an electrical insulator. The buried insulator layer14has a lower surface in direct contact with the handle substrate16along an interface and an upper surface in direct contact with the device layer12along another interface, and the interfaces are separated by the thickness of the buried insulator layer14. The device layer12is electrically isolated from the handle substrate16by the buried insulator layer14. In an embodiment, the device layer12may have a thickness in a range of about 4 nanometers (nm) to about 100 nm, and the buried insulator layer14may have a thickness in a range of about 50 nm to about 250 nm. A shallow trench isolation region18is formed in the device layer12, and may extend fully through the device layer12. The shallow trench isolation region18may be formed by patterning a trench extending through the device layer12with lithography and etching processes, depositing a dielectric material to fill the trench, and planarizing and/or recessing the dielectric material. The shallow trench isolation region18may contain a dielectric material, such as silicon dioxide, deposited by chemical vapor deposition and planarized by chemical-mechanical polishing. With reference toFIG.2in which like reference numerals refer to like features inFIG.1and at a subsequent fabrication stage of the processing method, a trench isolation region20is formed that penetrates through the shallow trench isolation region18and the buried insulator layer14, and into the handle substrate16. The trench isolation region20may be formed by patterning a trench19with lithography and etching processes, depositing a dielectric material to fill the trench19, and planarizing and/or recessing the dielectric material. The trench isolation region20may contain a dielectric material, such as silicon dioxide, deposited by chemical vapor deposition and planarized by chemical-mechanical polishing. With reference toFIG.3in which like reference numerals refer to like features inFIG.2and at a subsequent fabrication stage of the processing method, a trench22is formed within the interior (i.e., inside the outer perimeter) of the trench isolation region20. The trench22may be formed by patterning the dielectric material of the trench isolation region20with lithography and etching processes. To that end, an etch mask23is formed by a lithography process over the trench isolation region20. The etch mask23includes an opening located at the intended location for the trench22. The opening in the etch mask23has an area in a normal direction that is less than the surface area of the trench isolation region20. An etching process, such as reactive ion etching, is employed to etch and remove the dielectric material of the trench isolation region20exposed by the opening in the etch mask23. The trench22includes a bottom24and sidewalls26that are fully surrounded by a thickness of the dielectric material of the trench isolation region20. The etching process is controlled (e.g., timed) to penetrate only partially through the thickness of the trench isolation region20. As a result, a thickness of the dielectric material of the trench isolation region20is arranged as a lower margin between the bottom24of the trench22and the handle substrate16. The lateral dimensions of the trench22are less than the lateral dimensions of the trench isolation region20. As a result, a thickness of the dielectric material of the trench isolation region20is arranged as a lateral margin between the sidewalls26of the trench22and the handle substrate16and surrounding the sidewalls26of the trench22. With reference toFIG.4in which like reference numerals refer to like features inFIG.3and at a subsequent fabrication stage of the processing method, openings30are formed that penetrate fully through the dielectric material of the trench isolation region20at the bottom24of the trench22to the handle substrate16. The openings30may be formed by patterning the dielectric material of the trench isolation region20at the bottom24of the trench22with lithography and etching processes. The openings30extend from the trench19to the trench22such that open paths exist between the interior of the trench22and the handle substrate16. The openings30may be rectangular trenches or may have another suitable geometrical shape. With reference toFIGS.5,5Ain which like reference numerals refer to like features inFIG.4and at a subsequent fabrication stage of the processing method, a semiconductor layer32is formed inside the trench22after the openings30are formed. The semiconductor layer32may be comprised of a single-crystal semiconductor material, such as single-crystal silicon, that is monocrystalline with a defect density less than a threshold defect level. In an embodiment, the semiconductor layer32may be undoped to provide a high electrical resistivity. In an embodiment, the semiconductor layer32may contain single-crystal semiconductor material having an electrical resistivity in range of about 1,000 ohm-cm to about 50,000 ohm-cm. The semiconductor layer32may be formed using an epitaxial growth process to grow single-crystal semiconductor material (e.g., single-crystal silicon) that is subsequently planarized by chemical-mechanical polishing. The semiconductor layer32may be formed by a selective epitaxial growth process in which process conditions are selected to cause the semiconductor material to selectively grow from exposed semiconductor material but not from exposed dielectric material. The portions of the handle substrate16accessible through the openings30provide seed windows during epitaxial growth and collectively serve as a crystalline template for the crystal structure of the epitaxially-grown semiconductor layer32. The semiconductor layer32is effectively positioned inside a tub of dielectric material provided by the dielectric material margins of the patterned trench isolation region20. The tub of dielectric material contributes to electrically isolating the semiconductor layer32from the handle substrate16. The semiconductor layer32may include a top surface33that is either coplanar or substantially coplanar, following planarization, with a top surface17of the shallow trench isolation region18and/or with a top surface11of the device layer12. Portions of the semiconductor layer32, which contain single-crystal semiconductor material, are positioned as pillars inside the openings30. With reference toFIG.6in which like reference numerals refer to like features inFIG.5and at a subsequent fabrication stage of the processing method, a polycrystalline layer36containing polycrystalline semiconductor material (e.g., polysilicon) may be formed in the handle substrate16beneath the trench isolation region20. In the representative embodiment, the semiconductor layer32inside the openings30and a lower portion of the semiconductor layer32adjacent to the bottom24of the trench22may be converted to polycrystalline semiconductor material when the polycrystalline layer36is formed. In an alternative embodiment, the portions of the semiconductor layer32inside the openings30may contain single-crystal semiconductor material. The polycrystalline semiconductor material in the polycrystalline layer36and the polycrystalline semiconductor material formed in the semiconductor layer32may contain polycrystalline grains of semiconductor material, as well as other defects. The polycrystalline semiconductor material may be characterized as a trap-rich material that is capable of efficiently capturing charge carriers and provides additional electrical isolation between the semiconductor layer32and the handle substrate16. In that regard, the polycrystalline semiconductor material may have an electrical resistivity that is greater than or equal to the electrical resistivity of the handle substrate16. In an embodiment, the polycrystalline semiconductor material may have an electrical resistivity that is greater than or equal to 1,000 ohm-cm. In an embodiment, the electrical resistivity of the polycrystalline semiconductor material may be within a range of 1,000 ohm-cm to 10,000 ohm-cm. The polycrystalline semiconductor material in the polycrystalline layer36and the polycrystalline semiconductor material formed in the semiconductor layer32may be formed by a sequence of ion implantation and annealing processes. The ion implantation process, which may utilize an implantation mask and argon ions, causes damage to the crystal structure of the semiconductor material. An annealing process (e.g., a rapid thermal anneal) may be used to recrystallize the damaged semiconductor material. The conditions for the ion implantation may be adjusted to control the spatial extent and boundaries of the polycrystalline semiconductor material. With reference toFIG.7in which like reference numerals refer to like features inFIG.6and at a subsequent fabrication stage of the processing method, a switch field-effect transistor40may be fabricated by front-end-of-line processing as a device structure in the semiconductor layer32. The switch field-effect transistor40may include gates42over the top surface33of the semiconductor layer32and source/drain regions44that are formed in the semiconductor layer32. The gates42may be formed, for example, as gate fingers by patterning a deposited layer of heavily-doped polysilicon, and the source/drain regions44may be formed by ion implantation or diffusion of, for example, an n-type dopant. The switch field-effect transistor40may include other elements, such as a gate dielectric between the gates42and the semiconductor layer32, halo regions, and extension regions. In an embodiment, the switch field-effect transistor40may be configured to switch signal paths in a radiofrequency integrated circuit. Middle-of-line processing and back-end-of-line processing follow, which includes formation of contacts, vias, and wiring for an interconnect structure that is coupled to the switch field-effect transistor40. In an alternative embodiment, the semiconductor substrate may be a bulk substrate comprised of a single-crystal semiconductor material, such as single-crystal silicon. The trench isolation region20is bordered by the single-crystal semiconductor of the bulk substrate, and the dielectric material of the trench isolation region20is arranged between the semiconductor layer32and the bulk substrate other than at the locations of the openings30. The semiconductor layer32defines a single-crystal semiconductor body that is embedded inside the dielectric material of the patterned trench isolation region20(i.e., inside a tub of dielectric material). The device layer12, the trench isolation region20, and the semiconductor layer32may have coplanar or substantially coplanar upper or top surfaces11,17,33. The openings30provide seed windows during epitaxial growth and are arranged between the handle substrate16and the semiconductor body defined by the semiconductor layer32. The polycrystalline layer36provides high-resistivity polysilicon in the handle substrate16underneath the trench isolation region20and between the single-crystal semiconductor material of the semiconductor layer32and the handle substrate16. The polycrystalline semiconductor material of the semiconductor layer32inside the seed windows also provides high-resistivity polysilicon between the single-crystal semiconductor material of the semiconductor layer32and the handle substrate16. In an embodiment, the switch field-effect transistor40may be formed using the single-crystal semiconductor material as a device structure in an upper portion of the semiconductor layer32. The dielectric material of the trench isolation region20surrounding the semiconductor layer32, as well as the polycrystalline semiconductor material in the polycrystalline layer36and the polycrystalline semiconductor material formed in the semiconductor layer32, may contribute to reducing harmonic distortion at small channel lengths during operation of the switch field-effect transistor40. The linearity, off-capacitance, electrical isolation, occupied chip area, electrostatic discharge performance, and latch-up performance of the switch field-effect transistor40may also be improved during operation. With reference toFIG.8in which like reference numerals refer to like features inFIG.4and in accordance with alternative embodiments of the invention, the single-crystal semiconductor material of the semiconductor layer32may be initially formed only inside the openings30. The semiconductor material inside each opening30defines an initial pillar of single-crystal semiconductor material extending away from the handle substrate16. With reference toFIG.9in which like reference numerals refer to like features inFIG.8and at a subsequent fabrication stage of the processing method, the dielectric material of the trench isolation region20between the bottom24of the trench22and the handle substrate16may be thinned, but not removed, by performing an etching process. The etching process may remove the dielectric material of the trench isolation region20selective to the single-crystal semiconductor material of the semiconductor layer32arranged as pillars inside the openings30. As used herein, the term “selective” in reference to a material removal process (e.g., etching) denotes that, with an appropriate etchant choice, the material removal rate (i.e., etch rate) for the targeted material is greater than the removal rate for at least another material exposed to the material removal process. As a result, a portion of the pillar of semiconductor material inside each opening30projects by a distance D above the dielectric material of the trench isolation region20at the bottom24of the trench22. The semiconductor layer32is subsequently formed inside the remainder of the trench22by an epitaxial growth process as previously described. The pillars inside the openings30in the thinned trench isolation region20provide growth seeds for the epitaxial growth process, and epitaxial growth may initially proceed laterally from the different pillars and then merge into a single mass as the trench22is filled by semiconductor material. Processing may continue to form the polycrystalline layer36and the switch field-effect transistor40. With reference toFIG.10and in accordance with alternative embodiments of the invention, deep trench isolation regions46may be formed that surround a region of the semiconductor-on-insulator substrate. The deep trench isolation regions46may be formed when the trench isolation region20is formed. The device layer12and buried insulator layer14may be removed from the surrounded region to expose the handle substrate16, and a device structure48, such as a low-noise amplifier or a power amplifier, may be formed using the exposed handle substrate16. A device structure50, such as a fully-depleted field-effect transistor, may be formed using the device layer12in a different region of the semiconductor-on-insulator substrate. The device structures48,50are formed on the same substrate as the switch field-effect transistor40. The dielectric material of the trench isolation region20at the bottom24of the trench22may be multiple times (e.g., 3 times to 5 times) thicker than the buried insulator layer14because the switch field-effect transistor40may require a greater thickness of electrical insulator than the device structure50to provide adequate electrical isolation from the handle substrate16. In an embodiment, the switch field-effect transistor40may be connected through the interconnect structure to the device structure48. The methods as described above are used in the fabrication of integrated circuit chips. The resulting integrated circuit chips can be distributed by the fabricator in raw wafer form (e.g., as a single wafer that has multiple unpackaged chips), as a bare die, or in a packaged form. The chip may be integrated with other chips, discrete circuit elements, and/or other signal processing devices as part of either an intermediate product or an end product. The end product can be any product that includes integrated circuit chips, such as computer products having a central processor or smartphones. References herein to terms modified by language of approximation, such as “about”, “approximately”, and “substantially”, are not to be limited to the precise value specified. The language of approximation may correspond to the precision of an instrument used to measure the value and, unless otherwise dependent on the precision of the instrument, may indicate a range of +/−10% of the stated value(s). References herein to terms such as “vertical”, “horizontal”, etc. are made by way of example, and not by way of limitation, to establish a frame of reference. The term “horizontal” as used herein is defined as a plane parallel to a conventional plane of a semiconductor substrate, regardless of its actual three-dimensional spatial orientation. The terms “vertical” and “normal” refer to a direction perpendicular to the horizontal, as just defined. The term “lateral” refers to a direction within the horizontal plane. A feature “connected” or “coupled” to or with another feature may be directly connected or coupled to or with the other feature or, instead, one or more intervening features may be present. A feature may be “directly connected” or “directly coupled” to or with another feature if intervening features are absent. A feature may be “indirectly connected” or “indirectly coupled” to or with another feature if at least one intervening feature is present. A feature “on” or “contacting” another feature may be directly on or in direct contact with the other feature or, instead, one or more intervening features may be present. A feature may be “directly on” or in “direct contact” with another feature if intervening features are absent. A feature may be “indirectly on” or in “indirect contact” with another feature if at least one intervening feature is present. Different features may “overlap” if a feature extends over, and covers a part of, another feature. The descriptions of the various embodiments of the present invention have been presented for purposes of illustration but are not intended to be exhaustive or limited to the embodiments disclosed. Many modifications and variations will be apparent to those of ordinary skill in the art without departing from the scope and spirit of the described embodiments. The terminology used herein was chosen to best explain the principles of the embodiments, the practical application or technical improvement over technologies found in the marketplace, or to enable others of ordinary skill in the art to understand the embodiments disclosed herein. | 19,343 |
11862512 | DETAILED DESCRIPTION The following disclosure provides many different embodiments, or examples, for implementing different features of the provided subject matter. Specific examples of components and arrangements are described below to simplify the present disclosure. These are, of course, merely examples and are not intended to be limiting. For example, the formation of a first feature over or on a second feature in the description that follows may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features may be formed between the first and second features, such that the first and second features may not be in direct contact. In addition, the present disclosure may repeat reference numerals and/or letters in the various examples. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed. Further, spatially relative terms, such as “beneath,” “below,” “lower,” “above,” “upper” and the like, may be used herein for ease of description to describe one component or feature's relationship to another component(s) or feature(s) as illustrated in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The apparatus may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein may likewise be interpreted accordingly. Other features and processes may also be included. For example, testing structures may be included to aid in the verification testing of the 3D packaging or 3DIC devices. The testing structures may include, for example, test pads formed in a redistribution layer or on a substrate that allows the testing of the 3D packaging or 3DIC, the use of probes and/or probe cards, and the like. The verification testing may be performed on intermediate structures as well as the final structure. Additionally, the structures and methods disclosed herein may be used in conjunction with testing methodologies that incorporate intermediate verification of known good dies to increase the yield and decrease costs. FIGS.1-7schematically illustrate various stages of processes for forming a redistribution layer according to a method of fabricating a semiconductor package in accordance with some embodiments. Referring toFIG.1, a substrate102having a plurality of contacts104is provided. In some embodiments, a first dielectric material layer110is formed over the substrate100and covering the contacts104. In some embodiments, the substrate102may include one or more semiconductor chips or plural dies of a semiconductor wafer or a reconstituted wafer. In certain embodiments, the substrate102is a reconstituted wafer including a plurality of dies molded in a molding compound. In some embodiments, the contacts104are contact pads or conductive pads of the die(s). In some embodiments, the substrate102may be a monocrystalline semiconductor substrate such as a silicon substrate, a silicon-on-insulator (SOI) substrate or a germanium-on-insulator (GOI) substrate, for example. In accordance with the embodiments, the semiconductor substrate may include other conductive layers, doped regions or other semiconductor elements, such as transistors, diodes or the like. The embodiments are intended for illustration purposes but not intended to limit the scope of the present disclosure. Referring toFIG.1, in some embodiments, the first dielectric material layer110may be formed by a coating process such as spin-coating process, or a deposition process including a chemical vapor deposition (CVD) process. In certain embodiments, the first dielectric material layer110may be a positive photo-sensitive material layer. In some embodiments, a material of the dielectric material layer110may be a positive type photo-sensitive material, including polyimide, benzocyclobutene (BCB), polybenzooxazole (PBO), or any other suitable photo-sensitive polymer materials or other photoresist materials. In certain embodiments, the material of the dielectric material layer110may be a positive photoresist material, and the positive photoresist materials may be H-line, I-line, wide-band or deep-UV photoresist materials. Referring toFIG.2, a first exposure process E1is performed to the first dielectric material layer110to form first exposure portions110A. In some embodiments, the first exposure process E1is performed using a mask MK1with a first pattern PT1, with light or illumination (as arrows) radiated from a light source (not shown) passing through the mask MK1. In some embodiments, the first pattern PT1includes a plurality of openings PTO1. In certain embodiments, the image of the first pattern PT1is transferred to the first dielectric material layer110through the first exposure process E1. InFIG.2, the first dielectric material layer110is partially exposed by the light or illumination through the first exposure process E1, and the first exposure portions110A are formed in the exposed regions (shown as the spotted regions) of the first dielectric material layer110exposed to the light passing through the openings PTO1. In some embodiments, by adjusting the energy level or energy dose of the energy source (i.e. light source) and/or the exposure time, the depth of the exposure regions (the depth that light can reach) may be accurately controlled. In some embodiments, the first exposure process E1is performed with a first energy dose, and the first exposure portions110A are formed with a depth d1and a bottom size S1in the horizontal direction x (perpendicular to the thickness direction z of the first dielectric material layer110). In certain embodiments, the depth d1of the first exposure portions110A is substantially equivalent to a thickness T1of the first dielectric material layer110. In certain embodiments, the thickness T1of the first dielectric material layer110ranges from about 10 microns to about 30 microns, and the first energy dose ranges from about 50 mJ/cm2to about 100 mJ/cm2. In some embodiments, the first exposure portions110A constitute a latent pattern and the latent pattern is a reproduce of the first pattern PT1. That is, the locations and shapes of the first exposure portions110A correspond to and simulate substantially the locations and shapes of the openings PTO1. In some embodiments, the latent pattern of the first exposure portions110A includes a via-opening pattern. In accordance with the embodiments, the image of the pattern(s) of the mask will be transferred fully or partially to the target material layer or structure in any specific ratio for amplification or reduction purposes. The embodiments are intended for illustration purposes but not intended to limit the scope of the present disclosure. For the positive photo-sensitive material or positive photoresist material, exposure to light of a suitable wavelength (which is material dependent) leads to chemical reactions of the positive photo-sensitive material or positive photoresist material, and the treated portions will become more soluble or be much easier to be removed during the subsequently development process. In some embodiments, as the first dielectric material layer110is a positive photo-sensitive material layer, the first exposure portions110A of the first dielectric material layer110are chemically reacted and become soluble during the subsequently development process. Referring toFIG.3, a second exposure process E2is performed to the first dielectric material layer110to form second exposure portions110B. In some embodiments, the second exposure process E2is performed using a mask MK2with a second pattern PT2, with light or illumination (as arrows) passing through the mask MK2. In some embodiments, the masks MK1, MK2may refer to different portions of the same mask or two masks. In some embodiments, the second pattern PT2includes a plurality of openings PTT1. In certain embodiments, the image of the second pattern PT2is transferred to the first dielectric material layer110through the second exposure process E2. InFIG.3, the first dielectric material layer110is partially exposed by the light or illumination through the second exposure process E2, and the second exposure portions110B are formed in the exposed regions (shown as the spotted regions) of the first dielectric material layer110exposed to the light passing through the openings PTT1. In certain embodiments, the locations and shapes of the second exposure portions110B correspond to and simulate substantially the locations and shapes of the openings PTT1. In some embodiments, the second exposure process E2is performed with a second energy dose and the second exposure portions110B are formed with a depth d2and a bottom size S2in the horizontal direction x (perpendicular to the thickness direction z of the first dielectric material layer110). In certain embodiments, the depth d2of the second exposure portions110B is smaller than the thickness T1of the first dielectric material layer110. In certain embodiments, the depth d2of the second exposure portions110B is smaller than the depth d1of the first exposure portions110A. In one embodiment, the second energy dose is lower than the first energy dose. In some embodiments, the second energy dose ranges from about 50 mJ/cm2to about 100 mJ/cm2. In some embodiments, the second exposure portions110B constitute a latent pattern and the latent pattern is a reproduce of the second pattern PT2. In some embodiments, the ratio of depth d2/d1may be about 0.4˜0.6. In some embodiments, the locations of the first exposure portions110A are overlapped with the locations of parts of the second exposure portions110B. In some embodiments, the latent pattern of the second exposure portions110B includes a trench-opening pattern. In some embodiments, the first exposure process E1and the second exposure process E2can be considered as a double exposure process. In certain embodiments, only one photo-sensitive dielectric material layer is needed for such double exposure process, the process steps of such double exposure process are much simplified when compared with conventional photolithographic exposure processes performed twice, thus lowering the costs and saving time for the formation of the redistribution layer (RDL). In some embodiments, by performing two consecutive exposure processes, better exposure alignment for the patterns and more accurate pattern overlay (especially RDL to the vias) can be achieved. In certain embodiments, the same mask is used for performing the two consecutive exposure processes, only once mask alignment is required and no extra alignment is required and better pattern overlay is attained. InFIG.4, in some embodiments, a first development process is conducted to remove the first and second exposure portions110A,110B of the first dielectric material layer110, and the first dielectric pattern111is formed, thus implementing the pattern transfer of masks MK1, MK2. In some embodiments, the first development process includes applying a developer solution to dissolve or remove at least the exposed regions during the first and second exposure processes E1, E2(i.e. the first and second exposure portions110A,110B) so as to expose the underlying contacts104. For example, the developer solution includes solutions of tetramethyl ammonium hydroxide (TMAH). In some embodiments, the developed first dielectric pattern111is then cured under 200-250 degrees Celsius. In some embodiments, the first and second exposure portions110A,110B may be removed simultaneously by the same development process. In certain embodiments, following the removal of at least the first and second exposure portions110A,110B, the trench openings TS1with the depth d4and the via openings VS1with the depth d3are formed and the first dielectric pattern111having the thickness T2is formed. In some embodiments, film loss may occur during the first development process and the thickness T2of the first dielectric pattern111is smaller than the thickness T1of the first dielectric material layer110. In certain embodiments, the trench openings TS1and the via openings VS1correspondingly and spatially communicated with the trench openings TS1constitute dual damascene openings or damascene openings DS1. In some embodiments, only some of trench openings TS1are connected with some of the via openings VS1to form the damascene openings DS1. In some embodiments, some of trench openings TS1are not connected with some of the via openings VS1. In some embodiments, in addition to the removal of the first and second exposure portions110A,110B, the first development process may include over-developing the first dielectric material layer110by removing the first dielectric material layer110excessively around the first and second exposure portions110A,110B to form the via openings VS1and trench openings TS1as well as the damascene openings DS1as shown inFIG.4. In some embodiments, similar to the isotropic etching process, the over-developing of the first dielectric material layer110further widen the openings. In addition, a curing process may be included to cure the first dielectric material layer110, and the curing of the first dielectric material layer110makes the sidewalls of the openings inclined. In some embodiments, owing to the over-developing and curing, the via opening VS1is formed with a depth d3and a bottom size S3in the horizontal direction x (perpendicular to the thickness direction z), and the trench opening TS1is formed with a depth d4and a bottom size S4in the horizontal direction x. In some embodiments, the trench openings TS1, the via openings VS1and the damascene openings DS1become tapering with slanted sidewalls. In some embodiments, the bottom size S3of the via openings VS1is larger than the bottom size S1of the first exposure portions110A. In some embodiments, the bottom size S4of the trench openings TS1is larger than the bottom size S2of the second exposure portions110B. In some embodiments, the depth d3is smaller than the depth d1, while the depth d4is smaller than the depth d2. In some embodiments, the ratio of depth d4/d3may be about 0.4˜0.6. In some embodiments, the ratio of bottom sizes S3/S1is equivalent to 1.5 or larger than 1.5. In some embodiments, the ratio of bottom sizes S4/S2is equivalent to 1.5 or larger than 1.5. In some embodiments, the via opening VS1is a round shaped opening and the bottom size S3of the via opening VS1is the largest dimension or the diameter of the via opening VS1. In some embodiments, the trench opening TS1is a strip trench and the bottom size S4of the trench opening TS1is the largest dimension or the length in the length direction (marked as direction x inFIG.4). Referring toFIG.5, in some embodiments, a first seed metallic layer120is formed over the first dielectric pattern111having damascene openings DS1and on the contacts104. In some embodiments, the first seed metallic layer120is formed conformal to the profiles of the first dielectric pattern111with damascene openings DS1, evenly covering the sidewalls and bottom surfaces of the damascene openings DS1and the top surface of the first dielectric pattern111. In certain embodiments, the first seed metallic layer120is formed by chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), high density plasma CVD (HDPCVD) or combinations thereof. In certain embodiments, the first seed metallic layer120is formed by sequentially depositing or sputtering a titanium layer and a copper layer (not shown) conformal to the first dielectric pattern111and the damascene openings DS1. In one embodiment, the first seed metallic layer120covers and is in contact with the exposed surfaces of the contacts104(i.e. bottom surfaces of the via openings VS1). In certain embodiments, for the trench openings TS1that are not connected with the via openings VS1, the first seed metallic layer120is formed conformally covering the sidewalls and bottom surfaces of the trench openings TS1. Owing to the slant or inclined sidewalls of the openings TS1, VS1or DS1, better and more uniform step coverage may be achieved, especially for the first seed metallic layer120formed by sputtering. Hence, the reliability and electrical performance of the redistribution layer/structure are further improved. Referring toFIG.6, a first metal layer130is formed to fill up the damascene openings DS1and on the first seed metallic layer120over the first dielectric pattern111. In some embodiments, the formation of the first metal layer130including forming a copper layer or a copper alloy layer (not shown) by electroplating to fill the damascene openings DS1and on the first seed metallic layer120over the first dielectric pattern111. However, it is appreciated that the scope of this disclosure is not limited to the materials and descriptions disclosed above. In certain embodiments, for the trench openings TS1that are not connected with the via openings VS1, the first metal layer130is formed filling up the trench openings TS1. In some embodiments, as a conformal seed layer is formed before filling the metal layer into the openings, better adhesion is ensured for the later formed metal layer. Moreover, the conformal seed layer may assist lowering the resistance and improving electrical properties for the redistribution layer. Referring toFIG.7, a planarization process is performed to partially remove the first metal layer130and the first seed metallic layer120above the top surface111aof the first dielectric pattern111. In some embodiments, the first metal layer130along with the first seed metallic layer120above the top surface111aof the first dielectric pattern111are removed until the top surface111aof the first dielectric pattern111is exposed, and first seed metallic patterns121and dual damascene redistribution patterns131filled within the damascene openings DS1are formed. In some embodiments, the planarization process may include a chemical-mechanical polishing (CMP) process, a mechanical grinding process, a fly cutting process or an etching back process. In some embodiments, the planarization process may include a chemical-mechanical polishing (CMP) process or a fly cutting process. In certain embodiments, after planarization, the formation of the first redistribution layer (RDL1) within the package structure100is completed. In some embodiments, after planarization, the first seed metallic layer120and the first metal layer130remained within the damascene openings DS1become the first seed metallic patterns121and dual damascene redistribution patterns131. In some embodiments, the first seed metallic pattern121is located with the damascene opening DS1, sandwiched between the dual damascene redistribution pattern131and the damascene openings DS1, and conformally covers the sidewalls and bottom surface of the damascene openings DS1. In some embodiments, the first seed metallic pattern121located with the damascene opening DS1is formed as an integral piece as the first seed metallic patterns121are formed from the same layer (first seed metallic layer120). In some embodiments, the first redistribution layer RDL1includes at least the first dielectric pattern111, the first seed metallic patterns121and the dual damascene redistribution patterns131. The first redistribution layer RDL1is electrically connected with the contacts104of the substrate102. In alternative embodiments, the first redistribution layer RDL1may include more than one dielectric patterns and various types of redistribution patterns including traces or connection lines. In exemplary embodiments, the layout of the redistribution patterns of the first redistribution layer RDL1may form fan-out routings for an integrated fan-out (InFO) package structure. In some embodiments, the dual damascene redistribution pattern131located with the damascene opening DS1includes via portions132(located within the via openings VS1) and routing portions133(located within the trench openings TS1). In some embodiments, the top surface111aof the first dielectric pattern111is coplanar with and flush with the top surfaces131aof the dual damascene redistribution patterns131. In certain embodiments, for the trench openings TS1that are not connected with the via openings VS1, after planarizing the first metal layer filling up the trench openings TS1, trace patterns (not shown) remained in the trench openings TS1are obtained. In certain embodiments, following the above process steps, the first redistribution layer is accomplished without using photolithographic processes and etching processes, thus avoiding the issues of photoresist peeling or swelling. In some embodiments, using the double exposure process described above, better pattern overlay and better pattern alignment are offered and damascene openings including via openings and trench openings are formed. In certain embodiments, through the formation of the damascene openings, filling capability of the metal layer into the damascene openings is improved and better adhesion between the damascene openings and the dual damascene redistribution patterns is provided through first seed metallic patterns121formed there-between. FIGS.8-14schematically illustrate various stages of processes for forming another redistribution layer according to a method of fabricating a semiconductor package in accordance with some embodiments. Referring toFIG.8, in some embodiments, a second dielectric material layer140may be formed on the first redistribution layer RDL1. The first redistribution layer RDL1may be formed following some or all processes as described inFIGS.1-7. In some embodiments, the second dielectric material layer140may be formed by a coating process such as a spin-coating process, or a deposition process including a CVD process. In certain embodiments, the second dielectric material layer140may be a positive type photo-sensitive material layer. In some embodiments, a material of the dielectric material layer140may be a positive photo-sensitive material, including polyimide, BCB, PBO, or any other suitable photo-sensitive polymer materials or other photoresist materials. In certain embodiments, the material of the dielectric material layer140may be positive photoresist materials. In some embodiments, the material of the second dielectric material layer140is the same as that of the first dielectric material layer110. In some embodiments, the material of the second dielectric material layer140is different from that of the first dielectric material layer110. Referring toFIG.9, a third exposure process E3is performed to the second dielectric material layer140to form third exposure portions140A. In some embodiments, the third exposure process E3is performed using a mask MK3with a third pattern PT3. In some embodiments, the third exposure portions140A are formed in the exposed regions (shown as the spotted regions) of the second dielectric material layer140exposed to the light passing through the openings PTO2. The third exposure process E3may be performed under similar or same conditions as described in the first exposure process E1, and will not repeated herein. In some embodiments, the third exposure process E3is performed with a third energy dose, and the third exposure portions140A are formed with a depth d5and a bottom size S5in the horizontal direction x (perpendicular to the thickness direction z of the second dielectric material layer140). In certain embodiments, the depth d5of the third exposure portions140A is substantially equivalent to a thickness T3of the second dielectric material layer140. In certain embodiments, the latent pattern of the third exposure portions140A includes a via-opening pattern. In accordance with the embodiments, the pattern of the third exposure portions140A is different from the pattern of the first exposure portions110A. The embodiments are intended for illustration purposes but not intended to limit the scope of the present disclosure. Referring toFIG.10, a fourth exposure process E4is performed to the second dielectric material layer140to form fourth exposure portions140B. In some embodiments, the fourth exposure process E4is performed using a mask MK4with a fourth pattern PT4. In some embodiments, the masks MK3, MK4may refer to different portions of the same mask or two masks. The fourth exposure process E4may be performed under similar or same conditions as described in the second exposure process E2, and will not repeated herein. InFIG.10, the second dielectric material layer140is partially exposed by the fourth exposure process E4, and the fourth exposure portions140B are formed in the exposed regions (shown as the spotted regions) of the second dielectric material layer140exposed to the light passing through the openings PTT2of the fourth pattern PT4. In some embodiments, the fourth exposure process E4is performed with a fourth energy dose and the fourth exposure portions140B are formed with a depth d6and a bottom size S6in the horizontal direction x (perpendicular to the thickness direction z). In certain embodiments, the depth d6of the fourth exposure portions140B is smaller than the thickness T3of the second dielectric material layer140. In certain embodiments, the depth d6of the fourth exposure portions140B is smaller than the depth d5of the third exposure portions140A. In one embodiments, the fourth energy dose is lower than the third energy dose. In some embodiments, the ratio of depth d6/d5may be about 0.4˜0.6. In some embodiments, the locations of the third exposure portions140A are overlapped with the locations of parts of the fourth exposure portions140B. In some embodiments, the latent pattern of the fourth exposure portions140B includes a trench-opening pattern. In some embodiments, the third exposure process E3and the fourth exposure process E4can be considered as another double exposure process. InFIG.11, in some embodiments, a second development process is conducted to remove at least the third and fourth exposure portions140A,140B of the second dielectric material layer140, and the second dielectric pattern141is formed. The second development process may be performed using similar or same conditions or materials as described in the first development process, and will not repeated herein. In some embodiments, the third and fourth exposure portions140A,140B may be removed simultaneously by the same development process. In certain embodiments, following the removal of at least the third and fourth exposure portions140A,140B, the trench openings TS2with a depth d8and the via openings VS2with a depth d7are formed and the second dielectric pattern141having the thickness T4is formed. In some embodiments, film loss may occur during the second development process and the thickness T4of the second dielectric pattern141is smaller than the thickness T3of the second dielectric material layer140. In certain embodiments, the trench openings TS2and the via openings VS2correspondingly and spatially communicated with the trench openings TS2constitute dual damascene openings or damascene openings DS2. In some embodiments, some of trench openings TS2are connected with some of the via openings VS2. In some embodiments, some of trench openings TS2are not connected with some of the via openings VS2. In some embodiments, other than the removal of the third and fourth exposure portions140A,140B, the second development process may include over-developing the second dielectric material layer140by removing the second dielectric material layer140excessively around the third and fourth exposure portions140A,140B to form the via openings VS2and trench openings TS2as well as the damascene openings DS2. In some embodiments, the over-developing of the second dielectric material layer140further widen the openings. In addition, a curing process may be included, and the curing of the second dielectric material layer140makes the sidewalls of the openings inclined. In some embodiments, owing to the widening effect of over-developing, the via opening VS2is formed with a bottom size S7(in the horizontal direction x) wider than the bottom size S5of the third exposure portions140A, and the trench opening TS2is formed with a bottom size S8(measuring at the depth d8in the horizontal direction x) wider than the bottom size S6of the fourth exposure portions140B. In some embodiments, the trench openings TS2, the via openings VS2and the damascene openings DS2become tapering with slanted sidewalls after the curing process. In some embodiments, the depth d7is smaller than the depth d5, while the depth d8is smaller than the depth d6. In some embodiments, the ratio of depth d8/d7may be about 0.4˜0.6. In some embodiments, the ratio of bottom sizes S7/S5ranges from 1.1 to 2. In some embodiments, the ratio of bottom sizes S8/S6ranges from 1.1 to 2. In some embodiments, the via openings VS2expose the underlying dual damascene redistribution patterns131. In some embodiments, the via opening VS2is a round shaped opening and the bottom size S7of the via opening VS2is the largest dimension or the diameter of the via opening VS2. In some embodiments, the trench opening TS2is a strip trench and the bottom size S8of the trench opening TS2is the largest dimension or the length in the length direction (marked as direction x inFIG.11). Referring toFIG.12, in some embodiments, a second seed metallic layer150is formed over the second dielectric pattern141having damascene openings DS2. In some embodiments, the second seed metallic layer150is formed conformal to the profiles of the second dielectric pattern141with damascene openings DS2, evenly covering the sidewalls and bottom surfaces of the damascene openings DS2and the top surface of the second dielectric pattern141. In certain embodiments, the second seed metallic layer150is formed by sequentially depositing or sputtering a titanium layer and a copper layer (not shown) conformal to the second dielectric pattern141and the damascene openings DS2. In one embodiment, the second seed metallic layer150covers and is in contact with the exposed surfaces of the dual damascene redistribution patterns131(i.e. bottom surfaces of the via openings VS2). Owing to the slant or inclined sidewalls of the openings TS2, VS2or DS2, better and more uniform step coverage may be achieved for the second seed metallic layer150. Hence, the reliability and electrical performance of the redistribution layer/structure are further improved. Referring toFIG.13, a second metal layer160is formed to fill up the damascene openings DS2and on the second seed metallic layer150over the second dielectric pattern141. In some embodiments, the material of the second metal layer160includes copper or copper alloys. In some embodiments, the material of the second metal layer160is the same or different from that of the first metal layer130. Referring toFIG.14, a planarization process is performed to partially remove the second metal layer160and the second seed metallic layer150above the top surface141aof the second dielectric pattern141, and second seed metallic patterns151and dual damascene redistribution patterns161filled within the damascene openings DS2are formed. In certain embodiments, after planarization, the formation of the second redistribution layer (RDL2) in the package structure100is completed. In some embodiments, the second seed metallic pattern151is located with the damascene opening DS2, sandwiched between the dual damascene redistribution pattern161and the damascene openings DS2, and conformally covers the sidewalls and bottom surface of the damascene openings DS2. In some embodiments, the second seed metallic pattern151is formed as an integral piece located with the damascene opening DS2. The second redistribution layer RDL2is disposed on the first redistribution layer RDL1and is electrically connected with the first redistribution layer RDL1. InFIG.14, the dual damascene redistribution pattern161located with the damascene opening DS2includes via portions162(located within the via openings VS2) and routing portions163(located within the trench openings TS2). FIG.15illustrates a schematic layout top view of a redistribution layer in a semiconductor package in accordance with some embodiments. InFIG.15, more than one dual damascene redistribution patterns161are shown. In some embodiments, some of the dual damascene redistribution pattern161includes two via portions162connected through the routing portion163located in-between. However, the pattern of the dual damascene redistribution pattern or the layout of the redistribution layer is not limited by the embodiments described herein. FIG.16schematically illustrates a semiconductor package having one or more redistribution layers in accordance with some embodiments. In some embodiments, after the formation of the second redistribution layer RDL2, the package structure100may undergo a dicing process and the package structure100is cut into a plurality of packages10. Referring toFIG.16, the package10includes a package subunit1500having a molding compound1560and at least one die1500and through inter-layer vias (TIVs)1520molded in the molding compound1560. In some embodiments, the first redistribution layer RDL1is disposed on the molding compound1560and on the die1510and the TIVs1520. In some embodiments, the first redistribution layer RDL1is electrically connected with the contact pads1512of the die1510and the TIVs1520. The second redistribution layer RDL2is disposed on the first redistribution layer RDL1and is electrically connected with the first redistribution layer RDL1. The structure shown inFIG.16may be formed following the processes described inFIGS.1-14, except for replacing the substrate102with the molded package subunit1500. In some embodiments, the molded package subunit1500is provided without the TIVs1520. FIGS.17-20schematically illustrate various stages of a method of fabricating a semiconductor package in accordance with some embodiments. Referring toFIG.17, a package structure200having at least a first redistribution layer RDL1, a second redistribution layer RDL2and a third redistribution layer RDL3is provided. The formation of the third redistribution layer RDL3is similar to the formation of the first redistribution layer RDL1and the second redistribution layer RDL2. In some embodiments, the third redistribution layer RDL3may be formed by forming a third dielectric pattern211, forming third seed metallic patterns220and then forming the dual damascene redistribution patterns231. Referring toFIG.18, a passivation layer240with openings S is formed over the third redistribution layer RDL3to partially expose the dual damascene redistribution patterns231. Referring toFIG.19, conductive elements250are formed on the exposed surfaces of the dual damascene redistribution patterns231within the openings S of the passivation layer240. In some embodiments, after the formation of the conductive elements250on the third redistribution layer RDL3, the package structure200may undergo a dicing process and the package structure200is cut into a plurality of packages20(only one is shown), inFIG.20. Referring toFIG.21, the package20A includes at least a first redistribution layer RDL1, a second redistribution layer RDL2and a third redistribution layer RDL3, and the redistribution layers RDL1-RDL3may be formed following the processes as described inFIGS.1-14. In some embodiments, the planarization processes performed to remove the extra first, second or third metal layer includes an etching process. Due to the etching back process(es) performed during the formation of the redistribution layers RDL1-RDL3, the top surfaces131a,161a,231aof the dual damascene redistribution patterns131,161,231are lower than the top surfaces111a,141a,211aof the dielectric patterns111,141,211. In accordance with some embodiments of the present disclosure, a semiconductor package has at least a redistribution layer located on a substrate. The redistribution layer is electrically connected with contacts of the substrate. The redistribution layer includes a dielectric pattern having a dual damascene opening and a redistribution pattern disposed within the dual damascene opening. The redistribution layer includes a seed metallic pattern sandwiched between the dual damascene opening and the redistribution pattern. In some embodiments, the etching back process (processes) may also form a rounded corner between the sidewalls of the trench openings and the top surfaces111a,141a,211aof the dielectric patterns111,141,211 In accordance with alternative embodiments of the present disclosure, a method of fabricating a semiconductor package includes at least the following steps. A substrate having at least one contact is provided and a redistribution layer is formed on the substrate. The formation of the redistribution layer includes forming a dielectric material layer over the substrate and performing a double exposure process to the dielectric material layer. A development process is then performed and a dual damascene opening is formed in the dielectric material layer. A seed metallic layer is formed over the dual damascene opening and over the dielectric material layer. A metal layer is formed over the seed metallic layer. A redistribution pattern is formed in the first dual damascene opening and is electrically connected with the at least one contact. In accordance with alternative embodiments of the present disclosure, a method of fabricating a semiconductor package includes at least the following steps. A substrate having contacts is provided. A first dielectric material layer is formed over the substrate. A first double exposure process is performed to the first dielectric material layer. A first development process is performed and a first dual damascene opening is formed in the first dielectric material layer exposing the contacts. A first seed metallic layer is formed over the first dual damascene opening and over the first dielectric material layer. A first metal layer is formed on the first seed metallic layer. A first redistribution layer having a first redistribution pattern is formed in the first dual damascene opening. A second dielectric material layer is formed over the first redistribution layer. A second double exposure process is performed to the second dielectric material layer. A second development process is performed and a second dual damascene opening is formed in the second dielectric material layer. A second seed metallic layer is formed over the second dual damascene opening and over the second dielectric material layer. A second metal layer is formed on the second seed metallic layer. A second redistribution layer having a second redistribution pattern is formed in the second dual damascene opening. In accordance with alternative embodiments of the present disclosure, a method of fabricating a redistribution layer includes at least the following steps. A substrate having contacts is provided. A dielectric material layer is formed on the substrate. A first exposure process is performed with a first energy dose to form first exposure portions with a first depth in the dielectric material layer. A second exposure process is performed with a second energy dose to form second exposure portions with a second depth in the dielectric material layer. The first depth is larger than the second depth and the first energy dose is larger than the second energy dose. The first exposure portions and second exposure portions of the dielectric material layer are removed at the same time to form via openings and trench openings respectively. A seed metallic layer is formed over the dielectric material layer and covers the via openings and trench openings. A metal layer is formed over the seed metallic layer and fills the via openings and the trench openings. The foregoing outlines features of several embodiments so that those skilled in the art may better understand the aspects of the present disclosure. Those skilled in the art should appreciate that they may readily use the present disclosure as a basis for designing or modifying other processes and structures for carrying out the same purposes and/or achieving the same advantages of the embodiments introduced herein. Those skilled in the art should also realize that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and that they may make various changes, substitutions, and alterations herein without departing from the spirit and scope of the present disclosure. | 40,912 |
11862513 | DETAILED DESCRIPTION Reference is made toFIG.1, which is a schematic cross-sectional view of a semiconductor structure. The semiconductor structure includes a medium layer11and a hard mask layer12on the medium layer. The same etching process has a relatively small etch selectivity ratio of the hard mask layer12and the medium layer11, and the hard mask layer12has a higher hardness and a larger thickness. In the process of etching the hard mask layer12to form an opening pattern13, since the hard mask layer12has a higher hardness and a larger thickness, it is easy to cause sidewalls of the opening patterns13finally formed by etching to be not perpendicular to a surface of the medium layer11. When such opening patterns13with etching defects are used for selective etching to form a plurality of discrete capacitor holes, a problem of penetration between adjacent capacitor holes may occur. Further, since the same etching process has a relatively small etch selectivity ratio of the hard mask layer12and the medium layer11, after the opening patterns13are formed by etching, excess etchant is in contact with the medium layer11, thereby causing etching by mistake of the medium layer11. The etching by mistake may cause changes in performance of the medium layer11, such as weakening of the supporting capacity, damage to electronic components inside the medium layer11, or the like. In order to solve the above-mentioned problems, the embodiments of the present disclosure provide a manufacturing method of a semiconductor structure. The difficulty of etching is adjusted by controlling the material of a sacrificial layer to ensure that first trenches formed by etching has a preset topography, so that second trenches that are formed subsequently and complementary to the first trenches and the hard mask layer that fills the second trenches have a preset topography. Further, a barrier layer formed on the substrate, which may be used as an etch stop layer, facilitates avoiding etching damage to the substrate caused by the same etching process. In order to make the objectives, technical solutions, and advantages of the embodiments of the present disclosure clearer, embodiments of the present disclosure will be described below in detail in combination with the drawings. However, those of ordinary skill in the art can understand that, in each embodiment of the present disclosure, many technical details are proposed to make readers understand the present disclosure better. However, the technical solutions claimed by the present disclosure may also be implemented even if without these technical details and various variations and modifications made based on the following embodiments. FIG.2toFIG.11are schematic diagrams of sectional structures corresponding to steps of a manufacturing method of a semiconductor structure provided in an embodiment of the present disclosure. Details are as follows. Referring toFIG.2, a substrate21is provided. A barrier layer22is formed on the substrate21. A sacrificial layer23is formed on the barrier layer22. An opening pattern244is formed over the sacrificial layer23by utilizing a photolithography process. In this embodiment, the substrate21is a multi-layer stacked structure. The multi-layer stacked structure includes a conductive structure210, a second medium layer213, a second support layer214, a first medium layer215, and a first support layer216stacked in this order in a same direction. The first support layer216and the second support layer214play a supporting role in the substrate21, to prevent the substrate21from collapsing in the process of forming capacitor holes. The conductive structure210includes an insulating medium211and conductive layers212. The material of the conductive layer212includes tungsten or tungsten compound. In this embodiment, the barrier layer22is used as an etch stop layer so that the etching process stops etching after the sacrificial layer23is penetrated and a surface of the barrier layer22is exposed, to avoid etching by mistake of the substrate21caused by the etching process and thus ensuring that the substrate21has good performance. In this embodiment, the etch selectivity ratio of the sacrificial layer23to the barrier layer22is greater than 100. The material of the sacrificial layer23includes carbon-containing materials which include organic carbide (such as resin) and inorganic carbide (such as silicon carbide). The material of the barrier layer22includes titanium nitride. In this embodiment, the hardness of the sacrificial layer is less than that of the hard mask layer formed subsequently. In this way, it is beneficial to avoid etching defects caused by too high hardness of the material. When the sacrificial layer23is etched to form trenches, it can be ensured that the formed trenches have a preset topography. In this embodiment, before the photolithography process is performed to form the opening pattern244, a pattern transfer layer24is formed on the sacrificial layer23. The pattern transfer layer24includes an isolation layer241, an anti-reflection coating layer242, and a photoresist layer243stacked in this order in a direction away from the substrate21. The isolation layer241is configured to isolate the sacrificial layer23from the photoresist layer243, to prevent a removal process of the photoresist layer243from damaging the sacrificial layer23or changing the material properties of the sacrificial layer23. The removal process of the photoresist layer243includes an ashing process, which is typically configured to remove carbides such as the organic materials. When the material of the sacrificial layer23is a carbide material that will be affected by the ashing process, the isolation layer241with a certain thickness is adopted to isolate the sacrificial layer23from the photoresist layer243, which is beneficial to avoid damage to the sacrificial layer23caused by the ashing process, removing of a portion of the sacrificial layer23or change of the material performance of the sacrificial layer23, so as to ensure that the first trench formed subsequently has a better topography. Further, when the material of the sacrificial layer23is polysilicon, the isolation layer241is adopted for isolation, which is beneficial to prevent the ashing process from oxidizing polysilicon to form silicon dioxide, thereby ensuring that the sacrificial layer23has preset physical properties, especially the hardness property. Accordingly, when the ashing process does not cause damage to the material of the sacrificial layer23and does not change the material properties of the sacrificial layer23, the isolation layer241may not be required. The material of the isolation layer241includes at least one of nitride or silicide. Referring toFIG.3, after the opening pattern244(referring toFIG.2) is formed in the photoresist layer243(referring toFIG.2), pre-openings241aare formed in the anti-reflection coating layer242and the isolation layer241according to the opening pattern244, and the photoresist layer243is removed after the pre-openings241aare formed. Since the sacrificial layer23needs to be etched subsequently to form first trenches, and the area of sidewalls of the first trench is typically larger than the area of a bottom surface of the pre-opening241a, the formation of the first trench will increase an exposed area of the sacrificial layer23. The exposed area refers to the area exposed to the air or process environment. For example, the ashing process is dry etching performed by ionizing the oxygen source gas to form oxygen plasma, and the exposed area is an area that may be contacted with the oxygen plasma or the oxygen source gas. Removing the photoresist layer243in advance enables the etchant in the removal process of the photoresist layer243to only contact the area of bottom surface of the pre-opening241a, instead of contacting the material of the sacrificial layer23at the sidewalls of the first trench. In this way, even if the etchant may damage, remove or modify the material of a portion of the sacrificial layer23at the bottom of the pre-opening241ato form a certain etching defect, this etching defect will also be subsequently eliminated when the sacrificial layer23is etched through the pre-opening241ato form the first trench, without casing the topography of the first trench formed to deviate from the preset topography due to damage to, removing of or modification of the material of the sacrificial layer23at the sidewalls of the first trench, so as to ensure that the topography of the first trench is accurate and complete. When the ashing process does not affect the sacrificial layer23and thus the isolation layer241does not need to be provided, it is possible to directly form the first trenches in the sacrificial layer23through the opening pattern244(referring toFIG.2) provided in the photoresist layer243(referring toFIG.2). Referring toFIG.4, the sacrificial layer23is etched according to the pre-openings241a(referring toFIG.3) by taking the barrier layer22as the etch stop layer, to form first trenches231. It is to be noted that when the material of the isolation layer241has a hardness greater than a hardness of the material of the sacrificial layer23, a mask-less dry process may be adopted to etch and remove a portion of the sacrificial layer23to form the first trenches231. When the mask-less dry etching process is performed, the anti-reflection coating layer242(referring toFIG.3) at a top surface of the isolation layer241will be removed. In this embodiment, the material of the sacrificial layer23is organic carbide. Typically, compared with the inorganic carbide, the organic carbide has a lower hardness, are easier to be etched, and has a better trench topography after being etched. Thus, it is beneficial to shorten the time-consuming of the process and ensure that the trench has a good topography. Referring toFIG.5, a medium layer material251is filled in each of the first trenches231(referring toFIG.3) and the isolation layer241(referring toFIG.3) is removed. In this embodiment, the photomask used for the photolithography process is an existing photomask. In a direction perpendicular to a surface of the substrate21, an orthographic projection of an opening of the existing photomask and an orthographic projection of the conductive layer212in the conductive structure210are at least partially overlapped, that is, the first trench231may be etched to form a capacitor hole exposing the conductive layer212. Therefore, in order to ensure that the capacitor hole exposing the conductive layer212can be formed by etching the hard mask layer, the medium layer material251needs to be filled in the first trench231to occupy a physical position, and the etching process is adjusted to selectively etch and remove the sacrificial layer23in a certain region, and after the sacrificial layer23is etched, the hard mask material is filled to the position in which the original sacrificial layer23is located, so that the hard mask material surrounds the medium layer material251and is filled between adjacent medium layer materials. In this way, the hard mask layer can be formed after the medium layer material251is removed, and the hard mask layer has openings that may be used for etching to form the capacitor holes. In other embodiments, the material of the hard mask layer may be directly filled in the first trenches, and the sacrificial layer is etched and removed to form the hard mask layer. It is to be noted that in order to ensure that the capacitor hole exposing the conductive layer can be etched through the opening of the hard mask layer, when this technical solution is adopted, the photomask used in the photolithography process is complementary to the existing photomask, that is, the opening positions of the photomasks are opposite. It is to be noted that when a different photomask is select to form the capacitor holes, in addition to considering the difficulty of obtaining the photomask, the etch selectivity ratio of the material of the sacrificial layer23and the hard mask material shall also be considered. When the same etching process has a small etch selectivity ratio of the material of the sacrificial layer and the hard mask material, which may damage, consume, or modify the hard mask material in the process of etching the sacrificial layer23, the existing photomask may be adopted. In this way, the medium layer material251is filled, so that the medium layer material251and the material of the sacrificial layer23have a larger etch selectivity ratio, as well as the medium layer material251and the hard mask material have a larger etch selectivity ratio, to avoid changes of the trench topography by the etching process of etching the sacrificial layer23and the medium layer material251, thereby ensuring that a plurality of discrete capacitor holes can be formed finally. In this embodiment, the first trench231may be filled with the medium layer material251first, and then the planarization process may be performed to remove the excess medium layer material251and the isolation layer241. It is also possible to remove the isolation layer241first, and then fill the first trench231with the medium layer material251and perform the planarization process. In this embodiment, the etch selectivity ratio of the medium layer material251to the barrier layer22is greater than 100. In this way, it is beneficial to prevent the barrier layer22from being etched through and ensure that the performance of the substrate21is not affected. The medium layer material251includes one of oxide or nitride, for example, one of silicon oxide, silicon nitride, or silicon oxynitride. Reference is made toFIG.6, which is a top schematic structural view of the semiconductor structure illustrated inFIG.5. The sacrificial layer23is a continuous and complete film layer. The medium layer material251is located in a plurality of through holes in the sacrificial layer23, and the arrangement pattern of the through holes is the same as the arrangement pattern of the conductive layers212. In this embodiment, the medium layer materials251in adjacent rows/columns are arranged in a staggered arrangement, accordingly the conductive layers212in adjacent rows/columns are arranged in a staggered arrangement. In this way, it is beneficial to improve the utilization of space, increase the number of through holes/conductive layers212that can be formed in the same cross-sectional area, and improve the degree of integration of the semiconductor structure. In this embodiment, the spacing between adjacent through holes is related to characteristic parameters of the capacitor to be formed later, and the characteristic parameters include the thickness of an electrode layer, the distance between the adjacent electrode layers, and whether the electrode layers are shared. When the spacing between adjacent through holes is controlled, it is necessary to not only ensure that there is a sufficient spacing to form the electrode layer, but also to ensure that the dielectric layer between the adjacent electrode layers will not be broken down or leak electricity due to being too thin, and further to ensure that the capacitance value of the capacitor formed by the electrode layer and the dielectric layer meets the preset requirements. Further, the spacing between adjacent through holes is also related to the following characteristic parameters which include: the etch selectivity ratio of the sacrificial layer23to the barrier layer22in the same etching process, the etch selectivity ratio of the medium layer material251to the barrier layer22in the same etching process, and the thickness of a pillar-shaped capacitor formed subsequently. Specifically, in the actual manufacturing process of the semiconductor structure, the same etching process has a relatively high etch selectivity ratio of other materials to the barrier layer22, which only means that the etching rate of the barrier layer22by the etchant is relatively low, but the etching will still occur. Therefore, the barrier layer22as the etch stop layer will be certainly etched during the process of etching the sacrificial layer23and the subsequently etching the medium layer material251, and as long as the etching occurs, there may be a case of etching by mistake. The degree of etching by mistake is related to the etch selectivity ratio of other materials to the barrier layer22in the same etching process, the higher the etch selectivity ratio, the lower the degree of etching by mistake. In the process of subsequently forming discrete capacitor holes, that is, in the process of etching the barrier layer22to expose the conductive layers212, the etching by mistake in the barrier layer22is gradually enlarged, so that the minimum spacing between the adjacent capacitor holes is gradually reduced. At the point, the lower the degree of etching by mistake of the barrier layer22, the larger the minimum spacing between the adjacent capacitor holes, and the higher the degree of discrete of the adjacent capacitor holes; and the thinner the pillar-shaped capacitor, the lower the degree of magnification of the etching by mistake, and the higher the degree of discrete of the adjacent capacitor holes. In this embodiment, it is necessary to control the spacing between the adjacent through-holes according to the plurality of characteristic parameters mentioned above, thereby ensuring that adjacent capacitor holes have a relatively high degree of discrete to ensure the performance of the finally formed semiconductor structure. Referring toFIG.7, the sacrificial layer23(referring toFIG.5) is etched by taking the barrier layer22as the etch stop layer, to form second trenches232. The second trench232is complementary to the first trench and configured to be filled with the hard mask material. In this embodiment, the medium layer material251and the material of the sacrificial layer23have a relatively high selectivity ratio. In this way, when the sacrificial layer23is etched, the mask-less dry etching process may be adopted to etch and remove the sacrificial layer23, without needing to provide an additional photomask and forming an additional mask layer, which is beneficial to reduce process costs and reduce process steps. Referring toFIG.8andFIG.9, the hard mask material is filled in the second trenches and configured to form a hard mask layer261. The hard mask material may be selected according to process requirements which include hardness, the etch selectivity ratio of the medium layer material251and so on. The higher the hardness of the hard mask material, the more difficult it is etched in the process of subsequently forming third grooves. In this way, the hard mask layer formed by the hard mask material may better define an etching direction of the dry etching process to ensure that sidewalls of the third grooves formed by etching are perpendicular to a top surface of the conductive structure210, so as to ensure that the capacitor holes are discrete. Accordingly, the higher the etch selectivity ratio of the medium layer material251, in the process of etching the medium layer material251to form the hard mask layer261, the smaller the damage to the hard mask material caused by the etching process, and the higher the verticality of the sidewalls of the hard mask layer261with respect to the substrate21, so that the hard mask layer261can better define the etching direction of the dry etching process, thereby ensuring the discrete of the capacitor holes. Verticality refers to the approach degree of an angle between two straight lines relative to the right angle (i.e., 90 degrees). The higher the verticality, the higher the approach degree, and the lower the verticality, the lower the approach degree. In this embodiment, the hard mask material includes polysilicon. In other embodiments, the hard mask material also includes an organic material having a relatively high hardness such as polyimide, or the like. Compared with the organic material, the polysilicon is a common material and has a low cost. Using polysilicon as the hard mask material facilitates reducing process costs. Further, since the organic material as the hard mask material and the organic carbide as the sacrificial layer material belong to carbon-containing compounds, the same etching process may have a relatively low etch selectivity ratio of the two materials, and therefore when the organic material is used as the hard mask material, and the etch selectivity ratio of the two materials is relatively low, it is suitable for forming capacitor holes by adopting the existing photomask. In this way, in the same etching process, the hard mask material and the sacrificial layer material do not exist at the same time, and the type of the medium layer material can be controlled, to increase the etch selectivity ratio of the medium layer material and the hard mask material, and the etch selectivity ratio of the medium layer material and the sacrificial layer material, thereby ensuring that the finally formed hard mask layer has a good sidewall topography, that is, the sidewalls of the hard mask layer have a higher verticality relative to the top surface of the substrate21. Accordingly, when the polysilicon is used as the hard mask material, the existing photomask may be used to form the capacitor holes, or another photomask which is complementary to the existing photomask may also be used to form the capacitor holes. When another complementary photomask is selected to form the capacitor holes, since the same etching process has relatively high etch selectivity ratio of the polysilicon and the organic carbide, it is possible to ensure that the sidewalls of the finally formed hard mask layer261have a good topography and also to reduce process steps, which facilitate shortening the process cycle. Referring toFIG.10andFIG.11, the medium layer material is etched by taking the barrier layer22as the etch stop layer to form the hard mask layer261. Referring toFIG.12, the barrier layer22, the first support layer216, the first medium layer215, the second support layer214, and the second medium layer213are etched in this order based on the hard mask layer261to form third trenches211that expose the conductive layers212. In the process of forming the third trenches211, different etchants may be selected for the material features of the objects to be etched, or the same etchant may also be selected. Specifically, since the first support layer216and the second support layer214need to perform a support function, their hardness may be typically larger than that of the materials of the first medium layer215and the second medium layer213. In the process of etching the first support layer216and the first medium layer215, different etchants having different main etching components or different concentrations of the main etching components may be selected, to etch the first support layer216and the first medium layer215respectively, thereby ensuring a relatively high etch rate of the overall etching process and shortening the process cycle. In this embodiment, the same etching process has a relatively high etch selectivity ratio of the hard mask layer261to the barrier layer22, to the first support layer216, to the first medium layer215, to the second support layer214, and to the second medium layer213. When the barrier layer22, the first support layer216, the first medium layer215, the second support layer214, and the second medium layer213are etched, the hard mask layer261can always maintain better sidewall topography. Referring toFIG.13, the etching process is adopted to remove the hard mask layer261(referring toFIG.12) and the barrier layer22(referring toFIG.12). It is to be noted that when a specific process of removing the hard mask layer261and the barrier layer22is selected, it should be considered to avoid generating a relatively large tensile stress, thereby avoiding resulting in the structure collapse or misalignment between adjacent film layers due to excessive tensile stress, so that it is ensured that the sidewalls of the third groove211have a relatively high verticality and thus the film layer with a good quality can be formed on the sidewalls and bottom of the third groove211, and the quality of the finally formed pillar-shaped capacitor structure is improved. Referring toFIG.14, a first conductive layer221is formed at the sidewalls and the bottom of the third trench211(referring toFIG.13). A portion of the first support layer, a portion of the first medium layer, a portion of the second support layer, and a portion of the second medium layer are removed. A dielectric layer231and a second conductive layer241are formed to form a pillar-shaped capacitor structure. In this embodiment, the pillar-shaped capacitor structure is a two-layered pillar-shaped capacitor structure. Since the outermost side of each two-layered pillar-shaped capacitor structure is the second conductive layer241, adjacent two-layered pillar-shaped capacitor structures may use a same outermost conductive layer. The process of forming the two-layered pillar-shaped capacitor structure includes the following steps. After the first conductive layer221is formed, all of the first support layer, the first medium layer, the second support layer, and the second medium layer between the adjacent first conductive layers221are removed to form a vacant region for providing the second conductive layer241and the dielectric layer231. In this embodiment, when all materials between the adjacent first conductive layers221are etched, the mask-less etching process may be directly adopted, and the photomask does not need to be specially provided, which is beneficial to reduce process costs. Further, a conductive material is filled into the vacant region after etching, so that the second conductive layer241that may completely surround the dielectric layer231and may be shared by the adjacent pillar-shaped capacitor structure may be formed, which facilitates the improvement of the capacitance and spatial utilization of the pillar-shaped capacitor structure. In other embodiments, it is also possible to remove a portion of the first support layer, a portion of the first medium layer, and a portion of the second support layer to form the second conductive layer that partially surrounds the dielectric layer, and/or to form the second conductive layer that may not be shared. When this type of pillar-shaped capacitor structure is adopted, other elements may be formed in the medium material that is not occupied by the second conductive layer, thereby improving the integration of the semiconductor structure. After the removal process is completed, the dielectric layers231are respectively formed at inner and outer sidewalls of the first conductive layer221. After the dielectric layers are formed, a deposition process may be adopted to simultaneously form the second conductive layers241inside the dielectric layer231and between the adjacent dielectric layers231, which shortens the process cycle of the semiconductor structure. In this embodiment, the difficulty of etching the sacrificial layer may be adjusted by controlling the material of the sacrificial layer, and the etch selectivity ratio of the medium layer material and the material of the hard mask layer may be controlled by controlling the material of the medium layer, to avoid damage of the etching process to the hard mask layer and to ensure that the finally formed hard mask layer has a good topography. Further, the barrier layer is formed on the substrate, and the arrangement of the barrier layer facilitates the avoidance of etching by mistake the substrate by the etching process. Those of ordinary skill in the art can understand that each embodiment is a specific embodiment implementing the present disclosure, and in practical applications, various variations about the form and details can be made thereto without departing from the spirit and scope of the present disclosure. Those skilled in the art may make respective alterations and modifications without departing from the spirit and scope of the present disclosure, so the scope of protection of the present disclosure is determined based on the scope defined in claims. | 28,408 |
11862514 | DETAILED DESCRIPTION OF EMBODIMENTS Hereinafter, embodiments of the inventive concepts will be described in detail with reference to the accompanying drawings. FIGS.1A to1Dare diagrams illustrating an integrated circuit device according to an embodiment of the inventive concepts. In detail,FIG.1Ais a cross-sectional view of an integrated circuit device10,FIG.1Bis an enlarged cross-sectional view of the region BB ofFIG.1A,FIG.1Cis an enlarged cross-sectional view of the region CC ofFIG.1A, andFIG.1Dis a cross-sectional view taken along the line DD ofFIG.1A. Referring toFIGS.1A to1Dtogether, the integrated circuit device10includes lower wiring structures120formed on a substrate100, an air gap AG arranged between the lower wiring structures120, a capping layer160covering an upper surface of the air gap AG, an etch stop layer170having a protrusion and recess structure, an insulating layer210covering the etch stop layer170, and/or an upper wiring structure220electrically connected to the lower wiring structure120. The substrate100may include a wafer including silicon (Si). In some embodiments, the substrate100may include a wafer including a semiconductor element such as germanium (Ge) or a compound semiconductor such as silicon carbide (SiC), gallium arsenide (GaAs), indium arsenide (InAs), and indium phosphide (InP). Moreover, the substrate100may have a silicon on insulator (SOI) structure. Furthermore, the substrate100may have a device area including a transistor TR, an active area, a field area, and the like. An interlayer dielectric101and a contact plug102penetrating therethrough may be formed on the substrate100. In some embodiments, the interlayer dielectric101may include a silicon-based insulating material such as silicon oxide, silicon nitride, and silicon oxynitride. The contact plug102may be a conductive structure including metal. This metal may include copper (Cu), tungsten (W), aluminum (Al), cobalt (Co), ruthenium (Ru), and the like. In some embodiments, the contact plug102may be electrically connected to the active area formed on the substrate100. For example, the contact plug102may be connected to a source/drain area or gate electrode of the transistor TR formed on the substrate100. A lower support layer110may be arranged on an upper surface of the substrate100. The lower support layer110may include an insulating material. Furthermore, the lower support layer110may include a material having a different etch selectivity from that of the lower wiring structure120. For example, the material of the lower support layer110may be selected from among silicon oxide, silicon nitride, silicon oxynitride, and silicon carbide. However, the material of the lower support layer110is not limited thereto. In some embodiments, the contact plug102may penetrate the lower support layer110so as to be electrically connected to the lower wiring structure120. The lower wiring structures120may be arranged on the lower support layer110. On the upper surface of the substrate100, the lower wiring structures120may be spaced apart in a first direction (X direction), may extend in a second direction (Y direction) perpendicular to the first direction (X direction), and may be substantially flush with each other in a third direction (Z direction) perpendicular to the upper surface of the substrate100. The lower wiring structures120may be spaced an equal pitch120P apart in the first direction (X direction). That is, the plurality of lower wiring structures120may have the same width120W, and the plurality of air gaps AG corresponding to a gap between adjacent lower wiring structures of the lower wiring structures120may be formed to have the same width AGW. However, embodiments are not limited thereto. The lower wiring structures120may be a conductive structure including metal. For example, the lower wiring structures120may include copper (Cu), tungsten (W), aluminum (Al), cobalt (Co), ruthenium (Ru), or a combination thereof. The lower wiring structures120may be electrically connected to the contact plug102, and the lower wiring structures120may be electrically connected to the upper wiring structure220. In some embodiments, the lower wiring structures120may include a first lower wiring structure121electrically connected to the upper wiring structure220and a second lower wiring structure122not electrically connected to the upper wiring structure220. However, this division is merely for convenience, and thus the second lower wiring structure122may also be electrically connected to the upper wiring220in another area not illustrated in the drawings. The air gap AG may be arranged between the lower wiring structures120. The air gap AG may include air having a relatively low dielectric constant. That is, since the air gap AG which includes air having a relatively low dielectric constant is formed around the lower wiring structures120, parasitic capacitance between the lower wiring structures120may be reduced and/or crosstalk between the lower wiring structures120may be reduced. As a space occupied by the air gap AG increases, the parasitic capacitance and/or crosstalk between the lower wiring structures120may further be reduced. Therefore, in some embodiments, a level of an upper surface AGS of the air gap AG may be substantially the same as a level of an upper surface120S of the lower wiring structure120. The air gap AG may be arranged so as to be completely surrounded by an insulating material. That is, the air gap AG may be sealed to have a space that is completely independent of the lower wiring structure120by an insulating barrier layer140surrounding a side surface and lower surface of the air gap AG and the capping layer160covering the upper surface AGS of the air gap AG. The insulating barrier layer140and the capping layer160may include different materials. Alternatively, the insulating barrier layer140and the capping layer160may include substantially the same materials, but may have different densities. The upper surface AGS of the air gap AG is covered with the capping layer160, and the upper surface120S of the lower wiring structure120is not covered with the capping layer160. In other words, the capping layer160may be selectively arranged only on the upper surface AGS of the air gap AG. The insulating barrier layer140may be arranged so as to surround the side surface and lower surface of the air gap AG. That is, the insulating barrier layer140may be conformally formed along the upper surface of the substrate100, a side surface of the lower support layer110, a side surface of the lower wiring structure120, and a side surface of the capping layer160. The insulating barrier layer140may not only partition a space in which the air gap AG is formed but also reduce or prevent diffusion of a metal material included in the lower wiring structure120by being formed on the side surface of the lower wiring structure120. In some embodiments, the insulating barrier layer140may include a material selected from among silicon oxide, silicon nitride, silicon oxynitride, and silicon carbide. In other embodiments, the insulating barrier layer140may include a material selected from among high density plasma (HDP) oxide, tetra ethyl ortho silicate (TEOS), plasma enhanced-TEOS (PE-TEOS), undoped silicate glass (USG), phospho silicate glass (PSG), boro silicate glass (BSG), boro phospho silicate glass (BPSG), fluoride silicate glass (FSG), spin on glass (SOG), and tonen silazene (TOSZ). The capping layer160may be arranged so as to cover the upper surface AGS of the air gap AG. The capping layer160may include a first capping layer161which conformally covers a portion of a side surface of the insulating barrier layer140and the upper surface AGS of the air gap AG and a second capping layer163which fills the first capping layer161. The first capping layer161and the second capping layer163may include different materials. Alternatively, the first capping layer161and the second capping layer163may include substantially the same materials, but may have different densities. Alternatively, the first capping layer161and the second capping layer163may include the same materials, but may be formed using different methods. In some embodiments, the capping layer160may include a material having a density that allows carbon (C) to pass through. This configuration is for providing a space through which carbon (C) that is a major material of a second sacrificial layer150(seeFIG.6D) may be smoothly discharged during a process of removing the second sacrificial layer150(seeFIG.6D) to form the air gap AG. A relationship between the capping layer160and the lower wiring structure120is described as below. The lower wiring structure120may have a first thickness120T, and the capping layer160may have a second thickness160T that is less than the first thickness120T. Furthermore, the level of the upper surface of the lower wiring structure120may be lower than the level of the upper surface of the capping layer160. That is, the lower wiring structure120and the capping layer160may be formed as a protrusion and recess structure having a height difference. The etch stop layer170may be arranged so as to conformally cover the upper surface120S of the lower wiring structure120, the side surface of the capping layer160, and the upper surface of the capping layer160. That is, the etch stop layer170may be formed to have a protrusion and recess structure. The etch stop layer170may include a material having a different etch selectivity from that of the insulating layer210. Furthermore, the material of the etch stop layer170may have a dielectric constant that is larger than that of the material of the insulating layer210. To satisfy such conditions, the material of the etch stop layer170may include a material including aluminum (Al), for example, aluminum oxide (AlxOy), aluminum nitride (AlxNy), aluminum oxynitride (AlxOyNz), or any one selected from among zirconium oxide (ZrxOy) and hafnium oxide (HfxOy). However, the material of the etch stop layer170is not limited thereto. The insulating layer210may be arranged on the etch stop layer170. A lower surface of the insulating layer210may be arranged so as to conformally cover an upper surface of the etch stop layer170. That is, the lower surface of the insulating layer210may form a protrusion and recess structure having an opposite phase to that of the protrusion and recess structure formed by the etch stop layer170. In some embodiments, the insulating layer210may include a silicon-based insulating material. For example, the insulating layer210may include a material such as plasma enhanced oxide (PEOX), TEOS, boro TEOS (B-TEOS), phosphorous TEOS (P-TEOS), boro phospho TESO (BP-TEOS), BSG, PSG, BPSG, and the like. In other embodiments, the insulating layer210may include a dielectric layer having a low dielectric constant of from about 2.2 to about 3.0, for example, a SiOC layer or SiCOH layer. However, the material of the insulating layer210is not limited thereto. The upper wiring structure220may penetrate the insulating layer210so as to be electrically connected to the lower wiring structure120. The upper wiring structure220may include a metal layer223and a conductive barrier layer221surrounding the metal layer223. The metal layer223may include copper (Cu), tungsten (W), aluminum (Al), cobalt (Co), ruthenium (Ru), or a combination thereof. Furthermore, the conductive barrier layer221may include tantalum (Ta), tantalum nitride (TaN), titanium (Ti), titanium nitride (TiN), or a combination thereof. The capping layer160and the etch stop layer170may not be formed on the upper surface120S of the lower wiring structure120connected to the upper wiring structure220. In some embodiments, the upper wiring structure220may include an upper structure and a lower structure. The upper structure may be a wiring line (not shown) extending in a direction perpendicular to the lower wiring structure120, and the lower structure may be a via arranged at a position at which the wiring line intersects with the lower wiring structure120. For convenience, only the lower structure (e.g., the via) of the upper wiring structure220is illustrated in the drawings. That is, the lower wiring structure120may correspond to a first-layer metal wiring (layer M1of an integrated circuit), the wiring line may correspond to a second-layer metal wiring (layer M2of the integrated circuit), and the lower structure may correspond to a conductive via which electrically connects between the first-layer and second-layer metal wirings. In some embodiments, the upper wiring structure220may be formed as a stair structure including a protruding portion225contacting a portion of the upper surface of the capping layer160, a side surface of the etch stop layer170, and an upper surface of the insulating barrier layer140. Furthermore, in a side cross-sectional view, the etch stop layer170may be provided in plurality such that the etch stop layers170are spaced apart with the upper wiring structure220therebetween, and side surfaces of the upper wiring structure220respectively contact side surfaces of the etch stop layers170neighboring each other. A relationship between the upper wiring structure220and the lower wiring structure120is described as below. A shortest distance between the first lower wiring structure121and the second lower wiring structure122that is closest thereto is defined as a first shortest distance MMX. Furthermore, a shortest distance between the protruding portion225, at which the upper wiring structure220covers the upper surface of the capping layer160, and the second lower wiring structure122that is closest thereto is defined as a second shortest distance VMX. In this case, the first shortest distance MMX may be less than the second shortest distance VMX. This may result from a design in which the width of the air gap AG in the first direction (X direction) is less than the thickness160T of the capping layer160in the third direction (Z direction). In general, with regard to an integrated circuit device including an ultra-micro device, when a lithography process is performed, a process margin of a lower wiring structure and an upper wiring structure is reduced, possibly causing difficulty in securing reliability. To resolve this issue, a fully aligned via (FAV) process has been proposed. The FAV process requires a process of forming a protrusion and recess structure by relatively recessing an upper surface of a lower wiring structure relative to a peripheral structure and a process of forming an etch stop layer on the formed protrusion and recess structure. These processes make it more difficult to form an air gap between adjacent lower wiring structures of lower wiring structures. To resolve this issue, the integrated circuit device10according to inventive concepts may allow the FAV process to be relatively easily used while forming the air gap AG between the lower wiring structures120, by forming the air gap AG using a sacrificial layer and forming the capping layer160having a predetermined (or alternatively, desired) thickness or more on the upper surface AGS of the air gap AG. Accordingly, the integrated circuit device10may have one or more of the following advantages. Since the air gap AG which includes air having a low dielectric constant is formed between the lower wiring structures120, parasitic capacitance between the lower wiring structures120may be reduced and/or crosstalk between the lower wiring structures120may be reduced. In addition, since the air gap AG is also formed around the first lower wiring structure121on which a via is located, reduction of the parasitic capacitance may be increased or maximized. Next, since a current leakage in a multi-layer wiring structure may be suppressed by the capping layer160, a time dependent dielectric breakdown (TDDB) of the integrated circuit device10may be reduced or prevented. Furthermore, in a situation in which a line width and pitch of the lower wiring structure120are scaled down, the capping layer160is formed thick enough to secure a separation by a predetermined (or alternatively, desired) distance between the upper wiring structure220and the lower wiring structure120. That is, when performing a lithography process for forming the upper wiring structure220, a possibility of occurrence of a short circuit between the upper wiring structure220and the neighboring lower wiring structure120may be remarkably reduced even if unexpected misalignment occurs due to an insufficient process margin. As a result, the integrated circuit device10according to the inventive concepts may have improved electrical characteristics and/or reliability. FIGS.2to4are cross-sectional views illustrating an integrated circuit device according to an embodiment of the inventive concepts. Most of the components of the integrated circuit devices20,30, and40described below and materials of the components are substantially the same as or similar to those described above with reference toFIGS.1A to1D. Thus, for convenience, the following descriptions are focused on differences between the integrated circuit device10(seeFIG.1A) described above and integrated circuit devices20,30, and40. Referring toFIG.2, the integrated circuit device20includes lower wiring structures120formed on a substrate100and having different pitches, air gaps AG arranged between the lower wiring structures120and having different widths, capping layers160covering upper surfaces of the air gaps AG and having different widths, an etch stop layer170having a protrusion and recess structure, an insulating layer210covering the etch stop layer170, and an upper wiring structure220electrically connected to the lower wiring structure120. The lower wiring structures120may be arranged on the lower support layer110. On the upper surface of the substrate100, the lower wiring structures120may be spaced apart in a first direction (X direction), may extend in a second direction (Y direction) perpendicular to the first direction (X direction), and may be substantially flush with each other in a third direction (Z direction) perpendicular to the upper surface of the substrate100. The lower wiring structures120may be spaced a first pitch120P1or a second pitch120P2apart in the first direction (X direction). The second pitch120P2may be greater than the first pitch120P1. That is, the plurality of lower wiring structures120may have the same width120W, and the plurality of air gaps AG corresponding to a gap between adjacent lower wiring structures of the lower wiring structures120may be formed to have a first width AG1W or a second width AG2W which are different from each other. However, embodiments are not limited thereto. As a space occupied by the air gaps AG increases, the parasitic capacitance and crosstalk between the lower wiring structures120may be further reduced. Thus, the air gaps AG may include a first air gap AG1having the first width AG1W and a second air gap AG2having the second width AG2W, which is larger than the first width AG1W. The air gaps AG may have a rectangular cross-section. The capping layers160may be arranged so as to cover the upper surface AGS of the air gaps AG. The capping layers160may include a first capping layer161, which conformally covers a portion of a side surface of the insulating barrier layer140and the upper surface AGS of the air gap AG, and a second capping layer163, which fills the first capping layer161. The capping layers160may have substantially the same width as the air gaps AG. That is, the width of the capping layer160covering the upper surface AGS of the first air gap AG1may be the same as the first width AG1W of the first air gap AG1, and the width of the capping layer160covering the upper surface AGS of the second air gap AG2may be the same as the second width AG2W of the second air gap AG2. As a result, since the air gaps AG may also be formed between the lower wiring structures120having different pitches (multiple pitches) in the integrated circuit device20according to the inventive concepts, the integrated circuit device20may have improved electrical characteristics and/or reliability. Referring toFIG.3, the integrated circuit device30includes lower wiring structures120formed on a substrate100, air gaps AG3arranged between the lower wiring structures120and having an upper surface lower than an upper surfaces of the lower wiring structures120, capping layers160covering the upper surfaces of the air gaps AG3, an etch stop layer170having a protrusion and recess structure, an insulating layer210covering the etch stop layer170, and an upper wiring structure220electrically connected to the lower wiring structure120. The air gaps AG3may be arranged between the lower wiring structures120. Since the air gaps AG3, which include air having a low dielectric constant are formed around the lower wiring structures120, parasitic capacitance between the lower wiring structures120may be reduced and/or crosstalk between the lower wiring structures120may be reduced. As a space occupied by the air gaps AG3increases, the parasitic capacitance and crosstalk between the lower wiring structures120may be further reduced. However, in this case, since structural stability may decrease, the space occupied by the air gaps AG3may be adjusted considering the relationships with other components. Therefore, in some embodiments, the level of the upper surface AGS of the air gap AG3may be formed lower than the level of the upper surface120S of the lower wiring structure120. The air gaps AG3may have a rectangular cross-section. A relationship between the capping layer160and the lower wiring structure120is described as below. The level of the upper surface of the lower wiring structure120may be lower than the level of the upper surface of the capping layer160. Furthermore, the level of the upper surface of the lower wiring structure120may be higher than the level of the lower surface of the capping layer160. That is, the side surface of the lower wiring structure120and the side surface of the capping layer160may have areas facing each other. As a result, since the air gaps AG3having structural stability may be formed between the lower wiring structures120in the integrated circuit device30according to the inventive concepts, the integrated circuit device30may have improved electrical characteristics and/or reliability. Referring toFIG.4, the integrated circuit device40includes lower wiring structures120formed on a substrate100, air gaps AG4arranged between the lower wiring structures120and having an upper surface higher than an upper surfaces of the lower wiring structures120, capping layers160covering the upper surfaces of the air gaps AG4, an etch stop layer170having a protrusion and recess structure, an insulating layer210covering the etch stop layer170, and an upper wiring structure220electrically connected to the lower wiring structure120. The air gaps AG4may be arranged between the lower wiring structures120. Since the air gaps AG4, which include air having a relatively low dielectric constant are formed around the lower wiring structures120, parasitic capacitance between the lower wiring structures120may be reduced and/or crosstalk between the lower wiring structures120may be reduced. As a space occupied by the air gaps AG4increases, the parasitic capacitance and crosstalk between the lower wiring structures120may further reduce. Therefore, in some embodiments, the level of the upper surface AGS of the air gap AG4may be formed higher than the level of the upper surface120S of the lower wiring structure120. The air gaps AG4may have a rectangular cross-section. A relationship between the capping layer160and the lower wiring structure120is described as below. The level of the upper surface of the lower wiring structure120may be lower than the level of the upper surface of the capping layer160. Furthermore, the level of the upper surface of the lower wiring structure120may be lower than the level of the lower surface of the capping layer160. That is, the side surface of the lower wiring structure120and the side surface of the capping layer160may not have areas facing each other. As a result, since a space occupied by the air gaps AG4may be relatively large in the integrated circuit device40according to the inventive concepts, reduction of parasitic capacitance may be increased or maximized, thus improving electrical characteristics and/or reliability. FIG.5is a block diagram illustrating a method of manufacturing an integrated circuit device according to an embodiment of the inventive concepts. Referring toFIG.5, a method of manufacturing an integrated circuit device (S10) includes a first process of forming a lower wiring structure and a first sacrificial pattern (S110), a second process of conformally forming an insulating barrier layer forming layer (S120), a third process of forming a second sacrificial layer (S130), a fourth process of forming a capping layer forming layer (S140), a fifth process of polishing the capping layer forming layer and the insulating barrier layer forming layer (S150), a sixth process of forming an air gap by removing the first sacrificial pattern and the second sacrificial layer (S160), a seventh process of conformally forming an etch stop layer (S170), an eighth process of forming an insulating layer (S180), and a ninth process of forming an upper wiring structure penetrating the insulating layer (S190). The method of manufacturing an integrated circuit device (S10) may include the above processes S110to S190. In the case where some embodiments are differently implementable, particular processes may be performed in a different sequence from that described herein. For example, two processes described as being performed successively may be performed simultaneously, or may be performed in a reverse sequence to that described herein. Technical features related to the first to ninth processes S110to S190will be described in detail with reference toFIGS.6A to6L. FIGS.6A to6Lare cross-sectional views illustrating, according to a sequence of processes, a method of manufacturing an integrated circuit device according an embodiment of the inventive concepts. Referring toFIG.6A, a lower support layer forming layer110L, a lower wiring structure forming layer120L, a first sacrificial layer130L, and a first mask pattern M1are sequentially formed on a substrate100. The lower support layer forming layer110L may be formed on the substrate100. The lower support layer forming layer110L may include a material having a different etch selectivity from that of the lower wiring structure forming layer120L. For example, the material of the lower support layer forming layer110L may be selected from among silicon oxide, silicon nitride, silicon oxynitride, and silicon carbide. The lower wiring structure forming layer120L may be formed on the lower support layer forming layer110L. The lower wiring structure forming layer120L may include copper (Cu), tungsten (W), aluminum (Al), cobalt (Co), ruthenium (Ru), or a combination thereof. The first sacrificial layer130L may be formed on the lower wiring structure forming layer120L. A material of the first sacrificial layer130L may include an insulating material. For example, a material such as BPSG, SOG, PSG, TEOS, PE-TEOS, or the like may be used in the first sacrificial layer130L. The first mask pattern M1is formed on the first sacrificial layer130L through a lithography process. The first mask pattern M1may be photoresist or a hardmask. When the air gap AG (seeFIG.6H) is formed by the first mask pattern M1, a first open area M1H may be defined. Furthermore, an anti-reflective coating (ARC) (not shown) may be formed on the first sacrificial layer130L. Referring toFIG.6B, the first sacrificial layer130L (seeFIG.6A), the lower wiring structure forming layer120L (seeFIG.6A), and the lower support layer forming layer110L (seeFIG.6A) are sequentially etched using the first mask pattern M1(seeFIG.6A) as an etching mask, and the first mask pattern M1(seeFIG.6A) is removed. Through the etching process, a plurality of first holes120H may be formed, and the upper surface of the substrate100may be exposed through the first holes120H. Moreover, through the etching process, the first sacrificial layer130L (seeFIG.6A) becomes the first sacrificial pattern130, the lower wiring structure forming layer120L (seeFIG.6A) becomes the lower wiring structure120, and the lower support layer forming layer110L (seeFIG.6A) becomes the lower support layer110. In some embodiments, the plurality of lower wiring structures120may have the same width120W. In the case where the etching process is a dry etching process, the plurality of first holes120H may be tapered so that a lower line width thereof is less than an upper line width thereof. However, for convenience, the first holes120H are illustrated as being vertically straight in the drawings. Referring toFIG.6C, an insulating barrier layer forming layer140L is conformally formed on a whole surface of a resultant structure of the etching process. The insulating barrier layer forming layer140L may be conformally formed along the upper surface of the substrate100, a side surface of the lower support layer110, a side surface of the lower wiring structure120, a side surface of the first sacrificial pattern130, and an upper surface of the first sacrificial pattern130. Therefore, the insulating barrier layer forming layer140L may prevent diffusion of a metal material included in the lower wiring structure120. The insulating barrier layer forming layer140L may include a material selected from among silicon oxide, silicon nitride, silicon oxynitride, and silicon carbide. Alternatively, the insulating barrier layer forming layer140L may include a material selected from among HDP oxide, TEOS, PE-TEOS, USG, PSG, BSG, BPSG, FSG, SOG, and TOSZ. The insulating barrier layer forming layer140L may be formed through chemical vapor deposition (CVD) or atomic layer deposition (ALD). Referring toFIG.6D, the second sacrificial layer150, which partially fills each of the plurality of first holes120H, is formed. The second sacrificial layer150may be formed as a carbon-containing layer. The carbon-containing layer may be a spin on hardmask (SOH) or amorphous carbon layer (ACL). In some embodiments, the carbon-containing layer may be a heat eliminable polymer (HELP) removable through a thermal process. However, the material of the second sacrificial layer150is not limited thereto. A spin coating or chemical vapor deposition process may be used to form the second sacrificial layer150. Examples of processes for forming the second sacrificial layer150are described below. The second sacrificial layer150, which fully fills each of the plurality of first holes120H, is formed. Next, an etching process may be performed by recessing an upper surface of the second sacrificial layer150so that the level of the upper surface of the lower wiring structure120is substantially the same as the level of the upper surface of the second sacrificial layer150. Accordingly, the second sacrificial layer150, which partially fills each of the plurality of first holes120H, is formed. In other embodiments, the level of the upper surface of the second sacrificial layer150may be different from that illustrated in the drawings. That is, the level of the upper surface of the second sacrificial layer150may be higher or lower than the level of the upper surface of the lower wiring structure120. Referring toFIG.6E, a capping layer forming layer160L is formed on an exposed upper surface of the second sacrificial layer150and the insulating barrier layer forming layer140L. The capping layer forming layer160L may include a first capping layer forming layer161L and a second capping layer forming layer163L. In more detail, the first capping layer forming layer161L is conformally formed on the upper surface of the second sacrificial layer150, a side surface of the insulating barrier layer forming layer140L, and an upper surface of the insulating barrier layer forming layer140L, and the second capping layer forming layer163L is formed on the first capping layer forming layer161L. The first capping layer forming layer161L and the second capping layer forming layer163L may include different materials. Alternatively, the first capping layer forming layer161L and the second capping layer forming layer163L may include substantially the same materials, but may have different densities. Alternatively, the first capping layer forming layer161L and the second capping layer forming layer163L may include the same materials, but may be formed using different methods. For example, the first capping layer forming layer161L may be formed through atomic layer deposition, whereas the second capping layer forming layer163L may be formed through chemical vapor deposition. However, forming methods are not limited thereto. Referring toFIG.6F, the capping layer forming layer160L (seeFIG.6E) and the insulating barrier layer forming layer140L (seeFIG.6E) are etched so that the upper surface of the first sacrificial pattern130is exposed. This etching process (or polishing process) may be a chemical mechanical polishing (CMP) process or an etch-back process. Through the etching process, the upper surface of the first sacrificial pattern130is completely exposed. Moreover, through the etching process, the insulating barrier layer forming layer140L (seeFIG.6E) becomes the insulating barrier layer140, and the capping layer forming layer160L (seeFIG.6E) becomes the capping layer160. Furthermore, through the etching process, the second capping layer163remains only in the first capping layer161. As a result, the capping layer160may be formed only on the upper surface of the second sacrificial layer150. Referring toFIG.6G, the upper surface of the lower wiring structure120is exposed by completely removing the first sacrificial pattern130(seeFIG.6F). An etching process may vary according to a constituent material of the first sacrificial pattern130(seeFIG.6F). For example, when the first sacrificial pattern130(seeFIG.6F) is silicon oxide or silicon nitride, the first sacrificial pattern130(seeFIG.6F) may be removed through dry etching. During a process of removing the first sacrificial pattern130(seeFIG.6F), as a thickness proportion occupied by the first sacrificial pattern130(seeFIG.6F) and a density of the constituent material thereof increase, influence of the removing process on other components may increase. Therefore, removal of the first sacrificial pattern130(seeFIG.6F) may be performed under a condition in which influence of the removal on the lower wiring structure120and the insulating barrier layer140is suppressed. Referring toFIG.6H, the second sacrificial layer150(seeFIG.6G) is entirely removed, and an air gap AG is formed in a location from which the second sacrificial layer150has been removed. An etching process may vary according to a constituent material of the second sacrificial layer150(seeFIG.6G). For example, when the second sacrificial layer150(seeFIG.6G) is a carbon-containing layer, the second sacrificial layer150(seeFIG.6G) may be removed through an ashing process. During a process of removing the second sacrificial layer150(seeFIG.6G), as a thickness proportion occupied by the second sacrificial layer150(seeFIG.6G) and a density of the constituent material thereof increase, influence of the removing process on other components may increase. Therefore, removal of the second sacrificial layer150(seeFIG.6G) may be performed under a condition in which influence of the removal on the lower wiring structure120and the insulating barrier layer140is suppressed. Here, the capping layer160may include a material having a density that allows carbon (C) to pass through. This configuration is for providing a space through which carbon (C) that is a major material of the second sacrificial layer150(seeFIG.6G) may be smoothly discharged during the ashing process for removing the second sacrificial layer150. Referring toFIG.6I, the etch stop layer170is formed to conformally cover the upper surface of the lower wiring structure120, the insulating barrier layer140, and the capping layer160. The etch stop layer170may be formed to have a protrusion and recess structure. That is, the etch stop layer170may form a protrusion and recess structure having the same phase as the protrusion and recess structure formed by the lower wiring structure120and the capping layer160. The material of the etch stop layer170may include a material including aluminum (Al), for example, aluminum oxide (AlxOy), aluminum nitride (AlxNy), aluminum oxynitride (AlxOyNz), or any one selected from among zirconium oxide (ZrxOy) and hafnium oxide (HfxOy). However, the material of the etch stop layer170is not limited thereto. Referring toFIG.6J, an insulating layer210is formed to cover the etch stop layer170, and a second mask pattern M2is formed on the insulating layer210. The insulating layer210is formed so that a lower surface thereof covers the upper surface of the etch stop layer170. Therefore, the lower surface of the insulating layer210may form a protrusion and recess structure having an opposite phase to that of the protrusion and recess structure of the etch stop layer170. The second mask pattern M2is formed on the insulating layer210through a lithography process. The second mask pattern M2is formed by applying photoresist and patterning the photoresist through exposure and development. Here, when the upper wiring structure220(seeFIG.1A) is formed by the second mask pattern M2, a second open area M2H may be defined. Referring toFIG.6K, the insulating layer210is etched using the second mask pattern M2as an etching mask. The etch stop layer170is enabled to stop the etching process by adjusting an etching condition. Therefore, the etching process may be performed so that the upper surface of the etch stop layer170is exposed. That is, a first groove210H1may be formed in the insulating layer210. The etching process for the insulating layer210may be a dry etching process. Thereafter, the second mask pattern M2may be removed using an ashing and strip process. The process of removing the second mask pattern M2may be performed under a condition in which damage to the insulating layer210and the etch stop layer170is suppressed. Referring toFIG.6L, an exposed portion of the etch stop layer170is etched using the insulating layer210as an etching mask. An etching condition may be adjusted so as to only etch the exposed portion of the etch stop layer170without etching the insulating layer210, the insulating barrier layer140, and the capping layer160. Therefore, the etching process may be performed so that the upper surface of the insulating barrier layer140and a portion of the capping layer160are exposed. That is, a second groove210H2may be formed in the insulating layer210. The etching process for the exposed portion of the etch stop layer170may be a wet etching process. Referring back to FIG. IA, the conductive barrier layer221is formed on an inner wall of the second groove210H2, and the metal layer223filling the second groove210H2is formed on the conductive barrier layer221. The conductive barrier layer221may be conformally formed to cover the insulating layer210, the insulating barrier layer140, and the capping layer160exposed in the second groove210H2. The metal layer223filling the second groove210H2is formed on the conductive barrier layer221. Thereafter, a resultant structure including the conductive barrier layer221and the metal layer223are polished through a chemical mechanical polishing process so that an upper surface of the insulating layer210is exposed so that the conductive barrier layer221and the metal layer223remain only in the second groove210H2. As a result, the upper wiring structure220, which fills the second groove210H2and is electrically connected to the lower wiring structure120, may be formed. The integrated circuit device10according to the inventive concepts may be manufactured through the above-mentioned manufacturing processes, and the integrated circuit device10may have improved electrical characteristics and reliability. FIG.7is a configuration diagram illustrating a system of an integrated circuit device according to an embodiment of the inventive concepts. Referring toFIG.7, a system1000includes a controller1010, an input/output device1020, a memory1030, an interface1040, and a bus1050. The system1000may be a mobile system or a system for transmitting or receiving information. In some embodiments, the mobile system may be a portable computer, a tablet, a mobile phone, a digital music player, a memory card, or the like. The controller1010, which controls a running program in the system1000, may include a microprocessor, a digital signal processor, a microcontroller, or a similar device. The controller1010may implemented with processing circuitry such as hardware including logic circuits; a hardware/software combination such as a processor executing software; or a combination thereof. For example, the processing circuitry more specifically may include, but is not limited to, a central processing unit (CPU), an arithmetic logic unit (ALU), a digital signal processor, a microcomputer, a field programmable gate array (FPGA), a System-on-Chip (SoC), a programmable logic unit, a microprocessor, application-specific integrated circuit (ASIC), etc. The input/output device1020may be used to input or output data of the system1000. The system1000may be connected to an external device, such as a computer or a network through the input/output device1020, and may exchange data with the external device. The input/output device1020may be, for example, a touchpad, a keyboard, a mouse, or a display. The memory1030may store data for operating the controller1010, or may store data processed by the controller1010. The memory1030may include any one of the integrated circuit devices10to40according to the inventive concepts, described above with reference toFIGS.1A to4. The interface1040may be a data transfer path between the system1000and an external device. The controller1010, the input/output device1020, the memory1030, and the interface1040may communicate with each other via the bus1050. While the inventive concepts have been particularly shown and described with reference to embodiments thereof, it will be understood that various changes in form and details may be made therein without departing from the spirit and scope of the following claims. | 42,842 |
11862515 | DETAILED DESCRIPTION The following disclosure provides many different embodiments, or examples, for implementing different features of the provided subject matter. Specific examples of components and arrangements are described below to simplify the present disclosure. These are, of course, merely examples and are not intended to be limiting. For example, the formation of a first feature over or on a second feature in the description that follows may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features may be formed between the first and second features, such that the first and second features may not be in direct contact. In addition, the present disclosure may repeat reference numerals and/or letters in the various examples. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed. Further, spatially relative terms, such as “beneath,” “below,” “lower,” “above,” “upper” and the like, may be used herein for ease of description to describe one element or feature's relationship to another element(s) or feature(s) as illustrated in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The apparatus may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein may likewise be interpreted accordingly. Multi-dimensional integrated chips are formed by stacking a plurality of integrated chips onto one another. During a typical multi-dimensional integrated chip fabrication process a first wafer—a so called “carrier wafer”—is bonded to a second wafer. The carrier wafer is a wafer that has a sufficient thickness to provide mechanical support to the second wafer. After bonding, the second wafer is subsequently thinned to reduce a thickness of the second wafer. Whether before or after bonding, the outer edge of the first and/or second wafers typically have a circular shape as viewed from above, and have a rounded outer edge as viewed in cross section. As the wafer is thinned, it becomes thinner along the outer edge than in central regions due to the rounded shape. The resulting outer edge has a sharp edge and low mechanical integrity, which can lead to chipping or flaking if the wafer is subsequently grinded down. To prevent such damage to the wafer, edge trimming may be performed. Edge trimming is a process by which an outer edge of the wafer is removed or trimmed. By trimming an outer edge of the wafer, the rounded edge is removed and damage during the grinding process is mitigated. However, it has been appreciated that trimming the edge of the wafer and/or forming metals, such as forming copper on the wafer through an electrochemical plating process, can leave metal residue on the wafer. This metal residue can lead to risk of arcing, for example during a high power process (e.g., high power etch, thinning of film, or chemical vapor deposition). If arcing occurs, it can damage one or more chips included on the wafer, thereby reducing the yield. The present disclosure relates to techniques that employ a capping dielectric structure to cover areas where metal residue may be present. For example, in some embodiments, the metal residue and the capping dielectric structure are formed only on the wafer edge. For instance, for a 300 mm wafer having a radius of 150 mm, the metal residue and capping dielectric structure may be formed only on the outermost 4 mm, and may not cover the inner central portion (e.g., remaining radius 146 mm) of the wafer. This capping dielectric structure prevents or limits the risk of arcing during processing, and thereby improves the overall yield compared to previous approaches. In other embodiments, the capping dielectric structure and/or metal residue may cover the entire upper surface of the wafer. FIGS.1A-1B, which are now described concurrently, depict a top view and cross-sectional view of a semiconductor wafer structure100in accordance with some embodiments. As shown inFIG.1B, the semiconductor wafer structure100includes a semiconductor wafer substrate101including an upper face101U and a lower face101L whose outermost extents are circumferentially bounded by a circumferential edge region112. Dies (e.g.,107a,107b) including active and/or passive circuitry are arranged in grid-like fashion on the wafer, and are separated by scribe lines (e.g.,111). The circumferential edge region112includes an upper bevel region102extending between the upper face101U and an outermost edge105of the circumferential edge region and a lower bevel region106extending between the outermost edge105of the circumferential edge region and the lower face101L. In some instances, the upper bevel region102and lower bevel region106have the same radius of curvature, though in some cases the upper bevel region102is truncated in height relative to the lower bevel region106. This difference in height can arise, for example, when the upper bevel region102and lower bevel region106start with equal heights and equal radii of curvatures, and an edge trimming operation is carried out on the upper bevel region102(and not on the lower bevel region106) during processing, for example. This gives rise to a recessed sidewall101s, which surrounds a central region104corresponding to a central upper surface region101UC of the substrate. In some embodiments, the recessed sidewall101smay have a first depth that is equal to a difference in height between101UC and101UP. In some embodiments, the first depth may greater than or equal to approximately 20 microns. A plurality of transistor devices103can be disposed within the central upper surface region101UC of the semiconductor wafer substrate101, and an interconnect structure114is disposed over the central upper surface region101UC. In some embodiments, the interconnect structure114may comprise a dielectric structure including a plurality of stacked inter-level dielectric (ILD) layers106a-106e. In some embodiments (not shown), the plurality of stacked ILD layers106a-106emay be vertically separated from one another by etch stop layers. In some embodiments, one or more of the plurality of stacked ILD layers106a-106emay comprise a low-k dielectric layer (i.e., a dielectric layer having a dielectric constant that is less than that of silicon dioxide). In some embodiments, the plurality of stacked ILD layers106a-106emay comprise one or more of silicon dioxide, doped silicon dioxide (e.g., carbon doped silicon dioxide), silicon oxynitride, borosilicate glass (BSG), phosphoric silicate glass (PSG), borophosphosilicate glass (BPSG), fluorinated silicate glass (FSG), or the like. A plurality of conductive interconnect layers108are disposed within the dielectric structure over the upper surface of the semiconductor wafer substrate101. The plurality of conductive interconnect layers108are electrically coupled to the plurality of transistor devices103. In some embodiments, the plurality of conductive interconnect layers108may comprise conductive contacts108a, interconnect wires108b, and interconnect vias108c. In some embodiments, the plurality of conductive interconnect layers108may comprise copper, tungsten, aluminum, and/or the like. A metal layer109is disposed over at least a portion of the circumferential edge region112over the conductive interconnect layers108. In some cases, the metal layer109can be only over the circumferential edge region112and not over the central region104, while in other embodiments the metal layer109can extend fully over the central region104as well as circumferential edge region112. Further, in some cases, the metal layer109can extend along a sidewall of the interconnect structure114and/or a top surface of the interconnect structure114and/or the peripheral upper face region101UP of the substrate101. In some embodiments, a second semiconductor wafer116can be disposed over the interconnect structure114. Absent countermeasures, the metal layer109(which can be a residue that arises from edge trimming, an etching process, an electrochemical plating process, and/or another plating process), provides a potential pathway for high energy arcing that can damage the semiconductor wafer structure100. The metal layer can comprise copper in some embodiments. To prevent and/or limit the risk of such arcing, a dielectric capping structure110covers an upper surface of the metal layer109over at least the portion of the circumferential edge region112, but does not cover the lower face101L and does not directly cover a central upper surface region101UC over the interconnect structure114. Note that in some cases, the circumferential edge region112may correspond to an innermost edge of the dielectric capping structure110, while in other cases the circumferential edge region112′ may correspond to the recessed sidewall101sin the upper face of the wafer. In some embodiments, the dielectric capping structure110is formed by a low-power process, and comprises silicon oxynitride, silicon nitride, silicon carbide, silicon dioxide, and/or un-doped silicate glass (USG) for example. In some embodiments, the capping dielectric structure110is formed only on the peripheral region112of the wafer. For instance, for a 300 mm wafer having a radius of 150 mm, the capping dielectric structure110may be formed only on the outermost 4 mm, or somewhere between the outermost 3 mm and the outermost 20 mm, and may not cover the central region104(e.g., remaining radius 146 mm) of the wafer. This capping dielectric structure110prevents or limits the risk of arcing during processing, and thereby improves the overall yield compared to previous approaches. In other embodiments, the capping dielectric structure110may cover the entire upper surface of the wafer. In some cases, the second substrate116can separate an upper face of the interconnect structure114from the metal layer109and/or the dielectric capping structure110. In other embodiments, the second semiconductor wafer116can be omitted, such that the metal layer109and/or dielectric capping structure110directly contact the upper face101U (e.g., peripheral upper face region101UP) and/or a sidewall of the interconnect structure114and/or a top surface of the interconnect structure114. Still further, thoughFIG.1Billustrates an example where the dielectric capping structure110is a single conformal layer, in other examples the dielectric capping structure110may include multiple layers, and these layers can be conformal and/or non-conformal. FIG.2illustrates another embodiment where the dielectric capping structure110has a laminated structure made up of multiple layers. Thus, inFIG.2's example, the dielectric capping structure110includes a first dielectric layer110a, and a second dielectric layer110bthat can have a different material composition and/or structure from the first dielectric layer110a. In some cases, the dielectric layers of the laminated structure can include inner sidewalls that are aligned with one another. In some embodiments, the first dielectric layer110acomprises silicon oxynitride, silicon nitride, silicon carbide, silicon dioxide, and/or un-doped silicate glass (USG) for example. Further, the second dielectric layer110bcan comprise silicon nitride (SixNy) or silicon oxynitride (SixOyNz), for example. It will be appreciated thatFIG.2is merely a non-limiting example, and in other embodiments, the laminated structure can include additional layers. FIG.3illustrates another embodiment where the metal layer109extends fully over the upper surface of the wafer and along sidewalls of the interconnect structure114. The dielectric capping structure110extends fully over the upper surface of the metal layer109and along sidewalls of the metal layer109to limit and/or prevent arcing during processing. FIG.4illustrates another embodiment where the metal layer109covers only the peripheral upper surface regions of the interconnect structure114, sidewalls of the interconnect structure114, and the peripheral upper surface region112of the substrate. Thus, inFIG.4, the metal layer109does not cover a central upper surface region104over the interconnect structure. The dielectric capping structure110extends fully over the metal residue layer109, and may have an outer edge that contacts the upper bevel region of the substrate to encapsulate the metal residue109, thereby further limiting arcing during processing. In contrast toFIGS.1-4, which each depicted a substrate101and interconnect structure114that had undergone an edge trimming operation prior to the formation of the dielectric capping structure,FIG.5depicts an embodiment where an interconnect structure114has been formed over the wafer without the use of an edge trimming operation. Thus, inFIG.5, the substrate101includes a lower bevel region106as well as an upper bevel region102that are fully intact. The interconnect structure114is disposed over the upper bevel region102of the substrate, and the metal residue109is disposed over the dielectric material of the interconnect structure. The dielectric capping structure110then surrounds the metal residue109; such that the metal residue109and the dielectric capping structure110have cross-sections that each takes the form of a bevel with rounded edges. FIG.6illustrates a cross-sectional view of some embodiments of a multi-dimensional integrated chip structure having one or more dielectric capping structures. The multi-dimensional integrated chip structure comprises a first tier202aand a second tier202b. The first tier202acomprises a first semiconductor substrate101ahaving a central region104surrounded by a peripheral region112. The central region104is defined by an upper surface101uof the first semiconductor substrate101a. The peripheral region112is defined by a location where an outer sidewall101sof the first semiconductor substrate101ameets a recessed surface of the first semiconductor substrate101a. The first tier202afurther comprises a first interconnect structure114. A metal residue layer109and capping dielectric structure110are present along sidewalls of the first interconnect structure114. The second tier202bcomprises a second interconnect structure214on a front-side of a second semiconductor substrate101b. The first interconnect structure114is bonded to the second interconnect structure214. A second dielectric capping structure160is disposed on a recessed surface of the second semiconductor substrate101band along the outer sidewall102sof the recessed portion of the second semiconductor substrate101b, along an outer sidewall of the second interconnect structure214, along an outer sidewall of the first dielectric capping structure110, and along an outer sidewall and over an upper surface (backside) of the first semiconductor substrate101a. In some embodiments, the first dielectric capping structure110comprises silicon oxynitride, silicon nitride, silicon carbide, silicon dioxide, and/or un-doped silicate glass (USG) for example; and the second dielectric capping structure160comprises silicon oxynitride, silicon nitride, silicon carbide, silicon dioxide, and/or un-doped silicate glass (USG) for example. The first dielectric capping structure110can have the same material composition as the second dielectric capping structure160, or can have a different material composition from the second dielectric capping structure160, depending on the implementation. FIG.7illustrates a cross-sectional view of some embodiments of a multi-dimensional integrated chip structure having one or more dielectric capping structures, including a second dielectric capping structure170. In contrast toFIG.6, the second dielectric capping structure170inFIG.1is contained entirely between outermost edges of the first semiconductor substrate101aand second semiconductor substrate101b, and does not extend past an upper or lower surface of the first semiconductor substrate101aor second semiconductor substrate101b. As withFIG.6, the first dielectric capping structure110can have the same material composition as the second dielectric capping structure170, or can have a different material composition from the second dielectric capping structure170, depending on the implementation. In some embodiments, the first dielectric capping structure110comprises silicon oxynitride, silicon nitride, silicon carbide, silicon dioxide, and/or un-doped silicate glass (USG) for example; and the second dielectric capping structure170comprises silicon oxynitride, silicon nitride, silicon carbide, silicon dioxide, and/or un-doped silicate glass (USG) for example. FIGS.8-15illustrate cross-sectional views800-1500of some embodiments of various methods of forming an integrated chip structure having one or more dielectric capping structure(s). AlthoughFIGS.8-15are described in relation to various methods, it will be appreciated that the structures disclosed inFIGS.8-15are not limited to such methods, but instead may stand alone as structures independent of the methods. As shown in cross-sectional view800ofFIG.8, one or more transistor devices103are formed within a first semiconductor substrate101a. In various embodiments, the first semiconductor substrate101amay be any type of semiconductor body (e.g., silicon, SiGe, SOI, etc.), such as a semiconductor wafer and/or one or more die on a wafer, as well as any other type of semiconductor and/or epitaxial layers, associated therewith. In some embodiments, the transistor devices103may comprise a transistor formed by depositing a gate dielectric film and a gate electrode film over the first semiconductor substrate101a. The gate dielectric film and the gate electrode film are subsequently patterned to form a gate dielectric and a gate electrode. The first semiconductor substrate101amay be subsequently implanted to form a source region and a drain region within the first semiconductor substrate101aon opposing sides of the gate electrode. After formation of the transistor devices103, a first interconnect structure114is formed over an upper surface101uof the first semiconductor substrate101a. The first interconnect structure114comprises a dielectric structure having one or more stacked ILD layers106a-106drespectively surrounding one or more conductive interconnect layers108. In some embodiments, the first interconnect structure114may be formed by forming an ILD layer over the first semiconductor substrate101, selectively etching the ILD layer (e.g., an oxide, a low-k dielectric, or an ultra low-k dielectric) to define a via hole and/or a trench within the ILD layer, forming a conductive material (e.g., copper, aluminum, etc.) within the via hole and/or a trench to fill the opening, and performing a planarization process (e.g., a chemical mechanical planarization process). In some embodiments, the ILD layer may comprise one or more of silicon dioxide, doped silicon dioxide (e.g., carbon doped silicon dioxide), silicon oxynitride, borosilicate glass (BSG), phosphoric silicate glass (PSG), borophosphosilicate glass (BPSG), fluorinated silicate glass (FSG), or the like. Subsequent ILD layers are then formed in turn, and via openings and metal line/wiring openings are formed within each ILD layer. A metal (e.g.,108) is then deposited over the entire surface of a given ILD layer to fill the via openings and metal line/wiring openings. As shown in cross-sectional view900ofFIG.9, an edge trimming process is then performed. The edge trimming process removes parts of the first semiconductor substrate101aand the first interconnect structure114along a perimeter of the first semiconductor substrate101a. By removing parts of the first semiconductor substrate101, the edge trimming process defines a central region104and a recessed peripheral region112of the first semiconductor substrate101a. In some embodiments, the recessed region peripheral112is defined by a recessed surface coupled to the upper surface101uby an outer sidewall101sof the first semiconductor substrate101a. In some embodiments, the edge trimming process may be performed by bringing a blade902into contact with the first semiconductor substrate101aand the first interconnect structure114along a closed loop that extends along a perimeter of the first semiconductor substrate101a. The blade902has abrasive elements904(e.g., diamond particles) bonded to a core906having a circular cross-section. The core906is configured to rotate around an axis908, as the abrasive elements904are brought into contact with the first semiconductor substrate101aand the first interconnect structure114. As shown in cross-sectional view1000aofFIG.10A, subsequent processing, such as chemical mechanical planarization (CMP) operation can form a metal residue layer109over the structure. In some embodiments, the metal residue layer109may be a layer that completely covers the ILD structure of the interconnect114, but in other embodiments, the metal residue layer109is “blotchy” or “patchy”, meaning that the metal residue layer includes a series of patches or blotches that cover at least part of the upper surface and sidewalls, but do not cover the entire upper surface and sidewalls. For example, the metal residue can include patches of different shapes and size (e.g., random shapes and sizes) that cover between 10% and 90% of the surface are of the upper surface and sidewalls of the interconnect structure114in some embodiments. In other embodiments, such as in the illustrated embodiments, the metal residue can cover 100% of the surface are of the upper surface and sidewalls; and in other embodiments the metal residue may not be present. To prevent this metal residue layer109from promoting arcing during subsequent high-energy processing, a dielectric capping structure110is formed along an outermost sidewall of the first interconnect structure114defined by the edge trimming process, and may cover an upper surface of the metal residue layer109. In some embodiments, the dielectric capping structure110may also be formed onto a sidewall of the first semiconductor substrate101a. In some embodiments, the dielectric capping structure110comprises silicon oxynitride, silicon nitride, silicon carbide, silicon dioxide, and/or un-doped silicate glass (USG) for example. In some embodiments, the dielectric capping structure110may be deposited by way of a low-power process, such as a lower power deposition that uses a power ranging from 100 Watts (W) to 300 W. For example, the dielectric capping structure may comprise un-doped silicate glass (USG), silicon nitride (SixNy), or silicon oxynitride (SixOyNz), formed by such a low-power process. In some embodiments, the metal residue layer109and/or capping dielectric layer110can be formed in a bevel deposition apparatus, such as shown inFIGS.17A-17B, which is described further herein. In some embodiments, after the dielectric capping structure110has been formed, the dielectric capping structure110may be exposed to a high power process that is prone to arcing. Thus, the dielectric capping structure110has a thickness and/or density that offers a sufficient resistance to arcing to protect the wafer from arcing damage. In some embodiments, the first thickness t1of the dielectric capping structure110is greater than or equal to approximately 200 Angstroms. A first thickness t1that is greater than or equal to approximately 200 Angstroms is able to isolate the interconnect structure114from arcing during subsequent processing. In some such embodiments, the first thickness t1is in a range of between approximately 200 Angstroms and approximately 2000 Angstroms. In other embodiments, the first thickness t1of the dielectric capping structure110may be greater than or equal to approximately 500 Angstroms, greater than or equal to approximately 750 Angstroms, or greater than or equal to approximately 1000 Angstroms. In some such embodiments, the dielectric capping structure110may completely cover or only partially cover the first semiconductor substrate101aand the first interconnect structure114. As shown in cross-sectional view1000bofFIG.10B, in other embodiments (shown in cross-sectional view ofFIG.10B, which is an alternate embodiment that proceeds fromFIG.8), the edge trimming operation fromFIG.9may be skipped, and the metal residue layer109and/or dielectric capping structure110may be formed by way of a bevel deposition process. In such embodiments the dielectric capping structure110is formed over an outer region of the first semiconductor substrate101aand over and along sidewalls of the interconnect structure114, but not over a center of the first semiconductor substrate101a. The resulting dielectric capping structure110comprises one or more inner sidewalls that define an opening1020over the first interconnect structure114. The metal residue may also be formed during a bevel deposition operation, such that the metal residue is also formed over the outer region of the first semiconductor substrate but not over the center of the first semiconductor substrate101a. As shown in cross-sectional view1000cofFIG.10C, in still other embodiments (shown in cross-sectional view ofFIG.10C, which is an alternate embodiment that proceeds fromFIG.9), an edge trimming operation is used on the interconnect structure, and the metal residue may again be formed during a bevel deposition operation, such that the metal residue is formed over the outer region of the first semiconductor substrate but not over the center of the first semiconductor substrate101a. The dielectric capping structure110may be formed to cover an entire top surface of the structure. In such embodiments, the dielectric capping structure110is formed over an outer region of the first semiconductor substrate101a, and over a center of the first semiconductor substrate101a. As shown in cross-sectional view1000dofFIG.10D, in still other embodiments (shown in cross-sectional view ofFIG.10D, which is an alternate embodiment that proceeds fromFIG.9), the metal residue covers the dielectric capping structure110may be formed to cover an entire top surface of the structure. In such embodiments, the dielectric capping structure110is formed over an outer region of the first semiconductor substrate101a, and over a center of the first semiconductor substrate101a. As shown in cross-sectional view1100ofFIG.11, a chemical mechanical planarization (CMP) operation is carried out to planarize the dielectric capping structure110and metal residue layer109. Thus, the CMP operation can follow fromFIG.10A-10D, and the illustrated structure ofFIG.11is consistent with some embodiments that follow fromFIG.10A,FIG.10C, and/orFIG.10D. As shown in cross-sectional view1200ofFIG.12, the first semiconductor substrate101ais bonded to a second semiconductor substrate101bto form a multi-tier semiconductor structure having a first tier202aand a second tier202b. In some embodiments, the first semiconductor substrate101ais bonded to the second semiconductor substrate101bby way of the first interconnect structure114and second interconnect structure214. The metal residue layer109and/or dielectric capping layer110may also have a planarized upper surface that contacts the upper surface of the second interconnect structure214. As shown in cross-sectional views1200-1300ofFIGS.12-13, the first semiconductor substrate101ais then thinned (see lines1302inFIGS.12-13). In various embodiments, the first semiconductor substrate101amay be thinned by etching and/or mechanical grinding a back-side of the first semiconductor substrate101aalong line1302. In some embodiments, the first semiconductor substrate101amay be thinned by a first grinding process, a subsequent second grinding process, and a chemical mechanical polishing (CMP) process. In some embodiments, the first grinding process may achieve a first surface roughness, the second grinding process may achieve a second surface roughness that is less than the first surface roughness, and the CMP process may achieve a third surface roughness that is less than the second surface roughness. As shown in cross-sectional view1400ofFIG.14, a second edge trimming process is performed to remove upper parts of the second semiconductor substrate101band the second interconnect structure214along a perimeter of the structure. In some embodiments, the edge trimming process may be performed by bringing a blade1402into contact with these features. As indicated by lines1404, in some cases this second edge trimming process may also extend up to remove perimeter portions of the first semiconductor substrate101a, resulting in outermost sidewalls of the first semiconductor substrate being flush with outermost sidewalls of the second interconnect structure214and dielectric capping layer110. As shown in cross-sectional view1500aofFIG.15A, in some embodiments the edge trimming process can trim the outer edge of the first semiconductor substrate101ato be flush with sidewalls of the first dielectric capping structure110. Then, a second dielectric capping structure160is formed along sidewalls of the second interconnect structure214. In some embodiments, the second dielectric capping structure160may also be formed on sidewalls of the first semiconductor substrate101aand/or along a recessed surface of the second semiconductor substrate101bdefined by the edge trimming process. As shown in cross-sectional view1500bofFIG.15B, which shows an alternative embodiment that proceeds fromFIG.14, the second edge trimming process can also leave an outer edge of the first semiconductor substrate101ato overhang the outer sidewall of the first dielectric capping structure110. Thus, a second dielectric capping structure170can be formed along sidewalls of the first interconnect structure114and along sidewalls of the second interconnect structure214between bevel regions of the first substrate101aand second substrate101b. As shown in cross-sectional view1500cofFIG.15C, in some cases the second substrate101bas well as the second interconnect structure214and optionally the first interconnect structure114have been edge trimmed. This edge trimming in some cases can provide an offset1502such that outer sidewalls of the first substrate101aare recessed by a distance, for example ranging from about 1 mm to about 2 mm (and being about 1.5 mm in some examples), from the outer sidewalls of the second substrate101bto help limit cracking that could otherwise arise from wafer vibration. As shown in cross-sectional view1500dofFIG.15D, in some cases one or more additional substrates, such as a third substrate101C and third interconnect structure314can be stacked over the first substrate1011. Edges of the third substrate101cand third interconnect structure314can be trimmed with the second substrate101aand optionally second interconnect structure214(and/or portion of second substrate101b), such that there is an offset1504between outer sidewalls of the first substrate101aare recessed by a distance, for example ranging from about 1 mm to about 3 mm (and being about 2.0 mm in some examples) from the outer sidewalls of the third substrate101cto help limit cracking that could otherwise arise from wafer vibration. FIG.16illustrates a flow diagram of some embodiments of a method1600of forming an integrated chip structure having a dielectric capping structure. While the methods disclosed herein are illustrated and described herein as a series of acts or events, it will be appreciated that the illustrated ordering of such acts or events are not to be interpreted in a limiting sense. For example, some acts may occur in different orders and/or concurrently with other acts or events apart from those illustrated and/or described herein. In addition, not all illustrated acts may be required to implement one or more aspects or embodiments of the description herein. Further, one or more of the acts depicted herein may be carried out in one or more separate acts and/or phases. At1602, transistors are formed within a first semiconductor substrate. At1604, a first interconnect structure is formed over the first semiconductor substrate.FIG.8illustrates a cross-sectional view800of some embodiments corresponding to acts1602and1604. At1606, an edge trimming process is performed to remove parts of the first semiconductor substrate and the first interconnect structure along a perimeter of the first semiconductor substrate.FIG.9illustrates a cross-sectional view900of some embodiments corresponding to act1606. At1608, a metal layer of metal residue is formed along sidewalls and over a top surface of the first interconnect structure. At1610, a dielectric capping layer is formed along sidewalls and over a top surface of the metal layer of metal residue.FIGS.10A-10Dillustrate various cross-sectional views of some embodiments corresponding to act1608and act1610. At1612, chemical mechanical planarization (CMP) is performed to remove an upper portion of the metal layer of metal residue and an upper portion of the dielectric capping layer, thereby exposing an upper surface of the first interconnect structure.FIG.11illustrates a cross-sectional view1100of some embodiments corresponding to act1612. At1614, the first semiconductor substrate is bonded to a second semiconductor substrate to form a multi-tier semiconductor structure.FIG.12illustrates a cross-sectional view1200of some embodiments corresponding to act1614. At1616, the first semiconductor substrate is thinned, for example using a grinding operation. This grinding operation, which can also be followed by a CMP, can exposed surfaces of through-substrate-vias (TSVs) through the backside of the first semiconductor substrate to enable electrical connections of additional substrates to the backside of the semiconductor substrate.FIG.13illustrates a cross-sectional view1300of some embodiments corresponding to act1616. At1618, an edge trimming process is performed to remove parts of the first semiconductor substrate and the first interconnect structure and/or parts of the second semiconductor substrate and the second interconnect structure along a perimeter there of.FIG.14illustrates a cross-sectional view1400of some embodiments corresponding to act1618. At1620, a second dielectric capping layer is formed along sidewalls of the multi-tier semiconductor structure. This second dielectric capping layer can also limit arcing when the multi-tier semiconductor structure is subjected to a subsequent high power process.FIGS.15A-15Billustrate cross-sectional views of some embodiments corresponding to act1620. At1622, the multi-tier semiconductor structure is diced into multiple die. FIG.17Aillustrates a perspective view of some embodiments of a bevel deposition apparatus1700. The bevel deposition apparatus in this example has a clamshell design that includes an upper chamber1702and a lower chamber1704. The upper chamber1702includes an upper extended electrode1706that surrounds an upper insulator1708. An upper plasma exclusion zone (PEZ) ring1710surrounds the upper insulator1708and separates the upper insulator1708from the upper extended electrode1706. The lower wafer includes an engagement surface to receive a semiconductor wafer101, and a lower PEZ ring1712surrounding the engagement surface. During operation, a semiconductor wafer101is placed on an engagement surface1714of the lower chamber1704, and the upper chamber1702is closed, thereby establishing a vacuum chamber about the wafer101. Thus, the semiconductor wafer101is disposed vertically between an upper plasma exclusion zone (PEZ) ring1710and a lower PEZ ring1712. FIG.17Billustrates a cross-sectional view of some embodiments of the bevel deposition apparatus along the line B-B′ ofFIG.17A, illustrating the upper PEZ ring1710, wafer101, and lower PEZ ring1712. During operation, in some embodiments, a deposition process (e.g., a chemical vapor deposition (CVD) process, plasma enhance CVD, etc.) is utilized to form the dielectric capping structure110by loading the semiconductor wafer101into the vacuum chamber. Subsequently, one or more processing gas(es)1720is/are flowed into the vacuum chamber, with the upper and lower PEZ rings1710,1712in place, such that the dielectric capping structure110is selectively deposited over the peripheral region112of the semiconductor wafer101. By virtue of a shape and/or position of the upper PEZ ring1710, the upper PEZ ring1710is configured to prevent the deposition process from depositing the dielectric capping structure110over the central region104of the semiconductor wafer101. Further, during the deposition process, the lower PEZ ring1712is disposed below the back-side surface of the semiconductor wafer101and is configured to prevent the deposition process from depositing the dielectric capping structure110on the back-side surface. In some embodiments, the upper PEZ ring1710and the lower PEZ ring1712comprise a same material such as, for example, yttrium oxide (e.g., Y2O3) or another suitable material. Accordingly, in some embodiments, the present disclosure relates to a method of forming an integrated chip structure. In the method, a plurality of interconnect layers are formed within a first interconnect structure disposed over an upper surface of a first semiconductor substrate. An edge trimming process is performed to remove parts of the first interconnect structure and the first semiconductor substrate along a perimeter of the first semiconductor substrate. The edge trimming process results in the first semiconductor substrate having a recessed surface coupled to the upper surface by way of an outer sidewall disposed directly over the first semiconductor substrate. A dielectric capping structure is formed along a sidewall of the first interconnect structure after performing the edge trimming process. In some embodiments, the present disclosure relates to a method of forming a multi-dimensional integrated chip. In this method, a plurality of interconnect layers are formed within a dielectric structure over an upper surface of a first substrate. A first edge trimming process is performed that removes parts of the dielectric structure and the first substrate along a perimeter of the first substrate. A metal residue layer is formed after the first edge trimming process. The metal residue layer extends over the plurality of interconnect layers. A first dielectric capping structure is formed along sidewalls of the metal residue layer and over an upper surface of the metal residue layer. In other embodiments, the present disclosure relates to an integrated chip structure. The integrated chip structure includes a first substrate having an upper surface within a central region and a recessed surface within a peripheral region surrounding the central region. The recessed surface laterally extends from the central region to an outermost edge of the first substrate and is vertically between the upper surface and a lower surface of the first substrate opposing the upper surface. A first plurality of interconnect layers is disposed within a first dielectric structure on the upper surface. A metal residue layer is disposed along a sidewall of the first dielectric structure. A first dielectric capping structure is disposed over the recessed surface and along an outer sidewall of the metal residue layer. The foregoing outlines features of several embodiments so that those skilled in the art may better understand the aspects of the present disclosure. Those skilled in the art should appreciate that they may readily use the present disclosure as a basis for designing or modifying other processes and structures for carrying out the same purposes and/or achieving the same advantages of the embodiments introduced herein. Those skilled in the art should also realize that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and that they may make various changes, substitutions, and alterations herein without departing from the spirit and scope of the present disclosure. | 40,319 |
11862516 | REFERENCE NUMERALS 100semiconductor substrate; 200first reaction layer; 210first portion; 220second portion; 300second reaction layer; 310first portion; 320second portion; 321portion; 322remaining portion; 400amorphous diffusion barrier layer; 500conductive layer. DESCRIPTION OF EMBODIMENTS The exemplary implementations will now be described more fully with reference to the accompanying drawings. However, the exemplary implementations can be implemented in a variety of forms and should not be construed as limited to the implementations set forth herein. Rather, these implementations are provided so that the present application will be thorough and complete and will fully convey the concepts of the exemplary implementations to those skilled in the art. Throughout the drawings, the same reference signs indicate the same or similar structures, and their detailed description will be omitted. The barrier layer is commonly used in semiconductor structures. For instance, the barrier layer may surround a fin structure, be in a contact opening, be in a metal gate, be in a metal interconnecting structure, and be among a plurality of gate layers. The barrier layer can avoid the situation where unwanted diffusions occur since the material penetrates into other layers. In general, the commonly used barrier layer is made of a crystalline material. However, owing to the presence of grain boundaries in the crystal, metal atoms of a metal layer are prone to diffusion towards other layers (such as semiconductor substrate) along the grain boundaries, which therefore adversely affects the circuit performances. On this basis, the embodiments of the present application propose a semiconductor structure manufacturing method, in which the first and second reaction layers are formed respectively on the semiconductor substrate and then undergo a thermal reaction to form an amorphous diffusion barrier layer between the first and second reaction layers. This amorphous diffusion barrier layer is an amorphous body with no grain boundary therein. As a result, the diffusion path for metal atoms is cut off, thereby improving the barrier effect of the barrier layer efficiently and solving the circuit performance issue caused by metal atom diffusion. In addition, after the amorphous diffusion barrier layer is formed by the thermal reaction, the second reaction layer has not fully reacted with the first reaction layer, and there is still an unreacted region on the upper portion of the second reaction layer. Without varying the thickness of the amorphous diffusion barrier layer, the thicknesses of the first reaction layer and the second reaction layer can be effectively decreased by removing a part of the unreacted region of the second reaction layer. This further contributes to reducing the critical size of the semiconductor device. According to the embodiments of the present application, any suitable semiconductor devices for the barrier layer may be used, e.g., complementary metal oxide semiconductor field effect transistors, complementary metal oxide semiconductor devices, p-type metal oxide semiconductor devices, n-type metal oxide semiconductor devices, fin field effect transistors, fully-wound gate metal oxide semiconductor field effect transistors such as nanowire devices or nanosheet devices, or other multi-gate field effect transistors. The semiconductor device may be manufactured when an integrated circuit or portions thereof (which may include static random access memory and/or logic circuits, passive components such as resistors, capacitors or inductors, and active components such as p-type field effect transistors, n-type field effect transistors, fin field effect transistors, complementary metal oxide semiconductor field effect transistors, complementary metal oxide semiconductor transistors, bipolar transistors, high-voltage transistors, high-frequency transistors, other memory cells, or combinations of the above) are processed. As shown inFIG.1toFIG.7,FIG.1illustrates a flow chart of the semiconductor structure manufacturing method according to an embodiment of the present application, andFIG.2toFIG.7illustrate sectional diagrams of different process stages of the semiconductor structure manufacturing method according to an embodiment of the present application. As shown in the step1010ofFIG.1and inFIG.2, a semiconductor substrate100is provided. The semiconductor substrate100may be a plane (planar metal gate) as shown in the drawing, and may be of a trench type (buried wordline) or hole type structure (metal interconnecting structure). The semiconductor substrate100includesa semiconductor material such as matrix silicon or monocrystalline silicon. In other embodiments or additional embodiments, the semiconductor substrate100may include another semiconductor element, such as germanium with a crystalline structure. The semiconductor substrate100may also include semiconductor compounds, such as silicon germanium, silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, indium antimonide, or combinations thereof. The semiconductor substrate100may also include a semiconductor-on-insulator substrate100, such as silicon-on-insulator substrate, silicon germanium-on-insulator substrate, or germanium-on-insulator substrate. In some embodiments, the semiconductor substrate100is a bulk semiconductor substrate100, e.g., semiconductor wafer. For example, the semiconductor substrate100includes a semiconductor material of silicon or other elements, e.g., germanium. The semiconductor substrate100may be doped (e.g., P-type, N-type, or combinations of the above) or undoped. In some embodiments, the semiconductor substrate100includes a semiconductor layer growing epitaxially on a dielectric layer. The epitaxially growing semiconductor layer may be made of silicon germanium, silicon, germanium, one or more other suitable materials, or combinations of the above. In some other embodiments, the semiconductor substrate100includes a compound semiconductor. For example, the compound semiconductor includes one or more Group III-V compound semiconductors having a composition as defined in the formula Alx1GaX2InX3AsY1PY2NY3SbY4, where X1, X2, X3, Y1, Y2, Y3 and Y4 represent relative proportions. They are each more than or equal to 0, and their sum is equal to 1. The compound semiconductor may include silicon carbide, gallium arsenide, indium arsenide, indium phosphide, one or more other suitable compound semiconductors, or combinations of the above. Other suitable substrates including Group II-VI compound semiconductors may also be used. In some embodiments, the semiconductor substrate100is an active layer of a semiconductor-on-insulator (SOI) substrate. The manufacturing of the SOI substrate may be achieved using a separation by implantation of oxygen (SIMOX) process, a wafer bonding process, other suitable processes, or combinations of the above. In some other embodiments, the semiconductor substrate100includes a multilayer structure. For instance, the semiconductor substrate100includes a silicon germanium layer formed on a bulk silicon layer. As shown in the step1020ofFIG.1and inFIG.3, a first reaction layer200is formed on the semiconductor substrate100. In some implementations, the first reaction layer200is made of a metal compound material. In some implementations, the above metal compound material may include titanium nitride (TiN), tantalum nitride (TaN), titanium carbonitride (TiCN), or tantalum carbonitride (TaCN). In an implementation, when titanium nitride (TiN) is formed on the semiconductor substrate100, atomic layer deposition, chemical vapor deposition, plasma-assisted chemical vapor deposition, physical vapor deposition (PVD), electroplating, electroless plating, one or more other suitable processes, or combinations of the above may be used to deposit a TiN layer on the semiconductor substrate100. In some implementations, the physical vapor deposition process is utilized to deposit the TiN layer on the semiconductor substrate100, and the reaction gas for TiN may be TiCl4and NH3. In an implementation, the first reaction layer200may have a thickness ranging from 10 nm to 50 nm, e.g., 20 nm, 25 nm, 30 nm, 35 nm, 40 nm, 45 nm, etc. As shown in the step1030ofFIG.1and inFIG.4, a second reaction layer300is formed on the first reaction layer200. In some implementations, the second reaction layer300is made of a metal conductive material, which may be cobalt (Co), molybdenum (Mo), tungsten (W) or iridium (Ir), or combinations thereof. In an implementation, formation of a cobalt layer on the first reaction layer200may be achieved using chemical vapor deposition, atomic layer deposition, physical vapor deposition, plasma-assisted chemical vapor deposition, electroplating, electroless plating, spin coating, one or more other suitable processes, or combinations of the above. In some implementations, when the physical vapor deposition process is employed to deposit Co on the first reaction layer200, dicobalt hexacarbonyl butylacetylene and H2may be used in particular. In some implementations, formation of the first reaction layer200and the second reaction layer300using the physical vapor deposition process may be as follows: the first reaction layer200and the second reaction layer300are formed in the same machine, in order to avoid the influence of the external environment on the deposited film layer. Undoubtedly, the first reaction layer200and the second reaction layer300may also be formed in different machines in a stepwise manner. In an implementation, the second reaction layer300may have a thickness ranging from 10 nm to 50 nm, e.g., 20 nm, 25 nm, 30 nm, 35 nm, 40 nm, 45 nm, etc. In an implementation, the ratio of the thickness of the first reaction layer200to the thickness of the second reaction layer300may range from 1:0.5 to 1:4. Within this range, the amorphous diffusion barrier layer400that is attained later has a uniform thickness and a small thickness error range. As shown in the step1040ofFIG.1and inFIG.5, at least a portion of the first reaction layer200is thermally reacted with at least a portion of the second reaction layer300, to form an amorphous diffusion barrier layer. As shown inFIG.5, the first reaction layer200includes a first portion210and a second portion220, and the first portion210and the second portion220are stacked along a thickness direction of the first reaction layer200. The first portion210is a portion that does not react with the second reaction layer300, and the second portion220is a portion that reacts with the second reaction layer300. The second reaction layer300includes a first portion310and a second portion320, and the first portion310and the second portion320are stacked along the thickness direction of the second reaction layer300. The first portion310is a portion that reacts with the second portion220of the first reaction layer200, and the second portion320is a portion that does not react with the first reaction layer200. When the semiconductor structure is subjected to thermal treatment, the metal atoms (such as cobalt) of the second reaction layer300will diffuse towards the first reaction layer200(such as titanium nitride), so as to form the above-mentioned amorphous diffusion barrier layer400. It is to be understood that the thickness of the amorphous diffusion barrier layer400may be less than or equal to the sum of the thickness of the second portion220of the first reaction layer200and the thickness of the first portion310of the second reaction layer300. In some implementations, the thickness of the amorphous diffusion barrier layer400may range from 2 nm to 10 nm. In some implementations, the above-mentioned amorphous diffusion barrier layer400may be formed by reacting the metal compound material of the first reaction layer200with the metal conductive material of the second reaction layer300. In some implementations, the amorphous diffusion barrier layer400may include cobalt titanium nitride (CoTiN), which is an amorphous body with no grain boundary therein. As a result, the diffusion path for metal atoms is cut off, thereby improving the barrier effect of the barrier layer efficiently and solving the circuit performance issue caused by metal atom diffusion. In some implementations, the thermal reaction described above is rapid thermal annealing. The temperature of the rapid thermal annealing may range from 200° C. to 1000° C., and may be 300° C., 450° C., 550° C., 650° C., or 800° C., for example. The time of the rapid thermal annealing may range from 1 s to 3 min, and may be 10 s, 30 s, 60 s, 90 s, 120 s, or 150 s, for example. As shown in the step1050ofFIG.1and inFIG.6, a portion321of the second portion320of the second reaction layer300is removed along a thickness direction. Without varying the thickness of the amorphous diffusion barrier layer400, the thicknesses of the first reaction layer200and the second reaction layer300can be effectively decreased by removing a part of the unreacted region of the second reaction layer300. This further contributes to reducing the critical size of the semiconductor device. In some implementations, removal of the portion321of the second portion320of the second reaction layer300may be achieved using a chemical mechanical polishing process, a grinding process, an etching process, a dry polishing process, wet cleaning, one or more other suitable processes, or combinations of the above. In an implementation, the wet cleaning process is employed to remove the portion321of the second portion320of the second reaction layer300. In particular, removal is done using a mixed liquid of sulfuric acid and hydrogen peroxide. The mixed liquid of sulfuric acid and hydrogen peroxide may have the volume ratio of concentrated sulfuric acid, hydrogen peroxide and water of 5:1:1. The cleaning temperature may range from 70° C. to 90° C., and the cleaning time may range from 10 s to 5 min. A portion322that is left after the portion of the second portion320of the second reaction layer300is removed may serve as an adhesion layer or a seed layer for formation of a conductive layer500in the step1060ofFIG.1. In an implementation, the thickness of the portion322that is left after the portion of the second portion320of the second reaction layer300is removed may range from 5 nm to 50 nm, and may be 8 nm, 10 nm, 15 nm, 25 nm, or 40 nm, for example. As shown in the step1060ofFIG.1and inFIG.7, a conductive layer500is formed on the second reaction layer300. In some implementations, the conductive layer500is made of or includes a metal material. The metal material may include tungsten, aluminum, copper, one or more other suitable materials, or combinations of the above. The conductive layer500may be deposited on the second reaction layer300, and deposition of the conductive layer500may be achieved using chemical vapor deposition, atomic layer deposition, physical vapor deposition, plasma-assisted chemical vapor deposition, electroplating, electroless plating, spin coating, one or more other suitable processes, or combinations of the above. In some implementations, the conductive layer500is made of copper, the first reaction layer200is made of a metal compound material, e.g., TiN, and the second reaction layer300is made of a metal conductive material, e.g., Co. In some other implementations, the conductive layer500is made of tungsten, the first reaction layer200is made of a metal conductive material e.g., Co, and the second reaction layer300is made of a metal compound material, e.g., TiN. The semiconductor structure manufacturing method according to another implementation of the present application will be described in detail below with reference toFIG.8toFIG.13. In these drawings,FIG.8illustrates a flow chart of the semiconductor structure manufacturing method according to another embodiment of the present application, andFIG.9toFIG.13illustrate sectional diagrams of different process stages of the semiconductor structure manufacturing method according to another embodiment of the present application. As shown in the step2010ofFIG.8and inFIG.9, a semiconductor substrate100is provided. The semiconductor substrate100may be a plane (planar metal gate) as shown in the drawing, and may be of a trench type (buried wordline) or hole type structure (metal interconnecting structure). The semiconductor substrate100includes a semiconductor material such as matrix silicon or monocrystalline silicon. In other embodiments or additional embodiments, the semiconductor substrate100may include another semiconductor element, such as germanium with a crystalline structure. The semiconductor substrate100may also include semiconductor compounds, such as silicon germanium, silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, indium antimonide, or combinations thereof. The semiconductor substrate100may also include a semiconductor-on-insulator substrate100, such as silicon-on-insulator substrate, silicon germanium-on-insulator substrate, or germanium-on-insulator substrate. In some embodiments, the semiconductor substrate100is a bulk semiconductor substrate100, e.g., semiconductor wafer. For example, the semiconductor substrate100includes a semiconductor material of silicon or other elements, e.g., germanium. The semiconductor substrate100may be doped (e.g., P-type, N-type, or combinations of the above) or undoped. In some embodiments, the semiconductor substrate100includes a semiconductor layer growing epitaxially on a dielectric layer. The epitaxially growing semiconductor layer may be made of silicon germanium, silicon, germanium, one or more other suitable materials, or combinations of the above. In some other embodiments, the semiconductor substrate100includes a compound semiconductor. For example, the compound semiconductor includes one or more Group III-V compound semiconductors having a composition as defined in the formula Alx1GaX2InX3AsY1PY2NY3SbY4, where X1, X2, X3, Y1, Y2, Y3 and Y4 represent relative proportions. They are each more than or equal to 0, and their sum is equal to 1. The compound semiconductor may include silicon carbide, gallium arsenide, indium arsenide, indium phosphide, one or more other suitable compound semiconductors, or combinations of the above. Other suitable substrates including Group II-VI compound semiconductors may also be used. In some embodiments, the semiconductor substrate100is an active layer of a semiconductor-on-insulator (SOI) substrate. The manufacturing of the SOI substrate may be achieved using a separation by implantation of oxygen (SIMOX) process, a wafer bonding process, other suitable processes, or combinations of the above. In some other embodiments, the semiconductor substrate100includes a multilayer structure. For instance, the semiconductor substrate100includes a silicon germanium layer formed on a bulk silicon layer. As shown in the step2020ofFIG.8and inFIG.10, a plurality of first reaction layers200and a plurality of second reaction layers300are formed on the semiconductor substrate100, and the plurality of first reaction layers200and the plurality of second reaction layers300are alternately arranged. In some implementations, the first reaction layer200is a made of metal compound material. In some implementations, the above metal compound material may include titanium nitride (TiN), tantalum nitride (TaN), titanium carbonitride (TiCN), or tantalum carbonitride (TaCN). In an implementation, when titanium nitride (TiN) is formed on the semiconductor substrate100, atomic layer deposition, chemical vapor deposition, plasma-assisted chemical vapor deposition, physical vapor deposition (PVD), electroplating, electroless plating, one or more other suitable processes, or combinations of the above may be used to deposit a TiN layer on the semiconductor substrate100. In some implementations, the physical vapor deposition process is utilized to deposit the TiN layer on the semiconductor substrate100, and the reaction gas for TiN may be TiCl4and NH3. In an implementation, the first reaction layer200may have a thickness ranging from 2 nm to 10 nm, e.g., 3 nm, 5 nm, 7 nm, 9 nm, etc. In some implementations, the second reaction layer300is made of a metal conductive material, which may be cobalt (Co), molybdenum (Mo), tungsten (W) or iridium (Ir), or combinations thereof. In an implementation, formation of a cobalt layer on the first reaction layer200may be achieved using chemical vapor deposition, atomic layer deposition, physical vapor deposition, plasma-assisted chemical vapor deposition, electroplating, electroless plating, spin coating, one or more other suitable processes, or combinations of the above. In some implementations, when the physical vapor deposition process is employed to deposit Co on the first reaction layer200, dicobalt hexacarbonyl butylacetylene and H2may be used in particular. In some implementations, formation of the first reaction layer200and the second reaction layer300using the physical vapor deposition process may be as follows: the first reaction layer200and the second reaction layer300are formed in the same machine, in order to avoid the influence of the external environment on the deposited film layer. Undoubtedly, the first reaction layer200and the second reaction layer300may also be formed in different machines in a stepwise manner. In an implementation, the second reaction layer300may have a thickness ranging from 2 nm to 10 nm, e.g., 3 nm, 5 nm, 7 nm, 9 nm, etc. In an implementation, the ratio of the thickness of the first reaction layer200to the thickness of the second reaction layer300may range from 1:0.5 to 1:4. Within this range, the amorphous diffusion barrier layer400that is attained later has a uniform thickness and a small thickness error range. The above operation of depositing the first reaction layers200and the second reaction layers300is repeated, and a plurality of first reaction layers200and second reaction layers300arranged alternately are formed on the semiconductor substrate100(e.g., TiN/Co/TiN/Co/TiN/Co . . . ). As shown in the step2030ofFIG.8and inFIG.11, at least a portion of the adjacent first reaction layer200is thermally reacted with at least a portion of the adjacent second reaction layer300, to form an amorphous diffusion barrier layer400between each of the adjacent first reaction layers200and each of the adjacent second reaction layers300. As shown inFIG.11, the plurality of first reaction layers200and the plurality of second reaction layers300are alternately arranged, to form an amorphous diffusion barrier layer400between each of the adjacent first reaction layers200and each of the adjacent second reaction layers300. As such, a plurality of amorphous diffusion barrier layers400are formed in the semiconductor structure, and the barrier effect of the barrier layers are improved. When the semiconductor structure is subjected to thermal treatment, the metal atoms (such as cobalt) of the second reaction layer300will diffuse towards two first reaction layers200(such as titanium nitride) adjacent thereto, so as to form the above-mentioned amorphous diffusion barrier layer400. In some implementations, the thickness of the amorphous diffusion barrier layer400may range from 1 nm to 5 nm. In some implementations, the above-mentioned amorphous diffusion barrier layer400may be formed by reacting the metal compound material of the first reaction layer200with the metal conductive material of the second reaction layer300. In some implementations, the amorphous diffusion barrier layer400may include cobalt titanium nitride (CoTiN), which is an amorphous body with no grain boundary therein. As a result, the diffusion path for metal atoms is cut off, thereby improving the barrier effect of the barrier layers efficiently and solving the circuit performance issue caused by metal atom diffusion. In some implementations, the thermal reaction described above is rapid thermal annealing. The temperature of the rapid thermal annealing may range from 200° C. to 1000° C., and may be 300° C., 450° C., 550° C., 650° C., or 800° C., for example. The time of the rapid thermal annealing may range from 1 s to 3 min, and may be 10 s, 30 s, 60 s, 90 s, 120 s, or 150 s, for example. As shown in the step2040ofFIG.8and inFIG.12, a portion321of the unreacted portion of the uppermost layer of the plurality of first reaction layers200and the plurality of second reaction layers300is removed along a thickness direction. Without varying the thickness of the amorphous diffusion barrier layer400, the thicknesses of the plurality of first reaction layers200and the plurality of second reaction layers300can be effectively decreased by removing a part of the unreacted region of the uppermost layer. This further contributes to reducing the critical size of the semiconductor device. In some implementations, removal of the portion321of the unreacted portion of the uppermost layer may be achieved using a chemical mechanical polishing process, a grinding process, an etching process, a dry polishing process, wet cleaning, one or more other suitable processes, or combinations of the above. In an implementation, the wet cleaning process is employed to remove the portion321of the unreacted portion of the uppermost layer. In particular, removal is done using a mixed liquid of sulfuric acid and hydrogen peroxide. The mixed liquid of sulfuric acid and hydrogen peroxide may have the volume ratio of concentrated sulfuric acid, hydrogen peroxide and water of 5:1:1. The cleaning temperature may range from 70° C. to 90° C., and the cleaning time may range from 10 s to 5 min. A portion322that is left after the portion of the unreacted region of the uppermost layer is removed may serve as an adhesion layer or a seed layer for formation of a conductive layer500in the step2050ofFIG.8. For example, the amorphous diffusion barrier layer400may include cobalt titanium nitride (CoTiN), the first reaction layer200may include TiN, and the second reaction layer300may include Co. The uppermost layer of the plurality of first reaction layers200and the plurality of second reaction layers300may be the second reaction layer300, e.g., Co. The portion322that is left after the portion of the unreacted region of the second reaction layer300is removed may serve as an adhesion layer or a seed layer for subsequent copper deposition. Certainly, it will be appreciated that the uppermost layer of the plurality of first reaction layers200and the plurality of second reaction layers300may also be the first reaction layer200, e.g., TiN, which may serve as an adhesion layer and a barrier layer for subsequent tungsten deposition. Therefore, CoTiN may serve as an adhesion layer and a barrier layer at the time of tungsten deposition, in order to block erosion of the semiconductor substrate100caused by fluorine (F) atoms in tungsten. In an implementation, the thickness of the portion that is left after the portion of the unreacted region of the uppermost layer is removed may range from 2 nm to 10 nm, and in particular may be 4 nm, 6 nm, or 8 nm. As shown in the step2050ofFIG.8and inFIG.13, a conductive layer500is formed on the uppermost layer of the plurality of first reaction layers200and the plurality of second reaction layers300. In some implementations, the conductive layer500is made of or includes a metal material. The metal material may include tungsten, aluminum, copper, one or more other suitable materials, or combinations of the above. The conductive layer500may be deposited using chemical vapor deposition, atomic layer deposition, physical vapor deposition, plasma-assisted chemical vapor deposition, electroplating, electroless plating, spin coating, one or more other suitable processes, or combinations of the above. In conclusion, the semiconductor structure manufacturing method according to the embodiments of the present application has the following advantages and beneficial effects. In the semiconductor structure manufacturing method according to the embodiments of the present application, the first and second reaction layers are formed respectively on the semiconductor substrate and then undergo a thermal reaction to form an amorphous diffusion barrier layer between the first and second reaction layers. This amorphous diffusion barrier layer is an amorphous body with no grain boundary therein. As a result, the diffusion path for metal atoms is cut off, thereby improving the barrier effect of the barrier layer efficiently and solving the circuit performance issue caused by metal atom diffusion. In addition, after the amorphous diffusion barrier layer is formed by the thermal reaction, the second reaction layer has not fully reacted with the first reaction layer, and there is still an unreacted region on the upper portion of the second reaction layer. Without varying the thickness of the amorphous diffusion barrier layer, the thicknesses of the first reaction layer and the second reaction layer can be effectively decreased by removing a part of the unreacted region of the second reaction layer. This further contributes to reducing the critical size of the semiconductor device. It is to be noted herein that the semiconductor structure manufacturing method shown in the drawings and described in this specification is merely an example of use of the principle of the present application. Those ordinary skilled in the art shall clearly understand that the principle of the present application is not limited only to any details or any components of the device shown in the drawings or described in the specification. It should be understood that the present application does not limit its application to the detailed structure and arrangement of the components proposed in this specification. The present application can have other implementations, and can be implemented and executed in various ways. The aforementioned deformations and modifications fall within the scope of the present application. It should be understood that the present application disclosed and defined in this specification extends to all alternative combinations of two or more than two individual features that are mentioned or become obvious in the text and/or drawings. All these different combinations constitute multiple alternative aspects of the present application. The implementations described in this specification illustrate the best way known to implement the present application, and will enable those skilled in the art to use this application. | 30,740 |
11862517 | DETAILED DESCRIPTION A dual hydrogen barrier for memory devices and methods of fabrication are described. While various embodiments are described with reference to FeRAM or paraelectric RAM, capacitive structures formed herein can be used for any application where a capacitor is desired. For example, the capacitive structure can be used for fabricating ferroelectric based or paraelectric based majority gate, minority gate, and/or threshold gate. In the following description, numerous specific details are set forth, such as structural schemes and detailed fabrication methods to provide a thorough understanding of embodiments of the present disclosure. It will be apparent to one skilled in the art that embodiments of the present disclosure may be practiced without these specific details. In other instances, well-known features, such as process equipment and device operations, are described in lesser detail to not unnecessarily obscure embodiments of the present disclosure. Furthermore, it is to be understood that the various embodiments shown in the Figures are illustrative representations and are not necessarily drawn to scale. In some instances, in the following description, well-known methods and devices are shown in block diagram form, rather than in detail, to avoid obscuring the present disclosure. Reference throughout this specification to “an embodiment” or “one embodiment” or “some embodiments” means that a particular feature, structure, function, or characteristic described in connection with the embodiment is included in at least one embodiment of the disclosure. Thus, the appearances of the phrase “in an embodiment” or “in one embodiment” or “some embodiments” in various places throughout this specification are not necessarily referring to the same embodiment of the disclosure. Furthermore, the particular features, structures, functions, or characteristics may be combined in any suitable manner in one or more embodiments. For example, a first embodiment may be combined with a second embodiment anywhere the particular features, structures, functions, or characteristics associated with the two embodiments are not mutually exclusive. As used in the description and the appended claims, the singular forms “a”, “an” and “the” are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will also be understood that the term “and/or” as used herein refers to and encompasses all possible combinations of one or more of the associated listed items. The terms “coupled” and “connected,” along with their derivatives, may be used herein to describe functional or structural relationships between components. These terms are not intended as synonyms for each other. Rather, in particular embodiments, “connected” may be used to indicate that two or more elements are in direct physical, optical, or electrical contact with each other. “Coupled” may be used to indicated that two or more elements are in either direct or indirect (with other intervening elements between them) physical, electrical or in magnetic contact with each other, and/or that the two or more elements co-operate or interact with each other (e.g., as in a cause an effect relationship). The terms “over,” “under,” “between,” and “on” as used herein refer to a relative position of one component or material with respect to other components or materials where such physical relationships are noteworthy. For example, in the context of materials, one material or material disposed over or under another may be directly in contact or may have one or more intervening materials. Moreover, one material disposed between two materials may be directly in contact with the two layers or may have one or more intervening layers. In contrast, a first material “on” a second material is in direct contact with that second material/material. Similar distinctions are to be made in the context of component assemblies. As used throughout this description, and in the claims, a list of items joined by the term “at least one of” or “one or more of” can mean any combination of the listed terms. The term “adjacent” here generally refers to a position of a thing being next to (e.g., immediately next to or close to with one or more things between them) or adjoining another thing (e.g., abutting it). The term “signal” may refer to current signal, voltage signal, magnetic signal, or data/clock signal. The term “device” may generally refer to an apparatus according to the context of the usage of that term. For example, a device may refer to a stack of layers or structures, a single structure or layer, a connection of various structures having active and/or passive elements, etc. Generally, a device is a three-dimensional structure with a plane along the x-y direction and a height along the z direction of an x-y-z Cartesian coordinate system. The plane of the device may also be the plane of an apparatus which comprises the device. Unless otherwise specified in the explicit context of their use, the terms “substantially equal,” “about equal” and “approximately equal” mean that there is no more than incidental variation between two things so described. In the art, such variation is typically no more than +/−10% of a predetermined target value. The terms “left,” “right,” “front,” “back,” “top,” “bottom,” “over,” “under,” and the like in the description and in the claims, if any, are used for descriptive purposes and not necessarily for describing permanent relative positions. For example, the terms “over,” “under,” “front side,” “back side,” “top,” “bottom,” “over,” “under,” and “on” as used herein refer to a relative position of one component, structure, or material with respect to other referenced components, structures, or materials within a device, where such physical relationships are noteworthy. These terms are employed herein for descriptive purposes only and predominantly within the context of a device z-axis and therefore may be relative to an orientation of a device. Hence, a first material “over” a second material in the context of a figure provided herein may also be “under” the second material if the device is oriented upside-down relative to the context of the figure provided. Similar distinctions are to be made in the context of component assemblies. The term “between” may be employed in the context of the z-axis, x-axis or y-axis of a device. A material that is between two other materials may be in contact with one or both of those materials. In another example, a material that is between two or other material may be separated from both of the other two materials by one or more intervening materials. A material “between” two other materials may therefore be in contact with either of the other two materials. In another example, a material “between” two other materials may be coupled to the other two materials through an intervening material. A device that is between two other devices may be directly connected to one or both of those devices. In another example, a device that is between two other devices may be separated from both of the other two devices by one or more intervening devices. Capacitors with a wide variety of materials have been implemented for memory (random access memory or RAM) applications. Perovskite materials have been implemented in capacitors such for high density FeRAM applications owing to their low power consumption and high on/off ratio. Perovskite FeRAM devices (herein FeRAM devices) are also desirable over other forms of memory such as magnetic tunnel junction (MTJ)-based devices due to the relatively low number of layers within a device compared to the MTJ. A typical FeRAM device may be fully operational with three layers, where a ferroelectric dielectric is contained between two electrode layers. The electrode layers may also include Perovskite materials to enable lattice matching and reduction in electrical resistance. Introduction of lead-free Perovskite materials offer additional environmental benefits without sacrificing device performance. However, FeRAM devices including lead-free Perovskite materials are prone to damage from reaction with hydrogen during processing. Specifically, the damage may be result of hydrogen traveling along grain boundaries between or along electrodes coupled with two terminals of a FeRAM device. Hydrogen can cause reduction when it reacts with the one or more materials of the FeRAM device, such the electrodes or the ferroelectric material itself. Sources of hydrogen during fabrication arise from anneal operations carried to tie up dangling bonds. However, FeRAM devices can lose their polarization hysteresis characteristics as a result of hydrogen reduction. In some embodiments, the capacitor devices have a planar structure where the individual layers are sequentially layered, one on top of another, where the layers are patterning into cylinder or rectangular shapes. Thus, it is highly desirable to protect capacitor sidewalls, top and bottom surfaces from reacting with hydrogen. In some embodiments, solutions against hydrogen diffusion include forming an insulating barrier layer, such as for example, silicon nitride, to protect sidewalls and top surfaces. A contact electrode at a top of the FeRAM device may be formed by piercing through the insulating barrier layer and exposing one or more top electrode materials. The barrier layer themselves may be further surrounded by additional insulating material such as an interlayer dielectric (ILD). However, the contact electrode formed may be wider than a width of a FeRAM device and can result in erosion of spacer. Spacer erosion can lead to exposure to the adjacent ILD material. ILD material such as silicon oxide or silicon oxide doped with carbon in general do not act as a hydrogen diffusion barrier, and are less desirable directly adjacent to one or more layers of the memory device. In other examples, hydrogen may diffuse through one or more materials of the contact electrode towards the FeRAM device stack through a top electrode. To protect against hydrogen diffusion through a top surface of the top electrode noble metals have been implemented as part of the contact electrode structure. However, noble metals normally have crystalline structures due to strong metallic bonding. Hence their amorphous phase is thermodynamically unstable favoring transformation into a crystalline phase. Furthermore, it is to be appreciated that hydrogen can also diffuse from layers below a bottom electrode of the ReRAM device. Typically, the bottom electrode is physically isolated from a conductive interconnect by at least one transition electrode. The conductive interconnect may be laterally surrounded by an ILD. The transition electrode may be laterally surrounded by an insulator layer that can act as a barrier against hydrogen diffusion as well as provide etch stop capability while patterning the ReRAM stack. The insulator layer is typically formed above the ILD and the conductive interconnect. The interface between the transition electrode and the conductive interconnect, can be a pathway for hydrogen diffusion. Depending on a width of the transition electrode relative to the conductive interconnect. the transition electrode may be in contact with the ILD adjacent to the conductive interconnect. The inventors have devised a scheme to implement a dual hydrogen barrier that includes an insulative hydrogen barrier material directly adjacent to the memory device and a conductive hydrogen barrier that is integrated as part of the contact electrode. In some embodiments, the contact electrode may have a shape of a via that include a conductive hydrogen barrier having a first portion directly in contact with the memory device and a second portion that laterally surrounds a conductive (contact) material. The conductive contact material may further include one or more layers. The contact electrode may extend over a portion or an entire uppermost surface of the memory device. To provide a barrier against hydrogen diffusion towards a bottom electrode, the transition electrode may also include a conductive hydrogen barrier material. The structure of the transition electrode may depend on the size of the memory device relative to the transition electrode. In embodiments, the transition electrode may include a conductive hydrogen barrier laterally surrounding a conductive material. In other embodiments, the transition electrode may include conductive hydrogen barrier directly across a top portion and in direct contact with the memory device. To provide a barrier against hydrogen diffusion directly into sidewalls of the memory device, a dielectric that is amorphous, having a high film density (a film density above 90% of theoretical material density or film density) and is electrically insulating, may be directly in contact with the sidewalls of the memory device. Furthermore, when memory devices are integrated in a high density array, the space between the devices may not be large enough to deposit a barrier liner (spacer) as well as an ILD. In some such instances the high film density-dielectric is present over the entire memory region. Memory devices in the memory region may be directly adjacent to a logic region within a memory level, for system functionality. In particular, the ferroelectric devices may be directly adjacent to routing interconnects in the logic region. To minimize line capacitance, the routing interconnects are embedded within a low dielectric constant interlayer dielectric (ILD), where the ILD has a low film density (less than 90% film density) or a high porosity material. The ferroelectric capacitors may be integrated with transistors in a memory region of a substrate. For example, ferroelectric capacitors may be on a memory level above a transistor level. There may be one or more layers of conductive interconnects between the ferroelectric capacitors (herein ferroelectric devices) and transistors in the transistor level. A vertical thickness or height of a single level of routing interconnects (herein interconnect level) is determined by a combined thickness of one or more stacked vias and metal lines within the routing interconnects and is substantially fixed. To minimize fabrication cost, it is highly desirable to match a height of the memory level with a height of a single level of routing interconnects. The single level may include one or more stacked conductive interconnects such as a metal line on a via, or a via on a via. For manufacturability ferroelectric devices may be generally formed directly above conductive interconnects that are coupled with transistors on a lower level. When a conductive interconnect includes copper, it is high desirable to not etch a ferroelectric device and expose the copper conductive interconnect. In such instances, an etch stop layer may be inserted between the conductive interconnect and the ferroelectric device. The etch stop layer also acts as a hydrogen barrier layer to prevent diffusion of hydrogen from a dielectric adjacent to the conductive interconnect to one or more memory devices in a layer above. However, to provide electrical conductivity between the ferroelectric device and the conductive interconnect, a transition electrode may be inserted between a ferroelectric device and a conductive interconnect. The transition electrode may be embedded within the etch stop layer. Because the transition electrode is embedded within the etch stop layer, alignment and sizing requirements of the etch stop layer relative to the conductive interconnect (or the ferroelectric device) may be relaxed. Additionally, the shape of the transition electrode may be independent of a shape of the conductive interconnect. The ferroelectric device may be patterned by a plasma etch process. Depending on a shape and size of the ferroelectric device relative to the transition electrode, the plasma etch process may etch portions of the transition electrode and/or the etch stop layer. A resulting shape of the transition electrode and/or the etch stop layer adjacent to the ferroelectric device may partially depend on thicknesses of the transition electrode and/or the etch stop layer. The ferroelectric device spans a height that depends on thickness of individual layers in the ferroelectric devices. Thus, depending on the thicknesses of the individual layers, the height of the ferroelectric device can vary depending on application. In general, the transition electrode has a fixed thickness. In order to maintain a height of the memory level, individual thicknesses of the ferroelectric devices and the via electrodes may be co-dependently tuned. For example, when the ferroelectric device has a reduced thickness, the thickness of the via electrode may be increased, and vice versa. To enable high density FeRAM devices the inventors have resorted to non-lead-based perovskite materials owing its environmental friendliness for mass production. A stack for ferroelectric capacitors can include one or more hardmask materials. The one or more hardmask materials can include dielectric materials, metallic materials or a combination thereof. Implementation of an etch with high selectivity (such as a reactive ion etching, or plasma etch process) between the hardmask and device layers can advantageously enable patterning. In some embodiments, the conductive interconnects coupled with a respective ferroelectric device are discrete island structures. In other embodiments, the conductive interconnect may be a continuous trench line, where a plurality of ferroelectric devices may be coupled with the trench line. In some such embodiments, the transition electrode may be continuous between a respective ferroelectric device and extend along a length of the trench line. In other embodiments, the conductive interconnect may be discrete, but the transition electrode (herein electrode structure) may be continuous between two or more adjacent capacitors. In further embodiments, the conductive interconnects are discrete, but a top electrode of individual ferroelectric capacitors are coupled together by a single conductive plate. FIG.1Ais a cross-sectional illustration of a device structure100A, including a region101A, adjacent to a region101B above a substrate150. The region101A and101B may be, for example, a memory region and a logic region, respectively or vice versa. In the illustrative embodiment, region101A is a memory region101A and region101B is a logic region101B. The memory region101A includes a plurality of conductive interconnects within level104. Each conductive interconnect102is substantially identical within level104. The conductive interconnect102is laterally surrounded by a dielectric105. The dielectric105includes a material having a low film density, such as for example density less than 90% of theoretical material density. In some embodiments, dielectric105includes a material having a dielectric constant that is below 3.5. Dielectric105may include SiO2, SiOC, SiC or SiO2doped with F. The device structure100A further includes a level106above level104. Level106include a plurality of memory devices each including one or more ferroelectric materials or one or more paraelectric materials. In the illustrative embodiment, each memory device108within device structure100A are substantially identical. While two memory device such as memory devices108are illustrated, an array can have more than 1000 substantially identical memory devices108. As shown, each memory device108is above and electrically coupled with a respective conductive interconnect102. As shown, an electrode structure112is coupled between a respective memory device108and a respective conductive interconnect102. The electrode structure112is laterally surrounded by an etch stop layer113. In exemplary embodiments, etch stop layer113includes a dielectric material. In exemplary embodiments, the dielectric material of the etch stop layer113does not include a metal. The electrode structure112may cover an entire top surface or at least a portion of the top surface of conductive interconnect102, depending on a lateral thickness (or width), WES, of electrode structure112compared to a lateral thickness, WCI, of conductive interconnect102. In the illustrative embodiment, WES, is greater than WCI. In embodiments where WES, is greater than WCI, electrode structure112is also on a portion of the dielectric105. In some such embodiments, hydrogen may diffuse from the dielectric105to the memory device108. For example, interface107A between electrode structure112and dielectric105, and interface107B between electrode structure112and etch stop layer113may provide pathways for hydrogen diffusion. To prevent hydrogen diffusion through interfaces107A and107B, electrode structure112can include a hydrogen barrier layer along interfaces107A and107B. The hydrogen barrier layer may have various structural embodiments. In the illustrative embodiment, electrode structure112includes a conductive hydrogen barrier114and a conductive fill material115adjacent to conductive hydrogen barrier114. As shown, conductive hydrogen barrier114extends along interfaces107A and107B and is in contact with uppermost surface102B of conductive interconnect102. In the illustrative embodiment, conductive hydrogen barrier114includes a portion114A which is below conductive fill material115and a portion114B that laterally surrounds conductive fill material115. Portion114B is directly between conductive fill material115and etch stop layer113. Portion114A is directly between conductive fill material115and conductive interconnect102. In the illustrative embodiment, where WES, is greater than WCI, portion114A is also directly in contact with the dielectric105. Conductive hydrogen barrier114and etch stop layer113form a dual hydrogen barrier from below the memory device108. Conductive hydrogen barrier114includes a material that is amorphous. Amorphous materials lack defined grain boundaries that can facilitate hydrogen diffusion and are thus desirable. Embodiments of the conductive hydrogen barrier114include materials such as, but not limited to, TiAlN, with >30 atomic percent AlN, TaN, with >30 atomic percent N2, TiSiN, with >20 atomic percent SiN, Ta carbide, TaC, Ti carbide, TiC, tungsten carbide, WC, tungsten nitride, WN, carbonitrides of Ta, Ti, W, i.e., TaCN, TiCN, WCN, titanium monoxide, TiO, Ti2O, Tungsten oxide, WO3, Tin oxide, SnO2, indium tin oxide, ITO, Iridium Oxide, Indium Gallium Zinc Oxide, IGZO, Zinc Oxide or METGLAS series of alloys, e.g., Fe40Ni40P14B6(METGLAS is a Honeywell™). In some embodiments, the conductive hydrogen barrier114has a thickness that is less than 5 nm. The device structure100A further includes a second dielectric, such as dielectric116spanning the entire memory region101A. In exemplary embodiments, the dielectric116includes a hydrogen barrier material where the hydrogen barrier material is amorphous, has a high film density (a film density above 90% of theoretical material density) and is electrically insulating. Amorphous materials prevent diffusion along grain boundary. High film density prevents diffusion through interconnected pores, closing all diffusion pathways. In an embodiment, dielectric116includes a transition metal and oxygen, such as for example AlxOy, HfOX, ZrOx, TaOx, TiOX, AlSiOx, HfSiOXor TaSiOx. In other embodiments, dielectric116includes a nitride of Al, Zr or Hf, for example AlN, ZrN, or HfN. The dielectric116may include a high density SiOx, SiN, SiCN, SiC or SiON. A high density material has film density greater that 90% of theoretical material density. The dielectric116does not include low density SiOx, SiN, SiCN, SiC or SiON. A low density material has film density less that 90% of theoretical material density. As shown dielectric116laterally surrounds each memory device and is in direct contact with sidewalls108A. In the illustrative embodiment, dielectric116spans an entire space between any two adjacent memory devices108. In some embodiments, the dielectric116is also on portions of an uppermost surface108B of the memory device108, such as is shown. In embodiments, the dielectric116includes a material that is compatible with the selection of ferroelectric oxide within the memory device108. Depending on embodiments, memory device108can have three or more layers. An embodiment of the memory device108including three layers is illustrated inFIG.1B. As shown, memory device108includes at least a bottom electrode128, a dielectric layer130and a top electrode132. In an embodiment, bottom electrode128and top electrode132include a conductive ferroelectric oxide (when memory device108is a ferroelectric memory device108). The conductive ferroelectric oxide includes one of a non-Pb perovskite metal oxides, such as but not limited to, La—Sr—CoO3, SrRuO3, La—Sr—MnO3, YBa2Cu3O7, Bi2Sr2CaCu2O8, or LaNiO3. In an embodiment, dielectric layer130is a ferroelectric dielectric layer130that includes non-Pb perovskite material in the form ABO3, where A and B are two cations of different sizes and O is Oxygen. A is generally larger than B in size. In some embodiments, non-Pb Perovskites can also be doped, e.g., by La or Lanthanides. The non-Pb Perovskite material can include one or more of La, Sr, Co, Cr, K, Nb, Na, Sr, Ru, Y, Fe, Ba, Hf, Zr, Cu, Ta, Bi, Ca, Ti and Ni. In other embodiments, ferroelectric dielectric layer130includes low voltage ferroelectric material sandwiched between top electrode132and bottom electrode128. These low voltage FE materials can be of the form AA′BB′O3, where A′ is a dopant for atomic site A and can be an element from the Lanthanides series, where B′ is a dopant for atomic site B and can be an element from the transition metal elements such as Sc, Ti, V, Cr, Mn, Fe, Co, Ni, Cu, Zn. A′ may have the same valency of site A, with a different ferroelectric polarizability. A voltage below 2-Volts is sufficiently low to be characterized as low voltage. The ferroelectric dielectric layer130is chosen to have a similar young's modulus as the dielectric116. Furthermore, dielectric116is chosen to have a low probability of presence of defects at the interface between dielectric and the ferroelectric dielectric layer130. Additionally, dielectric116has a lower dielectric constant than the dielectric constant of the ferroelectric dielectric layer130to enable field lines to be concentrated between the top electrode132and the bottom electrode128. In some embodiments, the ferroelectric dielectric layer130can dictate a choice of the dielectric116. For example, in some embodiments, where ferroelectric dielectric layer130include a PbxZr1-xTiyO3group of families, dielectric116can include AlxOy, HfOX, ZrOx, TaOxor TiOX. In some embodiments, where ferroelectric dielectric layer130include a LaxBi1-xFeyO3group of families, dielectric116can include AlxOy, HfOX, ZrOx, TaOxor TiOx. In some embodiments, where ferroelectric dielectric layer130include a BaTiO3group of families, dielectric116can include AlxOy, HfOX, ZrOx, TaOxor TiOX. In some embodiments, where ferroelectric dielectric layer130include a BiFeO3group of families, dielectric116can include AlxOy, HfOX, ZrOx, TaOxor TiOX. In the illustrative embodiment, level106further includes a via electrode118coupled with each memory device108. The via electrode118may include different structures. In each embodiment, the via electrode118includes at least one conductive hydrogen barrier, such as conductive hydrogen barrier120on the memory device108, a liner layer122on the conductive hydrogen barrier120and a conductive fill material124on the liner layer122. In the illustrative embodiment, the conductive hydrogen barrier120laterally surrounds the liner layer122, and the liner layer122laterally surrounds the conductive fill material124. The conductive fill material124may include a material such as tantalum, titanium, ruthenium, tungsten, molybdenum or copper. In the illustrative embodiment, the conductive hydrogen barrier120is on a portion of the uppermost surface108B and directly adjacent to the dielectric116. In one such embodiment, the conductive hydrogen barrier120and the dielectric116combine to provide a seal against hydrogen diffusion to uppermost surface108B and to sidewalls108A. Embodiments of the conductive hydrogen barrier120include a material that is amorphous. Amorphous materials lack defined grain boundaries that can facilitate hydrogen diffusion and are thus desirable. Embodiments of the conductive hydrogen barrier120include materials such as, but not limited to, TiAlN, with >30 atomic percent AlN, TaN, with >30 atomic percent N2, TiSiN, with >20 atomic percent SiN, Ta carbide, TaC, Ti carbide, TiC, tungsten carbide, WC, tungsten nitride, WN, carbonitrides of Ta, Ti, W, i.e., TaCN, TiCN, WCN, titanium monoxide, TiO, Ti2O, Tungsten oxide, WO3, Tin oxide, SnO2, indium tin oxide, ITO, Iridium Oxide, Indium Gallium Zinc Oxide, IGZO, Zinc Oxide or METGLAS series of alloys, e.g., Fe40Ni40P14B6(METGLAS is a Honeywell™). In some embodiments, the conductive hydrogen barrier120has a thickness that is dependent on WVE. In some embodiments, conductive hydrogen barrier120has a thickness that is less than 5 nm. It is to be appreciated that conductive hydrogen barrier120may include a material that is the same or different from the material of conductive hydrogen barrier114. The extent to which the dielectric116is on the memory device108is dependent on a lateral width, WMD, of the memory device108compared to a width, WVE, of the via electrode118. In some embodiments, as is illustrated inFIG.1C, the memory device108has a width, WMD, that is less than the width, WVE. In some such embodiments, dielectric116is directly in contact with sidewalls108A but not uppermost surface108B. In other embodiments, the via electrode118depicted inFIG.1C, extends below the uppermost surface108B of the memory device108, as illustrated inFIG.1D. In the illustrative embodiment, conductive hydrogen barrier120includes a portion120A that is adjacent to sidewall108A and below uppermost surface108B. To prevent shorting and/or cause device degradation, the conductive hydrogen barrier120does not extend below an interface123(indicated by dashed lines) between a ferroelectric oxide layer and one or more top electrode layers. As further illustrated, depending on a thickness of the conductive hydrogen barrier120and relative widths, WVEand WMDliner layer122may also have a portion at or below the uppermost surface108B. In the illustrative embodiment, liner layer122has a lower most portion that is substantially at a level of the uppermost surface108B. In some embodiments, liner layer122has a lower most portion that is at a level above the uppermost surface108B. In other embodiments, liner layer122has a lower most portion that is at a level below the uppermost surface108B. In some embodiments, the conductive hydrogen barrier120matches a contour of the uppermost surface108B as illustrated inFIG.1E. In some such embodiments, the combination of conductive hydrogen barrier120and the dielectric116provide barriers against hydrogen diffusion towards memory device108. Referring again toFIG.1A, the conductive interconnect102, electrode structure112and the memory device108can have widths that are substantially independent of each other. A spacing, SM, between adjacent memory devices108depends on which of the conductive interconnect102, electrode structure112and the memory device108has the largest width. In embodiments, when WESis greater than WMD, and WCI, as is shown, SMis determined by a spacing, SES, between the adjacent electrode structures112. In some such embodiments, SMis larger than SESand SMmay range between 20 nm and 50 nm. Reduction in SES, also leads to reduction in SM. However, dielectric116provides further advantages when SESis reduced. Dielectric116permits adequate insulation and prevents hydrogen from diffusing against sidewalls108A such that no spacer is needed between memory device108and dielectric116. Dielectric116may provide further advantages when SMis less than SES.FIG.1Fis a cross-sectional illustration of the device structure100B, in accordance with an embodiment of the present disclosure. Logic region101B is not shown for clarity. Device structure100B is an embodiment of the device structure100A. In the illustrative embodiment, WESis less than WMD, and WCI. When WESis less than WMD, and when WMDis greater than WCI, SMcan be less than SES, as shown. In some such embodiments, SM, can be between 20 nm and 50 nm. Reducing SMcan advantageously increase the density of memory devices per unit plan view area of device structure100B. While two memory devices108are shown, the memory region can include 1000 memory devices arranged in an array. In some embodiments, the spacing, SM, between adjacent memory devices108may be comparable to or less than height, TMD, of the memory device108. In some such embodiments, a single dielectric116including a material that can act as a barrier against hydrogen diffusion can be implemented without inclusion of spacers adjacent to memory devices108. In some embodiments, avoiding implementation of spacer layer adjacent to memory devices108can also help to tune the height, TMD, of memory device108. In some embodiments, SMmay depend on a total thickness of layers in the stack of the memory device108. In some embodiments, sidewalls108A are tapered as indicated by dashed lines125. The taper in sidewall108A can reduce SM. Taper in sidewall108A may increase with a taller stack (or an increase in TMD) further reducing SM. However, memory device108may need to have a minimum height for device functionality. In some such embodiments, a single dielectric such as dielectric116provides substantial advantages as density of memory devices108is increased because a single insulator material can be present in the space between two adjacent memory devices108. Reduction in SMreduces space to implement a spacer. In general, the lateral thicknesses WCI, and WEScan be independent of each other. A WESthat is greater than WCIor WCIand WMD, may determine choice of material of electrode structure112and conductive fill material115. The conductive fill material115may include a material such as tantalum, titanium, ruthenium, tungsten, molybdenum or copper. For example, when WESis greater than WMD, electrode structure112may not include a material such as copper to prevent sputtering of the electrode structure112during fabrication of the memory device108. When WESis less than WMD(as illustrated inFIG.1F) conductive fill material115may include copper. In some embodiments, depending on the material, the conductive fill material115can further include an adhesion liner115A and a fill metal115B on the adhesion liner115A as illustrated inFIG.1G. Referring again toFIG.1A, in different embodiments, WCIcan depend on a plan view shape of the conductive interconnect102. Conductive interconnect102and the electrode structure112can have a variety of plan view shapes as will be discussed below. The relative shapes (discussed below) of the electrode structure112and conductive interconnect102can determine relative alignment between sidewalls112A and102A. In some embodiments, the memory device108can be directly in contact with the conductive hydrogen barrier114, if WMDand WESare substantially similar and if there is positional misalignment. In some embodiments, etch stop layer113includes a material such as silicon, nitrogen and/or carbon. In exemplary embodiments, etch stop layer113includes a material that is different from the material of the dielectric116. The etch stop layer113and the electrode structure112have a thickness that is determined by a vertical thickness of the memory device108and thickness, T106, of the level106. As shown the etch stop layer113has a vertical thickness, TL, and the electrode structure112has a vertical thickness TES. In the illustrative embodiment, TL, is substantially equal to TES. As such an uppermost surface113A is co-planar or substantially co-planar with uppermost surface112B. In some embodiments, portions of the uppermost surface112B is concaved due to a processing methodology utilized. Thicknesses of conductive hydrogen barrier114and conductive fill material are determined by a desired TES. In most embodiments thickness of conductive fill material115is equal to or greater than that the thickness of the conductive hydrogen barrier114. Relative size of WCI, WESand WMD, can also provide flexibility in a thickness of the etch stop layer113or electrode structure112. In some examples when WESis greater than WMD, TESand TELcan be relatively thinner compared to when WESis less than WMDbecause of process margins to be discussed below. As shown, and via electrode118has a vertical thickness, TVE. Level106has a vertical thickness, T106that is substantially equal to a combined sum of TES, TMD, and TVE. It is to be appreciated that individual thicknesses TES, TMD, and TVEmay be co-dependently chosen to optimize performance of memory device108. For example, TMDmay vary between 30 nm and 90 nm and TESand TVEmay be adjusted co-dependently to balance T106. In the illustrative embodiment, logic region101B includes an interconnect structure127spanning levels104and106. Interconnect structure127includes one or more conductive interconnects in level104and one or more vias and metal lines coupled with conductive interconnect134in level106. In the illustrative embodiment, interconnect structure127includes conductive interconnect134in level104and a plurality of metal lines136and138, where metal line138is coupled with conductive interconnect134through via structure140. Metal line138may be coupled with a conductive interconnect through a via on a different plane, behind the plane of the illustration. In the illustrative embodiment, level106within the logic region further includes a dielectric142on the etch stop layer113, where dielectric142is directly adjacent to the dielectric116. Dielectric142includes a material that is designed to minimize electrical impact to logic circuitry, for example signal delays such as RC delays. Such electrical impact can arise due to scaling in feature sizes of metallic interconnects, such as vias and metal lines, as well as due to reduction in space between them. Increase in capacitive coupling and electrical resistance can increase signal delays. However, reducing a dielectric constant of the dielectric116can ameliorate electrical impact. Lowering the dielectric constant may be generally associated with increasing porosity in the film. Film porosity may be greater than 90 atomic percent by volume in dielectric116. In some embodiments dielectric142has a dielectric of approximately 3.5 or less. In embodiments dielectric142includes silicon and oxygen (such as low K SiO2). In the illustrative embodiment, dielectric142laterally surrounds at least a portion of the via structure140. Depending on TLan T106, dielectric142includes a material with a low film density (a film density much below 90% of theoretical material density) for example low density SiO2, carbon doped oxide (CDO), SiOC, SiCN, SiC, SiOxNy, F-doped oxides, or H-doped oxides. In the illustrative embodiment, etch stop layer113extends continuously from memory region101A to logic region101B. At least a portion of the via structure140is adjacent to the etch stop layer113, as shown. The etch stop layer113may be in contact with the conductive interconnect134depending on a lateral thickness of the via structure140. In some embodiments, such as is shown, at least a portion of the etch stop layer113is on the conductive interconnect134. Via structure140has a vertical thickness, TV, as measured from a lower most point of level104or from surface134A of conductive interconnect134, and metal line138has a vertical thickness, TM. In exemplary embodiments, a combined sum of TMand TVis equal to a combined sum of individual thicknesses TES, TMD, and TVE. In general, TMand TVEneed not be equal. In some embodiments, TVEis between 80%-100% of TM. In some embodiments, TMis between 20 nm and 50 nm. In other embodiments, TMis between 50 nm and 200 nm. In an embodiment, TMDhas a thickness between 10 nm and 100 nm and TEShas a thickness between 2 nm and 20 nm. In an embodiment, sum of TMDand TESis approximately between 85%-100% of TV. In some embodiments, TVis between 20 nm and 50 nm. In other embodiments, TVis between 20 nm and 150 nm. Conductive interconnect134has one or more properties of conductive interconnect102. Conductive interconnects102and134include a metal such as copper, cobalt, molybdenum, tungsten or ruthenium. In some embodiments, conductive interconnects102and134include a liner layer and a fill metal on the liner layer. For example, the liner layer may include a material, such as but not limited to, ruthenium, cobalt or tantalum and the fill metal may include copper, molybdenum or tungsten. Conductive interconnects102and134have a thickness that spans a portion of dielectric105within level104. There may be other vias and interconnect routing connections within level104that are not shown in the Figure. The conductive interconnects102and134may be discrete vias or continuous trenches, as will be discussed further below. In an embodiment, via structure140, metal lines136and138, include a same or substantially the same material. In the illustrative embodiment, via structure140, metal lines136each include a liner layer144and a fill material146on the liner layer144. For example, the liner layer144may include a material, such as but not limited to, ruthenium, cobalt, tantalum, or nitrides of tantalum and titanium, and the fill material146may include copper, molybdenum or tungsten. In some embodiments, via structure140and metal lines136and138, include a same or substantially the same material as the material of the conductive interconnect102. The substrate150may include a suitable substrate such as is utilized in semiconductor device fabrication and may comprise a material such as silicon, germanium, silicon germanium, group III-V materials, group III-N materials or quartz. FIG.1His an example of a device structure100C, that includes an electrode structure148that has a structure that is different from the electrode structure112depicted in the device structure100A ofFIG.1A. The electrode structure148includes conductive fill material115and conductive hydrogen barrier114, where the conductive hydrogen barrier114extends laterally above and in direct contact with conductive fill material115. In the illustrative embodiment, though conductive hydrogen barrier114does not laterally surround conductive fill material115, it forms a barrier between memory device108and the dielectric105. In the illustrative embodiment, conductive hydrogen barrier114has an uppermost surface that is co-planar or substantially co-planar with the uppermost surface of the etch stop layer113. Electrode structure148has a vertical thickness TES. In exemplary embodiments, TESis equal to or substantially equal to TL, as shown. In the illustrative embodiment, the electrode structure148has a lateral thickness WESthat is greater than WMD. In some such embodiments, memory device108is on a portion of the electrode structure148. Device structure100C is the same or substantially the same as device structure100A in all other regards. In other embodiments, WESof electrode structure148that is less than WMDas illustrated in device structure100D inFIG.1I. In the illustrative embodiment, memory device108is also on a portion of the etch stop layer113. While WESis less than WMD, the combination of etch stop layer113and conductive hydrogen barrier114provide adequate protection as a hydrogen barrier to memory device108. Device structure100D is substantially the same or substantially the same as device structure100C in all other regards. In some embodiments, the dielectric116may be separated from the memory device108by a layer of material that may be similar or different than the material of dielectric116.FIG.1Jis an illustrative embodiment of the device structure100A inFIG.1A, where an encapsulation layer152is inserted between the dielectric116and memory device108. The encapsulation layer152in device structure100E may include a material that is substantially similar to a material of the dielectric116or be different. In the illustrative embodiment, encapsulation layer152is directly adjacent to sidewalls108A, on a portion of electrode structure112and on the etch stop layer113. As shown, encapsulation layer152is on an uppermost surface108B and adjacent to conductive hydrogen barrier120, where WVEis less than WMD. In one or more embodiments, the encapsulation layer152can have a thickness, TEC, that varies between 1 nm and 5 nm. The encapsulation layer152may be substantially conformal with sidewalls108A and uppermost surface108B, as illustrated. But in other embodiments, an upper portion152A of the encapsulation layer152may be wider than TEC. The encapsulation layer152may extend over to a boundary between the memory region101A and logic region101B, as shown. As shown, encapsulation layer152is adjacent to dielectric142. The encapsulation layer152does not extend over the logic region101B to exclude material that is capable of possessing a high dielectric constant in a region filled with logic interconnect circuitry. In the illustrative embodiment, where WESis greater than WMD, the encapsulation layer152is in contact with both the conductive hydrogen barrier114and the conductive fill material115. In other embodiments, where WESis less than WMD, encapsulation layer152is not in contact with electrode structure112. In some embodiments, it is advantageous for TMDto be comparable to TES. For example, TMDmay be at most 2 times TES. In some such embodiments, TMDand TESCombined may not be equivalent to TVsuch as is illustrated inFIG.2A.FIG.2Ais a cross-sectional illustration of a device structure200A, in accordance with an embodiment of the present disclosure. Device structure200A includes many of the features of the device structure100A such as conductive interconnect102, electrode structure112, memory device108, via electrode118, conductive interconnect134, dielectric116, and dielectric142. In the illustrative embodiment, the device structure200A further includes a level202above level106. Level202includes a dielectric204on the dielectric116. For integration flexibility dielectric204may include a material having a lower film density than dielectric116. In some embodiments, dielectric204includes a material that is the same or substantially the same as the material of the dielectric142. In the illustrative embodiment, device structure200A includes an electrode structure205that is coupled with the memory device108. As shown, electrode structure205includes via electrode118and a contact electrode206on the via electrode118. Via electrode is adjacent to dielectric116and contact electrode206is adjacent to dielectric204. Electrode structure205includes layers that are contiguous with layers within via electrode118and contact electrode206. In the illustrative embodiment, via electrode118has one or more features of the via electrode118described in association withFIG.1A. Referring again toFIG.2A, conductive hydrogen barrier120within via electrode118includes a lateral portion120B that is on memory device108and a plurality of vertical portions120C. Vertical portions120C are directly adjacent to dielectric116. The via electrode also includes liner layer122and conductive fill material124. As shown, conductive hydrogen barrier120, liner layer122, and conductive fill material124are contagious within electrode structure205. The contact electrode206(within electrode structure205) includes vertical portions120C of conductive hydrogen barrier120, where vertical portions120C are adjacent to dielectric204. In the illustrative embodiment, contact electrode206has a width, WCthat is greater than a width WVE. In some such embodiments, the conductive hydrogen barrier120includes a portion that is on uppermost surface116A of dielectric116, as shown. As such, conductive hydrogen barrier120extends from the uppermost surface108B adjacent to dielectric116and dielectric204, to an uppermost surface204A. The conductive hydrogen barrier120, liner layer122within contact electrode206do not include lateral portions. The absence of lateral portions is an artifact of a co-fabrication process that is utilized to form electrode structure205, as will be discussed below. The liner layer122follows a contour of and is directly adjacent to the conductive hydrogen barrier120. Conductive fill material124includes a portion within the contact electrode118and a portion within contact electrode206. Dielectric116and conductive hydrogen barrier120combine to facilitate blocking of hydrogen such that dielectric204may include a porous, low density ILD material without impact to memory device108. A dielectric such as dielectric204that includes an ILD material facilitates fabrication of electrodes and lines within both the memory region101A and logic region101B in level202. Contact electrode206may be a via or a trench. Depending on embodiments, contact electrode206can have a width that is the same as the width of via electrode118or be different. In embodiments, where contact electrode206is a trench electrode206, contact electrode206may couple a plurality of via electrodes118above a respective memory device108, as will be discussed below. In other embodiments, as will be discussed below, contact electrode206may not include conductive hydrogen barrier120. In the illustrative embodiment, via electrode118and metal lines136and138are on two different levels. In the illustrative embodiment, metal lines136and138are within level202above via structure208. Via structure208includes one or more properties of via structure140such as material composition and lateral thickness. In some such embodiments, via structure208has a vertical thickness, TVthat is equal to a vertical thickness, T106, of level106. In the illustrative embodiment, TVis equivalent or substantially equivalent to sum of TES, TMDand TVE. It is to be appreciated that TVEcan be reduced to accommodate a taller stack (increase in TMD) for memory device108. As discussed earlier metal lines136and138have a vertical thickness TM. In the illustrative embodiment, TMis a thickness of level202. As shown, TM is also substantially equal to a vertical thickness TTE of contact electrode206. The electrode structure112inFIG.2Amay be replaced by an electrode structure148, as illustrated inFIG.2B, in accordance with an embodiment of the present disclosure. Device structure200B includes one or more features of the device structure200A other than the electrode structure148. It is to be appreciated that electrode structure148in device structure200B, may be wider than or narrower than the memory device108and conductive interconnect102. FIG.3Ais an isometric illustration of the device structure300A, in accordance with an embodiment of the present disclosure. Device structure300A includes many of the features of device structure100A described in association withFIG.1A. As shown, conductive interconnects102are discrete islands. Device structure300A further includes further features not illustrated inFIG.1Aas well as some variations in features of certain structures. Device structure300A includes a plurality of memory devices such as memory device302on plane304, behind a plane306of memory device108. Memory device302is substantially identical to and has all the properties of memory device108. In the illustrative embodiment, each of the memory devices108and302are coupled with a respective conductive interconnect102. As shown each conductive interconnect102has a discrete island structure (i.e., a conductive interconnect surrounded by dielectric105). The conductive interconnect102may include a variety of shapes. As illustrated conductive interconnect102is discrete, cylindrical, and spaced apart from an adjacent conductive interconnect102. In some such embodiments, lateral thickness or width, WCIis also a diameter. In the illustrative embodiment, the respective memory device108and memory device302have a cylindrical shape. In some such embodiments lateral thickness or width, WMD, is a diameter of the respective memory device108or memory device302. In the illustrative embodiment, electrode structure112also has a cylindrical shape. In some such embodiments WES, is a diameter of the electrode structure112. However, it is to be appreciated that the shape of the electrode structure112can be independent of the shape of the memory device108or302, or a shape of conductive interconnect102. As shown a portion of the conductive hydrogen barrier114is an annular shaped ring around the conductive fill material115. In the illustrative embodiment, each electrode structures112is spaced apart from an adjacent electrode structures112by a distance, SMalong the x-direction and along the y-direction. In embodiments, SMalong the x-direction and along the y-direction may be the same or different. In the illustrative embodiment, conductive interconnect134is a conductive trench interconnect134that extends along the y-direction. As shown, metal lines136and138also extend along the y-direction. In some embodiments, via structure140is conductive via between metal line138and conductive trench interconnect134. In other embodiments, interconnect structure127can include a plurality of vias such as via structure140between metal line138and conductive interconnect134to prevent an increase in electrical line resistance. In other embodiments, via structure140may be replaced by a metal line (not illustrated). In some embodiments, conductive interconnect102is a trench interconnect308, as illustrated in device structure300B ofFIG.3B. Only the memory region101A is illustrated for clarity. The trench interconnect308may continuously extend continuously from under memory device108on plane306to under memory device302on plane304, as shown in the cross-sectional illustration ofFIG.3C. In the illustrative embodiment, the trench interconnect308couples a lower most electrode of memory device108and302along a length of the trench (along the y-direction). In embodiments, trench interconnect308includes a material that is the same or substantially the same as the material of the conductive interconnect102. Trench interconnect308is not exposed to memory device108or302during memory device fabrication. As shown, the conductive hydrogen barrier114and the etch stop layer113act as a collective hydrogen barrier. Referring again toFIG.3B, because the etch stop layer113extends over the trench interconnect308, the electrode structure112can have a shape and/size that is independent of the shape of trench interconnect308. It is also to be appreciated that electrode structure112can be offset along the x or the y direction relative to the trench interconnect308, without loss of device functionality, as long as there is at least 50% overlap. As shown, trench interconnect308has a lateral thickness, WTI. In general, WTImay be equal to, less than or greater than WES. In the presence of a trench interconnect308, etch stop layer113may be thicker than in the presence of conductive interconnect102(illustrated inFIG.3A). In the presence of a trench interconnect308, while the trench interconnect308can be narrower than electrode structure112, e.g., along x-direction, trench interconnect308is wider than that electrode structure112along the y-direction. A thicker etch stop layer113may advantageously provide sufficient material while patterning to form memory devices108and302(along the y-direction) as will be discussed below. As discussed above, the shape of the electrode structure112may be independent of the trench interconnect308or the memory device108. The electrode structure112(depicted inFIG.3B) has a cylindrical shape. However, the electrode structure112can be rectangular in other embodiments, such as is illustrated inFIG.3D(the etch stop layer113or dielectric116is not shown for clarity). As shown, the conductive interconnect102, in the memory region101A are discrete islands, however, electrode structure112is a trench electrode structure310that couples two or more memory devices108. Trench electrode structure310may extend laterally from above a conductive interconnect102on plane306to above conductive interconnect102on plane304, behind plane306. As such, trench electrode structure310couples a lower most electrode of the respective memory devices108and302. Trench electrode structure310provides enhanced flexibility to couple a selected number of memory devices along a row without having to provide a continuous trench. The flexibility to choose the number of devices and groups of devices can provide additional electrical advantages such as for programming. Trench electrode structure310has one or more properties of electrode structure112, such as conductive hydrogen barrier114and conductive fill material115. As shown, conductive hydrogen barrier114extends along the length and width LTEand a width WTE. In some embodiments, WTEis smaller or greater than WMD, or WCI. As shown, WTEis greater than WMD, and WCI. LTEis substantially greater than WCI. Although as illustrated, WTEis greater than WCI, in other embodiments, WTEcan be less than WCIwithout loss of functionality. Furthermore, as explained above, WMDcan be independent of WTE. FIG.4Ais an isometric illustration of device structure400, in accordance with an embodiment of the present disclosure. Device structure includes one or more features of the device structure200A illustrated inFIG.2. In the illustrative embodiment, contact electrode206extends from memory device108to memory device302(along y-direction). In other embodiments, contact electrode206connects two or more adjacent memory devices108(along x-direction). FIG.4Bis a cross-sectional illustration through a line A-A′ of the structure inFIG.4A. As shown, conductive hydrogen barrier120extends continuously from a first sidewall206A of contact electrode206above memory device108to a second sidewall206B. In the illustrative embodiment, liner layer122is adjacent to conductive hydrogen barrier120and conductive fill material124fills extends continuously from above memory device108to memory device302. FIG.5is a flow diagram to form memory devices in a memory region and conductive interconnects in a logic region, in accordance with some embodiments of the present disclosure. Some operations can be performed simultaneously or out of order. The method begins at operation510, with the formation conductive interconnects in a dielectric in a memory region and in an adjacent logic region. The method500continues at operation520with the deposition of an etch stop layer on the dielectric and on the conductive interconnects. The method continues at operation530with the formation of electrode structures including a conductive hydrogen barrier material on each of the conductive interconnects, in the memory region. The method continues at operation540with the process to etch a material layer stack deposited on the electrode material to form a memory device above a respective conductive interconnect in the memory region. The method continues at operation550with the deposition of a first dielectric including a high density film and forming a via electrode including a conductive hydrogen barrier material on a respective memory device. The method continues at operation560with a process to etch and remove the first dielectric from the logic region and replacing with a second dielectric including a porous material. The method continues at operation570with a formation of a hanging trench in the second dielectric in the logic region. The method continues at operation580with the formation of via opening below the hanging trench and exposing a conductive interconnect. The method concludes at operation590with the formation of a via structure in the via opening and a metal line in the hanging trench. FIG.6Ais a cross-sectional illustration of a plurality of conductive interconnects102and134formed within dielectric105above a substrate600. In the illustrative embodiment, conductive interconnects102, are formed in a memory region and conductive interconnect134is formed in a logic region. In exemplary embodiments, there may be one or more levels of transistors and interconnects between conductive interconnects102and134and substrate600. In high density memory applications, the number of conductive interconnects102and134can range between 1K and 5K within a given array in memory region101A. Conductive interconnects102and134have a lateral thickness, WCI, that may be determined by a minimum acceptable electrical resistance. In some embodiments, conductive interconnects102are discrete structures that are substantially, rectangular, circular or elliptical in plan-view shape and conductive interconnect134is a trench line (extending into the plane of the Figure). In some embodiments, conductive interconnects102have a lateral thickness between 20 nm and 40 nm. For example, conductive interconnects102may have a lateral thickness between 20 nm and 40 nm, along the x-direction, as shown. In other embodiments, conductive interconnects102and134are trenches that extend into the plane of the Figure. The conductive interconnects102and134may have shapes that are independent of each other. As shown, conductive interconnects102have substantially the same lateral thickness to minimize variability in device performance. In some embodiments, the conductive interconnects102and134are electrically and mechanically coupled with vias and/or lines such as via601and/or line601indicated in dashed boxes in the Figure. The via601and/or line601may include a same or substantially the same material as a material of the conductive interconnect102. In some embodiments, conductive interconnects102and134include a liner layer and a fill metal on the liner layer. For example, the liner layer may include a material, such as but not limited to, ruthenium, cobalt or tantalum and the fill metal may include copper or tungsten. In one or more embodiments, conductive interconnects102and134include copper fill metal on a ruthenium or a tantalum liner. In an embodiment, each of the conductive interconnects102are separated by spacing Sic. Sic is substantially determined by a designed density of memory devices to be fabricated within a given area, as well as by underlying structures embedded within layers below conductive interconnects102. In various embodiments, substrate600includes a material that is the same or substantially the same as the material of the substrate150described in association withFIG.1A. FIG.6Bis a cross-sectional illustration of the structure inFIG.6Afollowing the process to deposit an etch stop layer113on conductive interconnects102and134as well as on the dielectric105. Etch stop layer113is deposited to a thickness, TEDthat is chosen to accommodate a height of an electrode structure to be formed. For example, the as deposited thickness, TED, may include process margins for multiple planarization processes to be utilized. TEDis also chosen to provide sufficient material against etch erosion during process to form memory devices in the memory region101A. The etch stop layer113also functions as a diffusion barrier layer. A diffusion barrier is essential for preventing diffusion of copper from conductive interconnect134, and hydrogen during downstream process to the memory devices to be formed or other devices within the logic region. As such, etch stop layer113includes a material such as, but not limited to, silicon nitrogen and one or more of, oxygen or carbon. FIG.7Ais a cross-sectional illustration of the structure inFIG.7Afollowing the process to etch openings701in etch stop layer113to form electrode structures. In an embodiment, photoresist mask702is formed by a lithographic process on etch stop layer113. Exposed portions of etch stop layer113may be etched by a plasma etch process through opening in the photoresist mask702. In the illustrative embodiment, the openings701have a lateral thickness, WO. WOmay be substantially the same across various openings701that are designed to form electrode structures. WOmay be narrower, equal to or wider than WCIof conductive interconnects102. In the illustrative embodiment, WOis less than WCI. The substrate600is not illustrated inFIGS.6B-14C, for clarity. Shape of openings701may be circular or rectangular and the conductive interconnects may be discrete islands or trenches depending on embodiments.FIGS.7A-7Cillustrate different embodiments (for example portions704A,704B and704C) of a portion704of the conductive interconnect and opening inFIG.7A. The photoresist mask702is removed for clarity. FIG.7Bis an isometric illustration of a portion704A of the structure inFIG.7A, in accordance with an embodiment of the present disclosure. A cross section through opening701is illustrated. In the illustrative embodiment, the conductive interconnect102is cylindrical, where WCIis less than WO, (for example diameter) of opening701. As shown opening701is circular and WOmay be, for example, a diameter of the opening701. In other embodiments, opening701can be rectangular and/or extend over two or more conductive interconnects, such as for example, conductive interconnects102. The dielectric105is exposed during formation of the openings701when WCIis less than WO, as shown. In the illustrative embodiment, uppermost surface102B of conductive interconnect102is co-planar or substantially co-planar with uppermost surface105A of dielectric105. In some embodiments, the conductive interconnect within portion704C is a trench interconnect308as illustrated inFIG.7C. In some such embodiments, the openings701expose different portions of uppermost surface308A of trench interconnect308. In the illustrative embodiment, WTIis less than WOand openings701expose uppermost surface105A of the dielectric105. In the illustrative embodiment, uppermost surface308A of trench interconnect308is co-planar or substantially co-planar with uppermost surface105A. In the illustrative embodiment, opening701is circular. However, in other embodiments, the opening701can be rectangular as indicated by dashed lines705. While it is desirable for the opening701to be substantially aligned with sidewalls of trench interconnect308, in some embodiments, the opening701may be offset relative to trench interconnect308, as is illustrated in portion704C inFIG.7D. Such an offset may be a result of misalignment between photoresist mask702and the trench interconnect308(or a conductive interconnect in other embodiments). The method adopted to fabricate an electrode structure within opening701is not impacted by misalignment as long as at least 50% of the opening701exposes the uppermost surface308A of trench interconnect308. Misalignment does not enable hydrogen to diffuse through to the memory device108(not shown). FIG.8Ais a cross-sectional illustration of the structure inFIG.7Afollowing the process to deposit one or more electrode materials on the conductive interconnects102and on etch stop layer113. In an embodiment, a conductive hydrogen barrier material800is deposited in the opening701, on sidewalls of etch stop layer113and on the conductive interconnect102. In the illustrative embodiment, conductive hydrogen barrier material800is also deposited on exposed portions of the dielectric105. A fill material802is filled in remaining portions of opening701on the conductive hydrogen barrier material800. Depending on the type of material chosen for fill material802, a liner layer (indicated by dashed lines803) may be first deposited on the conductive hydrogen barrier material800and then the fill material802is deposited on the liner layer. In embodiments the conductive fill material115includes tantalum, titanium, ruthenium, tungsten or copper. FIG.8Bis a cross-sectional illustration of the structure inFIG.8Afollowing the process to planarize the fill material802and the conductive hydrogen barrier material800. In an embodiment, the planarization process includes a chemical mechanical planarization (CMP) process. The CMP process removes the fill material802and the conductive hydrogen barrier material800from an uppermost surface113A of the etch stop layer113. The planarization process isolates the conductive hydrogen barrier material800to form a conductive hydrogen barrier114and the fill material802to form a conductive fill material115 The CMP process may also reduce the as deposited thickness of the etch stop layer113to a thickness TEC. TECmay be substantially uniform across the memory and logic regions101A and101B, respectively. There may be variations in thicknesses of up 5% from the CMP processing due to the presence of the electrode structures. Additionally, in some embodiments, the conductive fill material115may be dished (or recessed in a concave manner) as indicated by dashed lines805. A concaved profile may change a surface profile of each layer within a memory device to be formed. The extent of dishing may be dependent on WCIand on a pattern density of and spacing between the electrode structures112. FIG.8Cis a cross-sectional illustration of the structure inFIG.8Bfollowing the process to form material layer stack806on the electrode structure112and on the etch stop layer113. The process to form material layer stack806includes blanket deposition of at least three material layers, where the number further depends on a type of memory device to be fabricated. In some embodiments, the material layer stack806includes deposition of layers for a ferroelectric memory device. In other embodiments, the material layer stack806includes deposition of layers for a paraelectric memory device. In an embodiment, individual layers of material layer stack806(for a ferroelectric memory device) are deposited in situ, i.e., without breaking vacuum. Material layer stack806may be deposited by an atomic layer deposition (ALD) process, a plasma enhanced chemical vapor deposition (PECVD), chemical vapor deposition (CVD), a physical vapor deposition (PVD) process or a combination thereof. In some embodiments, conductive layer806A is blanket deposited on electrode structure112and on etch stop layer113. In an embodiment, conductive layer806A includes a conductive ferroelectric oxide. The conductive ferroelectric oxide includes one of a non-Pb perovskite metal oxides, such as but not limited to, La—Sr—CoO3, SrRuO3, La—Sr—MnO3, YBa2Cu3O7, Bi2Sr2CaCu2O8, or LaNiO3. Conductive layer806A is deposited to a thickness, T1, that is suitable for minimizing electrical resistance and to minimize tapering of sidewalls during a patterning process that will be utilized to fabricate memory devices. In some embodiments, conductive layer806A has a thickness that is between 3 nm and 30 nm. A thickness of less than 30 nm is highly desirable to prevent significant tapering in sidewalls during the patterning process. In an embodiment, the deposition process is continued by deposition of a dielectric layer806B (for example, a ferroelectric dielectric layer806B for a ferroelectric memory device). The dielectric layer806B may be blanket deposited on the conductive layer806A. Dielectric layer806B has a thickness, T2, that is between 1 nm and 30 nm. In some embodiments, dielectric layer806B includes non-Pb Perovskite material in the form ABO3, where A and B are two cations of different sizes and O is oxygen. A is generally larger than B in size. In some embodiments, non-Pb Perovskites can also be doped, e.g., by La or Lanthanides. The non-Pb Perovskite material can include one or more of La, Sr, Co, Cr, K, Nb, Na, Sr, Ru, Y, Fe, Ba, Hf, Zr, Cu, Ta, Bi, Ca, Ti and Ni. In other embodiments, dielectric layer806B includes a low voltage ferroelectric material sandwiched between the conductive oxide layers (806A and806C). Low voltage materials can be of the form AA′BB′O3, where A′ is a dopant for atomic site A and can be an element from the Lanthanides series and B′ is a dopant for atomic site B and can be an element from the transition metal elements such as Sc, Ti, V, Cr, Mn, Fe, Co, Ni, Cu, Zn. A′ may have the same valency of site A, with a different ferroelectric polarizability. A voltage below 3 Volts is sufficiently low to be characterized as low voltage. The deposition process is continued with a deposition of conductive layer806C on dielectric layer806B. In an exemplary embodiment, the conductive layer806C includes a material that is the same or substantially the same as the material of conductive layer806A. When conductive layers806A and806C include the same material, the material layer stack is symmetric. In different embodiments, conductive layer806C can have a different thickness than conductive layer806A. In embodiments, conductive layer806C is deposited to a thickness, T3, between 3 nm and 30 nm. Conductive layer806C between 3 nm and 30 nm can facilitate the patterning process. In some embodiments, such as is shown, the deposition process concludes with the formation of hardmask layer808on conductive layer806C. In some embodiments, hardmask layer808is blanket deposited by a PECVD, CVD or PVD process. In an embodiment, hardmask layer808includes a material that has a favorable etch selectivity compared to the ferroelectric materials in material layer stack806. In some embodiments, hardmask layer808includes materials that can be patterned with high fidelity with respect to a masking layer formed on hardmask layer808, for example SiO2, Si3N4, DLC (Diamond Like Carbon) or Al2O3. In other embodiments, hardmask layer808includes a conductive material that is different from the conductive material of the ferroelectric material. In some embodiments it is desirable to deposit hardmask layer808to a thickness, T4, that enables patterning of at least the conductive layer806C. In other embodiments, hardmask layer808may deposited to a thickness, T4, that depends on a total thickness of material layer stack806. T4may be at least 20 nm. In a different embodiment, hardmask layer808includes a bilayer where the bilayer includes a metallic layer and a dielectric on the metallic layer. In an embodiment, photoresist mask810is formed on hardmask layer808and is formed by a lithographic process. The photoresist mask810includes blocks810A and810B. Each block810A-810B is a mask for patterning a discrete memory device, such as for example a ferroelectric memory device. In an embodiment, the dielectric layer806B includes paraelectric materials. Paraelectric materials may include: SrTiO3, Ba(x)Sr(y)TiO3 (where x is −0.05, and y is 0.95), HfZrO2, Hf—Si—O, La-substituted PbTiO3, or a PMN-PT based relaxor ferroelectrics. In some embodiments, material layer stack including paraelectric materials can range from 5 nm to 100 nm in total thickness. FIG.8Dis a cross-sectional illustration of the structure inFIG.8Cfollowing the process to pattern hardmask layer808and the material layer stack806. In an embodiment, hardmask layer808is etched by a plasma etch process. The plasma etch process may include a discharge produced by a magnetic enhanced reactive ion etching mechanism, an electron cyclotron resonance discharge or an inductively coupled plasma discharge. The plasma parameters may be characterized by a range of plasma densities such as between 1e9-1e12 ions/cm3, pressures in the range of 0.001-10 Torr, and electron temperatures in the range of 1-8 eV. Ions may be accelerated to the surface from a plasma sheath by means of electrostatic chuck with biasing capabilities that are independent of the power delivered to sustain various plasma configurations. It is highly desirable to pattern hardmask layer808to have substantially vertical side walls to prevent increase in a width when patterning the remaining layers in material layer stack806. A CHXFY(fluorocarbon) O2and Ar based gas combination may be utilized to etch hardmask layer808to form hardmask133in one of the three different plasma discharges described above. In an exemplary embodiment, hardmask133has a substantially vertical profile relative to a lowermost surface128A. In some embodiments, photoresist mask810is removed after forming hardmask133. The plasma etch process is continued to pattern conductive layer806C. Hardmask133is utilized to etch conductive layer806C. In an embodiment, a plasma etch process is utilized to etch the conductive layer806C to form a top electrode132. In the illustrative embodiment, top electrode132has substantially vertical sidewalls132A. In some embodiments, hardmask133is removed during the plasma etch process as indicated by dashed lines, when the hardmask133includes a dielectric material. The etch process is continued to etch dielectric layer806B to form etched dielectric layer130(herein dielectric layer130). The plasma etch process is continued to etch and form a bottom electrode128. In an embodiment, the process utilized to etch conductive layer806A (FIG.8C) to form bottom electrode128may be substantially the same as the etch process utilized to form top electrode132. In the illustrative embodiment, sidewalls of the memory device108are substantially vertical respect to a normal to lowermost surface128A. The process of forming the top electrode132, dielectric layer130, bottom electrode128also completes formation of memory device108. FIG.9Ais a cross-sectional illustration of the structure inFIG.8Dfollowing the process to deposit a dielectric116and following a process to planarize the dielectric116. In an embodiment, dielectric116can be deposited by an atomic layer deposition (ALD) process, a plasma enhanced chemical vapor deposition (PECVD), chemical vapor deposition (CVD), a physical vapor deposition (PVD) process or a combination thereof. In an embodiment, the dielectric includes a transition metal and oxygen, such as for example AlxOy, HfOX, ZrOx, TaOx, TiOx, AlSiOx, HfSiOXor TaSiOx. In other embodiments, dielectric116includes a nitride of Al, Zr or Hf, for example AlN, ZrN, or HfN. Some of the dielectric materials may be deposited by a process that utilizes hydrogen or ammonia containing precursor chemicals, while other materials may be deposited by a process that does not utilize hydrogen or be performed in an environment where hydrogen may be present. In some embodiments, deposition of dielectric116is performed by a combination of processing operations. A first operation may utilize a physical vapor deposition process to deposit a material including a transition metal and oxygen, such as but not limited to AlxOY, HfOX, ZrOX, TaOX, TiOX, AlSiOX, HfSiOX, TaSiOX, or a transition metal and nitrogen such as but not limited to AlN, ZrN, or HfN. A second operation may be subsequently performed where one or more of AlXOY, HfOX, ZrOX, TaOX, TiOX, AlSiOX, HfSiOX, TaSiOX, AlN, ZrN, or HfN may be deposited by a process that may or may not utilize a hydrogen precursor. In other embodiments, dielectric116may include a same material sequentially deposited by two different deposition methods. For example, a first deposition process may be utilized to deposit a material in a hydrogen free environment, and a second deposition process may be utilized to deposit the same material that utilizes hydrogen. The advantage of this dual deposition operation is important when spacing, SM, between adjacent memory devices108approaches 2-3 times a thickness of the material deposited by the first deposition process. In some such embodiments, a thin layer of dielectric116B (within dashed lines902) is deposited on the memory device108and on etch stop layer113. A physical vapor deposition (PVD) process can be utilized to deposit thin layer of dielectric116B to a thickness of less than 5 nm, where the deposition process does not expose the memory device108to hydrogen. In some embodiments, the PVD deposited material may have a wider portion adjacent to uppermost surface108B and a narrower portion on sidewall108A, as shown. The second deposition process may utilize a combination of CVD and ALD processes to provide uniform deposition, for example between adjacent memory devices108. In some such embodiments, the dielectric116includes a same material as the material of the thin layer of dielectric116B. In other embodiments, where SMis 20 nm or less, a dual deposition process described above can form a keyhole or an air gap between adjacent memory devices108. Some of the dielectric116materials can be deposited by a single ALD deposition process because they may be deposited by a hydrogen free precursor. In other embodiments, a first process may include ALD to deposit thin layer of dielectric116B, followed by a bulk dielectric deposition using a CVD or a PVD process. It is to be appreciated that thin layer of dielectric116B may include a different material than dielectric116. Such an embodiment is described below in association withFIGS.22A-22D. In the illustrative embodiment, the dielectric116is blanket deposited on the memory device108, on exposed portions of conductive fill material115and conductive hydrogen barrier114. The dielectric116is deposited to a vertical thickness, TDL, that is equal to or greater than a height of a via to be fabricated in the logic region101B. The material of the dielectric116can be chosen based on the material of the ferroelectric dielectric layer130in the memory device108, as discussed above. By pairing the dielectric116with the ferroelectric dielectric layer130can minimize lattice dislocations that can cause voids and potential pathways for hydrogen diffusion. In some embodiments, the plasma etch process described in association withFIG.8Dcan recess portions of the conductive fill material115. The shape of resulting conductive fill material115and resulting structure of dielectric116is illustrated with respect to portions900inFIGS.9B and9C.FIG.9Bis a cross-sectional illustration of the structure within portion900inFIG.9A, in accordance with an embodiment of the present disclosure. In some such embodiments, conductive fill material115, as shown in portion900A, may have surfaces that are at different levels or recessed relative to uppermost surface115C. For example, as shown, conductive fill material115includes a surface115D that is recessed relative to uppermost surface115C, where the uppermost surface115C and a lower most surface of memory device108meet at interface901. In some such embodiments, the surface115D may be substantially planar, and sidewall115E may be substantially vertical as shown. In some embodiments, the conductive hydrogen barrier114can be substantially unimpacted by the etch process as shown. In the illustrative embodiment, dielectric116also fills the space above the surface115D and below an interface901between memory device108and the conductive fill material115. When dielectric116is deposited, dielectric116is contact with surface115D, sidewall115E and vertical portion114B of conductive hydrogen barrier114. In other embodiments, the conductive fill material115is recessed with less well defined surfaces and sidewalls compared to conductive fill material115inFIG.9B.FIG.9Cis a cross-sectional illustration of the structure within portion900inFIG.9A, in accordance with an embodiment of the present disclosure. As shown in portion900B, exposed surfaces of conductive fill material115are recessed to produce a gradually sloped surface away from the sidewall of memory device108. The sloping surface is curved as shown. The conductive fill material115has a thickness TFMas measured from the interface901between the conductive fill material115and memory device108. TFMdecreases from a maximum thickness, TFMX, under the memory device108to a min thickness TFM1where conductive fill material115is directly in contact with vertical portion114B of conductive hydrogen barrier114. TFMchanges along the x-direction. As shown, TFMdecreases away from sidewall108A. In the illustrative embodiment, dielectric116also fills the space above the sloping surface115F and below an interface901between memory device108and conductive fill material115. When dielectric116is deposited, dielectric116is contact with surface115F and sidewall portion114B of conductive hydrogen barrier114. In some embodiments, where WESis less than WMD, memory device108is in contact with an uppermost surface113A of etch stop layer113as shown in portion900D inFIG.9D. In some embodiments, the plasma etch process utilized to form memory device108will also recess portions of the uppermost surface113A that is not covered by the memory device108. In some such embodiments, the dielectric116is also deposited below an interface903between the memory device108and etch stop layer113. The dielectric116is in contact with sidewall113B and recessed surface113C. The etch stop layer113has a thickness TLas measured from the interface903between the etch stop layer113and memory device108. TLdecreases from a maximum thickness, TLX, under the memory device108to a min thickness TL1away from sidewall108A. As shown, TLis substantially uniform away from sidewall108A. In other embodiments, where WESis less than WMD. the etch stop layer113is recessed with less well defined surfaces and sidewalls compared to etch stop layer113inFIG.9D. As shown in portion900E ofFIG.9E, exposed surfaces of etch stop layer113are recessed to produce a gradually sloped surface away from the sidewall of memory device108. The sloping surface is curved as shown. The etch stop layer113has a thickness TLas measured from the interface903between the etch stop layer113and memory device108. TLdecreases from a maximum thickness, TLX, under the memory device108to a min thickness, TL1, away from sidewall108A, TL1decreases away from sidewall108A. In the illustrative embodiment, dielectric116also fills the space above the sloping surface113D and below an interface903. When dielectric116is deposited, dielectric116is contact with surface113D. In various embodiments, discussed with reference toFIGS.9B-9D, conductive hydrogen barrier114, etch stop layer113and dielectric116combine to provide a conductive and an insulative hydrogen barrier. FIG.10Ais a cross-sectional illustration of the structure inFIG.9Afollowing the process to form openings1000in the dielectric116through a mask1001. The openings1000may have sidewalls that are substantially vertical or flared. In the illustrative embodiment, the sidewalls of opening1000are substantially vertical. Mask1001may be formed on the dielectric116by a lithographic process. The openings1000may be formed by a plasma etch process that etches dielectric116but is selective to top electrode132of memory device108. In some embodiments, the opening1000exposes a portion of the uppermost surface108B of the memory device108. In other embodiments, the openings1000are wider and expose an entire upper most surface108B. In some embodiments, when openings1000exposes the entire uppermost surface108B, etch process may recess portions of dielectric116adjacent to top electrode132. In some embodiments, openings1000can have a depth Do, between 30 nm-70 nm. The Do may be larger than a final vertical thickness of via electrode that is fabricated due to plurality of planarization process operations to be utilized. FIG.10Bis a cross-sectional illustration of the structure inFIG.10Afollowing the process to deposit materials to form via electrodes. In the illustrative embodiment, conductive hydrogen barrier material1002is blanket deposited into the openings1000, on the memory device108and on sidewall of dielectric116. The conductive hydrogen barrier material1002includes a material that is compatible with the dielectric116so that an interface1004between the conductive hydrogen barrier material1002and the dielectric116is not a source of dislocations. In an embodiment, a liner layer material1006is blanket deposited in the openings1000, and on the conductive hydrogen barrier material1002. A layer of fill metal1008is deposited into the remaining portions of openings1000on the liner layer material1006. In embodiments, the conductive hydrogen barrier material1002, the liner layer material1006and layer of fill metal1008are deposited by an ALD, PVD or sputter deposition process. FIG.10Cis a cross-sectional illustration of the structure inFIG.10Bfollowing the process to planarize and form a via electrode118on each memory device108and following the process to remove dielectric116from the logic region101B. In an embodiment, the planarization process includes a chemical mechanical planarization (CMP) process. The CMP process removes layer of fill metal1008, liner layer material1006and the conductive hydrogen barrier material1002from an uppermost surface116A of the dielectric116. The planarization process isolates the conductive hydrogen barrier material1002to form a conductive hydrogen barrier114, liner layer material1006to form liner layer122and the layer of fill metal1008form conductive fill material124within the openings1000. The CMP process may also reduce the as deposited thickness of the dielectric116. After the process to fabricate via electrodes118. A mask1010is formed on the dielectric116to further pattern and remove the dielectric116from the logic region101B. It is to be appreciated that while dielectric116is utilized to block diffusion of hydrogen toward memory device108, dielectric116includes a material that has a high film density. Dielectric116may also have a higher than desirable dielectric constant capable of increasing capacitance to the logic interconnect circuitry. It is advantageous to replace the dielectric116in the logic region101B with a dielectric that is compatible with interconnect circuitry. In an embodiment, a plasma etch process is utilized to etch the dielectric116, form an opening1011and expose the etch stop layer113in logic region101B. In some embodiments the dielectric116has a sidewall profile that is substantially vertical. In other embodiments. Sidewall116A is tapered as indicated the dashed line1012. FIG.10Dis a cross-sectional illustration of the structure inFIG.10Cfollowing the process to deposit a dielectric142in the logic region101B and planarizing the dielectric142. In an embodiment, the dielectric142is blanket deposited on the etch stop layer113, on the dielectric116and on via electrodes118. The blanket deposition may be carried out by an ALD, PVD, PECVD, or a CVD process. After deposition the dielectric142is planarized. The planarization process is designed to leave a dielectric142having a vertical thickness, To, that will accommodate fabrication of a via structure and metal lines within the dielectric142. In the illustrative embodiment, the dielectric116has an uppermost surface116A that is co-planar or substantially co-planar with an uppermost surface142A of dielectric142. Also as shown, uppermost surfaces118A of via electrodes118are co-planar or substantially co-planar with the uppermost surface142A, and116A. FIG.10Eis a cross-sectional illustration of the structure inFIG.10Dfollowing the process to form mask1013on dielectrics116and142, and on the via electrodes118, and following the process to etch dielectric142to form hanging trench openings1014A and1014B in logic region101B. Mask1013is designed to form an interconnect structure in logic region101B. In an embodiment, mask1013is formed by a lithographic process and includes a photoresist material. In different embodiments, DHcan be equal, less than or greater than DV. In general DHmay depend on interconnect circuitry within level106. In an embodiment, a plasma etch process is utilized to etch dielectric142through openings in mask1013to form hanging trench openings1014A and1014B. Dielectric142may be etched to a depth, DHand a width, WH, that is determined by a thickness TO, of dielectric142above the etch stop layer113. DHis measured relative to an uppermost surface142A. In embodiments, DHranges between 10 nm and 50 nm and WHranges between 10 nm and 200 nm. WHis determined by a width of interconnect vias to be formed within the trench. DHmay be set by a height and width of a via to be formed within hanging trench opening1014A. The height and width of a via is determined by a desired minimum line conductance of the via and a metal line to be formed within hanging trench opening1014A. FIG.10Fis a cross-sectional illustration of the structure inFIG.10Efollowing the process to form a form a via mask1015within the hanging trench in logic region101B. In an embodiment, mask utilized to form hanging trench openings1014A and1014B is removed and a via mask1015is formed. In an embodiment, via mask1015is formed by a lithographic process and includes a photoresist material. Via mask1015has an opening1017within hanging trench opening1014A that is designed to enable etching dielectric142to form a via opening in a subsequent operation. The opening1017has a lateral thickness WV. The opening may be symmetric about the hanging trench opening1014A or offset. WVcan range between 25%-75% of WH. FIG.10Gis a cross-sectional illustration of the structure inFIG.10Ffollowing the process to etch dielectric142to form a via opening1017A below the hanging trench opening1014A in logic region101B. In an embodiment, a plasma etch process is utilized to form via opening1017A by etching the dielectric142and etch stop layer113. In an embodiment, the dielectric142is first etched and the etch is halted after exposing etch stop layer113. The plasma etch process is continued with a different chemistry to etch stop layer113. An advantage of the process methodology outlined herein, is that etch stop layer113has a thickness, TL, that is determined by a deposition process and by the formation of electrode structure112in memory region101A. Formation of via opening1017A within etch stop layer113can be targeted and tuned by fixing a thickness of the etch stop layer113to a desired thickness. In the illustrative embodiment, the formation of via opening1017A exposes an uppermost surface134A of conductive interconnect134. The via opening1017A may have a first slope within dielectric142and a second slope within etch stop layer113due to a difference in material between the dielectric142and etch stop layer113. FIG.10His a cross-sectional illustration of the structure inFIG.10Gfollowing the process to remove mask utilized to form via opening within the hanging trench opening1014A and deposit a conductive material into the openings to form via structure140, and metal lines136. Mask utilized to form via opening1017A is removed and a conductive material is deposited into the hanging trench openings1014A and1014B and via opening1017A. In an embodiment, depositing the conductive material includes depositing a liner layer1018in the via opening1017A, hanging trench opening1014A, and1014B. In some such embodiments, the liner layer1018is also deposited on uppermost surface134A of the conductive interconnect134, on sidewalls of etch stop layer113, dielectric142, on uppermost surface142A and on surfaces of via electrodes118. A fill material1020is deposited on the liner layer1018. In some embodiments, fill material1020includes copper, tungsten, nickel or cobalt, and liner layer1018includes ruthenium tantalum, or nitrides of tantalum or titanium. In other embodiments where no liner is implemented a fill metal or a conductive material is directly deposited on uppermost surface134A of the conductive interconnect134, on sidewalls of etch stop layer113, dielectric142, on uppermost surface142A and on surfaces of via electrodes118. A planarization process may be utilized to remove an excess conductive material deposited on dielectric142and on via electrodes118. In an embodiment, the planarization process includes a chemical mechanical polish (CMP) process. The CMP process isolates metal lines136and138within hanging trench openings1014A and1014B. Via structure140is formed at the same time as metal line138. The liner layer is contiguous between via structure140and metal line138and fill material1020extends continuously from metal line138to via structure140. In the illustrative embodiment, uppermost surfaces118A of via electrode118and uppermost surfaces136A,138A of metal line are co-planar or substantially co-planar after the CMP process. In general, via electrodes118may be fabricated before or after fabrication of via structure140and metal line138. The method described in association withFIGS.8A-Fcan be performed so as to fabricate via structure140and metal line138prior to fabrication of via116, as is described herein. In some embodiments, the memory device108may be taller such that the via structure140is confined to level106and metal lines136and138are on a level above level106. In some such embodiments, the via electrodes may be fabricated before via structure140and metal lines136and138or after. In some such embodiment, via structure140may not be formed within a hanging trench opening1014A. FIG.11Ais a cross-sectional illustration of the structure inFIG.10Dfollowing the process to form via electrodes118, in accordance with an embodiment of the present disclosure. After formation of via electrodes118, an opening1100is formed in the dielectric142. An opening1100is formed by forming a mask1103on the dielectric116and142, and on the via electrodes118. In an embodiment, opening1100is formed by etching the dielectric142and the etch stop layer113and exposing conductive interconnect134. Opening1100has a width, WVEthat may be substantially the same as width of via structure140(FIG.10H). FIG.11Bis a cross-sectional illustration of the structure inFIG.11Afollowing the process to form via structure1101. The process further includes depositing a liner layer1102in the opening1100, on the conductive interconnect134, on sidewalls of dielectric142and of sidewalls of etch stop layer113and on the conductive interconnect134. A fill material1104may then deposited on the liner layer1102. A planarization is performed after the deposition process. In some embodiments, liner layer1102includes a material that is the same or substantially the same as the material of the liner layer1018. In some embodiments, fill material1104includes a material that is the same or substantially the same as the material of the fill material1020. Liner layer1102and fill material1104may be formed by a substantially identical process utilized to form liner layer1018and fill material1020described in association withFIG.10H. FIG.11Cis a cross-sectional illustration of the structure inFIG.11Bfollowing the process to deposit a dielectric204to form a level1106. The level1106is the same as level202described in association withFIG.2. In an embodiment, the dielectric204includes a material that is the same or substantially the same as the material of the dielectric142and is deposited to a thickness desirable to form electrodes in the memory region and metal lines in the logic region. In other embodiments dielectric204includes a material that is different from dielectric142. In some embodiments, dielectric204includes a substantially similar base material as dielectric142, for example, silicon and oxygen, but includes various concentrations of one or more of carbon or nitrogen. In other embodiments, dielectric204includes a substantially similar base material as dielectric142, for example, silicon and oxygen, but includes various concentrations of carbon but excludes nitrogen. In yet other embodiments, dielectric204includes a substantially similar base material as dielectric142, for example, silicon and oxygen but where the materials have different densities. It is to be appreciated that dielectric204includes a material that can be deposited at lower temperatures and have a lower film density than dielectric116. Dielectric204may not be required to provide a diffusion barrier capability like dielectric116. The conductive hydrogen barrier120within via electrode118permits a dielectric204having a higher porosity film with a low film density to be deposited instead of another dielectric similar to dielectric116. Additionally, depositing a material with lower film density can facilitate a single deposition over the logic and memory regions101B and101A, respectively. No further etching and removing of a dielectric material from the logic region is required, eliminating further fabrication process operations and reducing cost. In an embodiment, a plurality of openings are formed simultaneously in the dielectric204. Metal lines1107and1108are formed within the openings formed in the dielectric204in the logic region. In the illustrative embodiment, in contrast to metal line138, metal line1108includes a liner layer1110that is directly above and laterally on an uppermost surface of fill material1104, and in contact with liner layer1102. As shown, fill metal1111may be discontinuous from the fill material1104. The liner layer1110provides adhesion for fill metal1111. The deposition and planarization processes utilized to form metal lines1107and1108are substantially the same as the deposition and planarization processes utilized to fabricate via structure208. In some embodiments, liner layer1110and fill metal1111includes a material that is the same or substantially the same as the material of the liner layer1102and fill material1104. Depending on a width of metal lines1107and1108, liner layer1110may be thicker than liner layer1102and may include a material that is different from liner layer1102. In some embodiments, liner layer1110may have a thickness that is less than 5 nm and any reduction in electrical conductance may be negligible. FIG.11Dis a cross-sectional illustration of the structure inFIG.11Cfollowing the process to form openings1109to form electrodes in the memory region101A. In the illustrative embodiment, openings1109are formed in the dielectric204. Openings1109expose the via electrodes118. Openings1109may be formed by forming a mask on the dielectric204and patterning the dielectric204in the memory region101A. In the illustrative method embodiments, openings1109may be smaller than, substantially the same size as or larger the via electrodes118. This method also offers an advantage over methods that simultaneously form openings1109and a via opening for via electrode118. Misalignments between opening1109and via electrode118, by up to 50% of WVEmay be acceptable. Openings1109have a lateral thickness, WV. In embodiments, where the openings1109are larger than via electrodes118, i.e., WVgreater than WVE, dielectric116is also exposed while forming openings1109, as shown. FIG.11Eis a cross-sectional illustration of the structure inFIG.11Dfollowing the process to form an electrode1120on each of the via electrodes118. Electrode120may be a trench electrode1120. In the illustrative embodiment, a conductive hydrogen barrier1112is blanket deposited on the surface of the via electrode118, on portions of the dielectric116, on sidewalls of dielectric204and on an uppermost surface204A of the dielectric204and on the metal lines136and1108. The conductive hydrogen barrier1112may be deposited by an atomic deposition layer process that provides for substantially uniform deposition on via electrode118as well as on sidewalls of dielectric204. In the illustrative embodiment, the conductive hydrogen barrier1112extends over and is in contact with the conductive hydrogen barrier120, liner layer122and conductive fill material124. The deposition process continues with the formation of a liner layer1114in the openings1109on the conductive hydrogen barrier1112. A fill metal1116is then deposited on the liner layer1114in openings1109. A planarization process includes a CMP process that is performed to remove the fill metal1116, the liner layer1114and the conductive hydrogen barrier1112from on or above the uppermost surface204A. In an embodiment, the CMP process forms an electrode1120on via electrode118. In various embodiments, conductive hydrogen barrier1112includes a material that is the same or substantially the same as the material of the conductive hydrogen barrier114; liner layer1114includes a material that is the same or substantially the same as the material of the liner layer122, and conductive fill metal1116includes a material that is the same or substantially the same as the material of the conductive fill material124. As shown, electrode1120has an uppermost surface1120A that is substantially planar. The surface1120A can be co-planar or substantially co-planar with uppermost surface1108A of the metal line1108. The metal lines1107and1108, and electrodes1120are fabricated independently of a thickness requirement for the memory device and offers process flexibility. The electrode1120may be substantially similar to a contact electrode206, that is shaped in a trench, depicted inFIGS.4A and4Bthat couple a plurality of memory devices along the y-direction. In some such embodiments, the trench electrode1120couples a memory device such as memory device302on a plane behind a plane of the memory device108. In other embodiments, electrode1120is a trench electrode1120that couples two or more memory devices108along the x-direction as illustrated inFIG.11F(trench electrode1120may also be a contact electrode). The surface1120A can be co-planar or substantially co-planar with uppermost surface1108A of the metal line1108as shown. In some such embodiments, the conductive hydrogen barrier1112also extends on dielectric116between adjacent memory devices108. As shown, liner layer1114and fill metal1116also extend over dielectric116. In some embodiments, the via structure1101, metal lines1107and1108may be fabricated prior to formation of the via electrodes118and electrodes1120. In some such embodiments, the opening for electrode1120is made prior to forming an opening for a via electrode. The process is substantially similar to the process described in association withFIGS.10F-G. In some embodiments, where the combined height of memory device108and via electrode118, (TMD+TVE) is substantially equal to a height of via structure208, the dielectric142may not be planarized to a level of the uppermost surface116A of dielectric116in the memory region101A. In some such embodiments, dielectric142extends over dielectric116in the memory region101A, as illustrated inFIG.12A.FIG.12Ais a cross-sectional illustration of the structure inFIG.10Dfollowing the process to planarize dielectric142. In an embodiment, the planarization process leaves a thickness, TO1of dielectric142above dielectric116that is sufficient to fabricate electrodes above the via electrodes118and metal lines above a via in the logic region. Vertical thickness, TO2is equal to vertical thickness of a via and a thickness of metal lines to be fabricated in the logic region101B. FIG.12Bis a cross-sectional illustration of the structure inFIG.12Afollowing the process to form via structure1200, and metal lines1202and1204. In an embodiment, the process utilized to form via structure1200, and metal lines1202and1204includes a process that is the same or substantially the same as the process utilized to form via structure140, and metal lines136and138(described in association withFIGS.10E-10H), in accordance with an embodiment of the present disclosure. In the illustrative embodiment, the via structure1200includes a liner layer1206and a fill material1208on liner layer1206. In some embodiments, liner layer1206includes a material that is the same or substantially the same as the material of the liner layer1018. In some embodiments, fill material1208includes a material that is the same or substantially the same as the material of the fill material1020. In an embodiment, the materials utilized to form via structure1200, and metal lines1202and1204include materials that are the same or substantially the same as the materials utilized to form via structure140, and metal lines136and138, (described in association withFIGS.10E-10H). It is to be appreciated that lower most surface1202A of metal line1202and lower most surface1204A of metal line1204can be at a level that is below the uppermost surface116A of dielectric116. A plasma etch process utilized to form hanging trenches to form metal lines may be targeted to approximately achieve a desired depth in dielectric142. In some embodiments, lower most surface1202A of metal line1202and lower most surface1204A of metal line1204can be at a level that is at the uppermost surface116A of dielectric116, as shown. In other embodiments, lower most surface1202A of metal line1202and lower most surface1204A of metal line1204can be at a level that is above the uppermost surface116A of dielectric116. After formation of via structure1200, and metal lines1202and1204, the process is continued to form openings1205in the dielectric142in the memory region. The process utilized to form openings may be the same or substantially the same as process utilized to form openings1109(described in association withFIG.11D), in accordance with an embodiment of the present disclosure. FIG.12Cis a cross-sectional illustration of the structure inFIG.12Bfollowing the process to form an electrode1120on a respective via electrode118. In an embodiment, the process utilized to form electrodes1120is described in association withFIGS.11D-11E. In some embodiments, via and one or more metal lines in the logic region may be fabricated first and then via electrodes may be fabricated in the memory region.FIG.13Ais a cross-sectional illustration of the structure inFIG.11C, in an embodiment where via electrodes are not yet fabricated above a respective memory device108. FIG.13Bis a cross-sectional illustration of an embodiment of the structure inFIG.13Afollowing the formation of trench openings1300in the dielectric204above a respective memory device108. The trench openings1300may be made by forming a mask on the dielectric204and etching the dielectric204. Depending on the material of dielectric116, dielectric116may act as an etch stop while etching to form openings1300. The openings1300have a width, WE. WEmay be greater than or less than WMD. Depending on embodiment, openings1300may be a trench openings1300or via openings1300. A trench opening1300may couple two or more memory devices such as memory device108and memory device302depicted inFIG.4A. FIG.13Cis a cross-sectional illustration of the structure inFIG.13Bfollowing the process to etch dielectric116to form a via opening1302below the trench opening1300in memory region101A. In an embodiment, mask1304is formed on the dielectric204and on metal lines1107and1108, and on dielectric204by a lithographic process. Mask1304may include a photoresist material. Mask1304has an opening within hanging trench opening1300that is designed to enable etching the dielectric116to form a via opening. In an embodiment, the dielectric116is etched by a plasma etch process. The etch process is halted after uppermost surface108B of the memory device108is exposed. Via opening1302has a lateral thickness WVE. In the method illustrated herein, WVis at least equal to or greater than WVE. In such examples, WVEmay be greater than or less than WMD. In the illustrative embodiment, WVEis less than WMD. In some such embodiments, the uppermost surface108B is designed to protected by a combination of conductive and insulative hydrogen barrier materials. FIG.13Dis a cross-sectional illustration of the structure inFIG.13Cfollowing the process to fabricate a contact electrode206on the via electrode118, above a respective memory device108. In an embodiment, the mask utilized to form via openings1302may be removed by a plasma ashing or a wet chemical dissolution method. In the illustrative embodiment, electrode118and contact electrode206may be formed by single deposition process for each layer of material required. in accordance with embodiments of the present disclosure, conductive hydrogen barrier120is blanket deposited into the openings1300, and1302on the memory device108, on sidewalls of dielectric116, and dielectric204and on uppermost surface204A. The conductive hydrogen barrier120is contiguous within the openings1300and1302, as shown. The conductive hydrogen barrier120includes a material that is most compatible with the dielectric116so that an interface between the conductive hydrogen barrier120and the dielectric116is not a source of dislocations. In the illustrative embodiment, material of liner layer122is blanket deposited in the openings1300and1302on the conductive hydrogen barrier120. A layer of conductive fill material124is deposited into the remaining portions of openings1300and1302on the material of liner layer122. In embodiments, the material of conductive hydrogen barrier120, material of the liner layer122and layer of conductive fill material124are deposited by an ALD, PVD or a sputter deposition process. In an embodiment, the planarization process includes a chemical mechanical planarization (CMP) process. In an embodiment, the CMP process removes the excess layer of conductive fill material124, material of liner layer122and conductive hydrogen barrier120from an uppermost surface204A of dielectric204. The planarization process isolates the conductive hydrogen barrier120, conductive fill material124, liner layer122and conductive hydrogen barrier114from each via electrode118. The CMP process may also reduce the, as deposited, thickness of the dielectric204. FIG.14Ais an illustrative embodiment of the structure inFIG.12B, prior to the formation of via electrodes118above memory device108. In the illustrative embodiment, metal lines1202and1204and via structure1200are fabricated by a method that is the same or substantially the same as the method described in association withFIG.12B. In the illustrative embodiment, metal lines1202and1204and via structure1200are fabricated by a method that is the same or substantially the same as the method described in association withFIG.12B. In an embodiment, the metal lines1202and1204have a vertical thickness TM, relative to a relative to uppermost surface142A. Portions of the metal lines1202and1204may extend below uppermost surface116A due to the etch process utilized to form hanging trench openings. FIG.14Bis an illustrative embodiment of the structure inFIG.14A, following the process to form a plurality of openings1400and1402. In an embodiment, the method utilized to form openings1400and1402is the same or substantially the same as the method utilized to form openings1300and1302described in association withFIGS.13B and13C. A mask1403may be utilized to mask portions of openings1400and form openings1402. FIG.14Cis a cross-sectional illustration of the structure inFIG.14Bfollowing the process to fabricate via electrode118and contact electrode206. In an embodiment, via electrode118and contact electrode206are formed by a method that is the same or substantially the same as the method described in association withFIG.13D. In other embodiments, a single via opening may be made in the dielectrics116and204above each memory device108. The operation to make a single via electrode is described in association withFIGS.15A-15B. A single via electrode may be desirable when the height, TV, of via structure208is comparable to the height, TMDof memory device108. A single via electrode can also provide flexibility to couple different memory devices as will be shown inFIGS.15C-15D. FIG.15Ais a cross-sectional illustration of the structure inFIG.11E, in an embodiment where via electrodes and electrodes on top of via electrodes are yet to be fabricated. In some embodiments, an opened is formed in dielectrics204and116at the same time after fabrication of metal lines1107and1108and via structure208. In an embodiment, a mask1500is formed on the dielectric204and on the of metal lines1107and1108. A plasma etch process is utilized to etch dielectric204through openings in the mask1500to form opening1502. The plasma etch process may be continued to etch dielectric116, after etching dielectric204. In the illustrative embodiment, the opening1502, have a substantially uniform width, WVEin both materials, dielectric204and dielectric116. In other embodiments, there may be some taper in the dielectric116and dielectric204as indicated by dashed lines1503. The sidewalls of openings may be tapered defined by a single taper angle or be gradually tapered. FIG.15Bis a cross-sectional illustration of the structure inFIG.15Afollowing the process to form via electrode118having a first portion within the dielectric116having a high film density a second portion within dielectric204having a low film density in accordance with an embodiment of the present disclosure. In an embodiment, the process to form via electrode1504is the same or substantially the same as formation of contact electrode206and via118(described in association withFIG.12C). In the illustrative embodiment, via electrode1504does not extend beyond a periphery of the memory device108and includes a first portion1504A adjacent to dielectric116and a second portion1504B adjacent to dielectric204. In an embodiment, portion1504B has a height TVE. The portion of opening1502that is within dielectric204has a same or substantially the same plan view profile as the opening1502that is within dielectric116. In exemplary embodiments, unlike contact electrode206, portion1504B does not extend along the y-axis inFIG.15B. FIG.15Cis a cross-sectional illustration of the structure inFIG.15Bfollowing the process to form an opening1506between adjacent via electrodes1504that are spaced apart along the x-direction. In an embodiment, a mask1508is formed on the dielectric204, on the metal lines1107and1108. As shown the mask includes an opening where the dielectric204is to be removed. A plasma etch process is utilized to remove the dielectric204from the opening in the mask1508. In an embodiment, the dielectric204is etched selectively, by the plasma etch process, with respect to the materials of the via electrode1504and dielectric116. The plasma etch process utilized may selectively remove the dielectric204with respect to conductive hydrogen barrier120because of the differences in material. In some embodiments, the dielectric116may be reduced below uppermost surface116A. In other embodiments, the mask1508can be a hardmask, and a wet chemical process can be utilized to recess dielectric204selectively against materials of via electrode1504. In some embodiments a combination of plasma etch and wet chemical etch is utilized to remove dielectric204effectively from sidewalls120D to provide a sufficient surface area for contact with a conductive bridge to be formed. FIG.15Dis a cross-sectional illustration of the structure inFIG.15Cfollowing the process to form a conductive bridge1510between adjacent via electrodes1504. In the illustrative embodiment, the process utilized to form the conductive bridge1510includes materials and processes utilized to fabricate via electrode1504, described above. In the illustrative embodiment, a conductive hydrogen barrier1512is first blanket deposited into the opening1506, on the dielectric204, against outer sidewalls of conductive hydrogen barrier120, on uppermost surface1504C of via electrode1504, uppermost surfaces of metal line1107and1108. The deposition process continues with deposition of a liner layer1514on the conductive hydrogen barrier1512, followed by deposition of a fill material1516. There are numerous advantages in forming a conductive bridge1510after formation of the via electrode1504where upper most surfaces1510A are co-planar or substantially co-planar with uppermost surface1504C of via electrode1504. A conductive bridge1510can be inserted between any two or more adjacent memory devices108after the via electrodes are fabricated. Conductive bridge1510offers integration flexibility to choose two or more memory devices108to be connected by defining the layout of mask1508. Secondly, the materials included in the conductive bridge1510can be chosen independently of the materials of the via electrode1504. While, in the illustrative embodiment, conductive bridge1510includes conductive hydrogen barrier1512, and the liner layer1514, in other embodiments, the conductive hydrogen barrier1512, and the liner layer1514may be absent. The conductive hydrogen barrier120and dielectric116in themselves offer adequate protection against hydrogen diffusion toward memory device108. FIGS.16A-Cdepict various plan view embodiments of one or more conductive bridges. FIG.16Ais a plan view of the structure inFIG.15D, in accordance with an embodiment of the present disclosure. In the illustrative embodiment, via electrode1504and the conductive bridge have substantially rectangular plan view profiles. The conductive bridge1510has a width, WB(along the y direction) and the via electrode1504has a width, WVEY. WBmay be greater than, less than or equal to WMDY. In the illustrative embodiment, WBis substantially equal to WVEY. WBmay be less than WVEYas shown inFIG.16Bwith as long as WBis sufficiently wide to enable a minimum current conductance. The memory devices108are not illustrated for clarity. In other configurations via electrode1504may be present on a plane A, behind plane B, as shown in the plan-view illustration ofFIG.16C. A pair of via electrodes1504are coupled above a memory device302(hidden under via electrode1504). In some such embodiments, a conductive bridge1610may be further implemented to couple a pair of via electrodes1504on the plane A. Conductive bridge1610may be oriented parallel to conductive bridge1510. The flexibility to implement conductive bridges1610and1510is particularly advantageous when conductive bridges1610and1510have a substantially similar plan view shape and size. A substantially similar plan view size can minimize variations in depths, D01, of openings that are filled with material of conductive bridges1510and1610(such as opening1506inFIG.15C). In other embodiments, conductive bridges that are oriented perpendicular to conductive bridge1510or1610may also be formed sequentially or simultaneously. Formation of perpendicularly oriented conductive bridge provides enhanced flexibility to couple arbitrary numbers of memory devices. Such flexibility can be exercised by changing mask design instead of process flow. FIG.17Cis an embodiment of the structure inFIG.7A, where WCIis less than Wo, and surface105B of dielectric105may be recessed relative to an uppermost surface105A (which is covered by the etch stop layer113). The photoresist mask702is removed in the illustration for clarity. A recess in the dielectric105may occur when there is a loss of selectivity or where there is limited selectivity between the material of the etch stop layer113and the dielectric105. In some such embodiments, sidewalls102A of the conductive interconnect102are exposed after forming opening701. FIG.17Bis a cross-sectional illustration of the structure inFIG.17Afollowing the process to form an electrode structure112having a portion below an uppermost surface102B of the conductive interconnect102. In the illustrative embodiment, the conductive hydrogen barrier114is formed on the recessed surface105B, on a portion of sidewall102A, and on uppermost surface102B of conductive interconnect102. The conductive hydrogen barrier114is formed below uppermost surface102B. Depending on Wo, portions of conductive fill material115may above or below uppermost surface102B. FIG.18A-Care cross-sectional illustrations depicting a method to fabricate an electrode structure having a conductive hydrogen barrier above a fill metal. FIG.18Ais a cross-sectional illustration of the structure inFIG.7Afollowing the formation of conductive fill material within openings1801, in accordance with an embodiment of the present disclosure. In an embodiment, conductive fill material115is blanket deposited into the opening1801, and on the etch stop layer113. Portions of the conductive fill material115on the etch stop layer113are removed by a planarization process leaving the conductive fill material115within the openings1801. In an embodiment, a wet chemical process is utilized to recess the conductive fill material115below the uppermost surface113A. In an embodiment, level of recess of conductive fill material115relative to uppermost surface113A will depend on TLand on a desired thickness of the conductive hydrogen barrier to be formed. In some embodiments, the conductive fill material115is recessed relative to uppermost surface113A by up to half of TL. In some embodiments, uppermost surface115C of the conductive fill material115is concaved due to wet chemical recess as indicated by dashed lines1805. In an embodiment, a liner layer, indicated by dashed lines1803may be deposited into each opening1801prior to deposition of the conductive fill material115. The liner layer may be recessed at the same time as the conductive fill material115, prior to or after recessing the conductive fill material115. FIG.18Bis a cross-sectional illustration of the structure inFIG.18Afollowing the process to deposit a conductive hydrogen barrier material1807in each opening1801. In an embodiment, the materials implemented, and process utilized to deposit conductive hydrogen barrier material1807is the same or substantially the same as the material implemented and process utilized to deposit conductive hydrogen barrier material800, as described in association withFIG.8A. FIG.18Cis a cross-sectional illustration of the structure inFIG.18Bfollowing the process to form a conductive hydrogen barrier1808on the conductive fill material115. A planarization process may be utilized to remove an excess conductive hydrogen barrier material1807deposited on etch stop layer113. In an embodiment, the planarization process includes a chemical mechanical polish (CMP) process. The CMP process forms conductive hydrogen barrier1808within each opening1801. In some embodiments, an uppermost surface1808A of the conductive hydrogen barrier layer1808is curved as indicated by dashed lines1809. A curved surface can result from dishing during the CMP process. It is to be appreciated that when a material layer stack for the formation of memory device is deposited, a lowermost layer in the material layer stack may follow the contour of the curved surface. A curved surface can change a vertical thickness (height) of the conductive hydrogen barrier1808across the electrode structure112. However, changes in thickness is not substantial to materially affect hydrogen barrier properties of the conductive hydrogen barrier1808. The conductive hydrogen barrier1808includes a material that is the same or substantially the same as the material of the conductive hydrogen barrier layer114. In the illustrative embodiment, the electrode structure112includes a conductive hydrogen barrier1808above the conductive fill material115, where the conductive hydrogen barrier1808prevents hydrogen from diffusing towards a memory device to be formed above. Depending on embodiments, the electrode structure112has a width that can be greater than or less than a width of a memory device to be formed on electrode structure112. In either embodiment, conductive hydrogen barrier1808can effectively prevent hydrogen from diffusing towards the memory device. FIG.19Ais a cross-sectional illustration of the structure inFIG.10Dfollowing the process to deposit dielectric204to form a level1106. Material composition of dielectric204and method to deposit dielectric204has been described above. In an embodiment, a plurality of hanging trench openings1901and1902are formed simultaneously in the dielectric204in the logic region as shown. In an embodiment, a mask is formed on dielectric204and a plasma etch process is utilized to form hanging trench openings1901and1902. In the illustrative embodiment, the etch process is halted after dielectric142is exposed. FIG.19Bis a cross-sectional illustration of the structure inFIG.19Afollowing the formation of a via opening1905within hanging trench opening1902, in accordance with an embodiment of the present disclosure. In an embodiment, a lithography process is utilized to form a mask1903on the dielectric204. The dielectric142is etched to form via1905that exposes conductive interconnect134. FIG.19Cis a cross-sectional illustration of the structure inFIG.19Afollowing the process to form via structure1200, and metal lines1202and1204. The method to form via structure1200, and metal lines1202and1204described above in association withFIGS.10E-10H. FIG.19Dis a cross-sectional illustration of the structure inFIG.19Cfollowing the formation of openings1906in the dielectric204above a respective memory device108. The openings1906may be made by forming a mask on the dielectric204and etching the dielectric204. Depending on the material of dielectric116, dielectric116may act as an etch stop while etching to form openings1906. The openings1906have a width, WE. WEmay be greater than or less than WMD. Depending on embodiment, openings1906may be trench openings1906or via openings1906. A trench opening1906may couple two or more memory devices such as memory device108and memory device302as depicted inFIG.4A. FIG.19Eis a cross-sectional illustration of the structure inFIG.19Dfollowing the process to form an electrode1120on respective via electrodes118. In an embodiment, the process utilized to form electrodes1120is described in association withFIGS.11D-11E. In some embodiments, electrodes1120and metal lines1202and1204may be co-fabricated. However, in some such embodiments, electrodes1120and metal lines1202and1204may all include a same material. In some such embodiments, simultaneous fabrication necessitates that electrodes1120, metal lines1202and1204, and via structure1200can all include a conductive hydrogen barrier material or completely exclude the conductive hydrogen barrier material. FIG.20Ais a cross-sectional illustration of the structure inFIG.10Dfollowing the process to deposit dielectric204and form a plurality of openings in the dielectric204. In an embodiment, openings2000,2001, and2002are formed simultaneously by masking the dielectric204and utilizing a plasma etch process to etch dielectric204. The dept, DM, of each opening2000,2001and2002is substantially the same. In some embodiments, DMmay be different by less than 5% depending on a relative width of each opening. DMcan also be different based on the similarity between materials of dielectric204and dielectric142. If there is etch selectivity between dielectric142and204because of differences in etch rates, then then DMmay be substantially the same. FIG.20Bis a cross-sectional illustration of the structure inFIG.20Afollowing the process to form a via opening2003within opening2002. In an embodiment, the process to form via opening2003is substantially the same as the process utilized to form via opening1905described in association withFIG.19B. In the illustrative embodiment, mask2005also covers openings2000. FIG.20Cis a cross-sectional illustration of the structure inFIG.20Bfollowing the process to form electrodes2006, via structure1200and metal lines1202and1204. In the illustrative embodiment, the mask2005(FIG.20B) is removed and a liner layer1018is deposited into via opening2003, and in openings2000,2001and2002, and on dielectric204. A fill material1020is deposited on the liner layer1018. A planarization process may be performed to remove the liner layer1018from above dielectric204and fill metal from above the liner layer1018outside of openings2000,2001and2002. The planarization process forms metal lines1202and1204, via structure1200, and electrodes2006above each via electrode118. It is to be appreciated that electrodes2006may not have a conductive hydrogen barrier layer in contrast to the other examples described above. However, a lack of conductive hydrogen barrier layer in the electrodes2006does not materially impact memory device108performance because the uppermost surface108B of memory device108is protected by an insulative and a conductive hydrogen barrier material. FIG.21Ais an illustrative embodiment of the structure inFIG.13A, where metal lines1202,1204and via structure1200are fabricated by a method described in association withFIGS.19A,19B and19C. FIG.21Bis a cross-sectional illustration of the structure inFIG.21Afollowing the process to form electrode structure205. In an embodiment, the process to form electrode structure205is described in association withFIGS.13A-13D. In some embodiments, as described above in association inFIG.1J, the device structure100E includes a high density spacer directly adjacent to the memory device108.FIGS.22A-Dare cross-sectional illustration of a sequence of operations that depict an evolution of the structure inFIG.8Dto the structure inFIG.1J. FIG.22Ais a cross-sectional illustration of the structure inFIG.8Dfollowing the process to deposit encapsulation layer152. The process utilized to deposit encapsulation layer152depends on the material utilized, on a height of memory device108, as well as on the relative spacing between adjacent memory devices108. In exemplary embodiments, the deposition process utilized to deposit encapsulation layer152does not include hydrogen or ammonia containing chemicals to prevent hydrogen exposure to layers within memory device108. In an embodiment, the encapsulation layer152includes an insulator material. The insulator material includes a transition metal and oxygen, such as, but not limited to AlxOy, HfOx, AlSiOx, ZrOx, or TiOx. Materials such as AlxOy, HfOX, AlSiOx, ZrOx, or TiOxcan be deposited without a hydrogen or ammonia containing chemical precursor in an ALD deposition process. An ALD process may be advantageous when an aspect ratio between adjacent memory devices108is greater than 1:1. An aspect ratio is a ratio between height of memory device108to a spacing between adjacent memory devices108, i.e., TMD:SM. The encapsulation layer152may be deposited to a thickness in the range of 0.5 nm-10 nm. However, when SMis approximately in the range of 20 nm, encapsulation layer152may be deposited to a thickness of less than 5 nm. An ALD process can provide a substantially conformal thickness on sidewalls108A, as shown. In some embodiments, a PVD deposition process does not conformally deposit the encapsulation layer152with a uniform thickness TEC. In some such embodiments, portions of the encapsulation layer152adjacent to uppermost surface108B is wider (illustrated by dashed lines2201) than portions adjacent to lowermost surface108C. In other embodiments when the aspect ratio is less than 1:1, a physical vapor deposition (PVD) process may be utilized. In some such embodiments, encapsulation layer152can include materials such as compounds of nitrogen and a transition metal such as, but not limited to AlN, ZrN, and HfN, or compounds of Si and O and one or more of Al, Hf or Ta, such as, but not limited to, AlSiOx, HfSiOx and TaSiOx. A PVD process may not provide a substantially conformal deposition on sidewalls108A. A thickness of approximately 2 nm may be sufficient to prevent hydrogen transport through an encapsulation layer152that is deposited with a material density of at least 90%. In the illustrative embodiment, the encapsulation layer152is blanket deposited in the memory region101A and in the logic region101B. FIG.22Bis a cross-sectional illustration of the structure inFIG.22Afollowing the process to form via openings2200in a dielectric116and in the encapsulation layer152. In the illustrative embodiment, a dielectric116is deposited on the encapsulation layer152. The dielectric may be deposited by an ALD, PVD, CVD process. The deposition process and materials of dielectric116are described above. In exemplary embodiments, dielectric116may include a material other than a material of the encapsulation layer152. When an encapsulation layer152is first deposited on sidewalls108A, dielectric116can include a material that is deposited in the presence of a hydrogen or an ammonia precursor. In some such embodiments, dielectric116can include an insulative high density material such as, but not limited to, AlxOy, HfOx, ZrOx, TaOx, TiOx, AlSiOx, HfSiOx, TaSiOx, AlN, ZrN, or HfN. In the illustrative embodiment, the encapsulation layer152is blanket deposited in the memory region101A and in the logic region101B and the dielectric116is blanket deposited on the encapsulation layer152. In other embodiments, the encapsulation layer152may be removed from the logic region101B prior to deposition of the dielectric116. After deposition of dielectric116, a mask2202is formed on dielectric116. A plasma etch process may be utilized to form via openings2200in the dielectric116. The plasma etch removes portions of the dielectric116through the mask2202and further etches a portion of the encapsulation layer152as shown. FIG.22Cis a cross-sectional illustration of the structure inFIG.22Bfollowing the process to form via electrodes118. The deposition process utilized to deposit the conductive hydrogen barrier114, liner layer122and conductive fill material124is substantially the same as the method described in association withFIG.10B. In the illustrative embodiment, conductive hydrogen barrier120is deposited on uppermost surface108B, adjacent to encapsulation layer152, and adjacent to dielectric116in via openings2200. In some embodiments, where via opening2200is wider than memory device108, encapsulation layer152on uppermost surface108B is etched (as illustrated by dashed lines2204). In some such embodiments, the encapsulation layer152may also be recessed on sidewalls108A and conductive hydrogen barrier120may be deposited on a top portion of sidewall108A (as described in association withFIG.1D). After deposition, a planarization process is utilized (as described in association withFIG.10B) to form via electrode118on each memory device108. The dielectric116may be replaced by dielectric142in the logic region101B (as described in association withFIGS.10C-10D). In the illustrative embodiment, dielectric142is blanket deposited on the etch stop layer113. In exemplary embodiments, the encapsulation layer152is removed from the logic region101B prior to deposition of the dielectric142. The removal of encapsulation layer152from logic region101B is desirable to remove a high density film (greater than 90% film density). Depending on materials a high density film may have a high dielectric constant (such above 4) and can cause electrical degradation in interconnect operation due to higher charge storage capability. FIG.22Dis a cross-sectional illustration of the structure inFIG.22Cfollowing the process to form via structure140and metal lines136and138. The process to form via structure140and metal lines136and138is the same or substantially the same as described in association withFIGS.10E-10H. In the illustrative embodiment, formation of an opening to form via structure140includes further etching through encapsulation layer152and additionally depositing liner layer144adjacent to encapsulation layer152. The encapsulation layer152has been discussed herein, in a structural embodiment, where metal lines136and138are also formed at a same level as via electrode118. In other embodiments, encapsulation layer152may be formed in combination with various different electrode structures, such as electrode structure148. In yet other embodiments, encapsulation layer152may be formed in combination with dielectric204,142and116. In some embodiments, lateral thickness, WVEof via electrode118is greater than WMD. In some such embodiments via electrode118is on an entire uppermost surface108B. In further some such embodiments, the etch utilized to form opening to form via electrode118can etch portions of dielectric116below uppermost surface108B. The via electrode118can extend below uppermost surface108B and on sidewalls108A as indicated by dashed box2204. While electrode structure112is illustrated inFIGS.10A-15A, and in19A-22D, electrode structure112can be replaced in embodiments by electrode structure148, described in association withFIGS.1H and18C. FIG.23illustrates computing architecture2300with a coherent cache or memory-side buffer chiplet that includes a memory controller, wherein the coherent cache or memory-side buffer chiplet is coupled to an accelerator, a processor, and a memory, in accordance with some embodiments. Computing architecture2300comprises coherent cache or memory-side buffer chiplet2301, accelerator2302(e.g., inference chip), processor (e.g., central processing unit CPU2320), and memory die2304. In some embodiments, coherent cache or memory-side buffer chiplet2301comprises at least two channels2315which are configured to connect with accelerator2302and CPU2320. In some embodiments, coherent cache or memory-side buffer chiplet2301comprises I/O and controller2319to manage data traffic with memory die2404. By moving controller2319from CPU2320to coherent cache or memory-side buffer chiplet2301, cost in terms of power and die area for CPU2320is reduced. In some embodiments, coherent cache or memory-side buffer chiplet2301is a cache memory that comprises ferroelectric memory cells. For example, coherent cache or memory-side buffer chiplet2301comprises one or more of: FE-SRAM, FE-DRAM, SRAM, MRAM, resistance RAM (Re-RAM), embedded DRAM (e.g., 1T-1C based memory), or a combination of them. Using FE-SRAM, MRAM, or Re-RAM allows for low power and high-speed memory operation FIG.24illustrates architecture2400of the coherent cache or memory-side buffer chiplet (e.g.,2407) with multiple controllers and multiple cache banks, in accordance with some embodiments. In some embodiments, architecture2400comprises channels (e.g., ch02415-1and ch12415-2), cache banks2401, local cache controller2402, non-volatile (NV) controller2403, and reliability logic2404. Coherent cache or memory-side buffer chiplet2407may function as a cache or memory buffer. In some embodiments, cache lookups can map a large physical memory into a small physical cache using indirection via tags. Here, indirection refers to the use of tags to specify which address maps to which physical location. If multiple addresses can map to a single physical location, a tag is used to figure out which address is currently mapped. In some embodiments, each cache bank2401includes data bank2405(e.g., comprising memory cells) and associated tags2406. In some embodiments, data bank2405comprises ferroelectric memory cells. In some embodiments, data bank2405comprises one or more of: FE-SRAM, FE-DRAM, SRAM, MRAM, resistance RAM (Re-RAM), embedded DRAM (e.g., 1T-1C based memory), or a combination of them. Using FE-SRAM, MRAM, or Re-RAM allows for low power and high-speed memory operation. In some embodiments, when data bank2405includes ferroelectric memory, it uses NV controller2403and a stronger reliability logic (e.g., error correction code) for security compared to non-ferroelectric memory for data bank2405. When data bank2405is used to implement a cache, tags may be used to identify which addresses map to which physical locations in the bank. The cache may be set associative in which a particular address can map to several physical locations. The specific physical location a newly allocated address is mapped to may be determined by a replacement algorithm such as LRU (least recently used) or pseudo-LRU, or even random. On the other hand, the cache might be direct mapped, with each address mapping to merely a single physical cache line. In both set associative and direct mapped caches, several addresses map to a single physical cache line. To identify the address currently occupying the physical cache line, a tag2406may be coupled with each physical line. Tag2406may comprise some address bits, sufficient to uniquely identify which address currently occupies the physical line coupled with the tag. In some embodiments, cache controller2402could be used to control state transitions required for cache look ups such as comparing requested addresses with tags stored in the tags2406and identifying a candidate for replacement (replacement algorithm) when a cache miss occurs. In addition, the cache controller could be tasked with initializing the cache when the cache powers on. When FE memory of data bank2405, which retains state across power cycles, is used, cache controller2402could write 0s to all memory locations to ensure that data associated with previously executed programs is erased, thus preventing any data leakage to subsequently executed programs. The non-volatile memory may also include an NV bit, which could indicate that cache data is meant to be non-volatile and remain across power cycles. Cache controller2402would skip locations marked thus when initializing memory. In some embodiments, reliability logic2404performs error correction to the data. Any suitable error correction scheme (e.g., with error correction code (ECC)) may be used by reliability logic2404. In some embodiments, NV controller2403is provided to explicitly clear the cache when using a non-volatile memory, such as FM memory for data bank2405. NV controller2403may include an NV bit which indicates cache lines that should not be cleared but are expected to retain their contents across power cycles. The functions of NV controller2403can be combined in cache controller2402, or vice versa. FIG.25illustrates apparatus2500comprising memory and corresponding logic, wherein the memory comprises ferroelectric (FE) memory bit-cells, in accordance with some embodiments. Apparatus2500comprises M×N memory array2501of bit-cells, logic circuitry2502for address decoding, sense amplifier and write drivers2503, and plate-line (PL) driver2504. Logic circuitry2502comprises address decoders for selecting a row of bit-cells and/or a particular bit-cell from M×N memory array2501, where M and N are integers of same or different values. Logic circuitry2502comprises sense-amplifiers for reading the values from the selected bit-cell, while write drivers are used to write a particular value to a selected bit-cell. Here, a schematic of FE bit-cell25010,0is illustrated. The same embodiments apply to other bit-cells of the M×N array. In this example, a one-transistor one-capacitor (1T1C) bit cell is shown, but the embodiments are applicable to 1TnC bit-cell and multi-element FE gain bit-cell as described herein. In some embodiments, bit-cell25010,0comprises a word-line (WL), a plate-line (PL), a bit-line (BL), a complementary bit-line (BLB), and two half bit-cells25010,0_Aand25010,0_B. In some embodiments, bit-cell25010,0comprises an n-type transistor MN1, and FE capacitive structure Cfe1. The gates of transistor MN1are coupled to a common WL. In various embodiments, one terminal of the FE capacitive structure Cfe1is coupled to a PL. The second terminal of the FE capacitive structure is coupled to source or drain terminal of the transistor MN1. In various embodiments, BL is coupled to the source or drain terminal of first transistor MN1. In some embodiments, a BL capacitor CBl1is coupled to the source or drain terminal of first transistor MN1 and to a reference node (e.g., ground such that the FE capacitor is not coupled to the same source or drain terminal. In some embodiments, the PL is parallel to the BL and orthogonal to the WL. In some embodiments, the PL is parallel to the WL and orthogonal to the BL. In some embodiments, the FE capacitor is a planar capacitor. In some embodiments, the FE capacitor is a pillar or non-planar capacitor. In some embodiments, when the bit-cell is a 1TnC bit-cell, the FE capacitors are configured in a tower structure allowing the x-y foot-print to remain the same as for a 1T1C bit-cell but with taller bit-cell in the z-direction. In some embodiments, when the bit-cell is a multi-element FE gain bit-cell, the bit-cell allows for decoupling of the storage node from BL, allows for reducing the thickness scaling requirement for pillar capacitors, and allows for reducing polarization density requirements. Further, by stacking the ‘n’ capacitors in the z-direction (forming a tower), the area increases in the x-y direction due to the two transistors. The increase in area (due to the two transistors per bit-cell) allows for expanding the sizes (or radius) of the capacitors in the x-y direction. FIG.26illustrates a high-level architecture of an artificial intelligence (AI) machine2600comprising a compute die positioned on top of a memory die, in accordance with some embodiments. AI machine2600comprises computational block2601or processor having memory2602such as random-access memory (RAM)2602and compute die2603; first random-access memory2604(e.g., static RAM (SRAM), ferroelectric or paraelectric RAM (FeRAM), ferroelectric or paraelectric static random-access memory (FeSRAM)), main processor2605, second random-access memory2606(dynamic RAM (DRAM), FeRAM), and solid-state memory or drive (SSD)2607. In some embodiments, some or all components of AI machine2600are packaged in a single package forming a system-on-chip (SoC). The SoC can be configured as a logic-on-logic configuration, which can be in a 3D configuration or a 2.5D configuration. In some embodiments, computational block2601is packaged in a single package and then coupled to main processor2605and memories2604,2606, and2607on a printed circuit board (PCB). In some embodiments, computational block2601is configured as a logic-on-logic configuration, which can be in a 3D configuration or a 2.5D configuration. In some embodiments, computational block2601comprises a special purpose compute die2603or microprocessor. For example, compute die2603is a compute chiplet that performs a function of an accelerator or inference. In some embodiments, RAM2602is DRAM which forms a special memory/cache for the special purpose compute die2603. The DRAM can be embedded DRAM (eDRAM) such as 1T-1C (one transistor and one capacitor) based memories. In some embodiments, RAM2602is ferroelectric or paraelectric RAM (Fe-RAM). In some embodiments, compute die2603is specialized for applications such as Artificial Intelligence, graph processing, and algorithms for data processing. In some embodiments, compute die2603further has logic computational blocks, for example, for multipliers and buffers, a special data memory block (e.g., buffers) comprising DRAM, FeRAM, or a combination of them. In some embodiments, RAM2602has weights and inputs stored in-order to improve the computational efficiency. The interconnects between main processor2605(also referred to as special purpose processor), First RAM2604and compute die2603are optimized for high bandwidth and low latency. The architecture ofFIG.26allows efficient packaging to lower the energy, power, or cost and provides for ultra-high bandwidth between RAM2602and compute die2603of computational block2601. In some embodiments, RAM2602is partitioned to store input data (or data to be processed)2602A and weights2602B. In some embodiments, input data2602A is stored in a separate memory (e.g., a separate memory die) and weights2602B are stored in a separate memory (e.g., separate memory die). In some embodiments, computational logic or compute die2603comprises matrix multiplier, adder, concatenation logic, buffers, and combinational logic. In various embodiments, compute die2603performs multiplication operation on input data2602A and weight2602B. In some embodiments, weights2602B are fixed weights. For example, main processor2605(e.g., a graphics processor unit (GPU), field programmable grid array (FPGA) processor, application specific integrated circuit (ASIC) processor, digital signal processor (DSP), an AI processor, a central processing unit (CPU), or any other high-performance processor) computes the weights for a training model. Once the weights are computed, they are stored in memory2602. In various embodiments, the input data2602A, that is to be analyzed using a trained model, is processed by computational block2601with computed weights2602B to generate an output (e.g., a classification result). In some embodiments, First RAM2604is ferroelectric or paraelectric based SRAM. For example, a six transistor (6T) SRAM bit-cells having ferroelectric or paraelectric transistors are used to implement a non-volatile FeSRAM. In some embodiments, SSD2607comprises NAND flash cells. In some embodiments, SSD2607comprises NOR flash cells. In some embodiments, SSD2607comprises multi-threshold NAND flash cells. In various embodiments, the non-volatility of FeRAM is used to introduce new features such as security, functional safety, and faster reboot time of AI machine2600. The non-volatile FeRAM is a low power RAM that provides fast access to data and weights. First RAM2604can also serve as a fast storage for inference die (or accelerator), which typically has low capacity and fast access requirements. In various embodiments, the FeRAM (FeDRAM or FeSRAM) includes ferroelectric or paraelectric material. The ferroelectric or paraelectric (FE) material may be in a transistor gate stack or in a capacitor of the memory. The ferroelectric material can be any suitable low voltage FE material that allows the FE material to switch its state by a low voltage (e.g., 2600 mV). Threshold in the FE material has a highly non-linear transfer function in the polarization vs. voltage response. The threshold is related a) non-linearity of switching transfer function, and b) to the squareness of the FE switching. The non-linearity of switching transfer function is the width of the derivative of the polarization vs. voltage plot. The squareness is defined by the ratio of the remnant polarization to the saturation polarization; perfect squareness will show a value of 1. The squareness of the FE switching can be suitably manipulated with chemical substitution. For example, in PbTiO3 a P-E (polarization-electric field) square loop can be modified by La or Nb substitution to create an S-shaped loop. The shape can be systematically tuned to ultimately yield a non-linear dielectric. The squareness of the FE switching can also be changed by the granularity of a FE layer. A perfectly epitaxial, single crystalline FE layer will show higher squareness (e.g., ratio is closer to 1) compared to a poly crystalline FE. This perfect epitaxial can be accomplished using lattice matched bottom and top electrodes. In one example, BiFeO (BFO) can be epitaxially synthesized using a lattice matched SrRuO3 bottom electrode yielding P-E loops that are square. Progressive doping with La will reduce the squareness. In some embodiments, the FE material comprises a perovskite of the type ABO3, where ‘A’ and ‘B’ are two cations of different sizes, and ‘O’ is oxygen which is an anion that bonds to both the cations. Generally, the size of atoms of A is larger than the size of B atoms. In some embodiments, the perovskite can be doped (e.g., by La or Lanthanides). In various embodiments, when the FE material is a perovskite, the conductive oxides are of the type AA′BB′O3. A′ is a dopant for atomic site A, it can be an element from the Lanthanides series. B′ is a dopant for atomic site B, it can be an element from the transition metal elements especially Sc, Ti, V, Cr, Mn, Fe, Co, Ni, Cu, Zn. A′ may have the same valency of site A, with a different ferroelectric polarizability. In some embodiments, the FE material comprises hexagonal ferroelectrics of the type h-RMnO3, where R is a rare earth element viz. cerium (Ce), dysprosium (Dy), erbium (Er), europium (Eu), gadolinium (Gd), holmium (Ho), lanthanum (La), lutetium (Lu), neodymium (Nd), praseodymium (Pr), promethium (Pm), samarium (Sm), scandium (Sc), terbium (Tb), thulium (Tm), ytterbium (Yb), and yttrium (Y). The ferroelectric phase is characterized by a buckling of the layered MnO5 polyhedra, accompanied by displacements of the Y ions, which lead to a net electric polarization. In some embodiments, hexagonal FE includes one of: YMnO3 or LuFeO3. In various embodiments, when the FE material comprises hexagonal ferroelectrics, the conductive oxides are of A2O3 (e.g., In2O3, Fe2O3) and ABO3 type, where ‘A’ is a rare earth element and B is Mn. In some embodiments, the FE material is perovskite, which includes one or more of: La, Sr, Co, Sr, Ru, Y, Ba, Cu, Bi, Ca, and Ni. For example, metallic perovskites such as: (La,Sr)CoO3, SrRuO3, (La,Sr)MnO3, YBa2Cu3O7, Bi2Sr2CaCu2O8, LaNiO3, etc. may be used for FE material. Perovskites can be suitably doped to achieve a spontaneous distortion in a range of 0.3 to 2%. For chemically substituted BiFeO3, BrCrO3, BuCoO3 class of materials, La or rate earth substitution into the Bi site can tune the spontaneous distortion. In some embodiments, the FE material is contacted with a conductive metal oxide that includes one of the conducting perovskite metallic oxides exemplified by: La—Sr—CoO3, SrRuO3, La—Sr—MnO3, YBa2Cu3O7, Bi2Sr2CaCu2O8, and LaNiO3. In some embodiments, the FE material comprises a stack of layers including low voltage FE material between (or sandwiched between) conductive oxides. In various embodiments, when the FE material is a perovskite, the conductive oxides are of the type AA′BB′O3. A′ is a dopant for atomic site A, it can be an element from the Lanthanides series. B′ is a dopant for atomic site B, it can be an element from the transition metal elements especially Sc, Ti, V, Cr, Mn, Fe, Co, Ni, Cu, Zn. A′ may have the same valency of site A, with a different ferroelectric polarizability. In various embodiments, when metallic perovskite is used for the FE material, the conductive oxides can include one or more of: IrO2, RuO2, PdO2, OsO2, or ReO3. In some embodiments, the perovskite is doped with La or Lanthanides. In some embodiments, thin layer (e.g., approximately 10 nm) perovskite template conductors such as SrRuO3coated on top of IrO2, RuO2, PdO2, PtO2, which have a non-perovskite structure but higher conductivity to provide a seed or template for the growth of pure perovskite ferroelectric at low temperatures, are used as the conductive oxides. In some embodiments, ferroelectric materials are doped with s-orbital material (e.g., materials for first period, second period, and ionic third and fourth periods). In some embodiments, f-orbital materials (e.g., lanthanides) are doped to the ferroelectric material to make paraelectric material. Examples of room temperature paraelectric materials include: SrTiO3, Ba(x)Sr(y)TiO3 (where x is −0.05, and y is 0.95), HfZrO2, Hf—Si—O. In some embodiments, the FE material comprises one or more of: Hafnium (Hf), Zirconium (Zr), Aluminum (Al), Silicon (Si), their oxides or their alloyed oxides. In some embodiments, the FE material includes one or more of: Al(1−x)Sc(x)N, Ga(1−x)Sc(x)N, Al(1−x)Y(x)N or Al(1−x−y)Mg(x)Nb(y)N, y doped HfO2, where x includes one of: Al, Ca, Ce, Dy, Er, Gd, Ge, La, Sc, Si, Sr, Sn, or Y, wherein ‘x’ is a fraction. In some embodiments, the FE material includes one or more of: Bismuth ferrite (BFO), or BFO with doping material. In some embodiments, the FE material includes Bismuth ferrite (BFO), BFO with a doping material where in the doping material is one of Lanthanum, or any element from the lanthanide series of the periodic table. In some embodiments, the FE material includes a relaxor ferro-electric includes one of Barium Titanium-Bismuth Zinc Niobium Tantalum (BT-BZNT) or Barium Titanium-Barium Strontium Titanium (BT-BST). In some embodiments, the FE material includes Hafnium oxides of the form, Hf1−x Ex Oy where E can be Al, Ca, Ce, Dy, Er, Gd, Ge, La, Sc, Si, Sr, Sn, or Y. In some embodiments, the FE material includes Niobate type compounds LiNbO3, LiTaO3, Lithium iron Tantalum Oxy Fluoride, Barium Strontium Niobate, Sodium Barium Niobate, or Potassium strontium niobate. In some embodiments, the FE material comprises multiple layers. For example, alternating layers of [Bi2O2]2+, and pseudo-perovskite blocks (Bi4Ti3O12 and related Aurivillius phases), with perovskite layers that are n octahedral layers in thickness can be used. In some embodiments, the FE material comprises organic material. For example, Polyvinylidene fluoride or polyvinylidene difluoride (PVDF). In some embodiments, the FE material comprises hexagonal ferroelectrics of the type h-RMnO3, where R is a rare earth element viz. cerium (Ce), dysprosium (Dy), erbium (Er), europium (Eu), gadolinium (Gd), holmium (Ho), lanthanum (La), lutetium (Lu), neodymium (Nd), praseodymium (Pr), promethium (Pm), samarium (Sm), scandium (Sc), terbium (Tb), thulium (Tm), ytterbium (Yb), and yttrium (Y). The ferroelectric phase is characterized by a buckling of the layered MnO5 polyhedra, accompanied by displacements of the Y ions, which lead to a net electric polarization. In some embodiments, hexagonal FE includes one of: YMnO3 or LuFeO3. In various embodiments, when the FE material comprises hexagonal ferroelectrics, the conductive oxides are of A2O3 (e.g., In2O3, Fe2O3) and ABO3 type, where ‘A’ is a rare earth element and B is Mn. In some embodiments, the FE material comprises improper FE material. An improper ferroelectric is a ferroelectric where the primary order parameter is an order mechanism such as strain or buckling of the atomic order. Examples of improper FE material are LuFeO3 class of materials or super lattice of ferroelectric and paraelectric materials SnTiO3 (STO), respectively, and LaAlO3 (LAO) and STO, respectively. For example, a super lattice of [PTO/STO]n or [LAO/STO]n, where ‘n’ is between 1 to 2600. While various embodiments here are described with reference to ferroelectric material for storing the charge state, the embodiments are also applicable for paraelectric material. In some embodiments, paraelectric material includes one of: SrTiO3, Ba(x)Sr(y)TiO3 (where x is −0.5, and y is 0.95), HfZrO2, Hf—Si—O. The method of forming the structures described herein are applicable to various logic embodiments. For example, the FeRAM devices or capacitive structures formed herein can be used to forming other ferroelectric/paraelectric circuits. These circuits can be implemented majority gate, minority gate and/or threshold gate. Following examples are provided that illustrate the various embodiments. The examples can be combined with other examples. As such, various embodiments can be combined with other embodiments without changing the scope of the invention. FIG.27illustrates 3-input majority gate2700using non-linear input capacitors, in accordance with some embodiments. In some embodiments, 3-input majority gate2700comprises non-linear input capacitors C1nl, C2nl, and C3nlthat receives digital signals a, b, and c, respectively. Here, signal names and node names are interchangeably used. For example, ‘a’ refers to node ‘a’ or signal ‘a’ depending on the context of the sentence. One end or terminal of capacitor C1nlis coupled to node a while the other end of capacitor C1nlis coupled to summing node Vs. The same is true for other non-linear capacitors C2nland C3nlas shown. In some embodiments, 3-input majority gate2700comprises a driver circuitry2701. In this example, driver circuitry2701is an inverter. In other embodiments, other types of driver circuitries can be used such as NAND gate, NOR gate, multiplexer, buffer, and other logic gates. The majority function is performed at summing node Vs as Majority(a,b,c). In this example, since driver circuitry2701is an inverter, minority function is performed at output “out” as Minority(a,b,c). In some embodiments, in addition to the gate capacitance of driver circuitry2701, an additional linear capacitor CL is coupled to summing node Vs and ground as shown. In some embodiments, this linear capacitor CL is a non-ferroelectric capacitor. In some embodiments, the non-ferroelectric capacitor includes one of: dielectric capacitor, para-electric capacitor, or non-linear dielectric capacitor. A dielectric capacitor comprises first and second metal plates with a dielectric between them. Examples of such dielectrics are: HfOX, ABO3 perovskites, nitrides, oxy-fluorides, oxides, etc. A para-electric capacitor comprises first and second metal plates with a para-electric material between them. In some embodiments, f-orbital materials (e.g., lanthanides) are doped to the ferroelectric materials to make paraelectric material. Examples of room temperature paraelectric material include: SrTiO3, Ba(x)Sr(y)TiO3 (where x is −0.5, and y is 0.95)), HfZrO2, Hf—Si—O, La-substituted PbTiO3, PMN-PT based relaxor ferroelectrics. A dielectric capacitor comprises first and second metal plates with non-linear dielectric capacitor between them. The range for dielectric constant is 1.2 to 10000. The capacitor CL can be implemented as MIM (metal-insulator-metal) capacitor technology, transistor gate capacitor, hybrid of metal capacitors or transistor capacitor. The capacitor CL can be implemented as MIM (metal-insulator-metal) capacitor technology, transistor gate capacitor, or hybrid of metal capacitors or transistor capacitor. In some embodiments, the non-linear input capacitors C1nl, C2nl, and C3nlcomprise non-linear polar material. In some embodiments, the non-linear polar material includes one of: ferroelectric (FE) material, para-electric material, relaxor ferroelectric, or non-linear dielectric. In various embodiments, para-electric material is the same as FE material but with chemical doping of the active ferroelectric ion by an ion with no polar distortion. In some cases, the non-polar ions are non-s orbital ions formed with p, d, f external orbitals. In some embodiments, non-linear dielectric materials are same as para-electric materials, relaxors, and dipolar glasses. In some embodiments, f-orbital materials (e.g., lanthanides) are doped to the ferroelectric material to make paraelectric material. Examples of room temperature paraelectric material include: SrTiO3, Ba(x)Sr(y)TiO3 (where x is −0.5, and y is 0.95), HfZrO2, Hf—Si—O. In various embodiments, the FE material can be any suitable low voltage FE material that allows the FE material to switch its state by a low voltage (e.g., 100 mV). In some embodiments, the FE material comprises a perovskite of the type ABO3, where ‘A’ and ‘B’ are two cations of different sizes, and ‘O’ is oxygen which is an anion that bonds to both the cations. Generally, the size of A atoms is larger than the size of B atoms. In some embodiments, the perovskite can be doped (e.g., by La or Lanthanides). Perovskites can be suitably doped to achieve a spontaneous distortion in a range of 0.3 to 2%. For example, for chemically substituted lead titanate such as Zr in Ti site; La, Nb in Ti site, the concentration of these substitutes is such that it achieves the spontaneous distortion in the range of 0.3 to 2%. For chemically substituted BiFeO3, BiCrO3, BiCoO3 class of materials, La or rare earth substitution into the Bi site can tune the spontaneous distortion. In some embodiments, perovskite includes one of: BaTiO3, KNbO3, or NaTaO3. Threshold in the FE material has a highly non-linear transfer function in the polarization vs. voltage response. The threshold is related to: a) non-linearity of switching transfer function; and b) the squareness of the FE switching. The non-linearity of switching transfer function is the width of the derivative of the polarization vs. voltage plot. The squareness is defined by the ratio of the remnant polarization to the saturation polarization; perfect squareness will show a value of 1. The squareness of the FE switching can be suitably manipulated with chemical substitution. For example, in PbTiO3 a P-E (polarization-electric field) square loop can be modified by La or Nb substitution to create an S-shaped loop. The shape can be systematically tuned to ultimately yield a non-linear dielectric. The squareness of the FE switching can also be changed by the granularity of the FE layer. A perfect epitaxial, single crystalline FE layer will show higher squareness (e.g., ratio is closer to 1) compared to a poly crystalline FE. This perfect epitaxial can be accomplished using lattice matched bottom and top electrodes. In one example, BiFeO (BFO) can be epitaxially synthesized using a lattice matched SrRuO3 bottom electrode yielding P-E loops that are square. Progressive doping with La will reduce the squareness. In some embodiments, the FE material is contacted with a conductive metal oxide that includes one of the conducting perovskite metallic oxides exemplified by: La—Sr—CoO3, SrRuO3, La—Sr—MnO3, YBa2Cu3O7, Bi2Sr2CaCu2O27, LaNiO3, and ReO3. In some embodiments, the FE material comprises a stack of layers including low voltage FE material between (or sandwiched between) conductive oxides. In various embodiments, when FE material is a perovskite, the conductive oxides are of the type AA′BB′O3. A′ is a dopant for atomic site A, it can be an element from the Lanthanides series. B′ is a dopant for atomic site B, it can be an element from the transition metal elements especially Sc, Ti, V, Cr, Mn, Fe, Co, Ni, Cu, Zn. A′ may have the same valency of site A, with a different ferroelectric polarizability. In some embodiments, the FE material comprises hexagonal ferroelectrics of the type h-RMnO3, where R is a rare earth element such as: cerium (Ce), dysprosium (Dy), erbium (Er), europium (Eu), gadolinium (Gd), holmium (Ho), lanthanum (La), lutetium (Lu), neodymium (Nd), praseodymium (Pr), promethium (Pm), samarium (Sm), scandium (Sc), terbium (Tb), thulium (Tm), ytterbium (Yb), and yttrium (Y). The ferroelectric phase is characterized by a buckling of the layered MnO5 polyhedra, accompanied by displacements of the Y ions, which lead to a net electric polarization. In some embodiments, hexagonal FE includes one of: YMnO3 or LuFeO3. In various embodiments, when the FE material comprises hexagonal ferroelectrics, the conductive oxides adjacent to the FE material are of A2O3 (e.g., In2O3, Fe2O3) and AB2O3 type, where ‘A’ is a rare earth element and B is Mn. In some embodiments, FE material comprises improper FE material. An improper ferroelectric is a ferroelectric where the primary order parameter is an order mechanism such as strain or buckling of the atomic order. Examples of improper FE material are LuFeO3 class of materials or super lattice of ferroelectric and paraelectric materials. While various embodiments here are described with reference to ferroelectric material for storing the charge state, the embodiments are also applicable for paraelectric material. For example, the capacitor of various embodiments can be formed using paraelectric material instead of ferroelectric material. In some embodiments, the FE material includes one of: Hafnium (Hf), Zirconium (Zr), Aluminum (Al), Silicon (Si), their oxides or their alloyed oxides. In some embodiments, FE material includes one of: Al(1−x)Sc(x)N, Ga(1−x)Sc(x)N, Al(1−x)Y(x)N or Al(1−x−y)Mg(x)Nb(y)N, y doped HfO2, where x includes one of: Al, Ca, Ce, Dy, Er, Gd, Ge, La, Sc, Si, Sr, Sn, or Y, wherein ‘x’ is a fraction. In some embodiments, the FE material includes Bismuth ferrite (BFO) or BFO with doping material. In some embodiments, the FE material includes Bismuth ferrite (BFO), BFO with a doping material where in the doping material is one of Lanthanum, or any element from the lanthanide series of the periodic table. In some embodiments, the FE material includes a relaxor ferroelectric including one of Barium Titanium-Bismuth Zinc Niobium Tantalum (BT-BZNT), or Barium Titanium-Barium Strontium Titanium (BT-BST). In some embodiments, the FE material includes Hafnium oxides of the form, Hf1−x Ex Oy where E can be Al, Ca, Ce, Dy, er, Gd, Ge, La, Sc, Si, Sr, Sn, or Y. In some embodiments, FE material includes Niobate type compounds LiNbO3, LiTaO3, Lithium iron Tantalum Oxy Fluoride, Barium Strontium Niobate, Sodium Barium Niobate, or Potassium strontium niobate. In some embodiments, the FE material comprises multiple layers. For example, alternating layers of [Bi2O2]2+, and pseudo-perovskite blocks (Bi4Ti3O12 and related Aurivillius phases), with perovskite layers that are n octahedral layers in thickness can be used. In some embodiments, the FE material comprises organic material. For example, Polyvinylidene fluoride or polyvinylidene difluoride (PVDF). The FE material is between two electrodes. These electrodes are conducting electrodes. In some embodiments, the electrodes are perovskite templated conductors. In such a templated structure, a thin layer (e.g., approximately 10 nm) of a perovskite conductor (such as SrRuO3) is coated on top of IrO2, RuO2, PdO2, or PtO2 (which have a non-perovskite structure but higher conductivity) to provide a seed or template for the growth of pure perovskite ferroelectric at low temperatures. In some embodiments, when the ferroelectric comprises hexagonal ferroelectric material, the electrodes can have hexagonal metals, spinels, or cubic metals. Examples of hexagonal metals include: PtCoO2, PdCoO2, and other delafossite structured hexagonal metallic oxides such as Al-doped ZnO. Examples of spinels include Fe3O4and LiV2O4. Examples of cubic metals include Indium Tin Oxide (ITO) such as Sn-doped In2O3. The charge developed on node Vs produces a voltage and current that is the output of the majority gate2700. Any suitable driver circuitry2701can drive this output. For example, a non-FE logic, FE logic, CMOS logic, BJT logic, etc. can be used to drive the output to a downstream logic. Examples of the drivers include inverters, buffers, NAND gates, NOR gates, XOR gates, amplifiers, comparators, digital-to-analog converters, analog-to-digital converters, multiplexers, etc. The majority function is performed at the summing node Vs, and the resulting voltage is projected on to capacitance of driver circuitry2701. For example, the majority function of the currents (Ia, Ib, and Ic) on node Vs results in a resultant current that charges capacitor. Table 1 illustrates the majority function f(Majority a, b, c). TABLE 1abcVs (f(Majority a, b, c))00000010010001111000101111011111 The charge developed on node VSproduces a voltage and current that is the output of the majority gate2700. Any suitable driver circuitry2701can drive this output. For example, a non-FE logic, FE logic, CMOS logic, BJT logic, etc. can be used to drive the output to a downstream logic. Examples of the drivers include inverters, buffers, NAND gates, NOR gates, XOR gates, amplifiers, comparators, digital-to-analog converters, analog-to-digital converters, multiplexers, etc. WhileFIG.27illustrates a 3-input majority gate, the same concept can be extended to more than 3 inputs to make an N-input majority gate, where N is greater than 2. In various embodiments, ‘N’ is an odd number. For example, a 5-input majority gate is like an input majority gate2700but for additional inputs ‘d’ and ‘e’. These inputs can come from the same drivers or from different drivers. In some embodiments, the 3-input majority gate can be configured as a fast inverter with a much faster propagation delay compared to a similar sized (in terms of area footprint) CMOS inverter. This is particularly useful when the inputs have a significantly slower slope compared to the propagation delay through the non-linear input capacitors. One way to configurate the 3-input majority gate as an inverter is to set one input to a logic high (e.g., b=1) and set another input to a logic low (e.g., b=0). The third input is the driving input which is to be inverted. The inversion will be at the Vs node. The same technique can also be applied to N−input majority gate, where ‘N’ is 1 or any other odd number. In an N-input majority gate, (N−1)/2 inputs are set to ‘1’ and (N−1)/2 inputs are set to ‘0’, and one input is used to decide the inversion function. It will be appreciated that the various embodiments are described as a majority gate, the same concepts are applicable to a minority gate. In a minority gate the driving circuitry is an inverting circuitry coupled to the summing node Vs. The minority function is seen at the output of the inverting circuitry. In some embodiments, (2N−1) input majority gate can operate as an N-input AND gate where (N−1) inputs of the majority gate are set to zero. The AND function will be seen at the summing node Vs. Similarly, N-input NAND, OR, NOR gates can be realized. In various embodiments, the summing node Vs is driven by a driver circuitry (e.g., inverter, buffer, NAND gate, AND gate, OR gate, NOR gate, or any other logic circuitry). However, driver circuitry2701can be replaced with another majority or minority gate. In one such embodiment, the storage node Vs is directly coupled to a non-linear capacitor of another majority or minority gate. Any logic function f(x1, x2, . . . xn) can be represented by two levels of logic as given by the min-term expansion: f(x1, x2, . . . xn)=VC1, C2. . . cnf(x1, x2, . . . xn)∧x1C1∧x2C2∧x3C3. . . ∧xnCnwhere Ciis either 0 or 1. When Ciis 1, xiCis i=xi(the input is used in its original form). When Ciis 0, xiCi=xi(the input is used in its inverted form). The first level of logic is represented by at most 2nAND gates (Δ), one for each of the 2npossible combinations of 0 and 1 for C1, C2, . . . Cn. The second level of logic is represented by a single OR gate (∨). Each operand of the OR gate is a representation of a row in the truth table for f(x1, x2, . . . xn). A (2N−1)-input majority gate can represent an N-input AND gate, by tying (N−1) of the majority gate's inputs to a ground level. Similarly, a (2N−1)-input majority gate can represent an N-input OR gate, by tying (N−1) of the majority gate's inputs to a supply level (Vdd). Since a majority gate can represent AND and OR gates, and the inputs to the AND and OR gates are either original or inverted forms of the input digital signals, any logic function can be represented by majority gates and inverters only, in accordance with some embodiments. FIG.28illustrates complex logic gate2800implemented using a 5-input majority gate, in accordance with some embodiments. In some embodiments, an AOI (and-or-invert) logic comprises a 5-input majority gate. The 5-input majority gate includes non-linear capacitors C1nl, C2nl, C3nl, C4nl, and C5nland driving circuitry2801coupled as shown. In various embodiments, two of the non-linear capacitors receives the same input. Here, capacitors C3nland C4nlreceive input ‘c’. In various embodiments, C5nlis coupled to Vdd to produce an OR function at node Vs, where the OR function is OR(AND(a,b),c). In some embodiments, other logic gates can be realized by changing Vdd to ground for capacitor C5nl, and/or changing other inputs. Following examples are provided that illustrate the various embodiments. The examples can be combined with other examples. As such, various embodiments can be combined with other embodiments without changing the scope of the invention. Example 1: A device comprising: a first region comprising: a first conductive interconnect within a first dielectric in a first level; a second level above the first level, the second level comprising: an electrode structure on the first conductive interconnect, the electrode structure comprising: a first conductive hydrogen barrier layer; and a first conductive fill material on the first conductive hydrogen barrier layer, wherein the electrode structure comprises a first lateral thickness; an etch stop layer comprising an insulator, the etch stop layer laterally surrounding the electrode structure; a memory device comprising a ferroelectric material or a paraelectric material on least a portion of the electrode structure, the memory device further comprising a second lateral thickness, wherein the second lateral thickness is less than the first lateral thickness; a second dielectric spanning the first region and on the etch stop layer, the second dielectric comprising an amorphous, greater than 90% film density hydrogen barrier material, wherein the memory device is directly adjacent to and embedded within the second dielectric; and a via electrode on at least a portion of the memory device, the via electrode comprising: a second conductive hydrogen barrier layer comprising a lateral portion in contact with the memory device; substantially vertical portions directly adjacent to the second dielectric; and a second conductive fill material adjacent to the second conductive hydrogen barrier layer; and a second region adjacent to the first region, the second region comprising: a second conductive interconnect within the first level; the second level further comprising: a third conductive interconnect; a via structure coupled between the second conductive interconnect and the third conductive interconnect; and a third dielectric on the etch stop layer, the third dielectric directly adjacent to the second dielectric, wherein the third dielectric comprises a less than 90% film density material, wherein the third dielectric laterally surrounds a portion of the via structure. Example 2: The device of example 1, wherein the second dielectric comprises AlxOy, HfOX, AlSiOx, ZrOx, TiOx, AlSiOx, HfSiOx, TaSiOx, AlN, ZrN, or HfN. Example 3: The device of example 1, wherein the third dielectric comprises SiO2, SiOC, SiC or SiO2doped with F. Example 4: The device of example 1, wherein the etch stop layer comprises silicon and one or more of nitrogen and carbon and the second dielectric does not comprise silicon nitride. Example 5: The device of example 1, wherein the first conductive hydrogen barrier layer and the second conductive hydrogen barrier layer comprise TiAlN, with greater than 30 atomic percent AlN, TaN with greater than 30 atomic percent N2, TiSiN with greater than 20 atomic percent SiN, TaC, TiC, WC, WN, carbonitrides of Ta, Ti or W, TiO, Ti2O, WO3, SnO2, ITO, IGZO, ZO or METGLAS series of alloys. Example 6: The device of example 1, wherein the first conductive hydrogen barrier layer and the second conductive hydrogen barrier layer comprise different materials. Example 7: The device of example 1, wherein the first conductive hydrogen barrier layer and the second conductive hydrogen barrier layer comprise a thickness of least 1 nm. Example 8: The device of example 1, wherein the first conductive hydrogen barrier layer laterally surrounds the first conductive fill material, and wherein the memory device is not in contact with the first conductive hydrogen barrier layer. Example 9: The device of example 1, wherein the first conductive hydrogen barrier layer laterally surrounds the first conductive fill material, and wherein a portion of the first conductive hydrogen barrier layer and a portion of the first conductive fill material are in contact with a lower most surface of the memory device. Example 10: The device of example 1, wherein the electrode structure further comprises a first liner layer directly between the first conductive hydrogen barrier layer and the first conductive fill material and wherein the first liner layer comprises a material that is different from a material of the first conductive hydrogen barrier layer. Example 11: The device of example 1, wherein the via electrode further comprises a second liner layer between the second conductive hydrogen barrier layer and the second conductive fill material, and wherein the second liner layer comprises a material that is different from a material of the second conductive hydrogen barrier layer. Example 12: The device of example 1, wherein the etch stop layer comprises a first vertical thickness that is equal to a second vertical thickness of the electrode structure. Example 13: The device of example 1, wherein the third conductive interconnect has a lower most surface that is below an uppermost surface of the memory device. Example 14: The device of example 1, wherein the second conductive hydrogen barrier layer extends on an entire uppermost surface of the memory device. Example 15: The device of example 1, wherein the second conductive hydrogen barrier layer further extends below the uppermost surface and on to a portion of a sidewall of a top electrode of the memory device. Example 16: The device of example 1, wherein the memory device comprises a curved uppermost surface, and wherein the second conductive hydrogen barrier layer extends over an entire curved uppermost surface. Example 17: The device of example 1, wherein the via electrode is not symmetric about the memory device. Example 18: The device of example 1, wherein the first conductive interconnect has a third lateral thickness that is smaller than the first lateral thickness. Example 19: The device of example 18, wherein first conductive hydrogen barrier layer extends over an uppermost surface of the first conductive interconnect and below the uppermost surface on a top portion of a sidewall of the first conductive interconnect. Example 20: The device of example 1, wherein the third conductive interconnect has a lower most surface that is above an uppermost surface of the memory device. Example 21: The device of example 1, wherein the third conductive interconnect has a lower most surface that is below an uppermost surface of the memory device. Example 22: The device of example 1, wherein the via structure comprises an upper portion and a lower portion, wherein the lower portion is adjacent to the etch stop layer and the upper portion is adjacent to the third dielectric. Example 23: The device of example 1, wherein the ferroelectric material comprises one of: bismuth ferrite (BFO), BFO with a doping material where in the doping material is one of lanthanum, or elements from lanthanide series of periodic table; lead zirconium titanate (PZT), or PZT with a doping material, wherein the doping material is one of La, Nb; a relaxor ferroelectric material which includes one of lead magnesium niobate (PMN), lead magnesium niobate-lead titanate (PMN-PT), lead lanthanum zirconate titanate (PLZT), lead scandium niobate (PSN), barium titanium-bismuth zinc niobium tantalum (BT-BZNT), or Barium titanium-barium strontium titanium (BT-BST); a perovskite material which includes one of: BaTiO3, PbTiO3, KNbO3, or NaTaO3; hexagonal ferroelectric which includes one of: YMnO3, or LuFeO3; hexagonal ferroelectrics of a type h-RMnO3, where R is a rare earth element which includes one of: cerium (Ce), dysprosium (Dy), erbium (Er), europium (Eu), gadolinium (Gd), holmium (Ho), lanthanum (La), lutetium (Lu), neodymium (Nd), praseodymium (Pr), promethium (Pm), samarium (Sm), scandium (Sc), terbium (Tb), thulium (Tm), ytterbium (Yb), or yttrium (Y); Hafnium (Hf), Zirconium (Zr), Aluminum (Al), Silicon (Si), their oxides or their alloyed oxides; Hafnium oxides as Hf1−x Ex Oy, where E can be Al, Ca, Ce, Dy, er, Gd, Ge, La, Sc, Si, Sr, Sn, Zr, or Y; Al(1−x)Sc(x)N, Ga(1−x)Sc(x)N, Al(1−x)Y(x)N or Al(1−x−y)Mg(x)Nb(y)N, y doped HfO2, where x includes one of: Al, Ca, Ce, Dy, Er, Gd, Ge, La, Sc, Si, Sr, Sn, or Y, wherein ‘x’ is a fraction; or niobate type compounds LiNbO3, LiTaO3, lithium iron tantalum oxy fluoride, barium strontium niobate, sodium barium niobate, or potassium strontium niobate; or an improper ferroelectric material which includes one of: [PTO/STO]n or [LAO/STO]n, where ‘n’ is between 1 to 100. Example 24: The device of example 1, wherein the paraelectric material comprises SrTiO3, Ba(x)Sr(y)TiO3 (where x is −0.05, and y is 0.95), HfZrO2, Hf—Si—O, La-substituted PbTiO3, or a PMN-PT based relaxor ferroelectrics. Example 25: The device of example 1, wherein the first conductive material comprises an uppermost surface that is concaved, and wherein the memory device comprises a lower most surface that is substantially matched with the uppermost surface of the first conductive material. Example 26: The device of example 1, wherein a portion of the first conductive material not covered by the memory device is recessed below an uppermost surface of the first conductive material and wherein the second dielectric extends below a lowermost surface of the memory device. Example 27: The device of example 1, wherein the first conductive material comprises a first surface in contact with the memory device, and a second surface not covered by the memory device, wherein the second surface is tapered to decrease in thickness away from the memory device. Example 28: A device comprising: a first region comprising: a first conductive interconnect within a first dielectric in a first level; a second level above the first level, the second level comprising: an electrode structure on the first conductive interconnect, the electrode structure comprising: a first conductive hydrogen barrier layer; and a first conductive fill material on the first conductive hydrogen barrier layer, wherein the electrode structure comprises a first lateral thickness; an etch stop layer comprising an insulator, the etch stop layer laterally surrounding the electrode structure; a memory device comprising a ferroelectric material or a paraelectric material on least a portion of the electrode structure, the memory device further comprising a second lateral thickness, wherein the second lateral thickness is greater than the first lateral thickness; a second dielectric spanning the first region and on the etch stop layer, the second dielectric comprising an amorphous, greater than 90% film density hydrogen barrier material, wherein the memory device is directly adjacent to and embedded within the second dielectric; and a via electrode on at least a portion of the memory device, the via electrode comprising: a second conductive hydrogen barrier layer comprising a lateral portion in contact with the memory device; substantially vertical portions directly adjacent to the second dielectric; and a second conductive fill material adjacent to the second conductive hydrogen barrier layer; and a second region adjacent to the first region, the second region comprising: a second conductive interconnect within the first level; the second level further comprising: a third conductive interconnect; a via structure coupled between the second conductive interconnect and the third conductive interconnect; and a third dielectric on the etch stop layer, the third dielectric directly adjacent to the second dielectric, wherein the third dielectric comprises a less than 90% film density material, wherein the third dielectric laterally surrounds a portion of the via structure. Example 29: The device of example 27, wherein the first conductive hydrogen barrier layer and the second conductive hydrogen barrier layer comprise TiAlN, with >30 atomic percent AlN, TaN with >30 atomic percent N2, TiSiN with >20 atomic percent SiN, TaC, TiC, WC, WN, carbonitrides of Ta, Ti or W, TiO, Ti2O, WO3, SnO2, ITO, IGZO, ZO or METGLAS series of alloys. Example 30: The device of example 27, wherein the memory device is in contact with the first conductive hydrogen barrier layer and the first conductive fill material, and wherein the memory device covers the electrode structure. Example 31: The device of example 27, wherein the via electrode further comprises a liner layer between the second conductive hydrogen barrier layer and the second conductive fill material, wherein the liner layer comprises a material that is different from a material of the second conductive hydrogen barrier layer. Example 32: The device of example 27, wherein the memory device is in contact with the first conductive hydrogen barrier layer and the first conductive material, and wherein the memory device covers the electrode structure. Example 33: The device of example 27, wherein the first conductive hydrogen barrier layer laterally surrounds the first conductive material, and wherein a portion of the first conductive hydrogen barrier layer and a portion of the first conductive material are in contact with a lower most surface of the memory device. Example 34: The device of example 27, wherein the first conductive material comprises an uppermost surface that is concaved, and wherein the memory device comprises a lower most surface that is substantially matched with the uppermost surface of the first conductive material. Example 35: The device of example 27, wherein the memory device further extends on to an uppermost surface of the etch stop layer, and wherein a portion of the etch stop layer not covered by the memory device is recessed below an uppermost surface of the etch stop layer and wherein the second dielectric extends below a lowermost surface of the memory device. Example 36: The device of example 27, wherein the etch stop layer comprises a first surface in contact with the memory device, and a second surface not covered by the memory device, wherein the second surface is tapered to decrease in thickness away from the memory device. Example 37: The device of example 27, wherein the second dielectric comprises AlxOy, HfOX, AlSiOx, ZrOx, TiOx, AlSiOx, HfSiOx, TaSiOx, AlN, ZrN, or HfN and wherein the third dielectric comprises SiO2, SiOC, SiC or SiO2doped with F. Example 38: A system comprising: a processor; a communication interface communicatively coupled to the processor; and a memory coupled to the processor, wherein the memory comprises: bit-cells, wherein one of the bit-cells includes: a first region comprising: a first conductive interconnect within a first dielectric in a first level; a second level above the first level, the second level comprising: an electrode structure on the first conductive interconnect, the electrode structure comprising: a first conductive hydrogen barrier layer; and a first conductive fill material on the first conductive hydrogen barrier layer, wherein the electrode structure comprises a first lateral thickness; an etch stop layer comprising an insulator, the etch stop layer laterally surrounding the electrode structure; a memory device comprising a ferroelectric material or a paraelectric material on least a portion of the electrode structure, the memory device further comprising a second lateral thickness, wherein the second lateral thickness is less than the first lateral thickness; a second dielectric spanning the first region and on the etch stop layer, the second dielectric comprising an amorphous, greater than 90% film density hydrogen barrier material, wherein the memory device is directly adjacent to and embedded within the second dielectric; and a via electrode on at least a portion of the memory device, the via electrode comprising: a second conductive hydrogen barrier layer comprising a lateral portion in contact with the memory device; substantially vertical portions directly adjacent to the second dielectric; and a second conductive fill material adjacent to the second conductive hydrogen barrier layer; and a second region adjacent to the first region, the second region comprising: a second conductive interconnect within the first level; the second level further comprising: a third conductive interconnect; a via structure coupled between the second conductive interconnect and the third conductive interconnect; and a third dielectric on the etch stop layer, the third dielectric directly adjacent to the second dielectric, wherein the third dielectric comprises a less than 90% film density material, wherein the third dielectric laterally surrounds a portion of the via structure. Example 1a: A device comprising: a first region comprising: a first conductive interconnect within a first dielectric in a first level; a second level above the first level, the second level comprising: an electrode structure on the first conductive interconnect, the electrode structure comprising: a first conductive material; and a first conductive hydrogen barrier layer on the first conductive material, wherein the electrode structure comprises a first lateral thickness; an etch stop layer comprising an insulator, the etch stop layer laterally surrounding the electrode structure; a memory device comprising a ferroelectric material or a paraelectric material on least a portion of the electrode structure, the memory device further comprising a second lateral thickness, wherein the second lateral thickness is less than the first lateral thickness; a second dielectric spanning the first region, the second dielectric comprising an amorphous, greater than 90% film density hydrogen barrier material, wherein the memory device is directly adjacent to and embedded within the second dielectric; and a via electrode on at least a portion of the memory device, the via electrode comprising: a second conductive hydrogen barrier layer comprising a lateral portion in contact with the memory device; substantially vertical portions directly adjacent to the second dielectric; and a conductive fill material adjacent to the second conductive hydrogen barrier layer; and a second region adjacent to the first region, the second region comprising: a second conductive interconnect within the first level; the second level further comprising: a third conductive interconnect; a via structure coupled between the second conductive interconnect and the third conductive interconnect; and a third dielectric on the etch stop layer, the third dielectric directly adjacent to the second dielectric, wherein the third dielectric comprises a less than 90% film density material, wherein the third dielectric laterally surrounds a portion of the via structure. Example 2a: The device of example 1a, wherein the via electrode further comprises a second liner layer between the second conductive hydrogen barrier layer and the conductive fill material, wherein the second liner layer comprises a material that is different from a material of the second conductive hydrogen barrier layer. Example 3a: The device of example 1a, wherein the lateral portion of the second conductive hydrogen barrier layer is on a first portion of an uppermost surface of the memory device, and wherein the second dielectric is on a second portion of an uppermost surface of the memory device and directly adjacent to sidewalls of the memory device and wherein the lateral portion is directly between the second dielectric. Example 4a: The device of example 1a, wherein the second conductive hydrogen barrier layer extends on an entire uppermost surface of the memory device. Example 5a: The device of example 1a, wherein the second conductive hydrogen barrier layer further extends below the uppermost surface and on to a portion of a sidewall of a top electrode of the memory device. Example 6a: A device comprising: a first region comprising: a first conductive interconnect within a first dielectric in a first level; a second level above the first level, the second level comprising: an electrode structure on the first conductive interconnect, the electrode structure comprising: a first conductive material; and a first conductive hydrogen barrier layer on the first conductive material, wherein the electrode structure comprises a first lateral thickness; an etch stop layer comprising an insulator, the etch stop layer laterally surrounding the electrode structure; a memory device comprising a ferroelectric material or a paraelectric material on least a portion of the electrode structure, the memory device further comprising a second lateral thickness, wherein the second lateral thickness is greater than the first lateral thickness; a second dielectric spanning the first region, the second dielectric comprising an amorphous, greater than 90% film density hydrogen barrier material, wherein the memory device is directly adjacent to and embedded within the second dielectric; and a via electrode on at least a portion of the memory device, the via electrode comprising: a second conductive hydrogen barrier layer comprising a lateral portion in contact with the memory device; substantially vertical portions directly adjacent to the second dielectric; and a conductive fill material adjacent to the second conductive hydrogen barrier layer; and a second region adjacent to the first region, the second region comprising: a second conductive interconnect within the first level; the second level further comprising: a third conductive interconnect; a via structure coupled between the second conductive interconnect and the third conductive interconnect; and a third dielectric on the etch stop layer, the third dielectric directly adjacent to the second dielectric, wherein the third dielectric comprises a less than 90% film density material, wherein the third dielectric laterally surrounds a portion of the via structure. Example 7a: A device comprising: a first conductive interconnect; an electrode structure on the first conductive interconnect, the electrode structure comprising: a first conductive material; and a first conductive hydrogen barrier layer on the first conductive material; an etch stop layer comprising an insulator, the etch stop layer laterally surrounding the electrode structure; a memory device on least a portion of the electrode structure, the memory device comprising a ferroelectric material or a paraelectric material; a second dielectric spanning the first region, the second dielectric comprising an amorphous, greater than 90% film density hydrogen barrier material, wherein the hydrogen barrier material further comprises a transition metal, and wherein the memory device is directly adjacent to and embedded within the second dielectric; a via electrode on at least a portion of the memory device, the via electrode comprising: a second conductive hydrogen barrier layer comprising a lateral portion in contact with the memory device and substantially vertical portions directly adjacent to the second dielectric; and a conductive fill material adjacent to the second conductive hydrogen barrier layer. Example 1b; A device comprising a first region, the first region comprising a first conductive interconnect within a first dielectric in a first level; a second level above the first level, the second level comprising: an electrode structure on the first conductive interconnect, the electrode structure comprising a first conductive hydrogen barrier layer; and a first conductive fill material on the first conductive hydrogen barrier layer, wherein the electrode structure comprises a first lateral thickness; an etch stop layer comprising an insulator, the etch stop layer laterally surrounding the electrode structure; a memory device comprising a ferroelectric material or a paraelectric material on least a portion of the electrode structure, the memory device further comprising a second lateral thickness, wherein the second lateral thickness is less than the first lateral thickness; an encapsulation layer comprising a first amorphous, greater than 90% film density hydrogen barrier material directly on a sidewall of the memory device; a second dielectric spanning the first region, the second dielectric comprising a second amorphous, greater than 90% film density hydrogen barrier material adjacent the encapsulation layer; a via electrode on at least a portion of the memory device, the via electrode comprising: a second conductive hydrogen barrier layer comprising a lateral portion in contact with the memory device; substantially vertical portions directly adjacent to the second dielectric; and a second conductive fill material adjacent to the second conductive hydrogen barrier layer; a second region adjacent to the first region, the second region comprising: a second conductive interconnect within the first level; the second level further comprising: a third conductive interconnect; a via structure coupled between the second conductive interconnect and the third conductive interconnect; and a third dielectric on the etch stop layer, the third dielectric directly adjacent to the second dielectric and the encapsulation layer, wherein the third dielectric comprises a less than 90% film density material, wherein the third dielectric laterally surrounds a portion of the via structure. Example 2b: The device of example 1b, wherein the encapsulation layer comprises AlxOy, HfOX, AlSiOx, ZrOx, TiOx, AlSiOX, HfSiOX, TaSiOX, AlN, ZrN, or HfN, and wherein the encapsulation layer comprises a material that is different from a material of the second dielectric. Example 3b: The device of example 1b, wherein the encapsulation layer comprises a thickness of less than 5 nm. Example 4b: The device of example 1b, wherein the encapsulation layer comprises a thickness adjacent to an uppermost surface of the memory device that is greater than a thickness adjacent to a lowermost surface of the memory device. Example 5b: The device of example 1b, wherein the via electrode comprises a third lateral thickness that is less than the second lateral thickness and wherein an uppermost surface of the memory device comprises a first surface portion and a second surface portion, wherein the encapsulation layer is further on a first surface portion wherein the via electrode is on the second surface portion. Example 6b: The device of example 1b, wherein the via electrode comprises a third lateral thickness that is greater than the second lateral thickness and wherein the via electrode covers an uppermost surface of the memory device. Example 7b: The device of example 6b, wherein the via electrode further extends below the uppermost surface of the memory device and wherein the via electrode is on a portion of the encapsulation layer. Example 8b: The device of example 6b, wherein the encapsulation layer is in contact with the first conductive hydrogen barrier layer and wherein the encapsulation layer is further on an uppermost surface of the first conductive fill material. Example 9b: A device comprising: a first region comprising: a first conductive interconnect within a first dielectric in a first level; and a second level above the first level, the second level comprising: an electrode structure on the first conductive interconnect, the electrode structure comprising: a first conductive hydrogen barrier layer; and a first conductive fill material on the first conductive hydrogen barrier layer, wherein the electrode structure comprises a first lateral thickness; an etch stop layer comprising an insulator, the etch stop layer laterally surrounding the electrode structure; a memory device comprising a ferroelectric material or a paraelectric material on least a portion of the electrode structure, the memory device further comprising a second lateral thickness, wherein the second lateral thickness is greater than the first lateral thickness; an encapsulation layer comprising a first amorphous, greater than 90% film density hydrogen barrier material directly on a sidewall of the memory device; a second dielectric spanning the first region, the second dielectric comprising a second amorphous, greater than 90% film density hydrogen barrier material adjacent the encapsulation layer; a via electrode on at least a portion of the memory device, the via electrode comprising: a second conductive hydrogen barrier layer comprising a lateral portion in contact with the memory device; substantially vertical portions directly adjacent to the second dielectric; and a second conductive fill material adjacent to the second conductive hydrogen barrier layer; and a second region adjacent to the first region, the second region comprising: a second conductive interconnect within the first level; the second level further comprising: a third conductive interconnect; a via structure coupled between the second conductive interconnect and the third conductive interconnect; and a third dielectric on the etch stop layer, the third dielectric directly adjacent to the second dielectric, wherein the third dielectric comprises a less than 90% film density material, wherein the third dielectric laterally surrounds a portion of the via structure. Example 10b: The device of example 9b, wherein the encapsulation layer is on the etch stop layer but not in contact with the first conductive hydrogen barrier layer or the first conductive fill material. Example 11b: The device of example 9b, wherein the via electrode comprises a third lateral thickness that is greater than the second lateral thickness, wherein the via electrode covers an uppermost surface of the memory device, wherein the via electrode further extends below the uppermost surface of the memory device and wherein the via electrode is on a portion of the encapsulation layer. Example 12b: A system comprises a processor; a communication interface communicatively coupled to the processor; and a memory coupled to the processor, wherein the memory comprises: bit-cells, wherein one of the bit-cells includes a first region comprising a first conductive interconnect within a first dielectric in a first level; a second level above the first level, the second level comprising: an electrode structure on the first conductive interconnect, the electrode structure comprising a first conductive hydrogen barrier layer; and a first conductive fill material on the first conductive hydrogen barrier layer, wherein the electrode structure comprises a first lateral thickness; an etch stop layer comprising an insulator, the etch stop layer laterally surrounding the electrode structure; a memory device comprising a ferroelectric material or a paraelectric material on least a portion of the electrode structure, the memory device further comprising a second lateral thickness, wherein the second lateral thickness is less than the first lateral thickness; an encapsulation layer comprising a first amorphous, greater than 90% film density hydrogen barrier material directly on a sidewall of the memory device; a second dielectric spanning the first region, the second dielectric comprising a second amorphous, greater than 90% film density hydrogen barrier material adjacent the encapsulation layer; a via electrode on at least a portion of the memory device, the via electrode comprising: a second conductive hydrogen barrier layer comprising a lateral portion in contact with the memory device; substantially vertical portions directly adjacent to the second dielectric; and a second conductive fill material adjacent to the second conductive hydrogen barrier layer; a second region adjacent to the first region, the second region comprising: a second conductive interconnect within the first level; the second level further comprising: a third conductive interconnect; a via structure coupled between the second conductive interconnect and the third conductive interconnect; and a third dielectric on the etch stop layer, the third dielectric directly adjacent to the second dielectric and the encapsulation layer, wherein the third dielectric comprises a less than 90% film density material, wherein the third dielectric laterally surrounds a portion of the via structure. Example 1c: A method of fabricating a device structure, the method comprising: forming a first conductive interconnect in a first dielectric in a memory region and a second conductive interconnect in the first dielectric in a logic region; depositing an etch stop layer on the first dielectric and on the first conductive interconnect and on the second conductive interconnect; forming an electrode structure on the first conductive interconnect by a first process comprising: etching a first opening in the etch stop layer; depositing a first conductive hydrogen barrier layer in the first opening; and depositing a first conductive material on the first conductive hydrogen barrier layer; forming a memory device by depositing a material layer stack comprising a ferroelectric material or a paraelectric material on the electrode structure and etching the material layer stack; depositing a second dielectric comprising an amorphous, greater than 90% film density hydrogen barrier material on the memory device and on the etch stop layer; forming a via electrode on the memory device by a second process comprising: forming a second opening in the second dielectric; depositing a second conductive hydrogen barrier layer on at least a portion of a first uppermost surface of the memory device in the second opening; and depositing a second conductive material on the second conductive hydrogen barrier layer; etching and removing the second dielectric from the adjacent logic region and depositing a third dielectric comprising a less than 90% film density material; forming a hanging trench over the second conductive interconnect; forming a third opening in the third dielectric and in the etch stop layer; and depositing a conductive material in the third opening and in the hanging trench to form a via structure on the second conductive interconnect and a metal line on the via structure. Example 2c: The method of example 1c, wherein depositing the material layer stack comprises: depositing the ferroelectric material, comprising: one of bismuth ferrite (BFO), BFO with a first doping material where in the first doping material is one of lanthanum, or elements from lanthanide series of periodic table; lead zirconium titanate (PZT), or PZT with a second doping material, wherein the second doping material is one of La, Nb; a relaxor ferroelectric material which includes one of lead magnesium niobate (PMN), lead magnesium niobate-lead titanate (PMN-PT), lead lanthanum zirconate titanate (PLZT), lead scandium niobate (PSN), barium titanium-bismuth zinc niobium tantalum (BT-BZNT), or Barium titanium-barium strontium titanium (BT-BST); a perovskite material which includes one of: BaTiO3, PbTiO3, KNbO3, or NaTaO3; hexagonal ferroelectric which includes one of: YMnO3, or LuFeO3; hexagonal ferroelectrics of a type h-RMnO3, where R is a rare earth element which includes one of: cerium (Ce), dysprosium (Dy), erbium (Er), europium (Eu), gadolinium (Gd), holmium (Ho), lanthanum (La), lutetium (Lu), neodymium (Nd), praseodymium (Pr), promethium (Pm), samarium (Sm), scandium (Sc), terbium (Tb), thulium (Tm), ytterbium (Yb), or yttrium (Y); Hafnium (Hf), Zirconium (Zr), Aluminum (Al), Silicon (Si), their oxides or their alloyed oxides; Hafnium oxides as Hf1−x Ex Oy, where E can be Al, Ca, Ce, Dy, er, Gd, Ge, La, Sc, Si, Sr, Sn, Zr, or Y; Al(1−x)Sc(x)N, Ga(1−x)Sc(x)N, Al(1−x)Y(x)N or Al(1−x−y)Mg(x)Nb(y)N, y doped HfO2, where x includes one of: Al, Ca, Ce, Dy, Er, Gd, Ge, La, Sc, Si, Sr, Sn, or Y, wherein ‘x’ is a fraction; or niobate type compounds LiNbO3, LiTaO3, lithium iron tantalum oxy fluoride, barium strontium niobate, sodium barium niobate, or potassium strontium niobate; or an improper ferroelectric material which includes one of: [PTO/STO]n or [LAO/STO]n, where ‘n’ is between 1 to 100; or depositing the paraelectric material comprising SrTiO3, Ba(x)Sr(y)TiO3 (where x is −0.05, and y is 0.95), HfZrO2, Hf—Si—O, La-substituted PbTiO3, or a PMN-PT based relaxor ferroelectrics. Example 3c: The method of example 1c, wherein etching the first opening comprises forming the first opening with a first lateral thickness that is greater than a second lateral thickness of the first conductive interconnect, and wherein etching the material layer stack further comprises forming the memory device having a third lateral thickness that is less than the first lateral thickness. Example 4c: The method of example 3c, wherein depositing the first conductive hydrogen barrier layer comprises utilizing a first atomic layer deposition process to blanket deposit the first conductive hydrogen barrier layer on the first conductive interconnect and on sidewalls of the etch stop layer to form a conductive hydrogen barrier layer having a lateral portion and substantially vertical portions connected to the lateral portion. Example 5c: The method of example 4c, wherein depositing the first conductive hydrogen barrier layer comprises using the first atomic layer deposition process to deposit a material comprising TiAlN, with greater than 30 atomic percent AlN, TaN with greater than 30 atomic percent N2, TiSiN with greater than 20 atomic percent SiN, TaC, TiC, WC, WN, carbonitrides of Ta, Ti or W, TiO, Ti2O, WO3, SnO2, ITO, IGZO, ZO or METGLAS series of alloys. Example 6c: The method of example 5c, wherein forming the electrode structure further comprises performing a chemical mechanical planarization process to form the electrode structure that is substantially comprised of the first conductive material with a peripheral boundary comprising the first conductive hydrogen barrier layer, and wherein the first conductive material is planarized to form a second uppermost surface that is substantially co-planar with a third uppermost surface of the etch stop layer. Example 7c: The method of example 1c, wherein depositing the second dielectric comprises utilizing a second atomic layer deposition process to deposit a material comprising a transition metal and oxygen, such as but not limited to AlXOY, HfOX, ZrOX, TaOXor TiOX. Example 8c: The method of example 1c, wherein depositing the second dielectric comprises utilizing a plurality of processing operations where a first operation comprises utilizing a physical vapor deposition (PVD) process to deposit a material comprising a transition metal and oxygen, such as but not limited to AlXOY, HfOX, ZrOX, TaOX, TiOX, AlSiOX, HfsioX, TaSiOX, or a transition metal and nitrogen, such as, but not limited to AlN, ZrN, or HfN, wherein the PVD process deposits the second dielectric to a thickness of less than 5 nm, and further wherein the PVD process does not expose the memory device to hydrogen. Example 9c: The method of example 8c, further comprises a third atomic layer deposition or a chemical vapor deposition process to deposit a material comprising AlXOY, HfOX, ZrOX, TaOX, TiOX, AlSiOX, HfSiOX, TaSiOX, AlN, ZrN, or HfN. Example 10c: The method of example 1c, wherein forming the via electrode comprising forming an opening comprising a fourth lateral thickness that is less than a fifth lateral thickness of the memory device. Example 11c: The method of example 1c, wherein forming the via electrode further comprises: forming an opening comprising a sixth lateral thickness that is greater than a seventh lateral thickness of the memory device; and over-etching portions of the second dielectric below the first uppermost surface. Example 12c: The method of example 1c, wherein depositing the second conductive hydrogen barrier layer comprises depositing on an entire first uppermost surface, and on sidewall of a top electrode of the memory device. Example 13c: A method of fabricating a device structure, the method comprising: forming a first conductive interconnect in a first dielectric in a memory region and a second conductive interconnect in the first dielectric in a logic region; depositing an etch stop layer on the first dielectric and on the first conductive interconnect and on the second conductive interconnect; forming an electrode structure on the first conductive interconnect by a first process comprising: etching a first opening in the etch stop layer; depositing a first conductive material in the first opening; depositing a first conductive hydrogen barrier layer on the first conductive material; planarizing the first conductive hydrogen barrier layer; forming a memory device by depositing a material layer stack comprising a ferroelectric material or a paraelectric material on the electrode structure and etching the material layer stack; depositing a second dielectric comprising an amorphous, greater than 90% film density hydrogen barrier material on the memory device and on the etch stop layer; forming a via electrode on the memory device by a second process comprising: forming a second opening in the second dielectric; depositing a second conductive hydrogen barrier layer on at least a portion of an uppermost surface of the memory device in the second opening; and depositing a second conductive material on the second conductive hydrogen barrier layer; etching and removing the second dielectric from the logic region and depositing a third dielectric comprising a less than 90% film density material; forming a hanging trench over the second conductive interconnect; forming a third opening in the third dielectric and in the etch stop layer; and depositing a conductive material in the third opening and in the hanging trench to form a via structure on the second conductive interconnect and a metal line on the via structure. Example 14c: The method of example 1c, wherein depositing the first conductive hydrogen barrier layer comprises utilizing an atomic layer deposition process to blanket deposit the first conductive hydrogen barrier layer on the first conductive interconnect and on sidewalls of the etch stop layer to form a conductive hydrogen barrier layer having a lateral portion and substantially vertical portions, and wherein depositing the first conductive hydrogen barrier layer comprising using the atomic layer deposition process to deposit a material comprising TiAlN, with greater than 30 atomic percent AlN, TaN with greater than 30 atomic percent N2, TiSiN with greater than 20 atomic percent SiN, TaC, TiC, WC, WN, carbonitrides of Ta, Ti or W, TiO, Ti2O, WO3, SnO2, ITO, IGZO, ZO or METGLAS series of alloys. Example 15c: The method of example 13c, wherein etching the first opening comprises forming the first opening with a first lateral thickness that is less than a second lateral thickness of the first conductive interconnect, and wherein etching the material layer stack further comprises forming the memory device having a third lateral thickness that is greater than the first lateral thickness. Example 16c: The method of example 13c, wherein etching the material layer stack further recesses the etch stop layer below an interface between the memory device and the etch stop layer, and wherein depositing the second dielectric further comprises depositing below the interface. Example 17c: A method of fabricating a device structure, the method comprising: depositing an etch stop layer on a first conductive interconnect formed within a first dielectric in a memory region and on a second conductive interconnect formed within the first dielectric in an adjacent logic region; forming an electrode structure comprising a first conductive hydrogen barrier layer on the first conductive interconnect and a first conductive material on the first conductive hydrogen barrier layer; forming a memory device by depositing a material layer stack on the electrode structure and etching the material layer stack, wherein etching to form the memory device further comprises recessing portions of the first conductive material; depositing a second dielectric comprising an amorphous and greater than 90% film density hydrogen barrier material on the memory device; forming a via electrode comprising a second conductive hydrogen barrier layer on the memory device, wherein the second conductive hydrogen barrier layer is in contact with an uppermost surface of the memory device; etching and removing the second dielectric from the logic region and depositing a third dielectric comprising a less than 90% film density material; forming a hanging trench over the second conductive interconnect forming an opening in the third dielectric and in the etch stop layer; and depositing liner layer in the opening and in the hanging trench, the liner layer extending continuously from an uppermost surface of the second conductive interconnect to an uppermost surface of the third dielectric; depositing a fill metal in the opening and in the hanging trench on the liner layer; planarizing to remove the fill metal and the liner layer from above the third dielectric to form a via structure on the second conductive interconnect and a metal line on the via structure. Example 18c: The method of example 17c, wherein recessing portions of the first conductive material forms a first surface of the first conductive material adjacent the memory device that is below an uppermost surface of the etch stop layer, and wherein depositing the second dielectric comprises utilizing an atomic layer deposition process to deposit a material comprising a transition metal and oxygen, such as but not limited to AlXOY, HfOX, ZrOX, TaOXor TiOX, wherein depositing the second dielectric further comprises depositing below an interface between the first conductive material and the memory device. Example 1d: A device comprising: a first region comprising: a first conductive interconnect within a first dielectric in a first level; a second level above the first level, the second level comprising: an electrode structure on at least a portion of the first conductive interconnect, the electrode structure comprising: a first conductive hydrogen barrier layer; and a first conductive fill material adjacent to the first conductive hydrogen barrier layer; an insulator layer laterally surrounding the electrode structure; a memory device on least a portion of the electrode structure, the memory device comprising a ferroelectric material or a paraelectric material; a second dielectric spanning the first region, the second dielectric comprising an amorphous, greater than 90% film density hydrogen barrier material, wherein the memory device is directly adjacent to and embedded within the second dielectric; and a via electrode on at least a portion of the memory device, the via electrode comprising: a second conductive hydrogen barrier layer comprising a first lateral portion in contact with the memory device first substantially vertical portions directly adjacent to the second dielectric; and a second conductive fill material adjacent to the second conductive hydrogen barrier layer; and a third level above the second level, the third level comprising: a third dielectric comprising a first less than 90% film density material, wherein the third dielectric is on the second dielectric; and a contact electrode structure on the via electrode, the contact electrode structure comprising: a third conductive hydrogen barrier layer comprising a second lateral portion on the via electrode and second substantially vertical portions directly adjacent to the third dielectric; and a third conductive fill material adjacent to the second conductive hydrogen barrier layer; and a second region adjacent to the first region, the second region comprising: a fourth dielectric comprising a second less than 90% film density material on the insulator layer, the fourth dielectric directly adjacent to the second dielectric, a second conductive interconnect within the first dielectric in the first level; a third conductive interconnect within the third level, wherein the third dielectric extends over the fourth dielectric and wherein the third dielectric laterally surrounds the third conductive interconnect; and a via structure coupled between the second conductive interconnect and the third conductive interconnect, wherein a first portion of the via structure is adjacent to the insulator layer and a second portion of the via structure is adjacent to the fourth dielectric. Example 2d: The device of example 1d, wherein the insulator layer comprises silicon and one or more of nitrogen and carbon and the second dielectric does not comprise silicon nitride. Example 3d: The device of example 1d, wherein the contact electrode structure comprises a first lateral thickness that is greater than a second lateral thickness of the via electrode. Example 4d: The device of example 1d, wherein the first conductive hydrogen barrier layer, the second conductive hydrogen barrier layer or the third conductive hydrogen barrier layer comprise TiAlN, with greater than 30 atomic percent AlN, TaN with greater than 30 atomic percent N2, TiSiN with greater than 20 atomic percent SiN, TaC, TiC, WC, WN, carbonitrides of Ta, Ti or W, TiO, Ti2O, WO3, SnO2, ITO, IGZO, ZO or METGLAS series of alloys. Example 5d: The device of example 4d, wherein the first conductive hydrogen barrier layer, the second conductive hydrogen barrier layer and the third conductive hydrogen barrier layer comprise different materials. Example 6d: The device of example 1d, wherein the first conductive hydrogen barrier layer, the second conductive hydrogen barrier layer comprise a different material from a material of the third conductive hydrogen barrier layer. Example 7d: The device of example 1d, wherein the electrode structure is a first electrode structure, wherein the memory device is a first memory device, wherein the via electrode is a first via electrode, and wherein the device further comprises: a fourth conductive interconnect on a first plane behind the first conductive interconnect on a second plane; a second memory device above the fourth conductive interconnect; a second electrode structure coupled between the second memory device and the fourth conductive interconnect, the second electrode structure comprising the first conductive hydrogen barrier layer; a second via electrode comprising the second conductive hydrogen barrier layer and the second conductive fill material, and wherein the contact electrode structure is further on and electrically coupled with the second via electrode. Example 8d: The device of example 1d, wherein the third conductive hydrogen barrier layer extends on the second dielectric and is contact with the second conductive hydrogen barrier layer of the second via electrode, and wherein the third conductive fill material laterally extends over the second dielectric and over the second via electrode. Example 9d: The device of example 1d, wherein the via structure comprises a first vertical thickness that is substantially equal to a sum of vertical thicknesses of the electrode structure, the memory device, and the via electrode. Example 10d: A device comprising: a first region comprising: a first conductive interconnect within in a first level; a second level above the first level, the second level comprising: an electrode structure on at least a portion of the first conductive interconnect, the electrode structure comprising a first conductive hydrogen barrier layer and a first conductive fill material adjacent to the first conductive hydrogen barrier layer; an insulator layer laterally surrounding the electrode structure; a memory device on least a portion of the electrode structure, the memory device comprising a ferroelectric material or a paraelectric material; a first dielectric spanning the first region, the first dielectric comprising an amorphous, greater than 90% film density hydrogen barrier material, wherein the memory device is directly adjacent to and embedded within the first dielectric; and a via electrode on at least a portion of the memory device, the via electrode comprising: a second conductive hydrogen barrier layer comprising a first lateral portion on the memory device and first substantially vertical portions directly adjacent to the first dielectric; a first conductive fill material; and a first liner layer directly between the second conductive hydrogen barrier layer and the first conductive fill material; and a third level above the second level, the third level comprising: a second dielectric comprising a first less than 90% film density material on the first dielectric; and a contact electrode structure comprising: a second liner layer comprising a second lateral portion on the via electrode and second substantially vertical portions directly adjacent to the second dielectric; and a third conductive fill material adjacent to the second liner layer; a second region adjacent to the first region, the second region comprising: a third dielectric comprising a second less than 90% film density material directly adjacent to the first dielectric, the third dielectric on the insulator layer, and wherein the second dielectric extends laterally on the third dielectric; a second conductive interconnect within the first level; a third conductive interconnect within the third level; and a via structure within the second level, the via structure coupled between the second conductive interconnect and the third conductive interconnect, wherein the via structure and the third conductive interconnect comprise: a third liner layer adjacent to sidewalls of the third dielectric and the second dielectric, the third liner layer extending from an uppermost surface of the second conductive interconnect to an uppermost surface of the second dielectric; and a third conductive fill material continuously filling the via structure and the third conductive interconnect. Example 11d: The device of example 10d, wherein the second liner layer and the third liner layer comprise a same material. Example 12d: The device of example 10d, wherein the third conductive fill material and the third conductive fill material comprise a same material. Example 13d: A device comprising: a first region comprising: a first conductive interconnect within a first dielectric in a first level; and a second level above the first level, the second level comprising: an electrode structure on at least a portion of the first conductive interconnect, the electrode structure comprising: a first conductive hydrogen barrier layer; and a first conductive fill material adjacent to the first conductive hydrogen barrier layer; an insulator layer laterally surrounding the electrode structure; a memory device on least a portion of the electrode structure, the memory device comprising a ferroelectric material or a paraelectric material; a second dielectric comprising an amorphous greater than 90% film density hydrogen barrier material, wherein the memory device is directly adjacent to and embedded within the second dielectric; a via electrode comprising: a second conductive hydrogen barrier layer comprising a first lateral portion on the memory device and first substantially vertical portions directly adjacent to the second dielectric; a first conductive fill material; and a first liner layer directly between the second conductive hydrogen barrier layer and the first conductive fill material; a second region adjacent to the first region, the second region comprising: a second conductive interconnect within the first level; a via structure on the second conductive interconnect, the via structure within the second level; a metal line within a third level, the metal line in contact with the via structure; a third dielectric comprising a less than 90% film density material on the insulator layer, wherein the via structure and the metal line are laterally surrounded by the third dielectric, the third dielectric laterally adjacent to and in contact with the second dielectric, wherein the third dielectric laterally extends on an uppermost surface of the second dielectric; and wherein the first region further comprises: a contact electrode structure on the via electrode, the contact electrode comprising: a third conductive hydrogen barrier layer comprising a lateral portion on the via electrode and vertical portions adjacent to the third dielectric; a second conductive fill material; and a second liner layer directly between the second conductive hydrogen barrier layer and the second conductive fill material. Example 14d: The device of example 13d, the metal line has a lowermost surface that is at or below an uppermost surface of the via electrode. Example 1e: A method of fabricating a device structure, the method comprising: forming a first conductive interconnect in a first dielectric in a memory region and a second conductive interconnect in the first dielectric in a logic region; depositing an etch stop layer on the first dielectric and on the first conductive interconnect and on the second conductive interconnect; forming an electrode structure on the first conductive interconnect by a first process comprising: etching a first opening in the etch stop layer; depositing a first conductive hydrogen barrier layer in the first opening; and depositing a first conductive material on the first conductive hydrogen barrier layer; forming a memory device by depositing a material layer stack comprising a ferroelectric material or a paraelectric material on the electrode structure and etching the material layer stack; depositing a second dielectric comprising an amorphous, greater than 90% film density hydrogen barrier material on the memory device and on the etch stop layer; forming a via electrode on the memory device by a second process comprising: forming a second opening in the second dielectric; depositing a second conductive hydrogen barrier layer on at least a portion of a first uppermost surface of the memory device in the second opening; and depositing a second conductive material on the second conductive hydrogen barrier layer; etching and removing the second dielectric from the logic region and depositing a third dielectric comprising a less than 90% film density material; etching the third dielectric to form a via opening and exposing the second conductive interconnect; filling the via opening with a first one or more conductive materials; planarizing to form a via structure; depositing a fourth dielectric on the via electrode, on the second dielectric, on the third dielectric and on the via structure; forming a contact electrode by a third process, comprising: forming a third opening in the fourth dielectric and exposing the via electrode; depositing a third conductive hydrogen barrier layer on the via electrode in the third opening; depositing a second one or more conductive materials on the third conductive hydrogen barrier layer; and planarizing the second one or more conductive materials and the third conductive hydrogen barrier layer; forming a trench opening in the fourth dielectric and exposing the via structure; and depositing a third one or more conductive materials in the trench opening on the via structure to form a metal line. Example 2e: The method of example 1e, wherein depositing the first conductive hydrogen barrier layer comprises utilizing an atomic layer deposition process to blanket deposit the first conductive hydrogen barrier layer on the first conductive interconnect and on sidewalls of the etch stop layer to form a conductive hydrogen barrier layer having a lateral portion and substantially vertical portions connected to the lateral portion, wherein depositing the first conductive hydrogen barrier layer comprising using an atomic layer deposition process to deposit a material comprising TiAlN, with greater than 30 atomic percent AlN, TaN with greater than 30 atomic percent N2, TiSiN with greater than 20 atomic percent SiN, TaC, TiC, WC, WN, carbonitrides of Ta, Ti or W, TiO, Ti2O, WO3, SnO2, ITO, IGZO, ZO or METGLAS series of alloys. Example 3e: The method of example 1e, wherein depositing the third dielectric further comprises depositing the third dielectric on a second uppermost surface of the second dielectric and performing a first planarization process to remove third dielectric from the second uppermost surface, wherein the first planarization process forms the second uppermost surface and a third uppermost surface of the third dielectric that are substantially co-planar. Example 4e: The method of example 1e, wherein forming the first electrode structure further comprises performing a second planarization process to form the first conductive material comprising a substantially planar fourth uppermost surface, wherein the planar fourth uppermost surface is substantially co-planar with a fifth uppermost surface of the etch stop layer. Example 5e: The method of example 1e, wherein the via electrode is a first via electrode, the memory device is a first memory device, wherein etching the material layer stack further comprises forming a second memory device on a first plane behind the first memory device on a second plane, and wherein the third process further comprises forming a second via electrode on the second memory device, wherein forming the third opening in the fourth dielectric further comprises forming a fifth opening and exposing the second via electrode, and wherein depositing the third conductive hydrogen barrier layer further comprises depositing on the second via electrode. Example 6e: The method of example 5e, wherein depositing the third one or more conductive materials further comprises depositing a liner layer and a conductive fill material on the liner layer. Example 7e: The method of example 6e, wherein after depositing a third one or more conductive materials in the trench opening, a third planarization process is performed wherein the third planarization process forms a substantially planar sixth uppermost surface of the contact electrode that is co-planar with a seventh uppermost surface of the metal line. Example 8e: The method of example 7e, wherein forming the via electrode further comprises: forming the second opening comprising a fourth lateral thickness that is greater than a fifth lateral thickness of the memory device; and over-etching portions of the second dielectric below the first uppermost surface. Example 9e: A method of fabricating a device structure, the method comprising: forming a first conductive interconnect in a first dielectric in a memory region and a second conductive interconnect in the first dielectric in a logic region; depositing an etch stop layer on the first dielectric and on the first conductive interconnect and on the second conductive interconnect; forming an electrode structure on the first conductive interconnect by a first process comprising: etching a first opening in the etch stop layer; depositing a first conductive hydrogen barrier layer in the first opening; and depositing a first conductive material on the first conductive hydrogen barrier layer; forming a memory device by depositing a material layer stack comprising a ferroelectric material or a paraelectric material on the electrode structure and etching the material layer stack; depositing a second dielectric comprising an amorphous greater than 90% film density hydrogen barrier material on the memory device and on the etch stop layer; forming a via electrode on the memory device by a second process comprising: forming a second opening in the second dielectric; depositing a second conductive hydrogen barrier layer on at least a portion of an uppermost surface of the memory device in the second opening; depositing a conductive material on the second conductive hydrogen barrier layer; etching and removing the second dielectric from the logic region and depositing a third dielectric comprising a less than 90% film density material; performing a planarization of the third dielectric, wherein the planarization forms a first portion of the third dielectric above the second dielectric and forms a second portion of the third dielectric directly laterally adjacent to the second dielectric; etching the third dielectric to form a trench opening above the via electrode; forming a contact electrode in the trench opening by depositing a third conductive hydrogen barrier layer on the via electrode in the trench opening and on the third dielectric, by depositing a second conductive material on the third conductive hydrogen barrier layer, and by planarizing to remove the second conductive material and the third conductive hydrogen barrier layer from above the third dielectric; etching the third dielectric to form a hanging trench; masking a portion of the hanging trench to form a via opening in the third dielectric below the hanging trench; and forming a via structure by depositing one or more conductive materials in the via opening and in the hanging trench. Example 10e: The method of example 9e, wherein performing the planarization comprises forming a vertical thickness of the third dielectric above the second dielectric that is at least equal to a vertical thickness of the contact electrode. Example 11e: The method of example 9e, wherein etching the third dielectric to form the hanging trench further comprises etching to a level that is substantially co-planar with an uppermost surface of the via electrode. Example 12e: The method of example 9e, wherein etching the material layer stack further recesses the etch stop layer to a level below an interface between the memory device and the etch stop layer, and wherein depositing the second dielectric further comprises depositing below the interface. Example 13e: The method of example 9e wherein depositing a liner layer comprises simultaneously depositing a liner layer in the via opening, in the hanging trench and in the trench opening and on uppermost surface of the fourth dielectric. Example 14e: The method of example 9e, wherein the via opening in the third dielectric comprises a first lateral width that is between 25-75% of a second lateral width of the hanging trench. Example 1f: A device comprising: a first region comprising: a first conductive interconnect within a first dielectric in a first level; a second level above the first level, the second level comprising: a first electrode structure on at least a portion of the first conductive interconnect, the first electrode structure comprising: a first conductive hydrogen barrier layer; and a first conductive fill material adjacent to the first conductive hydrogen barrier layer; an insulator layer laterally surrounding the first electrode structure; and a memory device on least a portion of the first electrode structure, the memory device comprising a ferroelectric material or a paraelectric material; a second dielectric spanning the first region and on the insulator layer, the second dielectric comprising an amorphous, greater than 90% film density hydrogen barrier material, wherein the memory device is directly adjacent to and embedded within the second dielectric; a third dielectric comprising a less than 90% film density material on the second dielectric, the third dielectric within a third level above the second level; a second electrode structure coupled with the memory device, the second electrode structure comprising: a via electrode on at least a portion of the memory device and adjacent to the second dielectric; and a trench electrode on the via electrode, the trench electrode adjacent to the third dielectric; a second conductive hydrogen barrier layer comprising: a lateral portion on the memory device; first substantially vertical portions directly adjacent to the second dielectric; and second substantially vertical portions directly adjacent to the third dielectric; and a second conductive fill material that extends continuously from the lateral portion to a first uppermost surface of the third dielectric; and a second region adjacent to the first region, the second region comprising: a fourth dielectric comprising dielectric comprising a first less than 90% film density material directly adjacent to the second dielectric and below the third dielectric; a second conductive interconnect within the first level; a third conductive interconnect within the third level, wherein the third dielectric extends over the fourth dielectric and wherein the third dielectric laterally surrounds the third conductive interconnect; and a via structure coupled between the second conductive interconnect and the third conductive interconnect, wherein at least a first portion of the via structure is adjacent to the insulator layer. Example 2f: The device of example 1f, wherein the trench electrode has a first width and the via electrode has a second width, where the first width is greater than the second width. Example 3f: The device of example 2f, wherein the second conductive hydrogen barrier layer further extends on a second uppermost surface of the second dielectric. Example 4f: The device of example 1f, wherein the electrode structure is a first electrode structure, wherein the memory device is a first memory device, wherein the via electrode is a first via electrode, and wherein the device further comprises: a fourth conductive interconnect on a first plane behind the first conductive interconnect on a second plane; a second memory device above the fourth conductive interconnect; a third electrode structure coupled between the second memory device and the fourth conductive interconnect, the third electrode structure comprising the first conductive hydrogen barrier layer; a second via electrode comprising the second conductive hydrogen barrier layer and the second conductive fill material, and wherein the trench electrode is further on and electrically coupled with the second via electrode. Example 5f: The device of example 4f, wherein the second conductive hydrogen barrier layer extends from the first via electrode to the second via electrode on the second dielectric, and wherein the second conductive fill material laterally extends over the second dielectric and over the second via electrode. Example 6f: The device of example 4f, wherein the via structure comprises a first vertical thickness that is substantially equal to a sum of vertical thicknesses of the electrode structure, the memory device, and the via electrode. Example 7f: The device of example 4f, wherein the third conductive interconnect comprises a second vertical thickness that is substantially equal to a fourth vertical thickness of the trench electrode. Example 8f: The device of example 4f, wherein the electrode structure comprises a first lateral thickness; the memory device further comprising a second lateral thickness, wherein the first lateral thickness is less than the second lateral thickness. Example 9f: A device comprising: a first region comprising: a first conductive interconnect within a first dielectric in a first level; a second level above the first level, the second level comprising: a first electrode structure on the first conductive interconnect, the first electrode structure comprising: a first conductive fill material; a first conductive hydrogen barrier layer on the first conductive fill material; an insulator layer laterally surrounding the first electrode structure; a memory device on least a portion of the first electrode structure, the memory device comprising a ferroelectric material or a paraelectric material; and a second dielectric spanning the first region and on the insulator layer, the second dielectric comprising an amorphous, greater than 90% film density hydrogen barrier material, wherein the memory device is directly adjacent to and embedded within the second dielectric; a third dielectric comprising a less than 90% film density material on the second dielectric, the third dielectric within a third level above the second level; a second electrode structure coupled with the memory device, the second electrode structure comprising: a via electrode on at least a portion of the memory device and adjacent to the second dielectric; a trench electrode on the via electrode, the trench electrode adjacent to the third dielectric; a second conductive hydrogen barrier layer comprising: a lateral portion on the memory device; first substantially vertical portions directly adjacent to the second dielectric; and second substantially vertical portions directly adjacent to the third dielectric; a second conductive fill material that extends continuously from above the lateral portion to an uppermost surface of the third dielectric; and a liner layer between the second conductive hydrogen barrier layer and the second conductive fill material; and a second region adjacent to the first region, the second region comprising: a fourth dielectric comprising dielectric comprising a first less than 90% film density material directly adjacent to the second dielectric and below the third dielectric; a second conductive interconnect within the first level; a third conductive interconnect within the third level, wherein the third dielectric extends over the fourth dielectric and wherein the third dielectric laterally surrounds the third conductive interconnect; and a via structure coupled between the second conductive interconnect and the third conductive interconnect, wherein at least a first portion of the via structure is adjacent to the insulator layer. Example 10f: The device of example 9f, wherein the memory device is in contact with the first conductive hydrogen barrier layer and the first conductive fill material, and wherein the memory device covers the first electrode structure. Example 11f: A device comprising: a first region comprising: a first conductive interconnect within a first dielectric in a first level; a second level above the first level, the second level comprising: a first electrode structure on at least a portion of the first conductive interconnect, the first electrode structure comprising: a first conductive hydrogen barrier layer; and a first conductive fill material adjacent to the first conductive hydrogen barrier layer; an insulator layer laterally surrounding the first electrode structure; a memory device on least a portion of the first electrode structure, the memory device comprising a ferroelectric material or a paraelectric material; a second dielectric spanning the first region, the second dielectric comprising an amorphous, greater than 90% film density hydrogen barrier material, wherein the memory device is directly adjacent to and embedded within the second dielectric; a second region adjacent to the first region, the second region comprising: a second conductive interconnect within the first level; a via structure on the second conductive interconnect, the via structure within the second level; a metal line within a third level, the metal line in contact with the via structure; a third dielectric comprising a less than 90% film density material on the insulator layer, the third dielectric laterally adjacent to and in contact with the second dielectric, and wherein the via structure and the metal line are laterally surrounded by the third dielectric, wherein the third dielectric laterally extends on an uppermost surface of the second dielectric; and wherein the first region further comprises: a second electrode structure coupled with the memory device, the second electrode structure comprising: a via electrode on at least a portion of the memory device and adjacent to the second dielectric, the via electrode comprising: a second conductive hydrogen barrier layer comprising a first lateral portion on the memory device and first substantially vertical portions directly adjacent to the second dielectric; and a second conductive fill material on the second conductive hydrogen barrier layer, a trench electrode on the via electrode, the trench electrode adjacent to the third dielectric, the trench electrode comprising: the second conductive hydrogen barrier layer comprising a second lateral portion on the second dielectric; and second substantially vertical portions directly adjacent to the third dielectric, and wherein the second conductive fill material is directly adjacent to the second conductive hydrogen barrier layer and wherein the second conductive fill material extends continuously from a level of a lowermost surface to a level of an uppermost surface of the third dielectric. Example 12f: The device of example 11f wherein the metal line has a lowermost surface that is at or below an uppermost surface of the via electrode. Example 1g: A method of fabricating a device structure, the method comprising: forming a first conductive interconnect in a first dielectric in a memory region and a second conductive interconnect in the first dielectric in a logic region; depositing an etch stop layer on the first dielectric and on the first conductive interconnect and on the second conductive interconnect; forming a first electrode structure on the first conductive interconnect by a first process comprising: etching a first opening in the etch stop layer; depositing a first conductive hydrogen barrier layer in the first opening; and depositing a conductive material on the first conductive hydrogen barrier layer; forming a memory device by depositing a material layer stack comprising a ferroelectric material or a paraelectric material on the first electrode structure and etching the material layer stack; depositing a second dielectric comprising an amorphous greater than 90% film density hydrogen barrier material on the memory device and on the etch stop layer; etching and removing the second dielectric from the logic region and depositing a third dielectric comprising a first less than 90% film density material; etching the third dielectric to form a first via opening and exposing the second conductive interconnect; filling the first via opening with a first one or more conductive materials to form a via structure; depositing a fourth dielectric comprising a second less than 90% film density material on the third dielectric and on the via structure; forming a trench opening in the fourth dielectric and exposing the via structure; depositing a second one or more conductive materials in the trench opening on the via structure to form a metal line; forming a second electrode structure on the memory device by a second process comprising: forming a hanging trench opening in the fourth dielectric and exposing the third dielectric; forming a mask on a portion of the hanging trench, the mask providing a second opening that exposes a portion of the second dielectric; etching the second dielectric through the second opening to form a second via opening, the second via opening exposing the memory device; depositing a second conductive hydrogen barrier layer on a first uppermost surface of the memory device, in the second via opening, and in the hanging trench; and depositing a third one or more conductive materials on the second conductive hydrogen barrier layer in the second via opening to form a via electrode; and planarizing to form a contact electrode in the hanging trench, on the via electrode. Example 2g: The method of example 1g, wherein the via electrode is a first via electrode, the memory device is a first memory device, wherein etching the material layer stack further comprises forming a second memory device on a first plane behind the first memory device on a second plane, and wherein the hanging trench is a first hanging trench, wherein the second process further comprises: forming a second hanging trench above the second memory device; forming the mask in the second hanging trench, the mask providing a third opening that exposes a portion of the second dielectric; etching the second dielectric through the third opening to form a third via opening, the third via opening exposing the second memory device; depositing the second conductive hydrogen barrier layer on the second memory device in the third via opening and in the second hanging trench; and wherein the planarizing forms a second via electrode in the third via opening, and further forms the contact electrode in the second hanging trench on the second via electrode. Example 3g: The method of example 1g, wherein after depositing a third one or more conductive materials in the hanging trench opening and in the via opening, a third planarization process is performed wherein the third planarization process forms a substantially planar sixth uppermost surface of the trench electrode that is co-planar with a seventh uppermost surface of the metal line. Example 4g: The method of example 1g, herein the second via opening comprises a first lateral thickness that is less than a second lateral thickness of the memory device, and wherein the hanging trench opening comprises a third lateral thickness that is greater than the first lateral thickness. Example 5g: The method of example 1g, wherein forming the via electrode further comprises: forming the second opening comprising a fourth lateral thickness that is greater than a fifth lateral thickness of the memory device; and over-etching portions of the second dielectric below the first uppermost surface. Example 6g: A method of fabricating a device structure, the method comprising: forming a first conductive interconnect in a first dielectric in a memory region and a second conductive interconnect in the first dielectric in a logic region; depositing an etch stop layer on the first dielectric and on the first conductive interconnect and on the second conductive interconnect; forming a first electrode structure on the first conductive interconnect by a first process comprising: etching a first opening in the etch stop layer; depositing a first conductive material on the first conductive interconnect; planarizing and recessing the first conductive material; depositing a first conductive hydrogen barrier layer in the first opening on the first conductive material; and planarizing the first conductive hydrogen barrier layer to form a conductive hydrogen barrier; forming a memory device by depositing a material layer stack comprising a ferroelectric material or a paraelectric material on the first electrode structure and etching the material layer stack; depositing a second dielectric comprising an amorphous greater than 90% film density hydrogen barrier material on the memory device and on the etch stop layer; etching and removing the second dielectric from the logic region and depositing a third dielectric comprising a first less than 90% film density material; etching the third dielectric to form a first via opening and exposing the second conductive interconnect; filling the first via opening with a first one or more conductive materials to form a via structure; depositing a fourth dielectric comprising a second less than 90% film density material on the third dielectric and on the via structure; forming a trench opening in the fourth dielectric and exposing the via structure; depositing a second one or more conductive materials in the trench opening on the via structure to form a metal line; forming a second electrode structure on the memory device by a second process comprising: forming a hanging trench in the fourth dielectric and exposing the third dielectric; forming a mask on a portion of the hanging trench, the mask providing a second opening that exposes a portion of the second dielectric; etching the second dielectric through the second opening to form a second via opening, the second via opening exposing the memory device; depositing a second conductive hydrogen barrier layer on the memory device in the second via opening and in the hanging trench; depositing a third one or more conductive materials on the second conductive hydrogen barrier layer; and planarizing to form a via electrode in the second via opening and a contact electrode in the hanging trench, on the via electrode. Example 7g: The method of example 6g, wherein planarizing the first conductive hydrogen barrier layer to form a conductive hydrogen barrier causes dishing of an uppermost surface of the conductive hydrogen barrier. Example 8g: The method of example 7g, wherein depositing the material layer stack comprises forming a lower most layer having a contour that matches the uppermost surface of the conductive hydrogen barrier. Example 9g: The method of example 6g, wherein the first electrode structure comprises a first lateral thickness that is less than a second lateral thickness of the first electrode structure, and wherein etching the material layer stack recesses a portion of the etch stop layer to a level below an interface between the memory device and second conductive hydrogen barrier layer. Example 10g: A method of fabricating a device structure, the method comprising: forming a first conductive interconnect in a first dielectric in a memory region and a second conductive interconnect in the first dielectric in a logic region; depositing an etch stop layer on the first dielectric and on the first conductive interconnect and on the second conductive interconnect; forming an electrode structure on the first conductive interconnect by a first process comprising: etching a first opening in the etch stop layer; depositing a first conductive hydrogen barrier layer in the first opening; and depositing a first conductive material on the first conductive hydrogen barrier layer; forming a memory device by depositing a material layer stack comprising a ferroelectric material or a paraelectric material on the electrode structure and etching the material layer stack; depositing a second dielectric comprising an amorphous greater than 90% film density hydrogen barrier material on the memory device and on the etch stop layer; etching and removing the second dielectric from the logic region and depositing a third dielectric comprising a less than 90% film density material; performing a planarization of the third dielectric, wherein the planarization forms a first portion of the third dielectric directly laterally adjacent to the second dielectric and a second portion of the third dielectric above the second dielectric; etching the third dielectric to form a first hanging trench above the second conductive interconnect; forming a first mask within a portion of the first hanging trench; and etching the third dielectric through an opening in the first mask to form a first via opening; depositing a liner layer in the first via opening, in the first hanging trench and on an uppermost surface of the third dielectric; depositing a second conductive material on the liner layer in the first via opening, and in the first hanging trench; planarizing to remove the second conductive material and the liner layer from above the third dielectric and forming a via structure in the first via opening and a metal line in the first hanging trench; etching the third dielectric and forming a second hanging trench opening in the third dielectric and exposing the second dielectric; forming a second mask within a portion of the second hanging trench; etching the second dielectric through an opening in the second mask to form a second via opening; depositing a second conductive hydrogen barrier layer on at least a portion of an uppermost surface of the memory device in the second via opening and in the second hanging trench; depositing one or more layers of conductive material on the second conductive hydrogen barrier layer; and planarizing to form a via electrode in the second via opening and a contact electrode in the second hanging trench, on the via electrode. Example 11g: The method of example 10g, wherein etching the third dielectric to form the first hanging trench further comprises etching to a level that is substantially co-planar with an uppermost surface of the second dielectric. Example 1h: A device comprising a first region, the first region comprising: a first conductive interconnect within a first dielectric in a first level; a second level above the first level, the second level comprising: an electrode structure on at least a portion of the first conductive interconnect, the first electrode structure comprising: a first conductive hydrogen barrier layer; and a first conductive material adjacent to the first conductive hydrogen barrier layer; an insulator layer laterally surrounding the electrode structure; a memory device on least a portion of the first electrode structure, the memory device comprising a ferroelectric material or a paraelectric material; a second dielectric spanning the first region, the second dielectric comprising an amorphous, greater than 90% film density hydrogen barrier material, wherein the memory device is directly adjacent to and embedded within the second dielectric; a third dielectric comprising a first less than 90% film density material on the second dielectric, the third dielectric within a third level above the second level; a via electrode structure on at least a portion of the memory device, the second electrode structure comprising: a second conductive hydrogen barrier layer comprising a lateral portion on the memory device and substantially vertical portions at opposite ends of the lateral portion, wherein the lateral portion and the substantially vertical portions are configured as a cup; and a second conductive material in contact with the second conductive hydrogen barrier layer; and wherein the via electrode structure further comprises a first portion adjacent to the second dielectric and a second portion adjacent to the third dielectric; and a second region adjacent to the first region, the second region comprising: a fourth dielectric comprising dielectric comprising a second less than 90% film density material directly adjacent to the second dielectric and below the third dielectric; a second conductive interconnect within the first level; a third conductive interconnect within the third level, wherein the third dielectric extends over the fourth dielectric and wherein the third dielectric laterally surrounds the third conductive interconnect; and a via structure coupled between the second conductive interconnect and the third conductive interconnect, wherein at least a first portion of the via structure is adjacent to the insulator layer. Example 2h: The device of example 1h, wherein sidewalls of the second electrode structure are tapered, wherein the first portion is above the second portion, and wherein the first portion is wider than the second portion. Example 3h: The device of example 1h, wherein the first portion and the second portion have a same lateral thickness. Example 4h: The device of example 1h, wherein sidewalls of the second electrode structure are tapered, wherein the first portion is above the second portion, and wherein the first portion is wider than the second portion. Example 5h: The device of example 1h wherein the second conductive material further comprises: a first conductive fill material; and a first liner layer between the first conductive fill material and the second conductive hydrogen barrier layer. Example 6h: The device of example 1h wherein the electrode structure is a first electrode structure, the memory device is a first memory device and the device structure further comprises: a second memory device laterally separated from the first memory device; a third conductive interconnect below the second memory device; a second electrode structure directly between the third conductive interconnect and the second memory device; a second via electrode structure on the second memory device; and a bridge structure coupled between and in contact with the first via electrode structure and second via electrode structure, the bridge structure comprising a third conductive material, wherein an uppermost surface of the third conductive material is co-planar with an uppermost surface of the second conductive material. Example 7h: The device of example 6h, wherein the bridge structure further comprises a third conductive hydrogen barrier layer between the third conductive material and the second conductive hydrogen barrier layer. Example 8h: The device of example 7h wherein the third conductive material further comprises: a second conductive fill material; and a second liner layer between the second conductive fill material and the third conductive hydrogen barrier layer. Example 9h: The device of example 8h wherein the second via electrode comprises the second conductive hydrogen barrier layer, wherein the third conductive hydrogen barrier layer extends on the second dielectric and is contact with the second conductive hydrogen barrier layer of the second via electrode. Example 10h: The device of example 9h wherein the first conductive hydrogen barrier layer comprises one of TiAlN, with greater than 30 atomic percent AlN, TaN with greater than 30 atomic percent N2, TiSiN with greater than 20 atomic percent SiN, TaC, TiC, WC, WN, carbonitrides of Ta, Ti or W, TiO, Ti2O, WO3, SnO2, ITO, IGZO, ZO or METGLAS series of alloys, wherein the second conductive hydrogen barrier layer comprises one of TiAlN, with greater than 30 atomic percent AlN, TaN with greater than 30 atomic percent N2, TiSiN with greater than 20 atomic percent SiN, TaC, TiC, WC, WN, carbonitrides of Ta, Ti or W, TiO, Ti2O, WO3, SnO2, ITO, IGZO, ZO or METGLAS series of alloys and wherein the third conductive hydrogen barrier layer comprises one of TiAlN, with greater than 30 atomic percent AlN, TaN with greater than 30 atomic percent N2, TiSiN with greater than 20 atomic percent SiN, TaC, TiC, WC, WN, carbonitrides of Ta, Ti or W, TiO, Ti2O, WO3, SnO2, ITO, IGZO, ZO or METGLAS series of alloys. Example 11h: The device of example 6h, wherein the first conductive hydrogen barrier layer and the second conductive hydrogen barrier layer comprise different materials. Example 12h: A device comprising: a first region comprising: a plurality of first conductive interconnects within a first level; and a second level above the first level, the second level comprising: a plurality of memory devices above a respective first conductive interconnect in the plurality of first conductive interconnects; an electrode structure coupled between a respective ferroelectric memory device in the plurality of ferroelectric memory devices and the respective first conductive interconnect in the plurality of first conductive interconnects, the electrode structure comprising: a first conductive hydrogen barrier layer; and a first conductive material adjacent to the first conductive hydrogen barrier layer; a second dielectric spanning the first region, the second dielectric comprising an amorphous, greater than 90% film density hydrogen barrier material, wherein the plurality of memory devices are directly adjacent to and embedded within the second dielectric; a third dielectric comprising a first less than 90% film density material on the second dielectric, the third dielectric within a third level above the second level; a plurality of via electrode structures, wherein a respective via electrode of the plurality of via electrode structures is on at least a portion of the individual ones of the plurality of memory devices, the respective via electrode structure comprising:a second conductive hydrogen barrier layer comprising a lateral portion on individual ones of the plurality of memory devices memory device and substantially vertical portions at opposite ends of the lateral portion, wherein the lateral portion and the substantially vertical portions are configured as a cup; and a second conductive material in contact with the second conductive hydrogen barrier layer; wherein the respective via electrode structure further comprises a first portion adjacent to the second dielectric and a second portion adjacent to the third dielectric; a bridge structure coupled between and in contact with adjacent ones of the respective via electrode structures and second via electrode, the bridge structure comprising: a third conductive hydrogen barrier; and a third conductive material on the third conductive hydrogen barrier layer, wherein an uppermost surface of the third conductive material is co-planar with an uppermost surface of the second conductive material; and a second region adjacent to the first region, the second region comprising: a fourth dielectric comprising dielectric comprising a second less than 90% film density material directly adjacent to the second dielectric and below the third dielectric; a second conductive interconnect within the first level; a third conductive interconnect within the third level, wherein the third dielectric extends over the fourth dielectric and wherein the third dielectric laterally surrounds the third conductive interconnect; and a via structure coupled between the second conductive interconnect and the third conductive interconnect, wherein at least a first portion of the via structure is adjacent to the insulator layer. Example 13h: The device of example 12h, wherein a lowermost surface of the bridge structure is on an uppermost surface of the second dielectric. Example 14h: The device of example 12h, a lowermost surface of the bridge structure is below a level of an uppermost surface of the second dielectric. Example 15h: The device of example 12h, wherein the respective via electrode has a lateral thickness that is greater than a lateral thickness of the individual ones of the plurality of memory devices. Example 16h: A system comprising: a processor; a communication interface communicatively coupled to the processor; and a memory coupled to the processor, wherein the memory comprises bit-cells, wherein one of the bit-cell includes a first region comprising a first conductive interconnect within a first dielectric in a first level; a second level above the first level, the second level comprising: an electrode structure on at least a portion of the first conductive interconnect, the first electrode structure comprising: a first conductive hydrogen barrier layer; and a first conductive material adjacent to the first conductive hydrogen barrier layer; an insulator layer laterally surrounding the electrode structure; a memory device on least a portion of the first electrode structure, the memory device comprising a ferroelectric material or a paraelectric material; a second dielectric spanning the first region, the second dielectric comprising an amorphous, greater than 90% film density hydrogen barrier material, wherein the memory device is directly adjacent to and embedded within the second dielectric; a third dielectric comprising a first less than 90% film density material on the second dielectric, the third dielectric within a third level above the second level; a via electrode structure on at least a portion of the memory device, the second electrode structure comprising: a second conductive hydrogen barrier layer comprising a lateral portion on the memory device and substantially vertical portions at opposite ends of the lateral portion, wherein the lateral portion and the substantially vertical portions are configured as a cup; and a second conductive material in contact with the second conductive hydrogen barrier layer; and wherein the via electrode structure further comprises a first portion adjacent to the second dielectric and a second portion adjacent to the third dielectric; and a second region adjacent to the first region, the second region comprising: a fourth dielectric comprising dielectric comprising a second less than 90% film density material directly adjacent to the second dielectric and below the third dielectric; a second conductive interconnect within the first level; a third conductive interconnect within the third level, wherein the third dielectric extends over the fourth dielectric and wherein the third dielectric laterally surrounds the third conductive interconnect; and a via structure coupled between the second conductive interconnect and the third conductive interconnect, wherein at least a first portion of the via structure is adjacent to the insulator layer. | 279,536 |
11862518 | DETAILED DESCRIPTION Some IC devices, e.g., inductors or transformers, or packaging for IC devices, include relatively thick metallization structures, whose thicknesses are designed, e.g., to reduce parasitic resistance. However, metallization structures formed by plating are sometimes limited by the thickness of the masking layer, e.g., photoresist, used to define them. For example, photoresist can have a limited thickness in commercially available formulations, and other limits on photoresist thickness relate to the ability to define vertical walls through irradiation for the desired dimensional control. When a metallization structure is formed by plating in an opening formed through a photoresist layer, plating to a thickness greater than the photoresist layer can lead to what is sometimes referred to as “breadloafing,” which refers to a phenomenon in which the metal that is electroplated in excess of filling the opening grows or electrodeposits laterally as well as vertically, which then deviates from the desired lateral geometry and can cause various defects, including electrical shorts and nonplanarity. For these reasons, electroplated metallization structures are generally electroplated to a thickness comparable to or less than the photoresist used to define the electroplated areas. In the following, with respect toFIG.1A-1F, an example method of forming electroplated metallization structures is described, in which, to prevent formation of a bread loaf structure, the thickness of the metallization structures is kept at or below that of the photoresist. Subsequently, various methods according to embodiments are described, which can advantageously overcome some of the problems associated with plating metallization structures that are thicker than masking layers used to define them. In various examples and embodiments described herein, plating may be performed electrolytically (e.g., electroplating) or electrolessly (e.g., chemical plating), depending on various factors, including what the deposit will be used for, configuration of the part, materials compatibility and cost of processing. FIGS.1A-1Fillustrate intermediate structures100A-100F, respectively, at various stages of fabrication of an electroplated metallization structure on a substrate104, according to some example processes. Referring to the intermediate structure100A ofFIG.1A, prior to plating, an adhesion layer and/or an electrically conductive barrier layer108is formed on the substrate104, followed by formation of a seed layer112. Referring toFIG.1B, after formation of the seed layer112, with or without underlying adhesion and/or conductive barrier layer108, a masking layer116is formed on the substrate104to define a pattern which exposes areas in which the metal feature124is subsequently electroplated (FIG.1C). The masking layer may be an organic resist material, particularly photosensitive resist. Referring toFIG.1C, after exposing and developing the masking layer116to form the pattern including the opening120, a metallization feature124having the width W1is formed in the opening120by plating on the exposed seed layer112(illustrated). The metallization layer124may include a suitable material, e.g., gold and/or copper, depending on the technology. Still referring toFIG.1C, in the illustrated example, the metal feature124has a target thickness t1that is about the same or thinner than the thickness tPRof the masking layer116. Under this circumstance, because the metal feature124is electroplated selectively in the opening120, so long as the t1is about the same or smaller than the tPR, the metal feature124is contained substantially in the opening120vertically and laterally. Having the t1about equal or less than the tPRmay be advantageous, e.g., for reasons described below with respect toFIG.1D, including preventing electrical shorts. In the intermediate structure100D illustrated with respect toFIG.1D, unlike the metal feature124of the intermediate structure100C illustrated with respect toFIG.1C, the metal feature126is overplated to a thickness t2exceeding tPR. For example, the metal feature126may be overplated to t2of about 16 microns, while a commercially available photoresist may have a thickness of about 10 microns. When this occurs, as illustrated, a portion of the overplated metal feature126above the surface of the masking layer116grows or electrodeposits laterally beyond the width W1defined by the opening120. Such phenomenon is sometimes referred to as “bread loafing.” While the overplated metal feature124may provide a thickness t2greater than the tPR, the resulting bread loaf structure can cause various problems. For example, the lateral dimensions of the overplated feature126may be difficult to control accurately. In addition, bread loaf structure may cause portions of the masking layer116under the laterally overgrown overhang region to be incompletely removed. Thus, the bread loafing ofFIG.1Dis typically avoided in the art. Referring toFIG.1E, after plating the metallization layer124having the width W1to the thickness t1in the illustrated intermediate structure100C ofFIG.1C(or to the overplated thickness t2in the intermediate structure100D ofFIG.1D), the masking layer116is removed or stripped using a suitable wet and/or dry process. Referring toFIG.1F, after removing the masking layer116, e.g., by dissolving or ashing, the exposed seed layer112and any adhesion and/or conductive barrier layer108are removed from locations previously covered by the masking layer116(FIG.1C). The seed layer112, adhesion layer and/or the conductive barrier layer108may be removed by etching, e.g., by wet etching or dry etching, which may cause some of the material of the metal feature124to be also be removed for some etch chemistries, thereby forming the resulting final metal feature128. Because the thicknesses of the seed layer112, adhesion layer and/or the conductive barrier layer108are relatively small compared to the thickness of the metal feature124(FIG.1E), the final metal feature128has a thickness t1′ that may be substantially the same as the thickness t1of the metal feature124(FIG.1E) prior to the removal of the exposed seed layer112and/or the conductive barrier layer108(FIG.1F). For example, even if the etch chemistry is relatively non-selective and isotropic, the t1′ may approximately be the t1less the amount of the metallization layer124that is removed during the removal of the exposed seed layer112and/or the conductive barrier layer108. Still referring toFIG.1F, because the metal feature124(FIG.1E) was formed within the opening120having the width W1defined by the masking layer116(FIG.1B), upon removal of the masking layer116, the metal feature124(FIG.1E) has substantially the same width W1as the opening120. In addition, because any amount of the metal feature124removed during the removal of the seed layer112, adhesion layer and/or the conductive barrier layer108is relatively small, the final metal feature128has substantially the same width W1′ as the W1of the metal feature124prior to the removal of the seed layer112, adhesion layer and/or the conductive barrier layer108. Thus, in the example illustrated with respect toFIGS.1A-1F, the width W1of the opening120formed by the masking layers116has substantially the same width as the target width W1′ of the final metal feature128. Based on the foregoing, ways to achieve higher t1include overplating or increasing the tPR. However, as described above with respect toFIG.1D, when overplated to have a thickness t2substantially exceeding the thickness of the masking layer tPR, the resulting metal feature126having the bread loaf structure may lead to undesirable defects, e.g., electrical shorting of the metallization layers126and/or difficulty in removal of the masking layers. In addition, increasing the tPRto avoid a bread loaf structure also not be practical or desirable under manufacturing constraints, for reasons described below. When the target thickness of the metal feature124illustrated inFIG.1Cneeds to be substantially thicker than the tPR, e.g., to achieve lower electrical resistance, the thickness of the metal feature124that is contained substantially in the opening120vertically and laterally as described above with respect toFIG.1Cmay not be sufficient. However, according to examples and embodiments disclosed herein including the example process described above with respect toFIGS.1A-1F, the masking layer116may be designed, e.g., by a manufacturer and/or for the application process, to be used within a specified range of thicknesses tPRfor optimized manufacturability. The specified range of thicknesses may depend on factors such as, e.g., spinning speed during spin coating, depth of focus of light used for patterning, removal of solvent and mechanical stability, among various other factors. When used outside of the specified range of thicknesses, the masking layer116may undesirably cause various issues in manufacturing, e.g., insufficient or nonuniform exposure at different thickness of the masking layer116, inability to get vertical sidewalls, which may in turn lead to metallization structures whose shape or size deviate significantly from the intended shape or size. To address these and other undesirable effects of forming metal features having a thickness substantially greater than that of the masking layer, various methods according to embodiments described herein form electroplated metallization structures that are substantially thicker than the thickness of the masking layer. One example method is described with respect toFIG.2, which describes a method200of forming a relatively thick metal structure by plating, according to various embodiments. The method200includes providing204a substrate. The method includes forming208a first patterning layer over the substrate, including forming a first opening therethrough. A schematic example of the resulting intermediate structure is described infra, e.g., with respect toFIG.3B. The first opening may be formed, e.g., lithographically using a first optical mask or reticle configured to expose a portion of the first masking layer, also referred to herein as the first patterning layer, to form the first opening. The first opening defines a first region on the substrate. The method200additionally includes plating212a first metal in the first opening to form a first metal feature and removing216the first masking layer. A schematic example of the resulting intermediate structure is illustrated infra with respect to, e.g.,FIG.3D. The method additionally includes forming220a second masking layer, also referred to herein as the second patterning layer, over the substrate, where the second masking layer includes a second opening formed therethrough. The second opening is larger than the first opening and encompasses the first region of the substrate defined by of the first opening. The second opening may be formed, e.g., lithographically using a second optical mask configured to expose a portion of the second masking layer to form the second opening larger than the first opening. The second opening defines a second region on the substrate which encompasses the first region of the substrate defined by the first opening. Schematic examples of the resulting structures are illustrated inFIGS.3E,5A,6E,7D, and8D, described in detail infra. The method additionally includes plating224a second metal in the second opening, wherein the second metal is electroplated on the first metal feature to form a metallization structure at a single metallization level. The second metal encapsulates the first metal feature such that the second metal comprises a portion formed on the first metallization structure and a portion that laterally extends outside of the first metal feature. Schematic examples of the resulting structures are illustrated inFIGS.3H,5C,6H,7G and8G or8K, described in detail infra. Various features and intermediate structures that embody the method200can be used to form various metallization structures, including thick metallization structures (e.g.,FIGS.3A-3H), raised metallization structures for reducing the step height for subsequent overlying via (e.g.,FIGS.5A-5F) and encapsulated metallization structures (e.g.,FIGS.6A-6G;FIGS.7A-7F; andFIGS.8A-8K). Thick Electroplated Metallization Structures Formed Using Masking Layers Thinner than the Thick Metal Structure As described herein, electrolytic plating or electroplating refers to a process that uses electric current to reduce dissolved metal cations and electrodepositing or forming a thin metal coating therefrom on a substrate serving as an electrode. The electrodeposition process in electrolytic plating or electroplating can be analogous to a galvanic cell acting in reverse. In some processes, the substrate to be plated serves as the cathode of a circuit, while an anode contains or is formed of the metal to be plated on the substrate. Both components are immersed in a solution called an electrolyte containing one or more dissolved metal salts as well as other ions that permit the flow of electricity. A power supply supplies a current to the anode, oxidizing the metal atoms that it comprises and allowing them to dissolve in the solution. At the cathode, the dissolved metal ions in the electrolyte solution are reduced at the interface between the solution and the cathode, such that they “plate out” onto the substrate serving as the cathode. A rate at which the anode is dissolved may be substantially equal to the rate at which the cathode is plated, vis-a-vis the current through the circuit. In this manner, the ions in the electrolyte bath are continuously replenished by the anode. Plating as described herein is not limited to electroplating. As described herein, plating in various examples or embodiments can be electrolytic or electroless. Unlike electrolytic plating or electroplating described above, an electroless deposition process uses one electrode without an external source of electric current. However, the solution for the electroless process contains a reducing agent so that metal cations are reduced to elemental solid metal on the substrate surface. For example, electroless plating or chemical plating of silver, gold and copper can use a reducing agent such as low molecular weight aldehydes. FIGS.3A-3Hillustrate a method of plating a metallization structure, according to various embodiments. As noted, the method is useful in forming thick metal layers for reduced resistivity, particularly where the thickness is greater than the thicknesses of masking layers used to define the metallization structure. Examples of applications for this embodiment and the embodiments described below include, without limitations, conductors for forming inductors or transformers, such as for isocouplers. FIG.3Aillustrates an intermediate structure300A comprising a substrate104having formed thereon a seed layer112with or without underlying adhesion and/or conductive barrier layer108, similar to the intermediate structure100A described above with respect toFIG.1A. The barrier layer108can serve as an adhesion layer, can be replaced by an adhesion layer, or an additional adhesion layer can be provided below the barrier layer108. As described herein and throughout the specification, it will be appreciated that the substrate104on which metallization structures are formed can be implemented in a variety of materials, including, but not limited to, a semiconductor substrate, e.g., doped semiconductor substrate, which can be formed of an elemental Group IV material (e.g., Si, Ge, C or Sn) or an alloy formed of Group IV materials (e.g., SiGe, SiGeC, SiC, SiSn, SiSnC, GeSn, etc.); Group III-V compound semiconductor materials (e.g., GaAs, GaN, InAs, etc.) or an alloy formed of Group III-V materials; Group II-VI semiconductor materials (CdSe, CdS, ZnSe, etc.) or an alloy formed of Group II-VI materials. The substrate104may also be implemented as a semiconductor on insulator, such as silicon on insulator (SOI) substrate. An SOI substrate typically includes a silicon-insulator-silicon structure in which the various structures described above are isolated from a support substrate using an insulator layer such as a buried SiO2layer. In addition, it will be appreciated that the various structures described herein can be at least partially formed in an epitaxial layer formed at or near a surface region. According to some embodiments, the substrate104may be implemented as an insulating material such as a ceramic or a glass material. For example, the substrate104may be implemented as an aluminum-based material, such aluminum oxide (e.g., Al2O3) and/or aluminum nitride (AlN). However, embodiments are not so limited, and the substrate104can be formed of other materials, e.g., ceramics such as BeO, silicon carbide (SiC), silicon nitride (Si3N4), low temperature co-fired ceramic (LTCC) substrates, silicon dioxide (SiO2), zirconia (ZrO2) and ferrites, to name a few. According to yet some other embodiments, the substrate104may be implemented as a polymeric or a composite material, such as that used in printed circuit boards (PCBs). For example, the substrate104may comprise phenolic paper, phenolic cotton paper, paper impregnated with a phenol formaldehyde resin, a woven fiberglass cloth impregnated with an epoxy resin, polyimide and polyimide-fluoropolymer, to name a few. According to some embodiments, on the substrate104, an adhesion layer (not shown) and/or the electrically conductive barrier layer108when present and the seed layer112may be formed, in a similar manner as described above with respect toFIG.1A. When present, the conductive barrier layer108may serve to inhibit or retard diffusion or interdiffusion of atoms therethrough between layers formed above and below the conductive barrier layer108. For example, a conductive barrier layer108formed of, e.g., TiW or NiMn, can suppress diffusion of metal atoms into the substrate104. The diffusion of metal atoms into the substrate104may cause various undesirable results including, e.g., electrical shorts and/or degradation of characteristics of devices that may be formed in the substrate104. For example, metal diffusion may cause increased leakage current in semiconductor devices that may be formed in the substrate104formed of a semiconductor. Such barrier materials may also serve to improve adhesion to the insulators. According to various embodiments, the conductive barrier layer108may include of one or more of titanium (Ti), tantalum (Ta), tungsten (W) and nickel (Ni) and compounds thereof, alloys (e.g., titanium tungsten (TiW)), and compounds thereof, such as metal carbides or metal nitrides (e.g., titanium nitride (TiN), tungsten nitride (WN) and titanium nitride (TiN)), to name a few. Also as described above, the seed layer112may be a thin conductive layer which serves as nucleation layer for the subsequently electroplated first metal of the first metal feature324(FIG.3C). According to some embodiments, the seed layer112may include or be formed of the same material as the subsequently electroplated first metal feature324(FIG.3C). When formed of the same metal, the seed layer112may serve as a nucleation layer, e.g., a homogeneous nucleation layer, for subsequent growth of the metal during plating of the metallization feature324(FIG.3C). For example, when the subsequently electroplated first metal feature324comprises or is formed of gold, the seed layer112may also comprise or be formed of gold. Likewise, when the subsequently electroplated first metal feature324is formed of copper, the seed layer112may also comprise or be formed of copper. However, embodiments are not so limited, and the seed layer112may comprise or be formed of a metal different from the subsequently plated first metal feature324(FIG.3C), such that the seed layer112serves as a nucleation layer, e.g., a heterogeneous nucleation layer, for the subsequently electroplated first metal feature324. For example, the seed layer112may be formed of chromium (Cr), which can serve as a heterogeneous nucleation layer for subsequent growth of gold thereon during plating of the first metal feature324formed of gold or copper. Typically, the seed layer112extends across the substrate to facilitate electrical connection to a cathode (for electrolytic plating), but can later be removed from outside the feature of interest (see, e.g.,FIG.3H). InFIGS.3A-3Hand for the corresponding layers in other embodiments described herein below, each of the conductive barrier layer108, the seed layer112and the adhesion layer (not shown) can have a thickness of about less than 100 nm, 100 nm, 200 nm, 500 nm, 1000 nm or a thickness in a range defined by any of these values. As noted, in addition to serving as a diffusion barrier and a nucleation layer, the conductive barrier layer108and the seed layer112also may serve to promote adhesion of the first metal feature324to the substrate104. Furthermore, at least one of the conductive barrier layer108and/or the seed layer112may serve as an electrically conducting electrode during electrolytic plating of the first metal feature324. In the illustrated embodiment, both the conductive barrier layer108and the seed layer112are formed prior to plating the first metal feature324. However, here and in various other embodiments described throughout this specification, it will be appreciated that the conductive barrier layer108and/or separate adhesion layer (not shown) may be omitted. In these embodiments, a single layer may serve as conductive barrier and/or adhesion layer and a seed layer for the subsequent electroplated first metal feature324. For example, when the seed layer112is formed of a material which additionally serves as a barrier layer to suppress atomic diffusion therethrough and/or as an adhesion layer, a separate conductive barrier layer108and/or an adhesion layer may be omitted. It will be appreciated that, when the first metal feature324is formed by electrolytic plating, at least one of the substrate104, the conductive barrier layer108and the seed layer112is electrically conducting to serve as an electrode. Thus, when the substrate104is electrically insulating, one or both of the conductive barrier layer108and the seed layer112formed of electrically conductive material may serve as an electrode. The electrically conductive barrier layer108and the seed layer112may be formed using suitable deposition processes, e.g., physical vapor deposition (PVD), chemical vapor deposition (CVD), evaporation or plating. In a similar manner as described above with respect toFIG.1B,FIG.3Billustrates forming a first blanket masking layer on the substrate104and forming an opening320having a width W0therethrough to form a first masking layer116(intermediate structure300B ofFIG.3B) over the substrate104. The opening320is formed using a first optical mask or a reticle. As described herein and throughout the specification, a masking layer such as the masking layer116may include, e.g., a resist or any suitable organic or polymeric material that can be patterned, such as photosensitive materials patterned by exposure to light including, e.g., positive or negative photoresists such as polymethylmethacrylate (PMMA), thermally stable aromatic polymers (BCB or benzo-cyclo-butadiene), SU-8 epoxy resin and polyimides, to name a few. In other embodiments, resist can be patterned in other manners, such as stamping or imprinting. A blanket masking layer, e.g., a blanket photoresist layer, may first be formed to coat the substrate104using, e.g., a spin coating process. In some processes, a blanket photoresist layer may be soft baked, e.g., at a low temperature (e.g., 50° C. to 100° C.), followed by selectively exposing regions of the photoresist layer to light using an optical mask (not shown), also referred to as a photomask or a reticle. The optical mask may be configured to, e.g., expose a region of the masking layer116for forming the opening320through the masking layer116having a width W1. The light can be a UV light having, e.g., a wavelength between 350 nm and 450 nm. In some processes, the exposed photoresist may be post-expose soft baked, e.g., at a low temperature (e.g., 50° C. to 100° C.). Subsequently, photoresist having exposed regions is developed in a developer solution to form the pattern of the masking layer116, followed by rinsing and drying. In some processes, thus formed masking layer116may be hard baked at a higher temperature, e.g., 150° C. to 200° C. In the illustrated example, the masking layer116has formed therethrough the opening320which exposes the underlying seed layer112. As described herein and throughout the specification, the masking layer116may be formed of a positive masking layer, e.g., a positive photoresist in which portions that are exposed to light become soluble and are dissolved by a photoresist developer, while unexposed portions remain insoluble to the photoresist developer. However, in some other example processes, the masking layer116may be formed using a negative masking layer, e.g., a negative photoresist in which portions that are exposed to light become insoluble in a photoresist developer, while unexposed portions are insoluble in the photoresist developer. In a similar manner as described above with respect toFIGS.1C and1E,FIGS.3C and3Dillustrate plating a first metal in the opening320to form the first metal feature324in the opening320(FIG.3C) and subsequently removing the first masking layer116using a suitable stripping process to form the first metal feature324(FIG.3D). For example, when the second masking layer116is formed of photoresist, the masking layer116may be removed by oxidizing or ashing to volatilize the masking layer116under a dry oxidizing atmosphere including, e.g., ozone, oxygen plasma or oxygen radicals, or using a suitable wet stripping process, thereby exposing the underlying seed layer112as illustrated. As described above with respect toFIGS.1A-1F, the first metal feature324may include or be formed of a suitable material, e.g., gold and/or copper, depending on the technology. While metallization structures formed of electroplated gold has long served the electronics industry with its relatively superior electrical conductivity as well as chemical inertness, electroplated copper can offer advantages over gold in some circumstances. While offering significant commercial advantages over gold due to its lower cost, copper may be a good replacement for gold under some circumstances due to its similar electrical properties compared to gold, including inductance and self-capacitance and lower electrical resistivity. In applications where resistance can negatively impact circuit performance, copper can offer an improvement over gold. However, under some other circumstances, e.g., where copper may undesirably diffuse into adjacent interlayer dielectrics and/or substrates, having at least the outer portions of the metallization structures formed of gold may be advantageous. Still referring toFIGS.3B-3D, unlike the example illustrated with respect toFIGS.1A-1F, in which the opening120(FIG.1B) formed through the first masking layer116has substantially the same width W1as the as the target width W1′ of the metal feature124(FIG.1F), the opening320illustrated with respect toFIG.3Bformed using the first optical mask or the reticle and the resulting initial width W0of the first metal feature324is substantially smaller than the target width (W2′ inFIG.3H) of the final metallization structure because a second metal is electroplated to encapsulate the first metal feature324including top and side surfaces thereof, as described infra. In various embodiments described herein, as described above, the first masking layer116may be designed, e.g., by a manufacturer and/or the application process, to be used within a specified range of thicknesses for optimized manufacturability. For example, as formed, the first masking layer116can have a thickness tPR1that is less than 1 micron, 1 to 5 microns, 5 to 10 microns, 10 to 15 microns, 15 to 20 microns or greater than 20 microns, or a value within any range defined by these values, for instance about 10 microns. In various embodiments described herein, the thickness t1of the first metal feature324has a thickness that is smaller than or equal to the thickness tPR1of the first masking layer116. For example, the t1may have a value represented by a percentage of the tPR1described above, e.g., about 50%, 60%, 70%, 80%, 90%, 100% or a value within a range defined by any of these values. In the illustrated embodiment, because the t1is smaller than or equal to the tPR1, the resulting first metal feature324does not form a bread loaf structure. In other embodiments, t1may be greater than tPR1and bread loafing may occur (see, e.g.,FIGS.6A-7Gdiscussed below). Referring to an intermediate structure300E ofFIG.3E, after removing the first masking layer116(FIG.3D), a second masking layer316is formed on the same seed layer112that were employed for the first plating. Similar to forming the first masking layer116, the second masking layer316may include, e.g., a photoresist or any suitable organic or polymeric photoactive material that can be lithographically patterned by exposure to light. In a similar manner to forming the first masking layer116as described above with respect toFIG.3B, to form the second masking layer316, a blanket masking layer, e.g., a blanket photoresist, is first formed on the seed layer112, followed by selectively exposing using a second optical mask or a reticle (not shown) and developing to form the second masking layer316having formed therethrough a second opening322having a width W1wider than the width W0of the first opening320formed through the first masking layer116. Thus formed second opening322leaves expose a surface portions112S on each side of the first metal feature324. The exposed surface portions112S can expose the seed layer112and have a width corresponding to a difference ΔW between the W1and the W0. The skilled artisan will understand that, in the illustrated embodiment and other analogous embodiments in the specification, while only one dimension, e.g., x-dimension, is shown inFIG.3Ein which the width or the x-dimension of a conductive line is wider, the second opening322may also be larger than the feature324in other dimensions, such as, e.g., the y-dimension. In various embodiments, the second masking layer316may be designed, e.g., by a manufacturer and/or the application process, to be used within a similar or different specified range of thicknesses compared to the first masking layer116. For example, as formed, the second masking layer316can have a thickness tPR2that is less than 1 micron, 1 to 5 microns, 5 to 10 microns, 10 to 15 microns, 15 to 20 microns or greater than 20 microns, or a thickness within any range defined by these values, for instance about 10 microns. Referring toFIG.3F, subsequent to selectively exposing using a second reticle and developing the exposed masking layer316to form the second masking layer having the second opening322, a second metal328is electroplated in the second opening322on the exposed surface portions112S and on the first metal feature324, including sidewalls and the top surface thereof, thereby forming a metallization structure332, which may be, for example, a metal line or via in a device such as an inductor or transformer for an isocoupler. The metallization structure332includes the second metal328at least partially encapsulating the first metal feature324. In the illustrated embodiment, the second metal328may be formed of the same metal as the first metal feature324, e.g. gold or copper, depending on the technology. However, embodiments are not so limited and in other embodiments, the second metal328may be formed of a different metal than first metal feature324. For example, when the first metal feature324comprises or is formed of one of gold and copper, the second metal may comprise or be formed of the other of gold and copper. Still referring toFIG.3F, the topology of the metallization structure332thus formed by encapsulating the first metal feature324with the second metal328depends on, among other things, the relative magnitudes of the width difference ΔW between the W1and the W0, and the thickness t2of the second metal328as described above with respect toFIG.3E. For example, as in the illustrated embodiment, when the ΔW is about the same or greater than the thickness of the second metal328, the resulting metallization structure332does not form a bread loaf structure as described above with respect to, e.g.,FIG.1D. That is, when the second metal328is conformally electroplated in the second opening322, so long as the thickness t2of the second metal328does not substantially exceed the ΔW, a width W2of the resulting metallization structure332remains at or below the W1of the second opening322formed in the second patterning layer316by the second reticle, both inside and outside the second opening322. As a result, advantageously, while the sum of the t1of the first metal feature324and the t2of the second metal328is substantially greater than the thickness tPR1of the first masking layer116or the thickness tPR2of the second masking layer316, unlike the intermediate structure100D illustrated with respect toFIG.1D, the resulting metallization structure332does not form a bread loaf structure, thereby reducing the risk of undesirable effects thereof, such as electrical shorting. In various embodiments described herein including the embodiment illustrated with respect toFIG.3F, the thickness t2of the second metal328has a thickness that is equal to or smaller than the thickness tPR2of the second masking layer316. For example, the t2may have a value represented by a percentage of the tPR2, e.g., about 50%, 60%, 70%, 80%, 90%, or 100% or a percentage within a range defined by any of these values. While sidewalls of the metallization structure332are shown abutting sidewalls of the second masking layer316, the skilled artisan will appreciate that, in some embodiments, the sidewall plating may stop short of the masking layer sidewalls. In various embodiments, thus formed metallization structure332has a thickness that is a combined thickness of t1and t2, which has a value that is substantially greater than the first and second masking layers116,316used to form them. However, advantageously, the illustrated metallization structure332does not form a bread loaf structure. At the same time, the embodiment ofFIG.3Fhas more rounded upper corners compared to the conventional corners ofFIG.1C or3Cfrom plating through a mask. The skilled artisan will appreciate that the roundness of the corners is characteristic of a plating process that is conducted simultaneously on the exposed sidewalls and upper surface of the first metal feature324, with exposed sidewalls, ofFIG.3E. It will be understood that such characteristic roundness appears in the product ofFIG.3Hfor this present embodiment, as well as the products of subsequently described embodiments (such as feature532inFIG.5G, and feature852inFIG.8K). The roundedness can be detected in a cross-sectional electron micrograph that can be obtained, e.g., using focused ion beam microscopy. The degree of roundedness can be quantified as a radius of curvature measured from a reference center, e.g., the corner formed by a junction between a sidewall and the upper surface of the first metal feature324. According to various embodiments, the metallization structure332has a radius of curvature having a value that is equal to the t2of the second metal328or exceeding the t2by 10%, 20%, 50% or greater than the t2. Embodiments that include the mushroom shape from breadloafing (such as feature640inFIG.6Hand feature740inFIG.7G) also exhibit such characteristic rounded upper corners. In various embodiments, the thus formed metallization structure332has a combined thickness t1+t2of the first metal feature324and the second metal328which exceeds one or each of tPR1and tPR2by 20%, 40%, 60%, 80%, 100% or by a percentage in a range defined by any of these values. For example, the t1+t2may be 2 to 10 microns, 10 to 20 microns, 20 to 30 microns, 30 to 40 microns or greater than 40 microns, or a thickness within any range defined by these values, for instance about 16 microns. The t1+t2may be achieved by having each of the thicknesses t1and t2, which may be about the same or different, that is 1 to 5 microns, 5 to 10 microns, 10 to 15 microns, 15 to 20 microns or greater than 20 microns, or a thickness within any range defined by these values, for instance about 8 microns. The first metal feature324and the second metal328may have thicknesses such that the ratio of t1/t2is between about 0.5 and 1.5, between about 0.7 and 1.3, between about 0.9 and 1.1, or in a range defined by any of these values, for instance about 1. By way of illustration only, a target thickness for the metallization structure332may be about 16 microns, while a commercially available photoresist may typically provide a thickness of about 10 microns. When a single reticle process illustrated with respect toFIG.1Dis employed, the resulting metal feature may form a bread loaf structure. In contrast, in the illustrated embodiment, the first metal feature324and the second metal328may have thicknesses t1and t2, respectively, each of about 8 microns, such that the resulting metallization structure332formed using two separate masking layers patterned with two separate reticles may have a combined thickness t1+t2of about 16 microns that does not form a bread loaf structure. Other topologies of the metallization structure332are possible at this stage. For example, as described infra with respect to, e.g.,FIG.5B, when the magnitude of the ΔW is substantially greater than the thickness t2of the second metal328, the resulting metallization structure532(FIG.5B) can include an elevated or raised portion. In these embodiments, the second metal528(together with the underlying seed layer112and barrier layer108) encapsulates the first metal feature524and extends laterally beyond the first metal feature524such that the resulting metallization feature includes a raised portion formed the second metal528encapsulating the first metal feature and further includes portions formed by the second metal528that laterally extends to directly contact the seed layer112. FIG.3Gillustrates an intermediate structure300G which shows, subsequent to formation of the metallization structure332illustrated with respect toFIG.3F, removing the second masking layer316using a suitable stripping process to expose the seed layer112, in a similar manner as described above with respect toFIG.3D. FIG.3Hillustrates an intermediate structure300H after removing portions of the seed layer112and any underlying adhesion and/or the conductive barrier layer108that are exposed by removing the second masking layer316as described above with respect toFIG.3G. The exposed portions of the adhesion layer, conductive barrier layer108and/or the seed layer112are removed in a similar manner as described above with respect toFIG.1F, thereby forming the metallization structure332. Because the thicknesses of the adhesion layer, the seed layer112and/or the conductive barrier layer108are relatively small (e.g., few hundred nm) compared to the thickness t2(e.g., few microns) of the second metal328, the amount of the second metal removed as a result of removing the adhesion layer, the conductive barrier layer108and the seed layer112may also be relatively small. Thus, the resulting second metal328has a thickness t2′ that may be substantially the same as the thickness t2prior to removal of the adhesion layer, the conductive barrier layer108and/or the seed layer112. Accordingly, the thicknesses of the metallization structure332before and after removing the adhesion layer, the seed layer112and/or the conductive barrier layer108remain relatively unchanged (t1+t2before versus t1+t2′ after the removal of the adhesion layer, the seed layer112and/or the conductive barrier layer108). Thus, the metallization structure332formed according to the process illustrated above with respect toFIGS.3A-3Huses two optical masks or reticles to first electroplate a first metal324in a first opening320formed through a first masking layer116, where the first opening defines a first region of the substrate, followed by plating a second metal328in a second opening322formed through the second masking layer316, where the second opening defines a second region of the substrate. The second opening322is wider than the first opening320in one or both of the x and y dimensions, and the second region encompasses the first region of the substrate. The resulting metallization structure332comprises the first metal feature324encapsulated by the second metal328, where each of the first metal feature324and the second metal328contacts the same seed layer112, and overlies the same barrier108and/or adhesion layer, when present. It will be appreciated that, when the seed layer112is formed of the same material as the first metal feature324or the second metal328, it may not be distinguishable from the respective layer formed of the same material in a cross-sectional view. In these embodiments, as described with respect toFIGS.3A-3Hand other embodiments described infra, the metallization structure332comprises the first metal feature324encapsulated by the second metal328, where each of the first metal feature324and the second metal328contacts the same adhesion layer or the barrier layer108. In various embodiments, the resulting metallization structure332is formed at a single metallization level. Advantageously, while the metallization structure has a thickness that may substantially exceed the thicknesses of many commercially available masking layers as described above, the resulting metallization structure332can be substantially free of a bread loaf structure, unlike the intermediate structure100D illustrated with respect toFIG.1D. Deep Vias Formed Using Electroplated Thick Metallization Structures Some devices having electroplated metal structures include a plurality of metallization layers that are vertically interconnected by metal-filled vias, e.g., vias filled by electroplated metal.FIG.4illustrates an example intermediate structure400having such vias filled by electroplated metal. The intermediate structure400includes a plurality of electroplated metallization layers formed on a substrate104at different vertical levels. The intermediate structure400includes, e.g., a lower metal feature412, e.g., a lower metal line, formed of a first metal within a first interlayer dielectric (ILD) layer416at a lower vertical level, and an upper metal feature420c, e.g., an upper metal line, formed of a second metal at an upper vertical level, where the lower and upper metal features412and420care vertically interconnected by a via structure404. The via structure404may be formed in an opening formed through one or more intermediate dielectric layers, e.g., second and third ILD layers428,432formed at second and third and vertical levels, respectively, vertically between the lower and upper vertical levels. The via structure404includes portions420a,420bformed at the second and third vertical levels in the illustrated embodiment. In some example processes, the upper metal feature420cand the via structure404are formed in a single process as a via metallization structure420by plating a second metal in via openings formed through a plurality of ILD layers. The second metal may be the same or different from the first metal of the lower metal feature412. In a similar manner as described above with respect to the intermediate structures illustrated inFIGS.1A-1C, the lower metal feature412may be formed on the substrate104by plating on a seed layer408. The via structure404may be formed in the via openings formed through the second and third ILD layers428,432, thereby forming the via structure404connected to the upper metal feature420c. Each of the lower metal feature412, the via structure404and the upper metal feature420cmay include a suitable material, e.g., gold and/or copper, depending on the technology, as described above. Still referring toFIG.4, the intermediate structure400including the lower metal feature412and the via metallization structure420including the upper metal feature420c, the second metal feature420aand the third metal feature420b, may be fabricated as follows, according to one example. First, the lower feature412and the first ILD layer416are formed at the first vertical level according to the method described above with respect toFIGS.1A-1C, except, in the illustrated example, the first ILD layer may be formed of a photosensitive dielectric, such as polyimide, which not only serves as a masking layer for patterning the lower metal feature412but which also remains as part of the final IC device, instead of being formed of a masking layer that is sacrificial, as further described infra. Subsequently, the second and third ILD layers428,432may be successively formed, using similar materials and processes as those used to form the first ILD layer416, such that the second and third ILD layers428,432may permanently remain as part of the final IC device. Similar to the first dielectric layer416, the second and third ILD layers428,432may be formed by first blanket depositing or spin coating, followed by formation of openings therethrough. As illustrated, the openings formed in the second and third ILD layers428,432, are successively larger and formed using lithographic processes similar to those described above with respect toFIGS.1A-1C, in order to facilitate subsequent deposition into a hole of significant depth without forming keyholes. Thereafter, a second seed layer424may be blanket deposited on the exposed top surface of the lower metal feature412, sidewalls of the openings formed in the second and third ILD layers428,432, and upper surfaces of the third ILD layer432. Adhesion and/or barrier layers may also be formed under the second seed layer424. Subsequently, another blanket masking layer, e.g., a photoresist layer, may be formed on the blanket second seed layer424, followed by exposing and developing to remove the masking layer from exposed areas of the second seed layer424on which the via metallization structure420to be electroplated. Subsequently, the via metallization structure420electroplated on the exposed surfaces of the second seed layer424. Thereafter, upon removal of the masking layer followed by removal of the second seed layer424(and any underlying adhesion or barrier layers) in a similar manner as described above with respect toFIGS.1E and1F, the illustrated intermediate structure400is formed. It will be appreciated that, in order to electroplate the second metal in the openings formed through the second and third ILD layers428,432to form the via structure404with good electrical contact, prior to depositing the second seed layer424, the exposed masking layer should be removed essentially completely from the openings. However, when the depth h1of the opening formed through the second and third ILD layers428,432is relatively high, complete and/or uniform removal of the masking layer from the openings may be difficult. When the removal of the masking layer from the openings is incomplete and/or nonuniform prior to plating the via metallization structure420, the remaining masking layer may cause failure of the resulting IC device, e.g., open circuit or low conductivity. The incomplete or uneven removal of the masking layer may be caused by, among other things, limited depth of focus and/or uneven exposure of the masking layer as a function of the depth h1during exposure. In addition, when aspect ratios of the openings formed through the second and third ILD layers428,432are high, the complete removal of the masking layer therefrom may be difficult. To mitigate these and other difficulties associated with via formation, in the following, a fabrication method is described with respect toFIGS.5A-5Gin which, instead of forming a via structure or a via metallization structure by plating in a relatively deep opening to contact the lower metal feature as illustrated inFIG.4, the second metal is electroplated in a relatively shallow opening, which is in part enabled by formation of a metal feature having an elevated or raised portion or a stud portion, which is fabricated in a manner similar that described above with respect toFIGS.3A-3H. FIG.5Aillustrates an intermediate structure500A fabricated using a process sequence similar to the process sequence illustrated above with respect toFIGS.3A-3E. For example, after forming a first seed layer112with or without underlying adhesion and/or conductive barrier layer108, a first metal feature524having a thickness t1and a width W0is formed by first forming a first opening having the width W0in a first masking layer (not shown), e.g., a photoresist layer, using a first reticle or optical mask, and plating a first metal therein. Thereafter, the first masking layer (not shown) is stripped and a second masking layer316, e.g., a photoresist layer, having a second opening522having a width W1larger than the W0by ΔW is formed using a second reticle or optical mask. The resulting intermediate structure500A is analogous to the intermediate structure300E ofFIG.3E, except, the ΔW is greater than the thickness t2of the second metal528, as described below with respect toFIG.5B. FIG.5Billustrates an intermediate structure500B, after plating a second metal528in the second opening522and on the first metal feature524to a thickness t2, thereby forming the metallization structure532having a combined thickness t1+t2and the combined width W1. The metallization structure532is formed using a process sequence similar to that illustrated above with respect toFIG.3Fexcept, because the ΔW is greater than the thickness t2of the second metal528, the second metal528encapsulates the first metal feature524and laterally extends outside of the first metal feature524to form portions of the second metal528electroplated directly on the seed layer112. That is, unlike the metallization structure332(FIG.3H), the difference ΔW between the W1and the W0has a dimension such that the second metal528, in addition to coating top and side surfaces of the first metal feature524, laterally extends in the spaces between the first metal feature524and the sidewalls of the second masking layers316, thereby forming a raised or elevated portion532A or a stud portion having a width W2as illustrated inFIG.5B. However, embodiments are not so limited, and in other embodiments, the ΔW may be comparable or smaller than t2such that a metallization structure similar to the metallization structure332not having the raised or elevated portion532A may be formed, as illustrated with respect toFIG.3F. FIG.5Cillustrates an intermediate structure500C, after removing the second masking layer316from the intermediate structure500B ofFIG.5B, e.g., by stripping or ashing, thereby exposing the seed layer112, in a similar manner as described above with respect toFIG.3G. Thereafter, exposed portions of the seed layer112and any adhesion layer and/or the conductive barrier layer108are removed, in a similar manner as described above with respect toFIGS.3G and3H. Because a relatively small amount of the second metal328is removed during the removal of the seed layer112, any adhesion layer and/or the conductive barrier layer108, the second metal528has a thickness t2′ and the metallization structure532(FIG.5C) has a thickness of t1+t2′ that is substantially the same as the thickness t1+t2of the metallization structure532prior to the removal of the seed layer112, any adhesion layer and/or the conductive barrier layer108from regions exposed by removing the second masking layer316(FIG.5B). Referring toFIG.5D, after forming the metallization structure532having the raised or elevated portion532A, one or more interlayer dielectric (ILD) layers, e.g., a first ILD layer536, a second ILD layer540and a third ILD layer544are formed over the substrate. The first, second and third ILD layers536,540,544may be formed of a suitable photosensitive electrically insulating material adapted to serve as a masking layer as well as a permanent ILD, e.g., photosensitive polyimide. In various embodiments, the metallization structure532having the raised or elevated portion532A may first be buried in one or more ILD layers and subsequently be partially exposed by forming one or more openings through the one or more ILD layers. In the illustrated embodiment, the second ILD layer540has formed therein a first via opening548which exposes the raised or elevated portion532A of the metallization structure532, and the third ILD layer544has formed therein a second via opening552wider than the first opening and encompassing the first via opening, such that the resulting via opening through the second and third ILD layers540,544form a staircase structure. It will be appreciated that, because the metallization structure532includes the raised or elevated portion532A, a combined depth h2of the first and second via openings548,552through the second and third ILD layers540,544, respectively, is shallower compared to the corresponding combined depth h1through second and third ILD layers423,432without a raised or elevated portion in the intermediate structure400illustrated with respect toFIG.4by an amount comparable to the height of the raised or elevated portion532A of the metallization structure532. Advantageously, the shallower depth provides, among other things, a relatively shallower range of depth of penetration for the light used to expose and remove the masking layer from first and second via openings548,552, thereby reducing the tendency for incomplete and/or nonuniform removal of the masking layer therefrom, prior to subsequently plating in the via openings548,552to form a via metallization structure564(FIG.5G), which in turn reduces the risk of device failures, e.g., open circuit or low conductivity. The shallower depth also facilitates deposition into the vias with less risk of keyhole formation due to faster deposition over corners, which naturally exhibit higher electric field strength during deposition. In the illustrated embodiment, one or more of the first, second and third ILD layers536,540,544are formed of a photosensitive dielectric that can be patterned by photolithography, i.e., by being selectively exposed to light and developed. Unlike some photoresist layers that serve as temporary and sacrificial masking layers, however, the first, second and third ILD layers536,540,544serve as masking layers and ILD layers that remain as permanent part of the final IC device. In some embodiments, one or more of the first, second and third ILD layers536,540,544are formed of a photosensitive polyimide, which can be patterned, e.g., to form first and second via openings548,552as illustrated inFIG.5D, using a process analogous to photolithography. For example, to form one or more of the first, second and third ILD layers536,540,544, a photosensitive polyimide may be patterned by being spun-on, baked, and exposed using a reticle or an optical mask. The exposed photosensitive polyimide layer may subsequently be developed to form a patterned masking layer, including, e.g., the first and second via openings548,552as illustrated with respect toFIG.5D. In some embodiments, the one or more of the first, second and third ILD layers536,540,544may be optionally thermally cured. Curing the first, second and third ILD layers536,540,544may provide, among other things, increased resistance to subsequent exposures to solvents and solutions and improved quality as permanent dielectric layers as part of the final IC device. Referring toFIG.5E, after forming the first and second via openings548,552, a second seed layer556and any underlying adhesion layer and/or a second conductive barrier layer552may be blanket deposited on the surface of the intermediate structure500D (FIG.5D), thereby lining the inside and outside the first and second via opening openings548,552. The second conductive barrier layer552and the second seed layer556may serve similar functions and are formed using similar methods as the first conductive barrier layer108and the first seed layer112, respectively, as described supra. In addition, similar to the first conductive barrier layer108and the first seed layer112, the second seed layer556and one or both of the adhesion layer and the second conductive barrier layer552may be formed, according to different embodiments, depending on various factors including whether a subsequently electroplated via metallization structure564(FIG.5G) is formed of a metal that is the same or different than the first metal feature524and/or the second metal528. For example, when the first metal feature524and/or the second metal528are formed of gold and the third metal is formed of copper, the conductive barrier layer552and the seed layer556may be present to retard interdiffusion or diffusion of copper and/or gold therethrough. On the other hand, when the first metal feature524and/or the second metal528are formed of gold and the third metal is also formed of gold, the conductive barrier layer552may be omitted, and the seed layer556may also be omitted if the subsequent deposition does not rely upon it (e.g., CVD or sputtering). However, embodiments are not so limited and the conductive barrier layer552and the seed layer556may be present even when the first metal feature524and/or the second metal528are formed of gold and the third metal is also formed of gold. Still referring toFIG.5E, after any adhesion layer, the second conductive barrier layer552and the second seed layer556are formed, a third masking layer560, which may be similar to the first and second masking layers116,316, e.g., a photoresist, may be blanket deposited on the second conductive barrier layer552or the second seed layer556. The third blanket masking layer560may be patterned in a similar manner as described with respect to first and second masking layers116,316, to arrive at the intermediate structure500F illustrated with respect toFIG.5F, in which portions of the third blanket masking layer560have been removed from locations on which the via metallization structure564(FIG.5G) is to be electroplated, as described below with respect toFIG.5G. FIG.5Gillustrates an intermediate structure500G, after plating a third metal on areas from which the third masking layer560has been removed (FIG.5F), removing the third masking layer564by stripping or ashing and removing the exposed second conductive barrier layer552and the second seed layer556, thereby forming the via metallization structure564. Because the metallization structure532has the raised or elevated portion532A, the combined depth h2(FIG.5F) of the first and second via openings548,552formed through the second and third ILD layers is shallower compared to the corresponding combined depth h1through the second and third ILD layers without the raised or elevated portion in the intermediate structure400described above with respect toFIG.4, by an amount comparable to the height of the raised or elevated portion532A. The shallower depth h1provides, among other things, a relatively shallower range of depth of penetration for the light used to expose the third masking layer560formed in the first and second via openings548,551, thereby reducing the tendency for incomplete and/or uneven removal of the third masking layer560therefrom, prior to subsequently electroplating in the vias openings548,551to form the via metallization structure564(FIG.5G). Thus formed via metallization structure564may result from a lower risk of device failures, e.g., open circuit or low conductivity. Encapsulated Metallization Structures According to various embodiments described above, by using different reticles or optical masks to electroplate metals in in successively larger and overlapping openings formed through different masking layers, metallization structures that are thicker (e.g., the metallization structure332inFIG.3H) than the masking layers (e.g., first and second masking layers116,316inFIGS.3B,3E) can be formed, while avoiding undesirable effects arising from overplating, e.g., breadloafing. As described above, these methods can be particularly beneficial for forming metallization structures for IC devices or packaging for IC devices where a relatively higher thickness (e.g., greater than 10 microns) of the metallization structures is employed. For example, in some of the embodiments described above, the metallization structures formed of, e.g., gold, are formed within ILD layers formed of, e.g., polyimide. Under some circumstances, the metallization structures formed of gold can be desirable for various reasons arising from properties of gold, including relatively low electrical resistivity, relatively low chemical reactivity, relatively high moisture resistance and relatively low diffusivity within ILD layers, among other properties. However, relative to other metals that can be electroplated, e.g., copper or nickel, gold can be substantially more expensive. Nevertheless, a complete replacement of gold with another metal may not be desirable or practical despite the potential cost savings under some circumstances. For example, when the metallization structures formed of certain other metals, e.g., copper, are in direct contact with substrate and or the ILD layers, atoms of the metallization structures may migrate thereinto or therethrough, thereby potentially causing electrical failures. To address these and other needs and concerns, in the following, methods of forming thick composite metallization structures formed of a plurality of different electroplated metals are described, where one of the electroplated metals, e.g., copper, is at least partially encapsulated by another one of the electroplated metals, e.g., gold. FIGS.6A-6Hillustrate a method of forming an encapsulated composite metallization structure having a thickness greater than the thickness(es) of masking layer(s) used to define the metallization structure, where the metallization structure is formed by first plating to form a first metal feature, followed by plating a second metal different from the first metal to at least partially encapsulate the first metal feature, according to various embodiments. FIG.6Aillustrates an intermediate structure600A, formed in a similar manner as described above with respect toFIG.3A, which comprises a substrate104having formed thereon an electrically conductive barrier layer108and a seed layer112. FIG.6Billustrates an intermediate structure600B, formed in a similar manner as described above with respect toFIG.3B, including blanket depositing a first masking layer116on the conductive barrier layer108or the seed layer112, and using a first reticle or optical mask to form a first opening620in a first masking layer116having a width W0. However, unlike the intermediate structure300B described above with respect toFIG.3B, after forming the opening620, the exposed seed layer112is removed from the opening620, thereby exposing the underlying conductive barrier layer108. After forming the first opening620, the first masking layer116is removed. Referring toFIG.6C, after removing the first masking layer116, a second masking layer616is blanket deposited over the substrate104, and a second reticle or optical mask is used to form a second opening624formed through the second masking layer616having a width W1smaller than the width W0of the first opening620formed through the first masking layer116(FIG.6B). Because the W1is smaller than the W0, the second masking layer616covers the seed layer112and portions of the conductive barrier layer108exposed by removing the seed layer112from the first opening620as illustrated inFIG.6B. Referring toFIG.6D, subsequent to forming the second opening624, a first metal feature628is formed by plating a first metal in the second opening624. In some embodiments, the first metal may be copper. However, embodiments are not so limited and in some other embodiments, the first metal may be gold or another metal. Unlike the first metal feature324described above with respect toFIG.3C, in the illustrated embodiment, the first metal feature628is overplated to have a thickness t1that exceeds the thickness tPRof the second masking layer616. When overplated as illustrated, the first metal feature628may grow laterally beyond the W1above the second opening624, to form a bread loaf structure having a width W2above the second opening624, in a similar manner as described above with respect toFIG.1D. However, unlikeFIG.1D, because a second metal636subsequently encapsulates the bread loaf structure (FIG.6F), certain undesirable properties of the bread loaf described above with respect toFIG.1Dmay be mitigated, while advantageously forming a portion of the resulting metallization structure640(FIG.6F) using a less expensive metal, e.g., copper. However, embodiments are not so limited, and in other embodiments, the first metal may not be overplated and the t1of the first metal feature628may have be less than the tPRsuch that a bread loaf structure is not formed. After plating or overlplating to form the first metal feature628, the second masking layer616is removed. Referring toFIG.6E, after removing the second masking layer616, a third masking layer630is blanket deposited over substrate104and the first metal feature628, and a third reticle or optical mask is used to form a third opening634through the third masking layer630having a width W3wider than the W1of the second opening624(FIG.6C), such that gaps638are formed laterally between the first metal feature628and the third masking layer630on both sides of the first metal feature628. In some embodiments, the W3is about the same as the W0of the first opening620(FIG.6B). However, W3may be larger or smaller than the W0of the first opening620. It will be appreciated that when the first metal feature628has a bread loaf structure as illustrated, portions of a the third masking layer630formed underneath the overhang regions of the bread loaf structure may be prevented from being exposed to light used to define the third opening634. As a result, when the third masking layer630is formed of a positive masking layer, e.g., a positive photoresist, in which portions that are unexposed to light remain insoluble in a photoresist a developer, a complete removal of the third masking layer630from the overhang regions may be difficult. To address these and other concerns, in some embodiments, the third masking layer630may be formed of a negative masking layer, e.g., negative photoresist in which portions that are unexposed to light remains soluble. In these embodiments, by using a negative masking layer, the third opening634can be defined by exposing areas outside of the overhang regions, thereby obviating the concerns of incomplete removal of the masking layer from underneath the overhang regions. Referring toFIG.6F, after forming the third opening634, a second conductive barrier layer632may be formed on, e.g., to at least partially encapsulate or envelope, the first metal feature628. The second conductive barrier layer632is formed of a suitable material which may serve as a diffusion barrier and/or a seed layer for the second metal. In the illustrated embodiment, the second conductive barrier layer632is electroplated on conductive surfaces, including the exposed surfaces of the first metal feature628and the first conductive barrier layer108in the gaps638. Thereafter, a second metal636is electroplated on the first metal feature628. The second metal636at least partially encapsulates or envelopes the first metal feature628. The resulting metallization structure640is thus formed, where the first electroplated metal feature628formed of a first metal, e.g., copper, is encapsulated by a second metal, e.g., gold. As described above, in some embodiments, the first metal feature628may be formed of copper, while the second metal636may be formed of gold. As described above, by forming the metallization structure640as a composite metal structure, different characteristics of the component metals may provide complementary characteristics to the metallization structure640. For example, gold has various desirable properties described above, e.g., relatively low tendency to migrate into surrounding ILD layers, while copper has various complementarily desirable properties, e.g., low resistivity and lower cost. Thus, by encapsulating the first metal feature628formed of copper with gold as the second metal636, the metallization structure640can benefit from the low resistivity of copper while benefiting from the low tendency for migration of gold into the surrounding ILD layers. In addition, because copper is substantially cheaper than gold, the metallization structure640may provide substantial cost savings compared to a similar structure formed of gold. However, embodiments are not so limited, and in other embodiments, the first metal feature628and the second metal636may be formed of any combination of same of different electroplated metals. When the first metal feature628is formed of copper and the second metal636is formed of gold, without a suitable barrier layer therebetween, the copper atoms from the first metal feature628may diffuse through the second metal636formed of gold, which can be undesirable. For example, copper may diffuse to the surface of the second metal636and form an oxide, thereby degrading the electrical conductivity and/or forming an open circuit. Thus, in various embodiments, a suitable material may be selected for the second conductive barrier layer632to serve as a diffusion barrier to suppress diffusion or interdiffusion of copper and/or gold atoms therethrough, and/or to serve as a seed layer for the second metal636. In some embodiments, a suitable conductive barrier layer632may comprise nickel to serve as a diffusion barrier and/or a seed layer for gold. For example, the second conductive barrier layer632may be formed of elemental nickel or a nickel alloy, e.g., NiMn. The second conductive barrier layer632may be formed using a suitable process. For example, in the illustrated embodiment, the second conductive barrier layer632is selectively deposited on conductive surfaces including exposed surfaces of the first metal feature628and the first conductive barrier layer108by plating, such that the first metal feature628is conformally encapsulated. However, embodiments are not so limited, and in other embodiments, the second conductive barrier layer632may be formed using other suitable selective or nonselective techniques, e.g., chemical vapor deposition, atomic layer deposition or physical vapor deposition. Still referring to the illustrated embodiment ofFIG.6F, the metallization structure640has an upper portion protruding above the third opening634and having width W4that is smaller than the W3of the third opening634. In addition, the metallization structure640includes the second metal636formed in the gaps638that laterally extend to contact the third masking layer630. The resulting metallization structure640includes a raised or elevated portion similar to the metallization structure described above with respect toFIG.5B, except that the metallization structure640is a composite structure formed of a plurality of metals. However, it will be appreciated that, when the W4of the metallization is substantially the same as the W3, the raised or elevated portion may not be present, in a similar manner as described above with respect toFIG.3F. FIG.6Gillustrates an intermediate structure600G, after removing the third masking layer630, thereby exposing the first seed layer112or the first conductive barrier layer108laterally outside the metallization structure640. FIG.6Hillustrates an intermediate structure600H, after removing the first seed layer112and the first conductive barrier layer108laterally outside the metallization feature640. Thus formed metallization structure640has a thickness greater than the thickness of masking layers used to define the metallization structure640, where the metal structure640is a composite structure formed by plating the first metal, e.g., copper to form the first metal feature628, and plating the second metal636, e.g., gold to encapsulate the first metal feature628. The core of the metallization structure640formed of the first metal, e.g., copper, can thus provide high conductivity and/or lower cost, while the shell of the metallization structure640formed of the second metal, e.g., gold, can prevent the first metal from directly contacting the surrounding ILD layers. In addition, migration or diffusion of the first metal into or through the second metal636and into the substrate104and surrounding ILD layers can be retarded or suppressed by forming conductive barrier layers108,632that encapsulate the first metal feature628. FIGS.7A-7Gillustrate an alternative method of forming a composite encapsulated metallization structure including a first metal feature encapsulated by a second metal different from the first metal, according to embodiments. FIG.7Aillustrates an intermediate structure700A, formed in a similar manner as described above with respect toFIGS.3A and6A. FIG.7Billustrates an intermediate structure700B, after blanket depositing a first masking layer116on the conductive barrier layer108and/or the first seed layer112on a substrate104, and using a first reticle or optical mask to form a first opening720having a width W1through the first masking layer116, thereby exposing the first seed layer112(or the first conductive barrier layer108if the first seed layer112is not present), in a similar manner as descripted above with respect toFIG.3B. Thereafter, on the exposed first conductive barrier layer108or the first seed layer112, a second conductive barrier layer704is formed. A suitable material for the second conductive barrier layer704may be selected to serve as a diffusion barrier to further suppress, in addition to the first conductive barrier layer108, the diffusion of the subsequently electroplated first metal into the substrate104, and/or to serve as a seed layer for the first metal. For example, when the first metal is copper, a suitable conductive barrier layer632may comprise elemental nickel or a nickel alloy, e.g., NiMn, similar to the second conductive barrier632as described above with respect toFIG.6F. ReferringFIG.7C, a first metal is electroplated into the first opening720to form the first metal feature728. As described above with respect toFIG.6D, the first metal feature728may be formed of a first metal, e.g., copper, and may be overplated to have a thickness t1exceeding the thickness tPRof the first masking layer116to form a bread loaf structure having a width W2above the first opening720. Referring toFIG.7D, in a similar manner as described above with respect toFIG.6E, after plating to form the first metal feature728, the first masking layer116(FIG.7C) is removed, and a second masking layer716is blanket deposited and patterned using a second reticle or optical mask to form a second opening734through the second masking layer716having a W3wider than the W1, such that gaps738are laterally formed between the first metal feature728and the second masking layer716on both sides of the first metal feature728. UnlikeFIG.6E, the first seed layer112is exposed in the gaps738and the second conductive barrier layer704is interposed between the first metal feature728and the substrate104to serve as a further diffusion barrier therebetween. FIG.7Eillustrates an intermediate structure700E, after forming a third conductive barrier layer732to at least partially encapsulate or envelope the first metal feature728and plating a second metal736different from the first metal to at least partially encapsulate or envelope the first metal feature728, in a similar manner as described above with respect toFIG.6F. Also similarly, a suitable material, e.g., NiMn, may be selected for the third conductive barrier layer732to serve as a diffusion barrier and/or to as a seed layer for the second metal736. FIGS.7F and7Gillustrate intermediate structures700F,700G after removing the second masking layer716, and after removing the first seed layer112and the first conductive barrier layer108laterally outside the metallization feature740, respectively, in a similar manner as described above with respect toFIGS.6F and6G. Thus formed metallization structure740is similar to the metallization structure640described above with respect toFIG.6Gexcept, migration or diffusion of the first metal, e.g., copper, into the substrate104is further retarded or suppressed by the third conductive barrier layer704and/or the first seed layer112interposed between the metallization structure740and the substrate104. FIGS.8A-8Killustrate an alternative method of forming a composite encapsulated metallization structure, where the metal structure is formed by first plating a first metal feature, and subsequently plating more than one additional metal to at least partially encapsulate the first metal feature, according to embodiments. FIGS.8A and8Billustrate intermediate structures800A and800B, formed in a similar manner as described above with respect toFIGS.7A and7B.FIG.8Cillustrates an intermediate structure800C, formed in a similar manner as described above with respect toFIG.7Cincluding forming a first metal feature828by plating a first metal in a first opening720formed using a first reticle or optical mask. However, unlike the intermediate structure700C described above with respect toFIG.7C, the first metal feature728is electroplated to have a width W1and a thickness t1that is about to equal to or less than the thickness tPRof the first masking layer116, such that a bread loaf structure from overplating does not result. FIG.8Dillustrates an intermediate structure800D, fabricated in a similar manner as described above with respect toFIG.7D, including removing the first masking layer616and forming a second masking layer816having formed therethrough a second opening834using a second reticle or optical mask. The second opening834has a width W3wider than the width W1, such that first gaps838are formed between the first metal feature828and the second masking layer816on both sides of the first metal feature828. Subsequently, similar to as described above with respect toFIG.7E, a third conductive barrier layer832, e.g., NiMn, may be formed to at least partially encapsulate or envelope the first metal feature828. Referring toFIG.8F, a second metal836same or different from the first metal is electroplated to at least partially encapsulate or envelope the first metal feature828, thereby forming a first metallization structure840. FIG.8Gillustrates an intermediate structure800G after the second masking layer816is stripped. FIG.8Hillustrates an intermediate structure800H after forming a third masking layer846having formed therethrough a third opening842using a third reticle or optical mask. The third opening842has a width W4wider than the W3of the first metallization structure840(FIG.8G), such that second gaps838are formed between the first metallization structure840and the third masking layer846on both sides of the first metallization structure840. Referring toFIG.8I, a fourth conductive barrier layer844, e.g., NiMn, may be formed to at least partially encapsulate or envelope the first metallization feature840. After forming the third conductive barrier layer844, a third metal848same or different from the second metal836and/or the third metal836is electroplated on the first metallization structure840. The third metal848at least partially encapsulates or envelopes the first metallization structure840, thereby forming a second metallization structure852. The resulting second metallization structure852is thus formed by sequentially plating one, two or three different metals. While not illustrated, additional metals can be further electroplated. In some embodiments, each of the first metal feature828, the second metal836and third metal848can be formed of the same or different metal from each other, e.g., copper or gold For example, the first metal feature828and the second metal836can be formed of copper, while the outermost third metal848can be formed of gold. FIG.8Jillustrates an intermediate structure800J, after removing the third masking layer846, thereby exposing the first seed layer112or the first conductive barrier layer108laterally outside the second metallization structure852. FIG.8Killustrates an intermediate structure800K, after removing the first seed layer112and the first conductive barrier layer108laterally outside the second metallization structure852. Thus formed second metallization structure852is similar to the metallization structure740described above with respect toFIG.7Gexcept, migration or diffusion of the first metal, e.g., copper, outside the first metal feature828may be further suppressed by the fourth conductive barrier layer844. Aspects of this disclosure can be implemented in various electronic devices. Examples of the electronic devices can include, but are not limited to, consumer electronic products, parts of the consumer electronic products, electronic test equipment, cellular communications infrastructure such as a base station, etc. Examples of the electronic devices can include, but are not limited to, a mobile phone such as a smart phone, a wearable computing device such as a smart watch or an ear piece, a telephone, a television, a computer monitor, a computer, a modem, a hand-held computer, a laptop computer, a tablet computer, a personal digital assistant (PDA), a microwave, a refrigerator, a vehicular electronics system such as an automotive electronics system, a stereo system, a DVD player, a CD player, a digital music player such as an MP3 player, a radio, a camcorder, a camera such as a digital camera, a portable memory chip, a washer, a dryer, a washer/dryer, peripheral device, a clock, etc. Further, the electronic devices can include unfinished products. Unless the context clearly requires otherwise, throughout the description and the claims, the words “comprise,” “comprising,” “include,” “including” and the like are to be construed in an inclusive sense, as opposed to an exclusive or exhaustive sense; that is to say, in the sense of “including, but not limited to.” The word “coupled”, as generally used herein, refers to two or more elements that may be either directly connected, or connected by way of one or more intermediate elements. Likewise, the word “connected”, as generally used herein, refers to two or more elements that may be either directly connected, or connected by way of one or more intermediate elements. Additionally, the words “herein,” “above,” “below,” and words of similar import, when used in this application, shall refer to this application as a whole and not to any particular portions of this application. Where the context permits, words in the above Detailed Description using the singular or plural number may also include the plural or singular number, respectively. The word “or” in reference to a list of two or more items, that word covers all of the following interpretations of the word: any of the items in the list, all of the items in the list, and any combination of the items in the list. Moreover, conditional language used herein, such as, among others, “can,” “could,” “might,” “may,” “e.g.,” “for example,” “such as” and the like, unless specifically stated otherwise, or otherwise understood within the context as used, is generally intended to convey that certain embodiments include, while other embodiments do not include, certain features, elements and/or states. Thus, such conditional language is not generally intended to imply that features, elements and/or states are in any way required for one or more embodiments or whether these features, elements and/or states are included or are to be performed in any particular embodiment. While certain embodiments have been described, these embodiments have been presented by way of example only, and are not intended to limit the scope of the disclosure. Indeed, the novel apparatus, methods, and systems described herein may be embodied in a variety of other forms; furthermore, various omissions, substitutions and changes in the form of the methods and systems described herein may be made without departing from the spirit of the disclosure. For example, while blocks are presented in a given arrangement, alternative embodiments may perform similar functionalities with different components and/or circuit topologies, and some blocks may be deleted, moved, added, subdivided, combined, and/or modified. Each of these blocks may be implemented in a variety of different ways. Any suitable combination of the elements and acts of the various embodiments described above can be combined to provide further embodiments. The various features and processes described above may be implemented independently of one another, or may be combined in various ways. All possible combinations and subcombinations of features of this disclosure are intended to fall within the scope of this disclosure. | 85,768 |
11862519 | DETAILED DESCRIPTION The following disclosure provides many different embodiments, or examples, for implementing different features of the provided subject matter. Specific examples of components and arrangements are described below to simplify the present disclosure. These are, of course, merely examples and are not intended to be limiting. For example, the formation of a first feature over or on a second feature in the description that follows may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features may be formed between the first and second features, such that the first and second features may not be in direct contact. In addition, the present disclosure may repeat reference numerals and/or letters in the various examples. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed. Further, spatially relative terms, such as “beneath,” “below,” “lower,” “above,” “upper” and the like, may be used herein for ease of description to describe one element or feature's relationship to another element(s) or feature(s) as illustrated in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The apparatus may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein may likewise be interpreted accordingly. The present disclosure is directed to, but not otherwise limited to, an integrated circuit device having a FinFET device. The FinFET device, for example, may be a complementary metal-oxide-semiconductor (CMOS) device comprising a P-type metal-oxide-semiconductor (PMOS) FinFET device and an N-type metal-oxide-semiconductor (NMOS) FinFET device. The following disclosure will continue with a FinFET example to illustrate various embodiments of the present disclosure. It is understood, however, that the application should not be limited to a particular type of device, except as specifically claimed. The fins may be patterned by any suitable method. For example, the fins may be patterned using one or more photolithography processes, including double-patterning or multi-patterning processes. Generally, double-patterning or multi-patterning processes combine photolithography and self-aligned processes, allowing patterns to be created that have, for example, pitches smaller than what is otherwise obtainable using a single, direct photolithography process. For example, in some embodiments, a sacrificial layer is formed over a substrate and patterned using a photolithography process. Spacers are formed alongside the patterned sacrificial layer using a self-aligned process. The sacrificial layer is then removed, and the remaining spacers may then be used to pattern the fins. FIG.1is a cross-sectional view of an integrated circuit device100according to some embodiments of the present disclosure. The integrated circuit device100includes a semiconductor substrate110, isolation dielectrics120, a gate structure DG, gate spacers150, a fin sidewall spacer162, and an epitaxial feature170. The isolation dielectrics120is over the substrate110and surrounds a semiconductor fin112of the semiconductor substrate110. The gate structure DG is crossing a first portion of the fin112protruding from a top surface of the isolation dielectrics120. The gate structure DG may include a gate dielectric layer142and a gate electrode layer144. The gate spacers150are respectively on opposite sides of the gate structure DG. A second portion of the fin112not covered by the gate structure DG may be recessed to form a recess112r. The epitaxial feature170may be formed over the recessed second portion of the fin112and filling the recess112r. In some embodiments of the present disclosure, the fin sidewall spacer162is at a first side170aof the epitaxial feature170, and a second side170bof the epitaxial feature170may be free of a fin sidewall spacer. Through the configuration of the fin sidewall spacer162, the epitaxial growth of the epitaxial feature170on the second portion of the fin112may be limited by the fin sidewall spacer162. For example, the epitaxial feature170extends further to the second side170bthan to the first side170a. FIG.2is a cross-sectional view of an integrated circuit device100according to some embodiments of the present disclosure. The present embodiments are similar to those shown inFIG.1, and one of the differences between the present embodiments and the embodiments ofFIG.1is that: epitaxial features172and174are respectively on semiconductor fins112aand112bof the semiconductor substrate110, and the fin sidewall spacer162is at a first side172aof the epitaxial feature172. In some embodiments of the present disclosure, a second side172bof the epitaxial feature172and two opposite sides174aand174bof the epitaxial feature174are free of a fin sidewall spacer. Through the configuration of the fin sidewall spacer162, the epitaxial feature172extends further to the epitaxial feature174, thereby merging with the epitaxial feature174. Other details are similar to those illustrated with the embodiments ofFIG.1, and therefore not repeated herein. FIG.3is a cross-sectional view of an integrated circuit device100according to some embodiments of the present disclosure. The present embodiments are similar to those shown inFIG.2, and one of the differences between the present embodiments and the embodiments ofFIG.2is that: epitaxial features171-178are respectively on semiconductor fins112a-112hof the semiconductor substrate110, and the fin sidewall spacers162are respectively at a first side171aof the epitaxial feature171, a second side174bof the epitaxial feature174, a first side175aof the epitaxial feature175, and a second side178bof the epitaxial feature178. Through the configuration of the fin sidewall spacers162, the epitaxial features171-174are merged, the epitaxial features175-178are merged, and the merged epitaxial features171-174are spaced apart from the merged epitaxial features175-178. In some embodiments of the present disclosure, the integrated circuit device100further includes fin sidewall spacers162′ on opposite sides of the epitaxial features172,173,176, and177, and on a second side171bof the epitaxial feature171, a first side174aof the epitaxial feature174, a second side175bof the epitaxial feature175, and a first side178aof the epitaxial feature178. In some embodiments, a height of the fin sidewall spacers162′ is less than a height of the fin sidewall spacers162, such that the fin sidewall spacers162′ have less influence on the epitaxial growth of the epitaxial features171-178, which in turn result in that the epitaxial features171-174are merged, and the epitaxial features175-178are merged. In some other embodiments, the fin sidewall spacers162′ may be omitted. FIG.4is a cross-sectional view of an integrated circuit device100according to some embodiments of the present disclosure. The present embodiments are similar to those shown inFIG.2, and one of the differences between the present embodiments and the embodiments ofFIG.2is that: a recess112rbover the semiconductor fin112bis deeper than a recess112raover the semiconductor fin112a. By designing the recesses112raand112rbhave different depths, the semiconductor material may be epitaxially deposited over the semiconductor fins112aand112bwith different facets. For example, the epitaxial feature174has a sidewall surface174swith (111) facet, which tilts substantially 45 degrees with respect to a top surface of the substrate110. The epitaxial feature172over the semiconductor fin112amay have a sidewall surface172sat an angle greater than 45 degrees with respect to the top surface of the substrate110. That is, the sidewall surface172sof the epitaxial feature172may be more vertical than a sidewall surface174sof the epitaxial feature174is. Through the configuration, the epitaxial feature172extends laterally less than the epitaxial feature174does, and the epitaxial feature174over the semiconductor fin1126has a greater size than the epitaxial feature172over the semiconductor fin112a. In some embodiments, a height of the epitaxial feature174may be greater than a height of the epitaxial feature172. In some embodiments, a top surface of the epitaxial feature174may be higher than a top surface of the epitaxial feature172. The depths of the recesses112arand112brare tuned such that the epitaxial features172and174are merged. In the present embodiments, the fin sidewall spacers162and162′ (referring toFIGS.1-3) may be omitted. Alternatively, in some embodiments, fin sidewall spacers162and/or162′ (referring toFIGS.1-3) may be formed on sidewalls of the epitaxial features172and174. FIG.5is a cross-sectional view of an integrated circuit device100according to some embodiments of the present disclosure. The present embodiments are similar to those shown inFIG.4, and one of the differences between the present embodiments and the embodiments ofFIG.4is that: epitaxial features171-179are respectively on semiconductor fins112a-112iof the semiconductor substrate110, and recesses112r, over the semiconductor fins112b-112d,112g,112hare deeper than the recesses112rover the semiconductor fins112a,112e,112f, and112i. Through the configuration, the epitaxial features172-174,177, and178have a greater size than the epitaxial features171,175,176, and179. In some embodiments, a height of the epitaxial features172-174,177, and178may be greater than a height of the epitaxial features171,175,176, and179. In some embodiments, a top surface of the epitaxial features172-174,177, and178may be higher than a top surface of the epitaxial features171,175,176, and179. The deepness of the recesses112rare tuned such that the epitaxial features171-175are merged, the epitaxial features176-179are merged, and the merged epitaxial features171-175are spaced apart from the merged epitaxial features176-179. Also, in the present embodiments, the fin sidewall spacers162and162′ (referring toFIGS.1-3) may be omitted. Alternatively, in some embodiments, fin sidewall spacers162and/or162′ (referring toFIGS.1-3) may be formed on sidewalls of the epitaxial features171-179. FIGS.6A to14Dillustrate a method for manufacturing an integrated circuit device100at various stages in accordance with some embodiments of the present disclosure. The illustration is merely exemplary and is not intended to be limiting beyond what is specifically recited in the claims that follow. It is understood that additional operations may be provided before, during, and after the operations shown byFIGS.6A to14D, and some of the operations described below can be replaced or eliminated for additional embodiments of the method. The order of the operations/processes may be interchangeable. Reference is made toFIGS.6A and6B.FIG.6Ais a schematic top view of the integrated circuit device at an intermediate stage of the manufacturing method according to some embodiments of the present disclosure.FIG.6Bis a cross-sectional view taken along line B-B ofFIG.6A. A substrate110is illustrated. In some embodiments, the substrate110may be a semiconductor substrate, such as a bulk semiconductor, a semiconductor-on-insulator (SOI) substrate, or the like. The substrate110may be a wafer, such as a silicon wafer. Generally, an SOI substrate comprises a layer of a semiconductor material formed on an insulator layer. The insulator layer may be, for example, a buried oxide (BOX) layer, a silicon oxide layer, or the like. The insulator layer is provided on a substrate, a silicon or glass substrate. For example, the substrate110may include a wafer110a, a semiconductor device layer110bover the wafer110a, and a BOX layer (not shown) between the wafer110aand the semiconductor device layer110b. Other substrates, such as a multi-layered or gradient substrate may also be used. In some embodiments, the semiconductor material of the substrate110may include silicon; germanium; a compound semiconductor including silicon carbide, gallium arsenic, gallium phosphide, indium phosphide, indium arsenide, and/or indium antimonide; an alloy semiconductor including SiGe, GaAsP, AlInAs, AlGaAs, GalnAs, GaInP, and/or GaInAsP; or combinations thereof. A patterned mask P1is formed over the substrate110. The patterned mask P1may be a hard mask for protecting the underlying substrate110against subsequent etching process. The patterned mask P1may be formed by a series of operations including deposition, photolithography patterning, and etching processes. The photolithography patterning processes may include photoresist coating (e.g., spin-on coating), soft baking, mask aligning, exposure, post-exposure baking, developing the photoresist, rinsing, drying (e.g., hard baking), and/or other applicable processes. Reference is made toFIGS.7A and7B.FIG.7Ais a schematic top view of the integrated circuit device at an intermediate stage of the manufacturing method according to some embodiments of the present disclosure.FIG.7Bis a cross-sectional view taken along line B-B ofFIG.7A. In some embodiments, the substrate110is etched through the patterned mask P1(referring toFIGS.6A and6B) to form the trenches T, and portions of the substrate110surrounded by the trenches T can be referred to as semiconductor fins112. The etching processes may include dry etching, wet etching, and/or other etching methods (e.g., reactive ion etching). In some embodiments, plural semiconductor fins112are formed substantially parallel to each other. For better illustration, the semiconductor fins112are respectively labelled as semiconductor fins112a-112bin the figure. Reference is made toFIGS.8A-8C.FIG.8Ais a schematic top view of the integrated circuit device at an intermediate stage of the manufacturing method according to some embodiments of the present disclosure.FIG.8Bis a cross-sectional view taken along line B-B ofFIG.8A.FIG.8Cis a cross-sectional view taken along line C-C ofFIG.8A. Shallow trench isolation (STI) features130are formed interposing the fins112. In the present embodiments, a dielectric layer is deposited over the substrate110and filling the trenches T. In some embodiments, the dielectric layer may include silicon oxide, silicon nitride, silicon oxynitride, fluorine-doped silicate glass (FSG), a low-k dielectric, combinations thereof, and/or other suitable materials. In various examples, the dielectric layer may be deposited by a CVD process, a sub-atmospheric CVD (SACVD) process, a flowable CVD process, an ALD process, a physical vapor deposition (PVD) process, and/or other suitable process. In some embodiments, the dielectric layer may include a multi-layer structure, for example, having one or more liner layers. After deposition of the dielectric layer, the deposited dielectric material is thinned and planarized, for example by a chemical mechanical polishing (CMP) process, thereby forming the STI features130between the fins112. The STI features130may be recessed by suitable etching process, such as a dry etching process, a wet etching process, and/or a combination thereof. The recessing process provides the fins112extending above the STI features130. Reference is made toFIGS.9A-9D.FIG.9Ais a schematic top view of the integrated circuit device at an intermediate stage of the manufacturing method according to some embodiments of the present disclosure.FIG.9Bis a cross-sectional view taken along line B-B ofFIG.9A.FIG.9Cis a cross-sectional view taken along line C-C ofFIG.9A.FIG.9Dis a cross-sectional view taken along line D-D ofFIG.9A. A gate structure DG is formed over a portion of the semiconductor fin112. In some embodiments, the gate structure DG is dummy (sacrificial) gate structures that is subsequently removed. Thus, in some embodiments using a gate-last process, the gate structure DG is dummy gate structure and will be replaced by a final gate structure at a subsequent processing stage. In particular, the dummy gate structure DG may be replaced at a later processing stage by a high-k dielectric layer (HK) and metal gate electrode (MG) as discussed below. In some embodiments, the dummy gate structure DG is formed over the substrate110and is at least partially disposed over the fins112. The portion of the fins112underlying the dummy gate structure DG may be referred to as the channel region. The dummy gate structure DG may also define a source/drain (SID) region of the fins112, for example, the regions of the fin112adjacent and on opposing sides of the channel region. In some embodiments, the dummy gate structure DG is formed by various process steps such as layer deposition, patterning, etching, as well as other suitable processing steps. In the illustrated embodiment, the formation of the gate structure DG first includes depositing a dummy gate dielectric layer142, a dummy gate electrode layer144and a hard mask layer146over the fins112, and then patterning the layers142-146to form the dummy gate structure DG. In some embodiments, the dummy gate dielectric layer142may include SiO2, silicon nitride, a high-k dielectric material and/or other suitable material. In various examples, the dummy gate dielectric layer152may be deposited by a CVD process, a sub-atmospheric CVD (SACVD) process, a flowable CVD process, an ALD process, a PVD process, or other suitable process. By way of example, the dummy gate dielectric layer142may be used to prevent damages to the fins112by subsequent processes (e.g., subsequent formation of the dummy gate structure). In some embodiments, the dummy gate electrode layer144may include polycrystalline silicon (polysilicon). In some embodiments, the hard mask layer146includes an oxide layer such as a pad oxide layer that may include SiO2, and a nitride layer such as a pad nitride layer that may include Si3N4and/or silicon oxynitride. Exemplary layer deposition processes include CVD (including both low-pressure CVD and plasma-enhanced CVD), PVD, ALD, thermal oxidation, e-beam evaporation, or other suitable deposition techniques, or combinations thereof. In forming the gate structure for example, the patterning process includes a lithography process (e.g., photolithography or e-beam lithography) which may further include photoresist coating (e.g., spin-on coating), soft baking, mask aligning, exposure, post-exposure baking, photoresist developing, rinsing, drying (e.g., spin-drying and/or hard baking), other suitable lithography techniques, and/or combinations thereof. In some embodiments, the etching process may include dry etching (e.g., RIE etching), wet etching, and/or other etching methods. In some embodiments, after patterning the dummy gate electrode layer144, the dummy gate dielectric layer142is removed from the S/D regions of the fins112. The etch process may include a wet etch, a dry etch, and/or a combination thereof. The etch process is chosen to selectively etch the dummy gate dielectric layer142without substantially etching the fins112, the dummy gate electrode layer144, and the hard mask146. In some embodiments, gate spacers150are then formed on opposite sidewalls of the dummy gate structure DG. In some embodiments, the gate spacers150may include silicon oxide, silicon nitride, silicon oxynitride, silicon carbide, silicon carbonitride, silicon oxycarbonitride, silicon oxycarbide, porous dielectric materials, hydrogen doped silicon oxycarbide (SiOC:H), low-k dielectric materials or other suitable dielectric material. The gate spacers150may include a single layer or multilayer structure made of different dielectric materials. The method of forming the gate spacers150includes blanket forming a dielectric layer on top surface and sidewalls of the dummy gate structure DG using, for example, CVD, PVD or ALD, and then performing an etching process such as anisotropic etching to remove horizontal portions of the dielectric layer. The remaining portions of the dielectric layer on sidewalls of the dummy gate structure DG can serve as the gate spacers150. In some embodiments, the gate spacers150may be used to offset subsequently formed doped regions, such as source/drain regions. The gate spacers150may further be used for designing or modifying the source/drain region profile. Reference is made toFIG.10.FIG.10is a cross-sectional view of the integrated circuit device at an intermediate stage of the manufacturing method according to some embodiments of the present disclosure, andFIG.10is taken along the same cut as inFIG.9B. A spacer material layer160is conformally deposited over the structure ofFIGS.9A-9D. For example, the spacer material layer160extends over top surfaces of the STI features130, sidewalls of the fins112aand112b, and top surfaces of the fins112aand112b. The spacer material layer160may include a dielectric material such as silicon oxide, silicon nitride, silicon carbide, silicon oxynitride, SiCN films, silicon oxycarbide, SiOCN films, and/or combinations thereof. In some embodiments, the spacer material layer160may include multiple layers, such as main spacer walls, liner layers, and the like. By way of example, the spacer material layer160may be formed by depositing a dielectric material using processes such as, CVD process, a sub-atmospheric CVD (SACVD) process, a flowable CVD process, an ALD process, a PVD process, or other suitable process. In some embodiments, a patterned mask P2is formed over a portion of the spacer material layer160. The patterned mask P2may be a photoresist for protecting the spacer material layer160against subsequent etching process. The patterned mask P2may be formed by photolithography patterning processes, including photoresist coating (e.g., spin-on coating), soft baking, mask aligning, exposure, post-exposure baking, developing the photoresist, rinsing, drying (e.g., hard baking), and/or other applicable processes. In some other embodiments, the patterned mask P2may be a hard mask for protecting the spacer material layer160against subsequent etching process. The hard mask may include Si3N4and/or silicon oxynitride. Reference is made toFIGS.11A-11C.FIG.11Ais a schematic top view of the integrated circuit device at an intermediate stage of the manufacturing method according to some embodiments of the present disclosure.FIG.11Bis a cross-sectional view taken along line B-B ofFIG.11A.FIG.11Cis a cross-sectional view taken along line C-C ofFIG.11A. The spacer material layer160(referring toFIG.10) is patterned to form a spacer161on a sidewall of the fin112afacing the fin112b, and a spacer162on a sidewall of the fin112bfacing the fin112a, thereby exposing portions of the semiconductor fins112aand112b. In other words, the spacers161-162are between the semiconductor fins112aand112b. The patterning includes a suitable etching process. In some embodiments, the etching process includes a dry etching process using an etchant including a fluorine-containing gas, a chlorine-containing gas, other etching gas, or a combination thereof, such as CF4, SF6, NF3, or Cl2. By the etching process, portions of the spacer material layer160(referring toFIG.10) exposed by the patterned mask P2(referring toFIG.10) is etched away, while a portion of the spacer material layer160covered by the patterned mask P2(referring toFIG.10) is protected from being etched. The remaining portion of the spacer material layer160(referring toFIG.10) forms the spacers161-162. In the present embodiments, the remaining portion of the spacer material layer160(referring toFIG.10) further forms a portion169extending horizontally over the STI features130and connecting between the spacers161and162. A combination of the spacers161,162, and the portion169may be referred to as spacer160′. In some other embodiments, the patterned mask P2(referring toFIG.10) may be designed in another way such that the portion169is etched away, and the spacer161may be spaced apart from the spacer162. After the patterning process, the patterned mask P2(referring toFIG.10) may be removed by suitable stripping process. Reference is made toFIGS.12A-12C.FIG.12Ais a schematic top view of the integrated circuit device at an intermediate stage of the manufacturing method according to some embodiments of the present disclosure.FIG.12Bis a cross-sectional view taken along line B-B ofFIG.12A.FIG.12Cis a cross-sectional view taken along line C-C ofFIG.12A. Exposed portions of the semiconductor fins112(e.g., the fins112aand112b) are recessed by suitable etching process by using the dummy gate structure DG, the gate spacers150, and the STI features130as an etch mask, resulting in recesses112rinto the semiconductor fins112. In some embodiments, the etching process may be a dry etching, a wet etch, or the combination thereof. In some embodiments, the etching process includes a dry etching process using an etchant including a halogen-containing compounds or the like. In some embodiments, the etching process may also consume the spacer160′ (referring toFIGS.11A-11C). For example, in some embodiments, the portion169of the spacer160′ (referring toFIGS.11A-11C) may be removed by the etching process, such that the spacer161and162are disconnected from each other. For example, in some embodiments, the etching process may also lower top surfaces of the spacers161and162. Reference is made toFIGS.13A-13C.FIG.13Ais a schematic top view of the integrated circuit device at an intermediate stage of the manufacturing method according to some embodiments of the present disclosure.FIG.13Bis a cross-sectional view taken along line B-B ofFIG.13A.FIG.13Cis a cross-sectional view taken along line C-C ofFIG.13A. Epitaxial features171and172are respectively formed over the exposed portions of the semiconductor fins112aand112b. In some embodiments, the epitaxial features171and172may include Ge, Si, GaAs, AlGaAs, SiGe, GaAsP, SiP, or other suitable material. The epitaxial features171and172may be in-situ doped during the epitaxial process by introducing doping species including: p-type dopants, such as boron or BF2; n-type dopants, such as phosphorus or arsenic; and/or other suitable dopants including combinations thereof. If the epitaxial features171and172are not in-situ doped, an implantation process (i.e., a junction implant process) is performed to dope the epitaxial features171and172. The epitaxial features171and172may be formed by performing an epitaxial growth process that provides an epitaxial material on the fins112. Suitable epitaxial processes include CVD deposition techniques (e.g., vapor-phase epitaxy (VPE) and/or ultra-high vacuum CVD (UHV-CVD)), molecular beam epitaxy, and/or other suitable processes. The epitaxial growth process may use gaseous and/or liquid precursors, which interact with the composition of semiconductor materials of the fins112. In some further embodiments, the epitaxial growths of the epitaxial features171and172are respectively confined by the fin sidewall spacers161and162, thereby preventing the epitaxial features171and172from merging with each other. After the epitaxial growths of the epitaxial features171and172, the fin sidewall spacers161and162are respectively formed on a side of the epitaxial feature171and a side of the epitaxial feature172facing each other. Reference is made toFIGS.14A-14C.FIG.14Ais a schematic top view of the integrated circuit device100according to some embodiments of the present disclosure.FIG.14Bis a cross-sectional view taken along line B-B ofFIG.14A.FIG.14Cis a cross-sectional view taken along line C-C ofFIG.14A.FIG.14Dis a cross-sectional view taken along line C-C ofFIG.14D. An ILD layer180is formed on the substrate110. In some embodiments, the ILD layer180includes materials such as tetraethylorthosilicate (TEOS) oxide, un-doped silicate glass, or doped silicon oxide such as borophosphosilicate glass (BPSG), fused silica glass (FSG), phosphosilicate glass (PSG), boron doped silicon glass (BSG). The ILD layer180may be deposited by a PECVD process or other suitable deposition technique. In some embodiments, a contact etch stop layer (CESL) is also formed prior to forming the ILD layer180. In some examples, the CESL includes a silicon nitride layer, silicon oxide layer, a silicon oxynitride layer, and/or other suitable materials having a different etch selectivity than the ILD layer180. In some embodiments, after formation of the ILD layer180, the integrated circuit device100may be subject to a high thermal budget process to anneal the ILD layer180. In some examples, after depositing the ILD layer180, a planarization process may be performed to remove excessive materials of the ILD layer180. For example, a planarization process includes a chemical mechanical planarization (CMP) process which removes portions of the ILD layer180(and CESL layer, if present) overlying the dummy gate structures DG and planarizes a top surface of the integrated circuit device100. In some embodiments, the CMP process also removes hard mask layers136(as shown inFIGS.13B-13C) and exposes the dummy gate electrode layer144. Subsequently, the dummy gate structure DG is replaced with the metal gate structure190. For example, the dummy gate structure DG is removed by a selective etching process (e.g., selective dry etching, selective wet etching, or a combination thereof) that etches the materials in dummy gate structures DG at a faster etch rate than it etches other materials (e.g., gate spacers150, CESL and/or ILD layer180), thus resulting in a gate trench GT between corresponding gate spacers150. Then, a metal gate structure190is formed in the gate trench GT. The metal gate structure190may be a high-k/metal gate stack, however other compositions are possible. In various embodiments, the metal gate structure190includes an interfacial layer192, a high-k dielectric layer194, a work function metal layer196, and a fill metal198filling a remainder of gate trenches GT. Formation of the high-k/metal gate structures430may include depositions to form various gate materials, one or more liner layers, and one or more CMP processes to remove excessive gate materials. In some embodiments, the interfacial layer192may include a dielectric material such as silicon oxide (SiO2), HfSiO, or silicon oxynitride (SiON). The interfacial layer192may be formed by chemical oxidation, thermal oxidation, atomic layer deposition (ALD), chemical vapor deposition (CVD), and/or other suitable method. The high-k dielectric layer194may include hafnium oxide (HfO2). Alternatively, the high-k dielectric layer194may include other high-k dielectrics, such as hafnium silicon oxide (HfSiO), hafnium silicon oxynitride (HfSiON), hafnium tantalum oxide (HfTaO), hafnium titanium oxide (HfTiO), hafnium zirconium oxide (HfZrO), lanthanum oxide (LaO), zirconium oxide (ZrO), titanium oxide (TiO), tantalum oxide (Ta2O5), yttrium oxide (Y2O3), strontium titanium oxide (SrTiO3, STO), barium titanium oxide (BaTiO3, BTO), barium zirconium oxide (BaZrO), hafnium lanthanum oxide (HfLaO), lanthanum silicon oxide (LaSiO), aluminum silicon oxide (AlSiO), aluminum oxide (Al2O3), silicon nitride (Si3N4), oxynitrides (SiON), and combinations thereof. The work function metal layer196may include work function metals to provide a suitable work function for the high-k/metal gate structures190. For an n-type GAA FET, the work function metal layer196may include one or more n-type work function metals (N-metal). The n-type work function metals may exemplarily include, but are not limited to, titanium aluminide (TiAl), titanium aluminium nitride (TiAlN), carbo-nitride tantalum (TaCN), hafnium (Hf), zirconium (Zr), titanium (Ti), tantalum (Ta), aluminum (Al), metal carbides (e.g., hafnium carbide (HfC), zirconium carbide (ZrC), titanium carbide (TIC), aluminum carbide (AlC)), aluminides, and/or other suitable materials. On the other hand, for a p-type GAA FET, the work function metal layer196may include one or more p-type work function metals (P-metal). The p-type work function metals may exemplarily include, but are not limited to, titanium nitride (TiN), tungsten nitride (WN), tungsten (W), ruthenium (Ru), palladium (Pd), platinum (Pt), cobalt (Co), nickel (Ni), conductive metal oxides, and/or other suitable materials. In some embodiments, the fill metal198may exemplarily include, but are not limited to, tungsten, aluminum, copper, nickel, cobalt, titanium, tantalum, titanium nitride, tantalum nitride, nickel silicide, cobalt silicide, TaC, TaSiN, TaCN, TiAl, TiAlN, or other suitable materials. In some embodiments, contacts210are formed in the ILD layer180and over the epitaxial features171and172. In some embodiments, contact openings are first formed through the ILD layer180to expose the epitaxial features171and172by using suitable photolithography and etching techniques. Subsequently, silicide regions200are formed on the front side of the epitaxial features171and172by using a silicidation process, followed by forming contacts210over the silicide regions200. Silicidation may be formed by depositing a metal layer (e.g., nickel layer or cobalt layer) over the exposed epitaxial features171and172, annealing the metal layer such that the metal layer reacts with silicon (and germanium if present) in the epitaxial features171and172to form the metal silicide region200(e.g., nickel silicide or cobalt silicide), and thereafter removing the non-reacted metal layer. The contact210may be formed by depositing one or more metal materials (e.g., tungsten, cobalt, copper, the like or combinations thereof) to fill the contact holes by using suitable deposition techniques (e.g., CVD, PVD, ALD, the like or combinations thereof), followed by a CMP process to remove excess metal materials outside the contact openings. FIGS.15A to20Dillustrate a method for manufacturing an integrated circuit device100at various stages in accordance with some embodiments of the present disclosure. It is understood that additional operations may be provided before, during, and after the operations shown byFIGS.15A to20D, and some of the operations described below can be replaced or eliminated for additional embodiments of the method. The order of the operations/processes may be interchangeable. Reference is made toFIGS.15A-15C.FIG.15Ais a schematic top view of the integrated circuit device at an intermediate stage of the manufacturing method according to some embodiments of the present disclosure.FIG.15Bis a cross-sectional view taken along line B-B ofFIG.15A.FIG.15Cis a cross-sectional view taken along line C-C ofFIG.15A. STI features130are formed interposing the fins112, and the fins112extend above the STI features130. Dummy gate structure DG are formed over portions of the fins112. For better illustration, the semiconductor fins112are respectively labelled as semiconductor fins112a-112din the present embodiments. In some embodiments, the semiconductor fins112a-112dare equidistantly arranged. For example, a distance between the fins112aand112bis substantially equal to a distance between the semiconductor fins112band112cand a distance between the semiconductor fins112cand112d. Other details for forming the structure ofFIGS.15A-15Care similar to those aforementioned inFIGS.6A-9D, and therefore not repeated herein. Reference is made toFIG.16.FIG.16is a cross-sectional view of the integrated circuit device at an intermediate stage of the manufacturing method according to some embodiments of the present disclosure, andFIG.16is taken along the same cut as inFIG.15B. A spacer material layer160is conformally deposited over the structure ofFIGS.15A-15C. For example, the spacer material layer160extends over top surfaces of the STI features130, sidewalls of the fins112a-112d, and top surfaces of the fins112a-112d. The spacer material layer160may include a dielectric material such as silicon oxide, silicon nitride, silicon carbide, silicon oxynitride, SiCN films, silicon oxycarbide, SiOCN films, and/or combinations thereof. By way of example, the spacer material layer160may be formed by depositing a dielectric material using processes such as, CVD process, a subatmospheric CVD (SACVD) process, a flowable CVD process, an ALD process, a PVD process, or other suitable process. In some embodiments, a patterned mask P2′ is formed over a portion of the spacer material layer160over the fins112band112c, and another portion of the spacer material layer160over the fins112aand112dmay be free of coverage of the patterned mask P2′. The patterned mask P2′ may be a photoresist for protecting the spacer material layer160against subsequent etching process. The patterned mask P2′ may be formed by photolithography patterning processes, including photoresist coating (e.g., spin-on coating), soft baking, mask aligning, exposure, post-exposure baking, developing the photoresist, rinsing, drying (e.g., hard baking), and/or other applicable processes. In some other embodiments, the patterned mask P2′ may be a hard mask for protecting the spacer material layer160against subsequent etching process. Reference is made toFIGS.17A-17C.FIG.17Ais a schematic top view of the integrated circuit device at an intermediate stage of the manufacturing method according to some embodiments of the present disclosure.FIG.17Bis a cross-sectional view taken along line B-B ofFIG.17A.FIG.17Cis a cross-sectional view taken along line C-C ofFIG.17A. The spacer material layer160(referring toFIG.16) is patterned to form spacers161-162on opposite sidewalls of the fin112band spacers163-164on opposite sidewalls of the fin112c. The patterning process may include suitable etching process. By the etching process, the portions of the spacer material layer160free of coverage of the patterned mask P2′ (referring toFIG.16) is removed and etched away, while a portion of the spacer material layer160covered by the patterned mask P2′ (referring toFIG.16) is protected from being etched. The remaining portion of the spacer material layer160(referring toFIG.16) may be referred to as a spacer, which includes the spacers161-164. In the present embodiments, the remaining portion of the spacer material layer160(referring toFIG.16) further forms a portion169extending horizontally over the ST features130and connecting between the spacers162and163. In some other embodiments, the patterned mask P2′ (referring toFIG.16) may be designed in another way such that the portion169is etched away, and the spacer162may be spaced apart from the spacer163. After the patterning process, the patterned mask P2′ (referring toFIG.16) may be removed by suitable stripping process. In the present embodiments, the sidewalls of the fins112aand112dfacing the semiconductor fins112band112emay be free of a fin sidewall spacer. In alternative embodiments, other fin sidewall spacers may be formed on sidewalls of the fins112aand112dfacing the semiconductor fins112band112cwith a top lower than that of the spacers161-164. Reference is made toFIGS.18A-18C.FIG.18Ais a schematic top view of the integrated circuit device at an intermediate stage of the manufacturing method according to some embodiments of the present disclosure.FIG.18Bis a cross-sectional view taken along line B-B ofFIG.18A.FIG.18Cis a cross-sectional view taken along line C-C ofFIG.18A. Exposed portions of the semiconductor fins112are etched by using the dummy gate structure DG, the gate spacers150, and the STI features130as an etch mask, resulting in recesses112rinto the semiconductor fins112. In some embodiments, the etching process may be a dry etching, a wet etch, or the combination thereof. In some embodiments, the portion169(referring toFIG.17B) may be removed by the etching process, such that the spacer162and163are disconnected from each other. In some embodiments, the etching process may also lower top surfaces of the spacer161-164. Reference is made toFIGS.19A-19C.FIG.19Ais a schematic top view of the integrated circuit device at an intermediate stage of the manufacturing method according to some embodiments of the present disclosure.FIG.19Bis a cross-sectional view taken along line B-B ofFIG.19A.FIG.19Cis a cross-sectional view taken along line C-C ofFIG.19A. Epitaxial features171-174are respectively formed over the exposed portions of the semiconductor fins112a-112d. In some embodiments, the epitaxial features171-174may include Ge, Si, GaAs, AlGaAs, SiGe, GaAsP, SiP, or other suitable material. The epitaxial features171-174may be in-situ doped during the epitaxial process by introducing doping species including: p-type dopants, such as boron or BF2; n-type dopants, such as phosphorus or arsenic; and/or other suitable dopants including combinations thereof. If the epitaxial features171-174are not in-situ doped, an implantation process (i.e., a junction implant process) is performed to dope the epitaxial features171-174. The epitaxial features171-174may be formed by performing an epitaxial growth process that provides an epitaxial material on the fins112a-112d. Suitable epitaxial processes include CVD deposition techniques (e.g., vapor-phase epitaxy (VPE) and/or ultra-high vacuum CVD (UHV-CVD)), molecular beam epitaxy, and/or other suitable processes. The epitaxial growth process may use gaseous and/or liquid precursors, which interact with the composition of semiconductor materials of the fins112a-112d. In some further embodiments, the epitaxial growth of the epitaxial feature172is confined by the fin sidewall spacers161and162, and the epitaxial growth of the epitaxial feature173is confined by the fin sidewall spacers163and164. Through the confinement, the epitaxial features172and173are preventing from being merged with each other. In the present embodiments, the epitaxial growth of the epitaxial feature171is less or not confined by a fin sidewall spacer, such that the epitaxial feature171may extend laterally more than the epitaxial feature173extends. Through the configuration, the epitaxial feature172is merged with the epitaxial feature171and spaced apart from the epitaxial feature173. Similarly, in the present embodiments, the epitaxial growth of the epitaxial feature174is less or not confined by a fin sidewall spacer, such that the epitaxial feature174may extend laterally more than the epitaxial feature172extends. Through the configuration, the epitaxial feature173is merged with the epitaxial feature174and spaced apart from the epitaxial feature172. Reference is made toFIGS.20A-20D.FIG.20Ais a schematic top view of the integrated circuit device100according to some embodiments of the present disclosure.FIG.20Bis a cross-sectional view taken along line B-B ofFIG.20A.FIG.20Cis a cross-sectional view taken along line C-C ofFIG.20A.FIG.20Dis a cross-sectional view taken along line D-D ofFIG.20A. An ILD layer180is formed on the substrate110. Subsequently, the dummy gate structure DG (referring toFIG.19A) is replaced with the metal gate structure190. Contacts210are formed in the ILD layer180and over the epitaxial features171-174. Other details of the present embodiments are similar to those mentioned in the embodiments ofFIGS.6A to14D, and therefore not repeated herein. FIG.21is a cross-sectional view of an integrated circuit device100in accordance with some embodiments of the present disclosure, andFIG.21is taken along the same cut as inFIG.20B. The present embodiments are similar to the embodiments ofFIGS.15A to20C, except that the patterning process performed to the spacer material layer160(referring toFIGS.16-17C) further form spacers165-166on opposite sidewalls of the fin112a, and spacers167-168on opposite sidewalls of the fin112d. In some embodiments, the height of the spacers165-168is less than the height of the spacers162and163. For example, top surfaces of the spacers165-168are at a position lower than top surfaces of the spacers162-163. Through the configuration, in the present embodiments, the epitaxial growth of the epitaxial feature171is less confined by the fin sidewall spacers165-166than the epitaxial growth of the epitaxial feature173being confined by the fin sidewall spacers163-164. Therefore, the epitaxial feature171may extend laterally more than the epitaxial feature173extends, which in turn result in that the epitaxial feature172is merged with the epitaxial feature171and spaced apart from the epitaxial feature173. Similarly, in the present embodiments, the epitaxial growth of the epitaxial feature174is less confined by the fin sidewall spacers167-168than the epitaxial growth of the epitaxial feature172being confined by the fin sidewall spacers161-162. Therefore, the epitaxial feature174may extend laterally more than the epitaxial feature172extends, which in turn result in that the epitaxial feature173is merged with the epitaxial feature174and spaced apart from the epitaxial feature172. In some embodiments, the height of the spacers161and164is less than the height of the spacers162and163, for example, being substantially equal to the height of the spacers165-168. For example, top surfaces of the spacers161and164are at a position lower than top surfaces of the spacers162-163, and substantially at the same level as top surfaces of the spacers165-168. The lower spacer161allows the epitaxial feature172to extend laterally toward the epitaxial feature171, which is beneficial for the merge between the epitaxial features171and172. Similarly, the lower spacer164allows the epitaxial feature173to extend laterally toward the epitaxial feature174, which is beneficial for the merge between the epitaxial features173and174. In some alternative embodiments, the height of the spacers161and164is greater than the height of the spacers165-168, for example, being substantially equal to the height of the spacers162and163. For example, top surfaces of the spacers161and164are at a position higher than top surfaces of the spacers165-168, and may be substantially at the same level as top surfaces of the spacers162-163. Other details of the present embodiments is similar to those mentioned above, and therefore not repeated herein. FIGS.22to27Dillustrate a method for manufacturing an integrated circuit device100at various stages in accordance with some embodiments of the present disclosure. It is understood that additional operations may be provided before, during, and after the operations shown byFIGS.22to27D, and some of the operations described below can be replaced or eliminated for additional embodiments of the method. The order of the operations/processes may be interchangeable. Reference is made toFIG.22.FIG.22is a cross-sectional view taken of the integrated circuit device at an intermediate stage of the manufacturing method according to some embodiments of the present disclosure, andFIG.22is taken along the same cut as inFIGS.10and16. A spacer material layer160extends over top surfaces of the STI features130, sidewalls of the fins112a-112d, and top surfaces of the fins112a-112d. Other details regarding the structure ofFIG.22and the method for forming the structure ofFIG.22are similar to those mentioned above (e.g., inFIGS.10and16), and not repeated herein. In some embodiments, a patterned mask P2″ is formed over a portion of the spacer material layer160. The patterned mask P2″ may be a photoresist for protecting the spacer material layer160against subsequent etching process. The patterned mask P2′ may be formed by photolithography patterning processes, including photoresist coating (e.g., spin-on coating), soft baking, mask aligning, exposure, post-exposure baking, developing the photoresist, rinsing, drying (e.g., hard baking), and/or other applicable processes. In some other embodiments, the patterned mask P2″ may be a hard mask for protecting the spacer material layer160against subsequent etching process. Reference is made toFIGS.23A-23C.FIG.23Ais a schematic top view of the integrated circuit device at an intermediate stage of the manufacturing method according to some embodiments of the present disclosure.FIG.23Bis a cross-sectional view taken along line B-B ofFIG.23A.FIG.23Cis a cross-sectional view taken along line C-C ofFIG.23A. The spacer material layer160(referring toFIG.22) is patterned to expose top surfaces of the fins112a-112d. The patterning process may include suitable etching process. By the etching process, portions of the spacer material layer160exposed by the patterned mask P2″ (referring toFIG.22) is etched away, while a portion of the spacer material layer160covered by the patterned mask P2″ (referring toFIG.22) is protected from being etched. The remaining portion of the spacer material layer160(referring toFIG.22) may be referred to as the spacer160′. After the patterning process, the spacer160′ may include spacers161-168, in which the spacers161-162are on opposite sidewalls of the fin112b, the spacers163-164are on opposite sidewalls of the fin112c, the spacers165-166are on opposite sidewalls of the fin112a, and the spacers167-168are on opposite sidewalls of the fin112d. In some embodiments, the spacer160′ further forms horizontal portions169extending horizontally over the ST features130and connecting between the spacers162and163, the spacers166and161, and the spacers164and167. In some other embodiments, the patterned mask P2″ (referring toFIG.22) may be designed in another way such that the horizontal portions169are etched away, which in turn will result in that the spacer162is spaced apart from the spacer163, the spacer166is spaced apart from the spacer161, and the spacer164is spaced apart from the spacer167. After the patterning process, the patterned mask P2″ (referring toFIG.22) may be removed by suitable stripping process. In some other embodiments, the patterning process may include suitable anisotropic etching process without using the patterned mask P2″ (referring toFIG.22) since the anisotropic etching process does not entirely remove the vertical portions the spacer material layer160(referring toFIG.22). Reference is made toFIGS.24A-24C.FIG.24Ais a schematic top view of the integrated circuit device at an intermediate stage of the manufacturing method according to some embodiments of the present disclosure.FIG.24Bis a cross-sectional view taken along line B-B ofFIG.24A.FIG.24Cis a cross-sectional view taken along line C-C ofFIG.24A. Exposed portions of the semiconductor fins112a-112dare etched by using the dummy gate structure DG, the gate spacers150, and the STI features130as an etch mask, resulting in recesses112rinto the semiconductor fins112a-112d. In some embodiments, the etching process may be a dry etching, a wet etch, or the combination thereof. In some embodiments, the horizontal portions169(referring toFIG.23B) may be removed by the etching process, which in turn will result in that the spacer162is spaced apart from the spacer163, the spacer166is spaced apart from the spacer161, and the spacer164is spaced apart from the spacer167. In some embodiments, the etching process may also lower top surfaces of the spacer161-168. After the formation of the recesses112r, a patterned mask P3may be formed over the semiconductor fins112band112cand the spacers161-164, and expose the semiconductor fins112aand112dand the spacers165-168. The patterned mask P3may be a photoresist for protecting the semiconductor fins112band112cagainst subsequent etching process. The patterned mask P3may be formed by photolithography patterning processes, including photoresist coating (e.g., spin-on coating), soft baking, mask aligning, exposure, post-exposure baking, developing the photoresist, rinsing, drying (e.g., hard baking), and/or other applicable processes. In some other embodiments, the patterned mask P3may be a hard mask for protecting the spacers161-164against subsequent etching process. Reference is made toFIGS.25A-25C.FIG.25Ais a schematic top view of the integrated circuit device at an intermediate stage of the manufacturing method according to some embodiments of the present disclosure.FIG.25Bis a cross-sectional view taken along line B-B ofFIG.25A.FIG.25Bis a cross-sectional view taken along line B-B ofFIG.25C. The exposed portions of the semiconductor fins112aand112dare further recessed by suitable etching process, thereby deepening the recesses112r(referring toFIG.24B) in the112aand112d. The deepened recesses112r(referring toFIG.24B) in the fins112aand112dare referred to as recesses112r′ hereinafter. The etching process may use the dummy gate structure DG, the gate spacers150, the STI features130, and the patterned mask P3as an etch mask. In some embodiments, the etching process may be a dry etching, a wet etch, or the combination thereof. In some embodiments, the spacers165-168may be etched and/or removed by the etching process. Through the recessing portions of the semiconductor fins112aand112d, a top surface of the recessed portions of the semiconductor fins112aand112dis lower than a top surface of recessed portions of the second semiconductor fins112band112c. In some other embodiments, the patterned mask P3(referring toFIG.24B) may be formed over the semiconductor fins112band112cand the spacers162and163, and expose the semiconductor fins112aand112dand the spacers161and164-168. In some other embodiments, the spacers161and164-168may be etched and/or removed by the etching process. Reference is made toFIGS.26A-26C.FIG.26Ais a schematic top view of the integrated circuit device at an intermediate stage of the manufacturing method according to some embodiments of the present disclosure.FIG.26Bis a cross-sectional view taken along line B-B ofFIG.26A.FIG.26Cis a cross-sectional view taken along line C-C ofFIG.26A. Epitaxial features171-174are respectively formed over the exposed portions of the semiconductor fins112a-112d. In some embodiments, the epitaxial features171-174may include Ge, Si, GaAs, AlGaAs, SiGe, GaAsP, SiP, or other suitable material. The epitaxial features171-174may be in-situ doped during the epitaxial process by introducing doping species including: p-type dopants, such as boron or BF2; n-type dopants, such as phosphorus or arsenic; and/or other suitable dopants including combinations thereof. If the epitaxial features171-174are not in-situ doped, an implantation process (i.e., a junction implant process) is performed to dope the epitaxial features171-174. The epitaxial features171-174may be formed by performing an epitaxial growth process that provides an epitaxial material on the fins112a-112d. Suitable epitaxial processes include CVD deposition techniques (e.g., vapor-phase epitaxy (VPE) and/or ultra-high vacuum CVD (UHV-CVD)), molecular beam epitaxy, and/or other suitable processes. The epitaxial growth process may use gaseous and/or liquid precursors, which interact with the composition of semiconductor materials of the fins112a-112d. In the present embodiments, since the recesses112r′ is deeper than the recess112r, sizes of the epitaxial features171and174grown from the recess112r′ are greater than sizes of the epitaxial features172and173grown from the recess112r. For example, widths and heights of the epitaxial features171and174are greater than widths and heights of the epitaxial features172and173, respectively. In some other embodiments, top surfaces of the epitaxial features171and174may be higher than top surfaces of the epitaxial features172and173. Through the configuration, the epitaxial feature172is merged with the epitaxial feature171and spaced apart from the epitaxial feature173, and the epitaxial feature173is merged with the epitaxial feature174and spaced apart from the epitaxial feature172. In some embodiments, the epitaxial growth of the epitaxial feature172is confined by the fin sidewall spacers161and162, and the epitaxial growth of the epitaxial feature173is confined by the fin sidewall spacers163and164. Through the confinement, the epitaxial features172and173are preventing from being merged with each other. In some embodiments, the epitaxial growth of the epitaxial feature171is less or not confined by a fin sidewall spacer, such that the epitaxial feature171may extend laterally more than the epitaxial feature173extends. Through the configuration, the epitaxial feature172is merged with the epitaxial feature171and spaced apart from the epitaxial feature173. Similarly, in the present embodiments, the epitaxial growth of the epitaxial feature174is less or not confined by a fin sidewall spacer, such that the epitaxial feature174may extend laterally more than the epitaxial feature172extends. Through the configuration, the epitaxial feature173is merged with the epitaxial feature174and spaced apart from the epitaxial feature172. Reference is made toFIGS.27A-27D.FIG.27Ais a schematic top view of the integrated circuit device100according to some embodiments of the present disclosure.FIG.27Bis a cross-sectional view taken along line B-B ofFIG.27A.FIG.27Cis a cross-sectional view taken along line C-C ofFIG.27A.FIG.27Dis a cross-sectional view taken along line D-D ofFIG.27A. An ILD layer180is formed on the substrate110. Subsequently, the dummy gate structure DG is replaced with the metal gate structure190. Contacts210are formed in the ILD layer180and over the epitaxial features171-174. Other details of the present embodiments are similar to those mentioned above, and therefore not repeated herein. FIG.28is a cross-sectional view of an integrated circuit device in accordance with some embodiments of the present disclosure, andFIG.28is taken along the same cut as inFIG.27B. The present embodiments are similar to the embodiments ofFIGS.22to27D, except that the etching process performed for deepening the recess112r(referring toFIGS.24A-25C) does not fully consume the spacers165and166on opposite sidewalls of the fin112aand spacers167and168on opposite sidewalls of the fin112d, For example, in the present embodiments, the spacers165-168remains on the sidewalls of the fins112aand112d. In some embodiments, the etching process performed for deepening the recess112r(referring toFIGS.24A-25C) may partially consume the spacers165-168, thereby lowering tops of the spacers165-168. For example, the tops of the spacers165-168are at a position lower than tops of the spacers162and163. In some embodiments, the height of the spacers165-168is less than the height of the spacers162and163. In the present embodiments, the epitaxial growth of the epitaxial feature171is less confined by the fin sidewall spacers165-166than the epitaxial growth of the epitaxial feature173being confined by the fin sidewall spacers163-164. Therefore, the epitaxial feature171may extend laterally more than the epitaxial feature173extends. Through the configuration, the epitaxial feature172is merged with the epitaxial feature171and spaced apart from the epitaxial feature173. Similarly, in the present embodiments, the epitaxial growth of the epitaxial feature174is less confined by the fin sidewall spacers167-168than the epitaxial growth of the epitaxial feature172being confined by the fin sidewall spacers161-162. Therefore, the epitaxial feature174may extend laterally more than the epitaxial feature172extends. Through the configuration, the epitaxial feature173is merged with the epitaxial feature174and spaced apart from the epitaxial feature172. Other details of the present embodiments are similar to those mentioned above, and therefore not repeated herein. Based on the above discussions, it can be seen that the present disclosure offers advantages. It is understood, however, that other embodiments may offer additional advantages, and not all advantages are necessarily disclosed herein, and that no particular advantage is required for all embodiments. One advantage is that through the configuration of fin sidewall spacers, the profile of the epitaxial features can be adjusted free from pitch limit, such that an epitaxial feature can be prevented from merging with an adjacent epitaxial feature. Another advantage is that the profile of an epitaxial feature can be asymmetric for merging with an adjacent epitaxial feature and spaced apart from another adjacent epitaxial feature. Still another advantage is that depths of recesses in fins would influence the size of the epitaxial features, such that a epitaxial feature cane be merged with an adjacent epitaxial feature and spaced apart from another adjacent epitaxial feature. According to some embodiments, a method for manufacturing an integrated circuit device is provided. The method includes forming first, second, and third semiconductor fins over a semiconductor substrate, in which the second semiconductor fin is between the first and third semiconductor fins; forming first and second fin sidewall spacers respectively on a sidewall of a first portion of the first semiconductor fin and a sidewall of a first portion of the second semiconductor fin, wherein the first and second fin sidewall spacers are between the first and second semiconductor fins; recessing the first portions of the first and second semiconductor fins and a first portion of the third semiconductor fin; and forming first to third epitaxial features respectively on the recessed portions of the first to third semiconductor fins, wherein the second epitaxial feature is spaced apart from the first epitaxial feature and merged with the third epitaxial feature. According to some embodiments, a method for manufacturing an integrated circuit device is provided. The method includes forming a first semiconductor fin and a second semiconductor fin over a semiconductor substrate; recessing a first portion of the first semiconductor fin such that a top surface of the recessed first portion of the first semiconductor fin is lower than a top surface of a first portion of the second semiconductor fin; and forming a first epitaxial feature on the recessed first portion of the first semiconductor fin and a second epitaxial feature on the first portion of the second semiconductor fin, such that a size of the first epitaxial feature is greater than a size of the second epitaxial feature. According to some embodiments, an integrated circuit device includes first to third semiconductor fins and first to third epitaxy structures. The second semiconductor fin is between the first and third semiconductor fins. The first to third epitaxy structures are respectively on the first to third semiconductor fins. The second epitaxy structure is spaced apart from the first epitaxy structure, and the second epitaxy structure is merged with the third epitaxy structure. The foregoing outlines features of several embodiments so that those skilled in the art may better understand the aspects of the present disclosure. Those skilled in the art should appreciate that they may readily use the present disclosure as a basis for designing or modifying other processes and structures for carrying out the same purposes and/or achieving the same advantages of the embodiments introduced herein. Those skilled in the art should also realize that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and that they may make various changes, substitutions, and alterations herein without departing from the spirit and scope of the present disclosure. | 63,428 |
11862520 | DETAILED DESCRIPTION Described herein are technologies directed to systems and methods for predicting film thickness of individual layers using virtual metrology. A film can be deposited on a surface of a substrate during a deposition process performed at a process chamber of a manufacturing system. For example, in a chemical vapor deposition (CVD) process, the substrate is exposed to one or more precursors, which react on the substrate surface to produce the desired deposit. The film can include one or more layers of materials (hereafter “film stack”) that are formed during the deposition process, and each layer can include a particular thickness gradient (e.g., changes in the thickness along a layer of the deposited film). For example, a first layer can be formed directly on the surface of the substrate (referred to as a proximal layer or proximal end of the film) and have a first thickness. After the first layer is formed on the surface of the substrate, a second layer having a second thickness can be formed on the first layer. This process continues until the deposition process is completed and a final layer is formed for the film (referred to as the distal layer or distal end of the film). The film stack can include alternating layers of different materials. For example, a film stack can include alternating layers of oxide and nitride layers (oxide-nitride-oxide-nitride stack or ONON stack), alternating oxide and polysilicon layers (oxide-polysilicon-oxide-polysilicon stack or OPOP stack), and so forth. In some existing systems, metrology measurements are performed on substrates of a batch to generate metrology data, such as thickness data. For example, metrology equipment can analyze a substrate to determine the thickness of each layer in the film stack. Using the metrology data, the systems can perform quality control by adjusting a deposition rate of one or more layers to decrease defects and improve layer uniformity. This is important because a defect or small variation in layer thickness can result in a large deviation at the top of a film stack. However, existing systems cannot measure the thickness of individual layers on the substrate until the film stack is completed, and not without using destructive testing processes to obtain metrology data for each layer in the film stack. Aspects and implementations of the present disclosure address these and other shortcoming of existing technology by training a machine-learning model capable of generating predictive metrology data for each layer in a film stack. In some embodiments, the machine-learning model can be generated based on training data, which includes data from one or more sensors mapped to film thickness data. The film thickness data can include measured thickness values obtained from measuring individual layers of material produced by the manufacturing equipment or measured thickness values obtained from measuring film stacks produced by the manufacturing equipment. In some embodiments, the film thickness data can be generated using reflectometry techniques, ellipsometry techniques, a TEM analysis, or any other measurement techniques. In some embodiments, the machine-learning model can be calibrated using measured metrology data. In some embodiments, the system of the present disclosure can generate different trained machine-learning models for each type of material used in a film stack. For example, the present system can train a first machine-learning model to generate predictive metrology data used to predict the thickness of each oxide layer in an ONON stack generated by a process chamber, and train a second machine-learning model to generate predictive metrology data used to predict the thickness of each nitride layer in the ONON stack. The predictive metrology data can include a contour map (e.g., a vector map) including a set of spatial measurements (e.g., a set of vectors), each indicating a thickness of a particular location of a plurality of locations on each layer. In some embodiments, the predictive metrology data can be compared to actual (measured) metrology data of the substrate, which can be used to update or calibrate the machine-learning models. In one example, the trained machine-learning model can be calibrated based on the predictive metrology data and the measured mass of the film stack. In another example, the trained machine-learning model can be calibrated based on the predictive metrology data and the measured thickness of the film stack. Aspects of the present disclosure result in technological advantages of significant reduction in time required to achieve optimal settings during manufacturing of substrates, as well as improvements in energy consumption, and so forth. The disclosed technology results in reduced time requirements and eliminates using destructive techniques to measure individual layer thickness in film stacks by training one or more machine-learning models which can be used to obtain predictive data, detect excursions early during manufacturing of a film stack, and cause performance of corrective actions based on the predictive data. The disclosed technology can result in predicting metrology data for layers in real-time or near real-time to avoid inconsistent and abnormal products, unscheduled user time, and unnecessary metrology measurements. FIG.1depicts an illustrative computer system architecture100, according to aspects of the present disclosure. In some embodiments, computer system architecture100can be included as part of a manufacturing system for processing substrates, such as manufacturing system300ofFIG.3. Computer system architecture100includes a client device120, manufacturing equipment124, metrology equipment128, a predictive server112(e.g., to generate predictive data, to provide model adaptation, to use a knowledge base, etc.), and a data store140. The predictive server112can be part of a predictive system110. The predictive system110can further include server machines170and180. The manufacturing equipment124can include sensors126configured to capture data for a substrate being processed at the manufacturing system. In some embodiments, the manufacturing equipment124and sensors126can be part of a sensor system that includes a sensor server (e.g., field service server (FSS) at a manufacturing facility) and sensor identifier reader (e.g., front opening unified pod (FOUP) radio frequency identification (RFID) reader for sensor system). In some embodiments, metrology equipment128can be part of a metrology system that includes a metrology server (e.g., a metrology database, metrology folders, etc.) and metrology identifier reader (e.g., FOUP RFID reader for metrology system). Manufacturing equipment124can produce products, such as electronic devices, following a recipe or performing runs over a period of time. Manufacturing equipment124can include a process chamber, such as process chamber400described with respect toFIG.4. Manufacturing equipment124can perform a process for a substrate (e.g., a wafer, etc.) at the process chamber. Examples of substrate processes include a deposition process to deposit one or more layers of film on a surface of the substrate, an etch process to form a pattern on the surface of the substrate, etc. Manufacturing equipment124can perform each process according to a process recipe. A process recipe defines a particular set of operations to be performed for the substrate during the process and can include one or more settings associated with each operation. For example, a deposition process recipe can include a temperature setting for the process chamber, a pressure setting for the process chamber, a flow rate setting for a precursor for a material included in the film deposited on the substrate surface, etc. In some embodiments, manufacturing equipment124can include sensors126that are configured to generate data associated with a substrate processed at manufacturing system100. For example, a process chamber can include one or more sensors configured to generate spectral or non-spectral data associated with the substrate before, during, and/or after a process (e.g., a deposition process) is performed for the substrate. In some embodiments, spectral data generated by sensors126can indicate a concentration of one or more materials deposited on a surface of a substrate. Sensors126configured to generate spectral data associated with a substrate can include reflectometry sensors, ellipsometry sensors, thermal spectra sensors, capacitive sensors, and so forth. Sensors126configured to generate non-spectral data associated with a substrate can include temperature sensors, pressure sensors, flow rate sensors, voltage sensors, etc. Further details regarding manufacturing equipment124are provided with respect toFIG.3andFIG.4. In some embodiments, sensors126can provide sensor data (e.g., sensor values, features, trace data) associated with manufacturing equipment124(e.g., associated with producing, by manufacturing equipment124, corresponding products, such as wafers). The manufacturing equipment124may produce products following a recipe or performing runs over a period of time. Sensor data received over a period of time (e.g., corresponding to at least part of a recipe or run) may be referred to as trace data (e.g., historical trace data, current trace data, etc.) received from different sensors126over time. Sensor data can include a value of one or more of temperature (e.g., heater temperature), spacing (SP), pressure, high frequency radio frequency (HFRF), voltage of electrostatic chuck (ESC), electrical current, material flow, power, voltage, etc. Sensor data can be associated with or indicative of manufacturing parameters such as hardware parameters, such as settings or components (e.g., size, type, etc.) of the manufacturing equipment124, or process parameters of the manufacturing equipment124. The sensor data can be provided while the manufacturing equipment124is performing manufacturing processes (e.g., equipment readings when processing products). The sensor data can be different for each substrate. Metrology equipment128can provide metrology data associated with substrates processed by manufacturing equipment124. The metrology data can include a value of film property data (e.g., wafer spatial film properties), dimensions (e.g., thickness, height, etc.), dielectric constant, dopant concentration, density, defects, etc. In some embodiments, the metrology data can further include a value of one or more surface profile property data (e.g., an etch rate, an etch rate uniformity, a critical dimension of one or more features included on a surface of the substrate, a critical dimension uniformity across the surface of the substrate, an edge placement error, etc.). The metrology data can be of a finished or semi-finished product. The metrology data can be different for each substrate. Metrology data can be generated using, for example, reflectometry techniques, ellipsometry techniques, TEM techniques, and so forth. In some embodiments, metrology equipment128can be included as part of the manufacturing equipment124. For example, metrology equipment128can be included inside of or coupled to a process chamber and configured to generate metrology data for a substrate before, during, and/or after a process (e.g., a deposition process, an etch process, etc.) while the substrate remains in the process chamber. In such instances, metrology equipment128can be referred to as in-situ metrology equipment. In another example, metrology equipment128can be coupled to another station of manufacturing equipment124. For example, metrology equipment can be coupled to a transfer chamber, such as transfer chamber310ofFIG.3, a load lock, such as load lock320, or a factory interface, such as factory interface306. In such instances, metrology equipment128can be referred to as integrated metrology equipment. In other or similar embodiments, metrology equipment128is not coupled to a station of manufacturing equipment124. In such instances, metrology equipment128can be referred to as inline metrology equipment or external metrology equipment. In some embodiments, integrated metrology equipment and/or inline metrology equipment are configured to generate metrology data for a substrate before and/or after a process. The client device120my include a computing device such as personal computers (PCs), laptops, mobile phones, smart phones, tablet computers, netbook computers, network connected televisions (“smart TVs”), network-connected media players (e.g., Blu-ray player), a set-top box, over-the-top (OTT) streaming devices, operator boxes, etc. In some embodiments, the metrology data can be received from the client device120. Client device120can display a graphical user interface (GUI), where the GUI enables the user to provide, as input, metrology measurement values for substrates processed at the manufacturing system. The client device120can include a corrective action component122. Corrective action component122can receive user input (e.g., via a Graphical User Interface (GUI) displayed via the client device120) of an indication associated with manufacturing equipment124. In some embodiments, the corrective action component122transmits the indication to the predictive system110, receives output (e.g., predictive data) from the predictive system110, determines a corrective action based on the output, and causes the corrective action to be implemented. In some embodiments, the corrective action component122receives an indication of a corrective action from the predictive system110and causes the corrective action to be implemented. Each client device120may include an operating system that allows users to one or more of generate, view, or edit data (e.g., indication associated with manufacturing equipment124, corrective actions associated with manufacturing equipment124, etc.) Data store140can be a memory (e.g., random access memory), a drive (e.g., a hard drive, a flash drive), a database system, or another type of component or device capable of storing data. Data store140can include multiple storage components (e.g., multiple drives or multiple databases) that can span multiple computing devices (e.g., multiple server computers). The data store140can store data associated with processing a substrate at manufacturing equipment124. For example, data store140can store data collected by sensors126at manufacturing equipment124before, during, or after a substrate process (referred to as process data). Process data can refer to historical process data (e.g., process data generated for a prior substrate processed at the manufacturing system) and/or current process data (e.g., process data generated for a current substrate processed at the manufacturing system). Data store can also store spectral data or non-spectral data associated with a portion of a substrate processed at manufacturing equipment124. Spectral data can include historical spectral data and/or current spectral data. In some embodiments, data store140can also store film thickness data associated with one or more layers deposited on a surface of a substrate. Film thickness data refers to a particular thickness gradient of the deposited film (e.g., changes in the thickness along a layer of deposited film). In some embodiments, film thickness data can include a thickness value of a film stack (e.g., multiple layers of one or more materials) deposited on a surface of a substrate (e.g., as determined by metrology inspection or as determined by prediction). For example, the film thickness data can include a thickness value(s) of an ONON stack, an OPOP stack, an aggregated stack (e.g., an aggregated oxide stack, an aggregated nitride stack, an aggregated polysilicon stack etc.), or any other film stack generated by the manufacturing equipment124. An aggregated stack can include thickness data associated with layers of a single material from a film stack having multiple layers of different materials. For example, from an ONON stack, an aggregated oxide stack can include thickness data from only the oxide layers, and an aggregated nitride stack can include thickness data from only the nitride layers. In some embodiments, one or more film stacks can be generated in a test production run for training machine-learning model190(e.g., for use by the training set generator172and/or training engine182), which will be explained in greater detail below. In some embodiments, film thickness data can include thickness values of individual layers deposited on a surface of a substrate (e.g., as determined by metrology inspection or as determined by prediction). For example, the film thickness data can include a thickness value(s) one or more layers of an ONON stack, one or more layers of an OPOP stack, one or more layers of an aggregated oxide stack, one or more layers of an aggregated nitride stack, one or more layers of an aggregated polysilicon stack, or any other layer(s) generated by the manufacturing equipment124. In some embodiments, one or more layers can be generated in a test production run for training machine-learning model190. In some embodiments, film thickness data can be provided by a user (e.g., an operator) of the manufacturing system (e.g., via client device120). In other or similar embodiments, film thickness data can be determined by a processing device of the manufacturing system, (e.g., system controller328ofFIG.3) based on sensor data and/or metrology data stored at the data store140. Film thickness data can refer to historical thickness data (e.g., film thickness data for a prior film deposited on a prior substrate) or current thickness data (e.g., film thickness data for a current film deposited on a current substrate). In some embodiments, film thickness data can also include data associated with a target thickness for a film to be deposited on a surface of a substrate. For example, a user of the operating system (e.g., an operator) can provide data associated with a target film thickness via client device120. The data associated with the target film thickness can include at least of a target thickness of the film to be deposited on the surface of the substrate, a target initial thickness of a particular material of the film (e.g., a thickness of the particular material at a proximal layer of the film, and a target final thickness of the particular material of the film (e.g., a thickness of the particular material at the distal layer of the film). In some embodiments, the data associated with the target thickness can also include an indication of a target rate of change (e.g., linear, non-linear, etc.) of the thickness gradient for the particular material within the layers between the proximal and distal layers of the film. The data store140can also store contextual data associated with one or more substrates processed at the manufacturing system. Contextual data can include a recipe name, recipe step number, preventive maintenance indicator, operator, etc. Contextual data can refer to historical contextual data (e.g., contextual data associated with a prior process performed for a prior substrate) and/or current process data (e.g., contextual data associated with current process or a future process to be performed for a prior substrate). In some embodiments, contextual data can also include an indication of one or more settings associated with a particular process. For example, contextual data for a deposition process can include a temperature setting for a process chamber, a pressure setting for a process chamber, a flow rate setting for a precursor for a material of a film deposited on a substrate, etc. In some embodiments, data store140can be configured to store data that is not accessible to a user of the manufacturing system. For example, process data, spectral data, contextual data, etc. obtained for a substrate being processed at the manufacturing system is not accessible to a user (e.g., an operator) of the manufacturing system. In some embodiments, all data stored at data store140can be inaccessible by the user of the manufacturing system. In other or similar embodiments, a portion of data stored at data store140can be inaccessible by the user while another portion of data stored at data store140can be accessible by the user. In some embodiments, one or more portions of data stored at data store140can be encrypted using an encryption mechanism that is unknown to the user (e.g., data is encrypted using a private encryption key). In other or similar embodiments, data store140can include multiple data stores where data that is inaccessible to the user is stored in one or more first data stores and data that is accessible to the user is stored in one or more second data stores. In some embodiments, predictive system110includes predictive server112, server machine170and server machine180. The predictive server112, server machine170, and server machine180may each include one or more computing devices such as a rackmount server, a router computer, a server computer, a personal computer, a mainframe computer, a laptop computer, a tablet computer, a desktop computer, Graphics Processing Unit (GPU), accelerator Application-Specific Integrated Circuit (ASIC) (e.g., Tensor Processing Unit (TPU)), etc. Server machine170includes a training set generator172that is capable of generating training data sets (e.g., a set of data inputs and a set of target outputs) to train, validate, and/or test a machine-learning model190. Machine-learning model190can be any algorithmic model capable of learning from data. Some operations of data set generator172is described in detail below with respect toFIG.2. In some embodiments, the data set generator172can partition the training data into a training set, a validating set, and a testing set. In some embodiments, the predictive system110generates multiple sets of training data. Server machine180can include a training engine182, a validation engine184, a selection engine185, and/or a testing engine186. An engine can refer to hardware (e.g., circuitry, dedicated logic, programmable logic, microcode, processing device, etc.), software (such as instructions run on a processing device, a general purpose computer system, or a dedicated machine), firmware, microcode, or a combination thereof. Training engine182can be capable of training one or more machine-learning models190. Machine-learning model190can refer to the model artifact that is created by the training engine182using the training data (also referred to herein as a training set) that includes training inputs and corresponding target outputs (correct answers for respective training inputs). The training engine182can find patterns in the training data that map the training input to the target output (the answer to be predicted), and provide the machine-learning model190that captures these patterns. The machine-learning model190can use one or more of a statistical modelling, support vector machine (SVM), Radial Basis Function (RBF), clustering, supervised machine-learning, semi-supervised machine-learning, unsupervised machine-learning, k-nearest neighbor algorithm (k-NN), linear regression, random forest, neural network (e.g., artificial neural network), etc. The validation engine184can be capable of validating machine-learning model190using a corresponding set of features of a validation set from training set generator172. The validation engine184can determine an accuracy of machine-learning model190based on the corresponding sets of features of the validation set. The validation engine184can discard a trained machine-learning model190that has an accuracy that does not meet a threshold accuracy. In some embodiments, the selection engine185can be capable of selecting a trained machine-learning model190that has an accuracy that meets a threshold accuracy. In some embodiments, the selection engine185can be capable of selecting the trained machine-learning model190that has the highest accuracy of the trained machine-learning models190. The testing engine186can be capable of testing a trained machine-learning model190using a corresponding set of features of a testing set from data set generator172. For example, a first trained machine-learning model190that was trained using a first set of features of the training set can be tested using the first set of features of the testing set. The testing engine186can determine a trained machine-learning model190that has the highest accuracy of all of the trained machine-learning models based on the testing sets. As described in detail below, predictive server112includes a predictive component114that is capable of providing data associated with film thickness data for one or more layers of film deposited on a surface of a substrate during a deposition process for the substrate, and running trained machine-learning model190on the input to obtain one or more outputs. The predictive server112can further provide metrology predictions of each layer of a film stack produced during deposition process. This will be explained in further detail below. The client device120, manufacturing equipment124, sensors126, metrology equipment128, predictive server112, data store140, server machine170, and server machine180can be coupled to each other via a network130. In some embodiments, network130is a public network that provides client device120with access to predictive server112, data store140, and other publically available computing devices. In some embodiments, network130is a private network that provides client device120access to manufacturing equipment124, metrology equipment128, data store140, and other privately available computing devices. Network130can include one or more wide area networks (WANs), local area networks (LANs), wired networks (e.g., Ethernet network), wireless networks (e.g., an 802.11 network or a Wi-Fi network), cellular networks (e.g., a Long Term Evolution (LTE) network), routers, hubs, switches, server computers, cloud computing networks, and/or a combination thereof. It should be noted that in some other implementations, the functions of server machines170and180, as well as predictive server112, can be provided by a fewer number of machines. For example, in some embodiments, server machines170and180can be integrated into a single machine, while in some other or similar embodiments, server machines170and180, as well as predictive server112, can be integrated into a single machine. In general, functions described in one implementation as being performed by server machine170, server machine180, and/or predictive server112can also be performed on client device120. In addition, the functionality attributed to a particular component can be performed by different or multiple components operating together. In embodiments, a “user” can be represented as a single individual. However, other embodiments of the disclosure encompass a “user” being an entity controlled by a plurality of users and/or an automated source. For example, a set of individual users federated as a group of administrators can be considered a “user.” FIG.2is a flow chart of a method200for training a machine-learning model, according to aspects of the present disclosure. Method200is performed by processing logic that can include hardware (circuitry, dedicated logic, etc.), software (such as is run on a general purpose computer system or a dedicated machine), firmware, or some combination thereof. In one implementation, method200can be performed by a computer system, such as computer system architecture100ofFIG.1. In other or similar implementations, one or more operations of method200can be performed by one or more other machines not depicted in the figures. In some aspects, one or more operations of method200can be performed by server machine170, server machine180, and/or predictive server112. For simplicity of explanation, the methods are depicted and described as a series of acts. However, acts in accordance with this disclosure can occur in various orders and/or concurrently, and with other acts not presented and described herein. Furthermore, not all illustrated acts can be performed to implement the methods in accordance with the disclosed subject matter. In addition, those skilled in the art will understand and appreciate that the methods could alternatively be represented as a series of interrelated states via a state diagram or events. Additionally, it should be appreciated that the methods disclosed in this specification are capable of being stored on an article of manufacture to facilitate transporting and transferring such methods to computing devices. The term article of manufacture, as used herein, is intended to encompass a computer program accessible from any computer-readable device or storage media. At block210, processing logic initializes a training set T to an empty set (e.g., { }). At block212, processing logic obtains sensor data (e.g., sensor values, features, trace data) associated with a prior deposition process performed to deposit one or more layers of film on a surface of a prior substrate. In some embodiments, the sensor data associated with the deposition process is historical data associated with one or more prior deposition settings for a prior deposition process previously performed for a prior substrate at a manufacturing system. For example, the historical data can be historical contextual data associated with the prior deposition process stored at data store140. In some embodiments, the one or more prior deposition settings can include at least one of a prior temperature setting for the prior deposition process, a prior pressure setting for the prior deposition setting, a prior flow rate setting for a precursor for one or more material of the prior film deposited on the surface of the prior substrate, or any other setting associated with the deposition process. A flow rate setting can refer to a flow rate setting for the precursor at an initial instance of the prior deposition process (referred to as an initial flow rate setting), a flow rate setting for the precursor at a final instance of the prior deposition process (referred to as a final flow rate setting), or a ramping rate for the flow rate of the precursor during the deposition process. In one example, the precursor for the prior film can include a boron-containing precursor or a silicon-containing precursor. At block214, processing logic obtains film thickness data associated with the film deposited on the surface of the prior substrate. As discussed previously, film thickness data refers to a thickness measurement of individual film layer(s), total film stack(s), and/or aggregated layer stack(s). Film thickness data can include historical film thickness data for a prior film deposited on a surface of a prior substrate. In some embodiments, the historical film thickness data for the prior film can correspond to a historical metrology measurement value associated with the prior film. Processing logic can obtain the film thickness data associated with the deposited film from data store140, in accordance with previously described embodiments. At block216, processing logic generates first training data based on the obtained data associated with the prior deposition process performed for the prior substrate. At block218, processing logic generates second training data based on the film thickness data associated with the film deposited on the surface of the prior substrate. For example, the second training data can be associated with a thickness measurement(s) of a film layer(s), a total film stack, and/or an aggregated layer stack. At block220, processing logic generates a mapping between the first training data and the second training data. The mapping refers to the first training data that includes or is based on data for the prior deposition process performed for the prior substrate and the second training data that includes or is based on film thickness data associated with the film deposited on the surface of the prior substrate, where the first training data is associated with (or mapped to) the second training data. At block224, processing logic adds the mapping to the training set T. At block226, processing logic determines whether the training set, T, includes a sufficient amount of training data to train a machine-learning model. It should be noted that in some implementations, the sufficiency of training set T can be determined based simply on the number of mappings in the training set, while in some other implementations, the sufficiency of training set T can be determined based on one or more other criteria (e.g., a measure of diversity of the training examples, etc.) in addition to, or instead of, the number of input/output mappings. Responsive to determining the training set does not include a sufficient amount of training data to train the machine-learning model, method200returns to block212. Responsive to determining the training set, T, includes a sufficient amount of training data to train the machine-learning model, method200continues to block228. At block228, processing logic provides the training set T to train the machine-learning model. In one implementation, the training set T is provided to training engine182of server machine180to perform the training. In the case of a neural network, for example, input values of a given input/output mapping are input to the neural network, and output values of the input/output mapping are stored in the output nodes of the neural network. The connection weights in the neural network are then adjusted in accordance with a learning algorithm (e.g., backpropagation, etc.), and the procedure is repeated for the other input/output mappings in the training set T. In some embodiments, method200can be used to train multiple machine-learning models for predicting the thickness of layers of different types of material from the same film stack. For example, method200can be used to train a first machine-learning model (hereafter “oxide model) for predicting the thickness of oxide layers in an ONON stack, and a second machine-learning model (hereafter “nitride model”) for predicting the thickness of nitride layers in the ONON stack. The machine-learning models can then be used to predict, for a deposition process performed for a current substrate, the thickness of each alternating film layer deposited on a surface of the current substrate. At block230, processing logic perform a calibration process on the trained machine-learning model. In some embodiments, the processing logic can compare the predictive metrology data to actual (measured) metrology data, and adjust the trained machine-learning model based on the differences in values between the predictive metrology data and the actual metrology data. In one example, the processing logic can compare the predictive thickness data generated by the oxide model to the measured thickness of the aggregated oxide stack. Based on the difference in thickness values, the processing logic can further train or refine the machine-learning model. In another example, the processing logic can compare predictive mass data of the oxide layers, determined from the predictive thickness data generated by the oxide model, to the measured mass of the aggregated oxide stack. Based on the difference in mass values, the processing logic can further train or refine the machine-learning model. In other examples, the processing logic can compare any predictive metrology data to any actual metrology data to further train or refine the trained machine-learning model. After block230, machine-learning model190can be used to predict, for a deposition process performed for a current substrate, the thickness of one or more layers deposited on a surface of the current substrate. In some embodiments, the predictive component114and/or the corrective action component112can adjust one or more parameters of a deposition process recipe (e.g., a temperature setting for the process chamber, a pressure setting for the process chamber, a flow rate setting for a precursor for a material included in the film deposited on the substrate surface, etc.) based on a desired target thickness for the a film layer(s). In some embodiments, the deposition process recipe can be adjusted before, during (e.g., in real time) or after the deposition process. In some embodiments, a manufacturing system can include more than one process chambers. For example, example manufacturing system300ofFIG.3illustrates multiple process chambers314,316,318. It should be noted that, in some embodiments, data obtained to train the machine-learning model and data collected to be provided as input to the machine-learning model can be associated with the same process chamber of the manufacturing system. In other or similar embodiments, data obtained to train the machine-learning model and data collected to be provided as input to the machine-learning model can be associated with different process chambers of the manufacturing system. In other or similar embodiments, data obtained to train the machine-learning model can be associated with a process chamber of a first manufacturing system and data collected to be provide as input to the machine-learning model can be associated with a process chamber of a second manufacturing system. FIG.3is a top schematic view of an example manufacturing system300, according to aspects of the present disclosure. Manufacturing system300can perform one or more processes on a substrate302. Substrate302can be any suitably rigid, fixed-dimension, planar article, such as, e.g., a silicon-containing disc or wafer, a patterned wafer, a glass plate, or the like, suitable for fabricating electronic devices or circuit components thereon. Manufacturing system300can include a process tool304and a factory interface306coupled to process tool304. Process tool304can include a housing308having a transfer chamber310therein. Transfer chamber310can include one or more process chambers (also referred to as processing chambers)314,316,318disposed therearound and coupled thereto. Process chambers314,316,318can be coupled to transfer chamber310through respective ports, such as slit valves or the like. Transfer chamber310can also include a transfer chamber robot312configured to transfer substrate302between process chambers314,316,318, load lock320, etc. Transfer chamber robot312can include one or multiple arms where each arm includes one or more end effectors at the end of each arm. The end effector can be configured to handle particular objects, such as wafers. Process chambers314,316,318can be adapted to carry out any number of processes on substrates302. A same or different substrate process can take place in each processing chamber314,316,318. A substrate process can include atomic layer deposition (ALD), physical vapor deposition (PVD), chemical vapor deposition (CVD), etching, annealing, curing, pre-cleaning, metal or metal oxide removal, or the like. Other processes can be carried out on substrates therein. Process chambers314,316,318can each include one or more sensors configured to capture data for substrate302before, after, or during a substrate process. For example, the one or more sensors can be configured to capture spectral data and/or non-spectral data for a portion of substrate302during a substrate process. In other or similar embodiments, the one or more sensors can be configured to capture data associated with the environment within process chamber314,316,318before, after, or during the substrate process. For example, the one or more sensors can be configured to capture data associated with a temperature, a pressure, a gas concentration, etc. of the environment within process chamber314,316,318during the substrate process. A load lock320can also be coupled to housing308and transfer chamber310. Load lock320can be configured to interface with, and be coupled to, transfer chamber310on one side and factory interface306. Load lock320can have an environmentally-controlled atmosphere that can be changed from a vacuum environment (wherein substrates can be transferred to and from transfer chamber310) to an at or near atmospheric-pressure inert-gas environment (wherein substrates can be transferred to and from factory interface306) in some embodiments. Factory interface306can be any suitable enclosure, such as, e.g., an Equipment Front End Module (EFEM). Factory interface306can be configured to receive substrates302from substrate carriers322(e.g., Front Opening Unified Pods (FOUPs)) docked at various load ports324of factory interface306. A factory interface robot326(shown dotted) can be configured to transfer substrates302between carriers (also referred to as containers)322and load lock320. Carriers322can be a substrate storage carrier or a replacement part storage carrier. Manufacturing system300can also be connected to a client device (not shown) that is configured to provide information regarding manufacturing system300to a user (e.g., an operator). In some embodiments, the client device can provide information to a user of manufacturing system300via one or more graphical user interfaces (GUIs). For example, the client device can provide information regarding a target thickness profile for a film to be deposited on a surface of a substrate302during a deposition process performed at a process chamber314,316,318via a GUI. The client device can also provide information regarding a modification to a process recipe in view of a respective set of deposition settings predicted to correspond to the target profile, in accordance with embodiments described herein. Manufacturing system300can also include a system controller328. System controller328can be and/or include a computing device such as a personal computer, a server computer, a programmable logic controller (PLC), a microcontroller, and so on. System controller328can include one or more processing devices, which can be general-purpose processing devices such as a microprocessor, central processing unit, or the like. More particularly, the processing device can be a complex instruction set computing (CISC) microprocessor, reduced instruction set computing (RISC) microprocessor, very long instruction word (VLIW) microprocessor, or a processor implementing other instruction sets or processors implementing a combination of instruction sets. The processing device can also be one or more special-purpose processing devices such as an application specific integrated circuit (ASIC), a field programmable gate array (FPGA), a digital signal processor (DSP), network processor, or the like. System controller328can include a data storage device (e.g., one or more disk drives and/or solid state drives), a main memory, a static memory, a network interface, and/or other components. System controller328can execute instructions to perform any one or more of the methodologies and/or embodiments described herein. In some embodiments, system controller328can execute instructions to perform one or more operations at manufacturing system300in accordance with a process recipe. The instructions can be stored on a computer readable storage medium, which can include the main memory, static memory, secondary storage and/or processing device (during execution of the instructions). System controller328can receive data from sensors included on or within various portions of manufacturing system300(e.g., processing chambers314,316,318, transfer chamber310, load lock320, etc.). In some embodiments, data received by the system controller328can include spectral data and/or non-spectral data for a portion of substrate302. In other or similar embodiments, data received by the system controller328can include data associated with processing substrate302at processing chamber314,316,318, as described previously. For purposes of the present description, system controller328is described as receiving data from sensors included within process chambers314,316,318. However, system controller328can receive data from any portion of manufacturing system300and can use data received from the portion in accordance with embodiments described herein. In an illustrative example, system controller328can receive data from one or more sensors for process chamber314,316,318before, after, or during a substrate process at the process chamber314,316,318. Data received from sensors of the various portions of manufacturing system300can be stored in a data store350. Data store350can be included as a component within system controller328or can be a separate component from system controller328. In some embodiments, data store350can be data store140described with respect toFIG.1. FIG.4is a cross-sectional schematic side view of a process chamber400, in accordance with embodiments of the present disclosure. In some embodiments, process chamber400can correspond to process chamber314,316,318, described with respect toFIG.3. Process chamber400can be used for processes in which a corrosive plasma environment is provided. For example, the process chamber400can be a chamber for a plasma etcher or plasma etch reactor, and so forth. In another example, process chamber can be a chamber for a deposition process, as previously described. In one embodiment, the process chamber400includes a chamber body402and a showerhead430that encloses an interior volume406. The showerhead430can include a showerhead base and a showerhead gas distribution plate. Alternatively, the showerhead430can be replaced by a lid and a nozzle in some embodiments, or by multiple pie shaped showerhead compartments and plasma generation units in other embodiments. The chamber body402can be fabricated from aluminum, stainless steel or other suitable material such as titanium (Ti). The chamber body402generally includes sidewalls408and a bottom410. An exhaust port426can be defined in the chamber body402, and can couple the interior volume406to a pump system428. The pump system428can include one or more pumps and throttle valves utilized to evacuate and regulate the pressure of the interior volume406of the process chamber400. The showerhead430can be supported on the sidewall408of the chamber body402. The showerhead420(or lid) can be opened to allow access to the interior volume406of the process chamber400, and can provide a seal for the process chamber400while closed. A gas panel458can be coupled to the process chamber400to provide process and/or cleaning gases to the interior volume406through the showerhead430or lid and nozzle (e.g., through apertures of the showerhead or lid and nozzle). For example. gas panel458can provide precursors for materials of a film451deposited on a surface of a substrate302. In some embodiments, a precursor can include a silicon-based precursor or a boron-based precursor. The showerhead430can include a gas distribution plate (GDP) and can have multiple gas delivery holes432(also referred to as channels) throughout the GDP. A substrate support assembly448is disposed in the interior volume406of the process chamber400below the showerhead430. The substrate support assembly448holds a substrate302during processing (e.g., during a deposition process). In some embodiments, processing chamber400can include metrology equipment (not shown) configured to generate in-situ metrology measurements during a process performed at process chamber400. The metrology equipment can be operatively coupled to the system controller (e.g., system controller328, as previously described). In some embodiments, the metrology equipment can be configured to generate a metrology measurement value (e.g., a thickness) for film451during particular instances of the deposition process. The system controller can generate a thickness profile for film451based on the received metrology measurement values from the metrology equipment. In other or similar embodiments, processing chamber400does not include metrology equipment. In such embodiments, the system controller can receive one or more metrology measurement values for film451after completion of the deposition process at process chamber400. System controller can determine a deposition rate based on the one or more metrology measurement values and can associate generate the thickness profile for film451based on the determined concentration gradient and the determined deposition rate of the deposition process. FIG.5is a flow chart of a method500for identifying predictive metrology data for layers of a film using a machine-learning model, according to aspects of the present disclosure. Method500is performed by processing logic that can include hardware (circuitry, dedicated logic, etc.), software (such as is run on a general purpose computer system or a dedicated machine), firmware, or some combination thereof. In one implementation, method500can be performed by a computer system, such as computer system architecture100ofFIG.1. In other or similar implementations, one or more operations of method500can be performed by one or more other machines not depicted in the figures. In some aspects, one or more operations of method500can be performed by server machine170, server machine180, and/or predictive server112. At block510, processing logic obtains a plurality of sensor values associated with a deposition process performed in a process chamber to deposit one or more layers of film on a surface of a substrate. At block512, processing logic applies a first machine-learning model to a first subset of the plurality of sensor values associated with layers of a first material. At block514, processing logic applies a second machine-learning model to a second subset of the plurality of sensor values associated with layers of a second material. In some embodiments, the first and second machine-learning models are trained based on historical sensor data and historical metrology data. At block516, processing logic obtains a first output of the first machine-learning model. For example, the first output can identify first predictive metrology data for one or more layers of the first material of the film (e.g., oxide). At block518, processing logic obtains a second output of the second machine-learning model. For example, the second output can identify second predictive metrology data for one or more layers of the second material of the film (e.g., nitride). In some embodiments, the predictive metrology data includes a contour map having a set of spatial measurements, each spatial measurement indicating a thickness of a particular location of a plurality of locations on one or more layers on the substrate. In some embodiments, the predictive metrology data indicates an average predictive layer thickness. FIG.6is a block diagram illustrating a computer system600, according to certain embodiments. In some embodiments, computer system600may be connected (e.g., via a network, such as a Local Area Network (LAN), an intranet, an extranet, or the Internet) to other computer systems. Computer system600may operate in the capacity of a server or a client computer in a client-server environment, or as a peer computer in a peer-to-peer or distributed network environment. Computer system600may be provided by a personal computer (PC), a tablet PC, a Set-Top Box (STB), a Personal Digital Assistant (PDA), a cellular telephone, a web appliance, a server, a network router, switch or bridge, or any device capable of executing a set of instructions (sequential or otherwise) that specify actions to be taken by that device. Further, the term “computer” shall include any collection of computers that individually or jointly execute a set (or multiple sets) of instructions to perform any one or more of the methods described herein. In a further aspect, the computer system600may include a processing device602, a volatile memory604(e.g., Random Access Memory (RAM)), a non-volatile memory606(e.g., Read-Only Memory (ROM) or Electrically-Erasable Programmable ROM (EEPROM)), and a data storage device616, which may communicate with each other via a bus608. Processing device602may be provided by one or more processors such as a general purpose processor (such as, for example, a Complex Instruction Set Computing (CISC) microprocessor, a Reduced Instruction Set Computing (RISC) microprocessor, a Very Long Instruction Word (VLIW) microprocessor, a microprocessor implementing other types of instruction sets, or a microprocessor implementing a combination of types of instruction sets) or a specialized processor (such as, for example, an Application Specific Integrated Circuit (ASIC), a Field Programmable Gate Array (FPGA), a Digital Signal Processor (DSP), or a network processor). Computer system600may further include a network interface device622(e.g., coupled to network674). Computer system600also may include a video display unit610(e.g., an LCD), an alphanumeric input device612(e.g., a keyboard), a cursor control device614(e.g., a mouse), and a signal generation device620. In some implementations, data storage device616may include a non-transitory computer-readable storage medium624on which may store instructions626encoding any one or more of the methods or functions described herein, including instructions encoding components ofFIG.1(e.g., corrective action component122, predictive component114, etc.) and for implementing methods described herein. Instructions626may also reside, completely or partially, within volatile memory604and/or within processing device602during execution thereof by computer system600, hence, volatile memory604and processing device602may also constitute machine-readable storage media. While computer-readable storage medium624is shown in the illustrative examples as a single medium, the term “computer-readable storage medium” shall include a single medium or multiple media (e.g., a centralized or distributed database, and/or associated caches and servers) that store the one or more sets of executable instructions. The term “computer-readable storage medium” shall also include any tangible medium that is capable of storing or encoding a set of instructions for execution by a computer that cause the computer to perform any one or more of the methods described herein. The term “computer-readable storage medium” shall include, but not be limited to, solid-state memories, optical media, and magnetic media. The methods, components, and features described herein may be implemented by discrete hardware components or may be integrated in the functionality of other hardware components such as ASICS, FPGAs, DSPs or similar devices. In addition, the methods, components, and features may be implemented by firmware modules or functional circuitry within hardware devices. Further, the methods, components, and features may be implemented in any combination of hardware devices and computer program components, or in computer programs. Unless specifically stated otherwise, terms such as “receiving,” “performing,” “providing,” “obtaining,” “causing,” “accessing,” “determining,” “adding,” “using,” “training,” or the like, refer to actions and processes performed or implemented by computer systems that manipulates and transforms data represented as physical (electronic) quantities within the computer system registers and memories into other data similarly represented as physical quantities within the computer system memories or registers or other such information storage, transmission or display devices. Also, the terms “first,” “second,” “third,” “fourth,” etc. as used herein are meant as labels to distinguish among different elements and may not have an ordinal meaning according to their numerical designation. Examples described herein also relate to an apparatus for performing the methods described herein. This apparatus may be specially constructed for performing the methods described herein, or it may include a general purpose computer system selectively programmed by a computer program stored in the computer system. Such a computer program may be stored in a computer-readable tangible storage medium. The methods and illustrative examples described herein are not inherently related to any particular computer or other apparatus. Various general purpose systems may be used in accordance with the teachings described herein, or it may prove convenient to construct more specialized apparatus to perform methods described herein and/or each of their individual functions, routines, subroutines, or operations. Examples of the structure for a variety of these systems are set forth in the description above. The above description is intended to be illustrative, and not restrictive. Although the present disclosure has been described with references to specific illustrative examples and implementations, it will be recognized that the present disclosure is not limited to the examples and implementations described. The scope of the disclosure should be determined with reference to the following claims, along with the full scope of equivalents to which the claims are entitled. | 57,346 |
11862521 | DETAILED DESCRIPTION OF PREFERRED EMBODIMENTS It is appreciated that the system and method described hereinbelow with reference toFIGS.1-2Bare used to measure misregistration between layers of a wafer on which semiconductor devices are formed and are part of a manufacturing process for semiconductor devices. The misregistration measured by the system and method described hereinbelow with reference toFIGS.1-2Bis used to adjust fabrication processes, such as lithography, during the manufacture of the semiconductor devices to ameliorate misregistration between various layers of the semiconductor devices being fabricated. Reference is now made toFIG.1, which is a simplified schematic illustration of a multiple-tool parameter set calibration and misregistration measurement system (MTPSCMMS)100. As seen inFIG.1, MTPSCMMS100includes at least one (e.g., two or more or a plurality of) reference misregistration metrology tool102and at least one (e.g., two or more or a plurality of) initially-uncalibrated misregistration metrology tool104. Each of at least one reference misregistration metrology tool102is operative to measure misregistration between at least two layers formed on a wafer112using a respective set of measurement parameters. Wafer112preferably includes a plurality of semiconductor devices and is selected from a batch of wafers120. The at least one reference misregistration metrology tool102thereby generates a respective misregistration data set. It is to be noted that each or any of the at least one reference misregistration metrology tools102and each or any of the initially-uncalibrated misregistration metrology tools104measures misregistration at a single site or at multiple sites on wafer112. In an embodiment of the present application, MTPSCMMS100is operative to use a first reference misregistration metrology tool102to measure misregistration between at least two layers formed on a wafer112using a first set of measurement parameters to generate a first misregistration data set. MTPSCMMS100is operative to (1) process the first set of measurement parameters and the first misregistration data set from first reference misregistration metrology tool102, (2) generate a calibrated set of measurement parameters on the basis of the first set of measurement parameters and the first misregistration data set from the first reference misregistration metrology tool102, and (3) calibrate at least one initially-uncalibrated misregistration metrology tool104(e.g., a plurality of initially-uncalibrated misregistration metrology tools104) using the calibrated set of measurement parameters. Once the at least one initially-uncalibrated misregistration metrology tools104is calibrated, initially-uncalibrated misregistration metrology tool104measures misregistration between at least two layers formed on wafer112, using the calibrated set of measurement parameters. It is to be noted that MTPSCMMS100is operative to use any number of reference misregistration metrology tools102to measure misregistration between at least two layers formed on wafer112, each reference misregistration metrology tool102using a respective set of measurement parameters to generate a respective misregistration data set. It is appreciated that each of various reference misregistration metrology tools102and each of initially-uncalibrated misregistration metrology tools104may measure misregistration between at least two layers of the same wafer112or of a different wafer112from batch of wafers120. In one embodiment of the present invention, each of wafers112in batch of wafers120undergoes the same fabrication steps and includes semiconductor devices which are intended to be identical to corresponding semiconductor devices on all other wafers112in batch of wafers120. In another embodiment of the present invention, at least one wafer112in batch of wafers120is intentionally fabricated differently than other wafers112in batch of wafers120, typically as a design of experiment (DOE) wafer, which is fabricated using parameters that intentionally vary from other wafers112in batch of wafers120. Reference misregistration metrology tools102and initially-uncalibrated misregistration metrology tools104may be any suitable misregistration metrology tools. Preferably, all misregistration metrology tools102and104in MTPSCMMS100belong to a single category of misregistration metrology tools. Examples of categories of misregistration metrology tools include, inter alia, scatterometry misregistration metrology tools, imaging misregistration metrology tools and electron beam misregistration metrology tools. A typical scatterometry misregistration metrology tool useful as misregistration metrology tools102and104is an ATL™100, commercially available from KLA Corporation of Milpitas, Calif., USA. A typical imaging misregistration metrology tool useful as misregistration metrology tools102and104is an Archer™750, commercially available from KLA Corporation of Milpitas, Calif., USA. A typical electron beam misregistration metrology tool useful as misregistration metrology tools102and104is an eDR7380™, commercially available from KLA Corporation of Milpitas, Calif., USA. It is noted that while all misregistration metrology tools102and104of MTPSCMMS100preferably belong to a single category of misregistration metrology tools, each of misregistration metrology tools102and104of MTPSCMMS100need not be the same model of misregistration metrology tool. For example, in an embodiment wherein misregistration metrology tools102and104belong to the imaging misregistration metrology tool category, one of misregistration metrology tools102and104may be an Archer™750and another of misregistration metrology tools102and104may be an Archer™600or any other suitable imaging misregistration metrology tool. Similarly, in an embodiment wherein misregistration metrology tools102and104belong to the scatterometry misregistration metrology tool category, one of misregistration metrology tools102and104may be an ATL™100and another of misregistration metrology tools102and104may be an ATL™150or any other suitable scatterometry misregistration metrology tool. Similarly, in an embodiment wherein misregistration metrology tools102and104belong to the electron beam misregistration metrology tool category, one of misregistration metrology tools102and104may be an eDR7380™ and another of misregistration metrology tools102and104may be an eDR7280™ or any other suitable electron beam misregistration metrology tool. It is appreciated that MTPSCMMS100may include more than one, e.g., more than two, reference misregistration metrology tools102and more than one, e.g., more than two, initially-uncalibrated misregistration metrology tools104. Preferably all misregistration metrology tools102and104in MTPSCMMS100belong to the same category, for example, all scatterometry misregistration metrology tools, all imaging misregistration metrology tools or all electron beam misregistration metrology tools. MTPSCMMS100further includes a calibrated set of measurement parameters generator (CSMPG)132. A first reference misregistration metrology tool102uses a first set of measurement parameters to measure misregistration between at least two layers on wafer112, thereby generating a first misregistration data set. First reference misregistration metrology tool102transmits to CSMPG132the first set of measurement parameters and the first misregistration data set. The first misregistration data set generated by first reference misregistration metrology tool102includes, inter alia, misregistration values and quality metrics. The misregistration values preferably include a magnitude and direction of misregistration between at least two layers of wafer112at one or more locations on wafer112. The quality metrics may include, inter alia, accuracy flags, tool induced shift (TIS), Qmerit, focus sensitivity, throughput and precision. If reference misregistration metrology tool102is embodied as an imaging or electron beam misregistration metrology tool, the set of quality metrics may also include, for example, contrast precision. If reference misregistration metrology tool102is embodied as a scatterometry misregistration metrology tool, the set of quality metrics may also include, for example, pupil 3σ, normalized pupil 3σ (MEB) and any additional suitable pupil data quality metrics. CSMPG132is operative to receive from first reference misregistration metrology tool102the first set of measurement parameters and the first misregistration data set generated by first reference misregistration metrology tool102, process the first set of measurement parameters and the first misregistration data set generated by first reference misregistration metrology tool102, and, by processing the first set of measurement parameters and the first misregistration data set generated by first reference misregistration metrology tool102, generate a calibrated set of measurement parameters. CSMPG132is operative to then communicate the calibrated set of measurement parameters to at least one initially-uncalibrated misregistration metrology tool104(e.g., a plurality of initially-uncalibrated misregistration metrology tools104) in order to facilitate calibrating the at least one initially-uncalibrated misregistration metrology tool104(e.g., a plurality of initially-uncalibrated misregistration metrology tools104) using the calibrated set of measurement parameters generated by CSMPG132. For some applications of the present invention, at least a second and/or additional reference misregistration metrology tool102is operative to use a second and/or additional set(s) of measurement parameters to measure misregistration between the at least two layers on wafer112selected from batch of wafers120, to generate a second and/or additional misregistration data set. CSMPG132is operative to (a) receive from the first and the at least second and/or additional reference misregistration metrology tools102the respective first and second, and/or additional sets of measurement parameters as well as the respective first and second and/or additional misregistration data sets generated by first and the at least second and/or additional reference misregistration metrology tools102respectively, (b) process the respective first and second and/or additional sets of measurement parameters as well as respective first and second and/or additional misregistration data sets generated by first and at least second and/or additional reference misregistration metrology tools102respectively, and (c) by processing the respective first and second and/or additional sets of measurement parameters as well as the respective first and second and/or additional misregistration data sets generated by first and second and/or additional reference misregistration metrology tools102respectively, generate the calibrated set of measurement parameters. CSMPG132then communicates the calibrated set of measurement parameters to at least one initially-uncalibrated misregistration metrology tool104(e.g., a plurality of initially-uncalibrated misregistration metrology tools104) in order to facilitate calibrating the at least one initially-uncalibrated misregistration metrology tool104(e.g., a plurality of initially-uncalibrated misregistration metrology tools104) using the calibrated set of measurement parameters generated by CSMPG132. Both in the embodiment of the present invention wherein CSMPG132receives the set of measurements parameters and the misregistration data set from only first reference misregistration metrology tool102and in the embodiment of the present invention wherein CSMPG132receives the respective sets of measurements parameters and the respective misregistration data sets from a plurality of reference misregistration metrology tools102, CSMPG132processes the set or sets of measurements parameters and the misregistration data set or sets to generate the calibrated set of measurement parameters for at least one initially-uncalibrated misregistration metrology tool104. Preferably, CSMPG processes the set or sets of measurements parameters and the set of misregistration data using a CSMPG algorithm (CSMPGA). CSMPGA may be any suitable algorithm, such as, inter alia, a machine-learning algorithm or a regression analysis algorithm. A suitable machine-learning algorithm may be, for example, a neural network analysis, a principle component analysis, a support vector machine, a decision tree or a gaussian process. Preferably, as part of CSMPGA, CSMPG132models expected misregistration data sets for various sets of measurement parameters. CSMPG132compares the expected misregistration data sets generated by CSMPGA to each other, and any set of measurement parameters associated with a particularly desirable expected misregistration data set is identified by CSMPG132as the calibrated set of measurement parameters. A particularly desirable expected misregistration data set may be an expected misregistration data set having at least one of particularly desirable misregistration values and particularly desirable quality metrics. The set of measurement parameters transmitted from reference misregistration metrology tool or tools102to CSMPG132as well as the calibrated set of measurement parameters communicated from CSMPG132to any of initially-uncalibrated misregistration metrology tools104may include, inter alia, a linear position of a wafer stage used in misregistration measurement, an azimuthal orientation of a wafer stage used in misregistration measurement, an elevation angular orientation of a wafer stage used in misregistration measurement, an axis along which misregistration is measured, a region of interest of a metrology target, a numerical aperture used in misregistration measurement, a polarization of light used in misregistration measurement, wavelengths of light used in misregistration measurement, a bandwidth of wavelengths of light used in misregistration measurement, an intensity of light used in misregistration measurement, a focal depth used in misregistration measurement, an apodizer used in misregistration measurement, an optics channel used in misregistration measurement and a camera used in misregistration measurement. Reference is now made toFIGS.2A &2B, which are together a simplified flow chart illustrating a multiple-tool parameter set calibration and misregistration measurement method (MTPSCMMM)200useful by MTPSCMMS100. As seen inFIG.2A, at a first step202, first reference misregistration metrology tool102uses a first set of measurement parameters to measure misregistration between at least two layers on wafer112, selected from batch of wafers120. At a next step204, a decision is made whether or not to measure either the same wafer112or an additional wafer112, selected from batch of wafers120, using an additional (e.g., a second) reference misregistration metrology tool102which uses a second set of measurement parameters to measure misregistration between at least two layers on wafer112, selected from batch of wafers120in order to generate a second misregistration data set. Then, at a next step206, if either the same wafer112or an additional wafer112, selected from batch of wafers120, is to be measured using additional (e.g., the second) reference misregistration metrology tool102, wafer112is measured using additional (e.g., the second) reference misregistration metrology tool102using additional set of measurement parameters. MTPSCMMM200then returns to step204. If either the same wafer112or an additional wafer112, selected from batch of wafers120, is not to be measured using an additional reference misregistration metrology tool102, then at a next step208, CSMPG132(a) receives the sets of measurement parameters and the misregistration data sets from step202and optionally from step206, which are preferably transmitted to CSMPG132from first reference misregistration metrology tool102and from any additional (e.g., second) reference misregistration metrology tools102, (b) processes the transmitted sets of measurement parameters and misregistration data sets, and (c) by the processing, generates a calibrated set of measurement parameters. The sets of measurement parameters used in steps202and206may include, inter alia, a linear position of a wafer stage used in misregistration measurement, an azimuthal orientation of a wafer stage used in misregistration measurement, an elevation angular orientation of a wafer stage used in misregistration measurement, an axis along which misregistration is measured, a region of interest of a metrology target, a numerical aperture used in misregistration measurement, a polarization of light used in misregistration measurement, wavelengths of light used in misregistration measurement, a bandwidth of wavelengths of light used in misregistration measurement, an intensity of light used in misregistration measurement, a focal depth used in misregistration measurement, an apodizer used in misregistration measurement, an optics channel used in misregistration measurement and a camera used in misregistration measurement. The misregistration data set or sets generated in steps202and206may include, inter alia, misregistration values and quality metrics. The misregistration values preferably include a magnitude and direction of misregistration between at least two layers of wafer112at one or more locations on wafer112. The quality metrics may include, inter alia, accuracy flags, tool induced shift (TIS), Qmerit, focus sensitivity, throughput and precision. If reference misregistration metrology tool102is embodied as an imaging or electron beam misregistration metrology tool, the set of quality metrics may also include, for example, contrast precision. If reference misregistration metrology tool102is embodied as a scatterometry misregistration metrology tool, the set of quality metrics may also include, for example, pupil 3σ, normalized pupil 3σ (MEB) and any additional suitable pupil data quality metrics. Preferably, at step208, CSMPG132generates the calibrated set of measurement parameters using CSMPG algorithm (CSMPGA), which may be any suitable algorithm, such as, inter alia, a regression analysis algorithm or CSMPG-machine-learning algorithm (CSMPGMLA). CSMPGMLA may be any suitable algorithm, such as, inter alia, a neural network analysis, a principle component analysis, a support vector machine, a decision tree and a gaussian process. Preferably, as part of CSMPGA, CSMPG132models expected misregistration data sets for various sets of measurement parameters. CSMPG132compares the expected misregistration data sets generated by CSMPGA to each other, and any set of measurement parameters associated with a particularly desirable expected misregistration data set is identified by CSMPG132as the calibrated set of measurement parameters. A particularly desirable expected misregistration data set may be an expected misregistration data set having at least one of particularly desirable misregistration values and particularly desirable quality metrics. As a next step214, the calibrated set of measurement parameters generated in step208is transmitted to one or more initially-uncalibrated misregistration metrology tools104in MTPSCMMS100. In step214, the one or more initially-uncalibrated misregistration metrology tools104is/are calibrated in accordance with and based upon the calibrated set of measurement parameters generated in step208. The calibrated set of measurement parameters of steps208,214,216, and218which are communicated from CSMPG132to any of initially-uncalibrated misregistration metrology tools104may include, inter alia, a linear position of a wafer stage used in misregistration measurement, an azimuthal orientation of a wafer stage used in misregistration measurement, an elevation angular orientation of a wafer stage used in misregistration measurement, an axis along which misregistration is measured, a region of interest of a metrology target, a numerical aperture used in misregistration measurement, a polarization of light used in misregistration measurement, wavelengths of light used in misregistration measurement, a bandwidth of wavelengths of light used in misregistration measurement, an intensity of light used in misregistration measurement, a focal depth used in misregistration measurement, an apodizer used in misregistration measurement, an optics channel used in misregistration measurement and a camera used in misregistration measurement. At a next step218, MTPSCMMM200uses at least one of initially-uncalibrated misregistration metrology tools104used in steps214and216using the corresponding calibrated set or sets of measurement parameters generated at step208, to measure misregistration between at least two layers of at least one wafer112from batch of wafers120. It will be appreciated by persons skilled in the art that the present invention is not limited to what has been particularly shown and described hereinabove. The scope of the present invention includes both combinations and subcombinations of various features described hereinabove as well as modifications thereof, all of which are not in the prior art. | 21,276 |
11862522 | DETAILED DESCRIPTION OF THE INVENTION In the following description, various aspects of the present invention are described. For purposes of explanation, specific configurations and details are set forth in order to provide a thorough understanding of the present invention. However, it will also be apparent to one skilled in the art that the present invention may be practiced without the specific details presented herein. Furthermore, well known features may have been omitted or simplified in order not to obscure the present invention. With specific reference to the drawings, it is stressed that the particulars shown are by way of example and for purposes of illustrative discussion of the present invention only, and are presented in the cause of providing what is believed to be the most useful and readily understood description of the principles and conceptual aspects of the invention. In this regard, no attempt is made to show structural details of the invention in more detail than is necessary for a fundamental understanding of the invention, the description taken with the drawings making apparent to those skilled in the art how the several forms of the invention may be embodied in practice. Before at least one embodiment of the invention is explained in detail, it is to be understood that the invention is not limited in its application to the details of construction and the arrangement of the components set forth in the following description or illustrated in the drawings. The invention is applicable to other embodiments that may be practiced or carried out in various ways as well as to combinations of the disclosed embodiments. Also, it is to be understood that the phraseology and terminology employed herein is for the purpose of description and should not be regarded as limiting. Unless specifically stated otherwise, as apparent from the following discussions, it is appreciated that throughout the specification discussions utilizing terms such as “processing”, “computing”, “calculating”, “determining”, “enhancing” or the like, refer to the action and/or processes of a computer or computing system, or similar electronic computing device, that manipulates and/or transforms data represented as physical, such as electronic, quantities within the computing system's registers and/or memories into other data similarly represented as physical quantities within the computing system's memories, registers or other such information storage, transmission or display devices. Embodiments of the present invention provide efficient and economical methods and mechanisms for improving accuracy, particularly in overlay optical metrology and provide improvements to the technology field. Novel methods are disclosed to achieve superior accuracy in optical metrology that are aimed to deliver very small inaccuracies in run time and/or train. Methods, metrology modules and target designs are provided, which improve the accuracy of metrology measurements. Methods provide flexible handling of multiple measurement recipes and setups and enable relating them to landscape features that indicate their relation to resonance regions and to flat regions. Clustering of recipes, self-consistency tests, common processing of aggregated measurements, noise reduction, cluster analysis, detailed analysis of the landscape and targets with skewed cells are employed separately or in combination to provide cumulative improvements of measurement accuracy. Landscapes Optical overlay metrology is a metrology of the asymmetry carried by the metrology signal that is due to the overlay between two lithography steps. This asymmetry is present in the electromagnetic signal because the latter reflects the interference of electric fields with relative phases that carry the overlay information. Specifically, (i) in overlay scatterometry (be it pupil scatterometry of field scatterometry) the overlay mark (target) is a grating-over-grating structure and the overlay information is carried in the relative phase of the lower and upper gratings; (ii) in overlay scatterometry of the side-by-side type (see, e.g., WIPO Publication No. 2014062972) the overlay mark (target) comprises a grating next to a grating structure and the overlay information is again carried in the relative phase of the lower and upper gratings; (iii) in overlay imaging the overlay mark (target) comprises separate marks for the separate layers and the overlay information is carried in the position of each individual mark on the detector which, in turns, is a result of interferences between different diffraction orders of the individual marks. As a result, the sensitivity of the signal (i.e., the extent by which the signal asymmetry is affected by the sought for overlay) is primarily affected by the change in the size of the interference term in these signals. For example, in grating-over-grating and side-by-side targets, some of the terms in the interference phase depend on the optical path difference between light scattered from the lower and upper gratings, which is linear in the thickness of the film stack separating them and inversely proportional on the wavelength. It also depends on other parameters like the angle of incidence, or reflectance, and on the polarization properties of the incident and reflected light. Other properties include the target attributes and the stack and gratings electromagnetic characteristics. In contrast, in overlay imaging, the interference phase is also be linear in the tool's focus and to depend on other parameters such as the incident angles. Observing how the sensitivity of the metrology tool depends on the tool parameters in a continuous fashion, and in particular on various differentials of many of the metrology characteristics (such as the first, second, and higher derivatives of the sensitivity on wavelength, focus, polarization, etc.) reveals the landscape of the technology performance, as explained below. This landscape is particular to any nominal stack, and the inventors have discovered, using simulations and theory, that this landscape is universal in the sense that is largely independent of many type of process variations including all those that break the symmetry of the overlay mark and cause inaccuracy. Tool performances of course include also the inaccuracy which, by definition, strongly depends on the asymmetric process variations, however, the landscape that determines at which sub-sections of the landscape the sensitivity to these process variations is the strongest and in which sub-sections it is the weakest, and how the sensitivity looks like. Specifically, and to a large degree, the same regions that are sensitive to process variation of a certain type are always sensitive to all other types of process variations as this is determined by the nominal stack's sensitivity to overlay, i.e., the sensitivity of a stack with no asymmetric process variations). FIG.1is a high level schematic block diagram of a pupil image90and a landscape95, according to the prior art. Landscape95exhibits pupil locations90A having zero sensitivity (in form of an arc across the pupil image), resonance regions95A, flat regions95B and intermediate regions95C which are analyzed and handled by various embodiments of the invention, e.g., to enhance the accuracy of the metrology measurements, as explained below. WIPO Publication No. 2016086056 discloses the concept of the landscape in metrology measurements, which is a dependency of one or more metrology metric(s), e.g., scatterometry overlay (SCOL) metrics, on one or more parameter. As a non-limiting example, the landscape may express the dependency of any of the overlay, the variation of the overlay (e.g., the Pupil3S metric) and/or the inaccuracy (estimated overlay minus real overlay) upon one or more process parameters, measurement parameters and target parameters. In particular, as described in WIPO Publication No. 2016086056, the inventors have found out that certain regions in the landscape exhibit steep changes that are related to resonances in the optical system (e.g., resonance of illumination within the wafer layers and/or between target structures), which may be used to provide more information on the measured region. The following provides various techniques to use the perspective of the landscape on overlay accuracy, and the way it is reflected by various properties of the signal (for example in the way it depends on the pupil coordinates in pupil scatterometry), to improve overlay accuracy. Any of the disclosed methods and tools may be combined in actual metrology methods and tools to add up the benefits provided by different embodiments and aspects of the disclosed invention. Clustering of Measurements and Recipes FIG.2is a high level schematic illustration of a method100of measuring self-consistency and diversity among recipes111and clustering the measurements accordingly, according to some embodiments of the invention. Metrology tools101are configured to apply measurement recipe(s)111to derive metrology measurements of metrology targets70on wafer(s)60. Metrology tools101typically utilize processing unit(s)109and possibly simulation tool(s)105in determining in adjusting measurements recipes111. Measurements recipes111(also termed setups in the following) derive values of metrology metric(s)91form the measurement, and may be used to derive landscape(s)95of the measured values, as explained above and in WIPO Publication No. 2016086056. Landscape(s)95express the dependency of metrology metric(s)91on parameters such as: hardware parameters (e.g., focus, spot position, illumination wavelengths and polarization, optical elements such as apodizers and various other parameters relating to hardware aspects of the measurements), algorithmic parameters (e.g., various software parameters such as per-pixel weight or algorithmic thresholds, types of algorithms, applied processing steps) and other recipe parameters, as well as target design parameters and target location on the wafer—all of which are indicated inFIG.2schematically by arrows that represent possible axes of landscape(s)95. Resonance regions95A and flat regions95B may be identified in landscape(s)95, as explained in WIPO Publication No. 2016086056. The inventors have found out that accuracy may be improved by determining the most accurate measuring method out of many possible options with the use of self-consistency as an indicator for accuracy. Assuming that when measuring a physical quantity of interest (for example, the CD (critical dimension) value of a bar in target70in a certain wafer position, or the overlay in a certain alignment scheme at a certain wafer position) by a set of measurements that are all expected to be accurate and precise (for example, all the measurements having good TMU (total measurement uncertainty) and good pupil-derived metrics of a certain type and\or all the measurements having good image or signal quality according to specified criteria in optical, SEM (scanning electron microscopy), TEM (transmission electron microscopy) and/or AFM (atomic force microscopy) image or signals)—then a quantitative agreement between these measurements should take place. This can be considered a test to the accuracy of the measurements termed a self-consistency test, which may provide a basis for an algorithm that finds and fuses different measurements together into an accurate one, as disclosed below. For example, in overlay metrology, data shows that when many setups from different and diverse flat regions95B in landscape95agree on their overlay value, they are also most likely to be accurate. This agreement may be used to distinguish between setup measurements from flat regions95B and other measurement which have good or moderate pupil-derived metrics, but that do not agree with any or few of the other setups or recipes111. These considerations may be applied to various metrology metric91, e.g., to CD measurements as well. In practice, the inventors have found that the disclosed test of self-consistency often reveals in data and\or simulations groups of setups that show an agreement on the measurement value within a group but that may disagree between each other. These groups of setups are denoted as clusters112(e.g., clusters A, B, etc.) within a space92of diverse values of measured metrics91and are shown schematically inFIG.2. Finding the accurate group (cluster112) with correspond to the accurate setups may be carried out by calculating the number of different flat regions95B the group members belong to, and the diversity of each group's member list, as well as other metrics such as the maximal difference of the measurement value within each group. The self-consistency test may be performed by finding the groups (clusters112) of setups and applying an algorithm to determine the diversity of the groups (clusters112). The diversity in each cluster112may be quantified in different ways, e.g., as the number of setups in a group that represent different flat regions95B. The diversity of clusters112may be used to estimate the likelihood of a group to be accurate (its likelihood increases if, despite its diversity, its size is tight and the setups disagreement is small) as well as to separate, algorithmically, trivial agreement among setups resulting from factors such as a simple repetition of the measurement and\or a situations where setups agree only because they come from very close points in landscape95, denoted schematically inFIG.2as a trivial subset of setups114. Finally, the groups (clusters112) and measurements within the groups may be ranked to provide a recommendation of the best measuring conditions. In certain embodiments, measurements92may be formalized by describing each measurement setup111as an n dimensional vector, with n being the number of independent realizations of such a measurement, for example, the number of wafer positions on which the measurement takes place). A dimensionally reduced quantity, e.g. a scalar distance, may be defined between pairs of measurements. The distance may be defined from raw data or from model terms. For example, a threshold of maximal distance within groups may be used to give a graph representation of the connections. A m by m adjacency matrix (x1,1…x1,m⋮⋱⋮xm,1…xm,m) may be constructed, with m being the number of measurements setups, with elements xi,jbeing equal to one if the distance between two measurements i, j is below the threshold and zero above or by weighting the connection according to the dimensionally reduced quantity. Using the adjacency matrix the measurements may be clustered by means of machine learning and/or graph theory algorithms. A more generalized version of this option is to adaptively find the typical size of cluster112by analyzing the spectral function of the way the amount and size distribution of clusters112behave as a function of the cluster thresholds and searching for plateaus. Each cluster112may be composed of many measurements, which, however, may not necessarily be independent from each other, as some layers are less sensitive to machine setup or target designs, in which the measurement may differ from each other. Counting the number of measurements in each cluster112may be modified to take into account only independent measurements. In order to determine the independence of two measurements the correlation between them may be calculated, e.g., using metrics that are not used for the clustering itself, such as signal-derived metrics. The correlation may be calculated on the n-dimensional space mentioned above, to determine independent measurements. In order for two recipes111within one cluster112to be independent, they must agree within a bound on the measurement value across the wafer and disagree across wafer in their signal metrics. Alternatively or complementarily, the clustering may be carried out by employing clustering analysis techniques from the world of data mining. A number of clustering methods can be used. Cliques give groups that are not sampling dependent but give overlapping clusters. Hierarchical clustering give separate clusters, no measurement can appear in two clusters but can yield different results when omitting measurements. K means has no overlap but needs a defined number of clusters. A combination of methods can be used to find the clusters. After clustering is carried out, metrics that are cluster-specific, e.g., diversity or diameter, may be calculated, along with finding representative recipes for clusters112. These metrics may be further used to rank clusters112and recipes111within and between clusters112. Both signal-derived metrics per recipe (like those derived from the pupil in the case of pupil scatterometry, or from the harmonic space in the case of imaging based overlay) and data arriving from the other recipes in the same cluster may be used to grade each recipe and rank it to provide a set of recommended recipes. Corresponding self-consistent measures may be derived from the disclosed deriving and processing of clusters112. FIG.11is a high level schematic flowchart illustrating a list of steps of methods disclosed herein, according to some embodiments of the invention.FIG.11comprises multiple methods disclosed herein, which may be carried out separately or in combination. Any of the stages of any one of the methods may be carried out by at least one computer processor (stage199). Method100of clustering of setups with relation to different flat regions in the landscape may comprise measuring self-consistency and diversity among recipes111and clustering the measurements accordingly. Certain embodiments comprise a computer program product comprising a non-transitory computer readable storage medium having computer readable program embodied therewith, the computer readable program configured to carry out any of the stages of method100; and possibly a metrology module configured to carry out any of the stages of method100. Any of the relevant stages of method100may be carried out by a computer processor, e.g., in processing unit(s)109. Method100may comprise identifying measurement setups which correspond to each other in measurement values of at least one metric by applying a self-consistency test to the measurement values, to yield a plurality of clusters of setups (stage112A), wherein the identifying may be carried out using a distance metric in a space of the measurement values (stage112B). Method100further comprises determining a most reliable cluster according to statistical characteristics of the clusters (stage113) and deriving a measurement result from at least one setup in the determined most reliable cluster (stage115). The statistical characteristics may comprise at least a size and a diversity of each cluster. Method100may further comprise relating the identified measurement setups to corresponding at least one flat region in a measurement landscape that comprises an at least partially continuous dependency of at least one metrology metric on at least one parameter (stage116). Clustering of Wafer Regions FIG.3is a high level schematic illustration of a method120of spatial clustering, according to some embodiments of the invention. Method120may use different recipes to measure different wafer regions121(denoted schematically in a non-limiting manner as regions A and B) and/or different sites62to yield a spatial clustering of wafer60with respect to measurements and/or recipes111. The inventors have found out that the accuracy may be improved by allowing setup flexibility across sites62, wafer regions121, wafers60, wafer lots, etc., instead of the traditional metrology method, in which the measurement setup is selected at the train stage and remains fixed for all subsequent target measurements. The term “setup” refers to setting recipe parameters, such as shown schematically inFIG.2concerning the parameters according to which landscape95is analyzed, such as set by hardware knobs (e.g., focus, spot position, wavelength, polarization, apodization), target design parameters, and/or software parameters (e.g., per-pixel weight, algorithmic thresholds etc.) and so forth. The per-measurement setup may be chosen based on a priori simulations, on-the-fly determination using measurement merits, by some parameterization of the setup parameters and/or by performing multiple per-target measurements and determining the best setup a posteriori. For example, one may use a set of accuracy-related quantities like the variability of the overlay on the pupil (in pupil scatterometry) or the combined overlay sensitivity of the pupil pixels to optimize over and find the best setup on a per-measurement basis. As illustrated schematically inFIG.3, sites in different regions121on wafer60may be measured using different parameters and/or setups122,124and/or different sites62on wafer60may be measured using different parameters and/or setups126. Regions121may be concentric (e.g., a wafer center and a wafer periphery may be measured using different setups), adjacent or have any other spatial relation. A combination of wafer regions121and specific sites62may be used to further differentiate the application of different measurement setups. Advantageously, method120may be configured to utilize differences between individual measurements to improve the overall accuracy, especially differences due to process variations and particularly with respect to specific sites62or regions121which exhibit low measurability or increased inaccuracy for a few targets, when measuring all targets with the same fixed setup. In the landscape representation95, the flexibility provided by method120may enable to adjust the setup per-measurement to be measuring in a favorable region of landscape95with respect to measurability and/or accuracy; and avoid changes to landscape95due to process variations. In certain embodiments, the term “region”121may also be used to refer to a group of setups with some common landscape-related property, for example a group of succeeding wavelengths which lie on a flat95B region in landscape95, such as clusters112illustrated schematically inFIG.2. Method120may thus be optionally applied to clusters112illustrated schematically inFIG.2as regions121and similar processing may be used to improve accuracy according to the clustering of setups. For example, N setup parameters (e.g., hardware and/or software parameters) may be denoted as {S1, S2, . . . , SN}, in a linear space V, and the k measurements parameters (lot, wafer, on-wafer location, etc.) may be denoted as {M1, M2, . . . , Mk}. In certain embodiments, method120may implement the per-measurement flexibility in the form of a function S(M), with the setup knobs being determined by the measurement parameters. As a non-limiting example, S(M) may describe the setting the illumination polarization separately for each target location across wafer60, based on the polarization which yields the best merits. A more general way to establish the flexibility described above is to apply a mapping of the setup parameters to a generalized set of parameters P1, P2, . . . , PL, so that the setups space is parametrized as functions of these parameters: Si=Fi({Pj}). Method120may then comprise finding the function ƒ(P) that is optimal from the point of view of a cost function Q(F) which is related e.g., to the accuracy. The optimization may be carried out with respect to the variability across landscape regions, to setups of pupil-derived metrics like the sensitivity or the overlay per setups\pixel, and so forth. Referring toFIG.11as a high level schematic flowchart, method120may comprise selecting a plurality of measurement setups for a corresponding plurality of wafer regions (stage123), wherein the wafer regions are pre-determined or determined on-the-fly and wherein the measurement setups are selected according to at least one accuracy metric (stage125), and carrying out metrology measurements with the selected measurement setup for each corresponding wafer region (stage127). As described above, the measurement setups may be selected according to a clustering of measurements or simulation values of at least one metric by applying a self-consistency test thereto, to yield a plurality of clusters of setups from which a most reliable cluster is determined for each of the wafer regions according to statistical characteristics of the clusters. Certain embodiments comprise a computer program product comprising a non-transitory computer readable storage medium having computer readable program embodied therewith, the computer readable program configured to carry out any of the stages of method120; and possibly a metrology module configured to carry out any of the stages of method120. Any of the relevant stages of method120may be carried out by a computer processor, e.g., in processing unit(s)109. Noise Reduction FIG.4is a high level schematic flowchart of a method130of noise removal and smoothing of the pupil images, according to some embodiments of the invention. Method130may comprise pre-processing stages which improve the signal to noise ratio of the overlay and of the pupil derived metrics and algorithms, in any one of the disclosed embodiments and/or independently therefrom. Noise reduction134may be applied to the differential signals D1and D2(measured by measurement recipes111)132by using a spatial algorithmic filter, for example, one may use a filter that averages a pixel's value with its neighboring pixels' values. Noise reduction may eliminate or reduce noise (unrelated to accuracy, such as random noise) in scatterometry signals which may be caused by different sources and improve the quality of the overlay measurement by means of different pupil metrics and/or the overlay of a specific SCOL measurement. a Method130may be used to improve any of the other methods disclosed herein. Noise reduction may be carried out with or without a symmetrization of the signal136with respect to reflection symmetry in the direction perpendicular to the grating direction (i.e., the measurement direction of a periodic structure in target70). Symmetrization may be applied to produce pupil-derived metrics that characterize the asymmetry in the perpendicular direction138and/or to clean the signal from these asymmetries to provide pupil-derived metrics137with improved fit to the landscape theory and phenomenology that is derived from simulations135. For example, various thresholds disclosed herein may be set in a more accurate manner according to simulation-derived values. Referring toFIG.11as a high level schematic flowchart, method130may comprise or be complemented by modifying a pixel value in a metrology pupil image according to an average of neighboring pixel values to reduce random noise in the pupil image (stage134), optionally further comprising symmetrizing pixel values in the pupil images prior to the modifying (stage136), wherein the symmetrizing is in a direction that is perpendicular measurement direction of a measured periodic structure target. Certain embodiments comprise a computer program product comprising a non-transitory computer readable storage medium having computer readable program embodied therewith, the computer readable program configured to carry out any of the stages of method130; and possibly a metrology module configured to carry out any of the stages of method130. Certain embodiments comprise pupil images derived by one or more stages of method130. Any of the relevant stages of method130may be carried out by a computer processor, e.g., in processing unit(s)109. Weighted Pupil Metrics FIG.5is a high level schematic flowchart of a method140of improving the metrics over the pupil images, according to some embodiments of the invention. Method140may be configured to fuse measurements from multiple recipes to derive weighted pupil images having improved accuracy. The inventors have found out that concatenating pixels from multiple pupils from multiple measurements which differ from each other in setup and target (e.g., in wavelength, polarization, apodizer, target design etc.) may be used to improve the accuracy of the measurements. Following this concatenation, the overlay (or any other metric91) may be calculated according to prior art algorithms but using all of the (concatenated) pixels together. Moreover, method140may comprise extending prior art overlay algorithms, which take into account the basic feature of sensitivity, to further comprise multiple pupils, while carrying out signal normalization with care, as described below. Method140may comprise concatenating pupil values and/or pupil images142from multiple measurements with different setups141, providing metric(s) for each pupil and deriving multiple-setup weighted metrics146to provide more accurate and stable metric148, as described below. Furthermore, the inventors have found out, that no further auxiliary storage is required for such a calculation, since the essence of the overlay algorithm can be subdivided to separable sums over a few quantities, so that each pupil is summed before the calculation. It is suggested to use this overlay algorithm during setup as a reference point, as well as during runtime. The algorithm performs a fit of D1and D2to the form D1,2(setup,pixel)=A(setup,pixel)×OFFSET1,2, where the OFFSET1,2are the offsets of the target cells. The fit may be weighted or may be unweighted with respect to signal characteristics such as the signal strength. A further improvement of the algorithm involves adding another degree of freedom, denoted {right arrow over (β)}, such that each pupil has an attached βnvalue. This β is used as weighting. This degree of freedom β may be optimized so that the overall pixel vector has some extremum feature, such as an extremum of the pupil variability per pupil of signal derived quantities like combination of D1and D2. In addition to applying nominal overlay algorithms across all pixels, an additional fit of the form D1,2(setup,pixel)=A(setup, pixel)×OFFSET1,2+B may be carried out to optimize the respective parameter B to increase the accuracy. An additional improvement may be achieved by using the principal components in the space of D1and D2. Advantageously, the disclosed algorithm is particularly stable with respect to different sampling choices. The stability may be measured using ‘robustness checks’, in which recipes may be algorithmically discarded according to random selection, and the algorithm is applied to the remaining recipes. This stage may be repeated with multiple random realizations, and the different results compared to provide an estimate of the algorithms stability. The ways to measure the comparisons include but are not limited to the overlay difference between the different realizations and a reference overlay, the minimal and maximal distance between the algorithm result and the references, and for the purposes of setup optimization, the changes in the leading recipe under different random realizations. Referring toFIG.11as a high level schematic flowchart, method140may comprise or be complemented by deriving a value of a metrology metric from multiple measurements of the metric (stage146A) using different measurement setups and/or different targets, wherein the value is derived from a concatenation142of pixels from the multiple measurements which is carried out with respect to the measurements (stage142A). Method140may further comprise weighting the pixels according to a weighting function and optimizing the weighting function to minimize pupil variation (stage146B). In certain embodiments, method140may further comprise estimating an algorithmic stability by comparing results from multiple concatenations of different sub-sets of the measurements and/or measurement recipes and/or measured targets (stage147). Certain embodiments comprise a computer program product comprising a non-transitory computer readable storage medium having computer readable program embodied therewith, the computer readable program configured to carry out any of the stages of method140; and possibly a metrology module configured to carry out any of the stages of method140. Certain embodiments comprise signals such as concatenated pupil images and/or pixels, which are derived by one or more stages of method140. Any of the relevant stages of method140may be carried out by a computer processor, e.g., in processing unit(s)109. Variation Analysis Among Recipes FIG.6is a high level schematic flowchart of a method150of analyzing variation among recipes, according to some embodiments of the invention. Method150may comprise using principal component analysis (PCA)154on differential signals152to analyze variation among recipes. The inventors observed that while in an ideal scatterometry measurement the differential signals D1and D2of the various pixels should all reside on the locus D1∝D2, real measurements are noisy and may contain either seemingly random noise which may cause the pixel's linear distribution to widen and/or may add bias to D1, or D2or both. The inventors have found out that the quality of the pupil data may be inferred from the ratio of the height and width of the scatter plot of the pixels in the x,y-plane. More specifically, the principal axes of the scatter plot in the D1-D2-plane may be determined by applying PCA154, by diagonalizing the covariance matrix defined by (Var(D1)Cov(D1,D2)Cov(D1,D2)Var(D2)). The eigenvectors and eigenvalues156of the covariance matrix may be used determine the overlay. The quality of the result may be determined by the ratio of the shortest to longest principal values, i.e., by the ratio of the smaller to larger eigenvalues—the lower the ratio, the higher the quality of the overlay obtained. Biases in D1and/or in D2are automatically handled by this procedure since the principal axes are impervious to translation of the origin. Method150may further comprise taking pixels from multiple measurement setups (multiple wavelengths, multiple target designs, multiple polarizations, different apodizers and/or other tool knobs), as exemplified in method140, and may also be applied to any combination of pupil pixel and setup and so applies to both pupil- and field-scatterometry, and may be used to improve method120, for evaluation and clustering the recipes158. Referring toFIG.11as a high level schematic flowchart, method150may comprise or be complemented by deriving a measurement setup by applying a PCA to a plurality of metrology measurements from using a plurality of setups (stage154A) and selecting a measurement setup which exhibits a smallest ratio of small to large eigenvalues from the PCA (stage156A), e.g., with respect to the covariance matrix. Method150may further comprise applying the PCA to a plurality of pixels from the metrology measurements (stage159), possibly concatenated from multiple measurements, and possibly from metrology measurements that comprise both pupil- and field-scatterometry measurements. Certain embodiments comprise a computer program product comprising a non-transitory computer readable storage medium having computer readable program embodied therewith, the computer readable program configured to carry out any of the stages of method150; and possibly a metrology module configured to carry out any of the stages of method150. Any of the relevant stages of method150may be carried out by a computer processor, e.g., in processing unit(s)109. Algorithm Validity Flags Referring toFIG.11as a high level schematic flowchart, method160of deriving, providing and utilizing algorithm validity flags is presented, and explained in detail below. Method160comprises indicating inaccuracy in metrology measurements by calculating a difference between at least two values of at least one metrology metric, the at least two values derived from at least two metrology algorithms (stage163), and setting a threshold for the calculated difference (stage164). In certain embodiments, method160further comprises reporting the difference as a flag indicator for measurement inaccuracy (stage166) and possibly using the algorithm validity flag to improve accuracy and/or to further characterize the landscape (stage168). FIG.7is a high level schematic examplary illustration160A of an algorithm validity flag165and its derivation by method160, according to some embodiments of the invention. Algorithm validity flag165may be used to evaluate inaccuracies by comparing results from different algorithms. The inventors have found out that accuracy may be improved by using the pupil metric disclosed below. In the scatterometry overlay (SCOL) metrology the signals are expected to behave in an idealized way, which, in the linear approximation, means that the differential signals D1and D2, the overlay per-pixel and per-setup on the pupil in pupil scatterometry or the overlay per-setup in field scatterometry are determined by the proportionality coefficient between D1and D2. Denoting the true overlay by ϵ, the inaccuracy δϵper-pixelis given, in the linear approximation, by Equation 1, δϵper-pixel=ϵper-pixel−ϵ=u׃(D1,D2) Equation 1 with u being the per-pixel and/or per-setup deviation from the ideal signal (i.e., the deviation from the signal of an ideal target, with no inaccuracy) and ƒ(D1, D2) being a well-defined function that depends on the algorithm. For example, ƒ(D1, D2) may be ((D1−D2)−5>, where the brackets denote an average over measurement conditions. The functional form of δϵper-pixel(u) may be determined as follows. Given any concrete model for the deviation from the ideal signal u, an algorithm may be devised, which fits the model to the measured signal and provides an estimate of the overlay. However, the accuracy provided by different algorithms depends on the accuracy of the assumptions upon which they is based, so that there is a need for a method of comparing the accuracy of different algorithms. Method160provides a way to test the assumptions on which an algorithm is based, which goes beyond the usual goodness of fit measures. By the using the aforementioned model-based algorithm one gets estimates ƒalgo(D1, D2) and ualgo, the deviation from the ideal signal. These, in turn may be used to estimate various measurable quantities of another algorithm (for example, of the nominal scatterometry algorithm), in a non-limiting example, the variance of the per-pixel overlay over the pupil, which can then be compared to the measured quantities. Any mismatch is an indication that the assumptions behind the model on which the algorithm is based are not valid. In a non-limiting example, the variance off and u divided by the measured variance may be used as the flag. It is noted that due to the definition off, such a flag may be different from the actual variance. Any other appropriate flag may be used. Method160may be configured to provide flag165which is derived from the inaccuracies of two different algorithms161,162. Flag165is illustrated inFIG.7to drop below one, when the assumptions behind algorithm161fail, as is evident by the high inaccuracy of algorithm161in the regions of flag165being smaller than one. Certain embodiments comprise a computer program product comprising a non-transitory computer readable storage medium having computer readable program embodied therewith, the computer readable program configured to carry out any of the stages of method160; and possibly a metrology module configured to carry out any of the stages of method160. Any of the relevant stages of method160may be carried out by a computer processor, e.g., in processing unit(s)109. Certain embodiments comprise a flag indicator signal comprising the calculated difference as disclosed herein. Detection of Regions which are Proximate to Resonance Regions Referring toFIG.11as a high level schematic flowchart, method170is presented of deriving, providing and utilizing indications of regions that are proximate to resonance regions, and explained in detail below. Method170comprises indicating a proximate region in a landscape which is proximate to a resonance region (stage176), wherein the landscape comprises an at least partially continuous dependency of at least one metrology metric on at least one parameter and the resonance region in the landscape corresponds to a resonance of optical illumination in a measured location. Indicating176may be carried out by calculating a variability of pupil signal or at least one function thereof (stage172), and comparing the calculated variability with a predefined threshold, wherein surpassing the predefined threshold indicates the proximate region (stage174). FIG.8is a high level schematic examplary illustration170A of a flag175that indicates proximate regions(s)175A and their derivation by method170, according to some embodiments of the invention. Resonance proximity flag175may be used to indicate resonance regions95A, flat regions95B and intermediate regions95C, and in particular proximate regions175A which indicate that the recipe or setup approach a resonant region which is characterized by high inaccuracy. The inventors have found out that accuracy may be improved by using the pupil metric disclosed below. In pupil scatterometry measurements resonances can be detected by the existence of certain features in the pupil, such as zero-sensitivity pixels in the sensitivity pupil described in WIPO Publication No. 2014062972. However, it is desirable to detect also the vicinity of resonances in order to indicate approaching resonant regions. The vicinity of resonances may be detected by computing the variability of the pupil signals and/or any functional combination of them (stage172). Far from resonances95A, this ratio has a value close to zero (see flag175in illustration170A). In particular, flag175is equal to zero if the pupil signal is flat, which has been found to correspond to flat region95B in landscape95. Approaching to resonances95A the value of flag175increases, close to resonances95A the value of flag175is large, and at the peak of the value of flag175or very close thereto, the contours of inaccuracy are most prominent in the pupil image, at resonance region95A of landscape95. Illustration170A presents a non-limiting example of the changing of inaccuracy171and flag175as function of wavelength as the measurement parameter, at proximate region175A and at resonance region95A (at which illumination resonances in the measured stack). Certain embodiments comprise a computer program product comprising a non-transitory computer readable storage medium having computer readable program embodied therewith, the computer readable program configured to carry out any of the stages of method170; and possibly a metrology module configured to carry out any of the stages of method170. Any of the relevant stages of method170may be carried out by a computer processor, e.g., in processing unit(s)109. Certain embodiments comprise a flag indicator signal comprising the calculated variability and/or the proximate regions as disclosed herein. Identification of Non-Analytical Behavior of the Landscape FIG.9is a high level schematic flowchart of a method180of identifying of non-analytical behavior of the landscape, according to some embodiments of the invention. Method180may comprise improving accuracy by using the following pupil metric, which detects non-analytical (and analytical) behavior of various quantities on the pupil in pupil scatterometry, to detect resonances95A and flat regions95B. Moreover, the inventors have found out that in both pupil- and field-scatterometry, non-analytic behavior of various quantities as functions of various tool knobs (e.g., wavelength and/or polarization as non-limiting examples) may be used to detect resonances95A and flat regions95B. The inventors have found out that certain functions on the pupil181(in a non-limiting example, the per-pixel overlay) behave non-analytically near resonant regions95A. Similarly, certain functions in pupil- and field-scatterometry behave non-analytically as functions over setups (which may include wavelength, polarization, etc., as described above, seeFIG.2). This non-analytic behavior can be detected by fitting pupil function181to a basis of functions185which spans (at least at good approximation) the spaceof analytical functions on the pupil (available in pupil-scatterometry) and/or in the setup space (available in both pupil- and field-scatterometry). Basis185of analytic functions that spans the spacesufficiently well is denoted by {ƒi(k,s)}i=0N, where k stands for the pupil coordinates and s stands for generalized coordinates in setup space. The projection of a function ƒ(k) on the spaceis given approximately by minimizing the function expressed in Equation 2 with respect to the coefficients ai, where the norm is defined to be a function bounded from below (residual182). χ2({ai})=∫d2k dsNorm(ƒ(k,s)−Σi=1Naiƒi(k,s)) Equation 2 The inventors have observed that an analytic function on the pupil and/or setup space has a small residual χ2182, while a non-analytic function has a higher residual182, even if its divergence lies outside of the pupil. Therefore, indications184for approaching non-analytic regions of landscape95may be generated according to the value of residual182(e.g., with respect to a predefined threshold) and may be used to provide alerts186of inaccuracies. The inventors have found out that the major power of suggested method180is derived from its sensitivity regime—because not only a pupil and/or a setup region that includes a singularity has a large residual182χ2({ai}), but also pupils and/or setups ‘near’ a singularity (e.g., proximate regions175A) may exhibit a large residual182. The definition of ‘near’ in the pixel-setup space includes at least small setup changes and process variations. Therefore, residual182, χ2({ai}), may be used to assess whether unexpected changes in the process or the tool could impact the accuracy of the measurements. Referring toFIG.11as a high level schematic flowchart, method180of determining resonant regions in the landscape (wherein the landscape comprises an at least partially continuous dependency of at least one metrology metric on at least one parameter and the resonance region in the landscape corresponds to a resonance of optical illumination in a measured location) may comprise or be complemented by detecting non-analytic behavior of at least one metrology metric (stage180A) comprising: spanning a space of the analytic functions over pupil coordinates by a basis of analytic functions (stage185A), expressing the metrology metric in terms of the basis of analytic functions (stage185B) and estimating a residual of the expression(s) (stage182), wherein a residual larger than a predetermined threshold indicates the non-analytic behavior (stage186A). Certain embodiments comprise a computer program product comprising a non-transitory computer readable storage medium having computer readable program embodied therewith, the computer readable program configured to carry out any of the stages of method180; and possibly a metrology module configured to carry out any of the stages of method180. Any of the relevant stages of method150may be carried out by a computer processor, e.g., in processing unit(s)109. Certain embodiments comprise a flag indicator signal comprising the estimations as disclosed herein. Diagonal Target Cells The inventors have further found, that addition of diagonal target cells to target designs and/or target designs which comprise diagonal cells, may provide improved accuracy of the measurements in various embodiments of the invention. For example,FIG.10is a high level schematic illustration of examplary, non-limiting target designs190with diagonal cells, according to some embodiments of the invention. Metrology targets190may comprise a plurality of target cells (denoted schematically by S1, S2, S3, S4, {tilde over (S)}1, {tilde over (S)}2, {tilde over (S)}3, having periodic structures along at least two different and non-perpendicular measurement directions, e.g., one of X or Y and any of the oblique directions denoted by ϕ1, ϕ2. The cells are grouped in an examplary non-limiting manner into two alternative target designs190A (along the X direction with two alternative skewed cells S3, S4) and190B (along the X and Y directions with two alternative skewed cells S3, {tilde over (S)}3). At least one of the measurement directions may be at an angle ϕ (e.g., ϕ1, ϕ2) to another measurement direction (e.g., X, Y), wherein the angle ϕ is selected to reduce an effect of target cell asymmetry. In certain embodiments, the measurement directions may comprise at least three measurement directions at angles different from 0° and 90° with respect to each other (e.g., X, Y and two ϕ1in target design190B). It is noted that skewed cells (e.g., S3, S4, {tilde over (S)}3) may comprise elements192A of the respective periodic structures which are designed to be oblique to measurement axis X, yet comprise sub-elements192B which are along or perpendicular to measurement axis X (in the illustrated non-limiting case, along perpendicular axis Y), in order to enhance the printability of the skewed cells, while maintaining their skew design—as illustrated in detail192. In the following, details of target designs190are explained in a non-limiting manner with respect to target designs190A,190B, and the accuracy improvements are demonstrated. The conventional SCOL algorithm, e.g., a four-cell SCOL algorithm, relies on the inversion symmetry of the diffraction gratings composing the target cells (each target cell comprises a periodic structure along measurement direction X or perpendicularly thereto, in direction Y). The inventors have found out that in practice this assumption is violated to a certain degree due to different process variations, which lead eventually to the inaccuracy of the overlay measurement. Certain embodiments provide target rotation algorithms designed to get rid of the requirement of the inversion symmetry of the constituent gratings (periodic structures). This is achieved by using several target cells with different and non-orthogonal directions of the periodicity. Each cell may be composed of the grating over grating (two periodic structures in two different layers and along the same measurement direction), as in the conventional scatterometry targets. In some cells, certain intentional overlay (offset) may be introduced between the top and the bottom gratings. The difference from the conventional SCOL target is that some cells have their periodicity direction different from the X or Y axes. The target cell designs shown inFIG.10are merely illustrative, and omit in a non-limiting manner, details of design such as the two or more periodic structures along the same measurement direction (one over the other or side by side), the offsets therebetween, as well as segmentation and dummification details. Disclosed target designs190cause the scatterometry metrology signal from the skewed cells to be sensitive to the projection of the overlay onto the cell periodicity direction. As the overlay measured by a cell transforms like a vector under the rotation of the cell, the sensitivity of the scatterometry signal to the parasitic target asymmetry undergoes a different type of the transformation, either completely different, or partially different, depending, e.g., on the combination of the target design and the specific manufacturing process. In this manner, the overlay information may be decoupled from the information related to the parasitic target asymmetry. Using the difference in the transformation properties of the scatterometry signal sensitivity to the overlay, at one hand, and the parasitic asymmetries, on the other hand, a modeling for the latter may be developed and used for the practical implementation of the decoupling, as exemplified in non-limiting examples below, of four-cell target190A and six-cell target190B. The number and orientations of the cells may be designed and adjusted according to details of specific requirements. Target design190A comprises four cells denoted S1, S2, S3, S4and has the parameters listed in Table 1, with the overlay vector being defined as {right arrow over (ε)}=εx{circumflex over (x)}+εyŷ. TABLE 1An example for a four-cell architectureCellInducedTotal cellindexGrating direction {circumflex over (τ)}offsetoffset (OF)1{circumflex over (τ)} = {circumflex over (x)}0εx2{circumflex over (τ)} = {circumflex over (x)}f0≠ 0f0+ εx3{circumflex over (τ)} = {circumflex over (x)} cos ϕ1+ ŷ sin ϕ10εxcos ϕ1+ εysin ϕ14{circumflex over (τ)} = {circumflex over (x)} cos ϕ2+ ŷ sin ϕ20εxcos ϕ2+ εysin ϕ2 For each cell, the differential signals are calculated as a difference between the plus and minus first diffraction orders at the inversion symmetric pupil points. For brevity, in the following the dependence of the differential signal on the pupil point coordinate is omitted. The modelling assumption is that the differential signal has the same functional dependence on the total offset OF for all cells, irrespectively of the grating direction {circumflex over (τ)}, which is written in the linear approximation as in Equation 3. D(OF)=D(0)+D′(0)·OFEquation 3 This assumption is possible for relatively small angles ϕ1, ϕ2, but becomes inconsistent for large angle. For the four cells of target190A, the following differential signals are expected, as expressed in Equations 4, which constitute a linear system with four unknowns: D1=D(0)+D′(0)·εx D2=D(0)+D′(0)·(ƒ0+εx) D3=D(0)+D′(0)·(εxcos ϕ1+εysin ϕ1) D4=D(0)+D′(0)·(εxcos ϕ2+εysin ϕ2) Equations 4 Equations 4 may be reduced to Equations 5: {ɛx(1-cosϕ1)-ɛysinϕ1=f0D1-D3D2-D1=Aɛx(1-cosϕ2)-ɛysinϕ2=f0D1-D4D2-D1=BEquation5 Equations 5 may solved for the overlay components, as expressed in Equations 6, for the overlay vector {right arrow over (ε)}=εx{circumflex over (x)}+εyŷ: ɛx=Asinϕ2-Bsinϕ1(1-cosϕ1)sinϕ2-(1-cosϕ2)sinϕ1=Asinϕ2-Bsinϕ1sinϕ2-sinϕ1+sin(ϕ1-ϕ2)ɛy=A(1-cosϕ2)-B(1-cosϕ1)(1-cosϕ1)sinϕ2-(1-cosϕ2)sinϕ1=A(1-cosϕ2)-B(1-cosϕ1)sinϕ2-sinϕ1+sin(ϕ1-ϕ2)Equation6 In a non-limiting manner, Table 2 provides the expressions for two particular examples of the relation between the angles ϕ1, ϕ2. TABLE 2Two non-limiting examples for parameters of target design 190A.Example 1Example 2ϕ1= ϕ, ϕ2= 2ϕϕ1= −ϕ2= ϕ{εx=B-2Acosϕ4sin2ϕ2εy=B-4Acos2ϕ22sinϕ{εx=(A+B)4sin2ϕ2εy=B-A2sinϕ Target design190B comprises six cells denoted S1, S2, S3, {tilde over (S)}1, {tilde over (S)}2, {tilde over (S)}3and has the parameters listed in Table 3, with the overlay vector being defined as {right arrow over (ε)}=εx{circumflex over (x)}+εyŷ. TABLE 3An example for a six-cell architectureCellInducedTotal cellindexGrating direction {circumflex over (τ)}offsetoffset (OF)1{circumflex over (τ)} = {circumflex over (x)}0εx2{circumflex over (τ)} = {circumflex over (x)}f0≠ 0f0+ εx3{circumflex over (τ)} = {circumflex over (x)} cos ϕ1+ ŷ sin ϕ10εxcos ϕ1+ εysin ϕ14{circumflex over (τ)} = ŷ0εy5{circumflex over (τ)} = ŷf0≠ 0f0+ εy6{circumflex over (τ)} = −{circumflex over (x)} sin ϕ1+ ŷ cos ϕ10−εxsin ϕ1+ εycos ϕ1 Three cells in target design190B, S1, S2, S3, constitute a x-set of cells (with respect to measurement direction X), and the other three cells, {tilde over (S)}2, {tilde over (S)}3, constitute a y-set of cells (with respect to measurement direction Y). For each set the differential signal parameters expressed in Equations 7 may be assumed: Dx(OF)=Dx(0)+Dx′(0)·OF; Dy(OF)=Dy(0)+Dy′(0)·OFEquations 7 The modelling assumption is that the differential signal have same functional dependence on the total offset OF for all cells in a given set irrespectively of the grating direction {circumflex over (τ)}. This assumption is plausible for relatively small angle ϕ1, but will become inconsistent for large angle. For the six cells of target190B, the following differential signals are expected, as expressed in Equations 8, which constitute a linear system with six unknowns: D1=Dx(0)+Dx′(0)·εx D2=Dx(0)+Dx′(0)·(ƒ0+εx) D3=Dx(0)+Dx′(0)·(εxcos ϕ1+εysin ϕ1) D4=Dy(0)+Dy′(0)·εy D5=Dy(0)+Dy′(0)·(ƒ0+εy) D6=Dy(0)+Dy′(0)·(−εxsin ϕ1+εycos ϕ1). Equations 8 Equations 8 may be reduced to Equations 9: {ɛx(1-cosϕ1)-ɛysinϕ1=D1-D3Dx′(0)=f0D1-D3D2-D1=Aɛxsinϕ1+ɛy(1-cosϕ1)=D4-D6Dy′(0)=f0D4-D6D5-D4=BEquation9 Equations 9 may solved for the overlay components, as expressed in Equations 10, for the overlay vector {right arrow over (ε)}=εx{circumflex over (x)}+εyŷ: {ɛx=A(1-cosϕ1)+Bsinϕ12-2cosϕ1ɛy=B(1-cosϕ1)-Asinϕ12-2cosϕ1Equation10 The examples given above used a specific modelling assumption made for the exemplification purposes. In practice, different assumption could be used, e.g., based on simulations or calibration measurements or theory, and provide a likewise sound basis for using target designs190to improve the accuracy of the metrology measurements, in particular with respect to asymmetric process variation. Referring toFIG.11as a high level schematic flowchart, target design method195may comprise adding to target cells having periodic structures along a measurement direction, at least one skewed target cell having a different and non-perpendicular direction with respect to the measurement direction (stage196), and optionally, designing the at least one skewed target cell to have a direction at an angle ϕ to the measurement direction, wherein the angle ϕ is selected to reduce an effect of target cell asymmetry (stage197). Certain embodiments comprise a computer program product comprising a non-transitory computer readable storage medium having computer readable program embodied therewith, the computer readable program configured to carry out any of the stages of method195; and possibly a target design module configured to carry out any of the stages of method195. Any of the relevant stages of method195may be carried out by a computer processor, e.g., in processing unit(s)109. Certain embodiments comprise target design file(s) and/or measurement signals of corresponding targets190, possibly derived by method195, as disclosed herein. Any of the disclosed methods and tools may be combined in actual metrology methods and tools in any operable combination to add up the benefits provided by different embodiments and aspects of the disclosed invention. For example, stages from methods100,120,130,140,150,160,170,180and195may be combined. For example, any of the following embodiments may be used separately or combined:(i) Using self-consistency as an indicator and test for accuracy in metrology. Defining the diversity and independence of setups and the use of clustering methods to perform the self-consistency tests (see e.g., method100). In particular, Diversity may be expressed by the identification of measurements that are found to be independent. The dependency may be found by correlation of pupil derived metrics. Clustering may be found by graph theoretic or machine learning techniques such as cliques, hierarchical clustering or distribution based clustering. When clustering is done the thresholds may be determined a priory or by an iterative process such finding a plateau or an intrinsic scale. Each measurement may be handled as a point in n dimensional space, for example measurements on n locations on a wafer. Dimension reduction maps this space into lower dimensional space of parameters of interest. Once all the clusters have been identified, ranking the clusters is performed with collective group metrics or with metrics of representatives.(ii) Allowing setup-flexibility such that each measurement may be made with an individual set of setup parameters, in order to increase robustness to process variations, improve measurability, and decrease inaccuracy, without significantly degrading the MAM (move-acquire-measure) time (see, e.g., methods100and120). The optimization of accuracy in the landscape may be achieved by finding parametric sub-spaces in the landscape having a better accuracy than achieved in the prior art by simple fixing of specific measurement parameters. The combination of parameters provided by such sub-spaces enables to change multiple parameters together in a correlated manner and as a function of space and/or time. Additionally, combinations of disclosed methods provide finding setups that are best correlated to external references in a way that treats the uncertainties involved, as well as the use of self-consistency, clustering algorithms, etc. in setup optimization and control by use of advanced algorithms.(iii) In certain coordinate systems, the slope of the large principal axis provides information on the overlay free of certain types of inaccuracy-causing biases (see e.g., method130). The use of noise reduction techniques in pupil scatterometry comprises Y-symmetrization, filtering and pupil calibration with reference images(iv) The fusion of measurements into a single one and generalizing the nominal overlay algorithms or generalization thereof (see e.g., method140). Advanced pupil analysis and the merging of setups into generalized pupils improve the accuracy of the measurements. Combining multiple measurements from multiple setups in pupil space further improves accuracy. Moreover, disclosed methods provide an optimization of the weighing in combined pupil space of multiple measurements by extremizing a pupil derived metric.(v) The ratio between the large and small eigenvalues of the covariance matrix gives an indication of the stability of the measurement and its error (see e.g., method150). Moreover, computing the overlay and its quality by using the principal components of multiple pixels, measurements and setups further increases the achieved accuracy of the measurements.(vi) Using an estimation of the deviation of the pupil scatterometry signal from its ideal form obtained from an algorithm based on modeling the signal, a measure of the validity of the assumptions at the basis of that model may be derived, by using the knowledge of the deviation in order to predict other measureable quantities. Failure of these predictions to match the measurements serves as an indication that the assumptions at the base of the model-based algorithm failed (see e.g., method160). Flags for testing the validity of the assumptions at the basis of a model to which the measured data is fitted by using its prediction for other measureable quantities.(vii) A set of flags which indicate a nearby resonance in the landscape by checking the variance of the signal across its independently defined sub-measurements like pupil pixels in pupil scatterometry or signal harmonics in imaging (see e.g., method170). Some flags may be used to detect resonances even when a zero-sensitivity contour is not present on the pupil by using the variability and the analyticity of appropriate functions on the pupil. Disclosed methods allow the use of resonant setups and other setups which are deemed inadequate for single setup algorithms in the prior art.(viii) The detection of non-analytic behaviors in the signal that reflect near-by resonance behavior and/or contrast reversals in the signal of the involved setup and\or close to it on the landscape (see e.g., method180).(ix) Novel target design that uses the different representations of the rotation group for the overlay and for the pattern asymmetry to separate signal asymmetry from the overlay and signal asymmetry from bar asymmetry (see e.g., method195and targets190). The novel target designs allow to decouple the overlay from the pattern asymmetry and, thus, to relax the critical assumption of the target pattern inversion symmetry applied in the standard overlay scatterometry targets. Combinations of these embodiments provide the following examplary advantages over the prior art:(i) Reduced sensitivity to the initial set of setups due to graph theoretic properties.(ii) Provision of a more faithful description of the structure of relations between setups and their grouping.(iii) Identification of equivalence classes in data, and avoidance of over-representation of physically similar measurements or recurring recipes.(iv) Ranking of different clusters, derived from collective properties of cluster members or properties of a representative recipe of each cluster.(v) Novel flags that derive their existence and usefulness from global features of the landscape and reflected in self-consistency.(vi) Indications of proximity to problematic measuring conditions (resonances), even at some distance away from the resonances leading to measurements more robust to symmetric process variations.(vii) Detection of the validity of model-based algorithms on a given set of measured data enabling the selection of an accurate model-based algorithm for a given set of measured data.(viii) Removal of some biases from overlay measurements and assessing the quality of the measurements based on the distribution of the measurements (where each pixel counts as a measurement) in the differential signals plane.(ix) The use of multiple pupil algorithms makes the reported metrology metric less sensitive to sampling and gives an estimate of this robustness.(x) The use of multiple pupil algorithms instead of reference metrology to estimate the accuracy of single setup measurements. Aspects of the present invention are described above with reference to flowchart illustrations and/or portion diagrams of methods, apparatus (systems) and computer program products according to embodiments of the invention. It will be understood that each portion of the flowchart illustrations and/or portion diagrams, and combinations of portions in the flowchart illustrations and/or portion diagrams, can be implemented by computer program instructions. These computer program instructions may be provided to a processor of a general purpose computer, special purpose computer, or other programmable data processing apparatus to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing apparatus, create means for implementing the functions/acts specified in the flowchart and/or portion diagram or portions thereof. These computer program instructions may also be stored in a computer readable medium that can direct a computer, other programmable data processing apparatus, or other devices to function in a particular manner, such that the instructions stored in the computer readable medium produce an article of manufacture including instructions which implement the function/act specified in the flowchart and/or portion diagram or portions thereof. The computer program instructions may also be loaded onto a computer, other programmable data processing apparatus, or other devices to cause a series of operational steps to be performed on the computer, other programmable apparatus or other devices to produce a computer implemented process such that the instructions which execute on the computer or other programmable apparatus provide processes for implementing the functions/acts specified in the flowchart and/or portion diagram or portions thereof. The aforementioned flowchart and diagrams illustrate the architecture, functionality, and operation of possible implementations of systems, methods and computer program products according to various embodiments of the present invention. In this regard, each portion in the flowchart or portion diagrams may represent a module, segment, or portion of code, which comprises one or more executable instructions for implementing the specified logical function(s). It should also be noted that, in some alternative implementations, the functions noted in the portion may occur out of the order noted in the figures. For example, two portions shown in succession may, in fact, be executed substantially concurrently, or the portions may sometimes be executed in the reverse order, depending upon the functionality involved. It will also be noted that each portion of the portion diagrams and/or flowchart illustration, and combinations of portions in the portion diagrams and/or flowchart illustration, can be implemented by special purpose hardware-based systems that perform the specified functions or acts, or combinations of special purpose hardware and computer instructions. In the above description, an embodiment is an example or implementation of the invention. The various appearances of “one embodiment”, “an embodiment”, “certain embodiments” or “some embodiments” do not necessarily all refer to the same embodiments. Although various features of the invention may be described in the context of a single embodiment, the features may also be provided separately or in any suitable combination. Conversely, although the invention may be described herein in the context of separate embodiments for clarity, the invention may also be implemented in a single embodiment. Certain embodiments of the invention may include features from different embodiments disclosed above, and certain embodiments may incorporate elements from other embodiments disclosed above. The disclosure of elements of the invention in the context of a specific embodiment is not to be taken as limiting their use in the specific embodiment alone. Furthermore, it is to be understood that the invention can be carried out or practiced in various ways and that the invention can be implemented in certain embodiments other than the ones outlined in the description above. The invention is not limited to those diagrams or to the corresponding descriptions. For example, flow need not move through each illustrated box or state, or in exactly the same order as illustrated and described. Meanings of technical and scientific terms used herein are to be commonly understood as by one of ordinary skill in the art to which the invention belongs, unless otherwise defined. While the invention has been described with respect to a limited number of embodiments, these should not be construed as limitations on the scope of the invention, but rather as exemplifications of some of the preferred embodiments. Other possible variations, modifications, and applications are also within the scope of the invention. Accordingly, the scope of the invention should not be limited by what has thus far been described, but by the appended claims and their legal equivalents. | 70,757 |
11862523 | DESCRIPTION OF THE EMBODIMENTS The following disclosure provides many different embodiments, or examples, for implementing different features of the present disclosure. Specific examples of components and arrangements are described below to simplify the present disclosure. These are, of course, merely examples and are not intended to be limiting. For example, the formation of a first feature over or on a second feature in the description that follows may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features may be formed between the first and second features, such that the first and second features may not be in direct contact. In addition, the present disclosure may repeat reference numerals and/or letters in the various examples. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed. Further, spatially relative terms, such as “beneath,” “below,” “lower,” “above,” “upper” and the like, may be used herein for ease of description to describe one element or feature's relationship to another element(s) or feature(s) as illustrated in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The apparatus may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein may likewise be interpreted accordingly. Other features and processes may also be included. For example, testing structures may be included to aid in the verification testing of the 3D packaging or 3DIC devices. The testing structures may include, for example, test pads formed in a redistribution layer or on a substrate that allows the testing of the 3D packaging or 3DIC, the use of probes and/or probe cards, and the like. The verification testing may be performed on intermediate structures as well as the final structure. Additionally, the structures and methods disclosed herein may be used in conjunction with testing methodologies that incorporate intermediate verification of known good dies to increase the yield and decrease costs. FIG.1AtoFIG.1Gillustrate a process flow for fabricating an integrated fan-out package in accordance with some embodiments of the present disclosure. Referring toFIG.1A, a wafer100including a plurality of semiconductor dies200arranged in, for example, an array is provided. Before a wafer dicing process is performed on the wafer100, the semiconductor dies200of the wafer100are connected one another. In some embodiments, the wafer100includes a semiconductor substrate110, a plurality of conductive pads120formed on the semiconductor substrate110, and a passivation layer130. The passivation layer130is formed over the substrate110and has a plurality of contact openings132such that the conductive pads120are partially exposed by the contact openings132of the passivation layer130. For example, the semiconductor substrate110may be a silicon substrate including active components (e.g., transistors or the like) and passive components (e.g., resistors, capacitors, inductors or the like) formed therein; the conductive pads120may be aluminum pads, copper pads or other suitable metal pads; and the passivation layer130may be a silicon oxide layer, a silicon nitride layer, a silicon oxy-nitride layer or a dielectric layer formed by other suitable dielectric materials. As shown inFIG.1A, in some embodiments, the wafer100may optionally include a post-passivation layer140formed over the passivation layer130. The post-passivation layer140covers the passivation layer130and has a plurality of contact openings142. The conductive pads120exposed by the contact openings132of the passivation130are partially exposed by the contact openings142of the post passivation layer140. For example, the post-passivation layer140may be a polyimide (PI) layer, a polybenzoxazole (PBO) layer, or a dielectric layer formed by other suitable polymers. Referring toFIG.1B, a plurality of conductive pillars150are formed on the conductive pads120. In some embodiments, the conductive pillars150are plated on the conductive pads120. The plating process of conductive pillars150is described in detail below. First, a seed layer is sputtered onto the post-passivation layer140and the conductive pads120exposed by the contact openings142. A patterned photoresist layer (not shown) is then formed over the seed layer by photolithography, wherein the patterned photoresist layer exposes portions of the seed layer that are corresponding to the conductive pads120. The wafer100including the patterned photoresist layer formed thereon is then immersed into a plating solution of a plating bath such that the conductive pillars150are plated on the portions of the seed layer that are corresponding to the conductive pads120. After the plated conductive pillars150are formed, the patterned photoresist layer is stripped. Thereafter, by using the conductive pillars150as a hard mask, portions of the seed layer that are not covered by the conductive pillars150may be removed through etching until the post passivation layer140is exposed, for example. In some embodiments, the conductive pillars150are plated copper pillars. Referring toFIG.1C, after the conductive pillars150are formed, a protection layer160is formed on the post passivation layer140so as to cover the conductive pillars150. In some embodiments, the protection layer160may be a polymer layer having sufficient thickness to encapsulate and protect the conductive pillars150. For example, the protection layer160may be a polybenzoxazole (PBO) layer, a polyimide (PI) layer or other suitable polymers. In some alternative embodiments, the protection layer160may be made of inorganic materials. Referring toFIG.1D, a back side grinding process is performed on the rear surface of the wafer100after the protection layer160is formed. During the back side grinding process, the semiconductor substrate110is ground such that a thinned wafer100′ including a thinned semiconductor substrate110′ is formed. Referring toFIG.1E, after performing the back side grinding process, a wafer dicing process is performed on the thinned wafer100′ such that the semiconductor dies200in the wafer100′ are singulated from one another. Each of the singulated semiconductor dies200includes a semiconductor substrate110a, the conductive pads120formed on the semiconductor substrate110a, a passivation layer130a, a post passivation layer140a, the conductive pillars150, and a protection layer160a. As shown inFIG.1DandFIG.1E, the materials and the characteristics of the semiconductor substrate110a, the passivation layer130a, the post passivation layer140a, and the protection layer160aare the same as those of the semiconductor substrate100, the passivation layer130, the post passivation layer140, and the protection layer160. Thus, the detailed descriptions of the semiconductor substrate110a, the passivation layer130a, the post passivation layer140a, and the protection layer160aare omitted. As shown inFIG.1DandFIG.1E, during the back side grinding and the wafer dicing processes, the protection layer160and160amay protect the conductive pillars150of the semiconductor dies200. In addition, the conductive pillars150of the semiconductor dies200may be protected from being damaged by sequentially performed processes, such as pick-up and placing process of the semiconductor dies200, molding process, and so on. Referring toFIG.1F, after the semiconductor dies200are singulated from the thinned wafer100′ (shown inFIG.1D), a carrier C having a de-bonding layer DB and a dielectric layer DI formed thereon is provided, wherein the de-bonding layer DB is between the carrier C and the dielectric layer DI. In some embodiments, the carrier C is a glass substrate, the de-bonding layer DB is a light-to-heat conversion (LTHC) release layer formed on the glass substrate, and the dielectric layer DI is a polybenzoxazole (PBO) layer formed on the de-bonding layer DB, for example. As shown inFIG.1F, in some embodiments, one of the semiconductor dies200including the conductive pads120, the conductive pillars150, and a protection layer160aformed thereon is picked and placed on the dielectric layer DI. The semiconductor die200is attached or adhered on the dielectric layer DI through a die attach film (DAF), an adhesion paste or the like. In some alternative embodiments, more than one of the semiconductor dies200are picked and placed on the dielectric layer DI, wherein the semiconductor dies200placed on the dielectric layer DI may be arranged in an array. Referring toFIG.1G, an insulating material210is formed on the dielectric layer DI to cover a semiconductor die200. In some embodiments, the insulating material210is a molding compound formed by a molding process. The conductive pillars150and the protection layer160aof the semiconductor die200are covered by the insulating material210. In other words, the conductive pillars150and the protection layer160aof the semiconductor die200are not revealed and are well protected by the insulating material210. In some embodiments, the insulating material210includes epoxy or other suitable dielectric materials. In some alternative embodiments, a plurality of semiconductor dies of at least two types are placed on the dielectric layer DI, where one of the types is same as the type of the semiconductor dies200and another one of the types is different from the type of the semiconductor dies200. The insulating material210is formed on the dielectric layer DI to cover the semiconductor dies of the at least two types. In some embodiments, the semiconductor dies of the at least two types are placed on the dielectric layer DI, and the insulating material210are formed on the semiconductor dies of the at least two types to generate a reconstructed wafer. The reconstructed wafer may be used in a grinding process, where an endpoint of the grinding process is detected in embodiments of the disclosure. In some embodiments,FIG.1Hillustrates a schematic block diagram of an endpoint detection system including an apparatus for detecting an endpoint of a grinding process according to an exemplary embodiment of the disclosure. Referring toFIG.1H, an endpoint detection system1000of the present embodiment may include a detection apparatus1010and a grinding tool1020. The grinding tool1020is configured to perform a grinding process on a reconstructed wafer1040to remove portions of an insulating layer formed by molding compound and other materials of the reconstructed wafer1040. In some embodiments, the grinding tool1020may include one or more grinding elements (not shown) that are driven to perform the grinding process. The grinding tool1020stops the grinding process at an endpoint of the grinding process. In some embodiments, the detection apparatus1010is configured to detect the endpoint of the grinding process of the grinding tool1040. The detection apparatus1010may include an endpoint detection (EPD) sensor1012, an EPD controller1014and a timer1016. The EPD controller1014is connected to the EPD sensor1012through a connecting device such as system bus, USB, firewire, thunderbolt, universal asynchronous receiver/transmitter (UART), serial peripheral interface bus (SPI), which is not limited herein. The EPD sensor1012is configured to periodically sense an interface of the reconstructed wafer1040to generate a thickness signal STHK1in a predetermined period such as 1 microsecond (μs) or a period ranging from 0.1 to 100 μs, which is not limited herein. In some embodiments, the reconstructed wafer1040may include a plurality of dies of at least two types and insulating material filled into the space between the dies and above the dies. The insulating material may form an insulating layer of the reconstructed wafer1040. The thickness signal STHK1sensed by the EPD sensor1012indicates thicknesses from a surface of the insulating layer of the reconstructed wafer1040to interfaces of the dies. In some embodiments, the thickness signal STHK1may include time-series data of the thicknesses from the surface of the reconstructed wafer's insulating layer to the interfaces of the dies. In other words, the thickness signal STHK1may include a thickness corresponding to each time point of the grinding process. In some embodiments, the EPD sensor1012senses the interface of the reconstructed wafer1040according to an optical signal scattered from the surface of the reconstructed wafer1040. The EPD sensor1012may emit an incident optical signal to the reconstructed wafer1040and receive reflected optical signals from the reconstructed wafer1040. The thickness signal is obtained by analyzing characteristics of the incident optical signal and the reflected optical signals, such as time-of-flight of the optical signals, intensity of the reflected optical signal (reflexivity), and the like. The timer1016is configured to generate a clock signal CLK having a plurality of pulses with a time interval. In some embodiments, the timer1016may include a clock generator (not shown) for generating the clock signal CLK with a periodic waveform. The time interval may include a pre-determined number of pulses of the clock signal CLK. In some embodiments, the EPD controller1014is coupled to the EPD sensor1012and the timer1016to receive the thickness signal STHK1from the EPD sensor1012and the clock signal CLK from the timer1016. The EPD sensor1012is configured to filter the thickness signal STHK1according to the clock signal CLK to output a filtered thickness signal STHK2. Particularly, the EPD sensor1012determines a thickness extremum among the thicknesses in the thickness signal STHK1within each time interval. The filtered thickness signal STHK2includes the thickness extrema determined in the time intervals. In some embodiments, the thickness extremum may be a thickness maximum or a thickness minimum. When the thickness extremum is the thickness maximum, the EPD controller1014determine a thickness maximum among the thicknesses of the thickness signal STHK1within each time interval, and output the determined thickness maximum to the grinding tool1020through the filtered thickness signal STHK2. Alternatively, when the thickness extremum is a thickness minimum, the EPD controller1014determine a thickness minimum among the thickness of the thickness signal STHK1within each time interval, and output the determined thickness minimum to the grinding tool1020through the filtered thickness signal STHK2. In some embodiments, a determination of whether the thickness extremum to be the thickness maximum or the thickness minimum may be done according to a selection of a target die among the dies of different types included in the reconstructed wafer1040. For example, if an average thickness of the target die is larger than the average thickness of the dies of other types in the reconstructed wafer1040, the thickness extremum is determined as the thickness maximum, and the thickness signal STHK1is filtered to output the thickness maximum among the thicknesses in the thickness signal STHK1generated within each time interval. Alternatively, if the average thickness of the target die is smaller than the average thickness of the dies of other types in the reconstructed wafer1040, the thickness extremum is determined as the thickness maximum, and the thickness signal STHK1is filtered out to output the thickness minimum among the thicknesses in the thickness signal STHK1generated within each time interval. In some embodiments, the endpoint detection system1000further includes an EPD software1030that may include a set of instructions and program codes for operating the grinding tool1020in different operating modes. The operating modes of the grinding tool1020may include a time mode, in which the grinding tool1020performs a grinding process until the endpoint is reached. The endpoint of the grinding process is determined according to the thickness extrema of the filtered thickness signal (e.g., STHK2). In addition to the time mode, the EPD software1030may be used to operate the grinding tool1020in different operating modes such as average target mode. In an alternative embodiment of the disclosure, the endpoint of the grinding process is determined according to the thickness signal corresponding to the target dies and a thickness difference between the dies of the first type and the dies of the second type. In some embodiments, if the thickness difference between the dies of the first type and the dies of the second type is within a proper range (e.g. 5 to 50 microns), the thickness difference is further considered to determine the endpoint of the grinding process. That is because, during the grinding process, the dies with smaller thickness will be ground out first, and if the thickness maximums are used to determine the endpoint of the grinding process, the thickness difference between the dies of two types may be used as a limit to the endpoint of the grinding process so as to ensure that the dies with smaller thickness will not be ground out. It is noted that, if the thickness difference is relatively small (e.g. less than 5 microns), the thickness difference may not be an issue for determining the endpoint and will not be considered. If the thickness difference is large (e.g. larger than 50 microns), instead of using the thickness maximums for determining the endpoint of the grinding process, the thickness minimums are used for determining the endpoint of the grinding process so as to increase the accuracy of grinding process. In some embodiments,FIG.2illustrates a schematic block diagram of an endpoint detection system including an apparatus for detecting an endpoint of a grinding process according to another exemplary embodiment of the disclosure. Referring toFIG.2, an endpoint detection system2000of the present embodiment may include an EPD sensor2012, an EPD controller2014and a grinding apparatus2020. The EPD sensor2012is configured to sense a surface of the reconstructed wafer1040to output a thickness signal STHK1. The EPD sensor2012inFIG.2is similar to the EPD sensor1012shown inFIG.1H, thus detailed description about the EPD sensor2012is omitted hereafter. In some embodiments, the EPD controller2014is coupled to the EPD sensor2012, and is configured to control operations of the EPD sensor2012. The EPD controller2014may receive the thickness signal STHK1generated by the EPD sensor2012, and perform some pre-processing operations such as averaging or sampling on the thickness signal STHK1to generate a thickness signal STHK3. Alternatively, the EPD controller2014may just forward the thickness signal STHK1as the thickness signal STHK3to the grinding apparatus2020. In other words, the thickness signal STHK3may be the same or may be different from the thickness signal STHK1. The grinding apparatus2020includes a grinding controller2022, a timer2024and a connecting device2026. The connecting device2026is, for example, any wired or wireless interface compatible to the EPD controller2014such as USB, firewire, thunderbolt, universal asynchronous receiver/transmitter (UART), serial peripheral interface bus (SPI), WiFi, or Bluetooth, which is not limited herein. The connecting device2026is used to connect the grinding apparatus2020with the EPD controller2014, such that the thickness signal STHK3is provided from the EPD controller2014to the grinding apparatus2020through the connecting device2026. The timer2024is configured to generate a clock signal CLK having a plurality of pulses with a time interval. The timer2024may have the similar function, structure, and operations to the timer1016, thus the detailed description about the timer2024is omitted hereafter. The grinding controller2022is coupled to the connecting device2026and the timer2024to receive the thickness signal STHK3through the connecting device2026and the clock signal CLK from the timer2024. The grinding controller2022is configured to filter the thickness signal STHK3according to the clock signal CLK to output a filtered thickness signal STHK2. The filtered thickness signal STHK2is used to determine an endpoint of a grinding process. Particularly, the grinding controller2022determines a thickness extremum among the thicknesses in the thickness signal STHK3within each time interval. The filtered thickness signal STHK2includes the thickness extrema determined in the time intervals. In some embodiments, the thickness extremum may be a thickness maximum or a thickness minimum. When the thickness extremum is the thickness maximum, the grinding controller2022determine a thickness maximum among the thicknesses of the thickness signal STHK3within each time interval to generate the filtered thickness signal STHK2. Alternatively, when the thickness extremum is a thickness minimum, the grinding controller2022determine a thickness minimum among the thickness of the thickness signal STHK3within each time interval to generate the filtered thickness signal STHK2. In some embodiments, a target die among the dies of different types included in the reconstructed wafer1040may be used to determine whether the thickness maximum or the thickness minimum of the thickness signal STHK3is used to generate the filtered thickness signal STHK2. In some embodiments, if an average thickness of the target die is larger than the average thickness of the dies of a specific type, the thickness extremum is the thickness maximum, and the filtered thickness signal STHK2is generated according to the thickness maximum among the thicknesses in the thickness signal STHK3generated within each time interval. Alternatively, if the average thickness of the target die is smaller than the average thickness of the dies of the specific type, the thickness extremum is the thickness minimum, and the filtered thickness signal STHK2is generated according to the thickness minimum among the thicknesses in the thickness signal STHK3generated within each time interval. In some embodiments, the endpoint detection system2000further includes an EPD software2030that may include a set of instructions and program codes for operating the grinding apparatus2020. The EPD software2030shown inFIG.2is similar to the EPD software1030shown inFIG.1H, thus the detailed description about the EPD software2030inFIG.2is omitted hereafter. In some embodiments, the apparatus for detecting an endpoint of a grinding process of the application includes all the elements in the endpoint detection systems as disclosed inFIG.1HandFIG.2, such as EPD controller, EPD sensor, timer, connecting device, grinding tool, and EPD software, which are not limited herein. That is, the apparatus for detecting an endpoint of a grinding process of the application may integrate functions of the detection apparatus1010inFIG.1, the grinding apparatus2020inFIG.2, and the EPD software. FIG.3Aillustrates a cross-sectional view of a reconstructed wafer portion including multiple dies before a grinding process according to an exemplary embodiment of the disclosure.FIG.3Billustrates a cross-sectional view of a reconstructed wafer portion including multiple dies during a grinding process according to an exemplary embodiment of the disclosure. Referring toFIG.3A, a portion of the reconstructed wafer1040includes a first die200as exemplified inFIG.1Gand a second die300, and insulating layer310. In some embodiments, the first die200and the second die300are one of a logic, a controller IC, a memory, an application processor, etc., and a type of the first die200is different from a type of the second die300. The second die300may be fabricated through the process as illustrated inFIGS.1A to1G, which is not repeated herein. The insulating layer310is formed with insulating material that is filled in the space between the dies200,300and covering the dies200,300. Referring toFIG.1HandFIG.3A, in some embodiments, the EPD sensor1012may emit incident signal S to the reconstructed wafer1040and receive signals S1and S2reflected from the reconstructed wafer1040to generate the thickness signal STHK1. The signal S1is a reflected signal of the incident signal S on the interface DS1of the first die200, and the signal S2is a reflected signal of the incident signal S on the interface DS2of the second die300. The incident signal S and the reflected signals S1and S2may be manipulated to calculate thicknesses from the surface WS1of the insulating layer310to the interfaces of the first die200and the second die300, respectively. Particularly, the incident signal S and the reflected signal S1may be manipulated to calculate thicknesses from the surface WS1of the insulating layer310to the interface DS1of the first die200, and the incident signal S and the reflected signal S2may be manipulated to calculate thicknesses from the surface WS1of the insulating layer310to the interface DS2of the second die300. The thickness signal STHK1may include thicknesses generated according to the incident signal S and the reflected signals S1and S2. In some embodiments, the signals S, S1and S2are optical signals, but any other type of signal that is capable of detecting thickness may be applied in the embodiment. Referring toFIG.3AandFIG.3B, in some embodiments, as a grinding process is performed on the reconstructed wafer1040, a portion311of the insulating layer310is ground and a surface of the insulating layer310is changed from the surface WS1to a surface WS2. The grinding process is ended according to an endpoint that is detected according to embodiment of the disclosure. Referring toFIG.3AtoFIG.3C, an exemplary thickness signal that includes a plurality of thicknesses THK1and a plurality of thicknesses THK2are illustrated, wherein the x-axis represents Time (s) of measurement and the y-axis represents measured thickness THK (um). The thicknesses THK2are the thicknesses measured from the surface WS1of the insulating layer310to the interface DS1of the first die200; and the thicknesses THK1are thicknesses measured from the surface WS1of the insulating layer310to the interface DS2of the second die300. In some embodiments, the thickness signal is periodically sensed from the EPD sensor, and the thicknesses THK1and THK2are time-series data. FIG.4illustrates time intervals and a thickness extremum in each of the time intervals according to an exemplary embodiment of the disclosure. Referring toFIG.4, the x-axis represents Time (s) of measurement, the y-axis represents measured thickness THK (um), and a thickness signal including a plurality of measured thicknesses are separated by a plurality of time intervals T. The time interval T may be determined according to a clock signal provided by a timer. For example, the time interval T may be determined according to the clock signal CLK generated by the timer1016shown inFIG.1H. Each of the thicknesses in the thickness signal represents a thickness from the surface of the insulating layer of the reconstructed wafer to the surface of the dies in the reconstructed wafer at a particular time point. Within each time interval T, a thickness extremum (e.g., thickness maximum or thickness minimum) among the thicknesses within the time interval T is determined. In the embodiment shown inFIG.4, the thickness extremum is the thickness maximum Max1, but in another embodiment, the thickness extremum may be the thickness minimum. The thickness maximum Max1within each of the time intervals T are combined to generate a filtered thickness signal that is used to detect an endpoint of a grinding process performed on the reconstructed wafer. In some embodiments,FIG.5AtoFIG.5Cillustrate thickness signals according to some exemplary embodiments of the disclosure, wherein the x-axis represents Time (s) of measurement and the y-axis represents measured thickness THK (um). Referring toFIG.5A, a thickness signal including a plurality of thicknesses THK1and a plurality of thicknesses THK2is illustrated. In some embodiments, the thicknesses THK1represents thicknesses from a surface of the insulating layer of the reconstructed wafer to the interface of a first die, and the thicknesses THK1represents thicknesses from a surface of the insulating layer of the reconstructed wafer to the interface of a second die. In some embodiments, the thickness signal shown inFIG.5Ais the thickness signal output by the EDP sensor. For example, the thickness signal shown inFIG.5Amay be the thickness signal STHK1output by the EPD sensor1012shown inFIG.1H. Alternatively, the thickness signal shown inFIG.5Amay be the thickness signal STHK1output by the EPD sensor2012shown inFIG.2. Referring toFIG.5B, a filtered thickness signal STHK2which includes thickness extrema of a thickness signal STHK1is illustrated. The filtered thickness signal STHK2may include thickness maxima of the thickness signal STHK1, where each of the thickness maxima is a thickness maximum of the thickness signal STHK1within one of a plurality of time intervals. Alternatively, in some embodiments, the filtered thickness signal may include thickness minima of the thickness signal, where each of the thickness minima is a thickness minimum of the thickness signal within one of a plurality of time intervals. The filtered thickness signal STHK2is used to determine an endpoint of a grinding process. FIG.5Cillustrates thickness signals according to an exemplary embodiment of the disclosure. Referring toFIG.5C, thickness signal in different timings are illustrated. In the time period from t0to t1, the thickness signal includes a plurality of thicknesses THK1, a plurality of thicknesses THK2and plurality of thicknesses THK3. In some embodiments, the thicknesses THK1are the thicknesses from the surface of the insulating layer of the reconstructed wafer to the interface of a first die, and the thicknesses THK2are the thickness from the surface of the insulating layer of the reconstructed wafer to the interface of a second die. The thicknesses THK3may be the thicknesses from the surface of the insulating layer of the reconstructed wafer to the interface of a third die, or may be the noises produced by the EPD sensor. In the period from t1to tn, the thickness signal generated by the EPD sensor is filtered to generate the filtered thickness signal STHK2, where the filtered thickness signal STHK2includes a thickness extremum of the thickness signal within each time interval. In other words, the thickness extrema of the thickness signal in time intervals are determined and combined to generate the filtered thickness signal STHK2. In the embodiments shown inFIG.5C, the filtered thickness signal STHK2includes thickness maxima of the thickness signal within the time intervals. In an alternative embodiment, the filtered thickness signal STHK2includes thickness minima of the thickness signal within the time intervals. The thicknesses of the filtered thickness signal STHK2are used to detect the endpoint of the grinding process. In some embodiments, the thicknesses of the filtered thickness signal STHK2are compared to a pre-determined thickness threshold Tn to determine the endpoint of the grinding process. When the thickness of the filtered thickness signal STHK2at the time point tn reaches the pre-determined thickness threshold Tn, the time point tn is determined as the endpoint of the grinding process. In some embodiments, the time period from t0to t1illustrates the thickness signal in a first operating mode of endpoint detection system, and the time period from t1to tn illustrates the thickness signal in a second operating mode of endpoint detection system. For example, the first operating mode may be an average target mode, and the second operating mode may be a time mode or a peak mode. Referring toFIG.6, an exemplary flowchart for detecting an endpoint of a grinding process is illustrated. In step S610, an interface of a reconstructed wafer is periodically sensed, where the reconstructed wafer includes a plurality of dies of at least two types, to generate a thickness signal comprising thicknesses from a surface of an insulating layer of the reconstructed wafer to the interface of the reconstructed wafer. In step S620, a clock signal having a plurality of pulses with a time interval is generated. In step S630, the thickness signal is filtered according to the clock signal to output a thickness extremum among the thicknesses in the thickness signal generated within each time interval to determine the endpoint of the grinding process being performed on the reconstructed wafer. Referring toFIG.7, a method for manufacturing a semiconductor structure according to an exemplary embodiment of the disclosure is illustrated. In step S710, a plurality of dies of at least two types placed on a carrier are encapsulated with an insulating layer to form a reconstructed wafer. In step S720, a grinding process is performed on the reconstructed wafer and an interface of the reconstructed wafer is periodically sensed to generate a thickness signal comprising thicknesses from a surface of the insulating layer of the reconstructed wafer to the interface of the reconstructed wafer. In step S730, a clock signal having a plurality of pulses with a time interval is generated. In step S740, the thickness signal is filtered according to the clock signal to output a thickness extremum among the thicknesses in the thickness signal generated within each time interval to determine the endpoint of the grinding process. In step S750, the grinding process is ended at the endpoint. In some embodiments, the method further includes a step of de-bonding the dies of the reconstructed wafer from the carrier to form a semiconductor structure. According to some embodiments of the disclosure, an apparatus for detecting an endpoint of a grinding process includes a connecting device, a timer and a controller. The connecting device is configured to connect with a sensor that periodically senses an interface of a reconstructed wafer comprising a plurality of dies of at least two types to generate a thickness signal comprising thicknesses from a surface of an insulating layer of the reconstructed wafer to the interface of the reconstructed wafer sensed by the sensor. The timer is configured to generate a clock signal having a plurality of pulses with a time interval. The controller is coupled to the sensor and the timer, and is configured to filter the thickness signal according to the clock signal to output a thickness extremum among the thicknesses in the thickness signal generated within each time interval, and wherein the thickness signal after the filtering is used to determine the endpoint of the grinding process being performed on the reconstructed wafer. According to some embodiments of the disclosure, a method of detecting an endpoint of a grinding process includes steps of periodically sensing an interface of a reconstructed wafer comprising a plurality of dies of at least two types to generate a thickness signal comprising thicknesses from a surface of an insulating layer of the reconstructed wafer to the interface of the reconstructed wafer; generating a clock signal having a plurality of pulses with a time interval; and filtering the thickness signal according to the clock signal to output a thickness extremum among the thicknesses in the thickness signal generated within each time interval to determine the endpoint of the grinding process being performed on the reconstructed wafer. According to some embodiments of the disclosure, a method includes steps of encapsulating a plurality of dies of at least two types placed on a carrier with an insulating layer to form a reconstructed wafer; performing a grinding process on the reconstructed wafer and periodically sensing an interface of the reconstructed wafer to generate a thickness signal comprising thicknesses from a surface of the insulating layer of the reconstructed wafer to the interface of the reconstructed wafer; generating a clock signal having a plurality of pulses with a time interval; filtering the thickness signal according to the clock signal to output a thickness extremum among the thicknesses in the thickness signal generated within each time interval to determine the endpoint of the grinding process; and ending the grinding process at the endpoint. The foregoing has outlined features of several embodiments so that those skilled in the art may better understand the detailed description that follows. Those skilled in the art should appreciate that they may readily use the present disclosure as a basis for designing or modifying other processes and structures for carrying out the same purposes and/or achieving the same advantages of the embodiments introduced herein. Those skilled in the art should also realize that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and that they may make various changes, substitutions and alterations herein without departing from the spirit and scope of the present disclosure. | 37,317 |
11862524 | DETAILED DESCRIPTION OF THE DISCLOSURE Although claimed subject matter will be described in terms of certain embodiments, other embodiments, including embodiments that do not provide all of the benefits and features set forth herein, are also within the scope of this disclosure. Various structural, logical, process step, and electronic changes may be made without departing from the scope of the disclosure. Accordingly, the scope of the disclosure is defined only by reference to the appended claims. In general, an overlay error between two process layers or a shift between two sets of structures on the same layer may be determined using overlay targets, for which the target structures are designed with a known relationship between their symmetry characteristics and discrepancies from such symmetry correspond to overlay error in such targets. As used herein, a layer may refer to any suitable materials, such as a semiconductor or a photoresist layer that are generated and patterned for fabrication of a wafer device or test structure. Although the following target examples are shown to have structures on two (or more) layers for measuring overlay, each target may include two (or more) sets of structures on the same layer for determining a shift error between such set of structures. Additionally, embodiments of the present disclosure may be applied to any type of periodic targets, and such targets may be formed in an inactive area (e.g., scribe line) or in an active region of a die on of a production wafer (e.g., as part of a device portion of a die). Techniques that are described herein may also be applied to targets for determining other types of characteristics, such as critical dimension (CD), CD uniformity (CDU), edge placement error (EPE), pattern fidelity, etc. Overlay targets typically occupy an expensive location on an integrated circuit. Semiconductor manufacturers generally seek to decrease measurement time and wafer area of these overlay targets. Space on a wafer can be saved, measurement time can be made faster, and a comparison of results from the two technologies can be performed by combining imaging-based and scatterometry-based targets. Thus, including two targets in an area of an integrated circuit and measuring both overlay targets at the same time would provide benefits to the semiconductor manufacturing process. Embodiments disclosed herein combine electron beam overlay (eOVL) with scatterometry overlay (SCOL). Currently the scanning electron microscope (SEM) technology is used as a ruler for optical metrology measurements. Embodiments disclosed herein provide solutions with new target designs for electron beam overlay for combination with optical measurements. Target architypes also can combine optical image-based overlay (IBO) and diffraction-based overlay (DBO) targets with electron beam overlay specialized targets. Alternating the combined targets can enable denser sampling to increase model accuracy because the number of measurement samples on the wafer increases while keeping the wafer real estate identical. The mixed targets use 100% real estate available for overlay metrology, which provides a 2× increased number of targets for both technologies. Target designs disclosed herein can reduce measurement move-acquire-measurement (MAM) time and improve measurements accuracy because the regions of interest (ROI) can contain both X and Y information content within small field of view (FOV). For example, in one ROI, one grating may be for information in the X direction, and another grating may be for information in the Y direction. It may not be necessary to move to two different targets because all the information is contained in one target. Thus, the disclosed targets increase the information content per area. The measurements can be applied on coarse and fine pitch of the different target architypes. The target stack materials can vary between line and space features. The reverse combination use case can use the current optical targets with a denser sampling of electron beam overlay targets. A combined design of four cell scatterometry overlay and electron beam overlay also can be used. The embodiments disclosed herein can enable scatterometry target axis separation, which contains two cells per direction as in standard four cell design with prolonged bars in both directions of each layer per cell. This can provide physical separation between the different alignment scheme layers. The region of interest placement on such target type can be separated for each layer. Since multiple region of interest used per direction targets architecture of bar over bar and bar over trench with induced overlay. This can be used for scatterometry target (f0) measurable regardless of their shift coverage. Both directions can be applicable within the same target as well with prolonged bars per axis. Any design image-based overlay or diffraction-based overlay can enable an electron beam overlay target, center of electron beam overlay, and optical target that coincide. This can eliminate process variation effect, placement error effect, and can improve the ability to correct of the modeled terms. Due to design rules, the electron beam overlay target may be placed as close as possible to the optical target. Additional segments can be added to the optical target to fill in the space occupied by electron beam overlay target placement or prolongation of the bars, which can enable more information content. FIG.1is a four cell scatterometry overlay (SCOL) target with combined placement on electron beam overlay (eOVL) target in center and edge. For example, scatterometry uses the areas where layers of gratings overlap, while electron beam overlay uses the areas where layers of gratings are separated. The target100includes a first periodic structure101and a second periodic structure102. These are shown with different shading for ease of illustration. The first periodic structure101is formed on a first layer of a semiconductor device and has a first pitch along an axis and the second periodic structure102is formed on a second layer of the semiconductor device and has a second pitch along that axis, different from the first pitch. When suitably illuminated, the first and second periodic structures101,102together form a pattern. The layers can be adjacent to each other or can be separated by other layers. The first periodic structure101and second periodic structure102are illustrated as see-through for ease of illustration. Each of a plurality of gratings in the first periodic structure101has a first width along a second axis (e.g., X) and a first height along a first axis (e.g., Y). The first width may be between 1 μm and 100 μm. The first height may be between 10 μm and 100 μm. The first width and the first height may be larger or smaller than these ranges depending on the application. The first periodic structure101has a first pitch. The first pitch may be between 200 nm and 1000 nm. The first pitch may be larger or smaller than this range depending on the application. A second periodic structure102is formed on a second layer of the semiconductor device. Each of a plurality of gratings in the second periodic structure102has a second width along the second axis (e.g., X) and a second height along the first axis (e.g., Y). The second width of the second periodic structure102is narrower than the first width of the first periodic structure101. The second width may be between 1 μm and 100 μm. The second height may be between 10 μm and 100 μm. The second width and the second height may be larger or smaller than these ranges depending on the application. The second periodic structure102has a second pitch less than the first pitch of the first periodic structure101. The second pitch may be between 200 nm and 1000 nm. The second pitch may be larger or smaller than this range depending on the application. The second pitch may be larger than the first pitch. The gratings of the first periodic structure101are positioned over the gratings of the second periodic structure102. The first and second periodic structures101,102are mutually overlaid and are formed of arrays of mutually parallel lines on the first and second layers of the semiconductor device. The lines are arranged in registration along an axis, such as the Y-axis. The structure sizes, dimensions, and angles of the fine segmentation may depend on the semiconductor manufacturer, technology node, and processing step. Nodes may operate at structure sizes of a few nm to several μm. In the case of diagonal structures, 15° to 30° may be common, but other angles are possible. Target100may be 10 μm to 60 μm in side length. For example, the side lengths of the target100may be not greater than 40 μm. In general, the size of the target100may depend on the selected optical wavelength and beam size. Larger targets100may make measurements easier, but may also take up more area on the semiconductor wafer. Reducing the size of the target100may reduce cost of production and increase available space on the wafer. The particular balance of physics and costs to select a target size may depend on the design rules of the process of the specific layer and/or product. The target100can be rectangular in shape. The target100further includes an eOVL structure103. The eOVL structure103may be disposed in a center of the target100. The eOVL structure103may be polygonal. For example, the eOVL structure may be rectangular. FIG.2is an advanced imaging metrology (AIM) target with combined center placement on eOVL target. The target200may comprise an array of cells. Each cell may include a periodic structure with a pitch. For example, the periodic structure may comprise a plurality of rectangular gratings, where the pitch refers to the distance between adjacent gratings. The periodic structure may include a first section201and a second section202, which are separated by a first gap204. Target200differs from target100in that the periodic structures of the first section201and the second section202are separated, while the first periodic structure101and the second periodic structure102overlap. In general, the size of the periodic structures of the target200may be similar to those of the target100described above. The array of cells may comprise a first cell200A, a second cell200B, a third cell200C, and a fourth cell200D. The second cell200B may be arranged along a first axis X and rotated 90 degrees relative to the first cell200A. The third cell200C may be arranged along a second axis Y and rotated −90 degrees relative to the first cell200A. The fourth cell200D may be arranged along the first axis X relative to the third cell200C, arranged along the second axis Y relative to the second cell200B, and rotated 180 degrees relative to the first cell200A. Accordingly, the array of cells may be arranged in a 2×2 grid, having rotational symmetry. Other arrangements of cells are possible, including 3×3, 4×4, or larger grids. The target200may further comprise an electron beam overlay target210disposed in a center of the array of the first cell200A, the second cell200B, the third cell200C, and the fourth cell200D. The electron beam overlay target210may be disposed in other locations of the target200depending on the application. The electron beam overlay target210may be about 2 μm in size, but smaller or larger sizes are possible. The periodic structure of the first cell200A may have a first cell height along the first axis X and a first cell width along the second axis Y. The periodic structure of the second cell200B may have a second cell height along the second axis Y and a second cell width along the first axis X. The periodic structure of the third cell200C may have a third cell height along the second axis Y and a third cell width along the first axis X. The periodic structure of the fourth cell200D may have a fourth cell height along the first axis X and a fourth cell width along the second axis Y. Target200may be 20 μm by 20 μm in size, and may contain a total of 80 lines (20 lines per layer and direction and two layers). The individual lines may be 1 μm in size and 2.5 μm apart. Other sizes of the target200and the individual lines and spacings are possible. FIG.3is a triple AIM target with combined center placement on triple eOVL target. The target300differs from the target200in that the periodic structure of each cell may further include a third section203. The second section202and the third section203may be separated by a second gap205. The target300may be larger than target200to accommodate placement of the third section203, but the target300and its structures may be similar in size to those of the target200described above. FIG.4is an AIM target with combined placement on eOVL target with added segments in center and edge. The target400differs from the target200in that the periodic structure of each cell may include additional gratings. The first section201and the second section202of each cell may each include additional gratings added at the edge of the target400and/or at the center of the target400. The presence of additional gratings in the target400may improve measurement performance as the signal strength increases. The size of the target400and its structures may be similar in size to those of target200described above. According to an embodiment of the present disclosure, the first cell width may be greater than the second cell height. The second cell width may be greater than the third cell height. The third cell width may be greater than the fourth cell height. The fourth cell width may be greater than the first cell height. For example, as shown inFIG.4, each cell in the array of the target400may be rectangular. In this arrangement, measurement performance may be improved without sacrificing real estate on the wafer. FIG.5is an AIM target with combined placement on eOVL target with no added segments in center and edge. The target500differs from the target200in that the periodic structure of each cell may include fewer gratings. The first section201and the second section202of each cell may each have fewer gratings at the edge of the target500and/or at the center of the target500than the target200. The presence of fewer gratings in the target500may reduce production cost and wafer space used by the target500. The size of the target500and its structures may be similar in size to those of target200described above. According to an embodiment of the present disclosure, the first cell width may be equal to the second cell height. The second cell width may be equal to the third cell height. The third cell width may be equal to the fourth cell height. The fourth cell width may be equal to the first cell height. For example, as shown inFIG.5, each cell in the array of the target500may be square. In this arrangement, measurement performance may be improved without sacrificing real estate on the wafer. FIG.6is an AIM target with combined placement on eOVL target with prolongation of segments in center and edge. The target600differs from the target200in that the periodic structure of each cell may include prolonged gratings. For example, the first periodic structure201may have a first height and the second periodic structure202may have a second height. The second height may be greater than the first height. In this way, the second periodic structure202of each cell may extend along each side of the centrally-located eOVL target210. The ratio of the first height and the second height may depend on the design rules of the particular application. The size of the target600and its structures may be similar in size to those of target200described above. FIG.7is an AIM target with AIM polygon reduction for optimization of real estate, process robustness, and dummification. As shown in the target700, the eOVL target210may be a plurality of nested polygonal shapes disposed inside each other that define a center hollow area. The interconnected polygonal shapes may be squares, but other shapes may be possible. Dummification structures may be used to fill empty areas (e.g., white areas inFIG.7) of the target700(or of other targets of the present disclosure) or to gradually change between large and small structures without interfering with target design. The target700may also differ from the target200in that the periodic structure of each cell may include shorter gratings202a. For example, the second periodic structure202may include gratings with a second height and a third height. The third height may be less than the second height. The ratio of the second height and the third height may depend on the design rules of the particular application. The shorter gratings202ahaving the third height may be disposed adjacent to the eOVL target210. In this way, the size of the eOVL target210may be increased, fitting within the space of the vacated by the shorter gratings202a, which optimizes the real estate of the target700. The size of the target700and its structures may be similar in size to those of target200described above. FIG.8is another AIM target with AIM polygon reduction for optimization of real estate, process robustness, and dummification. The target800differs from the target700in that the second periodic structure of each cell may include multiple shorter gratings202ahaving the third height. In this way, the size of the eOVL target210may be further increased, fitting within the increased space vacated by the shorter gratings202a, which further optimizes the real estate of the target800. The size of the target800and its structures may be similar in size to those of target200described above. FIG.9Ais a combined AIM and eOVL target design. As shown inFIG.9B, the eOVL target210of the target900may include a body211and a plurality of segments212extending from the body211. The plurality of segments212may be connected to each other by a connecting segment213at the ends extended away from the body211. In this arrangement, the eOVL target210may define a comb-like structure. Similar structures may be used for electrical tests on a wafer. Combining existing designs of other types of metrology with optical overlay targets can be beneficial, as it can reduce the total number required for a particular design. The target900may include a plurality of eOVL targets210. For example, each cell may include two eOVL targets210arranged adjacent to the second periodic structure202at opposite ends of each cell. Each eOVL target210may be arranged adjacent to the shorter gratings202aof the second periodic structure202. For example, each eOVL target210may be arranged perpendicular to the shorter gratings202aof each cell. Each eOVL target210may be arranged on the same side of the second periodic structure202of each cell. For example, each eOVL target210may be arranged opposite to the first gap204of each cell. The shorter gratings202amay be located in the second periodic structure202toward the center of the target900and toward the edges of the target900. In this arrangement, the target900may have rotational symmetry based on the placement of the eOVL targets210among the first periodic structures201and the second periodic structures202. According to an embodiment of the present disclosure, the periodic structures of each cell may include a first pitch and a second pitch. For example, individual gratings within the first periodic structures201and the second periodic structures202may be separated by a first pitch, and groups of periodic structures may be separated by the second pitch. The second pitch may be larger than the first pitch. The ratio of the first pitch and the second pitch may depend on the design rules of the particular application. The second periodic structure202of each cell may include a group of the shorter gratings202a. The group of shorter gratings202amay be separated from the other gratings in the second periodic structure202by the second pitch. The size of the target900and its structures may be similar in size to those of target200described above. FIG.10is another combined AIM and eOVL target design. The target1000differs from the target900in that each cell may include two eOVL targets210arranged adjacent to the first periodic structure201at opposite ends of each cell. The first periodic structure201may include shorter gratings201ahaving the third height, shorter than the first height. Each eOVL target210may be arranged perpendicular to the shorter gratings201aof each cell. Each eOVL target210may be arranged on the same side of the first periodic structure201of each cell. For example, each eOVL target201may be arranged opposite to the first gap204of each cell. The shorter gratings201amay be located in the first periodic structure201at opposite ends of each cell, on the outer edges of the target1000. In this arrangement, the target1000may have rotational symmetry based on the placement of the eOVL targets210among the first periodic structures201and the second periodic structures202. The size of the target1000and its structures may be similar in size to those of target200described above. FIG.11is another combined AIM and eOVL target design. The target1100differs from the target900in that the eOVL targets210may be arranged on opposite sides of the second periodic structure202of each cell. For example, one of the eOVL targets210may be arranged adjacent to the first gap204, and the other of the eOVL targets210may be arranged opposite to the first gap204of each cell. In this arrangement, the target1100may have rotational symmetry based on the placement of the eOVL targets210among the first periodic structures201and the second periodic structures202. The size of the target1100and its structures may be similar in size to those of target200described above. FIG.12Ais another combined AIM and eOVL target design. As shown inFIG.12BandFIG.12C, the eOVL target1210of the target1200may include a body1211and a plurality of segments1212extending from both sides the body1211. The body1211may be disposed between two gratings of the first section1201(FIG.12B) and the second section1202(FIG.12C) of the periodic structure of each cell, and the plurality of segments may be disposed on the first section1201and the second section1202respectively. The body1211may be comparable to existing AIM targets, which may be beneficial in certain cases. The two gratings of the first section1201and the second section1202disposed on either side of the body1211may have a width and a pitch that is less than that of other gratings in the first section1201and the second section1202. The first section1201and the second section1202of the periodic structure of each cell may be separated by a first gap1204. In this arrangement, the eOVL target210may be mixed optical target while keeping the overall symmetry. This may be beneficial where having different pitches close by is problematic for manufacturing, where dummification structures may be otherwise placed. The target1200may include a plurality of eOVL targets1210. For example, each cell may include a plurality of eOVL targets1210disposed alternately between the first section1201and the second section1202of the periodic structure. As shown inFIG.12A, the target1200may include two eOVL targets1210arranged between the gratings of the first section1201and three eOVL targets1210arranged on either side of each of the gratings of the second section1202. The inversion of the layer combinations betweenFIG.12BandFIG.12Cmay be beneficial as it may ensure that the signal content between the layers is as similar as possible, such that no layer signal will dominate the overlay result. The size of the target1200and its structures may be similar in size to those of the target200described above. FIG.13is another combined AIM and eOVL target design. The target1300differs from the target1200in that the plurality of eOVL targets1210disposed in each cell are disposed at the ends of the first section1201and the second section1202of the periodic structure. In this way, the plurality of eOVL targets1210may be disposed adjacent to the center of the target1300and/or adjacent to the outer edges of the target1300. This symmetry of the placement of the eOVL targets1210in the first section1201and the second section1202may be beneficial under certain design rules. The size of the target1300and its structures may be similar in size to those of the target200described above. FIG.14is another combined AIM and eOVL target design. The target1400differs from the target1200in that the plurality of eOVL targets1210are disposed between each pair of gratings of the first section1201and the second section1202of the periodic structure of each cell. In this way, each cell of the target1400may comprise the plurality of eOVL targets1210arranged consecutively within the first section1201and the second section1202of the periodic structure. The size of the target1400and its structures may be similar in size to those of the target200described above. In this arrangement, the target1400may be fully regular and symmetric, which may be beneficial under some design rules. FIG.15is a field layout with two types of combined AIM and eOVL targets. The layout1500may comprise a central target1510and a plurality of outer targets1520arranged around the periphery of the central target1510. The size of the layout1500and the spacing between the targets may depend on the design rules of the particular application. The central target1510may be larger than the plurality of outer targets1520. The ratio of the size of the central target1510to the outer targets1520may be defined by balancing the relative signal strengths and the available area on the wafer. The central target1510and the plurality of outer targets1520may be any of the target designs described herein. The plurality of outer targets1520may include a first target type1521and a second target type1522. The first target type1521and the second target type1522may be any two different target designs described herein or combination thereof. One of the first target type1521and the second target type1522may be of the same target design as the central target1510. Alternatively, the first target type1521and the second target type1522may be different target designs from the central target1510. The plurality of outer targets1520may be arranged around the periphery of the central target1510in an alternating manner. For example, as shown inFIG.15, the plurality of outer targets1520may alternate between the first target type1521and the second target type1522. By alternating target types, accuracy per target may be improved, and target noise may be reduced. As each target design can have its own accuracy errors and offsets, it may be possible to choose targets for the layout1500in such a way that the accuracy errors and offsets may at least partially cancel out, and may thereby improve accuracy. FIG.16is a field layout with single types of combined AIM and eOVL targets. The layout1600differs from the layout1500in that the plurality of outer targets1520includes only the first target type1521. The first target type1521may be different from the target design of the central target1510. The size of the layout1600and the spacing between the targets may depend on the design rules of the particular application. FIG.17is another field layout with single types of combined AIM and eOVL targets. The layout1700differs from the layout1500in that the plurality of outer targets1520includes only the second target type1522. The second target type1522may be the same as the target design of the central target1510. The size of the layout1700and the spacing between the targets may depend on the design rules of the particular application. FIG.18is a flowchart of a method1800. In the method, a target is provided at1801. The target can be one of the targets disclosed herein. Overlay measurements are performed at1802using a semiconductor metrology tool. The semiconductor metrology tool may be a conventional tool, which utilizes conventional processing algorithms, or may be an electron beam tool, which uses different measurement techniques. For example, one beam spot can be applied to a grating. A single reflectivity value is collected per grating. Each cell will contain an induced offset to calculate overlay. At least four cells with different induced offsets may be used. This method can be propagated until “n” cells occur. A beam spot can be scanned to average spot position accuracy. FIG.19is a diagram of a system1900. The system1900includes a chuck1902configured to hold a wafer1901. The wafer1901includes one or more overlay targets, such as those described in the embodiments herein. The system1900includes an imaging optical system1903configured to measure the overlay target on the chuck1902. The imaging optical system1903can include an illumination source oriented to direct radiation onto a specific location of the wafer1901and one or more detectors oriented to detect an optical signal which from the wafer1901. The illumination source in the optical system1903can generate an illumination beam directed at the wafer1901. The imaging optical system1903also can include various lenses, optical components, other steering devices, or other beam transport devices. The illumination beam can be an optical beam or an electron beam. The imaging optical system1903can be used for acquisition such that the imaging optical system1903is part of the acquisition sequence of the scatterometry measurement. The system1900includes a scatterometry system1904configured to measure the overlay target on the chuck1902. The scatterometry system1904can be configured to measure the same overlay target as the imaging optical system1903. The scatterometry system1904can include an illumination source oriented to direct radiation onto a specified location of the wafer1901and one or more detectors oriented to detect a scatterometry signal which has been scattered by the wafer1901. The illumination source in the scatterometry system1904can generate an illumination beam directed at the wafer1901. The scatterometry system1904also can include various lenses or optical components. The scatterometry system1904can use the imaging optical system1903or information from the imaging optical system1903during the scatterometry sequence. Measurements of the wafer1901by the imaging optical system1903and the scatterometry system1904can be performed while the wafer1901remains on the chuck1902. Thus, the wafer1901may not move between measurement by the imaging optical system1903and the scatterometry system1904. In an instance, a vacuum around the wafer1901is not broken between measurements by the imaging optical system1903and the scatterometry system1904. In an instance, one of the measurements by the imaging optical system1903and the scatterometry system1904occurs after the other. In another instance, the measurements by the imaging optical system1903and the scatterometry system1904occur at least partially simultaneously or at the same time. While disclosed as one system1900, the imaging optical system1903and the scatterometry system1904can be in two separate systems. Each of the systems may have a separate chuck. A processor1905is in electronic communication with an electronic data storage unit1906, the imaging optical system1903, and the scatterometry system1904. The processor1905may include a microprocessor, a microcontroller, or other devices. The processor1905can receive output from the imaging optical system1903and the scatterometry system1904. The system1900can include an imaging optical system acquisition module1907configured to acquire the overlay target on the chuck1902with the imaging optical system1903. The optical system acquisition module1907forms an acquisition image that can be used by the imaging optical system1903or the scatterometry system1904. While illustrated as separate units, the imaging optical system acquisition module1907may be part of the imaging optical system1903. The imaging optical system acquisition module1907also may be part of the processor1905. The processor1905and electronic data storage unit1906may be part of the system1900or another device. In an example, the processor1905and electronic data storage unit1906may be part of a standalone control unit or in a centralized quality control unit. Multiple processors1905or electronic data storage unit1906may be used. In an embodiment, the processor1905may be disposed in the system1900. The processor1905may be implemented in practice by any combination of hardware, software, and firmware. Also, its functions as described herein may be performed by one unit, or divided up among different components, each of which may be implemented in turn by any combination of hardware, software and firmware. Program code or instructions for the processor1905to implement various methods and functions may be stored in readable storage media, such as a memory in the electronic data storage unit1906or other memory. The processor1905may be coupled to the components of the system1900in any suitable manner (e.g., via one or more transmission media, which may include wired and/or wireless transmission media) such that the processor1905can receive output. The processor1905may be configured to perform a number of functions using the output. The processor1905, other system(s), or other subsystem(s) described herein may be part of various systems, including a personal computer system, image computer, mainframe computer system, workstation, network appliance, interne appliance, or other device. The subsystem(s) or system(s) may also include any suitable processor known in the art, such as a parallel processor. In addition, the subsystem(s) or system(s) may include a platform with high speed processing and software, either as a standalone or a networked tool. If the system includes more than one subsystem, then the different subsystems may be coupled to each other such that images, data, information, instructions, etc. can be sent between the subsystems. For example, one subsystem may be coupled to additional subsystem(s) by any suitable transmission media, which may include any suitable wired and/or wireless transmission media known in the art. Two or more of such subsystems may also be effectively coupled by a shared computer-readable storage medium (not shown). The processor1905may be configured to perform a number of functions using the output of the imaging optical system1903, and the scatterometry system1904, or other output. For instance, the processor1905may be configured to send measurement results of the wafer1901. In another example, the processor1905can determine electron beam overlay and/or scatterometry overlay error within the target. In another example, the processor1905may be configured to send the output to an electronic data storage unit1906or another storage medium. The processor1905may be further configured as described herein. The processor1905may be configured according to any of the embodiments described herein. The processor1905also may be configured to perform other functions or additional steps using the output of the system1900or using images or data from other sources. In another embodiment, the processor1905may be communicatively coupled to any of the various components or sub-systems of system1900in any manner known in the art. Moreover, the processor1905may be configured to receive and/or acquire data or information from other systems (e.g., inspection results from an inspection system such as a review tool, a remote database including design data and the like) by a transmission medium that may include wired and/or wireless portions. In this manner, the transmission medium may serve as a data link between the processor1905and other subsystems of the system1900or systems external to system1900. In some embodiments, various steps, functions, and/or operations of system1900and the methods disclosed herein are carried out by one or more of the following: electronic circuits, logic gates, multiplexers, programmable logic devices, ASICs, analog or digital controls/switches, microcontrollers, or computing systems. Program instructions implementing methods such as those described herein may be transmitted over or stored on carrier medium. The carrier medium may include a storage medium such as a read-only memory, a random access memory, a magnetic or optical disk, a non-volatile memory, a solid state memory, a magnetic tape, and the like. A carrier medium may include a transmission medium such as a wire, cable, or wireless transmission link. For instance, the various steps described throughout the present disclosure may be carried out by a single processor1905(or computer system) or, alternatively, multiple processors1905(or multiple computer systems). Moreover, different sub-systems of the system1900may include one or more computing or logic systems. Therefore, the above description should not be interpreted as a limitation on the present disclosure but merely an illustration. An additional embodiment relates to a non-transitory computer-readable medium storing program instructions executable on a processor for inspecting a wafer, as disclosed herein. In particular, a processor, such as the processor1905, can be coupled to a memory in an electronic data storage medium, such as the electronic data storage unit1906, with non-transitory computer-readable medium that includes executable program instructions. The computer-implemented method may include any step(s) of any method(s) described herein. For example, processor1905may be programmed to perform some or all of the steps ofFIG.18. The memory in the electronic data storage unit1906may be a storage medium such as a magnetic or optical disk, a magnetic tape, or any other suitable non-transitory computer-readable medium known in the art. The program instructions may be implemented in any of various ways, including procedure-based techniques, component-based techniques, and/or object-oriented techniques, among others. For example, the program instructions may be implemented using ActiveX controls, C++ objects, JavaBeans, Microsoft Foundation Classes (MFC), Streaming SIMD Extension (SSE), or other technologies or methodologies, as desired. In another embodiment, a method of designing of the targets disclosed herein can be used. The method may be performed with a processor, such as those described therein. The gratings of the first and second periodic structures of the targets disclosed herein can be optimized. While specific configurations are shown in the embodiments illustrated herein, variations that include all or some of the features of these embodiments are possible. Although the present disclosure has been described with respect to one or more particular embodiments, it will be understood that other embodiments of the present disclosure may be made without departing from the scope of the present disclosure. Hence, the present disclosure is deemed limited only by the appended claims and the reasonable interpretation thereof. | 39,252 |
11862525 | DETAILED DESCRIPTION Common reference numerals are used throughout the drawings and the detailed description to indicate the same or similar components. Embodiments of the present disclosure will be readily understood from the following detailed description taken in conjunction with the accompanying drawings. Spatial descriptions, such as “above,” “below,” “up,” “left,” “right,” “down,” “top,” “bottom,” “vertical,” “horizontal,” “side,” “higher,” “lower,” “upper,” “over,” “under,” and so forth, are specified with respect to a certain component or group of components, or a certain plane of a component or group of components, for the orientation of the component(s) as shown in the associated figure. It should be understood that the spatial descriptions used herein are for purposes of illustration only, and that practical implementations of the structures described herein can be spatially arranged in any orientation or manner, provided that the merits of embodiments of this disclosure are not deviated from by such arrangement. FIG.1Ais a top view of a semiconductor device package1in accordance with some embodiments of the present disclosure. The semiconductor device package1includes a substrate10, a supporting element12, a semiconductor device11, and an adhesive15. The supporting element12is disposed on the substrate10. The semiconductor device11is disposed on the substrate10. The supporting element12defines an opening or a space to accommodate the semiconductor device11. The supporting element12surrounds the semiconductor device11. The semiconductor device11may include light emitting diodes (LEDs), optical sensors, pressure sensors, or other semiconductor devices. The semiconductor device11may include a flip-chip type semiconductor device. The semiconductor device11may include a wire-bond type semiconductor device. The adhesive15is disposed on the supporting element12. The adhesive15is disposed on an internal periphery of the supporting element12(e.g. along an edge of the supporting element12that defines the opening or space to accommodate the semiconductor device11). The adhesive15discontinuously surrounds the semiconductor device11(e.g. surrounds a portion of semiconductor device11). One end of the adhesive15is separated from another end of the adhesive15by a gap (G). In one or more embodiments, the adhesive15continuously surrounds a circumference of the semiconductor device11other than a portion of the circumference corresponding to the gap (G). In some embodiments, a portion of the supporting element12corresponding to the gap (G) (e.g. adjacent to the gap (G)) may constitute at least a portion of a recess or depression of the supporting element12. An edge of the adhesive15is adjacent to the recess. The depth of the recess of the supporting element12may be ranged from about 40 μm to about 60 μm. The supporting element12may include one or more inner corners, and the gap (G) may be disposed adjacent to one or more of the inner corners of the supporting element12. The gap (G) may be disposed adjacent to any portion of an inner periphery of the supporting element12. FIG.1Bis a cross-sectional view of a semiconductor device package1across line Y-Y inFIG.1Ain accordance with some embodiments of the present disclosure. The semiconductor device package1includes the substrate10, the semiconductor device11, the supporting element12, a transparent plate/cover13, the adhesive15, an adhesive layer15′, and a lid14. The substrate10has an upper surface10aand a lower surface10bopposite to the upper surface10a. The supporting element12is disposed on the upper surface10aof the substrate10. The supporting element12can be secured to the substrate10via the adhesive layer15′ (e.g. a second portion of the adhesive layer15′, not denoted inFIG.1B). The supporting element12has a stepped structure. The supporting element12may be a lid. The lid14is disposed on the supporting element12. The lid14is secured to the supporting element12via the adhesive layer15′. The lid14includes an opaque material (e.g. a material having a transmittance of about 20% or less, or about 10% or less, for light that the semiconductor device11is configured to process). The lid14includes an extension portion141. The extension portion141extends over at least a portion of the transparent plate13. The extension portion141covers a periphery of the transparent plate13(e.g. covers a peripheral portion of an upper surface13aof the transparent plate13, the peripheral portion constituting about 20% or less of a total surface area of the upper surface13aof the transparent plate13, about 15% or less of the total surface area of the upper surface13aof the transparent plate13, about 10% or less of the total surface area of the upper surface13aof the transparent plate13, or less). The transparent plate13may have a transmittance of about 80% or more, or about 90% or more, for light that the semiconductor device11is configured to process. The semiconductor device11may be disposed under the transparent plate13. The extension portion141mitigates against light leakage through side surfaces of the transparent plate13. The supporting element12and the lid14define an accommodating space (S). A material of the supporting element12may be the same as or different from the material of the lid14. The semiconductor device11is disposed on the upper surface10aof the substrate10. The semiconductor device11includes a conductive wire111electrically connected to the substrate10. The substrate10and the supporting element12define a space (S′). The substrate10and the transparent plate13define the space (S′). The substrate10, the supporting element12, and the transparent plate13define the space (S′). The substrate10, the supporting element12, the adhesive15, and the transparent plate13define the space (S′). The semiconductor device11is disposed in the space (S′). The transparent plate13has the upper surface13aand a lower surface13bopposite to the upper surface13a. A filter layer (not denoted inFIG.1B) may be applied to cover the upper surface13aor the lower surface13bof the transparent plate13to mitigate against light leakage that adversely impacts detection sensitivity (e.g. of the semiconductor device11). The filter layer may cover both the upper surface13aand the lower surface13bof the transparent plate13. The transparent plate13is disposed on a stepped recess of the supporting element12. The transparent plate13is disposed in the accommodating space (S). The transparent plate13is secured to the supporting element12via the adhesive15. The adhesive15disposed between the supporting element12and the transparent plate13discontinuously surrounds the semiconductor device11(e.g. surrounds a portion of the semiconductor device11). The adhesive15defines the gap (G). At a portion corresponding to the gap (G), the transparent plate13is separated from the supporting element12. The transparent plate13and the supporting element12define a channel (C). The lower surface13bof the transparent plate13and the supporting element12define the channel (C). The transparent plate13and the lid14define the channel (C). The supporting element12and the adhesive15define the channel (C). The transparent plate13and the adhesive15define the channel (C). The supporting element12and the lid14define the channel (C). The supporting element12, the adhesive layer15′, and the lid14define the channel (C). The supporting element12, the adhesive15, and the lid14define the channel (C). The supporting element12, the transparent plate13, and the lid14define the channel (C). The supporting element12, the transparent plate13, the adhesive15, and the lid14define the channel (C). The supporting element12, the transparent plate13, the adhesive layer15′, and the lid14define the channel (C). The supporting element12, the transparent plate13, the adhesive15, the adhesive layer15′, and the lid14define the channel (C). The channel (C) is in fluid/air communication with the space (S′). The channel (C) may be used as an air venting channel to release vapor or moisture. The channel (C) may include a winding or tortuous path. The channel (C) can mitigate light, water, and particle leakage. The gap (G) may constitute at least a portion of the channel (C). It is contemplated that the gap (G) may be additionally or alternatively provided at other locations. The channel (C) can help to prevent detachment of the lid14due to a pop-corn effect during a thermal cycle in an operation of manufacturing the semiconductor device package. FIG.1Cis a cross-sectional view of a semiconductor device package1across line X-X inFIG.1Aaccording to some embodiments of the present disclosure. The adhesive15is disposed between the supporting element12and the transparent plate13. The adhesive15surrounds the semiconductor device11(e.g. is disposed on opposing sides of the semiconductor device11). FIG.2is a cross-sectional view of a semiconductor device package1′ according to some embodiments of the present disclosure. The structure ofFIG.2is similar to the structure ofFIG.1Bexcept that the substrate10defines a recess103. The recess103is disposed adjacent to an inner side surface of the supporting element12. FIG.3is a cross-sectional view of a semiconductor device package1″ according to some embodiments of the present disclosure. The structure ofFIG.3is similar to the structure ofFIG.1Bexcept that the substrate10defines a recess104. The recess104is disposed under a lower surface of the supporting element12. The recess104may extend along an outer side surface of the substrate10. The recess104may accommodate the adhesive layer15′, or may omit the adhesive layer15′. FIG.4is a cross-sectional view of a semiconductor device package1′″ according to some embodiments of the present disclosure. The structure ofFIG.4is similar to the structure ofFIG.3except that the supporting element12further includes a through via121. The through via121(which can include, for example, a channel) communicates with the recess104. The portion of the substrate10corresponding to the recess104and the portion of the support element12corresponding to the through via121omit the adhesive layer15′. The substrate10, the supporting element12, the transparent plate13, and the lid14define the channel (C). The channel (C) includes two winding or tortuous paths, and at least one such path can include the recces104and/or the through via121. This can provide for the channel (C) releasing vapor or moisture more efficiently. FIG.5is a cross-sectional view of a semiconductor device package2according to some embodiments of the present disclosure. The structure ofFIG.5is similar to the structure ofFIG.1Bexcept that the support element12further includes a recessed portion122. The recessed portion122may be disposed under the gap (G). An edge of the adhesive15is adjacent to the recessed portion122(not shown). The support element12has a first upper surface12aand a second upper surface12b(e.g. respectively corresponding to a highest stepped portion and stepped portion of intermediary height). The recessed portion122has an upper surface122a(e.g. corresponding to a lowest stepped portion). The upper surface122aof the recessed portion122is lower than the second upper surface12bof the support element12(e.g. a ratio of a distance between the top surface10aof the substrate10and the second upper surface12bof the support element12and a distance between the top surface10aof the substrate10and the upper surface122aof the recessed portion122is about 1.3 or more, about 1.6 or more, about 1.9 or more, about 2.2 or more, or about 2.5 or more). After securing the transparent plate13to the support element12via the adhesive15, bleeding of the adhesive15can flow to the recessed portion122of the support element12, and the larger width of the channel (C) at a portion of the channel corresponding to the recessed portion122can accommodate at least a portion of the bleeding adhesive15and still maintain a space between the transparent plate13and the recessed portion122. The vertical distance between the upper surface122aof the recessed portion122and the second upper surface12bof the supporting element12may be ranged from about 40 μm to about 60 μm. FIG.6Ais a cross-sectional view of a semiconductor device package3according to some embodiments of the present disclosure. The structure ofFIG.6Ais similar to the structure ofFIG.1Bexcept that the lid14and the adhesive layer15′ are omitted and the upper surface12aof the support element12is substantially coplanar with the upper surface13aof the transparent plate13. The support element12is a lid. The support element12and the transparent plate13define the channel (C). The support element12includes an opaque material. In some embodiments, an adhesive layer16or a tape16may be disposed on the upper surface12aof the support element12and the upper surface13aof the transparent plate13. The tape16may protect the transparent plate13and help to avoid damage or contamination of the upper surface13aof the transparent plate13. The tape16may be removed after a singulation operation. The tape16may also be applied to other embodiments of the present disclosure. FIG.6Bis a cross-sectional view of a semiconductor device package3′ according to some embodiments of the present disclosure. The semiconductor device package3′ ofFIG.6Bis similar to the semiconductor device package3ofFIG.6Aexcept that a height or thickness of a support element12′ is greater than that of the support element12. An upper surface12′aof the support element12′ is higher than the upper surface13aof the transparent plate13(e.g. the upper surface12′aof the support element12′ is not coplanar with the upper surface13aof the transparent plate13). The tape16is spaced from the transparent plate13. The tape16is not in contact with the transparent plate13. No residual material of the tape16is disposed on the upper surface13aof the transparent plate13subsequent to the removal of the tape16. FIG.7is a cross-sectional view of a semiconductor device package4in accordance with some embodiments of the present disclosure. The semiconductor device package4ofFIG.7is similar to the semiconductor device package1ofFIG.1B, except that the semiconductor device package4includes an opaque encapsulant17, an opaque film18, a supporting element42including an extension portion421, and an extension portion441of a lid44having a side surface441cwith a slope. The semiconductor device package4includes the substrate10, the semiconductor device11, the supporting element42, the transparent plate13, the adhesive15, the adhesive layer15′, and the lid44. The supporting element42may be a lid. The conductive wire111of the semiconductor device11is encapsulated by the opaque encapsulant17. The opaque encapsulant17may be used as a wire black pattern to block incident light from reaching the conductive wire111so as to avoid the unwanted incident light reflecting to the semiconductor device11. A size (e.g. thickness or diameter) of the opaque encapsulant17may be adjusted according to design specifications. The supporting element42is disposed on the substrate10via the adhesive layer15′. The supporting element42surrounds the semiconductor device11. The supporting element42includes the extension portion421. The extension portion421has an upper surface421a, a lower surface421b, and a side surface421c. The side surface421chas a slope (e.g. a slope relative to the upper surface421aor the lower surface421b). The slope of the side surface421cmay be a positive slope or a negative slope. The side surface421cmay be substantially planar along the slope. The extension portion421of the supporting element42may be used as a supporting stage or a carrier to support the transparent plate13. The transparent plate13is disposed on the upper surface421aof the extension portion421. The adhesive15is disposed between the transparent plate13and the extension portion421. The opaque film18is disposed on the lower surface13bof the transparent plate13. The opaque film18is disposed on the periphery of the transparent plate13(e.g. covers a peripheral portion of a lower surface13bof the transparent plate13, the peripheral portion constituting about 20% or less of a total surface area of the lower surface13bof the transparent plate13, about 15% or less of the total surface area of the lower surface13bof the transparent plate13, about 10% or less of the total surface area of the lower surface13bof the transparent plate13, or less). The opaque film18may be used as a glass black pattern to block unwanted incident light passing through the transparent plate13to the conductive wire111, which may result in noise being received by the semiconductor device11. A material of the opaque film18may be the same as or different from the material of the opaque encapsulant17. A size (e.g. thickness, length, or width) of the opaque film18may be adjusted according to design specifications. The substrate10and the transparent plate13define the space (S′). The substrate10and the supporting element42define the space (S′). The substrate10, the supporting element42, and the transparent plate13define the space (S′). The substrate10, the supporting element42, the adhesive15, and the transparent plate13define the space (S′). The lid44is disposed on the supporting element42via the adhesive layer15′. The lid44includes the extension portion441. The extension portion441has an upper surface441a, a lower surface441b, and the side surface441c. The side surface441cextends between the upper surface441aand the lower surface441b. The side surface441chas a slope. The slope of the side surface441cmay be a positive slope or a negative slope. The design of the side surface441cof the extension portion441may readily reflect unwanted light so as to avoid the unwanted light passing through the transparent plate13and arriving at the semiconductor device11. The lid44includes an opaque material. The supporting element42and the lid44define an accommodating space (S). The transparent plate13is disposed in the accommodating space (S). A material of the supporting element42may be the same as or different from the material of the lid44. The transparent plate13and the supporting element42define the channel (C). The lower surface13bof the transparent plate13and the supporting element42define the channel (C). The transparent plate13and the lid44define the channel (C). The supporting element42and the adhesive15define the channel (C). The supporting element42and the lid44define the channel (C). The supporting element42, the transparent plate13, and the lid44define the channel (C). The supporting element42, the transparent plate13, and the adhesive15define the channel (C). The supporting element42, the transparent plate13, the adhesive15, and the lid44define the channel (C). The supporting element42, the transparent plate13, the adhesive layer15′, and the lid44define the channel (C). The supporting element42, the transparent plate13, the adhesive15, the adhesive layer15′, and the lid44define the channel (C). The channel (C) is in fluid/air communication with the space (S′). The channel (C) may be used as an air venting channel to release vapor or moisture. The channel (C) may include a winding or tortuous path. FIG.8Ais a top view of a semiconductor device package5in accordance with some embodiments of the present disclosure. The semiconductor device package5includes a substrate10, a semiconductor device11, an adhesive15, and a supporting element52. The adhesive15is disposed on the substrate10. The semiconductor device11is disposed on the substrate10. The supporting element52is disposed on the adhesive15. The supporting element52defines an opening or a space to accommodate the semiconductor device11. The supporting element52surrounds the semiconductor device11. The semiconductor device11may include light emitting diodes (LEDs), optical sensors, pressure sensors, or other semiconductor devices. The semiconductor device11may include a flip-chip type semiconductor device. The semiconductor device11may include a wire-bond type semiconductor device. The adhesive15discontinuously surrounds the semiconductor device11(e.g. surrounds a portion of semiconductor device11). One end of the adhesive15is separated from another end of the adhesive15by a gap (G). In one or more embodiments, the adhesive15continuously surrounds a circumference of the semiconductor device11other than a portion of the circumference corresponding to the gap (G). In some embodiments, a bottom portion of the supporting element52corresponding to the gap (G) (e.g. adjacent to the gap (G)) may be a recess or depression of the supporting element52. An edge of the adhesive15is adjacent to the recess. The depth of the recess of the supporting element52may be ranged from about 40 μm to about 60 μm. The supporting element52may include one or more bottom corners, and the gap (G) may be disposed adjacent to one or more of the bottom corners of the supporting element52. The gap (G) may be disposed adjacent to any portion of the bottom of the supporting element52. FIG.8Bis a cross-sectional view of a semiconductor device package5across line Y-Y inFIG.8Ain accordance with some embodiments of the present disclosure. The semiconductor device package5includes the substrate10, the semiconductor device11, the adhesive15, an adhesive layer15′, the supporting element52, a transparent plate/cover13, and a lid54. The substrate10has an upper surface10aand a lower surface10bopposite to the upper surface10a. The supporting element52is disposed on the upper surface10aof the substrate10. The supporting element52is secured to the substrate10via the adhesive15. The supporting element52may be a dam or a lid. The supporting element52may include a solder mask, a photoresist, or other suitable materials. The adhesive15disposed between the substrate10and the supporting element52discontinuously surrounds the semiconductor device11(e.g. surrounds a portion of the semiconductor device11). The lid54is disposed on the upper surface10aof the substrate10. The lid54is secured to the substrate10via the adhesive layer15′. The lid54surrounds the semiconductor device11. The lid54surrounds the supporting element52. The lid54surrounds the transparent plate13. The adhesive layer15′ between the substrate10and the lid54surrounds the semiconductor device11. The adhesive layer15′ surrounds the supporting element52. The lid54includes an opaque material. The lid54includes an extension portion541. The extension portion541extends over at least a portion of the transparent plate13. The extension portion541covers a periphery of the transparent plate13(e.g. covers a peripheral portion of an upper surface13aof the transparent plate13, the peripheral portion constituting about 20% or less of a total surface area of the upper surface13aof the transparent plate13, about 15% or less of the total surface area of the upper surface13aof the transparent plate13, about 10% or less of the total surface area of the upper surface13aof the transparent plate13, or less). The extension portion541mitigates against light leakage through side surfaces of the transparent plate13. The supporting element52and the lid54define an accommodating space (S). A material of the supporting element52may be the same as or different from the material of the lid54. The semiconductor device11is disposed on the upper surface10aof the substrate10. The semiconductor device11includes a conductive wire111electrically connected to the substrate10. The substrate10and the supporting element52define a space (S′). The substrate10and the transparent plate13define the space (S′). The substrate10, the supporting element52, and the transparent plate13define the space (S′). The semiconductor device11is disposed in the space (S′). The transparent plate13has the upper surface13aand a lower surface13bopposite to the upper surface13a. A filter layer (not denoted inFIG.8B) may be applied to cover the upper surface13aor the lower surface13bof the transparent plate13to mitigate against light leakage that adversely impacts detection sensitivity (e.g. of the semiconductor device11). The filter layer may cover both the upper surface13aand the lower surface13bof the transparent plate13. The transparent plate13is disposed on the supporting element52. The transparent plate13is disposed in the accommodating space (S). The adhesive15defines the gap (G). At a portion corresponding to the gap (G), the supporting element52is separated from the substrate10. The substrate10and the supporting element52define the channel (C). The lower surface of the supporting element52and the substrate10define the channel (C). The supporting element52and the adhesive15define the channel (C). The transparent plate13and the adhesive15define the channel (C). The substrate10and the lid54define the channel (C). The supporting element52and the lid54define the channel (C). The transparent plate13and the lid54define the channel (C). The supporting element52, the transparent plate13, and the lid54define the channel (C). The substrate10, the transparent plate13, and the lid54define the channel (C). The supporting element52, the adhesive15, and the lid54define the channel (C). The substrate10, the supporting element52, the transparent plate13, and the lid54define the channel (C). The substrate10, the supporting element52, the adhesive15, the transparent plate13, and the lid54define the channel (C). The substrate10, the supporting element52, the transparent plate13, the adhesive layer15′, and the lid54define the channel (C). The substrate10, the supporting element52, the transparent plate13, the adhesive15, the adhesive layer15′, and the lid54define the channel (C). The channel (C) is in fluid/air communication with the space (S′). The channel (C) may be used as an air venting channel to release vapor or moisture. The channel (C) may include a winding or tortuous path. The channel (C) can mitigate light, water, and particle leakage. The gap (G) may constitute at least a portion of the channel (C). It is contemplated that the gap (G) may be additionally or alternatively provided at other locations. The channel (C) can help to prevent detachment of the lid54due to a pop-corn effect during a thermal cycle in an operation of manufacturing the semiconductor device package. FIG.8Cis a cross-sectional view of a semiconductor device package5across line X-X inFIG.8Aaccording to some embodiments of the present disclosure. The adhesive15is disposed between the substrate10and the supporting element52. The adhesive15surrounds the semiconductor device11. FIG.9is a cross-sectional view of a semiconductor device package5′ according to some embodiments of the present disclosure. The structure ofFIG.9is similar to the structure ofFIG.8Bexcept that the substrate10defines a recess104. The recess104is disposed under a lower surface of the supporting element52. The recess104may extend along an outer side surface of the substrate10. A portion of the substrate10corresponding to the recess104may omit the adhesive layer15′, or may have the adhesive layer15′ disposed thereon. FIG.10Ais a top view of a semiconductor device package5″ in accordance with some embodiments of the present disclosure. The semiconductor device package5″ includes a substrate10, a semiconductor device11, an adhesive15, and a supporting element52. The adhesive15is disposed on the supporting element52. The semiconductor device11is disposed on the substrate10. The supporting element52is disposed on the substrate10. The supporting element52defines an opening or a space to accommodate the semiconductor device11. The supporting element52surrounds the semiconductor device11. The semiconductor device11may include light emitting diodes (LEDs), optical sensors, pressure sensors, or other semiconductor devices. The semiconductor device11may include a flip-chip type semiconductor device. The semiconductor device11may include a wire-bond type semiconductor device. The adhesive15discontinuously surrounds the semiconductor device11(e.g. surrounds a portion of semiconductor device11). One end of the adhesive15is separated from another end of the adhesive15by a gap (G). In some embodiments, a bottom portion of the supporting element52corresponding to the gap (G) (e.g. adjacent to the gap (G) may be a recess or depression. An edge of the adhesive15is adjacent to the recess. The depth of the recess of the supporting element52may be ranged from about 40 μm to about 60 μm. The supporting element52may include one or more top corners, and the gap (G) may be disposed adjacent to one or more of the top corners of the supporting element52. The gap (G) may be disposed adjacent to any portion of the top of the supporting element52. FIG.10Bis a cross-sectional view of a semiconductor device package5″ across line Y-Y inFIG.10Ain accordance with some embodiments of the present disclosure. The semiconductor device package5″ includes the substrate10, the semiconductor device11, the adhesive15, an adhesive layer15′, the supporting element52, a transparent plate/cover13, and a lid54. The substrate10has an upper surface10aand a lower surface10bopposite to the upper surface10a. The supporting element52is disposed on the upper surface10aof the substrate10. The supporting element52may be a dam or a lid. The supporting element52may include a solder mask, a photoresist, or other suitable materials. The lid54is disposed on the upper surface10aof the substrate10. The lid54is secured to the substrate10via the adhesive layer15′. The lid54surrounds the semiconductor device11. The lid54surrounds the supporting element52. The lid54surrounds the transparent plate13. The adhesive layer15′ disposed between the substrate10and the lid54surrounds the semiconductor device11. The adhesive layer15′ surrounds the supporting element52. The lid54includes an opaque material. The lid54includes an extension portion541. The extension portion541extends over at least a portion of the transparent plate13. The extension portion541covers a periphery of the transparent plate13(e.g. covers a peripheral portion of an upper surface13aof the transparent plate13, the peripheral portion constituting about 20% or less of a total surface area of the upper surface13aof the transparent plate13, about 15% or less of the total surface area of the upper surface13aof the transparent plate13, about 10% or less of the total surface area of the upper surface13aof the transparent plate13, or less). The extension portion541mitigates against light leakage through side surfaces of the transparent plate13. The supporting element52and the lid54define an accommodating space (S). A material of the supporting element52may be the same as or different from the material of the lid54. The semiconductor device11is disposed on the upper surface10aof the substrate10. The semiconductor device11includes a conductive wire111electrically connected to the substrate10. The substrate10and the supporting element52define a space (S′). The substrate10and the transparent plate13define the space (S′). The substrate10, the supporting element52, and the transparent plate13define the space (S′). The semiconductor device11is disposed in the space (S′). The transparent plate13has the upper surface13aand a lower surface13bopposite to the upper surface13a. A filter layer (not denoted inFIG.8B) may be applied to cover the upper surface13aor the lower surface13bof the transparent plate13to mitigate against light leakage that adversely impacts detection sensitivity (e.g. of the semiconductor device11). The filter layer may cover both the upper surface13aand the lower surface13bof the transparent plate13. The transparent plate13is disposed on the supporting element52via the adhesive15. The transparent plate13is disposed in the accommodating space (S). The adhesive15disposed between the supporting element52and the transparent plate13discontinuously surrounds the semiconductor device11(e.g. surrounds a portion of semiconductor device11). The adhesive15defines the gap (G). At the portion corresponding to the gap (G), the supporting element52is separated from the transparent plate13. The supporting element52and the transparent plate13define the channel (C). The lower surface of the supporting element52and the transparent plate13define the channel (C). The supporting element52and the lid54define the channel (C). The supporting element52and the adhesive15define the channel (C). The transparent plate13and the adhesive15define the channel (C). The transparent plate13and the lid54define the channel (C). The supporting element52, the transparent plate13, and the lid54define the channel (C). The transparent plate13, the adhesive15, and the lid54define the channel (C). The supporting element52, the adhesive15, and the transparent plate13define the channel (C). The supporting element52, the adhesive15, and the lid54define the channel (C). The supporting element52, the transparent plate13, the adhesive layer15′, and the lid54define the channel (C). The supporting element52, the transparent plate13, the adhesive15, the adhesive layer15′, and the lid54define the channel (C). The channel (C) is in fluid/air communication with the space (S′). The channel (C) may be used as an air venting channel to release vapor or moisture. The channel (C) may include a winding or tortuous path. The channel (C) can mitigate light, water, and particle leakage. The gap (G) may constitute at least a portion of the channel (C). It is contemplated that the gap (G) may be additionally or alternatively provided at other locations. The channel (C) can help to prevent detachment of the lid54due to a pop-corn effect during a thermal cycle in an operation of manufacturing the semiconductor device package. FIG.10Cis a cross-sectional view of a semiconductor device package5″ across line X-X inFIG.10Aaccording to some embodiments of the present disclosure. The adhesive15is disposed between the supporting element52and the transparent plate13. The adhesive15surrounds the semiconductor device11. FIG.11is a cross-sectional view of a semiconductor device package6in accordance with some embodiments of the present disclosure. The semiconductor device package6ofFIG.11is similar to the semiconductor device package5ofFIG.8Bexcept that the semiconductor device package6includes an opaque encapsulant17, an opaque film18, and an extension portion541′ of a lid54′ having a side surface541′cwith a slope. The semiconductor device package6includes the substrate10, the semiconductor device11including the conductive wire111, the supporting element52, the transparent plate13, the adhesive15, the adhesive layer15′, and the lid54′. The supporting element52may be a dam or a lid. The conductive wire111of the semiconductor device11is encapsulated by the opaque encapsulant17. The opaque encapsulant17may be used as a wire black pattern to block incident light from reaching the conductive wire111so as to avoid the unwanted incident light reflecting to the semiconductor device11. A size (e.g. thickness or diameter) of the opaque encapsulant17may be adjusted according to design specifications. The supporting element52is disposed on the substrate10via the adhesive15. The supporting element52surrounds the semiconductor device11. The transparent plate13is disposed on the supporting element52. The opaque film18is disposed on the lower surface13bof the transparent plate13. The opaque film18is disposed on the periphery of the transparent plate13(e.g. covers a peripheral portion of the lower surface13bof the transparent plate13, the peripheral portion constituting about 20% or less of a total surface area of the lower surface13bof the transparent plate13, about 15% or less of the total surface area of the lower surface13bof the transparent plate13, about 10% or less of the total surface area of the lower surface13bof the transparent plate13, or less). The opaque film18may be used as a glass black pattern to block unwanted incident light passing through the transparent plate13to the conductive wire111, which may result in noise being received by the semiconductor device11. The material of the opaque film18may be the same as or different from the material of the opaque encapsulant17. A size (e.g. thickness, length, or width) of the opaque film18may be adjusted according to design specifications. The substrate10and the transparent plate13define the space (S′). The substrate10and the supporting element52define the space (S′). The substrate10, the supporting element52, and the transparent plate13define the space (S′). The substrate10, the supporting element52, the adhesive15, and the transparent plate13define the space (S′). The lid54′ is disposed on the substrate10via the adhesive layer15′. The lid54′ includes an extension portion541′. The extension portion541′ has an upper surface541′a, a lower surface541′b, and the side surface541′c. The side surface541′cextends between the upper surface541′aand the lower surface541′b. The side surface541′chas a slope (e.g. a slope relative to the upper surface541′aor the lower surface541′b). The slope of the side surface541′cmay be a positive slope or a negative slope. The side surface541′cmay be substantially planar along the slope. The design of the side surface541′cof the extension portion541′ may readily reflect unwanted light so as to avoid the unwanted light passing through the transparent plate13and arriving at the semiconductor device11. The lid54′ includes an opaque material. The supporting element52and the lid54′ define an accommodating space (S). The transparent plate13is disposed in the accommodating space (S). A material of the supporting element52may be the same as or different from the material of the lid54′. The transparent plate13and the supporting element52define the channel (C). The lower surface13bof the transparent plate13and the supporting element52define the channel (C). The transparent plate13and the lid54′ define the channel (C). The supporting element52and the adhesive15define the channel (C). The supporting element52and the lid54′ define the channel (C). The supporting element52, the transparent plate13, and the lid54′ define the channel (C). The supporting element52, the transparent plate13, and the adhesive15define the channel (C). The supporting element52, the transparent plate13, the adhesive15, and the lid54′ define the channel (C). The supporting element52, the transparent plate13, the adhesive layer15′, and the lid54′ define the channel (C). The supporting element52, the transparent plate13, the adhesive15, the adhesive layer15′, and the lid54′ define the channel (C). The channel (C) is in fluid/air communication with the space (S′). The channel (C) may be used as an air venting channel to release vapor or moisture. The channel (C) may include a winding or tortuous path. FIG.12Ais a top view of a semiconductor device package7in accordance with some embodiments of the present disclosure. The semiconductor device package7includes a substrate70, a semiconductor device11, and an adhesive15. The substrate70may be a supporting element. The substrate70defines a cavity or a space to accommodate the semiconductor device11. The adhesive15is disposed on the substrate70. The adhesive15surrounds the cavity. The semiconductor device11is disposed on the substrate70. The semiconductor device11is disposed in the cavity of the substrate70. The semiconductor device11may include light emitting diodes (LEDs), optical sensors, pressure sensors, or other semiconductor devices. The semiconductor device11may include a flip-chip type semiconductor device. The semiconductor device11may include a wire-bond type semiconductor device. The adhesive15discontinuously surrounds the semiconductor device11(e.g. surrounds a portion of the semiconductor device11). One end of the adhesive15is separated from another end of the adhesive15by a gap (G). In some embodiments, a portion of the substrate10corresponding to the gap (G) (e.g. adjacent to the gap (G)) may be a recess or depression. An edge of the adhesive15is adjacent to the recess. The depth of the recess of the substrate10may be ranged from about 40 μm to about 60 μm. The depth of the recess of the substrate10is less than the depth of the cavity of the substrate10. The cavity may have one or more corners, and the gap (G) may be disposed adjacent to one or more of the corners of the cavity. The gap (G) may be disposed adjacent to any portion of the periphery of the cavity. FIG.12Bis a cross-sectional view of a semiconductor device package7across line Y-Y inFIG.12Ain accordance with some embodiments of the present disclosure. The semiconductor device package7includes the substrate70, the semiconductor device11, the adhesive15, an adhesive layer15′, a transparent plate/cover13, and a lid74. The substrate70has an upper surface70aand a lower surface70bopposite to the upper surface70a. The substrate70has a cavity (C′). The substrate70may be a supporting element. The lid74is disposed on the upper surface70aof the substrate70. The lid74is secured to the substrate70via the adhesive layer15′. The lid74surrounds the semiconductor device11. The lid74surrounds the transparent plate13. The adhesive layer15′ disposed between the substrate10and the lid74surrounds the semiconductor device11. The lid74includes an opaque material. The lid74includes an extension portion741. The extension portion741extends over at least a portion of the transparent plate13. The extension portion741covers a periphery of the transparent plate13(e.g. covers a peripheral portion of an upper surface13aof the transparent plate13, the peripheral portion constituting about 20% or less of a total surface area of the upper surface13aof the transparent plate13, about 15% or less of the total surface area of the upper surface13aof the transparent plate13, about 10% or less of the total surface area of the upper surface13aof the transparent plate13, or less). The extension portion741mitigates against light leakage through side surfaces of the transparent plate13. The substrate70and the lid74define an accommodating space (S). The semiconductor device11is disposed on the upper surface70aof the substrate70. The semiconductor device11is disposed in the cavity (C′) of the substrate70. The upper surface70aof the substrate70may have a stepped shape. The semiconductor device11includes a conductive wire111electrically connected to the substrate70. The substrate70and the transparent plate13define a space (S′). The substrate70, the adhesive15, and the transparent plate13define the space (S′). The semiconductor device11is disposed in the space (S′). The transparent plate13has the upper surface13aand a lower surface13bopposite to the upper surface13a. A filter layer (not denoted inFIG.12B) may be applied to cover the upper surface13aor the lower surface13bof the transparent plate13to mitigate against light leakage that adversely impacts detection sensitivity (e.g. of the semiconductor device11). The filter layer may cover both the upper surface13aand the lower surface13bof the transparent plate13. The transparent plate13is disposed on the upper surface70aof the substrate70via the adhesive15. The transparent plate13is disposed in the accommodating space (S). The adhesive15disposed between the substrate70and the transparent plate13discontinuously surrounds the semiconductor device11(e.g. surrounds a portion of the semiconductor device11). The adhesive15defines the gap (G). At a portion corresponding to the gap (G), the substrate70is separated from the transparent plate13. The substrate70and the transparent plate13define the channel (C). The substrate70and the lower surface13bof the transparent plate13define the channel (C). The substrate70and the adhesive15define the channel (C). The transparent plate13and the adhesive15define the channel (C). The substrate70and the lid74define the channel (C). The transparent plate13and the lid74define the channel (C). The substrate70, the transparent plate13, and the lid74define the channel (C). The transparent plate13, the adhesive15, and the lid74define the channel (C). The substrate70, the adhesive15, and the transparent plate13define the channel (C). The substrate70, the adhesive15, and the lid74define the channel (C). The substrate70, the transparent plate13, the adhesive layer15′, and the lid74define the channel (C). The substrate70, the transparent plate13, the adhesive15, the adhesive layer15′, and the lid74define the channel (C). The channel (C) is in fluid/air communication with the space (S′). The channel (C) may be used as an air venting channel to release vapor or moisture. The channel (C) may include a winding or tortuous path. The channel (C) can mitigate light, water, and particle leakage. The gap (G) may constitute at least a portion of the channel (C). It is contemplated that the gap (G) may be additionally or alternatively provided at other locations. The channel (C) can help to prevent detachment of the lid74due to a pop-corn effect during a thermal cycle in an operation of manufacturing the semiconductor device package. FIG.12Cis a cross-sectional view of a semiconductor device package7across line X-X inFIG.12Aaccording to some embodiments of the present disclosure. The adhesive15is disposed between the substrate70and the transparent plate13. The adhesive15surrounds the semiconductor device11. FIG.13is a cross-sectional view of a semiconductor device package8in accordance with some embodiments of the present disclosure. The semiconductor device package8ofFIG.13is similar to the semiconductor device package7ofFIG.12Bexcept that the semiconductor device package8includes an opaque encapsulant17, an opaque film18, and an extension portion741′ of a lid74′ having a side surface741′cwith a slope. The semiconductor device package8includes the substrate70, the semiconductor device11, the transparent plate13, the adhesive15, the adhesive layer15′, and the lid74′. The conductive wire111of the semiconductor device11is encapsulated by the opaque encapsulant17. The opaque encapsulant17may be used as a wire black pattern to block incident light from reaching the conductive wire111so as to avoid the unwanted incident light reflecting to the semiconductor device11. A size (e.g. thickness or diameter) of the opaque encapsulant17may be adjusted according to design specifications. The transparent plate13is disposed on the substrate70. The opaque film18is disposed on the lower surface13bof the transparent plate13. The opaque film18is disposed on the periphery of the transparent plate13(e.g. covers a peripheral portion of the lower surface13bof the transparent plate13, the peripheral portion constituting about 20% or less of a total surface area of the lower surface13bof the transparent plate13, about 15% or less of the total surface area of the lower surface13bof the transparent plate13, about 10% or less of the total surface area of the lower surface13bof the transparent plate13, or less). The opaque film18may be used as a glass black pattern to block the unwanted incident light passing through the transparent plate13to the conductive wire111which may result in noise being received by the semiconductor device11. A material of the opaque film18may be the same as or different from the material of the opaque encapsulant17. A size (e.g. thickness, length, or width) of the opaque film18may be adjusted according to design specifications. The substrate70and the transparent plate13define the space (S′). The substrate70and the adhesive15define the space (S′). The substrate70, the adhesive15, and the transparent plate13define the space (S′). The substrate10, the adhesive15, and the transparent plate13define the space (S′). The lid74′ is disposed on the substrate10via the adhesive layer15′. The lid74′ includes the extension portion741′. The extension portion741′ has an upper surface741′a, a lower surface741′b, and the side surface741′c. The side surface741′cextends between the upper surface741′aand the lower surface741b. The side surface741′chas a slope (e.g. a slope relative to the upper surface741′aor the lower surface741′b). The side surface741′cmay be substantially planar. The slope of the side surface741′cmay be a positive slope or a negative slope. The design of the side surface741′cof the extension portion741′ may readily reflect unwanted light so as to avoid the unwanted light passing through the transparent plate13and arriving at the semiconductor device11. The lid74′ includes an opaque material. The substrate70and the lid74′ define an accommodating space (S). The transparent plate13is disposed in the accommodating space (S). The substrate70and the transparent plate13define the channel (C). The substrate70and the lower surface13bof the transparent plate13define the channel (C). The substrate70and the adhesive15define the channel (C). The transparent plate13and the adhesive15define the channel (C). The substrate70and the lid74′ define the channel (C). The transparent plate13and the lid74′ define the channel (C). The substrate70, the transparent plate13, and the lid74′ define the channel (C). The transparent plate13, the adhesive15, and the lid74′ define the channel (C). The substrate70, the adhesive15, and the transparent plate13define the channel (C). The substrate70, the adhesive15, and the lid74′ define the channel (C). The substrate70, the transparent plate13, the adhesive layer15′, and the lid74′ define the channel (C). The substrate70, the transparent plate13, the adhesive15, the adhesive layer15′, and the lid74′ define the channel (C). The channel (C) is in fluid/air communication with the space (S′). The channel (C) may be used as an air venting channel to release vapor or moisture. The channel (C) may include a winding or tortuous path. FIG.14illustrates a method of manufacturing a semiconductor device package1according to some embodiments of the present disclosure. A semiconductor device11is bonded and wire bonded to a substrate10. An adhesive layer15′ is applied to the substrate10. A supporting element12is attached to the substrate10. The supporting element12is secured to the substrate10via an adhesive layer15′. The adhesive layer15′ is applied to an outer periphery of the supporting element12. The adhesive15is applied to an inner periphery of the supporting element12. A transparent plate13is attached to the supporting element12. The transparent plate13is secured to the supporting element12via the adhesive15. A lid14is attached to the supporting element12. The lid14is secured to the supporting element12via the adhesive layer15′. The adhesive15defines a gap (G). The adhesive15discontinuously surrounds the semiconductor device11(e.g. surrounds a portion of the semiconductor device11). One end of the adhesive15is separated from another end of the adhesive15by the gap (G). At a portion corresponding to the gap (G), the supporting element12is separated from the transparent plate13. In some embodiments, a panel of semiconductor device packages1are singulated by a singulation operation. A strip sheet of semiconductor device packages1are singulated by a singulation operation. FIG.15illustrates a method of manufacturing a semiconductor device package5according to some embodiments of the present disclosure. A semiconductor device11is bonded and wire bonded to a substrate10. An adhesive layer15′ is applied to an outer periphery of the substrate10. An adhesive15is applied to a portion of the substrate10corresponding to a supporting element52. A transparent plate13is attached to the supporting element52. The supporting element52is attached to the substrate10. The supporting element52is secured to the substrate10via the adhesive15. The lid54is attached to the substrate10. The lid54is secured to the substrate10via the adhesive layer15′. The adhesive15defines a gap (G). The adhesive15discontinuously surrounds the semiconductor device11(e.g. surrounds a portion of the semiconductor device11). One end of the adhesive15is separated from another end of the adhesive15with the gap (G). At a portion corresponding to the gap (G), the supporting element52is separated from the substrate10. In some embodiments, a panel of semiconductor device packages5is singulated by a singulation operation. A strip sheet of semiconductor device packages5is singulated by a singulation operation. FIG.16illustrates a method of manufacturing a semiconductor device package7according to some embodiments of the present disclosure. A semiconductor device11is bonded and wire bonded to a substrate70. A semiconductor device11is disposed in a cavity (C′) defined by the substrate70. An adhesive layer15′ is applied to an outer periphery of the substrate70. An adhesive15is applied to a portion of the substrate70corresponding to a transparent plate13. The transparent plate13is attached to the substrate70. The transparent plate13is secured to the substrate70via the adhesive15. A lid74is attached to the substrate70. The lid74is secured to the substrate70via the adhesive layer15′. The adhesive15defines a gap (G). The adhesive15discontinuously surrounds the semiconductor device11(e.g. surrounds a portion of the semiconductor device11). One end of the adhesive15is separated from another end of the adhesive15with the gap (G). At a portion corresponding to the gap (G), the substrate70is separated from the transparent plate13. In some embodiments, a panel of semiconductor device packages7is singulated by a singulation operation. A strip sheet of semiconductor device packages7is singulated by a singulation operation. FIG.17illustrates a cross-sectional view of a comparative semiconductor device package9. The semiconductor device package9includes a substrate10′, a semiconductor device11, a lid12, a transparent plate13, and an adhesive15. The substrate10′ has an upper surface10′aand a lower surface10′bopposite to the upper surface10′a. The lid12is disposed on the upper surface10′aof the substrate10′. The lid12is secured to the substrate10′ via an adhesive layer15′ (not denoted inFIG.17). The semiconductor device11is disposed on the upper surface10′aof the substrate10′. The semiconductor device11may include an optical sensor or other suitable devices. The substrate10′ defines a vent hole105. The vent hole105in the substrate10′ might mitigate against detachment of the lid12due to a pop-corn effect at elevated temperatures during manufacturing. However, the vent hole105may lead to light leakage as well as water and particle contaminants can enter into an inner space of the comparative semiconductor device package9. The adhesive15is disposed on an inner periphery of the lid12. The adhesive15continuously surrounds the semiconductor device11. The transparent plate13is disposed on the lid12via the adhesive15. A filter layer (not denoted inFIG.17) may be applied to cover the upper surface13aand the lower surface13bof the transparent plate13to mitigate against light leakage that adversely impacts detection sensitivity (e.g. of the semiconductor device11). Since the side surfaces of the transparent plate13are not covered by the filter layer and are spaced from the lid12, light leakage through the side surfaces of the transparent plate13may occur. As used herein and not otherwise defined, the terms “substantially,” “substantial,” “approximately” and “about” are used to describe and account for small variations. When used in conjunction with an event or circumstance, the terms can encompass instances in which the event or circumstance occurs precisely as well as instances in which the event or circumstance occurs to a close approximation. For example, when used in conjunction with a numerical value, the terms can encompass a range of variation of less than or equal to ±10% of that numerical value, such as less than or equal to ±5%, less than or equal to ±4%, less than or equal to ±3%, less than or equal to ±2%, less than or equal to ±1%, less than or equal to ±0.5%, less than or equal to ±0.1%, or less than or equal to ±0.05%. The term “substantially coplanar” can refer to two surfaces within micrometers of lying along a same plane, such as within 40 μm, within 30 μm, within 20 μm, within 10 μm, or within 1 μm of lying along the same plane. For example, a surface can be deemed to be planar or substantially planar if a difference between a highest point and a lowest point of the surface is no greater than 5 μm, no greater than 2 μm, no greater than 1 μm, or no greater than 0.5 μm. As used herein, the singular terms “a,” “an,” and “the” may include plural referents unless the context clearly dictates otherwise. In the description of some embodiments, a component provided “on” or “over” another component can encompass cases where the former component is directly on (e.g., in physical contact with) the latter component, as well as cases where one or more intervening components are located between the former component and the latter component. While the present disclosure has been described and illustrated with reference to specific embodiments thereof, these descriptions and illustrations are not limiting. It should be understood by those skilled in the art that various changes may be made and equivalents may be substituted without departing from the true spirit and scope of the present disclosure as defined by the appended claims. The illustrations may not necessarily be drawn to scale. There may be distinctions between the artistic renditions in the present disclosure and the actual apparatus due to manufacturing processes and tolerances. There may be other embodiments of the present disclosure which are not specifically illustrated. The specification and the drawings are to be regarded as illustrative rather than restrictive. Modifications may be made to adapt a particular situation, material, composition of matter, method, or process to the objective, spirit and scope of the present disclosure. All such modifications are intended to be within the scope of the claims appended hereto. While the methods disclosed herein have been described with reference to particular operations performed in a particular order, it will be understood that these operations may be combined, sub-divided, or re-ordered to form an equivalent method without departing from the teachings of the present disclosure. Accordingly, unless specifically indicated herein, the order and grouping of the operations are not limitations. | 58,650 |
11862527 | DETAILED DESCRIPTION The following disclosure provides many different embodiments, or examples, for implementing different features of the provided subject matter. Specific examples of components, values, operations, materials, arrangements, etc., are described below to simplify the present disclosure. These are, of course, merely examples and are not intended to be limiting. Other components, values, operations, materials, arrangements, etc., are contemplated. For example, the formation of a first feature over or on a second feature in the description that follows may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features may be formed between the first and second features, such that the first and second features may not be in direct contact. In addition, the present disclosure may repeat reference numerals and/or letters in the various examples. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed. Further, spatially relative terms, such as “beneath,” “below,” “lower,” “above,” “upper” and the like, may be used herein for ease of description to describe one element or feature's relationship to another element(s) or feature(s) as illustrated in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The apparatus may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein may likewise be interpreted accordingly. Thermal management of integrated circuits is relevant to the lifespan of an integrated circuit during operation, and to the performance of an integrated circuit. In some instances, the operating voltage of an integrated circuit is modified to overclock the processor of the computer to increase the processor speed. The overclocking increases an amount of heat generated in the integrated circuit. Heat produced by an integrated circuit comes from the flow of electrical current through interconnection structures and transistors in the integrated circuit. Increased speed and increased operating voltages are associated with larger amounts of heat production by an integrated circuit. Integrated circuits have heat tolerance specifications to preserve and protect the operation of the integrated circuit. Integrated circuits which exceed the heat tolerance specifications tend to have reduced operating lifetimes and/or logic errors during operation. A reduced operating lifetime of an integrated circuit, or logic errors, are related to the quality of the channel region of the transistor. As dopants in the source and/or drain regions of an integrated circuit migrate outward from dopant regions in the source or drain regions of the integrated circuit (source or drain wells of the integrated circuit), leakage current of the transistors impacted by migrating dopants increases and the performance suffers. Heat generated from the integrated circuit flows away from the generation locations toward the surface of the integrated circuit. At the surface of the integrated circuit, heatsinks or ambient cooling material (air, or liquid for immersed computing devices) transfer heat away from the integrated circuit. Heat generated from transistors flows from the transistors through interconnection structures in the integrated circuit toward a top surface of the integrated circuit, where heatsinks and/or ambient cooling material transfer the heat away. The dielectric materials which surround the conductive vias and/or metal lines in the integrated circuit interconnection structure act as insulators, or poor heat conductors, with respect to the conductive vias and/or metal lines in the interconnection structure. In a silicon on insulator (SOI) device, an oxide layer, or layer of insulating material, is between transistors and the substrate. The oxide layer is a poor thermal conductor, and conducts little heat away from the integrated circuit. As a result, heat dissipation from the transistors through the substrate is limited in some approaches. This tends to negatively impact integrated circuits especially as device size continues to shrink and heat generating elements are located closer together within the integrated circuit. A thermal substrate contact which passes through the oxide layer and is in direct contact with the substrate helps to transfer heat from the transistors into the substrate. The thermal substrate contact lands on the substrate at the substrate top surface, or extends into a recess into the substrate. The thermal substrate contact is also in direct contact with the layer of semiconductor material above the oxide layer. Thus, downward (e.g., toward the substrate) thermal conduction combined with upward (e.g., away from the substrate, through the integrated circuit) thermal conduction increases the cooling rate of the integrated circuit. By increasing the cooling rate of an integrated circuit, the peak temperatures reached by the transistors and other components of the integrated circuit are reduced, extending the lifetime of the integrated circuit. Further, by increasing the cooling rate of the integrated circuit, the negative consequences (shortened lifetime, and so forth) of overclocking an integrated circuit are reduced. By increasing the cooling rate of the integrated circuit, the heat removed from the integrated circuit increases the time which an integrated circuit such as a central processing unit, or a graphic processing unit, operates before turning on active cooling systems to protect the integrated circuits from high temperature conditions. FIG.1is a flow diagram of a method100of making a thermal substrate contact, in accordance with some embodiments. Method100includes an operation102in which an oxide layer is formed over a substrate. A substrate suitable for integrated circuits includes a semiconductor material such as silicon (Si) or silicon germanium (SiGe), among other materials. Substrate materials used in integrated circuit manufacturing have relatively high thermal conductivity, with respect to an oxide layer grown over the substrate. In some embodiments, forming an oxide layer includes chemical vapor deposition of an insulator material. In some embodiments, forming an oxide layer includes physical vapor deposition of an insulator material. Methods of depositing, as opposed to growing, an oxide layer over a substrate are suitable for use on substrates which are not semiconductor materials (e.g., sapphire (aluminum oxide, Al2O3), diamond, and so forth). In some embodiments, an oxide layer includes a layer of silicon dioxide over a semiconductor material. In some embodiments, forming an oxide layer includes growing an oxide layer by processing the substrate top surface with oxygen, water vapor, or steam. Processing the substrate top surface with oxygen, water vapor, or steam promotes formation of native oxide on an exposed surface of a semiconductor material. According to some embodiments, the growth of a native oxide by reacting the semiconductor material with oxygen, water vapor, or steam, provides a uniform and dense insulating material to electrically isolate the unreacted semiconductor material from a layer of semiconductor material deposited over the oxide layer. In some embodiments, an oxide layer is grown over a top surface of a substrate in order to electrically isolate (e.g., insulate) the substrate from the integrated circuit over the oxide layer. By electrically isolating the substrate from the integrated circuit, the oxide layer reduces leakage current in the integrated circuit. Leakage current in an integrated circuit flows through from a source of one transistor of an integrated circuit through the substrate to a drain of another transistor of the integrated circuit. The oxide layer reduces the volume of semiconducting material available for leakage current to flow. In some embodiments, an oxide layer grown over a substrate abuts the bottom of a well of the transistor, such that leakage current does not flow below the well. A buried oxide layer also provides, by electrically isolating the substrate from a remainder of the integrated circuit, noise reduction by reducing and/or eliminating the influence of transient or permanent voltages applied to the substrate material on the integrated circuit (especially the channel regions of the integrated circuit). According to some embodiments, an interconnection structure of an integrated circuit is electrically connected to a thermal substrate contact which extends through the layer of semiconductor material and the oxide layer to electrically connect with the substrate. Tying the substrate to a voltage source from the integrated circuit decreases electrical noise in the integrated circuit. Tying the substrate to a voltage source of the integrated circuit adjusts and/or tightens a distribution of transistor switching speeds of the integrated circuit because bias from the substrate is consistent across the integrated circuit. Method100includes an operation104in which a layer of semiconductor material is deposited over the oxide layer. In some embodiments, the layer of semiconductor material is formed by epitaxial deposition. In epitaxial deposition, a layer of material is grown from a liquid or gaseous medium on a surface of a substrate during integrated circuit manufacturing. In some embodiments, the material has a same chemical composition and a same lattice constant as the material on which the material is grown. In some embodiments, such as embodiments wherein the material includes dopants different from the material on which the crystalline material is grown, the lattice constant of the grown material differs from the lattice constant of the growth surface material, resulting in strain being exerted at the interface between the grown material and the growth surface material. Materials suitable for epitaxial deposition include silicon, doped semiconductor material (e.g., with P-type or N-type dopants), undoped heterogeneous semiconductor materials, type III-V heterogeneous semiconductor materials, and so forth. In some embodiments, the layer of semiconductor material is deposited by chemical vapor deposition. In some embodiments, chemical vapor deposition produces a layer of material on a growth surface wherein the layer of material is less ordered than a purely crystalline material, but is not amorphous. Materials suitable for chemical vapor deposition include silicon, doped semiconductor material (e.g., with P-type or N-type dopants), undoped heterogeneous semiconductor materials, type III-V heterogeneous semiconductor materials, and so forth. In some embodiments, the layer of semiconductor material is deposited or grown over the oxide layer, and planarized using chemical mechanical polishing (CMP) to produce a flat surface for source, drain, and channel regions of transistors of the integrated circuit. In some embodiments, the layer of semiconductor material is deposited or grown over the oxide layer and thinned using a liquid or chemical etch process to adjust the thickness of the layer of semiconductor material prior to forming source, drain, and channel regions of transistors of the integrated circuit. Method100includes an operation106in which at least one isolation structure is manufactured in the layer of semiconductor material. Isolation structures prevent or reduce electrical interactions between elements of the integrated circuit in the layer of semiconductor material. In some embodiments, isolation structures include shallow trench isolation structures (STI structures, or STI) which extend part way into the layer of semiconductor material. In some embodiments, isolation structures include deep trench isolation structures (DTI structures, or DTI) which extend deeper into the layer of semiconductor material than shallow trench isolation structures. In some embodiments, deep trench isolation structures extend from a top surface of the layer of semiconductor material to a top surface of the oxide layer. In some embodiments, a shallow trench isolation structure has a portion of a deep trench isolation structure extending from a bottom of the shallow trench isolation structure to a top surface of the oxide layer. An isolation structure is formed in the layer of semiconductor material by operations of: depositing a layer of patterning material over the layer of semiconductor material; transferring a pattern to the layer of patterning material, the pattern having openings corresponding to the locations of the isolation structure in the layer of semiconductor material; etching openings in the layer of semiconductor material through the openings in the pattern; and filling the openings in the layer of semiconductor material with a dielectric material. For a shallow trench isolation structure, the openings in the layer of semiconductor material extend part-way through the layer of semiconductor material, and the dielectric material extends (after filling) part-way through the layer of semiconductor material. For a deep trench isolation structure, the openings in the layer of semiconductor material extend deeper into the layer of semiconductor material than for a shallow trench isolation structure. In some embodiments, the openings in the layer of semiconductor material, and the insulator material filled into the openings, extends from a top surface of the layer of semiconductor material to a top surface of the layer below the layer of semiconductor material (e.g., the oxide layer). In some embodiments, a shallow trench isolation structure is manufactured at a location in an integrated circuit, and a deep trench isolation structure is manufactured at the same location in the integrated circuit, and extends through the shallow trench isolation structure. The flow of method100next includes an operation108in which a thermal substrate contact is manufactured to provide a thermal connection to the substrate. In some embodiments of operation108, the thermal substrate contact is manufactured to land on a top surface of the substrate after clearing away a portion of the oxide layer to form an opening through the oxide layer. In some embodiments, the substrate has a recess formed therein and the thermal substrate contact fills the recess in the substrate. According to some embodiments, a recess is formed in a top surface of the substrate by an etch process which forms the opening in which conductive material of the thermal substrate contact is formed. According to some embodiments, the etch process to form an opening for a thermal substrate contact stops against a top surface of the substrate without forming a recess in the substrate material. In some embodiments, the etch process is a wet etch process. In an embodiment, a wet etch process uses hydrofluoric acid (HF) in water to etch openings in the layer of semiconductor material or the oxide layer. At 49% HF in water, aqueous hydrofluoric acid etches silicon dioxide or other oxide materials with good selectivity to semiconductor materials, especially silicon dioxide. Thus, aqueous hydrofluoric acid clears oxide layer material from the surface of the substrate without forming a recess in the substrate because the hydrofluoric acid etches the oxide layer material (e.g., silicon dioxide) faster than the substrate material (e.g., silicon). In some embodiments, the etch process is a dry etch process, or a plasma etch process. A plasma etch process forms openings for thermal substrate contacts by ionizing reactant molecules in a plasma above the surface of a substrate having the oxide layer and the layer of semiconductor material thereon, and applying a voltage to the plasma to accelerate the ions against the exposed surface of the oxide layer of layer of semiconductor material, through openings in a patterned layer of patterning material. Etchants for plasma etching of openings for thermal substrate contacts include one or more of trifluoromethane (CHF3), hexafluoroethane (C2F6), octafluoropropane (C3F8), and so forth with oxygen and argon (for dilution). Increasing the ratio of fluorocarbon to oxygen increases the selectivity of the plasma etch to silicon (over silicon dioxide) at the expense of additional polymer formation during etching. In some embodiments, an oxygen plasma, or an oxygen/tetrafluoromethane (CF4) plasma is used to remove residual polymer from thermal substrate contact openings before depositing thermally conductive material (e.g., a metallic compound or a semiconductor material) into the openings and against the substrate. Thermal substrate contacts have a higher thermal conductivity than the oxide layer between the layer of semiconductor material and the substrate. By providing a higher-thermal conductivity pathway for diffusion of heat downward in the integrated circuit, the thermal substrate contact increases cooling efficiency of the integrated circuit and increases the thermal and operating voltage window of the integrated circuit. According to some embodiments, the thermal substrate contact is a semiconductor material. In some embodiments, the thermal substrate contact is an electrically conductive material. In some embodiments, the electrically conductive material is a metallic material such as tungsten (W), cobalt (Co), titanium (Ti), tantalum (Ta), nickel (Ni), and so forth, or alloys thereof. In some embodiments, a semiconductor material used for a thermal substrate contact is deposited by, e.g., epitaxial deposition or chemical vapor deposition of the semiconductor material, as described above for deposition of the layer of semiconductor material. In some embodiments, an electrically conductive material is deposited by sputtering atoms of the electrically conductive material from a sputtering target onto the top surface of the integrated circuit. In some embodiments, the thermal substrate contact is manufactured by forming a single opening through the layer of semiconductor material and through the oxide layer to expose the substrate, and then filling the single opening with thermal substrate contact material in one fill step. In some embodiments, a thermal substrate contact is manufactured by forming a first opening through the oxide layer and filling the opening through the oxide layer to form a first thermal substrate contact segment, followed by depositing the layer of semiconductor material, and forming therethrough a second opening aligned with the first thermal substrate contact segment, and forming a second thermal substrate contact segment by filling the second opening with a thermal substrate contact material. In some embodiments, the thermal substrate contact material of the first thermal substrate contact segment and the second thermal substrate contact segment are a same thermal substrate contact material. In some embodiments, the thermal substrate contact material of the first thermal substrate contact segment and the second thermal substrate contact segment are different thermal substrate contact materials. The flow of method100next includes an operation110in which a transistor is manufactured over the oxide layer. The transistor is manufactured over the oxide layer by performing manufacturing steps of depositing patterning material over the layer of semiconductor material, forming a pattern in the layer of patterning material, the pattern having exposed areas of the layer of semiconductor material and masked areas of the layer of semiconductor material, and adding dopants to exposed areas of the layer of semiconductor material. In some embodiments, the patterning material includes a material such as photoresist or other semiconductor patterning material. In some embodiments, forming a pattern in the layer of patterning material includes photolithography, electron-beam lithography, and/or another method of pattern transfer for forming wells and channels in a layer of semiconductor material. In some embodiments, adding dopants to the exposed areas of the layer of semiconductor material is performed by implantation from an implant source into the layer of semiconductor material. In some embodiments, adding dopants to the exposed areas of the layer of semiconductor material is performed by depositing an epitaxial layer of semiconductor dopant (e.g., a doped semiconductor material with a high concentration of dopant) over the layer of semiconductor material and annealing the epitaxial layer of semiconductor dopant to drive the dopant into the layer of semiconductor material. According to some embodiments, manufacturing the transistor over the oxide layer is performed after manufacturing a thermal substrate contact against a top surface of the substrate. A planarization step performed after adding dopants to the layer of semiconductor material removes an upper portion of the layer of semiconductor material containing dopants for the source well, the drain well, or the doped regions next to the channel in the layer of semiconductor material. Planarizing the layer of semiconductor material after adding dopant introduces uncertainty in the amount of dopant in the layer of semiconductor material. Planarizing the layer of semiconductor material before adding dopant ensures that the dopants added to the layer of semiconductor material are not removed during, e.g., a planarization step. A thermal substrate contact is protected from dopants added to the layer of semiconductor material by the layer of patterning material over the top surface of the layer of semiconductor material. Once the thermal substrate contact is manufactured against the surface of the substrate, and the dopants are added to the layer of semiconductor material, manufacturing the transistor and the integrated circuit proceeds. In some embodiments, an order of operations of method100is altered. For example, in some embodiments, operation110is performed before operation108. In some embodiments, at least one operation of method100is omitted. For example, in some embodiments, operation106is omitted. In some embodiments, additional operations are included in method100. For example, in some embodiments, a heat sink is attached to a surface of the substrate opposite the transistor. FIG.2is a top view of an integrated circuit200having thermal substrate contacts, in accordance with some embodiments. InFIG.2, source regions202A,202B, and202C, and drain regions204A and204B, are part of a layer of semiconductor material deposited over an oxide layer. Cross sectional line A-A′ extends across source region202A, drain region204A, and source region202B, including an N-doped well (an N-well)208in the drain region204A. Cross-sectional line B-B′ extends across source region202A, drain region204A, and source region202B, including a thermal substrate contact210in the drain region204A. Source regions202A,202B, and202C include source wells (S) (e.g., portions of a doped well in the layer of semiconductor material) and barriers (B) between the source wells in a source region. Thermal substrate contacts210alternate with N-doped wells (N-wells) in the drain region204A. A pattern of N-wells and thermal substrate contacts in drain region204B is similar to the pattern of N-wells208and thermal substrate contacts210in drain region204A. N-wells are formed according to the method described above in operation110. Thermal substrate contacts210are manufactured according to the method described above in operation108. FIG.3is a cross-sectional view of an integrated circuit300, in accordance with some embodiments. Elements of integrated circuit300correspond to elements ofFIG.2along cross-sectional line A-A′, incremented by 100. InFIG.3, source region302A and source region302B are separated by drain region304in layer of semiconductor material305. Oxide layer307is above substrate301, and layer of semiconductor material305is above oxide layer307. Layer of semiconductor material305includes STI312A, STI312B, and STI312C. Layer of semiconductor material305includes DTI309A, DTI309B, DTI309C, and DTI309D. STI312A, STI312B, and STI312C extend partway through layer of semiconductor material305. DTI structures309A and309B extend below STI312A, and DTI309C and DTI309D extend below STI312C. In integrated circuit300, DTI309A-309D extend completely through the layer of semiconductor material305to a top surface of oxide layer307. In some embodiments, deep trench isolation structures extend below shallow trench isolation structures, but do not extend completely to an underlying layer such as the oxide layer over the substrate. Layer of semiconductor material305includes P-doped wells314A and314B, and N-doped well316. In integrated circuit300, P-doped well314A is in direct contact with STI312A and DTI309B. P-doped well314A is also in direct contact with a high voltage N-well (HVNW)315A. In layer of semiconductor material305, N-doped well316is between HVNW315A and HVNW315B. P-doped well314B and N-doped well316are on opposite sides of HVNW315B in layer of semiconductor material305. In some embodiments, the dopant concentration of N-type dopants in N-doped well316is the same as the dopant concentration of P-type dopants in P-doped well314A and P-doped well314B. In some embodiments, the dopant concentration of the N-type dopant in N-doped well316is greater than the concentration of P-type dopants in P-doped wells314A and314B. In some embodiments, the dopant concentration of the N-type dopant in N-doped well316is less than the concentration of P-type dopants in P-doped wells314A and314B. HVNW315A and HVNW315B have a different dopant concentration than N-doped well316and P-doped wells314A and314B. In some embodiments, HVNW315A and HVNW315B are doped with N-type dopants such that the wells have an N-type dopant concentration which is greater than the N-type dopant concentration in the N-doped well316. HVNW315A and HVNW315B are doped with larger N-type dopant concentrations in order to reduce leakage current between the source wells and the drain well of a transistor. P-doped region317A is situated in P-doped well314A, and P-doped region317B is situated in P-doped well314B. P-doped regions317A-B have higher P-type dopant concentrations than P-doped wells314A and314B. N-doped region319A is situated in P-doped well314A next to P-doped region317A. N-doped region319B is situated in P-doped well314B next to P-doped region317B. P-doped regions317A and317B serve to create a P/N junction in the P-doped wells314A and314B across which current flows upon application of a voltage to the drain or source regions of the integrated circuit transistor. In some embodiments, the dopant types described hereinabove are reversed: e.g., wells or regions described above as having P-type dopants have, instead, N-type dopants, and wells or regions described above as having N-type dopants have, instead, P-type dopants. Wells and/or regions having dopant concentrations different than a dopant profile/concentration in the substrate (e.g., substrate301), undergo at least one dopant addition process to enrich the well and/or region with a different dopant profile/concentration than the substrate. In some embodiments, the dopant addition process includes deposition of a patterning material over the layer of semiconductor material, transferring a pattern to the layer of patterning material, and epitaxial deposition of a thin layer of a dopant-rich semiconductor material. Dopant addition using epitaxial deposition of a thin layer of dopant-rich semiconductor material further includes an operation of thermally treating the thin layer of dopant-rich semiconductor material to diffuse dopants from the dopant-rich semiconductor material into the underlying layer of semiconductor material, followed by a patterning material removal process to expose the top surface of the layer of semiconductor material for [1] additional dopant addition processes, or [2] further transistor manufacturing operations (e.g., manufacturing of a gate dielectric, manufacturing of a gate electrode, deposition of a dielectric layer, formation of contacts through the dielectric layer to source/drain regions, and so forth). In some embodiments, the dopant addition process includes deposition of a patterning material over the layer of semiconductor material, transferring a pattern to the layer of patterning material, and implantation of dopant atoms into the layer of semiconductor material through openings in the patterned layer of patterning material. In some embodiments, a dopant addition process which includes implantation of dopant atoms into the layer of semiconductor material through openings in the patterned layer of patterning material, a patterning material removal process follows dopant implantation. In some embodiments, patterning material removal processes includes a solvent-based treatment of the patterning material to soften and lift the patterning material from the top surface of the layer of semiconductor material. In some embodiments, patterning material removal processes include a plasma-based removal process having oxygen-based plasma to react with the patterning material. In some embodiments, after a patterning material removal process, a top portion of the layer of semiconductor material is removed to expose unoxidized semiconductor material. Oxidized semiconductor material in the source and/or drain region, or in the channel region of the transistor, increases resistance of the transistor, increasing the electrical current used to operation the transistor. In some embodiments, unremoved oxidized material in the source/drain and/or channel regions of a transistor makes the transistor inoperable because the oxidized material blocks a flow of electrical current through the transistor. An interconnection structure320is over a top surface of layer of semiconductor material305. Interconnection structure320includes conductive vias310A-310N, conductive lines322A-322E, and conductive lines324A-324E. Conductive vias310C-310F are part of interconnections over source region302A, conductive vias310G-3101are part of interconnections over source region302B, and conductive vias310N and310M are interconnections over drain region304. Conductive vias310A-310B and310K-310L are conductive vias outside of source regions302A and302B, and drain region304. Conductive lines322E and324C are part of the interconnection structure over drain region304. Conductive via310N connects conductive line324C to conductive line322E, and conductive via310M connects conductive line322E to N-doped region319C between STI312B1and STI312B2. N-doped region319C is between STI312B1and312B2, and above N-doped well316. Conductive via310C electrically connects to a P-doped region317A at the top level of the layer of semiconductor material, and conductive via310E electrically connects to an N-doped region319A at the top of P-doped well314A. Conductive via310G electrically connects to an N-doped region319B at the top of P-doped well314B, and conductive via3101electrically connects to a P-doped region317B at the top of P-doped well314B. Gate electrode321A extends from a top surface of STI312B1toward N-doped region319A, and gate electrode321B extends from a top surface of STI312B2toward N-doped region319B. In some embodiments, the gate electrode is a polysilicon gate electrode. In some embodiments, the gate electrode includes a polysilicon material with a metal silicide on a surface thereof. In some embodiments, the gate electrode is another electrically conductive material (e.g., a semiconductor material or metal silicide). P-doped region317A is between N-doped region319A and STI structure (STI)312A. P-doped region317B is between N-doped region319B and STI312C. In integrated circuit300, thermal substrate contact318A1extends through STI312A and DTI309A. Thermal substrate contact318A1extends from a top surface of layer of semiconductor material305(or, a top surface of STI312A), through the layer of semiconductor material305, through the oxide layer307, to a top surface of substrate301. Thermal substrate contact318C1extends through STI312C and DTI309D. Thermal substrate contact318C1extends from a top surface of layer of semiconductor material305(or, a top surface of STI312C), through the layer of semiconductor material305, through the oxide layer307, to a top surface of substrate301. Thermal substrate contact318A1has a portion318A2which extends into a recess301RA into the substrate301. Thermal substrate contact318C1has a portion318C2which extends into a recess301RC into the substrate301. In some embodiments, thermal substrate contact318A is formed in a single manufacturing operation (e.g., an operation which includes steps related to etching an opening through STI312A and DTI309A as the layer extend through layer of semiconductor material305, and oxide layer307, and relating to filling the opening with thermally conductive material in a single filling process). In some embodiments, thermal substrate contact318A is formed in multiple manufacturing operations, in which steps related to etching openings and filling the openings are repeated for each layer (e.g., once for a layer of semiconductor material, and once for an oxide layer). In some embodiments, the thermal substrate contact is made of a metallic material such as tungsten (W), cobalt (Co), titanium (Ti), platinum (Pt), nickel (Ni), and alloys thereof. In some embodiments, the thermal substrate contact is made of silicon or a semiconductor material. In some embodiments, the thermal substrate contact material is deposited by epitaxial growth. In some embodiments, the thermal substrate contact material is deposited by sputtering material from a sputtering target. In some embodiments, thermal substrate contact material is different from the electrically-conductive material of the contacts connected to the source or drain regions of the integrated circuit transistors. In some embodiments, a thermal substrate contact is “thermally” connected to the interconnection structure of an integrated circuit by manufacturing a metallic contact similar to a source/drain contact, in direct contact with the top surface of the thermal substrate contact. In some embodiments, thermal substrate contacts include column-like structures extending to the substrate of the integrated circuit. In some embodiments, thermal substrate contacts include bar-like structures extending to the substrate of the integrated circuit (e.g., resulting from formation of a deep trench and filling the deep trench with thermally conductive material). Heat generated by electrical current flowing through transistors of integrated circuit300flows away from the source of the heat generation. In embodiments of integrated circuits having an insulating oxide layer between the layer of semiconductor material having the transistor wells (e.g., source wells and drain wells) and no thermal substrate contact, the heat generated flows up through the interconnection structure of the integrated circuit at a high rate (because the interconnection structure includes metal contacts, vias, conductive lines, and top pads or solder bumps), and down through the oxide layer (e.g., the buried oxide layer) at a low rate (because the oxide layer has a low thermal conductivity with respect to the thermal conductivity of the metal of the interconnection structure). A thermal substrate contact promotes thermal conductivity between the substrate and the interconnection structure of an integrated circuit by providing a thermal bridge between the substrate and the interconnection structure. The thermal substrate contact has a larger thermal conductivity than the oxide layer through which the contact extends. In some embodiments, in addition to providing a thermal bridge for heat to travel between the layer of semiconductor material and the substrate, a thermal substrate contact is configured to apply a voltage to the substrate near a transistor to reduce noise, or to regulate the operation of the transistor gates. For example, thermal substrate contact318A1in integrated circuit300is electrically connected to a conductive via310A. A voltage applied to conductive via310A is transmitted through thermal substrate contact318A1to substrate301, tying the substrate near recess301RA to the applied voltage source. Similarly, thermal substrate contact318C1is electrically connected to a conductive via310K. A voltage applied to conductive via310K is transmitted through thermal substrate contact318C1to substrate301, tying the substrate near recess301RC to the applied voltage source. In some embodiments, a fixed voltage is applied to the substrate near/below a transistor through the thermal substrate contact and the interconnection structure to decrease electrical noise in the integrated circuit. and/or to decrease the influence of an unregulated-voltage applied to the substrate on the transistor and/or and to regulate transistor performance. Unregulated voltages applied to the substrate have a capacitive effect on the layer of semiconductor material, which increases a likelihood of disruption of operation of the transistors because of the influence of the biased substrate (as one plate of a capacitor) on the layer of semiconductor material (as the other plate of a capacitor). In some embodiments, the substrate receives a positive voltage from the IC interconnection structure through the thermal substrate contact. In some embodiments, the substrate receives a negative voltage from the IC interconnection structure through the thermal substrate contact. In some embodiments, the substrate is connected to a reference voltage Vss. In some embodiments, the substrate is connected to an operation voltage Vdd. In some embodiments, the substrate is connected to ground. In some embodiments, the voltage applied to the substrate is between Vddand Vss. In some embodiments, the substrate is electrically connected to the IC interconnection structure by a thermal substrate contact, and the connected voltage (or, the substrate voltage) is allowed to float. FIG.4is a cross-sectional view of an integrated circuit400, in accordance with some embodiments. Elements of integrated circuit400correspond to elements ofFIG.2along cross-sectional line B-B′, incremented by 200. In integrated circuit400, thermal substrate contact418A1and thermal substrate contact418C1are source-region thermal substrate contacts, extending to the substrate near the source region of the transistor. In integrated circuit400, thermal substrate contact418A1extends through layer of semiconductor material405next to source well402A, and oxide layer407to the top surface of substrate401through STI412A and DTI409A. Thermal substrate contact418C1extends through layer of semiconductor material405next to source well402B, and oxide layer407to the top surface of substrate401through STI412C and DTI409D. Thermal substrate contacts418A1and418C1extend from the top of the P-wells414A and414B in the layer of semiconductor material405to below the bottom of the P-wells414A and414B. The thermal substrate contact418A1extends through STI412A. Thermal substrate contact418D is a drain-region thermal substrate contact, which extends through the N-well416in layer of semiconductor material405to the top surface of the substrate401. Sleeve411surrounds thermal substrate contact418B in the layer of semiconductor material405. A bottom edge of the thermal substrate contact418B is directly against the top surface of the substrate401. A bottom edge of sleeve411is directly against the top surface of oxide layer407. A bottom edge of the thermal substrate contact418B extends through an entirety of the oxide layer407. In some embodiments, thermal substrate contact418B extends partially into substrate401(not shown). In some embodiments, sleeve411is a layer of thermally conductive material deposited into an opening in the layer of semiconductor material605to increase thermal conductivity of heat downward toward the substrate601of the integrated circuit. In some embodiments, thermally conductive material used in sleeve411includes silicon, silicon germanium, or a semiconductor material similar to the material of the layer of semiconductor material405. In some embodiments, thermally conductive material used in sleeve411includes tungsten (W), cobalt (Co), titanium (Ti), platinum (Pt), nickel (Ni), and alloys thereof. The thermally conductive material of sleeve411has a thermal conductivity greater than the thermal conductivity of the oxide layer (e.g., oxide layer407). In some embodiments, the thermal conductivity of the material of sleeve411is approximately the same as the thermal conductivity of the substrate. In some embodiments, the material of sleeve411is a metal nitride, where the metal includes tungsten (W), cobalt (Co), titanium (Ti), platinum (Pt), nickel (Ni), and alloys thereof. Using, for a metallic thermal substrate contact, a metal nitride layer having a same metal type as the thermal substrate contact, the adhesion of the thermal substrate contact metal with the liner (e.g., the metal nitride layer) is improved, and filling is more likely to occur without voids in the thermal substrate contact. Voids in the thermal substrate contact reduce the thermal conductivity of the thermal substrate contact by reducing the cross-sectional area of metal in the thermal substrate contact. In embodiments of the sleeve which include a dielectric material, the sleeve material is deposited by, e.g., chemical vapor deposition, physical vapor deposition, and/or processing of exposed semiconductor material with oxygen to grow native oxide. According to some embodiments, the sleeve411and the thermal substrate contact418B are electrically isolated from the integrated circuit, and function as a “heat pipe” to conduct thermal energy through the oxide layer407and into substrate401. In some embodiments, a thermal substrate contact extends into a recess in the substrate401. In some embodiments of thermal substrate contacts which extend into recesses in the substrate, the thermal conductivity is higher than for thermal substrate contacts which do not extend into a recess in the substrate. The increased thermal conductivity results from the increased area of thermal substrate contact material against the substrate to conduct heat into the substrate. In some embodiments, some thermal substrate contacts extend into recesses in the substrate, and some thermal substrate contacts are directly against a top surface of the substrate. The presence or absence of a recess in the substrate below a thermal substrate contact is related to the films/materials through which the thermal substrate contact opening extends. In integrated circuit400, the drain-region thermal substrate contact418B is directly against a top surface of substrate401, while source-region thermal substrate contact418A1and source-region thermal contact substrate418C1have portions (e.g., portion418A2and portion418C2), which extend into recesses in the substrate401. According to some embodiments, a drain-region thermal substrate contact (see thermal substrate contact418A1) extends into a recess (see recess401RA), while source-region thermal substrate contacts (see thermal substrate contact418B) do not extend into a recess, but land on the surface of the substrate. Whether or not a thermal substrate contact extends into a recess is related to the profile of the materials through which the thermal substrate contact extends, the chemistry (wet etch or plasma etch) used to form the opening, and the dimensions (width) of the thermal substrate contacts in each region of the integrated circuit. In integrated circuit400, portion418A2extends into recess401RA, and portion418C2extends into recess401RC. In integrated circuit400, the etch process for forming thermal substrate contact openings was slightly selective to the semiconductor material of layer of semiconductor material405(e.g., the etch rate of layer of semiconductor material405and the oxide layer407in drain region408is slower than the combined etch rate of STI412A and DTI409A and oxide layer407), allowing the thermal substrate contact openings for thermal substrate contacts418A1and418C1to form recesses401RA and401RC. In some embodiments, the combined etch rates of the source and drain regions are reversed (e.g., drain is faster, source is slower) from the present description of integrated circuit400, and the recess is formed below thermal substrate contact of the drain region, rather than below the thermal substrate contacts near the source regions of the integrated circuit. FIG.5is a cross-sectional view of an integrated circuit500, in accordance with some embodiments. Integrated circuit500has elements similar to elements of integrated circuit400, as described above regardingFIG.4. Elements of integrated circuit500which are similar to integrated circuit400inFIG.4have a same identifying reference, incremented by 100 for clarity. Differences between integrated circuit400and integrated circuit500are described below. In integrated circuit500, conductive via510A aligns with thermal substrate contact518A at a top surface of the STI512A (corresponding to the top surface of layer of semiconductor material505), and thermal substrate contact518A extends through STI512A and through layer of semiconductor material505below STI512A, and is separated from DTI509A and509B by part of the layer of semiconductor material505(see also thermal substrate contact518C1which extends through DTI509D near source region502B). DTI506D surrounds a first portion of thermal substrate contact518C1, and STI512C surrounds a second portion of thermal substrate contact518C1, such that thermal substrate contact518C1is physically separated from the layer of semiconductor material505. Thermal substrate contact518C1is in direct contact with oxide layer507, and in direct contact with substrate501. In some embodiments, the thermal substrate contact makes partial contact with one or more DTI structures extending through the layer of semiconductor material, and makes partial contact with the layer of semiconductor material. In some embodiments, the thermal substrate contact is directly against multiple DTI structures extending through the layer of semiconductor material. In some embodiments, only one DTI is against the thermal substrate contact. In some embodiments, the DTI is against the thermal substrate contact for an entirety of the portion of the thermal substrate contact passing through the layer of semiconductor material. In some embodiments, the DTI is against the thermal substrate contact for an entirety of the height of the thermal substrate contact passing through the layer of semiconductor material below a bottom interface between the STI in the layer of semiconductor material. Conductive via510M is above the top surface of sleeve511and above the top surface of layer of semiconductor material505. In some embodiments, the sleeve is a deep trench isolation structure. In some embodiments, the sleeve is a layer of material having a thermal conductivity greater than the thermal conductivity of the oxide layer. In some embodiments, the sleeve is formed at the same time the thermal substrate contact is being filled. In some embodiments, thermal substrate contacts extend entirely through isolation structures (DTI, or STI and DTI) and the oxide layer of an integrated circuit. In some embodiments, thermal substrate contacts extend through an STI, the layer of semiconductor material, and the oxide layer of the integrated circuit (separated from any DTI in the integrated circuit). In some embodiments, the thermal substrate contacts extend through the entire layer of semiconductor material and the entire layer of oxide material of the integrated circuit (separated from any STI or DTI of the integrated circuit). In integrated circuit400, described above, thermal substrate contact418A1extends through STI412A, DTI409A, and oxide layer407, thermal substrate contact418B extends through sleeve411and oxide layer407, and thermal substrate contact418C1extends through STI412C, DTI409D, and oxide layer407. STI412A and DTI409A, combined, extend through an entire width of layer of semiconductor material405. In some embodiments, the STI and DTI also extend down into the oxide layer407. STI412C and DTI409C, combined, extend through an entire width of layer of semiconductor material405. In some embodiments, the STI and DTI also extend down into the oxide layer407. In integrated circuit500, thermal substrate contact518A1extends through STI512A, layer of semiconductor material505, and oxide layer507into the recess501RA; thermal substrate contact518C1extends through STI512C, DTI509D, oxide layer507, and into recess501RC; and thermal substrate contact518B1extends through sleeve511, and oxide layer507into recess501RB in substrate501. The portion of substrate contact518B1which extends into recess501RB is portion518B2, and is in direct contact with substrate501. In some embodiments, all the thermal substrate contacts of the integrated circuit are formed through the layer of semiconductor material (e.g., through a shallow trench isolation structure and the underlying semiconductor material of the layer of semiconductor material). A thermal substrate contact extending through and having a portion thereof directly against the layer of semiconductor material is more efficient at conducting heat away from the layer of semiconductor material than a thermal substrate contact having a sidewall directly against dielectric materials of a shallow trench isolation or deep trench isolation structure. Thermal conductivity efficiency of a thermal substrate contact increases with the amount of surface of area against the substrate and/or layer of semiconductor material because semiconductor materials and substrate materials have a higher thermal conductivity than dielectric materials of isolation structures. In some embodiments, positions of thermal substrate contacts through both epi (semiconductor material) layers and oxide layers (e.g., STO, DTI, oxide layer) are adjusted during a layout phase of the integrated circuit in order to tailor the cooling characteristics of the integrated circuit near transistors which will operate with higher frequency than other transistors of the IC. FIG.6Ais a top view of an integrated circuit600having thermal substrate contacts, in accordance with some embodiments. Elements of integrated circuit600which correspond to elements of integrated circuit300inFIG.3have a same identifying reference incremented by 300. Cross sectional line C-C′ extends through a source region602A having therein a thermal substrate contact618A, through active area regions606A and606B (having channels of an integrated circuit transistor located therein in the layer of semiconductor material), through thermal substrate contact618B in drain region604A, and through thermal substrate contact618C in source region602B. Each of source region602A, source region602B, and source region602C, as well as drain regions604A-B have more than one thermal substrate contact therein. In some embodiments, thermal substrate contacts are located only in source regions (see, e.g., source region602A). In some embodiments, thermal substrate contacts are located only in drain regions of the integrated circuit (see, e.g., drain region604A). In some embodiments, not all source regions (or, drain regions) have a same number of thermal substrate contacts. In some embodiments, each source region has a same number of thermal contacts as each other source region and each drain region. In some embodiments, at least one source region has a different number of thermal contacts from at least one other source region or at least one drain region. In some embodiments, some source regions have thermal substrate contacts, and other source regions have no thermal substrate contacts. In some embodiments, some drain regions have thermal substrate contacts, and other drain regions have no thermal substrate contacts. FIG.6Bis a cross-sectional view of an integrated circuit640corresponding to the cross section C-C′ ofFIG.6A, in accordance with some embodiments. Elements of integrated circuit640which correspond to elements of integrated circuit300inFIG.3have a same identifying reference, incremented by 300. In integrated circuit640, the source region602A includes two N-doped regions617A and617B in P-doped well614A. N-doped region617A is on a same side of thermal substrate contact618A as gate electrode616A (and adjoins a channel621A below gate electrode616A). N-doped region617B is on a same side of thermal substrate contact618A as gate electrode616B (and adjoins a channel621B below gate electrode616B). Similarly, N-doped region617C is in P-doped well614C on a same side of thermal substrate contact618C as gate electrode616C (and adjoins a channel621C below gate electrode616C). N-doped region617D is in P-doped well614C on a same side of thermal substrate contact617C as gate electrode616D, and adjoins a channel621D below gate electrode616D. Gate electrode616A is against a top surface of STI612A and over channel621A, gate electrode616B is against a top surface of STI612B and over channel621B, gate electrode616C is against a top surface of STI613C and over channel621C, and gate electrode616D is against a top surface of STI612D and over channel621D. According to some embodiments, the dopant patterns described hereinabove for integrated circuit are reverse, such that the wells are N-doped and the regions analogous to N-doped regions617A-617D are P-doped. Thermal substrate contact618B extends through layer of semiconductor material605and is isolated from the HVNW615B and HVNW615C on either side of DTI611B, such that thermal substrate contact618B is electrically isolated from layer of semiconductor material605by DTI611, and by oxide layer607. While DTI611A,611B, and611C extend down through the layer of semiconductor material605, and down to oxide layer607, in some embodiments, DTI extend down into oxide layer607. Thermal substrate contacts618A and618C provide increased capacity as compared to thermal substrate contacts518A1and518C1in integrated circuit500to conduct heat from the transistors in the layer of semiconductor material605because the thermal substrate contacts are not separated from the transistors by an isolation structure outside the well of the transistor. Thermal substrate contact618A is separated from the well614A by DTI611A, which is in the well614A. Thermal substrate contact618C is separated from the well614C by DTI611C, which is in well614C. Channels621A,621B are part of a split gate transistor structure, where each of the two gates (e.g., gate electrodes616A and616B) is readied for operation by applying current through a single current path: conductive line624A through conductive vias610A and610C, such that, upon activation of one or both of gate electrodes616A or616B, current is directed through a channel adjacent to the thermal substrate contact618A. Channels621C, and621D are part of a second split gate transistor structure, and the two gates (e.g., gate electrodes616C and616D) are readied for operation by applying current through a single current path: conductive line624B through conductive vias610E and610G, such that, upon activation of one or both of gate electrodes616C or616D, current is directed through a channel adjacent to the thermal substrate contact618C. Drain well614B is configured to receive current from either of channel621B or621C upon activation of the appropriate gate electrode. Conductive line625D is electrically connected to a drain-region thermal substrate contact618B. A top end of thermal substrate contact618B is at the same level as the top of conductive line625D. FIGS.7A-7Bare top views of embodiments of an integrated circuit700, and an integrated circuit740, in accordance with some embodiments. InFIG.7A, an active area702(e.g., a drain region or a source region, as described hereinabove forFIGS.2and6A) has thermal substrate contacts704situated within the active area. The active area702has a first width702W. The thermal substrate contacts704have a contact width704W. InFIG.7A, thermal substrate contact width704W is smaller than first width702W of the active area702, and the thermal substrate contacts704are laterally surrounded on four sides by the active area702. According to some embodiments, a thermal substrate contact width is not less than 10% of the active area width. In some embodiments, the thermal substrate contact width is not greater than 110% of an active area width. In embodiments where the thermal substrate contact width is less than 10% of the active area width, the thermal substrate contact is difficult to fill without creating voids during a filling or deposition step to add the thermal substrate contact material in the opening. In embodiments where the thermal substrate contact width is greater than 110% of the active area width, the thermal substrate contact crowds the transistor channels or other features of the integrated circuit near the thermal substrate contact. FIG.7Bis a top view of an integrated circuit740having therein an active area border region742and a plurality of thermal substrate contacts744. Active area border region742has an active area border width742W. Thermal substrate contacts744have a contact width744W. In integrated circuit740, active area border width742W is smaller than or equal to contact width744W. In some embodiments, the active area border742has openings in a top surface thereof which divide the top surface into separate discontinuous regions. In some embodiments, the thermal substrate contacts744divide the semiconductor material of the active area border into a plurality of portions of material which are completely separated from each other by the thermal substrate contacts extending therethrough. According to some embodiments, the thermal substrate contacts in an active area border have a contact width ranging from about 20% of the active area border width, up to more than 100% of the active area border width, as measured at the top surface of the active area border. Thermal substrate contacts having a contact width smaller than about 20% of the active area border width do not provide a sufficient path for removing heat from the substrate, or from the active area above the substrate, to appreciably increase the cooling capacity of an integrated circuit. Thermal substrate contacts having a contact width greater than 100% of the active area border width encroach on transistors or other elements of the integrated circuit in the layer of semiconductor material. FIG.8is a top view of an integrated circuit800, in accordance with some embodiments. Elements of integrated circuit800which are similar to elements of integrated circuit200inFIG.2are identified with a similar reference numeral, incremented by 600. Integrated circuit800includes source regions802A,802B, and802C, drain regions804A and804B, and active regions812A-C. In integrated circuit800, drain region804A has three thermal substrate contacts808A,808B, and808C at interior positions in the drain region. In drain region804A, thermal substrate contact808A separates N-well806A from N-well806B, thermal substrate contact808B separates N-well806B from N-well806C, thermal substrate contact808C separates N-well806C from N-well806D. N-wells806A and806D are terminal N-wells of the drain region804A. In drain region804B, N-wells813A,813B, and813C are at interior positions of the drain region, and N-well813A separates thermal substrate contact810A from thermal substrate contact810B, N-well813B separates thermal substrate contact810B from thermal substrate contact810C, and N-well813C separates thermal substrate contact810C from thermal substrate contact812D. Thermal substrate contacts810A and810D are terminal contacts of the drain region804B. FIG.9is a top view of an integrated circuit900, in accordance with some embodiments. Elements of integrated circuit900which are similar to elements of integrated circuit200inFIG.2are identified with a similar reference numeral, incremented by 700. Integrated circuit900includes source regions902A,902B, and902C. Drain region904A is between source region902A and902B. Drain region904B is between source region902B and source region902C. Active area region912A separates source region902A from drain region904A. Active area region912B separates drain region904A from source region902B. Active area region912C separates source region902B from drain region904B. Drain region904A includes a first thermal substrate contact906A and a second thermal substrate contact906B. First thermal substrate contact906A has a contact width914W and second thermal substrate contact906B has a contact width916W. Drain region904A is an N-doped well having a width equal to region width913W. Thermal substrate contact906A has a contact width914W, and thermal substrate contact906B has a contact width916W. The sum of contact width914W and contact width916W ranges from 20% to 100% of the region width913W. In some embodiments, contact width914W, and contact width916W, are greater than about 10% of region width913W. A thermal substrate contact having a contact width less than 10% of the region width913W is difficult to fill without creating voids in the contact. The sum of contact widths in a drain region (e.g.,914W and916W) is not greater than the region width (see region width913W) because the thermal substrate contact extending beyond a perimeter of the region intrudes on other cells or elements of the integrated circuit. In some embodiments, contact width914W is smaller than contact width916W. In some embodiments, contact width914W is greater than contact width916W. In some embodiments, contact width914W is the same as contact width916W. Drain region904B is an N-doped well having a width equal to region width913W. Thermal substrate contact908A has contact width924W, and thermal substrate contact908B has contact width926W. Contact widths in different N-doped wells, or different drain regions, are independent of each other. In some embodiments, contact width914W is larger than contact width924W. In some embodiments, contact width914W is smaller than contact width924W. In some embodiments, contact width914W is equal to contact width924W. Similarly, in some embodiments, contact width916W is larger than contact width926W. In some embodiments, contact width916W is smaller than contact width926W. In some embodiments, contact width916W is equal to contact width926W. A width of an individual thermal substrate contact (e.g., a dimension parallel to the direction of the source region (see source region902A)), is determined at a design phase of the IC manufacturing process in order to achieve a cooling performance specification based on transistor density in the region of the integrated circuit. In embodiments wherein the surface density, or coverage area, of thermal substrate contacts varies strongly across the integrated circuit, loading effects during etch processes to form thermal substrate contact openings in the layer of semiconductor material, and/or in the oxide material, make CD (critical dimension, e.g., the dimensions of openings, or other features on an IC substrate) control difficult. Loading effects result in variable contact widths across the surface of the substrate. In some embodiments, a pattern of variation in contact widths also results in a correlating pattern of recess locations across the integrated circuit. Larger contact openings have a higher frequency of recesses in the substrate than smaller contact openings because the substrate is exposed to more etchant through large openings. FIG.10Ais a block diagram of an integrated circuit1000, in accordance with some embodiments. In integrated circuit1000, a first source region1002A and a second source region1002B are separated within the cell boundary1008by a drain1004. Thermal substrate contacts1006are located within the cell boundary outside the active area wherein the first source region1002A, the second source region1002B, and the drain1004are located. FIG.10Bis a block diagram of an integrated circuit1020, in accordance with some embodiments. In integrated circuit1020, a cell boundary1028includes a plurality of source regions1022A,1022B, and1022C, as well as a plurality of drain regions1024A and1024B. A plurality of thermal substrate contacts1026C are located in the cell boundary1028to conduct heat from the cell into the substrate below the transistors. According to some embodiments of the present disclosure, the active area within a cell boundary (see cell boundary1008) includes as few as one source region and one drain region, up to as many as 32 source regions and 32 drain regions, although other numbers of source regions and drain regions are also contemplated within the scope of the present disclosure. Aspects of the present disclosure relate to an integrated circuit which includes an oxide layer over a substrate; a layer of semiconductor material over the oxide layer and having therein a P-well, an N-well, and a channel of a transistor; and a thermal substrate contact extending through the layer of semiconductor material and the oxide layer, and against a top surface of the substrate. In some embodiments, the integrated circuit further includes an isolation structure in the layer of semiconductor material, where the thermal substrate contact extending through the isolation structure. In some embodiments, the thermal substrate contact extends into the substrate from an isolation region around the transistor. In some embodiments, the integrated circuit further includes a thermally conductive sleeve, wherein the thermal substrate contact extends through the thermally-conductive sleeve and the oxide layer. In some embodiments, the thermally-conductive sleeve extends through the layer of semiconductor material and against a top surface of the oxide layer. In some embodiments, the thermal substrate contact is electrically connected to a fixed voltage source of the integrated circuit. In some embodiments, the thermal substrate contact floats electrically within the integrated circuit. Aspects of the present disclosure relate to a method of making an integrated circuit which includes operations related to forming an oxide layer over a top surface of a substrate; depositing a layer of semiconductor material over the oxide layer; and manufacturing a thermal substrate contact extending through the layer of semiconductor material and the oxide layer to the top surface of the substrate, wherein the thermal substrate contact is against, but does not extend through, the substrate. In some embodiments, manufacturing a thermal substrate contact further includes operations of etching a first opening through the layer of semiconductor material to expose the oxide layer; etching a second opening through the first opening to expose the substrate; and filling the first opening and the second opening with a conductive material. In some embodiments, filling the first opening and the second opening further includes operations of depositing a metallic layer into the first opening and the second opening; and planarizing the metallic layer to expose the layer of semiconductor material. In some embodiments, the method further includes operations of manufacturing a transistor having, in the layer of semiconductor material, an N-well, a P-well, and a channel; and manufacturing an interconnection structure of the integrated circuit over the layer of semiconductor material, wherein, the manufacturing an interconnection structure of the integrated circuit further includes an operation of electrically insulating the thermal substrate contact from the interconnection structure in the integrated circuit. In some embodiments, the method further includes operations of manufacturing a transistor having, in the layer of semiconductor material, an N-well, a P-well, and a channel; and manufacturing an interconnect structure over the thermal substrate contact, wherein the thermal substrate contact is electrically connected to the interconnect structure. In some embodiments, the method further includes connecting the thermal substrate contact, through the interconnect structure, to a fixed voltage source of the integrated circuit. In some embodiments, the method further includes connecting the thermal substrate contact, through the interconnect structure, to a floating voltage source of the integrated circuit. In some embodiments, manufacturing a thermal substrate contact further includes manufacturing an isolation structure in the layer of semiconductor material; etching a first opening through the isolation structure and the layer of semiconductor material; and filling the first opening through the isolation structure and the layer of semiconductor material with a first conductive material. In some embodiments, manufacturing a thermal substrate contact further includes etching a second opening through the oxide layer to expose the substrate; and filling the second opening with a second conductive material. Some aspects of the present disclosure relate to a device which includes an oxide layer on a substrate top surface; a layer of semiconductor material against an oxide layer top surface; and a first thermal substrate contact extending through a first doped well in the layer of semiconductor material, and a second thermal substrate contact extending through a second doped well in the layer of semiconductor material, a channel region of a transistor being between the first doped well and the second doped well. In some embodiments, the first doped well is a source well and the second doped well is a drain well. In some embodiments, the first doped well is a first source well and the second doped well is a second source well. The foregoing outlines features of several embodiments so that those skilled in the art may better understand the aspects of the present disclosure. Those skilled in the art should appreciate that they may readily use the present disclosure as a basis for designing or modifying other processes and structures for carrying out the same purposes and/or achieving the same advantages of the embodiments introduced herein. Those skilled in the art should also realize that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and that they may make various changes, substitutions, and alterations herein without departing from the spirit and scope of the present disclosure. | 71,083 |
11862528 | DETAILED DESCRIPTION The following disclosure provides many different embodiments, or examples, for implementing different features of the invention. Specific examples of components and arrangements are described below to simplify the present disclosure. These are, of course, merely examples and are not intended to be limiting. For example, the formation of a first feature over or on a second feature in the description that follows may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features may be formed between the first and second features, such that the first and second features may not be in direct contact. In addition, the present disclosure may repeat reference numerals and/or letters in the various examples. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed. Various features may be arbitrarily drawn in different scales for the sake of simplicity and clarity. Furthermore, spatially relative terms, such as “beneath,” “below,” “lower,” “above,” “upper” and the like, may be used herein for ease of description to describe one element or feature's relationship to another element(s) or feature(s) as illustrated in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The apparatus may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein may likewise be interpreted accordingly. Generally, the present disclosure provides example embodiments relating to a semiconductor package including a heat spreader with high thermal conductivity and the method of forming the same. The intermediate stages of forming the semiconductor package are illustrated. Some variations of the embodiments are described. Throughout the various views and illustrative embodiments, like reference numbers are used to designate like elements. FIGS.1A-1Gare cross-sectional views of a semiconductor package100(seeFIG.2A) at various stages of fabrication in accordance with some embodiments. It should be understood thatFIGS.1A-1Ghave been simplified for a better illustration of the concepts of the present disclosure. Moreover, the materials, geometries, dimensions, structures, and process parameters described herein are only illustrative, and are not intended to be, and should not be constructed to be, limiting to the present disclosure. Many alternatives and modifications will be apparent to those skilled in the art, once informed by the present disclosure. Referring toFIG.1A, a carrier101is provided. The carrier101may be configured to provide structural rigidity or a base for deposition of subsequent material layers or films. The carrier101is a substrate carrier or a semiconductor wafer carrier (e.g., silicon wafer) in some embodiments. However, the carrier101may also be a glass carrier, a ceramic carrier, or the like. A package substrate102is formed on the carrier101. The package substrate102may include one or more dielectric layers. Conductive redistribution lines1021(e.g., metal lines) may be formed in or between the dielectric layers to electrically couple a number of conductive features1022,1023(e.g., conductive pads) on opposite surfaces of the package substrate102. For example, the package substrate102may be formed by depositing dielectric layers through a chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), spin-on coating, lamination, or another suitable deposition process, depositing metal layers on or between the dielectric layers through any suitable deposition process described above, and patterning the metal layers to form the conductive redistribution lines1021and conductive features1022,1023through a lithography process and an etching process (e.g., wet or dry etching process). In some embodiments, the dielectric layers comprise polymer, polyimide, silicon oxide, silicon nitride, or another suitable dielectric material. The metal layers comprise Cu, Pt, Ag, Ni, another suitable metal, alloys thereof, or a combination thereof. As shown inFIG.1A, the package substrate102has a first surface102A (e.g., the bottom surface) attached to the carrier101and a second surface102B (e.g., the top surface) opposite to the first surface102A. The conductive features1023exposed to the second surface102B are configured to be electrically connected to the chips103(seeFIG.1B), and the conductive features1022exposed to the first surface102A are configured to be electrically connected to an external device (e.g., a printed circuit board (PCB) (not shown)). In some embodiments, the package substrate102also includes active and/or passive components (not shown). Referring toFIG.1B, a number of chips103are mounted on the package substrate102(only one chip103is depicted for simplicity). The chips103may be mounted on the second surface102B (the top surface) of the package substrate102(i.e., they may be electrically connected to the conductive features1023) by electrical connectors104, such as a ball grid array (BGA). In some embodiments, the electrical connectors104comprise lead-free solder or the like. A reflow process (not shown) may be performed to make the metallurgical connections in a chip-solder-chip carrier (i.e., the chip103-the electrical connectors104-the package substrate102). The chips103may be any suitable integrated circuit (IC) chip or die for a particular application. For example, the chips103may be memory chips, logic chips, processor chips, or the like. Referring toFIG.1C, an underfill material105is dispensed (e.g., by a dispenser (not shown)) into the space between each chip103and the package substrate102and the space between adjacent electrical connectors104, and then cured (e.g., ultraviolet (UV) or thermally cured) to harden. The underfill material105may be configured to provide a stronger mechanical connection and a heat bridge between the103chip and the package substrate102, to reduce cracking in the electrical connectors104caused by thermal expansion mismatches between the chip103and the package substrate102, and to protect the joints from contaminants, thereby improving reliability of the fabricated semiconductor package100(FIG.2A). In some embodiments, the underfill material105comprises liquid epoxy, deformable gel, silicon rubber, or the like. Afterwards, a molding compound106is formed over the package substrate102and encapsulates the side periphery of each chip103. The molding compound106may be configured to provide package stiffness, a protective or hermetic shielding, and/or provide a heat conductive path to prevent chip overheating. The molding compound106may be formed by a spin-on coating process, an injection molding process, or the like. In some embodiments, the molding compound106comprises epoxy, epoxy with thermally conductive filler materials, plastic molding compound, or another suitable material. In some embodiments, the molding compound106is formed in such a way that its top surface106A is substantially level (coplanar) with the top surface103A of chip103(i.e., the top surface103A of chip103is exposed as shown inFIG.1C). For example, the molding compound106may be formed to cover the top surface103A of chip103, and then planarized by a chemical mechanical polishing (CMP) process or another suitable grinding or etching process to remove a portion of the molding compound106to expose the top surface103A of chip103. Referring toFIG.1D, a heat spreader107and a thermal interface material (TIM)108are provided, and the thermal interface material108is dispensed (e.g., by a dispenser (not shown)) on the bottom surface107A of the heat spreader107. For example, the thermal interface material108may be dispensed on the heat spreader107when its bottom surface107A faces upward, and then the heat spreader107with the thermal interface material108are flipped as shown inFIG.1D. The heat spreader107may have high thermal conductivity. Furthermore, the heat spreader107may be flexible. In some embodiments, the heat spreader107is a graphite sheet having a thermal conductivity between about 1000 W/m-K and 1800 W/m-K. Alternatively, the heat spreader107may be a graphite sheet with metal reinforcement (i.e., it may comprise a metal material such as copper, aluminum, or another suitable metal) so that the structural strength of heat spreader107is further improved to prevent it from crushing or cracking easily. It should be appreciated that a graphite sheet used as the heat spreader107may have a higher thermal conductivity than a typical metal heat spreader, and may be flexible in order to facilitate the subsequent attachment process. In some embodiments, the thickness T1of the heat spreader107may be in a range between about 15 microns and about 70 microns to have a good flexibility. The shape and size (in a top view) of the heat spreader107may correspond to those of the package substrate102. The thermal interface material108may have a higher thermal conductivity than a typical adhesive material, however, the thermal conductivity of the thermal interface material108may still be much lower than that of the heat spreader107. In some embodiments, the thermal interface material108has a thermal conductivity between about 3 W/m-K and 8 W/m-K, although its thermal conductivity may also be slightly higher or lower. The thermal interface material108may comprise an organic material, and it may also act as an adhesive. In some embodiments, the thermal interface material108comprises a polymer matrix, a phase change polymer, a silicone-based matrix, a matrix additive (fluxing agent), a filler material (a metallic core with an organic solderability preservative coating), or the like. The thermal interface material108may be dispensed in a liquid form that has a high viscosity. After the thermal interface material108is applied to the bottom surface107A of the heat spreader107, the heat spreader107is attached to the chip103and the molding compound106by the thermal interface material108. In the embodiments illustrated inFIG.1D, after the heat spreader107with the thermal interface material108is placed over the chip103and molding compound106, an attachment process is performed. The attachment process includes rolling a rod R over the top surface107B of the heat spreader107(e.g., from one side (such as the left side in the figure) of the heat spreader107to the opposite side (such as the right side in the figure) thereof) to attach the heat spreader107to the chip103and molding compound106through the thermal interface material108. By doing it this way, the flexible heat spreader107can be easily and smoothly attached to the top surface103A of the chip103and the top surface106A of the molding compound106. Referring toFIG.1E, a compression process is performed (as indicated by the arrows inFIG.1E), in which the thermal interface material108below the heat spreader107is subjected to a compression force (e.g., by pressing a compression part or body (not shown) with appropriate weight against the top surface107B of the heat spreader107) for a period of time. Afterwards, a curing process is performed to fully cure the thermal interface material108. In the curing process, the thermal interface material108is subjected to a hot plate or oven, for example at a temperature of above 100° C. for a period of time in some embodiments. Once the compression and curing process is completed, the heat spreader107and the underlying thermal interface material108may uniformly cover the entire top surface103A of the chip103and the entire top surface106A of the molding compound106. Referring toFIG.1F, another carrier101′, similar to the carrier101(FIG.1E), is bonded to the top of the resulting structure ofFIG.1E(i.e., the heat spreader107), and then the carrier101is detached from the package substrate102. In some embodiments, a sacrificial layer (not shown) is formed between the carrier101and the package substrate102. When the sacrificial layer is removed by any suitable etching or cutting process, the carrier101can be detached from the package substrate102. Afterwards, a number of electrical connectors109, such as BGA, may be formed on the first surface102A of the package substrate102(i.e., they are electrically connected to the conductive features1022), in some embodiments as shown inFIG.1F. The electrical connectors109may be configured to electrically connect the fabricated semiconductor package100(FIG.2A) to an external device (e.g., a PCB (not shown)). In some embodiments, the electrical connectors109comprise lead-free solder or the like. Referring toFIG.1G, the resulting structure ofFIG.1Fis placed so that the electrical connectors109side is affixed to a dicing tape D or a die frame (not shown), and then the carrier101′ (FIG.1F) is detached from the heat spreader107by, for example the detaching process for the carrier101described above. Afterwards, a singulation process (also referred to as a saw process) is performed. In the singulation process, the heat spreader107, thermal interface material108, molding compound106, and package substrate102are die cut or diced along cutting lines C (depicted by dashed lines) to separate the package of the chip103, heat spreader107, and thermal interface material108into individual units. Each individual unit (i.e. a semiconductor package100unit) includes the heat spreader107attached to the chip103by the thermal interface material108. After removing the dicing tape D, the fabrication of a semiconductor package100(FIG.2A) is completed. It should be understood that the chip103(especially for that having a high power requirement) of the semiconductor package100can result in localized overheating H during the operation, as shown inFIG.2A. With the heat spreader107attached on top of the chip103, it provides a thermal path through which heat that is generated by the chip103is dissipated to the surrounding environment to prevent chip overheating. For example, when the localized overheating H is close to the center position of the heat spreader107, the heat may be conducted from the chip103to the center position of the heat spreader107through the thermal interface material108, then spread horizontally over the entire heat spreader107(i.e., conducted from the center position to other positions), and finally dissipated to the surrounding environment (the thermal path through the thermal interface material108and heat spreader107is shown by the arrows depicted inFIG.2A). It should be appreciated that the heat spreader107utilizing a graphite sheet may provide a high degree of heat dissipation, especially in the horizontal direction, thereby avoiding overheating of the chip103(i.e., the heat generated by the chip103can be dissipated or removed rapidly). Moreover, the semiconductor package100can also have a small thickness T due to the thin heat spreader107. Although not shown, it should be understood that the heat generated by the chip103may also be conducted to the electrical connectors109side of the semiconductor package100(alternatively be further conducted to the external device such as PCB) through the electrical connectors104and the metal lines in the package substrate102, but the heat dissipation by this thermal path is relatively low. FIG.2Bis a cross-sectional view of a semiconductor package100′ including a heat sink112in accordance with some embodiments. In the semiconductor package100′, a heat sink112is attached on top of the heat spreader107by a thermal interface material (TIM)113to facilitate the dissipation of heat from the chip103. The thermal interface material113may be similar to the thermal interface material108, and is not repeated here. The heat sink112may be formed of a metal or a metal alloy that has a high thermally conductivity. It should be appreciated that the heat spreader107can support the heat sink112(i.e., withstand the loading of the heat sink112) and protect the chip103from being easily damaged due to direct contact with the heat sink112without unduly hindering heat transfer to the heat sink112. Accordingly, the thermal and mechanical performance of the semiconductor package using the heat spreader107are also improved. FIG.3Ais a cross-sectional view of a semiconductor package300including multiple chips in accordance with some embodiments. As shown inFIG.3A, the semiconductor package300includes two chips1031and1032. However, the semiconductor package300according to other embodiments may also include more than two chips. Other elements of the semiconductor package300indicated with the same reference numerals as the corresponding elements of the semiconductor package100or100′ may be similar or identical to the elements of the semiconductor package100or100′, and the descriptions of those are omitted. In the embodiments illustrated inFIG.3A, the two chips (such as a first chip1031and a second chip1032) mounted on the top surface102B of the package substrate102have different thicknesses. For example, the thickness of first chip1031is greater than the thickness of the thickness of second chip1032. However, the first chip1031and second chip1032may have the same thickness in alternative embodiments. In some embodiments, the first chip1031is a memory chip, and the second chip1032is a process chip, although the chips1031and1032may be other type of chips in any combination. In some embodiments, at least one of the chips1031and1032(e.g., the second chip1032) can result in localized overheating H during the operation. Being flexible, the heat spreader107(e.g., a graphite sheet) conforms to the profile of top surface1031A of the first chip1031and the profile of top surface1032A of the second chip1032when it is attached on top of the first chip1031and the second chip1032by the thermal interface material108. As shown inFIG.3A, when the heat spreader107is attached on top of the first chip1031and the second chip1032, it covers the entire top surface1031A of the first chip103and the entire top surface1032A of the second chip1032. Furthermore, a first portion P1of the heat spreader107over the first chip1031and a second portion P2of the heat spreader107over the second chip1032have the same thickness T1(similarly, a first portion of the thermal interface material108over the first chip1031and a second portion of the thermal interface material108over the second chip1032have the same thickness). In some embodiments, the heat spreader107over the first chip1031, second chip1032, and molding compound106has a uniform thickness. As described above, the semiconductor package300may have a small thickness T due to the thin heat spreader107. With the above configuration, the heat spreader107provides a thermal path through which heat that is generated by at least one of the chips1031and1032is dissipated to the surrounding environment to prevent chip overheating. For example, when a localized overheating H occurs on the second chip1032, the heat may be conducted from the second chip1032to the heat spreader107through the thermal interface material108, then spread horizontally over the entire heat spreader107(i.e., conducted from one position close to the second chip1032to other positions), and finally dissipated to the surrounding environment (the thermal path through the thermal interface material108and heat spreader107is shown by the arrows depicted inFIG.3A). Accordingly, the overheating issue of the second chip1032can be solved. The heat generated from the first chip1031may also be dissipated to the surrounding environment through the thermal interface material108and heat spreader107. Referring toFIG.3B, in some alternative embodiments, a (metal) heat sink112with a bottom surface that conforms to the profile of the top surface of the heat spreader107may also be attached on top of the heat spreader107by a thermal interface material113to facilitate the dissipation of heat from the chips1031and1032. The heat spreader107can further support the heat sink112(i.e., withstand the loading of the heat sink112) and protect the chips1031and1032from being easily damaged due to direct contact with the heat sink112without unduly hindering heat transfer to the heat sink112. Accordingly, the thermal and mechanical performance of the semiconductor package300′ using the heat spreader107are also improved. It should be understood that the semiconductor package300(FIG.3A) with multiple chips may also be formed by the fabrication method illustrated inFIGS.1A-1G. For example, as shown inFIG.4, after the heat spreader107with the thermal interface material108is placed over the chips1031,1032and the molding compound106, an attachment process is performed. The attachment process (similar to the attachment process shown inFIG.1D) includes rolling a rod R over the top surface107B of the heat spreader107(e.g., from one side (such as the left side in the figure) of the heat spreader107to the opposite side (such as the right side in the figure) thereof) to attach the heat spreader107to the chips1031and1032and the molding compound106through the thermal interface material108. By doing it this way, the flexible heat spreader107can be easily and smoothly attached to the top surface1031A of the first chip1031, the top surface1032A of the second chip1032, and the top surface106A of the molding compound106(i.e., to conform to the profile of the top surfaces of the first chip1031, the second chip1032and the molding compound106). FIG.5is a cross-sectional view of a semiconductor package500including multiple package units stacked on each other in accordance with some embodiments. As shown inFIG.5, the semiconductor package500includes two stacking package units510and520. However, the semiconductor package500according to other embodiments may also include more than two stacking package units. The first package unit510(also referred as a bottom packing unit) may be configured to be electrically connected to an external device (e.g., a PCB (not shown)), and the second package unit520(also referred as a top packing unit) may be configured to be stacked on top of the first package unit510and electrically connected to the first package unit510. FIGS.6A-6Pare cross-sectional views of the semiconductor package500inFIG.5at various stages of fabrication in accordance with some embodiments, whereinFIGS.6A-6Hschematically shows the first package unit at various stages of fabrication andFIGS.6I-6Pschematically shows the second package unit at various stages of fabrication. It should be understood thatFIGS.6A-6Phave been simplified for a better illustration of the concepts of the present disclosure. Moreover, the materials, geometries, dimensions, structures, and process parameters described herein are only illustrative, and are not intended to be, and should not be constructed to be, limiting to the present disclosure. Many alternatives and modifications will be apparent to those skilled in the art, once informed by the present disclosure. Referring toFIG.6A, a first carrier511is provided. The first carrier511may be configured to provide structural rigidity or a base for deposition of subsequent material layers or films. The first carrier511is a substrate carrier or a semiconductor wafer carrier (e.g., silicon wafer) in some embodiments. However, the first carrier511may also be a glass carrier, a ceramic carrier, or the like. A first package substrate512is formed on the first carrier511. The first package substrate512may include one or more dielectric layers. Conductive redistribution lines5121(e.g., metal lines) may be formed in or between the dielectric layers to electrically couple a number of conductive features5122and5123(e.g., conductive pads) on opposite surfaces of the first package substrate512. For example, the first package substrate512may be formed by depositing dielectric layers through a chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), spin-on coating, lamination, or another suitable deposition process, depositing metal layers on or between the dielectric layers through any suitable deposition process described above, and patterning the metal layers to form the conductive redistribution lines5121and conductive features5122,5123through a lithography process and an etching process (e.g., wet or dry etching process). In some embodiments, the dielectric layers comprise polymer, polyimide, silicon oxide, silicon nitride, or another suitable dielectric material. The metal layers comprise Cu, Pt, Ag, Ni, another suitable metal, alloys thereof, or a combination thereof. As shown inFIG.6A, the first package substrate512has a first surface512A (e.g., the bottom surface) attached to the first carrier511and a second surface512B (e.g., the top surface) opposite to the first surface512A. The conductive features5123exposed to the second surface512B are configured to be electrically connected to first chips513(seeFIG.6B), and the conductive features5122exposed to the first surface512A are configured to electrically connect to an external device (e.g., a PCB (not shown)). In some embodiments, the first package substrate512also includes active and/or passive components (not shown). Furthermore, a number of through vias5124(i.e., metal pillars) are formed over the first package substrate512and are electrically connected to some conductive features5123. The through vias5124(also referred to as “through integrated fan-out (InFO) vias (TIV)”) may be configured to electrically connect the first package unit510to the second package unit520(seeFIG.5). In some embodiments, the through vias5124comprise Cu, Pt, Ag, Ni, another suitable metal, alloys thereof, or a combination thereof. For example, the through vias5124may be formed by depositing a dielectric layer over the first package substrate512through any suitable deposition process described above, patterning the dielectric layer through a lithography process and an etching process (e.g., wet or dry etching process) to form a number of openings or holes corresponding to some conductive features5123, forming metal features (e.g., metal pillars) in the openings through plating (e.g., electro plating or electro-less plating), and removing the dielectric layer through any suitable etching process. Referring toFIG.6B, a number of first chips513are mounted on the first package substrate512(only one first chip513is depicted for simplicity). The first chips513may be mounted on the second surface512B (the top surface) of the first package substrate512(i.e., they are electrically connected to the conductive features5123) by electrical connectors514, such as a ball grid array (BGA). In some embodiments, the electrical connectors514comprise lead-free solder or the like. A reflow process (not shown) may be performed to make the metallurgical connections in a chip-solder-chip carrier (i.e., the first chip513-the electrical connectors514-the first package substrate512). The first chips513may be any suitable integrated circuit (IC) chip or die for a particular application. For example, the first chips513may be memory chips, logic chips, processor chips, or the like. Referring toFIG.6C, an underfill material515is dispensed (e.g., by a dispenser (not shown)) into the space between each first chip513and the first package substrate512and the space between adjacent electrical connectors514, and then cured (e.g., ultraviolet (UV) or thermally cured) to harden. The underfill material515may be configured to provide a stronger mechanical connection and a heat bridge between the first chip513and the first package substrate512, to reduce cracking in the electrical connectors514caused by thermal expansion mismatches between the first chip513and the first package substrate512, and to protect the joints from contaminants, thereby improving reliability of the fabricated semiconductor package500(FIG.5). In some embodiments, the underfill material515comprises liquid epoxy, deformable gel, silicon rubber, or the like. Afterwards, a molding compound516is formed over the first package substrate512and encapsulates the side periphery of each first chip513(i.e., fills the gaps between the first chip513and the adjacent through vias5124). The molding compound516also encapsulates the side peripheries of the through vias5124so that the through vias5124are formed in the molding compound516. The molding compound516may be configured to provide package stiffness, a protective or hermetic shielding, and/or provide a heat conductive path to prevent chip overheating. The molding compound516may be formed by a spin-on coating process, an injection molding process, or the like. In some embodiments, the molding compound516comprises epoxy, epoxy with thermally conductive filler materials, plastic molding compound, or another suitable material. In some embodiments, the molding compound516is formed in such a way that its top surface516A is substantially level (coplanar) with the top surface513A of first chip513and the top surface5124A of through vias5124(i.e., the top surface513A of first chip513and the top surface5124A of through vias5124are exposed as shown inFIG.6C). For example, the molding compound516may be formed to cover the top surface513A of first chip513and the top surface5124A of through vias5124, and then planarized by a chemical mechanical polishing (CMP) process or another suitable grinding or etching process to remove a portion of the molding compound516to expose the top surface513A of first chip103and the top surface5124A of through vias5124. Referring toFIG.6D, a first heat spreader517and a first thermal interface material (TIM)518are provided, and the first thermal interface material518is dispensed (e.g., by a dispenser (not shown)) on the bottom surface517A of the first heat spreader517. The first heat spreader517may have high thermal conductivity. Furthermore, the first heat spreader517may be flexible. In some embodiments, the first heat spreader517is a graphite sheet having a thermal conductivity between about 1000 W/m-K and 1800 W/m-K. Alternatively, the first heat spreader517may be a graphite sheet with metal reinforcement (i.e., it may comprise a metal material such as copper, aluminum, or another suitable metal) so that the structural strength of first heat spreader517is further improved to prevent it from crushing or cracking easily. It should be appreciated that a graphite sheet used as the first heat spreader517may have a higher thermal conductivity than a typical metal heat spreader, and may be flexible in order to facilitate the subsequent attachment process. In some embodiments, the thickness T1of the first heat spreader517may be in a range between about 15 microns and about 70 microns to have a good flexibility (similar to the heat spreader107described above). The shape and size (in a top view) of the first heat spreader517may correspond to those of the first package substrate512. The first thermal interface material518may have a higher thermal conductivity than a typical adhesive material, however, the thermal conductivity of the first thermal interface material518may still be much lower than that of the first heat spreader517. In some embodiments, the first thermal interface material518has a thermal conductivity between about 3 W/m-K and 8 W/m-K, although its thermal conductivity may also be slightly higher or lower. The first thermal interface material518may comprise an organic material, and it may also act as an adhesive. In some embodiments, the first thermal interface material518comprises a polymer matrix, a phase change polymer, a silicone-based matrix, a matrix additive (fluxing agent), a filler material (a metallic core with an organic solderability preservative coating), or the like. The first thermal interface material518may be dispensed in a liquid form that has a high viscosity. After the first thermal interface material518is applied to the bottom surface517A of the first heat spreader517, the first heat spreader517is attached to the first chip513and the molding compound516by the first thermal interface material518. In the embodiments illustrated inFIG.6D, after the first heat spreader517with the first thermal interface material518is placed over the first chip513and molding compound516, an attachment process is performed. The attachment process includes rolling a rod R over the top surface517B of the first heat spreader517(e.g., from one side (such as the left side in the figure) of the first heat spreader517to the opposite side (such as the right side in the figure) thereof) to attach the first heat spreader517to the first chip513and molding compound516through the first thermal interface material518. By doing it this way, the flexible first heat spreader517can be easily and smoothly attached to the top surface513A of the first chip513and the top surface516A of the molding compound516. Referring toFIG.6E, a compression process is performed (as indicated by the arrows inFIG.6E), in which the first thermal interface material518below the first heat spreader517is subjected to a compression force (e.g., by pressing a compression part or body (not shown) with appropriate weight against the top surface517B of the first heat spreader517) for a period of time. Afterwards, a curing process is performed to fully cure the first thermal interface material518. In the curing process, the first thermal interface material518is subjected to a hot plate or oven, for example at a temperature of above 100° C. for a period of time in some embodiments. Once the compression and curing process is completed, the first heat spreader517and the underlying first thermal interface material518may uniformly cover the entire top surface513A of the first chip513and the entire top surface516A of the molding compound516. Moreover, the first heat spreader517over the first chip513and molding compound516(as well as the through vias5124) has a uniform thickness T1. Referring toFIG.6F, a number of openings O are formed in the first heat spreader517and first thermal interface material518to expose the through vias5124. In some embodiments, the openings O are formed by mechanical drilling, such as laser drilling. However, the openings O may also be formed by another suitable process. Referring toFIG.6G, another carrier511′, similar to the carrier511(seeFIG.6F), is bonded to the top of the resulting structure ofFIG.6F(i.e., the heat spreader517), and then the first carrier511is detached from the first package substrate512. In some embodiments, a sacrificial layer (not shown) is formed between the first carrier511and the first package substrate512. When the sacrificial layer is removed by any suitable etching or cutting process, the first carrier511can be detached from the first package substrate512. Afterwards, a number of electrical connectors519, such as BGA, may be formed on the first surface512A of the first package substrate512(i.e., they are electrically connected to the conductive features5122), in some embodiments as shown inFIG.6G. The electrical connectors519may be configured to electrically connect the fabricated semiconductor package500(FIG.5) to an external device (e.g., a PCB (not shown)). In some embodiments, the electrical connectors519comprise lead-free solder or the like. Referring toFIG.6H, the resulting structure ofFIG.6Gis placed so that the electrical connectors519side is affixed to a dicing tape D1or a die frame (not shown), and then the carrier511′ (FIG.6G) is detached from the first heat spreader517by, for example the detaching process for the first carrier511described above. Afterwards, a singulation process (also referred to as a saw process) is performed. In the singulation process, the first heat spreader517, first thermal interface material518, molding compound516, and first package substrate512are die cut or diced along cutting lines C (depicted by dashed lines) to separate the package of the first chip513, first heat spreader517, and first thermal interface material518into individual units. Each individual unit (i.e., a first package unit510) includes the first heat spreader517attached to the first chip513by the first thermal interface material518. The following describes the fabrication process of a second package unit520. Referring toFIG.6I, a second carrier521is provided. A second package substrate522is formed on the second carrier521. The second package substrate522may include one or more dielectric layers. Conductive redistribution lines5221(e.g., metal lines) may be formed in or between the dielectric layers to electrically couple a number of conductive features5222and5223(e.g., conductive pads) on opposite surfaces of the second package substrate522. As shown inFIG.6I, the second package substrate522has a first surface522A (e.g., the bottom surface) attached to the second carrier521and a second surface522B (e.g., the top surface) opposite to the first surface522A. The conductive features5223exposed to the second surface522B are configured to be electrically connected to second chips523(seeFIG.6J), and the conductive features5222exposed to the first surface522A are configured to be electrically connected to the first package unit (seeFIG.5). In some embodiments, the second package substrate522also includes active and/or passive components (not shown). The materials, fabrication processes, and functions of the second carrier521and second package substrate522may be similar to those of the first carrier511and first package substrate512described above, and are not repeated here. ReferringFIG.6J, a number of second chips523are mounted on the second package substrate522(only one second chip523is depicted for simplicity). The second chips523may be mounted on the second surface522B (the top surface) of the second package substrate522(i.e., they are electrically connected to the conductive features5223) by electrical connectors524, such as a ball grid array (BGA). In some embodiments, the electrical connectors524comprise lead-free solder or the like. A reflow process (not shown) may be performed to make the metallurgical connections in a chip-solder-chip carrier (i.e., the second chip523-the electrical connectors524-the second package substrate522). The second chips523may be any suitable integrated circuit (IC) chip or die for a particular application. For example, the second chips523may be memory chips, logic chips, processor chips, or the like. In various embodiments, the second chips523and the first chips513of the first package unit510are the same or different types of chips. Referring toFIG.6K, an underfill material525is dispensed (e.g., by a dispenser (not shown)) into the space between each second chip523and the second package substrate522and the space between adjacent electrical connectors524, and then cured (e.g., ultraviolet (UV) or thermally cured) to harden. Afterwards, a molding compound526is formed over the second package substrate522and encapsulates the side periphery of each second chip523, as shown inFIG.6K. In some embodiments, the molding compound526is formed in such a way that its top surface526A is substantially level (coplanar) with the top surface523A of second chip523(i.e., the top surface523A of second chip523is exposed as shown inFIG.6K). The materials, fabrication processes, and functions of the underfill material525and molding compound526may be similar to those of the underfill material515and molding compound516described above, and are not repeated here. Referring toFIG.6L, a second heat spreader527and a second thermal interface material (TIM)528are provided, and the second thermal interface material528is dispensed (e.g., by a dispenser (not shown)) on the bottom surface527A of the second heat spreader527. The second heat spreader527may have high thermal conductivity. Furthermore, the second heat spreader527may be flexible. The materials and features of the second heat spreader527may be similar to those of the first heat spreader517described above, and are not repeated here. It should be understood that the thermal conductivity of the second heat spreader527may be different from the thermal conductivity of the first heat spreader517in some embodiments. For example, when the second chip523is a different type of chip than the first chip513and may generate different amounts of heat (e.g., higher than) with respect to the first chip513, the used second heat spreader527may be chosen to have a higher thermal conductivity (than the first heat spreader517) to facilitate heat dissipation, and vice versa. In some embodiments, the second heat spreader527and the first heat spreader517comprise different materials. For example, one of them may be a graphite sheet, and the other may be a graphite sheet with metal reinforcement. The second thermal interface material528may be dispensed in a liquid form that has a high viscosity. The second thermal interface material528may have a higher thermal conductivity than a typical adhesive material, however, the thermal conductivity of the second thermal interface material528may still be much lower than that of the second heat spreader527. The materials and features of the second thermal interface material528may be similar to those of the first thermal interface material518described above, and are not repeated here. After the second thermal interface material528is applied to the bottom surface527A of the second heat spreader527, the second heat spreader527is attached to the second chip523and the molding compound526by the second thermal interface material528. In the embodiments illustrated inFIG.6L, after the second heat spreader527with the second thermal interface material528is placed over the second chip523and molding compound526, an attachment process is performed. The attachment process includes rolling a rod R over the top surface527B of the second heat spreader527(e.g., from one side (such as the left side in the figure) of the second heat spreader527to the opposite side (such as the right side in the figure) thereof) to attach the second heat spreader527to the second chip523and molding compound526through the second thermal interface material528. By doing it this way, the flexible second heat spreader527(e.g., a graphite sheet) can be easily and smoothly attached to the top surface523A of the second chip523and the top surface526A of the molding compound526. Referring toFIG.6M, a compression process and a curing process similar to those described above (seeFIG.6E) for the first heat spreader517and first thermal interface material518are performed. Once the compression and curing process is completed, the second heat spreader527and the underlying second thermal interface material528may uniformly cover the entire top surface523A of the second chip523and the entire top surface526A of the molding compound526. Moreover, the entire second heat spreader527(over the second chip523and molding compound526) has a uniform thickness T2. Referring toFIG.6N, another carrier521′, similar to the second carrier521(seeFIG.6M), is bonded to the top of the resulting structure ofFIG.6M(i.e., the second heat spreader527), and then the second carrier521is detached from the second package substrate522. In some embodiments, a sacrificial layer (not shown) is formed between the second carrier521and the second package substrate522. When the sacrificial layer is removed by any suitable etching or cutting process, the second carrier521can be detached from the second package substrate522. Afterwards, a number of electrical connectors529, such as BGA, may be formed on the first surface522A of the second package substrate522(i.e., they are electrically connected to the conductive features5222), in some embodiments as shown inFIG.6N. In some embodiments, the electrical connectors529comprise lead-free solder or the like. Referring toFIG.6O, the resulting structure ofFIG.6Nis placed so that the electrical connectors529side is affixed to a dicing tape D2or a die frame (not shown), and then the carrier521′ (FIG.6N) is detached from the second heat spreader527by, for example the detaching process for the second carrier521described above. Afterwards, a singulation process (also referred to as a saw process) is performed. In the singulation process, the second heat spreader527, second thermal interface material528, molding compound526, and second package substrate522are die cut or diced along cutting lines C (depicted by dashed lines) to separate the package of the second chip523, second heat spreader527, and second thermal interface material528into individual units. Each individual unit (i.e., a second package unit520) includes the second heat spreader527attached to the second chip523by the second thermal interface material528. Referring toFIG.6P, the fabricated second package unit520is removed from the dicing tap D2(FIG.6O) by a suction unit U (e.g., a vacuum suction unit), and then placed so that the electrical connectors529on the second package substrate522are aligned with, and electrically connected to, the through vias5124of the first package unit510(the electrical connectors529may pass through the openings O (FIG.6H) of the first heat spreader517and the first thermal interface material518to connect to the through vias5124) while the first package unit510is affixed to the dicing tape D1. A reflow process (not shown) may be performed to make the metallurgical connections in a chip package-solder-chip package (i.e., the second package unit520-the electrical connectors529-the first package unit510). After removing the dicing tape D1, the fabrication of the semiconductor package500(FIG.5) including multiple stacking package units is completed. As shown inFIG.5, with the first heat spreader517attached on top of the first chip513, it provides a thermal path (as indicated by the arrows in the figure) through which heat that is generated by the first chip513is dissipated to the surrounding environment to prevent chip overheating. Similarly, the second heat spreader527attached on top of the second chip523also provides a thermal path (as indicated by the arrows in the figure) through which heat that is generated by the second chip523is dissipated to the surrounding environment to prevent chip overheating. It should be appreciated that the heat spreader (517or527) utilizing a graphite sheet may provide a high degree of heat dissipation, especially in the horizontal direction, thereby avoiding overheating of the chip (i.e., the heat generated by the chip can be dissipated or removed rapidly). Moreover, the semiconductor package500can also have a small thickness T due to the thin heat spreaders517and527. The embodiments of the present disclosure have some advantageous features: The heat spreader attached on top of the chip can facilitate heat dissipation, thereby preventing chip overheating. In some embodiments, the heat spreader utilizing a graphite sheet may provide a high degree of heat dissipation, especially in the horizontal direction. Compared with heat dissipation in the vertical direction (e.g., through a heat sink placed on the backside of the semiconductor package), heat dissipation in the horizontal direction may accelerate the elimination or dissipation of overheating energy in the chip so that the hot spot issue can be resolved. Furthermore, the heat spreader utilizing a graphite sheet may have a relatively smaller thickness (than typical metal heat spreader), thereby reducing the thickness of the semiconductor package. Moreover, the heat spreader can protect the chip from being easily damaged due to direct contact with a heavy heat sink or another rigid object. Accordingly, the thermal and mechanical performance of the semiconductor package using the heat spreader are also improved. In addition, an attachment process using a rod to roll over the top surface of the flexible heat spreader is also provided to allow the heat spreader to be easily and smoothly attached on top of the chip. In some embodiments, a method of forming a semiconductor package is provided. The method includes mounting a chip on a package substrate. The method further includes placing a heat spreader over the chip and applying a thermal interface material to a first surface of the heat spreader facing the chip. The heat spreader is flexible. In addition, the method includes attaching the heat spreader to the chip through the thermal interface material by rolling a rod over a second surface of the heat spreader, the second surface being opposite to the first surface. In some embodiments, a method of forming a semiconductor package is provided. The method includes forming a conductive structure over a first package substrate, bonding a first chip on the first package substrate, forming a molding compound surrounding the conductive structure and the first chip, forming a first heat spreader and a first thermal interface material over the conductive structure, the first chip, and the molding compound, wherein the heat spreader is flexible, and forming an opening on the first heat spreader and the first thermal interface material to expose the conductive structure. In some embodiments, a method of forming a semiconductor package is provided. The method includes providing a package substrate on a first carrier, bonding a first chip on the package substrate, forming a molding compound surrounding the first chip, forming a heat spreader and a thermal interface material over the first chip and the molding compound, bonding the heat spreader on a second carrier, and forming an electrical connector on the package substrate. The heat spreader is flexible. The electrical connector and the first chip are disposed on opposite sides of the package substrate. Although embodiments of the present disclosure and their advantages have been described in detail, it should be understood that various changes, substitutions and alterations can be made herein without departing from the spirit and scope of the disclosure as defined by the appended claims. For example, it will be readily understood by those skilled in the art that many of the features, functions, processes, and materials described herein may be varied while remaining within the scope of the present disclosure. Moreover, the scope of the present application is not intended to be limited to the particular embodiments of the process, machine, manufacture, composition of matter, means, methods and steps described in the specification. As one of ordinary skill in the art will readily appreciate from the disclosure of the present disclosure, processes, machines, manufacture, compositions of matter, means, methods, or steps, presently existing or later to be developed, that perform substantially the same function or achieve substantially the same result as the corresponding embodiments described herein may be utilized according to the present disclosure. Accordingly, the appended claims are intended to include within their scope such processes, machines, manufacture, compositions of matter, means, methods, or steps. In addition, each claim constitutes a separate embodiment, and the combination of various claims and embodiments are within the scope of the disclosure. | 51,535 |
11862529 | DESCRIPTION OF REFERENCE SIGNS 10: die;10a: Cu pillar;11: active surface;11a: pad;12: passive surface;12a: opening;20: thermal conductive sheet;21: conductive pillar;20a: through hole;30: first bonding layer;31: insulated connection layer;31a: first connection sublayer;31b: second connection sublayer;32: electrical interconnection structure;40: second bonding layer;41: insulated connection layer;42: electrical interconnection structure;50: circuit board;51: substrate;51a: solderball;51b: solderball;52: interposer;52a: solderball;60: radiating fin; and70: third bonding layer. DESCRIPTION OF EMBODIMENTS An embodiment of this application provides a chip. In some examples, the chip is a processor chip, a memory chip, or the like. FIG.1is a schematic structural diagram of a chip according to an embodiment of this application. As shown inFIG.1, the chip includes a die10and a thermal conductive sheet20. The die10has an active surface11and a passive surface12. The active surface11is a surface on which an integrated circuit pattern is located, and the passive surface12is a surface opposite to the active surface11. The active surface11of the die10is connected to the thermal conductive sheet20by using a first bonding layer30. In an embodiment of the application, the die10is a product form after a semiconductor component is manufactured and before the semiconductor component is packaged, such as a silicon die. The active surface is connected to the thermal conductive sheet by using the first bonding layer. In a bonding connection manner, because thermal contact resistance between the die and the thermal conductive sheet is very small, and is less than 0.5 Kmm2/W, heat at a location with a relatively high temperature on the active surface can be quickly conducted to a location with a relatively low temperature by using the connected thermal conductive sheet, so that temperatures on the active surface can be evenly distributed, and performance of the chip can be prevented from being affected by an excessively high local temperature. A material thermal conductivity of the thermal conductive sheet is negatively correlated with thermal resistance of the thermal conductive sheet. That is, a larger material thermal conductivity of the thermal conductive sheet indicates smaller thermal resistance of the thermal conductive sheet and a better thermal conduction effect. Therefore, a larger material thermal conductivity of the thermal conductive sheet is preferred. Therefore, in an embodiment of the application, the thermal conductive sheet is made from a material with a high thermal conductivity. Herein, the material with a high thermal conductivity is a material whose thermal conductivity is greater than a specified value, for example, a material whose thermal conductivity is greater than or equal to 1000 W/m·K or a material whose thermal conductivity is greater than or equal to 1200 W/m·K. In some examples, the thermal conductive sheet20is made from an inorganic material with a high thermal conductivity. For example, the thermal conductive sheet20is made from one or more of a single crystal diamond film, a polycrystalline diamond film, a boron nitride film, and a boron arsenide film. The thermal conductive sheet20made from these materials not only has a high thermal conductivity, but also has strong chemical bond energy and stable chemical performance, and is not prone to causing corrosion and being corroded. Moreover, compared with a thermal conductive sheet made from a metal material, a thermal expansion coefficient of the thermal conductive sheet made from a nonmetallic material better matches that of a die made from a semiconductor material, and an insulating property of the thermal conductive sheet made from the nonmetallic material is excellent. No interference is caused by the material of the thermal conductive sheet to electrical signals. Performance is not affected in environments such as high temperature and high radiation environments. In the embodiment shown inFIG.1, the thermal conductive sheet20is a monolithic structure, and the first bonding layer30is formed by using an insulating material. In an embodiment, the die10needs to be electrically connected to another electronic component in a fanout manner, to implement electrical signal transmission. In some examples, pads are disposed on the active surface11of the die10. For example, the pads are located on an edge of the active surface, the integrated circuit pattern is located at a central part of the active surface, and the pads are electrically connected to the integrated circuit pattern. The first bonding layer30avoids the pads, and is connected between only the central part of the active surface of the die and the thermal conductive sheet. The pads are connected to the another electronic component by using a metal lead. The another electronic component includes but is not limited to another die and a substrate. This manner of connection to another electronic component by using an external metal lead is the fanout manner. FIG.2is a schematic structural diagram of a chip according to an embodiment of this application. As shown inFIG.2, the chip includes a die10and a thermal conductive sheet20. The die10has an active surface11and a passive surface12. The active surface11is a surface on which an integrated circuit pattern is located, and the passive surface12is a surface opposite to the active surface. The active surface11of the die10is connected to the thermal conductive sheet20by using a first bonding layer30. FIG.3is a schematic structural diagram of an active surface of a die according to an embodiment of this application. As shown inFIG.3, there are a plurality of pads11aon the active surface11. The pad11ais configured to electrically connect to another electronic component, to perform electrical signal transmission. It should be noted that, locations of the pads inFIG.3are merely examples, and are not used as a limitation on this application. For example, the pads11anot only are located on an edge of the active surface11, but also are located at a central part of the active surface11. In an embodiment of the application, the pads are usually made from a metal material. In some examples, the pads11aare made from a bonding metal material, for example, Cu, Ag, Au, or Al, or are made from a solder with a low melting point, for example, AgSn, AgCuSn, or CuSn. In an embodiment, the pads have a single-layer structure or a multi-layer structure. In some examples, the pads11aprotrude at least partially from the active surface11, to facilitate subsequent connection to conductive pillars21in the thermal conductive sheet20. Refer toFIG.2again. A plurality of through holes20aare provided in the thermal conductive sheet20, and one conductive pillar21is disposed in each through hole20a. The conductive pillars21run through the thermal conductive sheet20and protrude from a surface of the thermal conductive sheet20. For example, the conductive pillars21are made from a metal material, for example, Cu, Ag, or Au. In some examples, due to material characteristics, some materials of the conductive pillars easily diffuse into the thermal conductive sheet, affecting device performance. Therefore, a barrier layer needs to be disposed between the conductive pillars and the thermal conductive sheet. For example, when the conductive pillars are Cu pillars, Cu has a relatively high diffusion coefficient. To prevent Cu from diffusing into the thermal conductive sheet, a barrier layer needs to be disposed between the conductive pillars and the thermal conductive sheet. In an embodiment, the barrier layer uses one or more of the following materials: Ti, Cr, Ni, W, and Ta. In some examples, a connection strength between the conductive pillars and the thermal conductive sheet is relatively poor due to differences in materials and a method for manufacturing the conductive pillars. For example, when the thermal conductive sheet is a single crystal diamond film or a polycrystalline diamond film, the conductive pillars are copper pillars, and the conductive pillars are formed through electroplating, the connection strength between the conductive pillars and the thermal conductive sheet is relatively poor. In this case, the chip further includes: a seed layer located between the conductive pillars and the thermal conductive sheet, to enhance the connection strength between the conductive pillars and the thermal conductive sheet. In an embodiment, the seed layer and the barrier layer are a same layer, for example, a Ti layer, or the seed layer and the barrier layer are different layers, for example, the seed layer is a Ti layer, and the barrier layer is a Ni layer. In some examples, the conductive pillars are formed in the thermal conductive sheet through sintering. In this case, there is no need to dispose a seed layer between the conductive pillars and the thermal conductive sheet. In some examples, the barrier layer may be first formed on inner walls of the through holes of the thermal conductive sheet20in a manner such as sputtering, and then the conductive pillars are formed through electroplating. FIG.4is a schematic structural top view of a thermal conductive sheet according to an embodiment of this application. As shown inFIG.4, the plurality of conductive pillars21are disposed in the thermal conductive sheet20. In some examples, a diameter of the conductive pillars21is 3 μm to 50 μm. A diameter size of the conductive pillars matches a pad size of most chips. In practical application, adjustment may be made based on an actual situation. In an embodiment of the application, locations of the conductive pillars21in the thermal conductive sheet20are determined based on locations of the pads11a on the active surface11of the die10. The plurality of conductive pillars21correspond to the plurality of pads11a one to one, and are electrically connected to the corresponding pads11a. When the die10is connected to the thermal conductive sheet20, the pads11a on the die10first need to be aligned with the conductive pillars21in the thermal conductive sheet20, and alignment precision needs to fall within a required value, for example, within ±2 μm. In some examples, the alignment precision is represented by a distance between a center of the pad and a center of the conductive pillar. In some examples, because the active surface is connected to the thermal conductive sheet by using a first bonding layer, to electrically connect the pads on the active surface to the corresponding conductive pillars, the first bonding layer needs to be a hybrid bonding layer. The hybrid bonding layer needs to complete bonding of an insulating material and also needs to complete bonding of a conductive material. As shown inFIG.2, the first bonding layer30includes an insulated connection layer31and electrical interconnection structures32located in the insulated connection layer31. The pads11aof the active surface11are connected to the conductive pillars21in the thermal conductive sheet20through bonding by using the electrical interconnection structures32, and a region of the active surface11other than the pads11ais connected to the thermal conductive sheet20through bonding by using the insulated connection layer31. The insulated connection layer31is filled between the plurality of electrical interconnection structures32. In some examples, the insulated connection layer31is made from a compound material or a polymeric material. The compound material includes but is not limited to SiO2, AlN, and SiC. The polymeric material includes but is not limited to BCB, SU-8, and PI. In some examples, the electrical interconnection structures32are made from one or more of the following materials: Cu, Ni, W, CuSn, and AuSn. For example, the electrical interconnection structures32is of a single-layer structure, for example, a Cu layer, a CuSn layer, or an AuSn layer; or one of the electrical interconnection structures32is of a multi-layer structure, for example, one of the electrical interconnection structures32includes a Cu layer and a CuSn layer. FIG.5is a schematic diagram of a state of connection between a conductive pillar and a pad according to an embodiment of this application. A dashed line inFIG.5represents a bonding interface between the pad11aand the conductive pillar21. The electrical interconnection structure32is a part within a particular thickness range with the bonding interface as a center in an extension direction of the conductive pillar21, for example, a part shown by a dotted line box inFIG.5. Within this thickness range, the pad11aand the conductive pillar21are combined with each other. For example, atoms of the pad11aand the conductive pillar21infiltrate into each other and are combined with each other. In some examples, the pads11aand the conductive pillars21are made from a same material, for example, Cu, and then the electrical interconnection structures32each are a part in which Cu atoms infiltrate into each other. In some other examples, parts opposite to each other of the pads11aand the conductive pillars21respectively are made from different materials. For example, surfaces of the pads each are a Sn layer, the conductive pillars21are made from Cu, and the electrical interconnection structures32each are a part in which Sn atoms of the pads are combined with Cu atoms of the conductive pillars to form a CuSn alloy. In another example, the surfaces of the pads each are a CuSn layer, the conductive pillars21are made from Cu, and the electrical interconnection structures32each are a part in which the CuSn layer is combined with Cu. Alternatively, in another embodiment, the first bonding layer30includes only an insulated connection layer31. The conductive pillars21are deposited on the pads11aso as to connect to the pads11a. For example, the conductive pillars21are deposited on the pads11athrough electroplating. To further increase a temperature conduction speed of the active surface and improve heat dissipation performance of the chip, a proper material needs to be selected to make thermal resistance of the first bonding layer30relatively small, for example, less than a specified value. For example, the specified value is 1 Kmm2/W. For example, a thickness of the first bonding layer30is less than 10 μm. Thermal resistance is positively correlated with a thickness of a material. That is, a thicker material indicates larger thermal resistance. Therefore, the thickness of the first bonding layer30is set to be relatively small, to avoid excessively large thermal resistance of the first bonding layer, thereby preventing heat dissipation performance of the chip from being affected. A three-dimensional (3D) stacking technology is an important development trend in the field of chips. A three-dimensional stacked chip means that at least two interconnected dies are stacked and then packaged. In some examples, a plurality of dies stacked together are electrically connected by using a vertical interconnection structure. The vertical interconnection structure uses a through silicon via (TSV) based Cu interconnection technology. In the interconnection technology, through holes are provided in a die. The through holes extend from an active surface of the die to a passive surface, Cu pillars are disposed in the through holes, and the die is electrically connected to another die located on the passive surface of the die by using the Cu pillars. In an embodiment, the vertical interconnection structure can increase a chip integration level; and in an embodiment, the vertical interconnection structure can shorten a delay of inter-chip interconnection based on an advantage of short-range interconnection. For the three-dimensional stacked chip, a heat generation problem inside the chip is more serious. Therefore, in an embodiment of the application, thermal conductive sheets may be disposed on active surfaces of at least some dies in the three-dimensional stacked chip. For example, the thermal conductive sheet is disposed on the active surface of at least one die below (namely, a location close to a substrate), or the thermal conductive sheet is disposed on the active surface of at least one die in the middle or above (namely, a location away from the substrate), or the thermal conductive sheet is disposed on the active surface of each die except a lowest die, or the thermal conductive sheet is disposed on the active surface of each die. FIG.6is a schematic structural diagram of a chip according to an embodiment of this application. As shown inFIG.6, the chip includes a plurality of dies10and a plurality of thermal conductive sheets20. The dies10and the thermal conductive sheets20are stacked alternately. A quantity of the dies10is equal to that of the thermal conductive sheets20. An active surface11of each die10is connected to one thermal conductive sheet20by using a first bonding layer30. For example, the die10uses the foregoing TSV based Cu interconnection technology. FIG.7is a schematic structural diagram of a passive surface of a die according to an embodiment of this application. As shown inFIG.7, there are a plurality of openings12ain the passive surface12of the die10. Each opening12acorresponds to one through hole. Refer toFIG.3for a structure of the active surface of the die10inFIG.5. With reference toFIG.3andFIG.6, the openings12aof the passive surface12correspond to pads11aon the active surface11one to one. FIG.8is a schematic structural diagram of a cross section along a line A-A inFIG.7. As shown inFIG.8, a plurality of through holes are provided in the die10. Each of the through holes extends from the active surface11of the die10to the passive surface12. A Cu pillar10ais disposed in the through hole. One end of the Cu pillar10ais connected to a pad11aof the active surface11. The other end of the Cu pillar10ais exposed from an opening12aon the passive surface12through the through hole. Each thermal conductive sheet20is connected to the passive surface12of the adjacent die10by using a second bonding layer40. In this way, two adjacent dies and the second bonding layer between the two dies form an entirety, to reduce thermal resistance on a heat conduction path in a vertical direction (namely, a stacking direction), thereby improving heat dissipation performance of the chip. In some examples, the second bonding layer40also needs to implement bonding of an insulating material and bonding of a conductive material at the same time. Therefore, a structure of the second bonding layer40is the same as that of the first bonding layer30. Refer toFIG.6again. The second bonding layer40includes an insulated connection layer41and electrical interconnection structures42located in the insulated connection layer41. A conductive pillar21in the thermal conductive sheet20is connected to one end of the Cu pillar in the die10through bonding by using the electrical interconnection structure42. The thermal conductive sheet20is connected, through bonding, to a region other than Cu pillars on the passive surface12of the die10adjacent to the thermal conductive sheet20by using the insulated connection layer41. Electrical signal interconnection between the two adjacent dies10may be implemented by using the electrical interconnection structures32of the first bonding layer30, the conductive pillars21, and the electrical interconnection structures42of the second bonding layer40. Moreover, the thermal conductive sheet20between the two adjacent dies10can quickly spread and dissipate heat in a stacking region, thereby reducing a junction temperature. In an embodiment, referring toFIG.6again, the chip further includes a circuit board50, the dies10and the thermal conductive sheets20are located on the circuit board50, and in an arrangement direction of the dies10and the thermal conductive sheets20, the thermal conductive sheet20is adjacent to the circuit board50. The conductive pillars21in the outermost thermal conductive sheet20are connected to the circuit board50. Namely, the conductive pillars21in the lowest thermal conductive sheet20in the figure are connected to the circuit board50. The circuit board50includes a substrate51. The conductive pillars21in the thermal conductive sheet20are connected to pads on a surface of the substrate51, for example, by using solderballs51a. The substrate51is a chip package substrate, including but not limited to a printed circuit board or a ceramic substrate. For example, the other surface of the substrate51is connected to an external circuit by using solderballs51b. For a three-dimensional stacked chip, usually, a large amount of heat accumulates on the lowest die. When a thermal conductive sheet20is disposed between the substrate50and the lowest die10, quick temperature equalization of the lowest chip can be implemented. In an embodiment, as shown inFIG.6, the chip further includes a radiating fin60. The radiating fin60is connected to the passive surface12of the outermost die10, namely, the passive surface12of the uppermost die10, by using a third bonding layer70. In some examples, the third bonding layer70is made from a metal material. In an embodiment, the third bonding layer70has a single-layer structure, for example, is made from at least one of the following materials: Au, AuSn, Cu, CuSn, Ag, and AgSn. Alternatively, the third bonding layer70has a multi-layer structure. For example, the third bonding layer includes an interlayer and a bonding layer. The interlayer and the bonding layer are sequentially located on the passive surface of the die. For example, the interlayer is made from one or more of the following materials: Ti, Cr, W, and Ni. The bonding layer is made from one or more of the following: Au, AuSn, Cu, CuSn, Ag, and AgSn. In some other examples, the third bonding layer70is made from a nonmetallic material, and the nonmetallic material includes one or more of the following: SiO2, SiC, AlN, and Si. To further increase a temperature conduction speed of the active surface and improve heat dissipation performance of the chip, a proper material needs to be selected to make thermal resistance of the third bonding layer relatively small, for example, less than a specified value. For example, the specified value is 1 Kmm2/W. In some examples, a thickness of the third bonding layer70is 0.5 μm to 10 μm. The radiating fin60may be made from a material with a high thermal conductivity. Herein, the material with a high thermal conductivity is a material whose thermal conductivity is greater than a specified value, for example, a material whose thermal conductivity is greater than or equal to 1000 W/m·K or a material whose thermal conductivity is greater than or equal to 1200 W/m·K. In some examples, the radiating fin60is made from an inorganic material with a high thermal conductivity, for example, one or more of a single crystal diamond film, a polycrystalline diamond film, a boron nitride film, and a boron arsenide film. In some examples, to meet a heat dissipation requirement, a thickness of the radiating fin60is greater than or equal to 300 μm, for example, 300 μm to 2000 μm. In some examples, the radiating fin60is manufactured in any one of the following manners: high temperature high pressure (HTHP), microwave plasma assisted chemical vapor deposition (MWCVD), direct current arc plasma jet chemical vapor deposition (DC arc CVD), and physical vapor deposition (PVD). In some examples, manners of bonding between the radiating fin60and the passive surface12of the die10include but are not limited to eutectic bonding, atomic diffusion bonding (ADB), thermal compression bonding, and surface activated bonding (SAB). It should be noted that, in another embodiment, the radiating fin60may be replaced with a heat spreader in another form, for example, a heat sink or a vapor chamber. For example, the heat sink is made from a material such as Cu or Al. In an embodiment, a thickness of the die is 15 μm to 500 μm. Currently, thicknesses of most dies are 775 μm. Because a thermal conductivity of a material (for example, Si) of the die is relatively small, the thickness of the die is reduced to 15 μm to 500 μm, to reduce thermal resistance in a vertical direction of the three-dimensional stacked chip, thereby facilitating heat conduction in the vertical direction of the three-dimensional stacked chip. In some examples, a thickness of the thermal conductive sheet20is 50 μm to 500 μm. When the thickness of the die is reduced, a value of the thickness of the thermal conductive sheet is selected within this range. This is equivalent to replacing a material of a die with a low thermal conductivity with a thermal conductive sheet with a high thermal conductivity, to reduce thermal resistance in the vertical direction of the three-dimensional chip on a premise that the thickness of the chip remains basically unchanged. In the three-dimensional stacked chip inFIG.6, when polycrystalline diamond films with a thermal conductivity of 1200 W/m·K are used as the thermal conductive sheet and the radiating fin, a heat dissipation benefit of the chip is increased by 11% compared with a three-dimensional stacked chip in which no thermal conductive sheet or radiating fin is used. An on-chip temperature difference and a highest junction temperature of the chip can both have a heat dissipation benefit of greater than or equal to 10° C., thereby effectively reducing heat dissipation load of a system. To ensure a heat dissipation effect, a size of the thermal conductive sheet20is greater than or equal to that of the die10. In this way, after the thermal conductive sheet is connected to the active surface of the die, a projection of the die10on a surface of the connected thermal conductive sheet20overlaps the surface. That is, an outer edge of the die10is aligned with that of the thermal conductive sheet20. Alternatively, the projection of the die10on the surface of the connected thermal conductive sheet20is located within the surface. That is, the outer edge of the thermal conductive sheet20exceeds that of the die10. FIG.9is a schematic structural diagram of a chip according to an embodiment of this application. As shown inFIG.9, the chip includes a plurality of dies10and a plurality of thermal conductive sheets20. The dies10and the thermal conductive sheets20are stacked alternately. The structure shown inFIG.9differs from the structure shown inFIG.6in that, in the structure shown inFIG.9, a quantity of the dies10is one less than that of the thermal conductive sheets20. An active surface11of the outermost die10is not connected to the thermal conductive sheet20, but is directly connected to a substrate51by using solderballs51a. In some examples, the three-dimensional stacked chips inFIG.6andFIG.9are memory chips, for example, high-bandwidth memory (HBM) chips. It should be noted that, in the foregoing three-dimensional stacked chips, the plurality of thermal conductive sheets20are made from a same material. For example, the plurality of thermal conductive sheets20are all made from polycrystalline diamond films. Alternatively, the plurality of thermal conductive sheets20are made from different materials, for example, some thermal conductive sheets20are made from polycrystalline diamond films and some thermal conductive sheets20are made from boron nitride films. FIG.10is a schematic structural diagram of a chip according to an embodiment of this application. As shown inFIG.10, a structure of the chip differs from the structure of the chip shown inFIG.9in that, the chip shown inFIG.10includes only one die10and one thermal conductive sheet20. An active surface11of the die10is connected to the thermal conductive sheet20by using a first bonding layer30, and conductive pillars21in the thermal conductive sheet20are connected to a substrate51by using solderballs51a. A passive surface12of the die10is connected to a radiating fin60by using a third bonding layer70. For a chip power consumption density of 150 W/cm2, when polycrystalline diamond films with a thermal conductivity of 1200 W/m·K are used as the thermal conductive sheet and the radiating fin, a heat dissipation benefit of the chip is increased by 7%, and a junction temperature of the chip is decreased by greater than or equal to 7° C. compared with a chip in which no thermal conductive sheet or radiating fin is used, thereby effectively reducing heat dissipation load of a system. FIG.11is a schematic structural diagram of a chip according to an embodiment of this application. As shown inFIG.11, the structure of the chip differs from the structure of chip shown inFIG.6in that, in addition to a substrate51, a circuit board50further includes an interposer52. The substrate51is not directly connected to a die10and a thermal conductive sheet20that are stacked together, but is connected, by using the interposer52, to the die10and the thermal conductive sheet20that are stacked together. For example, as shown inFIG.11, a side surface of the interposer52is connected to conductive pillars21in the thermal conductive sheet20by using solderballs52a, and the other side surface of the interposer52is connected to the substrate51by using solderballs51a. Assuming that a group of dies includes one die or at least two dies that are stacked together, the chip inFIG.11includes two groups of dies. The two groups of dies are located on a same surface of the interposer52, and implement electrical signal interconnection by using the interposer52. In an embodiment, structures of the two groups of dies are different. For example, in the two groups of dies shown inFIG.11, a structure of the group of dies on a left side of the figure is the same as that shown inFIG.6, and the group of dies on a right side of the figure includes only one die10. An active surface of the die10is connected to the interposer52by using the solderballs52a, and a passive surface of the die10is connected to a radiating fin60by using a third bonding layer70. Alternatively, in another embodiment, structures of the two groups of dies are the same. For example, the two groups of dies both use the structure of the group of dies on the left side ofFIG.11. It should be noted that, in some embodiments, a structure of at least one group of dies in the two groups of dies inFIG.11is replaced with the structure inFIG.1,FIG.2,FIG.9, orFIG.10. This is not limited in this application. An embodiment of this application further provides a chip manufacturing method. The manufacturing method includes: providing a die; and forming a first bonding layer between an active surface of the die and the thermal conductive sheet, to connect the active surface of the die to the thermal conductive sheet by using the first bonding layer. In some examples, the thermal conductive sheet is a monolithic structure, and no conductive pillar is formed in the thermal conductive sheet. In this case, the connecting the active surface of the die to the thermal conductive sheet by using the first bonding layer includes: operation 1, forming an insulated first connection sublayer on the active surface of the die; operation 2, forming an insulated second connection sublayer on a side surface of the thermal conductive sheet; and operation 3, connecting the first connection sublayer to the second connection sublayer through bonding, to obtain the structure shown inFIG.1. For example, the first connection sublayer is formed in a manner such as spin-coating, and the second connection sublayer is formed in a manner such as spin-coating. In some examples, conductive pillars are formed in the thermal conductive sheet. In this case, there are the following three manners of connecting the active surface of the die to the thermal conductive sheet by using the first bonding layer. In a first manner, through holes are first formed in the thermal conductive sheet20, and the conductive pillars21are formed in the through holes. Then, the first bonding layer is formed between the active surface of the die and the thermal conductive sheet, to connect the thermal conductive sheet20with the conductive pillars21to the active surface of the die10by using the first bonding layer30. The conductive pillars21are formed in the thermal conductive sheet20in advance, and then the thermal conductive sheet is connected to the die10through bonding. A plurality of operations may be performed synchronously. For example, the die and the thermal conductive sheet are manufactured at the same time, so that efficiency of manufacturing the chip can be increased. In an embodiment, in the first manner, the forming a first bonding layer between an active surface of the die and a thermal conductive sheet includes: Operation 1: Form an insulated first connection sublayer31ain a region of the active surface11of the die10other than pads. As shown inFIG.12, the first connection sublayer31ais formed on the active surface11, and the pads11aon the active surface11are exposed from notches in the first connection sublayer31a. Operation 2: Form an insulated second connection sublayer31bin a region of a side surface of the thermal conductive sheet20other than the conductive pillars21. As shown inFIG.13, the plurality of conductive pillars21protrude from the side surface of the thermal conductive sheet20, and the second connection sublayer31bis located on the thermal conductive sheet20and is located in gaps between the conductive pillars21. Operation 3: Connect the first connection sublayer31ato the second connection sublayer31bthrough bonding, and connect the pads11ato the conductive pillars21through bonding, to form the first bonding layer30, so as to connect the active surface11of the die10to the thermal conductive sheet20by using the first bonding layer30, thereby obtaining the structure shown inFIG.2. In this case, the first connection sublayer31ais connected to the second connection sublayer31bthrough bonding, to form an insulated connection layer31. Electrical interconnection structures32are formed on bonding interfaces between the pads11aand the conductive pillars21. In some examples, to ensure that the pads11acan be connected to the conductive pillars21through bonding when the first connection sublayer31ais connected to the second connection sublayer31bthrough bonding, the pads11aprotrude from the active surface11of the die. In addition, an execution sequence of operation 1 and operation 2 may be exchanged. In an embodiment, operation 2 is performed before operation 1, or operation 1 and operation 2 may be performed at the same time. The first connection sublayer31ais made from a compound material or a polymeric material. The compound material includes but is not limited to SiO2, AlN, and SiC. The polymeric material includes but is not limited to BCB, SU-8, and PI. A material of the second connection sublayer31bis the same as that of the first connection sublayer31a, to ensure that the first connection sublayer31acan be connected to the second connection sublayer31bthrough bonding. In an embodiment, the pads11a are made from a bonding metal material, for example, Cu, Ag, Au, or Al, or are made from a solder with a low melting point, for example, AgSn, AgCuSn, or CuSn. In an embodiment, the conductive pillars21are made from a metal material, for example, Cu, Ag, or Au. The material of the conductive pillars21needs to correspond to that of the pads11a, to ensure that the pads11acan be connected to the conductive pillars21through bonding. It should be noted that, in an embodiment, the pads11aare directly connected to the conductive pillars21through bonding, to form the electrical interconnection structures32. In an embodiment, the method further includes: forming a solder layer on the pads11a, the conductive pillars21, or both, so that the pads11a are connected to the conductive pillars21through bonding by using the solder layer. The electrical interconnection structures each include the solder layer and a structure (the pad or the conductive pillar) opposite to the solder layer. In a second manner, through holes are first formed in the thermal conductive sheet20, and then the first bonding layer is formed between the active surface of the die and the thermal conductive sheet, to connect the thermal conductive sheet20to the active surface of the die10by using the first bonding layer30, and then conductive pillars21are formed in the through holes. In an embodiment, in the second manner, connecting the active surface of the die to the thermal conductive sheet by using the first bonding layer includes: Operation 1: Form an insulated first connection sublayer31aon the active surface11, where the first connection sublayer31acovers the active surface11, as shown inFIG.14. Operation 2: Form an insulated second connection sublayer31bon a side surface of the thermal conductive sheet20, where the second connection sublayer covers a side surface of the thermal conductive sheet, as shown inFIG.15. Operation 3: Connect the first connection sublayer31ato the second connection sublayer31bthrough bonding, to form an insulated connection layer31, as shown inFIG.16. Operation 4: Form, in the thermal conductive sheet20and the insulated connection layer31, through holes20acorresponding to pads11aon the active surface11, where a part in the insulated connection layer31other than the through holes20ais the first bonding layer30, as shown inFIG.17. Operation 5: Form, through deposition on the pads11a, the conductive pillars21located in the through holes20a, where the conductive pillars21run through the thermal conductive sheet20, to obtain the structure shown inFIG.2. It should be noted that, an execution sequence of operation 1 and operation 2 may be exchanged. In an embodiment, operation 2 is performed before operation 1, or operation 1 and operation 2 are performed at the same time. In a third manner, the thermal conductive sheet20is first connected to the active surface of the die10by using the first bonding layer30, then through holes are formed in the thermal conductive sheet20, and then conductive pillars21are formed in the through holes. In an embodiment, in the third manner, connecting the active surface of the die to the thermal conductive sheet by using the first bonding layer includes: Operation 1: Form an insulated first connection sublayer31ain a region of the active surface11other than pads11a, as shown inFIG.18. Operation 2: Form a plurality of through holes20ain the thermal conductive sheet20, where the through holes20acorrespond to the pads11a, as shown inFIG.19. Operation 3: Form an insulated second connection sublayer31bin a region of a side surface of the thermal conductive sheet20other than the through holes20a, as shown inFIG.20. Operation 4: Connect the first connection sublayer31ato the second connection sublayer31bthrough bonding, to form the first bonding layer31, as shown inFIG.17. Operation 5: Form, through deposition on the pads11a, the conductive pillars21located in the through holes20a, where the conductive pillars21run through the thermal conductive sheet20, to obtain the structure shown inFIG.2. It should be noted that, an execution sequence of operation 1, operation 2, and operation 3 is not limited in this application. For example, operation 2 and operation 3 are performed before operation 1, or operation 1 and operation 2 are performed at the same time, and then operation 3 is performed; or operation 2 is performed first, and then operation 1 and operation 3 are performed at the same time. In some examples, in the three manners, the through holes are formed in the thermal conductive sheet20in the following manner: forming a photoresist layer on a side surface of the thermal conductive sheet; exposing and developing the photoresist layer to obtain a patterned photoresist layer, where locations at the patterned photoresist layer that correspond to the through holes are hollowed out; etching the thermal conductive sheet by using the patterned photoresist layer as a mask, to form the through holes in the thermal conductive sheet. In some other examples, the through holes are formed in the thermal conductive sheet20through laser drilling. In an embodiment, in the three manners, the conductive pillars21are formed in the through holes20ain manners such as electroplating and sintering. It should be noted that, in the second and third manners, the conductive pillars21are directly deposited on the pads11a, for example, directly formed on the pads11ain a manner such as electroplating. In other words, the conductive pillars21extend into the first bonding layer30to be connected to the pads11a. In an embodiment, for any one of the foregoing three-dimensional stacked chips, the manufacturing method further includes: connecting a passive surface of the die to another thermal conductive sheet by using a second bonding layer, where a structure of the second bonding layer is the same as that of the first bonding layer, and two dies connected to two sides of the thermal conductive sheet are electrically connected to each other by using the conductive pillars in the thermal conductive sheet. For a process of connecting the passive surface of the die to the adjacent thermal conductive sheet by using the second bonding layer, refer to the process of connecting the active surface of the die to the thermal conductive sheet by using the first bonding layer. Detailed description is omitted herein. In an embodiment, the manufacturing method further includes: connecting, to a radiating fin by using a third bonding layer, the passive surface of the outermost die in the die and the thermal conductive sheet that are connected together. For example, a first bonding sublayer is first formed on the passive surface of the outermost die, then a second bonding sublayer is formed on the radiating fin, and then the first bonding sublayer is connected to the second bonding sublayer through bonding. Materials of the first bonding sublayer and the second bonding sublayer correspond to the material of the foregoing third bonding layer, and detailed description is omitted herein. In an embodiment, the radiating fin is manufactured in any one of the following manners: HTHP, MWCVD, DC arc CVD, and PVD. In some examples, manners of bonding between the radiating fin and the passive surface of the die include but are not limited to: eutectic bonding, ADB, thermal compression bonding, and surface activated bonding SAB. In an embodiment, the manufacturing method further includes: connecting, to a circuit board, the die and the thermal conductive sheet that are connected together. In an embodiment, the circuit board is a substrate, and the connecting, to a circuit board, the die and the thermal conductive sheet that are connected together includes: first placing, on the substrate, the die and the thermal conductive sheet that are connected together, and then connecting, to the substrate by using solderballs, the die and the thermal conductive sheet that are connected together. In an embodiment, the circuit board includes a substrate and an interposer. The interposer is located on the substrate. The connecting, to a circuit board, the die and the thermal conductive sheet that are connected together includes: connecting, to a side surface of the interposer by using solderballs, the die and the thermal conductive sheet that are connected together, and connecting the other side surface of the interposer to the substrate by using solderballs. An embodiment of this application further provides an electronic device, including any one of the foregoing chips. For example, the electronic device is a mobile terminal, including but not limited to a mobile phone, a tablet computer, or a notebook computer. Unless otherwise defined, a technical term or a scientific term used herein should have a general meaning understood by one of ordinary skilled in the art of this disclosure. In the specification and claims of the patent application of this disclosure, the terms “first”, “second”, and the like are not intended to indicate any order, quantity or significance, but are intended to distinguish between different components. Likewise, “a/an”, “one”, or the like is not intended to indicate a quantity limitation either, but is intended to indicate existing at least one. Similar words such as “include” or “comprise” mean that elements or articles preceding “include” or “comprise” cover elements or articles enumerated after “include” or “comprise” and their equivalents, and do not exclude other elements or articles. “Connection”, “link” or the like is not limited to a physical or mechanical connection, but may include an electrical connection, whether directly or indirectly. “Up”, “down”, “left”, “right”, “top”, “bottom”, and the like are only used to indicate a relative location relationship, and when an absolute location of a described object changes, the relative location relationship may also change accordingly. The foregoing descriptions are merely specific embodiments of this application, but are not intended to limit this application. Any modification, equivalent replacement, or improvement made without departing from the spirit and principle of this application should fall within the protection scope of this application. | 45,512 |
11862530 | It may be understood that the appended drawings are not necessarily to scale, presenting a somewhat simplified representation of various features illustrative of the basic principles of the present invention. The specific design features of the present invention as included herein, including, for example, specific dimensions, orientations, locations, and shapes will be determined in part by the particularly intended application and use environment. In the figures, reference numbers refer to the same or equivalent parts of the present invention throughout the several figures of the drawing. DETAILED DESCRIPTION Reference will now be made in detail to various embodiments of the present invention(s), examples of which are illustrated in the accompanying drawings and described below. While the present invention(s) will be described in conjunction with exemplary embodiments of the present invention, it will be understood that the present description is not intended to limit the present invention(s) to those exemplary embodiments. On the contrary, the present invention(s) is/are intended to cover not only the exemplary embodiments of the present invention, but also various alternatives, modifications, equivalents and other embodiments, which may be included within the spirit and scope of the present invention as defined by the appended claims. Embodiments of the present invention will be described in more detail below with reference to the accompanying drawings. However, the present invention is not limited to the embodiments that will be included below, and various different embodiments thereof can be implemented. The embodiments are only provided to make a complete disclosure of the present invention and to provide full notice of the scope of the present invention to a person of ordinary skill in the art to which various exemplary embodiments of the present invention pertains. The scope of the present invention may be only defined by claims. Like constituent elements are provided like reference characters. FIG.3is a cross-sectional view exemplarily illustrating a spacer according to various exemplary embodiments of the present invention. Like a spacer30that is illustrated inFIG.1, the spacer according to various exemplary embodiments of the present invention is provided between an upper substrate11and a semiconductor chip40. In the instant case, a power module including the spacer100includes: a signal lead41through which a signal is transmitted to and received from the semiconductor chip40, a wire42connecting the semiconductor chip40and the signal lead41to each other, and metal plates21to25made of a conductive material. The metal plates21and22are formed between the spacer100and the upper substrate11, and the metal plates23,24, and25are formed between the semiconductor chip40and the lower substrate12. The typical power module illustrated inFIG.1and the power module100according to various exemplary embodiments of the present invention are the same in terms of constituent elements other than the spacer100, the position of the spacer100, and the bonding method. Therefore, a redundant description will not be given. However, the spacer100according to the exemplary embodiment of the present invention is a multilayer structure in which layers of different metal materials are stacked. To be more specific, the spacer100includes first metal layers110which are made of a first metal and serve as the outermost layers, and a second metal layer120made of a second metal having a lower thermal expansion coefficient than the first meta and disposed between the first metal layers110. That is, the spacer100results from sequentially stacking the first metal layer110, the second metal layer120, and the first metal layer110in this order. In the instant case, the first metal of which the first metal layer110is made of and the second metal of which the second metal layer120is made have different thermal expansion coefficients and thermal conductivities. Thus, a thermal expansion coefficient and a thermal conductivity of the entire spacer are adjusted by adjusting respective thicknesses of the first metal layer110and the second metal layer120. Specifically, the thermal expansion coefficient of the first metal is lower than that of the second metal. Moreover, the second metal has lower solder wettability than the first metal. For example, the first metal is made of Cu, and the second metal is made of Mo or CuMo. Cu which is the material of the first metal layer110has a thermal expansion coefficient of 16.5×10−6/K and a thermal conductivity of 386 W/mK. CuMo which is the material of the second metal layer120has a thermal expansion coefficient of 9×10−6/K and a thermal conductivity of 200 W/mK. Thus, the thermal expansion coefficient and the thermal conductivity of the spacer100can be adjusted to 10×10−6/K or below and 195 W/mK or above by adjusting the thicknesses of the first metal layer110and the second metal layer120. The outermost layers of the spacer100are implemented with the first metal layers110made of Cu. Soldering is performed on the first layers110made of Cu, thus it is not necessary to form Cu plating layers33on the surfaces of the spacer30unlike the spacer in the related art. According to the exemplary embodiment of the present invention, since the surfaces of the spacer100are plated with a copper layer, the second metal layer120is exposed on lateral faces of the spacer100. In the instant case, since Mo or CuMo of which the second metal layer120is made has a lower solder wettability than Cu of which the first metal layer110is made, when performing soldering to connect the spacer100with the metal plate22and the semiconductor chip40, it is possible to prevent a solder portion S connecting the spacer100and the metal plate22from being connected to a solder portion S connecting the spacer100and the semiconductor chip40on a lateral surface of the spacer100. The second metal layer120has a sufficient thickness to prevent the solder portion S connected to the first metal layer110provided as the uppermost metal layer from being connected to the solder portion S connected to the first metal layer110provided as the lowermost metal layer, via the lateral surface of the second metal layer120. For example, the thickness of the second metal layer120accounts for about 33% to 50% of the total thickness of the spacer. In a case where the second metal layer120has a thickness smaller than a predetermined range suggested above, there is a risk that the solder portion S connected to the first metal layer110provided as the uppermost metal layer is electrically connected to the solder portion S connected to the first metal layer110provided as the lowermost metal layer, resulting in a short circuit. Conversely, in a case where the second metal layer120has a thickness greater than the predetermined range suggested above, the first metal layer110is formed to be excessively thin, which cannot secure a required thermal expansion coefficient and a required thermal conductivity of the spacer. The present invention is not limited to the spacer100structured such that the first metal layer110, the second metal layer120, and the first metal layer110are stacked in this order. As illustrated inFIG.4, many first metal layers110and second metal layers120are alternately stacked between the two first metal layers110provided as the outermost layers. For example, the metal layers are sequentially deposited on top of each other in this order: the first metal layer110, the second metal layer120, the first metal layer110, the second metal layer120, and the first metal layer110. Even in the instant case, the outermost layers of the spacer100are implemented with the first metal layers110. Next, with reference to a comparative example and an invention example, a solder joint on a spacer, according to the exemplary embodiment of the present invention, will be described, FIG.5AandFIG.5Bare views illustrating a comparative example and an invention example in each of which a spacer and a solder joint are formed. FIG.5Ais a view exemplarily illustrating a solder joint S on the spacer30in the related art in which the Cu plating layer33is provided, andFIG.5Bis a view exemplarily illustrating a solder joint S on the spacer100according to the exemplary embodiment of the present invention. As illustrated inFIG.5A, the Cu plating layer33covers the entire surface of the spacer30in the related art. Because of this, the solder joint S formed on the upper surface of the spacer30and the solder joint S formed on the lower surface of the spacer30undesirably extend up to a portion of the lateral surface of the spacer30. Thus, a short circuit between an upper portion and a lower portion of the spacer30occurs. In contrast, in the spacer100according to the exemplary embodiment of the present invention, since the metal material of which the second metal layer120is made has a poor solder wettability, as understood fromFIG.5B, the second metal layer120exposed on the lateral surface of the spacer100prevents the solder joint S formed on the first metal layer110provided as the uppermost metal layer from being connected to the solder joint S formed on the first metal110provided as the lowermost layer. For convenience in explanation and accurate definition in the appended claims, the terms “upper”, “lower”, “inner”, “outer”, “up”, “down”, “upwards”, “downwards”, “front”, “rear”, “back”, “inside”, “outside”, “inwardly”, “outwardly”, “internal”, “external”, “inner”, “outer”, “forwards”, and “backwards” are used to describe features of the exemplary embodiments with reference to the positions of such features as displayed in the figures. It will be further understood that the term “connect” or its derivatives refer both to direct and indirect connection. The foregoing descriptions of specific exemplary embodiments of the present invention have been presented for purposes of illustration and description. They are not intended to be exhaustive or to limit the present invention to the precise forms disclosed, and obviously many modifications and variations are possible in light of the above teachings. The exemplary embodiments were chosen and described in order to explain certain principles of the present invention and their practical application, to enable others skilled in the art to make and utilize various exemplary embodiments of the present invention, as well as various alternatives and modifications thereof. It is intended that the scope of the present invention be defined by the Claims appended hereto and their equivalents. | 10,659 |
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